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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Freescale Memory Controller kernel module
4 *
5 * Support Power-based SoCs including MPC85xx, MPC86xx, MPC83xx and
6 * ARM-based Layerscape SoCs including LS2xxx and LS1021A. Originally
7 * split out from mpc85xx_edac EDAC driver.
8 *
9 * Author: Dave Jiang <djiang@mvista.com>
10 *
11 * 2006-2007 (c) MontaVista Software, Inc.
12 */
13#ifndef _FSL_DDR_EDAC_H_
14#define _FSL_DDR_EDAC_H_
15
16#define fsl_mc_printk(mci, level, fmt, arg...) \
17 edac_mc_chipset_printk(mci, level, "FSL_DDR", fmt, ##arg)
18
19/*
20 * DRAM error defines
21 */
22
23/* DDR_SDRAM_CFG */
24#define FSL_MC_DDR_SDRAM_CFG 0x0110
25#define FSL_MC_CS_BNDS_0 0x0000
26#define FSL_MC_CS_BNDS_OFS 0x0008
27
28#define FSL_MC_DATA_ERR_INJECT_HI 0x0e00
29#define FSL_MC_DATA_ERR_INJECT_LO 0x0e04
30#define FSL_MC_ECC_ERR_INJECT 0x0e08
31#define FSL_MC_CAPTURE_DATA_HI 0x0e20
32#define FSL_MC_CAPTURE_DATA_LO 0x0e24
33#define FSL_MC_CAPTURE_ECC 0x0e28
34#define FSL_MC_ERR_DETECT 0x0e40
35#define FSL_MC_ERR_DISABLE 0x0e44
36#define FSL_MC_ERR_INT_EN 0x0e48
37#define FSL_MC_CAPTURE_ATRIBUTES 0x0e4c
38#define FSL_MC_CAPTURE_ADDRESS 0x0e50
39#define FSL_MC_CAPTURE_EXT_ADDRESS 0x0e54
40#define FSL_MC_ERR_SBE 0x0e58
41
42#define IMX9_MC_ERR_EN 0x1000
43#define IMX9_MC_DATA_ERR_INJECT_OFF 0x100
44
45#define DSC_MEM_EN 0x80000000
46#define DSC_ECC_EN 0x20000000
47#define DSC_RD_EN 0x10000000
48#define DSC_DBW_MASK 0x00180000
49#define DSC_DBW_32 0x00080000
50#define DSC_DBW_64 0x00000000
51
52#define ERR_ECC_EN 0x80000000
53#define ERR_INLINE_ECC 0x40000000
54
55#define DSC_SDTYPE_MASK 0x07000000
56#define DSC_X32_EN 0x00000020
57
58/* Err_Int_En */
59#define DDR_EIE_MSEE 0x1 /* memory select */
60#define DDR_EIE_SBEE 0x4 /* single-bit ECC error */
61#define DDR_EIE_MBEE 0x8 /* multi-bit ECC error */
62
63/* Err_Detect */
64#define DDR_EDE_MSE 0x1 /* memory select */
65#define DDR_EDE_SBE 0x4 /* single-bit ECC error */
66#define DDR_EDE_MBE 0x8 /* multi-bit ECC error */
67#define DDR_EDE_MME 0x80000000 /* multiple memory errors */
68
69/* Err_Disable */
70#define DDR_EDI_MSED 0x1 /* memory select disable */
71#define DDR_EDI_SBED 0x4 /* single-bit ECC error disable */
72#define DDR_EDI_MBED 0x8 /* multi-bit ECC error disable */
73
74#define TYPE_IMX9 0x1 /* MC used by iMX9 having registers changed */
75
76struct fsl_mc_pdata {
77 char *name;
78 int edac_idx;
79 void __iomem *mc_vbase;
80 void __iomem *inject_vbase;
81 int irq;
82 u32 orig_ddr_err_disable;
83 u32 orig_ddr_err_sbe;
84 bool little_endian;
85 unsigned long flag;
86};
87int fsl_mc_err_probe(struct platform_device *op);
88void fsl_mc_err_remove(struct platform_device *op);
89#endif
1/*
2 * Freescale Memory Controller kernel module
3 *
4 * Support Power-based SoCs including MPC85xx, MPC86xx, MPC83xx and
5 * ARM-based Layerscape SoCs including LS2xxx. Originally split
6 * out from mpc85xx_edac EDAC driver.
7 *
8 * Author: Dave Jiang <djiang@mvista.com>
9 *
10 * 2006-2007 (c) MontaVista Software, Inc. This file is licensed under
11 * the terms of the GNU General Public License version 2. This program
12 * is licensed "as is" without any warranty of any kind, whether express
13 * or implied.
14 *
15 */
16#ifndef _FSL_DDR_EDAC_H_
17#define _FSL_DDR_EDAC_H_
18
19#define fsl_mc_printk(mci, level, fmt, arg...) \
20 edac_mc_chipset_printk(mci, level, "FSL_DDR", fmt, ##arg)
21
22/*
23 * DRAM error defines
24 */
25
26/* DDR_SDRAM_CFG */
27#define FSL_MC_DDR_SDRAM_CFG 0x0110
28#define FSL_MC_CS_BNDS_0 0x0000
29#define FSL_MC_CS_BNDS_OFS 0x0008
30
31#define FSL_MC_DATA_ERR_INJECT_HI 0x0e00
32#define FSL_MC_DATA_ERR_INJECT_LO 0x0e04
33#define FSL_MC_ECC_ERR_INJECT 0x0e08
34#define FSL_MC_CAPTURE_DATA_HI 0x0e20
35#define FSL_MC_CAPTURE_DATA_LO 0x0e24
36#define FSL_MC_CAPTURE_ECC 0x0e28
37#define FSL_MC_ERR_DETECT 0x0e40
38#define FSL_MC_ERR_DISABLE 0x0e44
39#define FSL_MC_ERR_INT_EN 0x0e48
40#define FSL_MC_CAPTURE_ATRIBUTES 0x0e4c
41#define FSL_MC_CAPTURE_ADDRESS 0x0e50
42#define FSL_MC_CAPTURE_EXT_ADDRESS 0x0e54
43#define FSL_MC_ERR_SBE 0x0e58
44
45#define DSC_MEM_EN 0x80000000
46#define DSC_ECC_EN 0x20000000
47#define DSC_RD_EN 0x10000000
48#define DSC_DBW_MASK 0x00180000
49#define DSC_DBW_32 0x00080000
50#define DSC_DBW_64 0x00000000
51
52#define DSC_SDTYPE_MASK 0x07000000
53#define DSC_X32_EN 0x00000020
54
55/* Err_Int_En */
56#define DDR_EIE_MSEE 0x1 /* memory select */
57#define DDR_EIE_SBEE 0x4 /* single-bit ECC error */
58#define DDR_EIE_MBEE 0x8 /* multi-bit ECC error */
59
60/* Err_Detect */
61#define DDR_EDE_MSE 0x1 /* memory select */
62#define DDR_EDE_SBE 0x4 /* single-bit ECC error */
63#define DDR_EDE_MBE 0x8 /* multi-bit ECC error */
64#define DDR_EDE_MME 0x80000000 /* multiple memory errors */
65
66/* Err_Disable */
67#define DDR_EDI_MSED 0x1 /* memory select disable */
68#define DDR_EDI_SBED 0x4 /* single-bit ECC error disable */
69#define DDR_EDI_MBED 0x8 /* multi-bit ECC error disable */
70
71struct fsl_mc_pdata {
72 char *name;
73 int edac_idx;
74 void __iomem *mc_vbase;
75 int irq;
76};
77int fsl_mc_err_probe(struct platform_device *op);
78int fsl_mc_err_remove(struct platform_device *op);
79#endif