1#include "amd64_edac.h"
  2
  3static ssize_t amd64_inject_section_show(struct device *dev,
  4					 struct device_attribute *mattr,
  5					 char *buf)
  6{
  7	struct mem_ctl_info *mci = to_mci(dev);
  8	struct amd64_pvt *pvt = mci->pvt_info;
  9	return sprintf(buf, "0x%x\n", pvt->injection.section);
 10}
 11
 12/*
 13 * store error injection section value which refers to one of 4 16-byte sections
 14 * within a 64-byte cacheline
 15 *
 16 * range: 0..3
 17 */
 18static ssize_t amd64_inject_section_store(struct device *dev,
 19					  struct device_attribute *mattr,
 20					  const char *data, size_t count)
 21{
 22	struct mem_ctl_info *mci = to_mci(dev);
 23	struct amd64_pvt *pvt = mci->pvt_info;
 24	unsigned long value;
 25	int ret;
 26
 27	ret = kstrtoul(data, 10, &value);
 28	if (ret < 0)
 29		return ret;
 30
 31	if (value > 3) {
 32		amd64_warn("%s: invalid section 0x%lx\n", __func__, value);
 33		return -EINVAL;
 34	}
 35
 36	pvt->injection.section = (u32) value;
 37	return count;
 38}
 39
 40static ssize_t amd64_inject_word_show(struct device *dev,
 41					struct device_attribute *mattr,
 42					char *buf)
 43{
 44	struct mem_ctl_info *mci = to_mci(dev);
 45	struct amd64_pvt *pvt = mci->pvt_info;
 46	return sprintf(buf, "0x%x\n", pvt->injection.word);
 47}
 48
 49/*
 50 * store error injection word value which refers to one of 9 16-bit word of the
 51 * 16-byte (128-bit + ECC bits) section
 52 *
 53 * range: 0..8
 54 */
 55static ssize_t amd64_inject_word_store(struct device *dev,
 56				       struct device_attribute *mattr,
 57				       const char *data, size_t count)
 58{
 59	struct mem_ctl_info *mci = to_mci(dev);
 60	struct amd64_pvt *pvt = mci->pvt_info;
 61	unsigned long value;
 62	int ret;
 63
 64	ret = kstrtoul(data, 10, &value);
 65	if (ret < 0)
 66		return ret;
 67
 68	if (value > 8) {
 69		amd64_warn("%s: invalid word 0x%lx\n", __func__, value);
 70		return -EINVAL;
 71	}
 72
 73	pvt->injection.word = (u32) value;
 74	return count;
 75}
 76
 77static ssize_t amd64_inject_ecc_vector_show(struct device *dev,
 78					    struct device_attribute *mattr,
 79					    char *buf)
 80{
 81	struct mem_ctl_info *mci = to_mci(dev);
 82	struct amd64_pvt *pvt = mci->pvt_info;
 83	return sprintf(buf, "0x%x\n", pvt->injection.bit_map);
 84}
 85
 86/*
 87 * store 16 bit error injection vector which enables injecting errors to the
 88 * corresponding bit within the error injection word above. When used during a
 89 * DRAM ECC read, it holds the contents of the of the DRAM ECC bits.
 90 */
 91static ssize_t amd64_inject_ecc_vector_store(struct device *dev,
 92				       struct device_attribute *mattr,
 93				       const char *data, size_t count)
 94{
 95	struct mem_ctl_info *mci = to_mci(dev);
 96	struct amd64_pvt *pvt = mci->pvt_info;
 97	unsigned long value;
 98	int ret;
 99
100	ret = kstrtoul(data, 16, &value);
101	if (ret < 0)
102		return ret;
103
104	if (value & 0xFFFF0000) {
105		amd64_warn("%s: invalid EccVector: 0x%lx\n", __func__, value);
106		return -EINVAL;
107	}
108
109	pvt->injection.bit_map = (u32) value;
110	return count;
111}
112
113/*
114 * Do a DRAM ECC read. Assemble staged values in the pvt area, format into
115 * fields needed by the injection registers and read the NB Array Data Port.
116 */
117static ssize_t amd64_inject_read_store(struct device *dev,
118				       struct device_attribute *mattr,
119				       const char *data, size_t count)
120{
121	struct mem_ctl_info *mci = to_mci(dev);
122	struct amd64_pvt *pvt = mci->pvt_info;
123	unsigned long value;
124	u32 section, word_bits;
125	int ret;
126
127	ret = kstrtoul(data, 10, &value);
128	if (ret < 0)
129		return ret;
130
131	/* Form value to choose 16-byte section of cacheline */
132	section = F10_NB_ARRAY_DRAM | SET_NB_ARRAY_ADDR(pvt->injection.section);
133
134	amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_ADDR, section);
135
136	word_bits = SET_NB_DRAM_INJECTION_READ(pvt->injection);
137
138	/* Issue 'word' and 'bit' along with the READ request */
139	amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, word_bits);
140
141	edac_dbg(0, "section=0x%x word_bits=0x%x\n", section, word_bits);
142
143	return count;
144}
145
146/*
147 * Do a DRAM ECC write. Assemble staged values in the pvt area and format into
148 * fields needed by the injection registers.
149 */
150static ssize_t amd64_inject_write_store(struct device *dev,
151					struct device_attribute *mattr,
152					const char *data, size_t count)
153{
154	struct mem_ctl_info *mci = to_mci(dev);
155	struct amd64_pvt *pvt = mci->pvt_info;
156	u32 section, word_bits, tmp;
157	unsigned long value;
158	int ret;
159
160	ret = kstrtoul(data, 10, &value);
161	if (ret < 0)
162		return ret;
163
164	/* Form value to choose 16-byte section of cacheline */
165	section = F10_NB_ARRAY_DRAM | SET_NB_ARRAY_ADDR(pvt->injection.section);
166
167	amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_ADDR, section);
168
169	word_bits = SET_NB_DRAM_INJECTION_WRITE(pvt->injection);
170
171	pr_notice_once("Don't forget to decrease MCE polling interval in\n"
172			"/sys/bus/machinecheck/devices/machinecheck<CPUNUM>/check_interval\n"
173			"so that you can get the error report faster.\n");
174
175	on_each_cpu(disable_caches, NULL, 1);
176
177	/* Issue 'word' and 'bit' along with the READ request */
178	amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, word_bits);
179
180 retry:
181	/* wait until injection happens */
182	amd64_read_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, &tmp);
183	if (tmp & F10_NB_ARR_ECC_WR_REQ) {
184		cpu_relax();
185		goto retry;
186	}
187
188	on_each_cpu(enable_caches, NULL, 1);
189
190	edac_dbg(0, "section=0x%x word_bits=0x%x\n", section, word_bits);
191
192	return count;
193}
194
195/*
196 * update NUM_INJ_ATTRS in case you add new members
197 */
198
199static DEVICE_ATTR(inject_section, S_IRUGO | S_IWUSR,
200		   amd64_inject_section_show, amd64_inject_section_store);
201static DEVICE_ATTR(inject_word, S_IRUGO | S_IWUSR,
202		   amd64_inject_word_show, amd64_inject_word_store);
203static DEVICE_ATTR(inject_ecc_vector, S_IRUGO | S_IWUSR,
204		   amd64_inject_ecc_vector_show, amd64_inject_ecc_vector_store);
205static DEVICE_ATTR(inject_write, S_IWUSR,
206		   NULL, amd64_inject_write_store);
207static DEVICE_ATTR(inject_read,  S_IWUSR,
208		   NULL, amd64_inject_read_store);
209
210static struct attribute *amd64_edac_inj_attrs[] = {
211	&dev_attr_inject_section.attr,
212	&dev_attr_inject_word.attr,
213	&dev_attr_inject_ecc_vector.attr,
214	&dev_attr_inject_write.attr,
215	&dev_attr_inject_read.attr,
216	NULL
217};
218
219static umode_t amd64_edac_inj_is_visible(struct kobject *kobj,
220					 struct attribute *attr, int idx)
221{
222	struct device *dev = kobj_to_dev(kobj);
223	struct mem_ctl_info *mci = container_of(dev, struct mem_ctl_info, dev);
224	struct amd64_pvt *pvt = mci->pvt_info;
225
226	if (pvt->fam < 0x10)
227		return 0;
228	return attr->mode;
229}
230
231const struct attribute_group amd64_edac_inj_group = {
232	.attrs = amd64_edac_inj_attrs,
233	.is_visible = amd64_edac_inj_is_visible,
234};