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1// SPDX-License-Identifier: GPL-2.0
2#include <dt-bindings/clock/tegra124-car.h>
3#include <dt-bindings/gpio/tegra-gpio.h>
4#include <dt-bindings/memory/tegra124-mc.h>
5#include <dt-bindings/pinctrl/pinctrl-tegra.h>
6#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
7#include <dt-bindings/interrupt-controller/arm-gic.h>
8#include <dt-bindings/thermal/tegra124-soctherm.h>
9#include <dt-bindings/soc/tegra-pmc.h>
10
11#include "tegra132-peripherals-opp.dtsi"
12
13/ {
14 compatible = "nvidia,tegra132", "nvidia,tegra124";
15 interrupt-parent = <&lic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
18
19 pcie@1003000 {
20 compatible = "nvidia,tegra124-pcie";
21 device_type = "pci";
22 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
23 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
24 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */
25 reg-names = "pads", "afi", "cs";
26 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
27 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
28 interrupt-names = "intr", "msi";
29
30 #interrupt-cells = <1>;
31 interrupt-map-mask = <0 0 0 0>;
32 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
33
34 bus-range = <0x00 0xff>;
35 #address-cells = <3>;
36 #size-cells = <2>;
37
38 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */
39 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */
40 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
41 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */
42 <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
43
44 clocks = <&tegra_car TEGRA124_CLK_PCIE>,
45 <&tegra_car TEGRA124_CLK_AFI>,
46 <&tegra_car TEGRA124_CLK_PLL_E>,
47 <&tegra_car TEGRA124_CLK_CML0>;
48 clock-names = "pex", "afi", "pll_e", "cml";
49 resets = <&tegra_car 70>,
50 <&tegra_car 72>,
51 <&tegra_car 74>;
52 reset-names = "pex", "afi", "pcie_x";
53 status = "disabled";
54
55 pci@1,0 {
56 device_type = "pci";
57 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
58 reg = <0x000800 0 0 0 0>;
59 bus-range = <0x00 0xff>;
60 status = "disabled";
61
62 #address-cells = <3>;
63 #size-cells = <2>;
64 ranges;
65
66 nvidia,num-lanes = <2>;
67 };
68
69 pci@2,0 {
70 device_type = "pci";
71 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
72 reg = <0x001000 0 0 0 0>;
73 bus-range = <0x00 0xff>;
74 status = "disabled";
75
76 #address-cells = <3>;
77 #size-cells = <2>;
78 ranges;
79
80 nvidia,num-lanes = <1>;
81 };
82 };
83
84 host1x@50000000 {
85 compatible = "nvidia,tegra132-host1x",
86 "nvidia,tegra124-host1x";
87 reg = <0x0 0x50000000 0x0 0x00034000>;
88 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
89 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
90 interrupt-names = "syncpt", "host1x";
91 clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
92 clock-names = "host1x";
93 resets = <&tegra_car 28>;
94 reset-names = "host1x";
95
96 iommus = <&mc TEGRA_SWGROUP_HC>;
97
98 #address-cells = <2>;
99 #size-cells = <2>;
100
101 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;
102
103 dc@54200000 {
104 compatible = "nvidia,tegra124-dc";
105 reg = <0x0 0x54200000 0x0 0x00040000>;
106 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
107 clocks = <&tegra_car TEGRA124_CLK_DISP1>;
108 clock-names = "dc";
109 resets = <&tegra_car 27>;
110 reset-names = "dc";
111
112 iommus = <&mc TEGRA_SWGROUP_DC>;
113
114 nvidia,head = <0>;
115 };
116
117 dc@54240000 {
118 compatible = "nvidia,tegra124-dc";
119 reg = <0x0 0x54240000 0x0 0x00040000>;
120 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
121 clocks = <&tegra_car TEGRA124_CLK_DISP2>;
122 clock-names = "dc";
123 resets = <&tegra_car 26>;
124 reset-names = "dc";
125
126 iommus = <&mc TEGRA_SWGROUP_DCB>;
127
128 nvidia,head = <1>;
129 };
130
131 hdmi@54280000 {
132 compatible = "nvidia,tegra124-hdmi";
133 reg = <0x0 0x54280000 0x0 0x00040000>;
134 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
135 clocks = <&tegra_car TEGRA124_CLK_HDMI>,
136 <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>;
137 clock-names = "hdmi", "parent";
138 resets = <&tegra_car 51>;
139 reset-names = "hdmi";
140 status = "disabled";
141 };
142
143 sor@54540000 {
144 compatible = "nvidia,tegra124-sor";
145 reg = <0x0 0x54540000 0x0 0x00040000>;
146 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
147 clocks = <&tegra_car TEGRA124_CLK_SOR0>,
148 <&tegra_car TEGRA124_CLK_SOR0_OUT>,
149 <&tegra_car TEGRA124_CLK_PLL_D_OUT0>,
150 <&tegra_car TEGRA124_CLK_PLL_DP>,
151 <&tegra_car TEGRA124_CLK_CLK_M>;
152 clock-names = "sor", "out", "parent", "dp", "safe";
153 resets = <&tegra_car 182>;
154 reset-names = "sor";
155 status = "disabled";
156 };
157
158 dpaux: dpaux@545c0000 {
159 compatible = "nvidia,tegra124-dpaux";
160 reg = <0x0 0x545c0000 0x0 0x00040000>;
161 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
162 clocks = <&tegra_car TEGRA124_CLK_DPAUX>,
163 <&tegra_car TEGRA124_CLK_PLL_DP>;
164 clock-names = "dpaux", "parent";
165 resets = <&tegra_car 181>;
166 reset-names = "dpaux";
167 status = "disabled";
168
169 i2c-bus {
170 #address-cells = <1>;
171 #size-cells = <0>;
172 };
173 };
174 };
175
176 gic: interrupt-controller@50041000 {
177 compatible = "arm,cortex-a15-gic";
178 #interrupt-cells = <3>;
179 interrupt-controller;
180 reg = <0x0 0x50041000 0x0 0x1000>,
181 <0x0 0x50042000 0x0 0x2000>,
182 <0x0 0x50044000 0x0 0x2000>,
183 <0x0 0x50046000 0x0 0x2000>;
184 interrupts = <GIC_PPI 9
185 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
186 interrupt-parent = <&gic>;
187 };
188
189 gpu@57000000 {
190 compatible = "nvidia,gk20a";
191 reg = <0x0 0x57000000 0x0 0x01000000>,
192 <0x0 0x58000000 0x0 0x01000000>;
193 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
194 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
195 interrupt-names = "stall", "nonstall";
196 clocks = <&tegra_car TEGRA124_CLK_GPU>,
197 <&tegra_car TEGRA124_CLK_PLL_P_OUT5>;
198 clock-names = "gpu", "pwr";
199 resets = <&tegra_car 184>;
200 reset-names = "gpu";
201 status = "disabled";
202 };
203
204 lic: interrupt-controller@60004000 {
205 compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr";
206 reg = <0x0 0x60004000 0x0 0x100>,
207 <0x0 0x60004100 0x0 0x100>,
208 <0x0 0x60004200 0x0 0x100>,
209 <0x0 0x60004300 0x0 0x100>,
210 <0x0 0x60004400 0x0 0x100>;
211 interrupt-controller;
212 #interrupt-cells = <3>;
213 interrupt-parent = <&gic>;
214 };
215
216 timer@60005000 {
217 compatible = "nvidia,tegra124-timer", "nvidia,tegra30-timer";
218 reg = <0x0 0x60005000 0x0 0x400>;
219 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
220 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
221 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
222 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
223 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
224 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
225 clocks = <&tegra_car TEGRA124_CLK_TIMER>;
226 clock-names = "timer";
227 };
228
229 tegra_car: clock@60006000 {
230 compatible = "nvidia,tegra132-car";
231 reg = <0x0 0x60006000 0x0 0x1000>;
232 #clock-cells = <1>;
233 #reset-cells = <1>;
234 nvidia,external-memory-controller = <&emc>;
235 };
236
237 flow-controller@60007000 {
238 compatible = "nvidia,tegra132-flowctrl", "nvidia,tegra124-flowctrl";
239 reg = <0x0 0x60007000 0x0 0x1000>;
240 };
241
242 actmon@6000c800 {
243 compatible = "nvidia,tegra124-actmon";
244 reg = <0x0 0x6000c800 0x0 0x400>;
245 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
246 clocks = <&tegra_car TEGRA124_CLK_ACTMON>,
247 <&tegra_car TEGRA124_CLK_EMC>;
248 clock-names = "actmon", "emc";
249 resets = <&tegra_car 119>;
250 reset-names = "actmon";
251 operating-points-v2 = <&emc_bw_dfs_opp_table>;
252 interconnects = <&mc TEGRA124_MC_MPCORER &emc>;
253 interconnect-names = "cpu-read";
254 #cooling-cells = <2>;
255 };
256
257 gpio: gpio@6000d000 {
258 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
259 reg = <0x0 0x6000d000 0x0 0x1000>;
260 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
261 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
262 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
263 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
264 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
265 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
266 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
267 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
268 #gpio-cells = <2>;
269 gpio-controller;
270 #interrupt-cells = <2>;
271 interrupt-controller;
272 };
273
274 apbdma: dma@60020000 {
275 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
276 reg = <0x0 0x60020000 0x0 0x1400>;
277 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
278 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
279 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
280 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
281 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
282 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
283 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
284 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
285 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
286 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
287 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
288 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
289 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
290 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
291 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
292 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
293 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
294 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
295 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
296 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
297 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
298 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
299 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
300 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
301 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
302 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
303 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
304 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
305 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
306 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
307 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
308 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
309 clocks = <&tegra_car TEGRA124_CLK_APBDMA>;
310 clock-names = "dma";
311 resets = <&tegra_car 34>;
312 reset-names = "dma";
313 #dma-cells = <1>;
314 };
315
316 apbmisc@70000800 {
317 compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc";
318 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
319 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */
320 };
321
322 pinmux: pinmux@70000868 {
323 compatible = "nvidia,tegra124-pinmux";
324 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
325 <0x0 0x70003000 0x0 0x434>, /* Mux registers */
326 <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */
327 };
328
329 /*
330 * There are two serial driver i.e. 8250 based simple serial
331 * driver and APB DMA based serial driver for higher baudrate
332 * and performance. To enable the 8250 based driver, the compatible
333 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
334 * the APB DMA based serial driver, the compatible is
335 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
336 */
337 uarta: serial@70006000 {
338 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
339 reg = <0x0 0x70006000 0x0 0x40>;
340 reg-shift = <2>;
341 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
342 clocks = <&tegra_car TEGRA124_CLK_UARTA>;
343 resets = <&tegra_car 6>;
344 dmas = <&apbdma 8>, <&apbdma 8>;
345 dma-names = "rx", "tx";
346 status = "disabled";
347 };
348
349 uartb: serial@70006040 {
350 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
351 reg = <0x0 0x70006040 0x0 0x40>;
352 reg-shift = <2>;
353 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
354 clocks = <&tegra_car TEGRA124_CLK_UARTB>;
355 resets = <&tegra_car 7>;
356 dmas = <&apbdma 9>, <&apbdma 9>;
357 dma-names = "rx", "tx";
358 status = "disabled";
359 };
360
361 uartc: serial@70006200 {
362 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
363 reg = <0x0 0x70006200 0x0 0x40>;
364 reg-shift = <2>;
365 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
366 clocks = <&tegra_car TEGRA124_CLK_UARTC>;
367 resets = <&tegra_car 55>;
368 dmas = <&apbdma 10>, <&apbdma 10>;
369 dma-names = "rx", "tx";
370 status = "disabled";
371 };
372
373 uartd: serial@70006300 {
374 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
375 reg = <0x0 0x70006300 0x0 0x40>;
376 reg-shift = <2>;
377 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
378 clocks = <&tegra_car TEGRA124_CLK_UARTD>;
379 resets = <&tegra_car 65>;
380 dmas = <&apbdma 19>, <&apbdma 19>;
381 dma-names = "rx", "tx";
382 status = "disabled";
383 };
384
385 pwm: pwm@7000a000 {
386 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
387 reg = <0x0 0x7000a000 0x0 0x100>;
388 #pwm-cells = <2>;
389 clocks = <&tegra_car TEGRA124_CLK_PWM>;
390 resets = <&tegra_car 17>;
391 reset-names = "pwm";
392 status = "disabled";
393 };
394
395 i2c@7000c000 {
396 compatible = "nvidia,tegra124-i2c";
397 reg = <0x0 0x7000c000 0x0 0x100>;
398 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
399 #address-cells = <1>;
400 #size-cells = <0>;
401 clocks = <&tegra_car TEGRA124_CLK_I2C1>;
402 clock-names = "div-clk";
403 resets = <&tegra_car 12>;
404 reset-names = "i2c";
405 dmas = <&apbdma 21>, <&apbdma 21>;
406 dma-names = "rx", "tx";
407 status = "disabled";
408 };
409
410 i2c@7000c400 {
411 compatible = "nvidia,tegra124-i2c";
412 reg = <0x0 0x7000c400 0x0 0x100>;
413 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
414 #address-cells = <1>;
415 #size-cells = <0>;
416 clocks = <&tegra_car TEGRA124_CLK_I2C2>;
417 clock-names = "div-clk";
418 resets = <&tegra_car 54>;
419 reset-names = "i2c";
420 dmas = <&apbdma 22>, <&apbdma 22>;
421 dma-names = "rx", "tx";
422 status = "disabled";
423 };
424
425 i2c@7000c500 {
426 compatible = "nvidia,tegra124-i2c";
427 reg = <0x0 0x7000c500 0x0 0x100>;
428 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
429 #address-cells = <1>;
430 #size-cells = <0>;
431 clocks = <&tegra_car TEGRA124_CLK_I2C3>;
432 clock-names = "div-clk";
433 resets = <&tegra_car 67>;
434 reset-names = "i2c";
435 dmas = <&apbdma 23>, <&apbdma 23>;
436 dma-names = "rx", "tx";
437 status = "disabled";
438 };
439
440 i2c@7000c700 {
441 compatible = "nvidia,tegra124-i2c";
442 reg = <0x0 0x7000c700 0x0 0x100>;
443 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
444 #address-cells = <1>;
445 #size-cells = <0>;
446 clocks = <&tegra_car TEGRA124_CLK_I2C4>;
447 clock-names = "div-clk";
448 resets = <&tegra_car 103>;
449 reset-names = "i2c";
450 dmas = <&apbdma 26>, <&apbdma 26>;
451 dma-names = "rx", "tx";
452 status = "disabled";
453 };
454
455 i2c@7000d000 {
456 compatible = "nvidia,tegra124-i2c";
457 reg = <0x0 0x7000d000 0x0 0x100>;
458 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
459 #address-cells = <1>;
460 #size-cells = <0>;
461 clocks = <&tegra_car TEGRA124_CLK_I2C5>;
462 clock-names = "div-clk";
463 resets = <&tegra_car 47>;
464 reset-names = "i2c";
465 dmas = <&apbdma 24>, <&apbdma 24>;
466 dma-names = "rx", "tx";
467 status = "disabled";
468 };
469
470 i2c@7000d100 {
471 compatible = "nvidia,tegra124-i2c";
472 reg = <0x0 0x7000d100 0x0 0x100>;
473 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
474 #address-cells = <1>;
475 #size-cells = <0>;
476 clocks = <&tegra_car TEGRA124_CLK_I2C6>;
477 clock-names = "div-clk";
478 resets = <&tegra_car 166>;
479 reset-names = "i2c";
480 dmas = <&apbdma 30>, <&apbdma 30>;
481 dma-names = "rx", "tx";
482 status = "disabled";
483 };
484
485 spi@7000d400 {
486 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
487 reg = <0x0 0x7000d400 0x0 0x200>;
488 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
489 #address-cells = <1>;
490 #size-cells = <0>;
491 clocks = <&tegra_car TEGRA124_CLK_SBC1>;
492 clock-names = "spi";
493 resets = <&tegra_car 41>;
494 reset-names = "spi";
495 dmas = <&apbdma 15>, <&apbdma 15>;
496 dma-names = "rx", "tx";
497 status = "disabled";
498 };
499
500 spi@7000d600 {
501 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
502 reg = <0x0 0x7000d600 0x0 0x200>;
503 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
504 #address-cells = <1>;
505 #size-cells = <0>;
506 clocks = <&tegra_car TEGRA124_CLK_SBC2>;
507 clock-names = "spi";
508 resets = <&tegra_car 44>;
509 reset-names = "spi";
510 dmas = <&apbdma 16>, <&apbdma 16>;
511 dma-names = "rx", "tx";
512 status = "disabled";
513 };
514
515 spi@7000d800 {
516 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
517 reg = <0x0 0x7000d800 0x0 0x200>;
518 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
519 #address-cells = <1>;
520 #size-cells = <0>;
521 clocks = <&tegra_car TEGRA124_CLK_SBC3>;
522 clock-names = "spi";
523 resets = <&tegra_car 46>;
524 reset-names = "spi";
525 dmas = <&apbdma 17>, <&apbdma 17>;
526 dma-names = "rx", "tx";
527 status = "disabled";
528 };
529
530 spi@7000da00 {
531 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
532 reg = <0x0 0x7000da00 0x0 0x200>;
533 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
534 #address-cells = <1>;
535 #size-cells = <0>;
536 clocks = <&tegra_car TEGRA124_CLK_SBC4>;
537 clock-names = "spi";
538 resets = <&tegra_car 68>;
539 reset-names = "spi";
540 dmas = <&apbdma 18>, <&apbdma 18>;
541 dma-names = "rx", "tx";
542 status = "disabled";
543 };
544
545 spi@7000dc00 {
546 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
547 reg = <0x0 0x7000dc00 0x0 0x200>;
548 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
549 #address-cells = <1>;
550 #size-cells = <0>;
551 clocks = <&tegra_car TEGRA124_CLK_SBC5>;
552 clock-names = "spi";
553 resets = <&tegra_car 104>;
554 reset-names = "spi";
555 dmas = <&apbdma 27>, <&apbdma 27>;
556 dma-names = "rx", "tx";
557 status = "disabled";
558 };
559
560 spi@7000de00 {
561 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
562 reg = <0x0 0x7000de00 0x0 0x200>;
563 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
564 #address-cells = <1>;
565 #size-cells = <0>;
566 clocks = <&tegra_car TEGRA124_CLK_SBC6>;
567 clock-names = "spi";
568 resets = <&tegra_car 105>;
569 reset-names = "spi";
570 dmas = <&apbdma 28>, <&apbdma 28>;
571 dma-names = "rx", "tx";
572 status = "disabled";
573 };
574
575 tegra_rtc: rtc@7000e000 {
576 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
577 reg = <0x0 0x7000e000 0x0 0x100>;
578 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
579 clocks = <&tegra_car TEGRA124_CLK_RTC>;
580 clock-names = "rtc";
581 };
582
583 tegra_pmc: pmc@7000e400 {
584 compatible = "nvidia,tegra124-pmc";
585 reg = <0x0 0x7000e400 0x0 0x400>;
586 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
587 clock-names = "pclk", "clk32k_in";
588 #clock-cells = <1>;
589 };
590
591 fuse@7000f800 {
592 compatible = "nvidia,tegra124-efuse";
593 reg = <0x0 0x7000f800 0x0 0x400>;
594 clocks = <&tegra_car TEGRA124_CLK_FUSE>;
595 clock-names = "fuse";
596 resets = <&tegra_car 39>;
597 reset-names = "fuse";
598 };
599
600 mc: memory-controller@70019000 {
601 compatible = "nvidia,tegra132-mc";
602 reg = <0x0 0x70019000 0x0 0x1000>;
603 clocks = <&tegra_car TEGRA124_CLK_MC>;
604 clock-names = "mc";
605
606 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
607
608 #iommu-cells = <1>;
609 #reset-cells = <1>;
610 #interconnect-cells = <1>;
611 };
612
613 emc: external-memory-controller@7001b000 {
614 compatible = "nvidia,tegra132-emc", "nvidia,tegra124-emc";
615 reg = <0x0 0x7001b000 0x0 0x1000>;
616 clocks = <&tegra_car TEGRA124_CLK_EMC>;
617 clock-names = "emc";
618
619 nvidia,memory-controller = <&mc>;
620 operating-points-v2 = <&emc_icc_dvfs_opp_table>;
621
622 #interconnect-cells = <0>;
623 };
624
625 sata@70020000 {
626 compatible = "nvidia,tegra124-ahci";
627 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
628 <0x0 0x70020000 0x0 0x7000>; /* SATA */
629 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
630 clocks = <&tegra_car TEGRA124_CLK_SATA>,
631 <&tegra_car TEGRA124_CLK_SATA_OOB>;
632 clock-names = "sata", "sata-oob";
633 resets = <&tegra_car 124>,
634 <&tegra_car 129>,
635 <&tegra_car 123>;
636 reset-names = "sata", "sata-cold", "sata-oob";
637 status = "disabled";
638 };
639
640 hda@70030000 {
641 compatible = "nvidia,tegra132-hda", "nvidia,tegra124-hda",
642 "nvidia,tegra30-hda";
643 reg = <0x0 0x70030000 0x0 0x10000>;
644 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
645 clocks = <&tegra_car TEGRA124_CLK_HDA>,
646 <&tegra_car TEGRA124_CLK_HDA2HDMI>,
647 <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>;
648 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
649 resets = <&tegra_car 125>, /* hda */
650 <&tegra_car 128>, /* hda2hdmi */
651 <&tegra_car 111>; /* hda2codec_2x */
652 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
653 status = "disabled";
654 };
655
656 usb@70090000 {
657 compatible = "nvidia,tegra132-xusb", "nvidia,tegra124-xusb";
658 reg = <0x0 0x70090000 0x0 0x8000>,
659 <0x0 0x70098000 0x0 0x1000>,
660 <0x0 0x70099000 0x0 0x1000>;
661 reg-names = "hcd", "fpci", "ipfs";
662
663 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
664 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
665
666 clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>,
667 <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>,
668 <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>,
669 <&tegra_car TEGRA124_CLK_XUSB_SS>,
670 <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>,
671 <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>,
672 <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>,
673 <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>,
674 <&tegra_car TEGRA124_CLK_PLL_U_480M>,
675 <&tegra_car TEGRA124_CLK_CLK_M>,
676 <&tegra_car TEGRA124_CLK_PLL_E>;
677 clock-names = "xusb_host", "xusb_host_src",
678 "xusb_falcon_src", "xusb_ss",
679 "xusb_ss_div2", "xusb_ss_src",
680 "xusb_hs_src", "xusb_fs_src",
681 "pll_u_480m", "clk_m", "pll_e";
682 resets = <&tegra_car 89>, <&tegra_car 156>,
683 <&tegra_car 143>;
684 reset-names = "xusb_host", "xusb_ss", "xusb_src";
685
686 nvidia,xusb-padctl = <&padctl>;
687
688 status = "disabled";
689 };
690
691 padctl: padctl@7009f000 {
692 compatible = "nvidia,tegra132-xusb-padctl",
693 "nvidia,tegra124-xusb-padctl";
694 reg = <0x0 0x7009f000 0x0 0x1000>;
695 resets = <&tegra_car 142>;
696 reset-names = "padctl";
697
698 pads {
699 usb2 {
700 status = "disabled";
701
702 lanes {
703 usb2-0 {
704 status = "disabled";
705 #phy-cells = <0>;
706 };
707
708 usb2-1 {
709 status = "disabled";
710 #phy-cells = <0>;
711 };
712
713 usb2-2 {
714 status = "disabled";
715 #phy-cells = <0>;
716 };
717 };
718 };
719
720 ulpi {
721 status = "disabled";
722
723 lanes {
724 ulpi-0 {
725 status = "disabled";
726 #phy-cells = <0>;
727 };
728 };
729 };
730
731 hsic {
732 status = "disabled";
733
734 lanes {
735 hsic-0 {
736 status = "disabled";
737 #phy-cells = <0>;
738 };
739
740 hsic-1 {
741 status = "disabled";
742 #phy-cells = <0>;
743 };
744 };
745 };
746
747 pcie {
748 status = "disabled";
749
750 lanes {
751 pcie-0 {
752 status = "disabled";
753 #phy-cells = <0>;
754 };
755
756 pcie-1 {
757 status = "disabled";
758 #phy-cells = <0>;
759 };
760
761 pcie-2 {
762 status = "disabled";
763 #phy-cells = <0>;
764 };
765
766 pcie-3 {
767 status = "disabled";
768 #phy-cells = <0>;
769 };
770
771 pcie-4 {
772 status = "disabled";
773 #phy-cells = <0>;
774 };
775 };
776 };
777
778 sata {
779 status = "disabled";
780
781 lanes {
782 sata-0 {
783 status = "disabled";
784 #phy-cells = <0>;
785 };
786 };
787 };
788 };
789
790 ports {
791 usb2-0 {
792 status = "disabled";
793 };
794
795 usb2-1 {
796 status = "disabled";
797 };
798
799 usb2-2 {
800 status = "disabled";
801 };
802
803 hsic-0 {
804 status = "disabled";
805 };
806
807 hsic-1 {
808 status = "disabled";
809 };
810
811 usb3-0 {
812 status = "disabled";
813 };
814
815 usb3-1 {
816 status = "disabled";
817 };
818 };
819 };
820
821 mmc@700b0000 {
822 compatible = "nvidia,tegra124-sdhci";
823 reg = <0x0 0x700b0000 0x0 0x200>;
824 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
825 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
826 clock-names = "sdhci";
827 resets = <&tegra_car 14>;
828 reset-names = "sdhci";
829 status = "disabled";
830 };
831
832 mmc@700b0200 {
833 compatible = "nvidia,tegra124-sdhci";
834 reg = <0x0 0x700b0200 0x0 0x200>;
835 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
836 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
837 clock-names = "sdhci";
838 resets = <&tegra_car 9>;
839 reset-names = "sdhci";
840 status = "disabled";
841 };
842
843 mmc@700b0400 {
844 compatible = "nvidia,tegra124-sdhci";
845 reg = <0x0 0x700b0400 0x0 0x200>;
846 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
847 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
848 clock-names = "sdhci";
849 resets = <&tegra_car 69>;
850 reset-names = "sdhci";
851 status = "disabled";
852 };
853
854 mmc@700b0600 {
855 compatible = "nvidia,tegra124-sdhci";
856 reg = <0x0 0x700b0600 0x0 0x200>;
857 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
858 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
859 clock-names = "sdhci";
860 resets = <&tegra_car 15>;
861 reset-names = "sdhci";
862 status = "disabled";
863 };
864
865 soctherm: thermal-sensor@700e2000 {
866 compatible = "nvidia,tegra132-soctherm";
867 reg = <0x0 0x700e2000 0x0 0x600>, /* 0: SOC_THERM reg_base */
868 <0x0 0x70040000 0x0 0x200>; /* 2: CCROC reg_base */
869 reg-names = "soctherm-reg", "ccroc-reg";
870 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
871 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
872 interrupt-names = "thermal", "edp";
873 clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
874 <&tegra_car TEGRA124_CLK_SOC_THERM>;
875 clock-names = "tsensor", "soctherm";
876 resets = <&tegra_car 78>;
877 reset-names = "soctherm";
878 #thermal-sensor-cells = <1>;
879
880 throttle-cfgs {
881 throttle_heavy: heavy {
882 nvidia,priority = <100>;
883 nvidia,cpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>;
884
885 #cooling-cells = <2>;
886 };
887 };
888 };
889
890 ahub@70300000 {
891 compatible = "nvidia,tegra124-ahub";
892 reg = <0x0 0x70300000 0x0 0x200>,
893 <0x0 0x70300800 0x0 0x800>,
894 <0x0 0x70300200 0x0 0x600>;
895 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
896 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
897 <&tegra_car TEGRA124_CLK_APBIF>;
898 clock-names = "d_audio", "apbif";
899 resets = <&tegra_car 106>, /* d_audio */
900 <&tegra_car 107>, /* apbif */
901 <&tegra_car 30>, /* i2s0 */
902 <&tegra_car 11>, /* i2s1 */
903 <&tegra_car 18>, /* i2s2 */
904 <&tegra_car 101>, /* i2s3 */
905 <&tegra_car 102>, /* i2s4 */
906 <&tegra_car 108>, /* dam0 */
907 <&tegra_car 109>, /* dam1 */
908 <&tegra_car 110>, /* dam2 */
909 <&tegra_car 10>, /* spdif */
910 <&tegra_car 153>, /* amx */
911 <&tegra_car 185>, /* amx1 */
912 <&tegra_car 154>, /* adx */
913 <&tegra_car 180>, /* adx1 */
914 <&tegra_car 186>, /* afc0 */
915 <&tegra_car 187>, /* afc1 */
916 <&tegra_car 188>, /* afc2 */
917 <&tegra_car 189>, /* afc3 */
918 <&tegra_car 190>, /* afc4 */
919 <&tegra_car 191>; /* afc5 */
920 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
921 "i2s3", "i2s4", "dam0", "dam1", "dam2",
922 "spdif", "amx", "amx1", "adx", "adx1",
923 "afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
924 dmas = <&apbdma 1>, <&apbdma 1>,
925 <&apbdma 2>, <&apbdma 2>,
926 <&apbdma 3>, <&apbdma 3>,
927 <&apbdma 4>, <&apbdma 4>,
928 <&apbdma 6>, <&apbdma 6>,
929 <&apbdma 7>, <&apbdma 7>,
930 <&apbdma 12>, <&apbdma 12>,
931 <&apbdma 13>, <&apbdma 13>,
932 <&apbdma 14>, <&apbdma 14>,
933 <&apbdma 29>, <&apbdma 29>;
934 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
935 "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
936 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
937 "rx9", "tx9";
938 ranges;
939 #address-cells = <2>;
940 #size-cells = <2>;
941
942 tegra_i2s0: i2s@70301000 {
943 compatible = "nvidia,tegra124-i2s";
944 reg = <0x0 0x70301000 0x0 0x100>;
945 nvidia,ahub-cif-ids = <4 4>;
946 clocks = <&tegra_car TEGRA124_CLK_I2S0>;
947 clock-names = "i2s";
948 resets = <&tegra_car 30>;
949 reset-names = "i2s";
950 status = "disabled";
951 };
952
953 tegra_i2s1: i2s@70301100 {
954 compatible = "nvidia,tegra124-i2s";
955 reg = <0x0 0x70301100 0x0 0x100>;
956 nvidia,ahub-cif-ids = <5 5>;
957 clocks = <&tegra_car TEGRA124_CLK_I2S1>;
958 clock-names = "i2s";
959 resets = <&tegra_car 11>;
960 reset-names = "i2s";
961 status = "disabled";
962 };
963
964 tegra_i2s2: i2s@70301200 {
965 compatible = "nvidia,tegra124-i2s";
966 reg = <0x0 0x70301200 0x0 0x100>;
967 nvidia,ahub-cif-ids = <6 6>;
968 clocks = <&tegra_car TEGRA124_CLK_I2S2>;
969 clock-names = "i2s";
970 resets = <&tegra_car 18>;
971 reset-names = "i2s";
972 status = "disabled";
973 };
974
975 tegra_i2s3: i2s@70301300 {
976 compatible = "nvidia,tegra124-i2s";
977 reg = <0x0 0x70301300 0x0 0x100>;
978 nvidia,ahub-cif-ids = <7 7>;
979 clocks = <&tegra_car TEGRA124_CLK_I2S3>;
980 clock-names = "i2s";
981 resets = <&tegra_car 101>;
982 reset-names = "i2s";
983 status = "disabled";
984 };
985
986 tegra_i2s4: i2s@70301400 {
987 compatible = "nvidia,tegra124-i2s";
988 reg = <0x0 0x70301400 0x0 0x100>;
989 nvidia,ahub-cif-ids = <8 8>;
990 clocks = <&tegra_car TEGRA124_CLK_I2S4>;
991 clock-names = "i2s";
992 resets = <&tegra_car 102>;
993 reset-names = "i2s";
994 status = "disabled";
995 };
996 };
997
998 usb@7d000000 {
999 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
1000 reg = <0x0 0x7d000000 0x0 0x4000>;
1001 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1002 phy_type = "utmi";
1003 clocks = <&tegra_car TEGRA124_CLK_USBD>;
1004 clock-names = "usb";
1005 resets = <&tegra_car 22>;
1006 reset-names = "usb";
1007 nvidia,phy = <&phy1>;
1008 status = "disabled";
1009 };
1010
1011 phy1: usb-phy@7d000000 {
1012 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1013 reg = <0x0 0x7d000000 0x0 0x4000>,
1014 <0x0 0x7d000000 0x0 0x4000>;
1015 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1016 phy_type = "utmi";
1017 clocks = <&tegra_car TEGRA124_CLK_USBD>,
1018 <&tegra_car TEGRA124_CLK_PLL_U>,
1019 <&tegra_car TEGRA124_CLK_USBD>;
1020 clock-names = "reg", "pll_u", "utmi-pads";
1021 resets = <&tegra_car 22>, <&tegra_car 22>;
1022 reset-names = "usb", "utmi-pads";
1023 #phy-cells = <0>;
1024 nvidia,hssync-start-delay = <0>;
1025 nvidia,idle-wait-delay = <17>;
1026 nvidia,elastic-limit = <16>;
1027 nvidia,term-range-adj = <6>;
1028 nvidia,xcvr-setup = <9>;
1029 nvidia,xcvr-lsfslew = <0>;
1030 nvidia,xcvr-lsrslew = <3>;
1031 nvidia,hssquelch-level = <2>;
1032 nvidia,hsdiscon-level = <5>;
1033 nvidia,xcvr-hsslew = <12>;
1034 nvidia,has-utmi-pad-registers;
1035 nvidia,pmc = <&tegra_pmc 0>;
1036 status = "disabled";
1037 };
1038
1039 usb@7d004000 {
1040 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
1041 reg = <0x0 0x7d004000 0x0 0x4000>;
1042 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1043 phy_type = "utmi";
1044 clocks = <&tegra_car TEGRA124_CLK_USB2>;
1045 clock-names = "usb";
1046 resets = <&tegra_car 58>;
1047 reset-names = "usb";
1048 nvidia,phy = <&phy2>;
1049 status = "disabled";
1050 };
1051
1052 phy2: usb-phy@7d004000 {
1053 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1054 reg = <0x0 0x7d004000 0x0 0x4000>,
1055 <0x0 0x7d000000 0x0 0x4000>;
1056 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1057 phy_type = "utmi";
1058 clocks = <&tegra_car TEGRA124_CLK_USB2>,
1059 <&tegra_car TEGRA124_CLK_PLL_U>,
1060 <&tegra_car TEGRA124_CLK_USBD>;
1061 clock-names = "reg", "pll_u", "utmi-pads";
1062 resets = <&tegra_car 58>, <&tegra_car 22>;
1063 reset-names = "usb", "utmi-pads";
1064 #phy-cells = <0>;
1065 nvidia,hssync-start-delay = <0>;
1066 nvidia,idle-wait-delay = <17>;
1067 nvidia,elastic-limit = <16>;
1068 nvidia,term-range-adj = <6>;
1069 nvidia,xcvr-setup = <9>;
1070 nvidia,xcvr-lsfslew = <0>;
1071 nvidia,xcvr-lsrslew = <3>;
1072 nvidia,hssquelch-level = <2>;
1073 nvidia,hsdiscon-level = <5>;
1074 nvidia,xcvr-hsslew = <12>;
1075 nvidia,pmc = <&tegra_pmc 1>;
1076 status = "disabled";
1077 };
1078
1079 usb@7d008000 {
1080 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
1081 reg = <0x0 0x7d008000 0x0 0x4000>;
1082 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1083 phy_type = "utmi";
1084 clocks = <&tegra_car TEGRA124_CLK_USB3>;
1085 clock-names = "usb";
1086 resets = <&tegra_car 59>;
1087 reset-names = "usb";
1088 nvidia,phy = <&phy3>;
1089 status = "disabled";
1090 };
1091
1092 phy3: usb-phy@7d008000 {
1093 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1094 reg = <0x0 0x7d008000 0x0 0x4000>,
1095 <0x0 0x7d000000 0x0 0x4000>;
1096 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1097 phy_type = "utmi";
1098 clocks = <&tegra_car TEGRA124_CLK_USB3>,
1099 <&tegra_car TEGRA124_CLK_PLL_U>,
1100 <&tegra_car TEGRA124_CLK_USBD>;
1101 clock-names = "reg", "pll_u", "utmi-pads";
1102 resets = <&tegra_car 59>, <&tegra_car 22>;
1103 reset-names = "usb", "utmi-pads";
1104 #phy-cells = <0>;
1105 nvidia,hssync-start-delay = <0>;
1106 nvidia,idle-wait-delay = <17>;
1107 nvidia,elastic-limit = <16>;
1108 nvidia,term-range-adj = <6>;
1109 nvidia,xcvr-setup = <9>;
1110 nvidia,xcvr-lsfslew = <0>;
1111 nvidia,xcvr-lsrslew = <3>;
1112 nvidia,hssquelch-level = <2>;
1113 nvidia,hsdiscon-level = <5>;
1114 nvidia,xcvr-hsslew = <12>;
1115 nvidia,pmc = <&tegra_pmc 2>;
1116 status = "disabled";
1117 };
1118
1119 cpus {
1120 #address-cells = <1>;
1121 #size-cells = <0>;
1122
1123 cpu@0 {
1124 device_type = "cpu";
1125 compatible = "nvidia,tegra132-denver";
1126 reg = <0>;
1127 };
1128
1129 cpu@1 {
1130 device_type = "cpu";
1131 compatible = "nvidia,tegra132-denver";
1132 reg = <1>;
1133 };
1134 };
1135
1136 thermal-zones {
1137 cpu-thermal {
1138 polling-delay-passive = <1000>;
1139 polling-delay = <0>;
1140
1141 thermal-sensors =
1142 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
1143
1144 trips {
1145 cpu_shutdown_trip {
1146 temperature = <105000>;
1147 hysteresis = <1000>;
1148 type = "critical";
1149 };
1150
1151 cpu_throttle_trip: throttle-trip {
1152 temperature = <102000>;
1153 hysteresis = <1000>;
1154 type = "hot";
1155 };
1156 };
1157
1158 cooling-maps {
1159 map0 {
1160 trip = <&cpu_throttle_trip>;
1161 cooling-device = <&throttle_heavy 1 1>;
1162 };
1163 };
1164 };
1165
1166 mem-thermal {
1167 polling-delay-passive = <0>;
1168 polling-delay = <0>;
1169
1170 thermal-sensors =
1171 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
1172
1173 trips {
1174 mem_shutdown_trip {
1175 temperature = <101000>;
1176 hysteresis = <1000>;
1177 type = "critical";
1178 };
1179 mem_throttle_trip {
1180 temperature = <99000>;
1181 hysteresis = <1000>;
1182 type = "hot";
1183 };
1184 };
1185
1186 cooling-maps {
1187 /*
1188 * There are currently no cooling maps,
1189 * because there are no cooling devices.
1190 */
1191 };
1192 };
1193
1194 gpu-thermal {
1195 polling-delay-passive = <1000>;
1196 polling-delay = <0>;
1197
1198 thermal-sensors =
1199 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;
1200
1201 trips {
1202 gpu_shutdown_trip {
1203 temperature = <101000>;
1204 hysteresis = <1000>;
1205 type = "critical";
1206 };
1207
1208 gpu_throttle_trip: throttle-trip {
1209 temperature = <99000>;
1210 hysteresis = <1000>;
1211 type = "hot";
1212 };
1213 };
1214
1215 cooling-maps {
1216 map0 {
1217 trip = <&gpu_throttle_trip>;
1218 cooling-device = <&throttle_heavy 1 1>;
1219 };
1220 };
1221 };
1222
1223 pllx-thermal {
1224 polling-delay-passive = <0>;
1225 polling-delay = <0>;
1226
1227 thermal-sensors =
1228 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;
1229
1230 trips {
1231 pllx_shutdown_trip {
1232 temperature = <105000>;
1233 hysteresis = <1000>;
1234 type = "critical";
1235 };
1236 pllx_throttle_trip {
1237 temperature = <99000>;
1238 hysteresis = <1000>;
1239 type = "hot";
1240 };
1241 };
1242
1243 cooling-maps {
1244 /*
1245 * There are currently no cooling maps,
1246 * because there are no cooling devices.
1247 */
1248 };
1249 };
1250 };
1251
1252 timer {
1253 compatible = "arm,armv7-timer";
1254 interrupts = <GIC_PPI 13
1255 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1256 <GIC_PPI 14
1257 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1258 <GIC_PPI 11
1259 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1260 <GIC_PPI 10
1261 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1262 interrupt-parent = <&gic>;
1263 };
1264};
1#include <dt-bindings/clock/tegra124-car.h>
2#include <dt-bindings/gpio/tegra-gpio.h>
3#include <dt-bindings/memory/tegra124-mc.h>
4#include <dt-bindings/pinctrl/pinctrl-tegra.h>
5#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
6#include <dt-bindings/interrupt-controller/arm-gic.h>
7#include <dt-bindings/thermal/tegra124-soctherm.h>
8
9/ {
10 compatible = "nvidia,tegra132", "nvidia,tegra124";
11 interrupt-parent = <&lic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
14
15 pcie-controller@01003000 {
16 compatible = "nvidia,tegra124-pcie";
17 device_type = "pci";
18 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
19 0x0 0x01003800 0x0 0x00000800 /* AFI registers */
20 0x0 0x02000000 0x0 0x10000000>; /* configuration space */
21 reg-names = "pads", "afi", "cs";
22 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
23 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
24 interrupt-names = "intr", "msi";
25
26 #interrupt-cells = <1>;
27 interrupt-map-mask = <0 0 0 0>;
28 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
29
30 bus-range = <0x00 0xff>;
31 #address-cells = <3>;
32 #size-cells = <2>;
33
34 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */
35 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */
36 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
37 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
38 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
39
40 clocks = <&tegra_car TEGRA124_CLK_PCIE>,
41 <&tegra_car TEGRA124_CLK_AFI>,
42 <&tegra_car TEGRA124_CLK_PLL_E>,
43 <&tegra_car TEGRA124_CLK_CML0>;
44 clock-names = "pex", "afi", "pll_e", "cml";
45 resets = <&tegra_car 70>,
46 <&tegra_car 72>,
47 <&tegra_car 74>;
48 reset-names = "pex", "afi", "pcie_x";
49 status = "disabled";
50
51 phys = <&padctl TEGRA_XUSB_PADCTL_PCIE>;
52 phy-names = "pcie";
53
54 pci@1,0 {
55 device_type = "pci";
56 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
57 reg = <0x000800 0 0 0 0>;
58 status = "disabled";
59
60 #address-cells = <3>;
61 #size-cells = <2>;
62 ranges;
63
64 nvidia,num-lanes = <2>;
65 };
66
67 pci@2,0 {
68 device_type = "pci";
69 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
70 reg = <0x001000 0 0 0 0>;
71 status = "disabled";
72
73 #address-cells = <3>;
74 #size-cells = <2>;
75 ranges;
76
77 nvidia,num-lanes = <1>;
78 };
79 };
80
81 host1x@50000000 {
82 compatible = "nvidia,tegra124-host1x", "simple-bus";
83 reg = <0x0 0x50000000 0x0 0x00034000>;
84 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
85 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
86 clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
87 clock-names = "host1x";
88 resets = <&tegra_car 28>;
89 reset-names = "host1x";
90
91 #address-cells = <2>;
92 #size-cells = <2>;
93
94 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;
95
96 dc@54200000 {
97 compatible = "nvidia,tegra124-dc";
98 reg = <0x0 0x54200000 0x0 0x00040000>;
99 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
100 clocks = <&tegra_car TEGRA124_CLK_DISP1>,
101 <&tegra_car TEGRA124_CLK_PLL_P>;
102 clock-names = "dc", "parent";
103 resets = <&tegra_car 27>;
104 reset-names = "dc";
105
106 iommus = <&mc TEGRA_SWGROUP_DC>;
107
108 nvidia,head = <0>;
109 };
110
111 dc@54240000 {
112 compatible = "nvidia,tegra124-dc";
113 reg = <0x0 0x54240000 0x0 0x00040000>;
114 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
115 clocks = <&tegra_car TEGRA124_CLK_DISP2>,
116 <&tegra_car TEGRA124_CLK_PLL_P>;
117 clock-names = "dc", "parent";
118 resets = <&tegra_car 26>;
119 reset-names = "dc";
120
121 iommus = <&mc TEGRA_SWGROUP_DCB>;
122
123 nvidia,head = <1>;
124 };
125
126 hdmi@54280000 {
127 compatible = "nvidia,tegra124-hdmi";
128 reg = <0x0 0x54280000 0x0 0x00040000>;
129 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
130 clocks = <&tegra_car TEGRA124_CLK_HDMI>,
131 <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>;
132 clock-names = "hdmi", "parent";
133 resets = <&tegra_car 51>;
134 reset-names = "hdmi";
135 status = "disabled";
136 };
137
138 sor@54540000 {
139 compatible = "nvidia,tegra124-sor";
140 reg = <0x0 0x54540000 0x0 0x00040000>;
141 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
142 clocks = <&tegra_car TEGRA124_CLK_SOR0>,
143 <&tegra_car TEGRA124_CLK_PLL_D_OUT0>,
144 <&tegra_car TEGRA124_CLK_PLL_DP>,
145 <&tegra_car TEGRA124_CLK_CLK_M>;
146 clock-names = "sor", "parent", "dp", "safe";
147 resets = <&tegra_car 182>;
148 reset-names = "sor";
149 status = "disabled";
150 };
151
152 dpaux: dpaux@545c0000 {
153 compatible = "nvidia,tegra124-dpaux";
154 reg = <0x0 0x545c0000 0x0 0x00040000>;
155 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
156 clocks = <&tegra_car TEGRA124_CLK_DPAUX>,
157 <&tegra_car TEGRA124_CLK_PLL_DP>;
158 clock-names = "dpaux", "parent";
159 resets = <&tegra_car 181>;
160 reset-names = "dpaux";
161 status = "disabled";
162 };
163 };
164
165 gic: interrupt-controller@50041000 {
166 compatible = "arm,cortex-a15-gic";
167 #interrupt-cells = <3>;
168 interrupt-controller;
169 reg = <0x0 0x50041000 0x0 0x1000>,
170 <0x0 0x50042000 0x0 0x2000>,
171 <0x0 0x50044000 0x0 0x2000>,
172 <0x0 0x50046000 0x0 0x2000>;
173 interrupts = <GIC_PPI 9
174 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
175 interrupt-parent = <&gic>;
176 };
177
178 gpu@57000000 {
179 compatible = "nvidia,gk20a";
180 reg = <0x0 0x57000000 0x0 0x01000000>,
181 <0x0 0x58000000 0x0 0x01000000>;
182 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
183 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
184 interrupt-names = "stall", "nonstall";
185 clocks = <&tegra_car TEGRA124_CLK_GPU>,
186 <&tegra_car TEGRA124_CLK_PLL_P_OUT5>;
187 clock-names = "gpu", "pwr";
188 resets = <&tegra_car 184>;
189 reset-names = "gpu";
190 status = "disabled";
191 };
192
193 lic: interrupt-controller@60004000 {
194 compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr";
195 reg = <0x0 0x60004000 0x0 0x100>,
196 <0x0 0x60004100 0x0 0x100>,
197 <0x0 0x60004200 0x0 0x100>,
198 <0x0 0x60004300 0x0 0x100>,
199 <0x0 0x60004400 0x0 0x100>;
200 interrupt-controller;
201 #interrupt-cells = <3>;
202 interrupt-parent = <&gic>;
203 };
204
205 timer@60005000 {
206 compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer";
207 reg = <0x0 0x60005000 0x0 0x400>;
208 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
209 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
210 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
211 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
212 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
213 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
214 clocks = <&tegra_car TEGRA124_CLK_TIMER>;
215 clock-names = "timer";
216 };
217
218 tegra_car: clock@60006000 {
219 compatible = "nvidia,tegra132-car";
220 reg = <0x0 0x60006000 0x0 0x1000>;
221 #clock-cells = <1>;
222 #reset-cells = <1>;
223 nvidia,external-memory-controller = <&emc>;
224 };
225
226 flow-controller@60007000 {
227 compatible = "nvidia,tegra124-flowctrl";
228 reg = <0x0 0x60007000 0x0 0x1000>;
229 };
230
231 actmon@6000c800 {
232 compatible = "nvidia,tegra124-actmon";
233 reg = <0x0 0x6000c800 0x0 0x400>;
234 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
235 clocks = <&tegra_car TEGRA124_CLK_ACTMON>,
236 <&tegra_car TEGRA124_CLK_EMC>;
237 clock-names = "actmon", "emc";
238 resets = <&tegra_car 119>;
239 reset-names = "actmon";
240 };
241
242 gpio: gpio@6000d000 {
243 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
244 reg = <0x0 0x6000d000 0x0 0x1000>;
245 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
246 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
247 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
248 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
249 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
250 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
251 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
252 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
253 #gpio-cells = <2>;
254 gpio-controller;
255 #interrupt-cells = <2>;
256 interrupt-controller;
257 };
258
259 apbdma: dma@60020000 {
260 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
261 reg = <0x0 0x60020000 0x0 0x1400>;
262 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
263 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
264 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
265 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
266 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
267 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
268 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
269 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
270 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
271 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
272 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
273 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
274 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
275 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
276 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
277 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
278 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
279 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
280 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
281 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
282 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
283 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
284 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
285 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
286 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
287 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
288 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
289 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
290 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
291 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
292 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
293 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
294 clocks = <&tegra_car TEGRA124_CLK_APBDMA>;
295 clock-names = "dma";
296 resets = <&tegra_car 34>;
297 reset-names = "dma";
298 #dma-cells = <1>;
299 };
300
301 apbmisc@70000800 {
302 compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc";
303 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
304 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */
305 };
306
307 pinmux: pinmux@70000868 {
308 compatible = "nvidia,tegra124-pinmux";
309 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
310 <0x0 0x70003000 0x0 0x434>, /* Mux registers */
311 <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */
312 };
313
314 /*
315 * There are two serial driver i.e. 8250 based simple serial
316 * driver and APB DMA based serial driver for higher baudrate
317 * and performance. To enable the 8250 based driver, the compatible
318 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
319 * the APB DMA based serial driver, the compatible is
320 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
321 */
322 uarta: serial@70006000 {
323 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
324 reg = <0x0 0x70006000 0x0 0x40>;
325 reg-shift = <2>;
326 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
327 clocks = <&tegra_car TEGRA124_CLK_UARTA>;
328 clock-names = "serial";
329 resets = <&tegra_car 6>;
330 reset-names = "serial";
331 dmas = <&apbdma 8>, <&apbdma 8>;
332 dma-names = "rx", "tx";
333 status = "disabled";
334 };
335
336 uartb: serial@70006040 {
337 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
338 reg = <0x0 0x70006040 0x0 0x40>;
339 reg-shift = <2>;
340 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
341 clocks = <&tegra_car TEGRA124_CLK_UARTB>;
342 clock-names = "serial";
343 resets = <&tegra_car 7>;
344 reset-names = "serial";
345 dmas = <&apbdma 9>, <&apbdma 9>;
346 dma-names = "rx", "tx";
347 status = "disabled";
348 };
349
350 uartc: serial@70006200 {
351 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
352 reg = <0x0 0x70006200 0x0 0x40>;
353 reg-shift = <2>;
354 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
355 clocks = <&tegra_car TEGRA124_CLK_UARTC>;
356 clock-names = "serial";
357 resets = <&tegra_car 55>;
358 reset-names = "serial";
359 dmas = <&apbdma 10>, <&apbdma 10>;
360 dma-names = "rx", "tx";
361 status = "disabled";
362 };
363
364 uartd: serial@70006300 {
365 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
366 reg = <0x0 0x70006300 0x0 0x40>;
367 reg-shift = <2>;
368 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
369 clocks = <&tegra_car TEGRA124_CLK_UARTD>;
370 clock-names = "serial";
371 resets = <&tegra_car 65>;
372 reset-names = "serial";
373 dmas = <&apbdma 19>, <&apbdma 19>;
374 dma-names = "rx", "tx";
375 status = "disabled";
376 };
377
378 pwm: pwm@7000a000 {
379 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
380 reg = <0x0 0x7000a000 0x0 0x100>;
381 #pwm-cells = <2>;
382 clocks = <&tegra_car TEGRA124_CLK_PWM>;
383 clock-names = "pwm";
384 resets = <&tegra_car 17>;
385 reset-names = "pwm";
386 status = "disabled";
387 };
388
389 i2c@7000c000 {
390 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
391 reg = <0x0 0x7000c000 0x0 0x100>;
392 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
393 #address-cells = <1>;
394 #size-cells = <0>;
395 clocks = <&tegra_car TEGRA124_CLK_I2C1>;
396 clock-names = "div-clk";
397 resets = <&tegra_car 12>;
398 reset-names = "i2c";
399 dmas = <&apbdma 21>, <&apbdma 21>;
400 dma-names = "rx", "tx";
401 status = "disabled";
402 };
403
404 i2c@7000c400 {
405 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
406 reg = <0x0 0x7000c400 0x0 0x100>;
407 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
408 #address-cells = <1>;
409 #size-cells = <0>;
410 clocks = <&tegra_car TEGRA124_CLK_I2C2>;
411 clock-names = "div-clk";
412 resets = <&tegra_car 54>;
413 reset-names = "i2c";
414 dmas = <&apbdma 22>, <&apbdma 22>;
415 dma-names = "rx", "tx";
416 status = "disabled";
417 };
418
419 i2c@7000c500 {
420 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
421 reg = <0x0 0x7000c500 0x0 0x100>;
422 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
423 #address-cells = <1>;
424 #size-cells = <0>;
425 clocks = <&tegra_car TEGRA124_CLK_I2C3>;
426 clock-names = "div-clk";
427 resets = <&tegra_car 67>;
428 reset-names = "i2c";
429 dmas = <&apbdma 23>, <&apbdma 23>;
430 dma-names = "rx", "tx";
431 status = "disabled";
432 };
433
434 i2c@7000c700 {
435 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
436 reg = <0x0 0x7000c700 0x0 0x100>;
437 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
438 #address-cells = <1>;
439 #size-cells = <0>;
440 clocks = <&tegra_car TEGRA124_CLK_I2C4>;
441 clock-names = "div-clk";
442 resets = <&tegra_car 103>;
443 reset-names = "i2c";
444 dmas = <&apbdma 26>, <&apbdma 26>;
445 dma-names = "rx", "tx";
446 status = "disabled";
447 };
448
449 i2c@7000d000 {
450 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
451 reg = <0x0 0x7000d000 0x0 0x100>;
452 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
453 #address-cells = <1>;
454 #size-cells = <0>;
455 clocks = <&tegra_car TEGRA124_CLK_I2C5>;
456 clock-names = "div-clk";
457 resets = <&tegra_car 47>;
458 reset-names = "i2c";
459 dmas = <&apbdma 24>, <&apbdma 24>;
460 dma-names = "rx", "tx";
461 status = "disabled";
462 };
463
464 i2c@7000d100 {
465 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
466 reg = <0x0 0x7000d100 0x0 0x100>;
467 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
468 #address-cells = <1>;
469 #size-cells = <0>;
470 clocks = <&tegra_car TEGRA124_CLK_I2C6>;
471 clock-names = "div-clk";
472 resets = <&tegra_car 166>;
473 reset-names = "i2c";
474 dmas = <&apbdma 30>, <&apbdma 30>;
475 dma-names = "rx", "tx";
476 status = "disabled";
477 };
478
479 spi@7000d400 {
480 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
481 reg = <0x0 0x7000d400 0x0 0x200>;
482 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
483 #address-cells = <1>;
484 #size-cells = <0>;
485 clocks = <&tegra_car TEGRA124_CLK_SBC1>;
486 clock-names = "spi";
487 resets = <&tegra_car 41>;
488 reset-names = "spi";
489 dmas = <&apbdma 15>, <&apbdma 15>;
490 dma-names = "rx", "tx";
491 status = "disabled";
492 };
493
494 spi@7000d600 {
495 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
496 reg = <0x0 0x7000d600 0x0 0x200>;
497 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
498 #address-cells = <1>;
499 #size-cells = <0>;
500 clocks = <&tegra_car TEGRA124_CLK_SBC2>;
501 clock-names = "spi";
502 resets = <&tegra_car 44>;
503 reset-names = "spi";
504 dmas = <&apbdma 16>, <&apbdma 16>;
505 dma-names = "rx", "tx";
506 status = "disabled";
507 };
508
509 spi@7000d800 {
510 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
511 reg = <0x0 0x7000d800 0x0 0x200>;
512 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
513 #address-cells = <1>;
514 #size-cells = <0>;
515 clocks = <&tegra_car TEGRA124_CLK_SBC3>;
516 clock-names = "spi";
517 resets = <&tegra_car 46>;
518 reset-names = "spi";
519 dmas = <&apbdma 17>, <&apbdma 17>;
520 dma-names = "rx", "tx";
521 status = "disabled";
522 };
523
524 spi@7000da00 {
525 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
526 reg = <0x0 0x7000da00 0x0 0x200>;
527 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
528 #address-cells = <1>;
529 #size-cells = <0>;
530 clocks = <&tegra_car TEGRA124_CLK_SBC4>;
531 clock-names = "spi";
532 resets = <&tegra_car 68>;
533 reset-names = "spi";
534 dmas = <&apbdma 18>, <&apbdma 18>;
535 dma-names = "rx", "tx";
536 status = "disabled";
537 };
538
539 spi@7000dc00 {
540 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
541 reg = <0x0 0x7000dc00 0x0 0x200>;
542 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
543 #address-cells = <1>;
544 #size-cells = <0>;
545 clocks = <&tegra_car TEGRA124_CLK_SBC5>;
546 clock-names = "spi";
547 resets = <&tegra_car 104>;
548 reset-names = "spi";
549 dmas = <&apbdma 27>, <&apbdma 27>;
550 dma-names = "rx", "tx";
551 status = "disabled";
552 };
553
554 spi@7000de00 {
555 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
556 reg = <0x0 0x7000de00 0x0 0x200>;
557 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
558 #address-cells = <1>;
559 #size-cells = <0>;
560 clocks = <&tegra_car TEGRA124_CLK_SBC6>;
561 clock-names = "spi";
562 resets = <&tegra_car 105>;
563 reset-names = "spi";
564 dmas = <&apbdma 28>, <&apbdma 28>;
565 dma-names = "rx", "tx";
566 status = "disabled";
567 };
568
569 rtc@7000e000 {
570 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
571 reg = <0x0 0x7000e000 0x0 0x100>;
572 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
573 clocks = <&tegra_car TEGRA124_CLK_RTC>;
574 clock-names = "rtc";
575 };
576
577 pmc@7000e400 {
578 compatible = "nvidia,tegra124-pmc";
579 reg = <0x0 0x7000e400 0x0 0x400>;
580 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
581 clock-names = "pclk", "clk32k_in";
582 };
583
584 fuse@7000f800 {
585 compatible = "nvidia,tegra124-efuse";
586 reg = <0x0 0x7000f800 0x0 0x400>;
587 clocks = <&tegra_car TEGRA124_CLK_FUSE>;
588 clock-names = "fuse";
589 resets = <&tegra_car 39>;
590 reset-names = "fuse";
591 };
592
593 mc: memory-controller@70019000 {
594 compatible = "nvidia,tegra132-mc";
595 reg = <0x0 0x70019000 0x0 0x1000>;
596 clocks = <&tegra_car TEGRA124_CLK_MC>;
597 clock-names = "mc";
598
599 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
600
601 #iommu-cells = <1>;
602 };
603
604 emc: emc@7001b000 {
605 compatible = "nvidia,tegra132-emc", "nvidia,tegra124-emc";
606 reg = <0x0 0x7001b000 0x0 0x1000>;
607
608 nvidia,memory-controller = <&mc>;
609 };
610
611 sata@70020000 {
612 compatible = "nvidia,tegra124-ahci";
613 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
614 <0x0 0x70020000 0x0 0x7000>; /* SATA */
615 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
616 clocks = <&tegra_car TEGRA124_CLK_SATA>,
617 <&tegra_car TEGRA124_CLK_SATA_OOB>,
618 <&tegra_car TEGRA124_CLK_CML1>,
619 <&tegra_car TEGRA124_CLK_PLL_E>;
620 clock-names = "sata", "sata-oob", "cml1", "pll_e";
621 resets = <&tegra_car 124>,
622 <&tegra_car 123>,
623 <&tegra_car 129>;
624 reset-names = "sata", "sata-oob", "sata-cold";
625 phys = <&padctl TEGRA_XUSB_PADCTL_SATA>;
626 phy-names = "sata-phy";
627 status = "disabled";
628 };
629
630 hda@70030000 {
631 compatible = "nvidia,tegra132-hda", "nvidia,tegra124-hda",
632 "nvidia,tegra30-hda";
633 reg = <0x0 0x70030000 0x0 0x10000>;
634 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
635 clocks = <&tegra_car TEGRA124_CLK_HDA>,
636 <&tegra_car TEGRA124_CLK_HDA2HDMI>,
637 <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>;
638 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
639 resets = <&tegra_car 125>, /* hda */
640 <&tegra_car 128>, /* hda2hdmi */
641 <&tegra_car 111>; /* hda2codec_2x */
642 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
643 status = "disabled";
644 };
645
646 padctl: padctl@7009f000 {
647 compatible = "nvidia,tegra132-xusb-padctl",
648 "nvidia,tegra124-xusb-padctl";
649 reg = <0x0 0x7009f000 0x0 0x1000>;
650 resets = <&tegra_car 142>;
651 reset-names = "padctl";
652
653 #phy-cells = <1>;
654
655 phys {
656 pcie-0 {
657 status = "disabled";
658 };
659
660 sata-0 {
661 status = "disabled";
662 };
663
664 usb3-0 {
665 status = "disabled";
666 };
667
668 usb3-1 {
669 status = "disabled";
670 };
671
672 utmi-0 {
673 status = "disabled";
674 };
675
676 utmi-1 {
677 status = "disabled";
678 };
679
680 utmi-2 {
681 status = "disabled";
682 };
683 };
684 };
685
686 sdhci@700b0000 {
687 compatible = "nvidia,tegra124-sdhci";
688 reg = <0x0 0x700b0000 0x0 0x200>;
689 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
690 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
691 clock-names = "sdhci";
692 resets = <&tegra_car 14>;
693 reset-names = "sdhci";
694 status = "disabled";
695 };
696
697 sdhci@700b0200 {
698 compatible = "nvidia,tegra124-sdhci";
699 reg = <0x0 0x700b0200 0x0 0x200>;
700 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
701 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
702 clock-names = "sdhci";
703 resets = <&tegra_car 9>;
704 reset-names = "sdhci";
705 status = "disabled";
706 };
707
708 sdhci@700b0400 {
709 compatible = "nvidia,tegra124-sdhci";
710 reg = <0x0 0x700b0400 0x0 0x200>;
711 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
712 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
713 clock-names = "sdhci";
714 resets = <&tegra_car 69>;
715 reset-names = "sdhci";
716 status = "disabled";
717 };
718
719 sdhci@700b0600 {
720 compatible = "nvidia,tegra124-sdhci";
721 reg = <0x0 0x700b0600 0x0 0x200>;
722 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
723 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
724 clock-names = "sdhci";
725 resets = <&tegra_car 15>;
726 reset-names = "sdhci";
727 status = "disabled";
728 };
729
730 soctherm: thermal-sensor@700e2000 {
731 compatible = "nvidia,tegra132-soctherm";
732 reg = <0x0 0x700e2000 0x0 0x600 /* 0: SOC_THERM reg_base */
733 0x0 0x70040000 0x0 0x200>; /* 2: CCROC reg_base */
734 reg-names = "soctherm-reg", "ccroc-reg";
735 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
736 clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
737 <&tegra_car TEGRA124_CLK_SOC_THERM>;
738 clock-names = "tsensor", "soctherm";
739 resets = <&tegra_car 78>;
740 reset-names = "soctherm";
741 #thermal-sensor-cells = <1>;
742
743 throttle-cfgs {
744 throttle_heavy: heavy {
745 nvidia,priority = <100>;
746 nvidia,cpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>;
747
748 #cooling-cells = <2>;
749 };
750 };
751 };
752
753 thermal-zones {
754 cpu {
755 polling-delay-passive = <1000>;
756 polling-delay = <0>;
757
758 thermal-sensors =
759 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
760
761 trips {
762 cpu_shutdown_trip {
763 temperature = <105000>;
764 hysteresis = <1000>;
765 type = "critical";
766 };
767
768 cpu_throttle_trip: throttle-trip {
769 temperature = <102000>;
770 hysteresis = <1000>;
771 type = "hot";
772 };
773 };
774
775 cooling-maps {
776 map0 {
777 trip = <&cpu_throttle_trip>;
778 cooling-device = <&throttle_heavy 1 1>;
779 };
780 };
781 };
782 mem {
783 polling-delay-passive = <0>;
784 polling-delay = <0>;
785
786 thermal-sensors =
787 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
788
789 trips {
790 mem_shutdown_trip {
791 temperature = <101000>;
792 hysteresis = <1000>;
793 type = "critical";
794 };
795 };
796
797 cooling-maps {
798 /*
799 * There are currently no cooling maps,
800 * because there are no cooling devices.
801 */
802 };
803 };
804 gpu {
805 polling-delay-passive = <1000>;
806 polling-delay = <0>;
807
808 thermal-sensors =
809 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;
810
811 trips {
812 gpu_shutdown_trip {
813 temperature = <101000>;
814 hysteresis = <1000>;
815 type = "critical";
816 };
817
818 gpu_throttle_trip: throttle-trip {
819 temperature = <99000>;
820 hysteresis = <1000>;
821 type = "hot";
822 };
823 };
824
825 cooling-maps {
826 map0 {
827 trip = <&gpu_throttle_trip>;
828 cooling-device = <&throttle_heavy 1 1>;
829 };
830 };
831 };
832 pllx {
833 polling-delay-passive = <0>;
834 polling-delay = <0>;
835
836 thermal-sensors =
837 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;
838
839 trips {
840 pllx_shutdown_trip {
841 temperature = <105000>;
842 hysteresis = <1000>;
843 type = "critical";
844 };
845 };
846
847 cooling-maps {
848 /*
849 * There are currently no cooling maps,
850 * because there are no cooling devices.
851 */
852 };
853 };
854 };
855
856 ahub@70300000 {
857 compatible = "nvidia,tegra124-ahub";
858 reg = <0x0 0x70300000 0x0 0x200>,
859 <0x0 0x70300800 0x0 0x800>,
860 <0x0 0x70300200 0x0 0x600>;
861 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
862 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
863 <&tegra_car TEGRA124_CLK_APBIF>;
864 clock-names = "d_audio", "apbif";
865 resets = <&tegra_car 106>, /* d_audio */
866 <&tegra_car 107>, /* apbif */
867 <&tegra_car 30>, /* i2s0 */
868 <&tegra_car 11>, /* i2s1 */
869 <&tegra_car 18>, /* i2s2 */
870 <&tegra_car 101>, /* i2s3 */
871 <&tegra_car 102>, /* i2s4 */
872 <&tegra_car 108>, /* dam0 */
873 <&tegra_car 109>, /* dam1 */
874 <&tegra_car 110>, /* dam2 */
875 <&tegra_car 10>, /* spdif */
876 <&tegra_car 153>, /* amx */
877 <&tegra_car 185>, /* amx1 */
878 <&tegra_car 154>, /* adx */
879 <&tegra_car 180>, /* adx1 */
880 <&tegra_car 186>, /* afc0 */
881 <&tegra_car 187>, /* afc1 */
882 <&tegra_car 188>, /* afc2 */
883 <&tegra_car 189>, /* afc3 */
884 <&tegra_car 190>, /* afc4 */
885 <&tegra_car 191>; /* afc5 */
886 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
887 "i2s3", "i2s4", "dam0", "dam1", "dam2",
888 "spdif", "amx", "amx1", "adx", "adx1",
889 "afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
890 dmas = <&apbdma 1>, <&apbdma 1>,
891 <&apbdma 2>, <&apbdma 2>,
892 <&apbdma 3>, <&apbdma 3>,
893 <&apbdma 4>, <&apbdma 4>,
894 <&apbdma 6>, <&apbdma 6>,
895 <&apbdma 7>, <&apbdma 7>,
896 <&apbdma 12>, <&apbdma 12>,
897 <&apbdma 13>, <&apbdma 13>,
898 <&apbdma 14>, <&apbdma 14>,
899 <&apbdma 29>, <&apbdma 29>;
900 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
901 "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
902 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
903 "rx9", "tx9";
904 ranges;
905 #address-cells = <2>;
906 #size-cells = <2>;
907
908 tegra_i2s0: i2s@70301000 {
909 compatible = "nvidia,tegra124-i2s";
910 reg = <0x0 0x70301000 0x0 0x100>;
911 nvidia,ahub-cif-ids = <4 4>;
912 clocks = <&tegra_car TEGRA124_CLK_I2S0>;
913 clock-names = "i2s";
914 resets = <&tegra_car 30>;
915 reset-names = "i2s";
916 status = "disabled";
917 };
918
919 tegra_i2s1: i2s@70301100 {
920 compatible = "nvidia,tegra124-i2s";
921 reg = <0x0 0x70301100 0x0 0x100>;
922 nvidia,ahub-cif-ids = <5 5>;
923 clocks = <&tegra_car TEGRA124_CLK_I2S1>;
924 clock-names = "i2s";
925 resets = <&tegra_car 11>;
926 reset-names = "i2s";
927 status = "disabled";
928 };
929
930 tegra_i2s2: i2s@70301200 {
931 compatible = "nvidia,tegra124-i2s";
932 reg = <0x0 0x70301200 0x0 0x100>;
933 nvidia,ahub-cif-ids = <6 6>;
934 clocks = <&tegra_car TEGRA124_CLK_I2S2>;
935 clock-names = "i2s";
936 resets = <&tegra_car 18>;
937 reset-names = "i2s";
938 status = "disabled";
939 };
940
941 tegra_i2s3: i2s@70301300 {
942 compatible = "nvidia,tegra124-i2s";
943 reg = <0x0 0x70301300 0x0 0x100>;
944 nvidia,ahub-cif-ids = <7 7>;
945 clocks = <&tegra_car TEGRA124_CLK_I2S3>;
946 clock-names = "i2s";
947 resets = <&tegra_car 101>;
948 reset-names = "i2s";
949 status = "disabled";
950 };
951
952 tegra_i2s4: i2s@70301400 {
953 compatible = "nvidia,tegra124-i2s";
954 reg = <0x0 0x70301400 0x0 0x100>;
955 nvidia,ahub-cif-ids = <8 8>;
956 clocks = <&tegra_car TEGRA124_CLK_I2S4>;
957 clock-names = "i2s";
958 resets = <&tegra_car 102>;
959 reset-names = "i2s";
960 status = "disabled";
961 };
962 };
963
964 usb@7d000000 {
965 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
966 reg = <0x0 0x7d000000 0x0 0x4000>;
967 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
968 phy_type = "utmi";
969 clocks = <&tegra_car TEGRA124_CLK_USBD>;
970 clock-names = "usb";
971 resets = <&tegra_car 22>;
972 reset-names = "usb";
973 nvidia,phy = <&phy1>;
974 status = "disabled";
975 };
976
977 phy1: usb-phy@7d000000 {
978 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
979 reg = <0x0 0x7d000000 0x0 0x4000>,
980 <0x0 0x7d000000 0x0 0x4000>;
981 phy_type = "utmi";
982 clocks = <&tegra_car TEGRA124_CLK_USBD>,
983 <&tegra_car TEGRA124_CLK_PLL_U>,
984 <&tegra_car TEGRA124_CLK_USBD>;
985 clock-names = "reg", "pll_u", "utmi-pads";
986 resets = <&tegra_car 22>, <&tegra_car 22>;
987 reset-names = "usb", "utmi-pads";
988 nvidia,hssync-start-delay = <0>;
989 nvidia,idle-wait-delay = <17>;
990 nvidia,elastic-limit = <16>;
991 nvidia,term-range-adj = <6>;
992 nvidia,xcvr-setup = <9>;
993 nvidia,xcvr-lsfslew = <0>;
994 nvidia,xcvr-lsrslew = <3>;
995 nvidia,hssquelch-level = <2>;
996 nvidia,hsdiscon-level = <5>;
997 nvidia,xcvr-hsslew = <12>;
998 nvidia,has-utmi-pad-registers;
999 status = "disabled";
1000 };
1001
1002 usb@7d004000 {
1003 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1004 reg = <0x0 0x7d004000 0x0 0x4000>;
1005 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1006 phy_type = "utmi";
1007 clocks = <&tegra_car TEGRA124_CLK_USB2>;
1008 clock-names = "usb";
1009 resets = <&tegra_car 58>;
1010 reset-names = "usb";
1011 nvidia,phy = <&phy2>;
1012 status = "disabled";
1013 };
1014
1015 phy2: usb-phy@7d004000 {
1016 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1017 reg = <0x0 0x7d004000 0x0 0x4000>,
1018 <0x0 0x7d000000 0x0 0x4000>;
1019 phy_type = "utmi";
1020 clocks = <&tegra_car TEGRA124_CLK_USB2>,
1021 <&tegra_car TEGRA124_CLK_PLL_U>,
1022 <&tegra_car TEGRA124_CLK_USBD>;
1023 clock-names = "reg", "pll_u", "utmi-pads";
1024 resets = <&tegra_car 58>, <&tegra_car 22>;
1025 reset-names = "usb", "utmi-pads";
1026 nvidia,hssync-start-delay = <0>;
1027 nvidia,idle-wait-delay = <17>;
1028 nvidia,elastic-limit = <16>;
1029 nvidia,term-range-adj = <6>;
1030 nvidia,xcvr-setup = <9>;
1031 nvidia,xcvr-lsfslew = <0>;
1032 nvidia,xcvr-lsrslew = <3>;
1033 nvidia,hssquelch-level = <2>;
1034 nvidia,hsdiscon-level = <5>;
1035 nvidia,xcvr-hsslew = <12>;
1036 status = "disabled";
1037 };
1038
1039 usb@7d008000 {
1040 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1041 reg = <0x0 0x7d008000 0x0 0x4000>;
1042 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1043 phy_type = "utmi";
1044 clocks = <&tegra_car TEGRA124_CLK_USB3>;
1045 clock-names = "usb";
1046 resets = <&tegra_car 59>;
1047 reset-names = "usb";
1048 nvidia,phy = <&phy3>;
1049 status = "disabled";
1050 };
1051
1052 phy3: usb-phy@7d008000 {
1053 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1054 reg = <0x0 0x7d008000 0x0 0x4000>,
1055 <0x0 0x7d000000 0x0 0x4000>;
1056 phy_type = "utmi";
1057 clocks = <&tegra_car TEGRA124_CLK_USB3>,
1058 <&tegra_car TEGRA124_CLK_PLL_U>,
1059 <&tegra_car TEGRA124_CLK_USBD>;
1060 clock-names = "reg", "pll_u", "utmi-pads";
1061 resets = <&tegra_car 59>, <&tegra_car 22>;
1062 reset-names = "usb", "utmi-pads";
1063 nvidia,hssync-start-delay = <0>;
1064 nvidia,idle-wait-delay = <17>;
1065 nvidia,elastic-limit = <16>;
1066 nvidia,term-range-adj = <6>;
1067 nvidia,xcvr-setup = <9>;
1068 nvidia,xcvr-lsfslew = <0>;
1069 nvidia,xcvr-lsrslew = <3>;
1070 nvidia,hssquelch-level = <2>;
1071 nvidia,hsdiscon-level = <5>;
1072 nvidia,xcvr-hsslew = <12>;
1073 status = "disabled";
1074 };
1075
1076 cpus {
1077 #address-cells = <1>;
1078 #size-cells = <0>;
1079
1080 cpu@0 {
1081 device_type = "cpu";
1082 compatible = "nvidia,denver", "arm,armv8";
1083 reg = <0>;
1084 };
1085
1086 cpu@1 {
1087 device_type = "cpu";
1088 compatible = "nvidia,denver", "arm,armv8";
1089 reg = <1>;
1090 };
1091 };
1092
1093 timer {
1094 compatible = "arm,armv7-timer";
1095 interrupts = <GIC_PPI 13
1096 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1097 <GIC_PPI 14
1098 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1099 <GIC_PPI 11
1100 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1101 <GIC_PPI 10
1102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1103 interrupt-parent = <&gic>;
1104 };
1105};