1/* SPDX-License-Identifier: GPL-2.0-only */
 2/*
 3 *  arch/arm/include/debug/icedcc.S
 4 *
 5 *  Copyright (C) 1994-1999 Russell King
 
 
 
 
 
 6 */
 7
 8		@@ debug using ARM EmbeddedICE DCC channel
 9
10		.macro	addruart, rp, rv, tmp
11		.endm
12
13#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7)
14
15		.macro	senduart, rd, rx
16		mcr	p14, 0, \rd, c0, c5, 0
17		.endm
18
19		.macro	busyuart, rd, rx
201001:
21		mrc	p14, 0, \rx, c0, c1, 0
22		tst	\rx, #0x20000000
23		beq	1001b
24		.endm
25
26		.macro	waituartcts, rd, rx
27		.endm
28
29		.macro	waituarttxrdy, rd, rx
30		mov	\rd, #0x2000000
311001:
32		subs	\rd, \rd, #1
33		bmi	1002f
34		mrc	p14, 0, \rx, c0, c1, 0
35		tst	\rx, #0x20000000
36		bne	1001b
371002:
38		.endm
39
40#elif defined(CONFIG_CPU_XSCALE)
41
42		.macro	senduart, rd, rx
43		mcr	p14, 0, \rd, c8, c0, 0
44		.endm
45
46		.macro	busyuart, rd, rx
471001:
48		mrc	p14, 0, \rx, c14, c0, 0
49		tst	\rx, #0x10000000
50		beq	1001b
51		.endm
52
53		.macro	waituartcts, rd, rx
54		.endm
55
56		.macro	waituarttxrdy, rd, rx
57		mov	\rd, #0x10000000
581001:
59		subs	\rd, \rd, #1
60		bmi	1002f
61		mrc	p14, 0, \rx, c14, c0, 0
62		tst	\rx, #0x10000000
63		bne	1001b
641002:
65		.endm
66
67#else
68
69		.macro	senduart, rd, rx
70		mcr	p14, 0, \rd, c1, c0, 0
71		.endm
72
73		.macro	busyuart, rd, rx
741001:
75		mrc	p14, 0, \rx, c0, c0, 0
76		tst	\rx, #2
77		beq	1001b
78
79		.endm
80
81		.macro	waituartcts, rd, rx
82		.endm
83
84		.macro	waituarttxrdy, rd, rx
85		mov	\rd, #0x2000000
861001:
87		subs	\rd, \rd, #1
88		bmi	1002f
89		mrc	p14, 0, \rx, c0, c0, 0
90		tst	\rx, #2
91		bne	1001b
921002:
93		.endm
94
95#endif	/* CONFIG_CPU_V6 */

 
 1/*
 2 *  arch/arm/include/debug/icedcc.S
 3 *
 4 *  Copyright (C) 1994-1999 Russell King
 5 *
 6 * This program is free software; you can redistribute it and/or modify
 7 * it under the terms of the GNU General Public License version 2 as
 8 * published by the Free Software Foundation.
 9 *
10 */
11
12		@@ debug using ARM EmbeddedICE DCC channel
13
14		.macro	addruart, rp, rv, tmp
15		.endm
16
17#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7)
18
19		.macro	senduart, rd, rx
20		mcr	p14, 0, \rd, c0, c5, 0
21		.endm
22
23		.macro	busyuart, rd, rx
241001:
25		mrc	p14, 0, \rx, c0, c1, 0
26		tst	\rx, #0x20000000
27		beq	1001b
28		.endm
29
30		.macro	waituart, rd, rx
 
 
 
31		mov	\rd, #0x2000000
321001:
33		subs	\rd, \rd, #1
34		bmi	1002f
35		mrc	p14, 0, \rx, c0, c1, 0
36		tst	\rx, #0x20000000
37		bne	1001b
381002:
39		.endm
40
41#elif defined(CONFIG_CPU_XSCALE)
42
43		.macro	senduart, rd, rx
44		mcr	p14, 0, \rd, c8, c0, 0
45		.endm
46
47		.macro	busyuart, rd, rx
481001:
49		mrc	p14, 0, \rx, c14, c0, 0
50		tst	\rx, #0x10000000
51		beq	1001b
52		.endm
53
54		.macro	waituart, rd, rx
 
 
 
55		mov	\rd, #0x10000000
561001:
57		subs	\rd, \rd, #1
58		bmi	1002f
59		mrc	p14, 0, \rx, c14, c0, 0
60		tst	\rx, #0x10000000
61		bne	1001b
621002:
63		.endm
64
65#else
66
67		.macro	senduart, rd, rx
68		mcr	p14, 0, \rd, c1, c0, 0
69		.endm
70
71		.macro	busyuart, rd, rx
721001:
73		mrc	p14, 0, \rx, c0, c0, 0
74		tst	\rx, #2
75		beq	1001b
76
77		.endm
78
79		.macro	waituart, rd, rx
 
 
 
80		mov	\rd, #0x2000000
811001:
82		subs	\rd, \rd, #1
83		bmi	1002f
84		mrc	p14, 0, \rx, c0, c0, 0
85		tst	\rx, #2
86		bne	1001b
871002:
88		.endm
89
90#endif	/* CONFIG_CPU_V6 */