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1/*
2 * skl.c - Implementation of ASoC Intel SKL HD Audio driver
3 *
4 * Copyright (C) 2014-2015 Intel Corp
5 * Author: Jeeja KP <jeeja.kp@intel.com>
6 *
7 * Derived mostly from Intel HDA driver with following copyrights:
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; version 2 of the License.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
22 */
23
24#include <linux/module.h>
25#include <linux/pci.h>
26#include <linux/pm_runtime.h>
27#include <linux/platform_device.h>
28#include <linux/firmware.h>
29#include <linux/delay.h>
30#include <sound/pcm.h>
31#include "../common/sst-acpi.h"
32#include <sound/hda_register.h>
33#include <sound/hdaudio.h>
34#include <sound/hda_i915.h>
35#include "skl.h"
36#include "skl-sst-dsp.h"
37#include "skl-sst-ipc.h"
38
39static struct skl_machine_pdata skl_dmic_data;
40
41/*
42 * initialize the PCI registers
43 */
44static void skl_update_pci_byte(struct pci_dev *pci, unsigned int reg,
45 unsigned char mask, unsigned char val)
46{
47 unsigned char data;
48
49 pci_read_config_byte(pci, reg, &data);
50 data &= ~mask;
51 data |= (val & mask);
52 pci_write_config_byte(pci, reg, data);
53}
54
55static void skl_init_pci(struct skl *skl)
56{
57 struct hdac_ext_bus *ebus = &skl->ebus;
58
59 /*
60 * Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
61 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
62 * Ensuring these bits are 0 clears playback static on some HD Audio
63 * codecs.
64 * The PCI register TCSEL is defined in the Intel manuals.
65 */
66 dev_dbg(ebus_to_hbus(ebus)->dev, "Clearing TCSEL\n");
67 skl_update_pci_byte(skl->pci, AZX_PCIREG_TCSEL, 0x07, 0);
68}
69
70static void update_pci_dword(struct pci_dev *pci,
71 unsigned int reg, u32 mask, u32 val)
72{
73 u32 data = 0;
74
75 pci_read_config_dword(pci, reg, &data);
76 data &= ~mask;
77 data |= (val & mask);
78 pci_write_config_dword(pci, reg, data);
79}
80
81/*
82 * skl_enable_miscbdcge - enable/dsiable CGCTL.MISCBDCGE bits
83 *
84 * @dev: device pointer
85 * @enable: enable/disable flag
86 */
87static void skl_enable_miscbdcge(struct device *dev, bool enable)
88{
89 struct pci_dev *pci = to_pci_dev(dev);
90 u32 val;
91
92 val = enable ? AZX_CGCTL_MISCBDCGE_MASK : 0;
93
94 update_pci_dword(pci, AZX_PCIREG_CGCTL, AZX_CGCTL_MISCBDCGE_MASK, val);
95}
96
97/*
98 * While performing reset, controller may not come back properly causing
99 * issues, so recommendation is to set CGCTL.MISCBDCGE to 0 then do reset
100 * (init chip) and then again set CGCTL.MISCBDCGE to 1
101 */
102static int skl_init_chip(struct hdac_bus *bus, bool full_reset)
103{
104 int ret;
105
106 skl_enable_miscbdcge(bus->dev, false);
107 ret = snd_hdac_bus_init_chip(bus, full_reset);
108 skl_enable_miscbdcge(bus->dev, true);
109
110 return ret;
111}
112
113void skl_update_d0i3c(struct device *dev, bool enable)
114{
115 struct pci_dev *pci = to_pci_dev(dev);
116 struct hdac_ext_bus *ebus = pci_get_drvdata(pci);
117 struct hdac_bus *bus = ebus_to_hbus(ebus);
118 u8 reg;
119 int timeout = 50;
120
121 reg = snd_hdac_chip_readb(bus, VS_D0I3C);
122 /* Do not write to D0I3C until command in progress bit is cleared */
123 while ((reg & AZX_REG_VS_D0I3C_CIP) && --timeout) {
124 udelay(10);
125 reg = snd_hdac_chip_readb(bus, VS_D0I3C);
126 }
127
128 /* Highly unlikely. But if it happens, flag error explicitly */
129 if (!timeout) {
130 dev_err(bus->dev, "Before D0I3C update: D0I3C CIP timeout\n");
131 return;
132 }
133
134 if (enable)
135 reg = reg | AZX_REG_VS_D0I3C_I3;
136 else
137 reg = reg & (~AZX_REG_VS_D0I3C_I3);
138
139 snd_hdac_chip_writeb(bus, VS_D0I3C, reg);
140
141 timeout = 50;
142 /* Wait for cmd in progress to be cleared before exiting the function */
143 reg = snd_hdac_chip_readb(bus, VS_D0I3C);
144 while ((reg & AZX_REG_VS_D0I3C_CIP) && --timeout) {
145 udelay(10);
146 reg = snd_hdac_chip_readb(bus, VS_D0I3C);
147 }
148
149 /* Highly unlikely. But if it happens, flag error explicitly */
150 if (!timeout) {
151 dev_err(bus->dev, "After D0I3C update: D0I3C CIP timeout\n");
152 return;
153 }
154
155 dev_dbg(bus->dev, "D0I3C register = 0x%x\n",
156 snd_hdac_chip_readb(bus, VS_D0I3C));
157}
158
159/* called from IRQ */
160static void skl_stream_update(struct hdac_bus *bus, struct hdac_stream *hstr)
161{
162 snd_pcm_period_elapsed(hstr->substream);
163}
164
165static irqreturn_t skl_interrupt(int irq, void *dev_id)
166{
167 struct hdac_ext_bus *ebus = dev_id;
168 struct hdac_bus *bus = ebus_to_hbus(ebus);
169 u32 status;
170
171 if (!pm_runtime_active(bus->dev))
172 return IRQ_NONE;
173
174 spin_lock(&bus->reg_lock);
175
176 status = snd_hdac_chip_readl(bus, INTSTS);
177 if (status == 0 || status == 0xffffffff) {
178 spin_unlock(&bus->reg_lock);
179 return IRQ_NONE;
180 }
181
182 /* clear rirb int */
183 status = snd_hdac_chip_readb(bus, RIRBSTS);
184 if (status & RIRB_INT_MASK) {
185 if (status & RIRB_INT_RESPONSE)
186 snd_hdac_bus_update_rirb(bus);
187 snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK);
188 }
189
190 spin_unlock(&bus->reg_lock);
191
192 return snd_hdac_chip_readl(bus, INTSTS) ? IRQ_WAKE_THREAD : IRQ_HANDLED;
193}
194
195static irqreturn_t skl_threaded_handler(int irq, void *dev_id)
196{
197 struct hdac_ext_bus *ebus = dev_id;
198 struct hdac_bus *bus = ebus_to_hbus(ebus);
199 u32 status;
200
201 status = snd_hdac_chip_readl(bus, INTSTS);
202
203 snd_hdac_bus_handle_stream_irq(bus, status, skl_stream_update);
204
205 return IRQ_HANDLED;
206}
207
208static int skl_acquire_irq(struct hdac_ext_bus *ebus, int do_disconnect)
209{
210 struct skl *skl = ebus_to_skl(ebus);
211 struct hdac_bus *bus = ebus_to_hbus(ebus);
212 int ret;
213
214 ret = request_threaded_irq(skl->pci->irq, skl_interrupt,
215 skl_threaded_handler,
216 IRQF_SHARED,
217 KBUILD_MODNAME, ebus);
218 if (ret) {
219 dev_err(bus->dev,
220 "unable to grab IRQ %d, disabling device\n",
221 skl->pci->irq);
222 return ret;
223 }
224
225 bus->irq = skl->pci->irq;
226 pci_intx(skl->pci, 1);
227
228 return 0;
229}
230
231static int skl_suspend_late(struct device *dev)
232{
233 struct pci_dev *pci = to_pci_dev(dev);
234 struct hdac_ext_bus *ebus = pci_get_drvdata(pci);
235 struct skl *skl = ebus_to_skl(ebus);
236
237 return skl_suspend_late_dsp(skl);
238}
239
240#ifdef CONFIG_PM
241static int _skl_suspend(struct hdac_ext_bus *ebus)
242{
243 struct skl *skl = ebus_to_skl(ebus);
244 struct hdac_bus *bus = ebus_to_hbus(ebus);
245 struct pci_dev *pci = to_pci_dev(bus->dev);
246 int ret;
247
248 snd_hdac_ext_bus_link_power_down_all(ebus);
249
250 ret = skl_suspend_dsp(skl);
251 if (ret < 0)
252 return ret;
253
254 snd_hdac_bus_stop_chip(bus);
255 update_pci_dword(pci, AZX_PCIREG_PGCTL,
256 AZX_PGCTL_LSRMD_MASK, AZX_PGCTL_LSRMD_MASK);
257 skl_enable_miscbdcge(bus->dev, false);
258 snd_hdac_bus_enter_link_reset(bus);
259 skl_enable_miscbdcge(bus->dev, true);
260 skl_cleanup_resources(skl);
261
262 return 0;
263}
264
265static int _skl_resume(struct hdac_ext_bus *ebus)
266{
267 struct skl *skl = ebus_to_skl(ebus);
268 struct hdac_bus *bus = ebus_to_hbus(ebus);
269
270 skl_init_pci(skl);
271 skl_init_chip(bus, true);
272
273 return skl_resume_dsp(skl);
274}
275#endif
276
277#ifdef CONFIG_PM_SLEEP
278/*
279 * power management
280 */
281static int skl_suspend(struct device *dev)
282{
283 struct pci_dev *pci = to_pci_dev(dev);
284 struct hdac_ext_bus *ebus = pci_get_drvdata(pci);
285 struct skl *skl = ebus_to_skl(ebus);
286 struct hdac_bus *bus = ebus_to_hbus(ebus);
287 int ret = 0;
288
289 /*
290 * Do not suspend if streams which are marked ignore suspend are
291 * running, we need to save the state for these and continue
292 */
293 if (skl->supend_active) {
294 /* turn off the links and stop the CORB/RIRB DMA if it is On */
295 snd_hdac_ext_bus_link_power_down_all(ebus);
296
297 if (ebus->cmd_dma_state)
298 snd_hdac_bus_stop_cmd_io(&ebus->bus);
299
300 enable_irq_wake(bus->irq);
301 pci_save_state(pci);
302 } else {
303 ret = _skl_suspend(ebus);
304 if (ret < 0)
305 return ret;
306 skl->skl_sst->fw_loaded = false;
307 }
308
309 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) {
310 ret = snd_hdac_display_power(bus, false);
311 if (ret < 0)
312 dev_err(bus->dev,
313 "Cannot turn OFF display power on i915\n");
314 }
315
316 return ret;
317}
318
319static int skl_resume(struct device *dev)
320{
321 struct pci_dev *pci = to_pci_dev(dev);
322 struct hdac_ext_bus *ebus = pci_get_drvdata(pci);
323 struct skl *skl = ebus_to_skl(ebus);
324 struct hdac_bus *bus = ebus_to_hbus(ebus);
325 struct hdac_ext_link *hlink = NULL;
326 int ret;
327
328 /* Turned OFF in HDMI codec driver after codec reconfiguration */
329 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) {
330 ret = snd_hdac_display_power(bus, true);
331 if (ret < 0) {
332 dev_err(bus->dev,
333 "Cannot turn on display power on i915\n");
334 return ret;
335 }
336 }
337
338 /*
339 * resume only when we are not in suspend active, otherwise need to
340 * restore the device
341 */
342 if (skl->supend_active) {
343 pci_restore_state(pci);
344 snd_hdac_ext_bus_link_power_up_all(ebus);
345 disable_irq_wake(bus->irq);
346 /*
347 * turn On the links which are On before active suspend
348 * and start the CORB/RIRB DMA if On before
349 * active suspend.
350 */
351 list_for_each_entry(hlink, &ebus->hlink_list, list) {
352 if (hlink->ref_count)
353 snd_hdac_ext_bus_link_power_up(hlink);
354 }
355
356 if (ebus->cmd_dma_state)
357 snd_hdac_bus_init_cmd_io(&ebus->bus);
358 } else {
359 ret = _skl_resume(ebus);
360
361 /* turn off the links which are off before suspend */
362 list_for_each_entry(hlink, &ebus->hlink_list, list) {
363 if (!hlink->ref_count)
364 snd_hdac_ext_bus_link_power_down(hlink);
365 }
366
367 if (!ebus->cmd_dma_state)
368 snd_hdac_bus_stop_cmd_io(&ebus->bus);
369 }
370
371 return ret;
372}
373#endif /* CONFIG_PM_SLEEP */
374
375#ifdef CONFIG_PM
376static int skl_runtime_suspend(struct device *dev)
377{
378 struct pci_dev *pci = to_pci_dev(dev);
379 struct hdac_ext_bus *ebus = pci_get_drvdata(pci);
380 struct hdac_bus *bus = ebus_to_hbus(ebus);
381
382 dev_dbg(bus->dev, "in %s\n", __func__);
383
384 return _skl_suspend(ebus);
385}
386
387static int skl_runtime_resume(struct device *dev)
388{
389 struct pci_dev *pci = to_pci_dev(dev);
390 struct hdac_ext_bus *ebus = pci_get_drvdata(pci);
391 struct hdac_bus *bus = ebus_to_hbus(ebus);
392
393 dev_dbg(bus->dev, "in %s\n", __func__);
394
395 return _skl_resume(ebus);
396}
397#endif /* CONFIG_PM */
398
399static const struct dev_pm_ops skl_pm = {
400 SET_SYSTEM_SLEEP_PM_OPS(skl_suspend, skl_resume)
401 SET_RUNTIME_PM_OPS(skl_runtime_suspend, skl_runtime_resume, NULL)
402 .suspend_late = skl_suspend_late,
403};
404
405/*
406 * destructor
407 */
408static int skl_free(struct hdac_ext_bus *ebus)
409{
410 struct skl *skl = ebus_to_skl(ebus);
411 struct hdac_bus *bus = ebus_to_hbus(ebus);
412
413 skl->init_failed = 1; /* to be sure */
414
415 snd_hdac_ext_stop_streams(ebus);
416
417 if (bus->irq >= 0)
418 free_irq(bus->irq, (void *)bus);
419 snd_hdac_bus_free_stream_pages(bus);
420 snd_hdac_stream_free_all(ebus);
421 snd_hdac_link_free_all(ebus);
422
423 if (bus->remap_addr)
424 iounmap(bus->remap_addr);
425
426 pci_release_regions(skl->pci);
427 pci_disable_device(skl->pci);
428
429 snd_hdac_ext_bus_exit(ebus);
430
431 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI))
432 snd_hdac_i915_exit(&ebus->bus);
433 return 0;
434}
435
436static int skl_machine_device_register(struct skl *skl, void *driver_data)
437{
438 struct hdac_bus *bus = ebus_to_hbus(&skl->ebus);
439 struct platform_device *pdev;
440 struct sst_acpi_mach *mach = driver_data;
441 int ret;
442
443 mach = sst_acpi_find_machine(mach);
444 if (mach == NULL) {
445 dev_err(bus->dev, "No matching machine driver found\n");
446 return -ENODEV;
447 }
448 skl->fw_name = mach->fw_filename;
449
450 pdev = platform_device_alloc(mach->drv_name, -1);
451 if (pdev == NULL) {
452 dev_err(bus->dev, "platform device alloc failed\n");
453 return -EIO;
454 }
455
456 ret = platform_device_add(pdev);
457 if (ret) {
458 dev_err(bus->dev, "failed to add machine device\n");
459 platform_device_put(pdev);
460 return -EIO;
461 }
462
463 if (mach->pdata)
464 dev_set_drvdata(&pdev->dev, mach->pdata);
465
466 skl->i2s_dev = pdev;
467
468 return 0;
469}
470
471static void skl_machine_device_unregister(struct skl *skl)
472{
473 if (skl->i2s_dev)
474 platform_device_unregister(skl->i2s_dev);
475}
476
477static int skl_dmic_device_register(struct skl *skl)
478{
479 struct hdac_bus *bus = ebus_to_hbus(&skl->ebus);
480 struct platform_device *pdev;
481 int ret;
482
483 /* SKL has one dmic port, so allocate dmic device for this */
484 pdev = platform_device_alloc("dmic-codec", -1);
485 if (!pdev) {
486 dev_err(bus->dev, "failed to allocate dmic device\n");
487 return -ENOMEM;
488 }
489
490 ret = platform_device_add(pdev);
491 if (ret) {
492 dev_err(bus->dev, "failed to add dmic device: %d\n", ret);
493 platform_device_put(pdev);
494 return ret;
495 }
496 skl->dmic_dev = pdev;
497
498 return 0;
499}
500
501static void skl_dmic_device_unregister(struct skl *skl)
502{
503 if (skl->dmic_dev)
504 platform_device_unregister(skl->dmic_dev);
505}
506
507/*
508 * Probe the given codec address
509 */
510static int probe_codec(struct hdac_ext_bus *ebus, int addr)
511{
512 struct hdac_bus *bus = ebus_to_hbus(ebus);
513 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
514 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
515 unsigned int res;
516
517 mutex_lock(&bus->cmd_mutex);
518 snd_hdac_bus_send_cmd(bus, cmd);
519 snd_hdac_bus_get_response(bus, addr, &res);
520 mutex_unlock(&bus->cmd_mutex);
521 if (res == -1)
522 return -EIO;
523 dev_dbg(bus->dev, "codec #%d probed OK\n", addr);
524
525 return snd_hdac_ext_bus_device_init(ebus, addr);
526}
527
528/* Codec initialization */
529static int skl_codec_create(struct hdac_ext_bus *ebus)
530{
531 struct hdac_bus *bus = ebus_to_hbus(ebus);
532 int c, max_slots;
533
534 max_slots = HDA_MAX_CODECS;
535
536 /* First try to probe all given codec slots */
537 for (c = 0; c < max_slots; c++) {
538 if ((bus->codec_mask & (1 << c))) {
539 if (probe_codec(ebus, c) < 0) {
540 /*
541 * Some BIOSen give you wrong codec addresses
542 * that don't exist
543 */
544 dev_warn(bus->dev,
545 "Codec #%d probe error; disabling it...\n", c);
546 bus->codec_mask &= ~(1 << c);
547 /*
548 * More badly, accessing to a non-existing
549 * codec often screws up the controller bus,
550 * and disturbs the further communications.
551 * Thus if an error occurs during probing,
552 * better to reset the controller bus to get
553 * back to the sanity state.
554 */
555 snd_hdac_bus_stop_chip(bus);
556 skl_init_chip(bus, true);
557 }
558 }
559 }
560
561 return 0;
562}
563
564static const struct hdac_bus_ops bus_core_ops = {
565 .command = snd_hdac_bus_send_cmd,
566 .get_response = snd_hdac_bus_get_response,
567};
568
569/*
570 * constructor
571 */
572static int skl_create(struct pci_dev *pci,
573 const struct hdac_io_ops *io_ops,
574 struct skl **rskl)
575{
576 struct skl *skl;
577 struct hdac_ext_bus *ebus;
578
579 int err;
580
581 *rskl = NULL;
582
583 err = pci_enable_device(pci);
584 if (err < 0)
585 return err;
586
587 skl = devm_kzalloc(&pci->dev, sizeof(*skl), GFP_KERNEL);
588 if (!skl) {
589 pci_disable_device(pci);
590 return -ENOMEM;
591 }
592 ebus = &skl->ebus;
593 snd_hdac_ext_bus_init(ebus, &pci->dev, &bus_core_ops, io_ops);
594 ebus->bus.use_posbuf = 1;
595 skl->pci = pci;
596
597 ebus->bus.bdl_pos_adj = 0;
598
599 *rskl = skl;
600
601 return 0;
602}
603
604static int skl_i915_init(struct hdac_bus *bus)
605{
606 int err;
607
608 /*
609 * The HDMI codec is in GPU so we need to ensure that it is powered
610 * up and ready for probe
611 */
612 err = snd_hdac_i915_init(bus);
613 if (err < 0)
614 return err;
615
616 err = snd_hdac_display_power(bus, true);
617 if (err < 0) {
618 dev_err(bus->dev, "Cannot turn on display power on i915\n");
619 return err;
620 }
621
622 return err;
623}
624
625static int skl_first_init(struct hdac_ext_bus *ebus)
626{
627 struct skl *skl = ebus_to_skl(ebus);
628 struct hdac_bus *bus = ebus_to_hbus(ebus);
629 struct pci_dev *pci = skl->pci;
630 int err;
631 unsigned short gcap;
632 int cp_streams, pb_streams, start_idx;
633
634 err = pci_request_regions(pci, "Skylake HD audio");
635 if (err < 0)
636 return err;
637
638 bus->addr = pci_resource_start(pci, 0);
639 bus->remap_addr = pci_ioremap_bar(pci, 0);
640 if (bus->remap_addr == NULL) {
641 dev_err(bus->dev, "ioremap error\n");
642 return -ENXIO;
643 }
644
645 snd_hdac_bus_parse_capabilities(bus);
646
647 if (skl_acquire_irq(ebus, 0) < 0)
648 return -EBUSY;
649
650 pci_set_master(pci);
651 synchronize_irq(bus->irq);
652
653 gcap = snd_hdac_chip_readw(bus, GCAP);
654 dev_dbg(bus->dev, "chipset global capabilities = 0x%x\n", gcap);
655
656 /* allow 64bit DMA address if supported by H/W */
657 if (!dma_set_mask(bus->dev, DMA_BIT_MASK(64))) {
658 dma_set_coherent_mask(bus->dev, DMA_BIT_MASK(64));
659 } else {
660 dma_set_mask(bus->dev, DMA_BIT_MASK(32));
661 dma_set_coherent_mask(bus->dev, DMA_BIT_MASK(32));
662 }
663
664 /* read number of streams from GCAP register */
665 cp_streams = (gcap >> 8) & 0x0f;
666 pb_streams = (gcap >> 12) & 0x0f;
667
668 if (!pb_streams && !cp_streams)
669 return -EIO;
670
671 ebus->num_streams = cp_streams + pb_streams;
672
673 /* initialize streams */
674 snd_hdac_ext_stream_init_all
675 (ebus, 0, cp_streams, SNDRV_PCM_STREAM_CAPTURE);
676 start_idx = cp_streams;
677 snd_hdac_ext_stream_init_all
678 (ebus, start_idx, pb_streams, SNDRV_PCM_STREAM_PLAYBACK);
679
680 err = snd_hdac_bus_alloc_stream_pages(bus);
681 if (err < 0)
682 return err;
683
684 /* initialize chip */
685 skl_init_pci(skl);
686
687 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) {
688 err = skl_i915_init(bus);
689 if (err < 0)
690 return err;
691 }
692
693 skl_init_chip(bus, true);
694
695 /* codec detection */
696 if (!bus->codec_mask) {
697 dev_info(bus->dev, "no hda codecs found!\n");
698 }
699
700 return 0;
701}
702
703static int skl_probe(struct pci_dev *pci,
704 const struct pci_device_id *pci_id)
705{
706 struct skl *skl;
707 struct hdac_ext_bus *ebus = NULL;
708 struct hdac_bus *bus = NULL;
709 struct hdac_ext_link *hlink = NULL;
710 int err;
711
712 /* we use ext core ops, so provide NULL for ops here */
713 err = skl_create(pci, NULL, &skl);
714 if (err < 0)
715 return err;
716
717 ebus = &skl->ebus;
718 bus = ebus_to_hbus(ebus);
719
720 err = skl_first_init(ebus);
721 if (err < 0)
722 goto out_free;
723
724 skl->pci_id = pci->device;
725
726 device_disable_async_suspend(bus->dev);
727
728 skl->nhlt = skl_nhlt_init(bus->dev);
729
730 if (skl->nhlt == NULL) {
731 err = -ENODEV;
732 goto out_display_power_off;
733 }
734
735 skl_nhlt_update_topology_bin(skl);
736
737 pci_set_drvdata(skl->pci, ebus);
738
739 skl_dmic_data.dmic_num = skl_get_dmic_geo(skl);
740
741 /* check if dsp is there */
742 if (bus->ppcap) {
743 err = skl_machine_device_register(skl,
744 (void *)pci_id->driver_data);
745 if (err < 0)
746 goto out_nhlt_free;
747
748 err = skl_init_dsp(skl);
749 if (err < 0) {
750 dev_dbg(bus->dev, "error failed to register dsp\n");
751 goto out_mach_free;
752 }
753 skl->skl_sst->enable_miscbdcge = skl_enable_miscbdcge;
754
755 }
756 if (bus->mlcap)
757 snd_hdac_ext_bus_get_ml_capabilities(ebus);
758
759 /* create device for soc dmic */
760 err = skl_dmic_device_register(skl);
761 if (err < 0)
762 goto out_dsp_free;
763
764 /* register platform dai and controls */
765 err = skl_platform_register(bus->dev);
766 if (err < 0)
767 goto out_dmic_free;
768
769 /* create codec instances */
770 err = skl_codec_create(ebus);
771 if (err < 0)
772 goto out_unregister;
773
774 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) {
775 err = snd_hdac_display_power(bus, false);
776 if (err < 0) {
777 dev_err(bus->dev, "Cannot turn off display power on i915\n");
778 return err;
779 }
780 }
781
782 /*
783 * we are done probling so decrement link counts
784 */
785 list_for_each_entry(hlink, &ebus->hlink_list, list)
786 snd_hdac_ext_bus_link_put(ebus, hlink);
787
788 /* configure PM */
789 pm_runtime_put_noidle(bus->dev);
790 pm_runtime_allow(bus->dev);
791
792 return 0;
793
794out_unregister:
795 skl_platform_unregister(bus->dev);
796out_dmic_free:
797 skl_dmic_device_unregister(skl);
798out_dsp_free:
799 skl_free_dsp(skl);
800out_mach_free:
801 skl_machine_device_unregister(skl);
802out_nhlt_free:
803 skl_nhlt_free(skl->nhlt);
804out_display_power_off:
805 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI))
806 snd_hdac_display_power(bus, false);
807out_free:
808 skl->init_failed = 1;
809 skl_free(ebus);
810
811 return err;
812}
813
814static void skl_shutdown(struct pci_dev *pci)
815{
816 struct hdac_ext_bus *ebus = pci_get_drvdata(pci);
817 struct hdac_bus *bus = ebus_to_hbus(ebus);
818 struct hdac_stream *s;
819 struct hdac_ext_stream *stream;
820 struct skl *skl;
821
822 if (ebus == NULL)
823 return;
824
825 skl = ebus_to_skl(ebus);
826
827 if (skl->init_failed)
828 return;
829
830 snd_hdac_ext_stop_streams(ebus);
831 list_for_each_entry(s, &bus->stream_list, list) {
832 stream = stream_to_hdac_ext_stream(s);
833 snd_hdac_ext_stream_decouple(ebus, stream, false);
834 }
835
836 snd_hdac_bus_stop_chip(bus);
837}
838
839static void skl_remove(struct pci_dev *pci)
840{
841 struct hdac_ext_bus *ebus = pci_get_drvdata(pci);
842 struct skl *skl = ebus_to_skl(ebus);
843
844 release_firmware(skl->tplg);
845
846 pm_runtime_get_noresume(&pci->dev);
847
848 /* codec removal, invoke bus_device_remove */
849 snd_hdac_ext_bus_device_remove(ebus);
850
851 skl_platform_unregister(&pci->dev);
852 skl_free_dsp(skl);
853 skl_machine_device_unregister(skl);
854 skl_dmic_device_unregister(skl);
855 skl_nhlt_free(skl->nhlt);
856 skl_free(ebus);
857 dev_set_drvdata(&pci->dev, NULL);
858}
859
860static struct sst_acpi_mach sst_skl_devdata[] = {
861 { "INT343A", "skl_alc286s_i2s", "intel/dsp_fw_release.bin", NULL, NULL, NULL },
862 { "INT343B", "skl_n88l25_s4567", "intel/dsp_fw_release.bin",
863 NULL, NULL, &skl_dmic_data },
864 { "MX98357A", "skl_n88l25_m98357a", "intel/dsp_fw_release.bin",
865 NULL, NULL, &skl_dmic_data },
866 {}
867};
868
869static struct sst_acpi_mach sst_bxtp_devdata[] = {
870 { "INT343A", "bxt_alc298s_i2s", "intel/dsp_fw_bxtn.bin", NULL, NULL, NULL },
871 { "DLGS7219", "bxt_da7219_max98357a_i2s", "intel/dsp_fw_bxtn.bin", NULL, NULL, NULL },
872};
873
874static struct sst_acpi_mach sst_kbl_devdata[] = {
875 { "INT343A", "kbl_alc286s_i2s", "intel/dsp_fw_kbl.bin", NULL, NULL, NULL },
876 { "INT343B", "kbl_n88l25_s4567", "intel/dsp_fw_kbl.bin", NULL, NULL, &skl_dmic_data },
877 { "MX98357A", "kbl_n88l25_m98357a", "intel/dsp_fw_kbl.bin", NULL, NULL, &skl_dmic_data },
878 {}
879};
880
881/* PCI IDs */
882static const struct pci_device_id skl_ids[] = {
883 /* Sunrise Point-LP */
884 { PCI_DEVICE(0x8086, 0x9d70),
885 .driver_data = (unsigned long)&sst_skl_devdata},
886 /* BXT-P */
887 { PCI_DEVICE(0x8086, 0x5a98),
888 .driver_data = (unsigned long)&sst_bxtp_devdata},
889 /* KBL */
890 { PCI_DEVICE(0x8086, 0x9D71),
891 .driver_data = (unsigned long)&sst_kbl_devdata},
892 { 0, }
893};
894MODULE_DEVICE_TABLE(pci, skl_ids);
895
896/* pci_driver definition */
897static struct pci_driver skl_driver = {
898 .name = KBUILD_MODNAME,
899 .id_table = skl_ids,
900 .probe = skl_probe,
901 .remove = skl_remove,
902 .shutdown = skl_shutdown,
903 .driver = {
904 .pm = &skl_pm,
905 },
906};
907module_pci_driver(skl_driver);
908
909MODULE_LICENSE("GPL v2");
910MODULE_DESCRIPTION("Intel Skylake ASoC HDA driver");