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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Octeon Watchdog driver
4 *
5 * Copyright (C) 2007-2017 Cavium, Inc.
6 *
7 * Converted to use WATCHDOG_CORE by Aaro Koskinen <aaro.koskinen@iki.fi>.
8 *
9 * Some parts derived from wdt.c
10 *
11 * (c) Copyright 1996-1997 Alan Cox <alan@lxorguk.ukuu.org.uk>,
12 * All Rights Reserved.
13 *
14 * Neither Alan Cox nor CymruNet Ltd. admit liability nor provide
15 * warranty for any of this software. This material is provided
16 * "AS-IS" and at no charge.
17 *
18 * (c) Copyright 1995 Alan Cox <alan@lxorguk.ukuu.org.uk>
19 *
20 * The OCTEON watchdog has a maximum timeout of 2^32 * io_clock.
21 * For most systems this is less than 10 seconds, so to allow for
22 * software to request longer watchdog heartbeats, we maintain software
23 * counters to count multiples of the base rate. If the system locks
24 * up in such a manner that we can not run the software counters, the
25 * only result is a watchdog reset sooner than was requested. But
26 * that is OK, because in this case userspace would likely not be able
27 * to do anything anyhow.
28 *
29 * The hardware watchdog interval we call the period. The OCTEON
30 * watchdog goes through several stages, after the first period an
31 * irq is asserted, then if it is not reset, after the next period NMI
32 * is asserted, then after an additional period a chip wide soft reset.
33 * So for the software counters, we reset watchdog after each period
34 * and decrement the counter. But for the last two periods we need to
35 * let the watchdog progress to the NMI stage so we disable the irq
36 * and let it proceed. Once in the NMI, we print the register state
37 * to the serial port and then wait for the reset.
38 *
39 * A watchdog is maintained for each CPU in the system, that way if
40 * one CPU suffers a lockup, we also get a register dump and reset.
41 * The userspace ping resets the watchdog on all CPUs.
42 *
43 * Before userspace opens the watchdog device, we still run the
44 * watchdogs to catch any lockups that may be kernel related.
45 *
46 */
47
48#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
49
50#include <linux/interrupt.h>
51#include <linux/watchdog.h>
52#include <linux/cpumask.h>
53#include <linux/module.h>
54#include <linux/delay.h>
55#include <linux/cpu.h>
56#include <linux/irq.h>
57#include <linux/irqdomain.h>
58
59#include <asm/mipsregs.h>
60#include <asm/uasm.h>
61
62#include <asm/octeon/octeon.h>
63#include <asm/octeon/cvmx-boot-vector.h>
64#include <asm/octeon/cvmx-ciu2-defs.h>
65#include <asm/octeon/cvmx-rst-defs.h>
66
67/* Watchdog interrupt major block number (8 MSBs of intsn) */
68#define WD_BLOCK_NUMBER 0x01
69
70static int divisor;
71
72/* The count needed to achieve timeout_sec. */
73static unsigned int timeout_cnt;
74
75/* The maximum period supported. */
76static unsigned int max_timeout_sec;
77
78/* The current period. */
79static unsigned int timeout_sec;
80
81/* Set to non-zero when userspace countdown mode active */
82static bool do_countdown;
83static unsigned int countdown_reset;
84static unsigned int per_cpu_countdown[NR_CPUS];
85
86static cpumask_t irq_enabled_cpus;
87
88#define WD_TIMO 60 /* Default heartbeat = 60 seconds */
89
90#define CVMX_GSERX_SCRATCH(offset) (CVMX_ADD_IO_SEG(0x0001180090000020ull) + ((offset) & 15) * 0x1000000ull)
91
92static int heartbeat = WD_TIMO;
93module_param(heartbeat, int, 0444);
94MODULE_PARM_DESC(heartbeat,
95 "Watchdog heartbeat in seconds. (0 < heartbeat, default="
96 __MODULE_STRING(WD_TIMO) ")");
97
98static bool nowayout = WATCHDOG_NOWAYOUT;
99module_param(nowayout, bool, 0444);
100MODULE_PARM_DESC(nowayout,
101 "Watchdog cannot be stopped once started (default="
102 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
103
104static int disable;
105module_param(disable, int, 0444);
106MODULE_PARM_DESC(disable,
107 "Disable the watchdog entirely (default=0)");
108
109static struct cvmx_boot_vector_element *octeon_wdt_bootvector;
110
111void octeon_wdt_nmi_stage2(void);
112
113static int cpu2core(int cpu)
114{
115#ifdef CONFIG_SMP
116 return cpu_logical_map(cpu) & 0x3f;
117#else
118 return cvmx_get_core_num();
119#endif
120}
121
122/**
123 * octeon_wdt_poke_irq - Poke the watchdog when an interrupt is received
124 *
125 * @cpl:
126 * @dev_id:
127 *
128 * Returns
129 */
130static irqreturn_t octeon_wdt_poke_irq(int cpl, void *dev_id)
131{
132 int cpu = raw_smp_processor_id();
133 unsigned int core = cpu2core(cpu);
134 int node = cpu_to_node(cpu);
135
136 if (do_countdown) {
137 if (per_cpu_countdown[cpu] > 0) {
138 /* We're alive, poke the watchdog */
139 cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(core), 1);
140 per_cpu_countdown[cpu]--;
141 } else {
142 /* Bad news, you are about to reboot. */
143 disable_irq_nosync(cpl);
144 cpumask_clear_cpu(cpu, &irq_enabled_cpus);
145 }
146 } else {
147 /* Not open, just ping away... */
148 cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(core), 1);
149 }
150 return IRQ_HANDLED;
151}
152
153/* From setup.c */
154extern int prom_putchar(char c);
155
156/**
157 * octeon_wdt_write_string - Write a string to the uart
158 *
159 * @str: String to write
160 */
161static void octeon_wdt_write_string(const char *str)
162{
163 /* Just loop writing one byte at a time */
164 while (*str)
165 prom_putchar(*str++);
166}
167
168/**
169 * octeon_wdt_write_hex() - Write a hex number out of the uart
170 *
171 * @value: Number to display
172 * @digits: Number of digits to print (1 to 16)
173 */
174static void octeon_wdt_write_hex(u64 value, int digits)
175{
176 int d;
177 int v;
178
179 for (d = 0; d < digits; d++) {
180 v = (value >> ((digits - d - 1) * 4)) & 0xf;
181 if (v >= 10)
182 prom_putchar('a' + v - 10);
183 else
184 prom_putchar('0' + v);
185 }
186}
187
188static const char reg_name[][3] = {
189 "$0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
190 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
191 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
192 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
193};
194
195/**
196 * octeon_wdt_nmi_stage3:
197 *
198 * NMI stage 3 handler. NMIs are handled in the following manner:
199 * 1) The first NMI handler enables CVMSEG and transfers from
200 * the bootbus region into normal memory. It is careful to not
201 * destroy any registers.
202 * 2) The second stage handler uses CVMSEG to save the registers
203 * and create a stack for C code. It then calls the third level
204 * handler with one argument, a pointer to the register values.
205 * 3) The third, and final, level handler is the following C
206 * function that prints out some useful infomration.
207 *
208 * @reg: Pointer to register state before the NMI
209 */
210void octeon_wdt_nmi_stage3(u64 reg[32])
211{
212 u64 i;
213
214 unsigned int coreid = cvmx_get_core_num();
215 /*
216 * Save status and cause early to get them before any changes
217 * might happen.
218 */
219 u64 cp0_cause = read_c0_cause();
220 u64 cp0_status = read_c0_status();
221 u64 cp0_error_epc = read_c0_errorepc();
222 u64 cp0_epc = read_c0_epc();
223
224 /* Delay so output from all cores output is not jumbled together. */
225 udelay(85000 * coreid);
226
227 octeon_wdt_write_string("\r\n*** NMI Watchdog interrupt on Core 0x");
228 octeon_wdt_write_hex(coreid, 2);
229 octeon_wdt_write_string(" ***\r\n");
230 for (i = 0; i < 32; i++) {
231 octeon_wdt_write_string("\t");
232 octeon_wdt_write_string(reg_name[i]);
233 octeon_wdt_write_string("\t0x");
234 octeon_wdt_write_hex(reg[i], 16);
235 if (i & 1)
236 octeon_wdt_write_string("\r\n");
237 }
238 octeon_wdt_write_string("\terr_epc\t0x");
239 octeon_wdt_write_hex(cp0_error_epc, 16);
240
241 octeon_wdt_write_string("\tepc\t0x");
242 octeon_wdt_write_hex(cp0_epc, 16);
243 octeon_wdt_write_string("\r\n");
244
245 octeon_wdt_write_string("\tstatus\t0x");
246 octeon_wdt_write_hex(cp0_status, 16);
247 octeon_wdt_write_string("\tcause\t0x");
248 octeon_wdt_write_hex(cp0_cause, 16);
249 octeon_wdt_write_string("\r\n");
250
251 /* The CIU register is different for each Octeon model. */
252 if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
253 octeon_wdt_write_string("\tsrc_wd\t0x");
254 octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_SRC_PPX_IP2_WDOG(coreid)), 16);
255 octeon_wdt_write_string("\ten_wd\t0x");
256 octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_EN_PPX_IP2_WDOG(coreid)), 16);
257 octeon_wdt_write_string("\r\n");
258 octeon_wdt_write_string("\tsrc_rml\t0x");
259 octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_SRC_PPX_IP2_RML(coreid)), 16);
260 octeon_wdt_write_string("\ten_rml\t0x");
261 octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_EN_PPX_IP2_RML(coreid)), 16);
262 octeon_wdt_write_string("\r\n");
263 octeon_wdt_write_string("\tsum\t0x");
264 octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_SUM_PPX_IP2(coreid)), 16);
265 octeon_wdt_write_string("\r\n");
266 } else if (!octeon_has_feature(OCTEON_FEATURE_CIU3)) {
267 octeon_wdt_write_string("\tsum0\t0x");
268 octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU_INTX_SUM0(coreid * 2)), 16);
269 octeon_wdt_write_string("\ten0\t0x");
270 octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)), 16);
271 octeon_wdt_write_string("\r\n");
272 }
273
274 octeon_wdt_write_string("*** Chip soft reset soon ***\r\n");
275
276 /*
277 * G-30204: We must trigger a soft reset before watchdog
278 * does an incomplete job of doing it.
279 */
280 if (OCTEON_IS_OCTEON3() && !OCTEON_IS_MODEL(OCTEON_CN70XX)) {
281 u64 scr;
282 unsigned int node = cvmx_get_node_num();
283 unsigned int lcore = cvmx_get_local_core_num();
284 union cvmx_ciu_wdogx ciu_wdog;
285
286 /*
287 * Wait for other cores to print out information, but
288 * not too long. Do the soft reset before watchdog
289 * can trigger it.
290 */
291 do {
292 ciu_wdog.u64 = cvmx_read_csr_node(node, CVMX_CIU_WDOGX(lcore));
293 } while (ciu_wdog.s.cnt > 0x10000);
294
295 scr = cvmx_read_csr_node(0, CVMX_GSERX_SCRATCH(0));
296 scr |= 1 << 11; /* Indicate watchdog in bit 11 */
297 cvmx_write_csr_node(0, CVMX_GSERX_SCRATCH(0), scr);
298 cvmx_write_csr_node(0, CVMX_RST_SOFT_RST, 1);
299 }
300}
301
302static int octeon_wdt_cpu_to_irq(int cpu)
303{
304 unsigned int coreid;
305 int node;
306 int irq;
307
308 coreid = cpu2core(cpu);
309 node = cpu_to_node(cpu);
310
311 if (octeon_has_feature(OCTEON_FEATURE_CIU3)) {
312 struct irq_domain *domain;
313 int hwirq;
314
315 domain = octeon_irq_get_block_domain(node,
316 WD_BLOCK_NUMBER);
317 hwirq = WD_BLOCK_NUMBER << 12 | 0x200 | coreid;
318 irq = irq_find_mapping(domain, hwirq);
319 } else {
320 irq = OCTEON_IRQ_WDOG0 + coreid;
321 }
322 return irq;
323}
324
325static int octeon_wdt_cpu_pre_down(unsigned int cpu)
326{
327 unsigned int core;
328 int node;
329 union cvmx_ciu_wdogx ciu_wdog;
330
331 core = cpu2core(cpu);
332
333 node = cpu_to_node(cpu);
334
335 /* Poke the watchdog to clear out its state */
336 cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(core), 1);
337
338 /* Disable the hardware. */
339 ciu_wdog.u64 = 0;
340 cvmx_write_csr_node(node, CVMX_CIU_WDOGX(core), ciu_wdog.u64);
341
342 free_irq(octeon_wdt_cpu_to_irq(cpu), octeon_wdt_poke_irq);
343 return 0;
344}
345
346static int octeon_wdt_cpu_online(unsigned int cpu)
347{
348 unsigned int core;
349 unsigned int irq;
350 union cvmx_ciu_wdogx ciu_wdog;
351 int node;
352 struct irq_domain *domain;
353 int hwirq;
354
355 core = cpu2core(cpu);
356 node = cpu_to_node(cpu);
357
358 octeon_wdt_bootvector[core].target_ptr = (u64)octeon_wdt_nmi_stage2;
359
360 /* Disable it before doing anything with the interrupts. */
361 ciu_wdog.u64 = 0;
362 cvmx_write_csr_node(node, CVMX_CIU_WDOGX(core), ciu_wdog.u64);
363
364 per_cpu_countdown[cpu] = countdown_reset;
365
366 if (octeon_has_feature(OCTEON_FEATURE_CIU3)) {
367 /* Must get the domain for the watchdog block */
368 domain = octeon_irq_get_block_domain(node, WD_BLOCK_NUMBER);
369
370 /* Get a irq for the wd intsn (hardware interrupt) */
371 hwirq = WD_BLOCK_NUMBER << 12 | 0x200 | core;
372 irq = irq_create_mapping(domain, hwirq);
373 irqd_set_trigger_type(irq_get_irq_data(irq),
374 IRQ_TYPE_EDGE_RISING);
375 } else
376 irq = OCTEON_IRQ_WDOG0 + core;
377
378 if (request_irq(irq, octeon_wdt_poke_irq,
379 IRQF_NO_THREAD, "octeon_wdt", octeon_wdt_poke_irq))
380 panic("octeon_wdt: Couldn't obtain irq %d", irq);
381
382 /* Must set the irq affinity here */
383 if (octeon_has_feature(OCTEON_FEATURE_CIU3)) {
384 irq_set_affinity(irq, cpumask_of(cpu));
385 }
386
387 cpumask_set_cpu(cpu, &irq_enabled_cpus);
388
389 /* Poke the watchdog to clear out its state */
390 cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(core), 1);
391
392 /* Finally enable the watchdog now that all handlers are installed */
393 ciu_wdog.u64 = 0;
394 ciu_wdog.s.len = timeout_cnt;
395 ciu_wdog.s.mode = 3; /* 3 = Interrupt + NMI + Soft-Reset */
396 cvmx_write_csr_node(node, CVMX_CIU_WDOGX(core), ciu_wdog.u64);
397
398 return 0;
399}
400
401static int octeon_wdt_ping(struct watchdog_device __always_unused *wdog)
402{
403 int cpu;
404 int coreid;
405 int node;
406
407 if (disable)
408 return 0;
409
410 for_each_online_cpu(cpu) {
411 coreid = cpu2core(cpu);
412 node = cpu_to_node(cpu);
413 cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(coreid), 1);
414 per_cpu_countdown[cpu] = countdown_reset;
415 if ((countdown_reset || !do_countdown) &&
416 !cpumask_test_cpu(cpu, &irq_enabled_cpus)) {
417 /* We have to enable the irq */
418 enable_irq(octeon_wdt_cpu_to_irq(cpu));
419 cpumask_set_cpu(cpu, &irq_enabled_cpus);
420 }
421 }
422 return 0;
423}
424
425static void octeon_wdt_calc_parameters(int t)
426{
427 unsigned int periods;
428
429 timeout_sec = max_timeout_sec;
430
431
432 /*
433 * Find the largest interrupt period, that can evenly divide
434 * the requested heartbeat time.
435 */
436 while ((t % timeout_sec) != 0)
437 timeout_sec--;
438
439 periods = t / timeout_sec;
440
441 /*
442 * The last two periods are after the irq is disabled, and
443 * then to the nmi, so we subtract them off.
444 */
445
446 countdown_reset = periods > 2 ? periods - 2 : 0;
447 heartbeat = t;
448 timeout_cnt = ((octeon_get_io_clock_rate() / divisor) * timeout_sec) >> 8;
449}
450
451static int octeon_wdt_set_timeout(struct watchdog_device *wdog,
452 unsigned int t)
453{
454 int cpu;
455 int coreid;
456 union cvmx_ciu_wdogx ciu_wdog;
457 int node;
458
459 if (t <= 0)
460 return -1;
461
462 octeon_wdt_calc_parameters(t);
463
464 if (disable)
465 return 0;
466
467 for_each_online_cpu(cpu) {
468 coreid = cpu2core(cpu);
469 node = cpu_to_node(cpu);
470 cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(coreid), 1);
471 ciu_wdog.u64 = 0;
472 ciu_wdog.s.len = timeout_cnt;
473 ciu_wdog.s.mode = 3; /* 3 = Interrupt + NMI + Soft-Reset */
474 cvmx_write_csr_node(node, CVMX_CIU_WDOGX(coreid), ciu_wdog.u64);
475 cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(coreid), 1);
476 }
477 octeon_wdt_ping(wdog); /* Get the irqs back on. */
478 return 0;
479}
480
481static int octeon_wdt_start(struct watchdog_device *wdog)
482{
483 octeon_wdt_ping(wdog);
484 do_countdown = 1;
485 return 0;
486}
487
488static int octeon_wdt_stop(struct watchdog_device *wdog)
489{
490 do_countdown = 0;
491 octeon_wdt_ping(wdog);
492 return 0;
493}
494
495static const struct watchdog_info octeon_wdt_info = {
496 .options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING,
497 .identity = "OCTEON",
498};
499
500static const struct watchdog_ops octeon_wdt_ops = {
501 .owner = THIS_MODULE,
502 .start = octeon_wdt_start,
503 .stop = octeon_wdt_stop,
504 .ping = octeon_wdt_ping,
505 .set_timeout = octeon_wdt_set_timeout,
506};
507
508static struct watchdog_device octeon_wdt = {
509 .info = &octeon_wdt_info,
510 .ops = &octeon_wdt_ops,
511};
512
513static enum cpuhp_state octeon_wdt_online;
514/**
515 * octeon_wdt_init - Module/ driver initialization.
516 *
517 * Returns Zero on success
518 */
519static int __init octeon_wdt_init(void)
520{
521 int ret;
522
523 octeon_wdt_bootvector = cvmx_boot_vector_get();
524 if (!octeon_wdt_bootvector) {
525 pr_err("Error: Cannot allocate boot vector.\n");
526 return -ENOMEM;
527 }
528
529 if (OCTEON_IS_MODEL(OCTEON_CN68XX))
530 divisor = 0x200;
531 else if (OCTEON_IS_MODEL(OCTEON_CN78XX))
532 divisor = 0x400;
533 else
534 divisor = 0x100;
535
536 /*
537 * Watchdog time expiration length = The 16 bits of LEN
538 * represent the most significant bits of a 24 bit decrementer
539 * that decrements every divisor cycle.
540 *
541 * Try for a timeout of 5 sec, if that fails a smaller number
542 * of even seconds,
543 */
544 max_timeout_sec = 6;
545 do {
546 max_timeout_sec--;
547 timeout_cnt = ((octeon_get_io_clock_rate() / divisor) * max_timeout_sec) >> 8;
548 } while (timeout_cnt > 65535);
549
550 BUG_ON(timeout_cnt == 0);
551
552 octeon_wdt_calc_parameters(heartbeat);
553
554 pr_info("Initial granularity %d Sec\n", timeout_sec);
555
556 octeon_wdt.timeout = timeout_sec;
557 octeon_wdt.max_timeout = UINT_MAX;
558
559 watchdog_set_nowayout(&octeon_wdt, nowayout);
560
561 ret = watchdog_register_device(&octeon_wdt);
562 if (ret)
563 return ret;
564
565 if (disable) {
566 pr_notice("disabled\n");
567 return 0;
568 }
569
570 cpumask_clear(&irq_enabled_cpus);
571
572 ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "watchdog/octeon:online",
573 octeon_wdt_cpu_online, octeon_wdt_cpu_pre_down);
574 if (ret < 0)
575 goto err;
576 octeon_wdt_online = ret;
577 return 0;
578err:
579 cvmx_write_csr(CVMX_MIO_BOOT_LOC_CFGX(0), 0);
580 watchdog_unregister_device(&octeon_wdt);
581 return ret;
582}
583
584/**
585 * octeon_wdt_cleanup - Module / driver shutdown
586 */
587static void __exit octeon_wdt_cleanup(void)
588{
589 watchdog_unregister_device(&octeon_wdt);
590
591 if (disable)
592 return;
593
594 cpuhp_remove_state(octeon_wdt_online);
595
596 /*
597 * Disable the boot-bus memory, the code it points to is soon
598 * to go missing.
599 */
600 cvmx_write_csr(CVMX_MIO_BOOT_LOC_CFGX(0), 0);
601}
602
603MODULE_LICENSE("GPL");
604MODULE_AUTHOR("Cavium Inc. <support@cavium.com>");
605MODULE_DESCRIPTION("Cavium Inc. OCTEON Watchdog driver.");
606module_init(octeon_wdt_init);
607module_exit(octeon_wdt_cleanup);
1/*
2 * Octeon Watchdog driver
3 *
4 * Copyright (C) 2007, 2008, 2009, 2010 Cavium Networks
5 *
6 * Converted to use WATCHDOG_CORE by Aaro Koskinen <aaro.koskinen@iki.fi>.
7 *
8 * Some parts derived from wdt.c
9 *
10 * (c) Copyright 1996-1997 Alan Cox <alan@lxorguk.ukuu.org.uk>,
11 * All Rights Reserved.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
17 *
18 * Neither Alan Cox nor CymruNet Ltd. admit liability nor provide
19 * warranty for any of this software. This material is provided
20 * "AS-IS" and at no charge.
21 *
22 * (c) Copyright 1995 Alan Cox <alan@lxorguk.ukuu.org.uk>
23 *
24 * This file is subject to the terms and conditions of the GNU General Public
25 * License. See the file "COPYING" in the main directory of this archive
26 * for more details.
27 *
28 *
29 * The OCTEON watchdog has a maximum timeout of 2^32 * io_clock.
30 * For most systems this is less than 10 seconds, so to allow for
31 * software to request longer watchdog heartbeats, we maintain software
32 * counters to count multiples of the base rate. If the system locks
33 * up in such a manner that we can not run the software counters, the
34 * only result is a watchdog reset sooner than was requested. But
35 * that is OK, because in this case userspace would likely not be able
36 * to do anything anyhow.
37 *
38 * The hardware watchdog interval we call the period. The OCTEON
39 * watchdog goes through several stages, after the first period an
40 * irq is asserted, then if it is not reset, after the next period NMI
41 * is asserted, then after an additional period a chip wide soft reset.
42 * So for the software counters, we reset watchdog after each period
43 * and decrement the counter. But for the last two periods we need to
44 * let the watchdog progress to the NMI stage so we disable the irq
45 * and let it proceed. Once in the NMI, we print the register state
46 * to the serial port and then wait for the reset.
47 *
48 * A watchdog is maintained for each CPU in the system, that way if
49 * one CPU suffers a lockup, we also get a register dump and reset.
50 * The userspace ping resets the watchdog on all CPUs.
51 *
52 * Before userspace opens the watchdog device, we still run the
53 * watchdogs to catch any lockups that may be kernel related.
54 *
55 */
56
57#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
58
59#include <linux/interrupt.h>
60#include <linux/watchdog.h>
61#include <linux/cpumask.h>
62#include <linux/bitops.h>
63#include <linux/kernel.h>
64#include <linux/module.h>
65#include <linux/string.h>
66#include <linux/delay.h>
67#include <linux/cpu.h>
68#include <linux/smp.h>
69#include <linux/fs.h>
70#include <linux/irq.h>
71
72#include <asm/mipsregs.h>
73#include <asm/uasm.h>
74
75#include <asm/octeon/octeon.h>
76
77/* The count needed to achieve timeout_sec. */
78static unsigned int timeout_cnt;
79
80/* The maximum period supported. */
81static unsigned int max_timeout_sec;
82
83/* The current period. */
84static unsigned int timeout_sec;
85
86/* Set to non-zero when userspace countdown mode active */
87static int do_coundown;
88static unsigned int countdown_reset;
89static unsigned int per_cpu_countdown[NR_CPUS];
90
91static cpumask_t irq_enabled_cpus;
92
93#define WD_TIMO 60 /* Default heartbeat = 60 seconds */
94
95static int heartbeat = WD_TIMO;
96module_param(heartbeat, int, S_IRUGO);
97MODULE_PARM_DESC(heartbeat,
98 "Watchdog heartbeat in seconds. (0 < heartbeat, default="
99 __MODULE_STRING(WD_TIMO) ")");
100
101static bool nowayout = WATCHDOG_NOWAYOUT;
102module_param(nowayout, bool, S_IRUGO);
103MODULE_PARM_DESC(nowayout,
104 "Watchdog cannot be stopped once started (default="
105 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
106
107static u32 nmi_stage1_insns[64] __initdata;
108/* We need one branch and therefore one relocation per target label. */
109static struct uasm_label labels[5] __initdata;
110static struct uasm_reloc relocs[5] __initdata;
111
112enum lable_id {
113 label_enter_bootloader = 1
114};
115
116/* Some CP0 registers */
117#define K0 26
118#define C0_CVMMEMCTL 11, 7
119#define C0_STATUS 12, 0
120#define C0_EBASE 15, 1
121#define C0_DESAVE 31, 0
122
123void octeon_wdt_nmi_stage2(void);
124
125static void __init octeon_wdt_build_stage1(void)
126{
127 int i;
128 int len;
129 u32 *p = nmi_stage1_insns;
130#ifdef CONFIG_HOTPLUG_CPU
131 struct uasm_label *l = labels;
132 struct uasm_reloc *r = relocs;
133#endif
134
135 /*
136 * For the next few instructions running the debugger may
137 * cause corruption of k0 in the saved registers. Since we're
138 * about to crash, nobody probably cares.
139 *
140 * Save K0 into the debug scratch register
141 */
142 uasm_i_dmtc0(&p, K0, C0_DESAVE);
143
144 uasm_i_mfc0(&p, K0, C0_STATUS);
145#ifdef CONFIG_HOTPLUG_CPU
146 if (octeon_bootloader_entry_addr)
147 uasm_il_bbit0(&p, &r, K0, ilog2(ST0_NMI),
148 label_enter_bootloader);
149#endif
150 /* Force 64-bit addressing enabled */
151 uasm_i_ori(&p, K0, K0, ST0_UX | ST0_SX | ST0_KX);
152 uasm_i_mtc0(&p, K0, C0_STATUS);
153
154#ifdef CONFIG_HOTPLUG_CPU
155 if (octeon_bootloader_entry_addr) {
156 uasm_i_mfc0(&p, K0, C0_EBASE);
157 /* Coreid number in K0 */
158 uasm_i_andi(&p, K0, K0, 0xf);
159 /* 8 * coreid in bits 16-31 */
160 uasm_i_dsll_safe(&p, K0, K0, 3 + 16);
161 uasm_i_ori(&p, K0, K0, 0x8001);
162 uasm_i_dsll_safe(&p, K0, K0, 16);
163 uasm_i_ori(&p, K0, K0, 0x0700);
164 uasm_i_drotr_safe(&p, K0, K0, 32);
165 /*
166 * Should result in: 0x8001,0700,0000,8*coreid which is
167 * CVMX_CIU_WDOGX(coreid) - 0x0500
168 *
169 * Now ld K0, CVMX_CIU_WDOGX(coreid)
170 */
171 uasm_i_ld(&p, K0, 0x500, K0);
172 /*
173 * If bit one set handle the NMI as a watchdog event.
174 * otherwise transfer control to bootloader.
175 */
176 uasm_il_bbit0(&p, &r, K0, 1, label_enter_bootloader);
177 uasm_i_nop(&p);
178 }
179#endif
180
181 /* Clear Dcache so cvmseg works right. */
182 uasm_i_cache(&p, 1, 0, 0);
183
184 /* Use K0 to do a read/modify/write of CVMMEMCTL */
185 uasm_i_dmfc0(&p, K0, C0_CVMMEMCTL);
186 /* Clear out the size of CVMSEG */
187 uasm_i_dins(&p, K0, 0, 0, 6);
188 /* Set CVMSEG to its largest value */
189 uasm_i_ori(&p, K0, K0, 0x1c0 | 54);
190 /* Store the CVMMEMCTL value */
191 uasm_i_dmtc0(&p, K0, C0_CVMMEMCTL);
192
193 /* Load the address of the second stage handler */
194 UASM_i_LA(&p, K0, (long)octeon_wdt_nmi_stage2);
195 uasm_i_jr(&p, K0);
196 uasm_i_dmfc0(&p, K0, C0_DESAVE);
197
198#ifdef CONFIG_HOTPLUG_CPU
199 if (octeon_bootloader_entry_addr) {
200 uasm_build_label(&l, p, label_enter_bootloader);
201 /* Jump to the bootloader and restore K0 */
202 UASM_i_LA(&p, K0, (long)octeon_bootloader_entry_addr);
203 uasm_i_jr(&p, K0);
204 uasm_i_dmfc0(&p, K0, C0_DESAVE);
205 }
206#endif
207 uasm_resolve_relocs(relocs, labels);
208
209 len = (int)(p - nmi_stage1_insns);
210 pr_debug("Synthesized NMI stage 1 handler (%d instructions)\n", len);
211
212 pr_debug("\t.set push\n");
213 pr_debug("\t.set noreorder\n");
214 for (i = 0; i < len; i++)
215 pr_debug("\t.word 0x%08x\n", nmi_stage1_insns[i]);
216 pr_debug("\t.set pop\n");
217
218 if (len > 32)
219 panic("NMI stage 1 handler exceeds 32 instructions, was %d\n",
220 len);
221}
222
223static int cpu2core(int cpu)
224{
225#ifdef CONFIG_SMP
226 return cpu_logical_map(cpu);
227#else
228 return cvmx_get_core_num();
229#endif
230}
231
232static int core2cpu(int coreid)
233{
234#ifdef CONFIG_SMP
235 return cpu_number_map(coreid);
236#else
237 return 0;
238#endif
239}
240
241/**
242 * Poke the watchdog when an interrupt is received
243 *
244 * @cpl:
245 * @dev_id:
246 *
247 * Returns
248 */
249static irqreturn_t octeon_wdt_poke_irq(int cpl, void *dev_id)
250{
251 unsigned int core = cvmx_get_core_num();
252 int cpu = core2cpu(core);
253
254 if (do_coundown) {
255 if (per_cpu_countdown[cpu] > 0) {
256 /* We're alive, poke the watchdog */
257 cvmx_write_csr(CVMX_CIU_PP_POKEX(core), 1);
258 per_cpu_countdown[cpu]--;
259 } else {
260 /* Bad news, you are about to reboot. */
261 disable_irq_nosync(cpl);
262 cpumask_clear_cpu(cpu, &irq_enabled_cpus);
263 }
264 } else {
265 /* Not open, just ping away... */
266 cvmx_write_csr(CVMX_CIU_PP_POKEX(core), 1);
267 }
268 return IRQ_HANDLED;
269}
270
271/* From setup.c */
272extern int prom_putchar(char c);
273
274/**
275 * Write a string to the uart
276 *
277 * @str: String to write
278 */
279static void octeon_wdt_write_string(const char *str)
280{
281 /* Just loop writing one byte at a time */
282 while (*str)
283 prom_putchar(*str++);
284}
285
286/**
287 * Write a hex number out of the uart
288 *
289 * @value: Number to display
290 * @digits: Number of digits to print (1 to 16)
291 */
292static void octeon_wdt_write_hex(u64 value, int digits)
293{
294 int d;
295 int v;
296
297 for (d = 0; d < digits; d++) {
298 v = (value >> ((digits - d - 1) * 4)) & 0xf;
299 if (v >= 10)
300 prom_putchar('a' + v - 10);
301 else
302 prom_putchar('0' + v);
303 }
304}
305
306static const char reg_name[][3] = {
307 "$0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
308 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
309 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
310 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
311};
312
313/**
314 * NMI stage 3 handler. NMIs are handled in the following manner:
315 * 1) The first NMI handler enables CVMSEG and transfers from
316 * the bootbus region into normal memory. It is careful to not
317 * destroy any registers.
318 * 2) The second stage handler uses CVMSEG to save the registers
319 * and create a stack for C code. It then calls the third level
320 * handler with one argument, a pointer to the register values.
321 * 3) The third, and final, level handler is the following C
322 * function that prints out some useful infomration.
323 *
324 * @reg: Pointer to register state before the NMI
325 */
326void octeon_wdt_nmi_stage3(u64 reg[32])
327{
328 u64 i;
329
330 unsigned int coreid = cvmx_get_core_num();
331 /*
332 * Save status and cause early to get them before any changes
333 * might happen.
334 */
335 u64 cp0_cause = read_c0_cause();
336 u64 cp0_status = read_c0_status();
337 u64 cp0_error_epc = read_c0_errorepc();
338 u64 cp0_epc = read_c0_epc();
339
340 /* Delay so output from all cores output is not jumbled together. */
341 __delay(100000000ull * coreid);
342
343 octeon_wdt_write_string("\r\n*** NMI Watchdog interrupt on Core 0x");
344 octeon_wdt_write_hex(coreid, 1);
345 octeon_wdt_write_string(" ***\r\n");
346 for (i = 0; i < 32; i++) {
347 octeon_wdt_write_string("\t");
348 octeon_wdt_write_string(reg_name[i]);
349 octeon_wdt_write_string("\t0x");
350 octeon_wdt_write_hex(reg[i], 16);
351 if (i & 1)
352 octeon_wdt_write_string("\r\n");
353 }
354 octeon_wdt_write_string("\terr_epc\t0x");
355 octeon_wdt_write_hex(cp0_error_epc, 16);
356
357 octeon_wdt_write_string("\tepc\t0x");
358 octeon_wdt_write_hex(cp0_epc, 16);
359 octeon_wdt_write_string("\r\n");
360
361 octeon_wdt_write_string("\tstatus\t0x");
362 octeon_wdt_write_hex(cp0_status, 16);
363 octeon_wdt_write_string("\tcause\t0x");
364 octeon_wdt_write_hex(cp0_cause, 16);
365 octeon_wdt_write_string("\r\n");
366
367 octeon_wdt_write_string("\tsum0\t0x");
368 octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU_INTX_SUM0(coreid * 2)), 16);
369 octeon_wdt_write_string("\ten0\t0x");
370 octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)), 16);
371 octeon_wdt_write_string("\r\n");
372
373 octeon_wdt_write_string("*** Chip soft reset soon ***\r\n");
374}
375
376static int octeon_wdt_cpu_pre_down(unsigned int cpu)
377{
378 unsigned int core;
379 unsigned int irq;
380 union cvmx_ciu_wdogx ciu_wdog;
381
382 core = cpu2core(cpu);
383
384 irq = OCTEON_IRQ_WDOG0 + core;
385
386 /* Poke the watchdog to clear out its state */
387 cvmx_write_csr(CVMX_CIU_PP_POKEX(core), 1);
388
389 /* Disable the hardware. */
390 ciu_wdog.u64 = 0;
391 cvmx_write_csr(CVMX_CIU_WDOGX(core), ciu_wdog.u64);
392
393 free_irq(irq, octeon_wdt_poke_irq);
394 return 0;
395}
396
397static int octeon_wdt_cpu_online(unsigned int cpu)
398{
399 unsigned int core;
400 unsigned int irq;
401 union cvmx_ciu_wdogx ciu_wdog;
402
403 core = cpu2core(cpu);
404
405 /* Disable it before doing anything with the interrupts. */
406 ciu_wdog.u64 = 0;
407 cvmx_write_csr(CVMX_CIU_WDOGX(core), ciu_wdog.u64);
408
409 per_cpu_countdown[cpu] = countdown_reset;
410
411 irq = OCTEON_IRQ_WDOG0 + core;
412
413 if (request_irq(irq, octeon_wdt_poke_irq,
414 IRQF_NO_THREAD, "octeon_wdt", octeon_wdt_poke_irq))
415 panic("octeon_wdt: Couldn't obtain irq %d", irq);
416
417 cpumask_set_cpu(cpu, &irq_enabled_cpus);
418
419 /* Poke the watchdog to clear out its state */
420 cvmx_write_csr(CVMX_CIU_PP_POKEX(core), 1);
421
422 /* Finally enable the watchdog now that all handlers are installed */
423 ciu_wdog.u64 = 0;
424 ciu_wdog.s.len = timeout_cnt;
425 ciu_wdog.s.mode = 3; /* 3 = Interrupt + NMI + Soft-Reset */
426 cvmx_write_csr(CVMX_CIU_WDOGX(core), ciu_wdog.u64);
427
428 return 0;
429}
430
431static int octeon_wdt_ping(struct watchdog_device __always_unused *wdog)
432{
433 int cpu;
434 int coreid;
435
436 for_each_online_cpu(cpu) {
437 coreid = cpu2core(cpu);
438 cvmx_write_csr(CVMX_CIU_PP_POKEX(coreid), 1);
439 per_cpu_countdown[cpu] = countdown_reset;
440 if ((countdown_reset || !do_coundown) &&
441 !cpumask_test_cpu(cpu, &irq_enabled_cpus)) {
442 /* We have to enable the irq */
443 int irq = OCTEON_IRQ_WDOG0 + coreid;
444
445 enable_irq(irq);
446 cpumask_set_cpu(cpu, &irq_enabled_cpus);
447 }
448 }
449 return 0;
450}
451
452static void octeon_wdt_calc_parameters(int t)
453{
454 unsigned int periods;
455
456 timeout_sec = max_timeout_sec;
457
458
459 /*
460 * Find the largest interrupt period, that can evenly divide
461 * the requested heartbeat time.
462 */
463 while ((t % timeout_sec) != 0)
464 timeout_sec--;
465
466 periods = t / timeout_sec;
467
468 /*
469 * The last two periods are after the irq is disabled, and
470 * then to the nmi, so we subtract them off.
471 */
472
473 countdown_reset = periods > 2 ? periods - 2 : 0;
474 heartbeat = t;
475 timeout_cnt = ((octeon_get_io_clock_rate() >> 8) * timeout_sec) >> 8;
476}
477
478static int octeon_wdt_set_timeout(struct watchdog_device *wdog,
479 unsigned int t)
480{
481 int cpu;
482 int coreid;
483 union cvmx_ciu_wdogx ciu_wdog;
484
485 if (t <= 0)
486 return -1;
487
488 octeon_wdt_calc_parameters(t);
489
490 for_each_online_cpu(cpu) {
491 coreid = cpu2core(cpu);
492 cvmx_write_csr(CVMX_CIU_PP_POKEX(coreid), 1);
493 ciu_wdog.u64 = 0;
494 ciu_wdog.s.len = timeout_cnt;
495 ciu_wdog.s.mode = 3; /* 3 = Interrupt + NMI + Soft-Reset */
496 cvmx_write_csr(CVMX_CIU_WDOGX(coreid), ciu_wdog.u64);
497 cvmx_write_csr(CVMX_CIU_PP_POKEX(coreid), 1);
498 }
499 octeon_wdt_ping(wdog); /* Get the irqs back on. */
500 return 0;
501}
502
503static int octeon_wdt_start(struct watchdog_device *wdog)
504{
505 octeon_wdt_ping(wdog);
506 do_coundown = 1;
507 return 0;
508}
509
510static int octeon_wdt_stop(struct watchdog_device *wdog)
511{
512 do_coundown = 0;
513 octeon_wdt_ping(wdog);
514 return 0;
515}
516
517static const struct watchdog_info octeon_wdt_info = {
518 .options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING,
519 .identity = "OCTEON",
520};
521
522static const struct watchdog_ops octeon_wdt_ops = {
523 .owner = THIS_MODULE,
524 .start = octeon_wdt_start,
525 .stop = octeon_wdt_stop,
526 .ping = octeon_wdt_ping,
527 .set_timeout = octeon_wdt_set_timeout,
528};
529
530static struct watchdog_device octeon_wdt = {
531 .info = &octeon_wdt_info,
532 .ops = &octeon_wdt_ops,
533};
534
535static enum cpuhp_state octeon_wdt_online;
536/**
537 * Module/ driver initialization.
538 *
539 * Returns Zero on success
540 */
541static int __init octeon_wdt_init(void)
542{
543 int i;
544 int ret;
545 u64 *ptr;
546
547 /*
548 * Watchdog time expiration length = The 16 bits of LEN
549 * represent the most significant bits of a 24 bit decrementer
550 * that decrements every 256 cycles.
551 *
552 * Try for a timeout of 5 sec, if that fails a smaller number
553 * of even seconds,
554 */
555 max_timeout_sec = 6;
556 do {
557 max_timeout_sec--;
558 timeout_cnt = ((octeon_get_io_clock_rate() >> 8) *
559 max_timeout_sec) >> 8;
560 } while (timeout_cnt > 65535);
561
562 BUG_ON(timeout_cnt == 0);
563
564 octeon_wdt_calc_parameters(heartbeat);
565
566 pr_info("Initial granularity %d Sec\n", timeout_sec);
567
568 octeon_wdt.timeout = timeout_sec;
569 octeon_wdt.max_timeout = UINT_MAX;
570
571 watchdog_set_nowayout(&octeon_wdt, nowayout);
572
573 ret = watchdog_register_device(&octeon_wdt);
574 if (ret) {
575 pr_err("watchdog_register_device() failed: %d\n", ret);
576 return ret;
577 }
578
579 /* Build the NMI handler ... */
580 octeon_wdt_build_stage1();
581
582 /* ... and install it. */
583 ptr = (u64 *) nmi_stage1_insns;
584 for (i = 0; i < 16; i++) {
585 cvmx_write_csr(CVMX_MIO_BOOT_LOC_ADR, i * 8);
586 cvmx_write_csr(CVMX_MIO_BOOT_LOC_DAT, ptr[i]);
587 }
588 cvmx_write_csr(CVMX_MIO_BOOT_LOC_CFGX(0), 0x81fc0000);
589
590 cpumask_clear(&irq_enabled_cpus);
591
592 ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "watchdog/octeon:online",
593 octeon_wdt_cpu_online, octeon_wdt_cpu_pre_down);
594 if (ret < 0)
595 goto err;
596 octeon_wdt_online = ret;
597 return 0;
598err:
599 cvmx_write_csr(CVMX_MIO_BOOT_LOC_CFGX(0), 0);
600 watchdog_unregister_device(&octeon_wdt);
601 return ret;
602}
603
604/**
605 * Module / driver shutdown
606 */
607static void __exit octeon_wdt_cleanup(void)
608{
609 watchdog_unregister_device(&octeon_wdt);
610 cpuhp_remove_state(octeon_wdt_online);
611
612 /*
613 * Disable the boot-bus memory, the code it points to is soon
614 * to go missing.
615 */
616 cvmx_write_csr(CVMX_MIO_BOOT_LOC_CFGX(0), 0);
617}
618
619MODULE_LICENSE("GPL");
620MODULE_AUTHOR("Cavium Networks <support@caviumnetworks.com>");
621MODULE_DESCRIPTION("Cavium Networks Octeon Watchdog driver.");
622module_init(octeon_wdt_init);
623module_exit(octeon_wdt_cleanup);