Loading...
1// SPDX-License-Identifier: GPL-2.0-or-later
2
3/* Copyright (c) 2014 Linaro Ltd.
4 * Copyright (c) 2014 Hisilicon Limited.
5 */
6
7#include <linux/module.h>
8#include <linux/etherdevice.h>
9#include <linux/platform_device.h>
10#include <linux/interrupt.h>
11#include <linux/ktime.h>
12#include <linux/of_address.h>
13#include <linux/phy.h>
14#include <linux/of_mdio.h>
15#include <linux/of_net.h>
16#include <linux/mfd/syscon.h>
17#include <linux/regmap.h>
18
19#define SC_PPE_RESET_DREQ 0x026C
20
21#define PPE_CFG_RX_ADDR 0x100
22#define PPE_CFG_POOL_GRP 0x300
23#define PPE_CFG_RX_BUF_SIZE 0x400
24#define PPE_CFG_RX_FIFO_SIZE 0x500
25#define PPE_CURR_BUF_CNT 0xa200
26
27#define GE_DUPLEX_TYPE 0x08
28#define GE_MAX_FRM_SIZE_REG 0x3c
29#define GE_PORT_MODE 0x40
30#define GE_PORT_EN 0x44
31#define GE_SHORT_RUNTS_THR_REG 0x50
32#define GE_TX_LOCAL_PAGE_REG 0x5c
33#define GE_TRANSMIT_CONTROL_REG 0x60
34#define GE_CF_CRC_STRIP_REG 0x1b0
35#define GE_MODE_CHANGE_REG 0x1b4
36#define GE_RECV_CONTROL_REG 0x1e0
37#define GE_STATION_MAC_ADDRESS 0x210
38
39#define PPE_CFG_BUS_CTRL_REG 0x424
40#define PPE_CFG_RX_CTRL_REG 0x428
41
42#if defined(CONFIG_HI13X1_GMAC)
43#define PPE_CFG_CPU_ADD_ADDR 0x6D0
44#define PPE_CFG_MAX_FRAME_LEN_REG 0x500
45#define PPE_CFG_RX_PKT_MODE_REG 0x504
46#define PPE_CFG_QOS_VMID_GEN 0x520
47#define PPE_CFG_RX_PKT_INT 0x740
48#define PPE_INTEN 0x700
49#define PPE_INTSTS 0x708
50#define PPE_RINT 0x704
51#define PPE_CFG_STS_MODE 0x880
52#else
53#define PPE_CFG_CPU_ADD_ADDR 0x580
54#define PPE_CFG_MAX_FRAME_LEN_REG 0x408
55#define PPE_CFG_RX_PKT_MODE_REG 0x438
56#define PPE_CFG_QOS_VMID_GEN 0x500
57#define PPE_CFG_RX_PKT_INT 0x538
58#define PPE_INTEN 0x600
59#define PPE_INTSTS 0x608
60#define PPE_RINT 0x604
61#define PPE_CFG_STS_MODE 0x700
62#endif /* CONFIG_HI13X1_GMAC */
63
64#define PPE_HIS_RX_PKT_CNT 0x804
65
66#define RESET_DREQ_ALL 0xffffffff
67
68/* REG_INTERRUPT */
69#define RCV_INT BIT(10)
70#define RCV_NOBUF BIT(8)
71#define RCV_DROP BIT(7)
72#define TX_DROP BIT(6)
73#define DEF_INT_ERR (RCV_NOBUF | RCV_DROP | TX_DROP)
74#define DEF_INT_MASK (RCV_INT | DEF_INT_ERR)
75
76/* TX descriptor config */
77#define TX_FREE_MEM BIT(0)
78#define TX_READ_ALLOC_L3 BIT(1)
79#if defined(CONFIG_HI13X1_GMAC)
80#define TX_CLEAR_WB BIT(7)
81#define TX_RELEASE_TO_PPE BIT(4)
82#define TX_FINISH_CACHE_INV BIT(6)
83#define TX_POOL_SHIFT 16
84#else
85#define TX_CLEAR_WB BIT(4)
86#define TX_FINISH_CACHE_INV BIT(2)
87#endif
88#define TX_L3_CHECKSUM BIT(5)
89#define TX_LOOP_BACK BIT(11)
90
91/* RX error */
92#define RX_PKT_DROP BIT(0)
93#define RX_L2_ERR BIT(1)
94#define RX_PKT_ERR (RX_PKT_DROP | RX_L2_ERR)
95
96#define SGMII_SPEED_1000 0x08
97#define SGMII_SPEED_100 0x07
98#define SGMII_SPEED_10 0x06
99#define MII_SPEED_100 0x01
100#define MII_SPEED_10 0x00
101
102#define GE_DUPLEX_FULL BIT(0)
103#define GE_DUPLEX_HALF 0x00
104#define GE_MODE_CHANGE_EN BIT(0)
105
106#define GE_TX_AUTO_NEG BIT(5)
107#define GE_TX_ADD_CRC BIT(6)
108#define GE_TX_SHORT_PAD_THROUGH BIT(7)
109
110#define GE_RX_STRIP_CRC BIT(0)
111#define GE_RX_STRIP_PAD BIT(3)
112#define GE_RX_PAD_EN BIT(4)
113
114#define GE_AUTO_NEG_CTL BIT(0)
115
116#define GE_RX_INT_THRESHOLD BIT(6)
117#define GE_RX_TIMEOUT 0x04
118
119#define GE_RX_PORT_EN BIT(1)
120#define GE_TX_PORT_EN BIT(2)
121
122#define PPE_CFG_RX_PKT_ALIGN BIT(18)
123
124#if defined(CONFIG_HI13X1_GMAC)
125#define PPE_CFG_QOS_VMID_GRP_SHIFT 4
126#define PPE_CFG_RX_CTRL_ALIGN_SHIFT 7
127#define PPE_CFG_STS_RX_PKT_CNT_RC BIT(0)
128#define PPE_CFG_QOS_VMID_MODE BIT(15)
129#define PPE_CFG_BUS_LOCAL_REL (BIT(9) | BIT(15) | BIT(19) | BIT(23))
130
131/* buf unit size is cache_line_size, which is 64, so the shift is 6 */
132#define PPE_BUF_SIZE_SHIFT 6
133#define PPE_TX_BUF_HOLD BIT(31)
134#define SOC_CACHE_LINE_MASK 0x3F
135#else
136#define PPE_CFG_QOS_VMID_GRP_SHIFT 8
137#define PPE_CFG_RX_CTRL_ALIGN_SHIFT 11
138#define PPE_CFG_STS_RX_PKT_CNT_RC BIT(12)
139#define PPE_CFG_QOS_VMID_MODE BIT(14)
140#define PPE_CFG_BUS_LOCAL_REL BIT(14)
141
142/* buf unit size is 1, so the shift is 6 */
143#define PPE_BUF_SIZE_SHIFT 0
144#define PPE_TX_BUF_HOLD 0
145#endif /* CONFIG_HI13X1_GMAC */
146
147#define PPE_CFG_RX_FIFO_FSFU BIT(11)
148#define PPE_CFG_RX_DEPTH_SHIFT 16
149#define PPE_CFG_RX_START_SHIFT 0
150
151#define PPE_CFG_BUS_BIG_ENDIEN BIT(0)
152
153#define RX_DESC_NUM 128
154#define TX_DESC_NUM 256
155#define TX_NEXT(N) (((N) + 1) & (TX_DESC_NUM-1))
156#define RX_NEXT(N) (((N) + 1) & (RX_DESC_NUM-1))
157
158#define GMAC_PPE_RX_PKT_MAX_LEN 379
159#define GMAC_MAX_PKT_LEN 1516
160#define GMAC_MIN_PKT_LEN 31
161#define RX_BUF_SIZE 1600
162#define RESET_TIMEOUT 1000
163#define TX_TIMEOUT (6 * HZ)
164
165#define DRV_NAME "hip04-ether"
166#define DRV_VERSION "v1.0"
167
168#define HIP04_MAX_TX_COALESCE_USECS 200
169#define HIP04_MIN_TX_COALESCE_USECS 100
170#define HIP04_MAX_TX_COALESCE_FRAMES 200
171#define HIP04_MIN_TX_COALESCE_FRAMES 100
172
173struct tx_desc {
174#if defined(CONFIG_HI13X1_GMAC)
175 u32 reserved1[2];
176 u32 send_addr;
177 u16 send_size;
178 u16 data_offset;
179 u32 reserved2[7];
180 u32 cfg;
181 u32 wb_addr;
182 u32 reserved3[3];
183#else
184 u32 send_addr;
185 u32 send_size;
186 u32 next_addr;
187 u32 cfg;
188 u32 wb_addr;
189#endif
190} __aligned(64);
191
192struct rx_desc {
193#if defined(CONFIG_HI13X1_GMAC)
194 u32 reserved1[3];
195 u16 pkt_len;
196 u16 reserved_16;
197 u32 reserved2[6];
198 u32 pkt_err;
199 u32 reserved3[5];
200#else
201 u16 reserved_16;
202 u16 pkt_len;
203 u32 reserve1[3];
204 u32 pkt_err;
205 u32 reserve2[4];
206#endif
207};
208
209struct hip04_priv {
210 void __iomem *base;
211#if defined(CONFIG_HI13X1_GMAC)
212 void __iomem *sysctrl_base;
213#endif
214 phy_interface_t phy_mode;
215 int chan;
216 unsigned int port;
217 unsigned int group;
218 unsigned int speed;
219 unsigned int duplex;
220 unsigned int reg_inten;
221
222 struct napi_struct napi;
223 struct device *dev;
224 struct net_device *ndev;
225
226 struct tx_desc *tx_desc;
227 dma_addr_t tx_desc_dma;
228 struct sk_buff *tx_skb[TX_DESC_NUM];
229 dma_addr_t tx_phys[TX_DESC_NUM];
230 unsigned int tx_head;
231
232 int tx_coalesce_frames;
233 int tx_coalesce_usecs;
234 struct hrtimer tx_coalesce_timer;
235
236 unsigned char *rx_buf[RX_DESC_NUM];
237 dma_addr_t rx_phys[RX_DESC_NUM];
238 unsigned int rx_head;
239 unsigned int rx_buf_size;
240 unsigned int rx_cnt_remaining;
241
242 struct device_node *phy_node;
243 struct phy_device *phy;
244 struct regmap *map;
245 struct work_struct tx_timeout_task;
246
247 /* written only by tx cleanup */
248 unsigned int tx_tail ____cacheline_aligned_in_smp;
249};
250
251static inline unsigned int tx_count(unsigned int head, unsigned int tail)
252{
253 return (head - tail) % TX_DESC_NUM;
254}
255
256static void hip04_config_port(struct net_device *ndev, u32 speed, u32 duplex)
257{
258 struct hip04_priv *priv = netdev_priv(ndev);
259 u32 val;
260
261 priv->speed = speed;
262 priv->duplex = duplex;
263
264 switch (priv->phy_mode) {
265 case PHY_INTERFACE_MODE_SGMII:
266 if (speed == SPEED_1000)
267 val = SGMII_SPEED_1000;
268 else if (speed == SPEED_100)
269 val = SGMII_SPEED_100;
270 else
271 val = SGMII_SPEED_10;
272 break;
273 case PHY_INTERFACE_MODE_MII:
274 if (speed == SPEED_100)
275 val = MII_SPEED_100;
276 else
277 val = MII_SPEED_10;
278 break;
279 default:
280 netdev_warn(ndev, "not supported mode\n");
281 val = MII_SPEED_10;
282 break;
283 }
284 writel_relaxed(val, priv->base + GE_PORT_MODE);
285
286 val = duplex ? GE_DUPLEX_FULL : GE_DUPLEX_HALF;
287 writel_relaxed(val, priv->base + GE_DUPLEX_TYPE);
288
289 val = GE_MODE_CHANGE_EN;
290 writel_relaxed(val, priv->base + GE_MODE_CHANGE_REG);
291}
292
293static void hip04_reset_dreq(struct hip04_priv *priv)
294{
295#if defined(CONFIG_HI13X1_GMAC)
296 writel_relaxed(RESET_DREQ_ALL, priv->sysctrl_base + SC_PPE_RESET_DREQ);
297#endif
298}
299
300static void hip04_reset_ppe(struct hip04_priv *priv)
301{
302 u32 val, tmp, timeout = 0;
303
304 do {
305 regmap_read(priv->map, priv->port * 4 + PPE_CURR_BUF_CNT, &val);
306 regmap_read(priv->map, priv->port * 4 + PPE_CFG_RX_ADDR, &tmp);
307 if (timeout++ > RESET_TIMEOUT)
308 break;
309 } while (val & 0xfff);
310}
311
312static void hip04_config_fifo(struct hip04_priv *priv)
313{
314 u32 val;
315
316 val = readl_relaxed(priv->base + PPE_CFG_STS_MODE);
317 val |= PPE_CFG_STS_RX_PKT_CNT_RC;
318 writel_relaxed(val, priv->base + PPE_CFG_STS_MODE);
319
320 val = BIT(priv->group);
321 regmap_write(priv->map, priv->port * 4 + PPE_CFG_POOL_GRP, val);
322
323 val = priv->group << PPE_CFG_QOS_VMID_GRP_SHIFT;
324 val |= PPE_CFG_QOS_VMID_MODE;
325 writel_relaxed(val, priv->base + PPE_CFG_QOS_VMID_GEN);
326
327 val = RX_BUF_SIZE >> PPE_BUF_SIZE_SHIFT;
328 regmap_write(priv->map, priv->port * 4 + PPE_CFG_RX_BUF_SIZE, val);
329
330 val = RX_DESC_NUM << PPE_CFG_RX_DEPTH_SHIFT;
331 val |= PPE_CFG_RX_FIFO_FSFU;
332 val |= priv->chan << PPE_CFG_RX_START_SHIFT;
333 regmap_write(priv->map, priv->port * 4 + PPE_CFG_RX_FIFO_SIZE, val);
334
335 val = NET_IP_ALIGN << PPE_CFG_RX_CTRL_ALIGN_SHIFT;
336 writel_relaxed(val, priv->base + PPE_CFG_RX_CTRL_REG);
337
338 val = PPE_CFG_RX_PKT_ALIGN;
339 writel_relaxed(val, priv->base + PPE_CFG_RX_PKT_MODE_REG);
340
341 val = PPE_CFG_BUS_LOCAL_REL | PPE_CFG_BUS_BIG_ENDIEN;
342 writel_relaxed(val, priv->base + PPE_CFG_BUS_CTRL_REG);
343
344 val = GMAC_PPE_RX_PKT_MAX_LEN;
345 writel_relaxed(val, priv->base + PPE_CFG_MAX_FRAME_LEN_REG);
346
347 val = GMAC_MAX_PKT_LEN;
348 writel_relaxed(val, priv->base + GE_MAX_FRM_SIZE_REG);
349
350 val = GMAC_MIN_PKT_LEN;
351 writel_relaxed(val, priv->base + GE_SHORT_RUNTS_THR_REG);
352
353 val = readl_relaxed(priv->base + GE_TRANSMIT_CONTROL_REG);
354 val |= GE_TX_AUTO_NEG | GE_TX_ADD_CRC | GE_TX_SHORT_PAD_THROUGH;
355 writel_relaxed(val, priv->base + GE_TRANSMIT_CONTROL_REG);
356
357 val = GE_RX_STRIP_CRC;
358 writel_relaxed(val, priv->base + GE_CF_CRC_STRIP_REG);
359
360 val = readl_relaxed(priv->base + GE_RECV_CONTROL_REG);
361 val |= GE_RX_STRIP_PAD | GE_RX_PAD_EN;
362 writel_relaxed(val, priv->base + GE_RECV_CONTROL_REG);
363
364#ifndef CONFIG_HI13X1_GMAC
365 val = GE_AUTO_NEG_CTL;
366 writel_relaxed(val, priv->base + GE_TX_LOCAL_PAGE_REG);
367#endif
368}
369
370static void hip04_mac_enable(struct net_device *ndev)
371{
372 struct hip04_priv *priv = netdev_priv(ndev);
373 u32 val;
374
375 /* enable tx & rx */
376 val = readl_relaxed(priv->base + GE_PORT_EN);
377 val |= GE_RX_PORT_EN | GE_TX_PORT_EN;
378 writel_relaxed(val, priv->base + GE_PORT_EN);
379
380 /* clear rx int */
381 val = RCV_INT;
382 writel_relaxed(val, priv->base + PPE_RINT);
383
384 /* config recv int */
385 val = GE_RX_INT_THRESHOLD | GE_RX_TIMEOUT;
386 writel_relaxed(val, priv->base + PPE_CFG_RX_PKT_INT);
387
388 /* enable interrupt */
389 priv->reg_inten = DEF_INT_MASK;
390 writel_relaxed(priv->reg_inten, priv->base + PPE_INTEN);
391}
392
393static void hip04_mac_disable(struct net_device *ndev)
394{
395 struct hip04_priv *priv = netdev_priv(ndev);
396 u32 val;
397
398 /* disable int */
399 priv->reg_inten &= ~(DEF_INT_MASK);
400 writel_relaxed(priv->reg_inten, priv->base + PPE_INTEN);
401
402 /* disable tx & rx */
403 val = readl_relaxed(priv->base + GE_PORT_EN);
404 val &= ~(GE_RX_PORT_EN | GE_TX_PORT_EN);
405 writel_relaxed(val, priv->base + GE_PORT_EN);
406}
407
408static void hip04_set_xmit_desc(struct hip04_priv *priv, dma_addr_t phys)
409{
410 u32 val;
411
412 val = phys >> PPE_BUF_SIZE_SHIFT | PPE_TX_BUF_HOLD;
413 writel(val, priv->base + PPE_CFG_CPU_ADD_ADDR);
414}
415
416static void hip04_set_recv_desc(struct hip04_priv *priv, dma_addr_t phys)
417{
418 u32 val;
419
420 val = phys >> PPE_BUF_SIZE_SHIFT;
421 regmap_write(priv->map, priv->port * 4 + PPE_CFG_RX_ADDR, val);
422}
423
424static u32 hip04_recv_cnt(struct hip04_priv *priv)
425{
426 return readl(priv->base + PPE_HIS_RX_PKT_CNT);
427}
428
429static void hip04_update_mac_address(struct net_device *ndev)
430{
431 struct hip04_priv *priv = netdev_priv(ndev);
432
433 writel_relaxed(((ndev->dev_addr[0] << 8) | (ndev->dev_addr[1])),
434 priv->base + GE_STATION_MAC_ADDRESS);
435 writel_relaxed(((ndev->dev_addr[2] << 24) | (ndev->dev_addr[3] << 16) |
436 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5])),
437 priv->base + GE_STATION_MAC_ADDRESS + 4);
438}
439
440static int hip04_set_mac_address(struct net_device *ndev, void *addr)
441{
442 eth_mac_addr(ndev, addr);
443 hip04_update_mac_address(ndev);
444 return 0;
445}
446
447static int hip04_tx_reclaim(struct net_device *ndev, bool force)
448{
449 struct hip04_priv *priv = netdev_priv(ndev);
450 unsigned tx_tail = priv->tx_tail;
451 struct tx_desc *desc;
452 unsigned int bytes_compl = 0, pkts_compl = 0;
453 unsigned int count;
454
455 smp_rmb();
456 count = tx_count(READ_ONCE(priv->tx_head), tx_tail);
457 if (count == 0)
458 goto out;
459
460 while (count) {
461 desc = &priv->tx_desc[tx_tail];
462 if (desc->send_addr != 0) {
463 if (force)
464 desc->send_addr = 0;
465 else
466 break;
467 }
468
469 if (priv->tx_phys[tx_tail]) {
470 dma_unmap_single(priv->dev, priv->tx_phys[tx_tail],
471 priv->tx_skb[tx_tail]->len,
472 DMA_TO_DEVICE);
473 priv->tx_phys[tx_tail] = 0;
474 }
475 pkts_compl++;
476 bytes_compl += priv->tx_skb[tx_tail]->len;
477 dev_kfree_skb(priv->tx_skb[tx_tail]);
478 priv->tx_skb[tx_tail] = NULL;
479 tx_tail = TX_NEXT(tx_tail);
480 count--;
481 }
482
483 priv->tx_tail = tx_tail;
484 smp_wmb(); /* Ensure tx_tail visible to xmit */
485
486out:
487 if (pkts_compl || bytes_compl)
488 netdev_completed_queue(ndev, pkts_compl, bytes_compl);
489
490 if (unlikely(netif_queue_stopped(ndev)) && (count < (TX_DESC_NUM - 1)))
491 netif_wake_queue(ndev);
492
493 return count;
494}
495
496static void hip04_start_tx_timer(struct hip04_priv *priv)
497{
498 unsigned long ns = priv->tx_coalesce_usecs * NSEC_PER_USEC / 2;
499
500 /* allow timer to fire after half the time at the earliest */
501 hrtimer_start_range_ns(&priv->tx_coalesce_timer, ns_to_ktime(ns),
502 ns, HRTIMER_MODE_REL);
503}
504
505static netdev_tx_t
506hip04_mac_start_xmit(struct sk_buff *skb, struct net_device *ndev)
507{
508 struct hip04_priv *priv = netdev_priv(ndev);
509 struct net_device_stats *stats = &ndev->stats;
510 unsigned int tx_head = priv->tx_head, count;
511 struct tx_desc *desc = &priv->tx_desc[tx_head];
512 dma_addr_t phys;
513
514 smp_rmb();
515 count = tx_count(tx_head, READ_ONCE(priv->tx_tail));
516 if (count == (TX_DESC_NUM - 1)) {
517 netif_stop_queue(ndev);
518 return NETDEV_TX_BUSY;
519 }
520
521 phys = dma_map_single(priv->dev, skb->data, skb->len, DMA_TO_DEVICE);
522 if (dma_mapping_error(priv->dev, phys)) {
523 dev_kfree_skb(skb);
524 return NETDEV_TX_OK;
525 }
526
527 priv->tx_skb[tx_head] = skb;
528 priv->tx_phys[tx_head] = phys;
529
530 desc->send_size = (__force u32)cpu_to_be32(skb->len);
531#if defined(CONFIG_HI13X1_GMAC)
532 desc->cfg = (__force u32)cpu_to_be32(TX_CLEAR_WB | TX_FINISH_CACHE_INV
533 | TX_RELEASE_TO_PPE | priv->port << TX_POOL_SHIFT);
534 desc->data_offset = (__force u32)cpu_to_be32(phys & SOC_CACHE_LINE_MASK);
535 desc->send_addr = (__force u32)cpu_to_be32(phys & ~SOC_CACHE_LINE_MASK);
536#else
537 desc->cfg = (__force u32)cpu_to_be32(TX_CLEAR_WB | TX_FINISH_CACHE_INV);
538 desc->send_addr = (__force u32)cpu_to_be32(phys);
539#endif
540 phys = priv->tx_desc_dma + tx_head * sizeof(struct tx_desc);
541 desc->wb_addr = (__force u32)cpu_to_be32(phys +
542 offsetof(struct tx_desc, send_addr));
543 skb_tx_timestamp(skb);
544
545 hip04_set_xmit_desc(priv, phys);
546 count++;
547 netdev_sent_queue(ndev, skb->len);
548 priv->tx_head = TX_NEXT(tx_head);
549
550 stats->tx_bytes += skb->len;
551 stats->tx_packets++;
552
553 /* Ensure tx_head update visible to tx reclaim */
554 smp_wmb();
555
556 /* queue is getting full, better start cleaning up now */
557 if (count >= priv->tx_coalesce_frames) {
558 if (napi_schedule_prep(&priv->napi)) {
559 /* disable rx interrupt and timer */
560 priv->reg_inten &= ~(RCV_INT);
561 writel_relaxed(DEF_INT_MASK & ~RCV_INT,
562 priv->base + PPE_INTEN);
563 hrtimer_cancel(&priv->tx_coalesce_timer);
564 __napi_schedule(&priv->napi);
565 }
566 } else if (!hrtimer_is_queued(&priv->tx_coalesce_timer)) {
567 /* cleanup not pending yet, start a new timer */
568 hip04_start_tx_timer(priv);
569 }
570
571 return NETDEV_TX_OK;
572}
573
574static int hip04_rx_poll(struct napi_struct *napi, int budget)
575{
576 struct hip04_priv *priv = container_of(napi, struct hip04_priv, napi);
577 struct net_device *ndev = priv->ndev;
578 struct net_device_stats *stats = &ndev->stats;
579 struct rx_desc *desc;
580 struct sk_buff *skb;
581 unsigned char *buf;
582 bool last = false;
583 dma_addr_t phys;
584 int rx = 0;
585 int tx_remaining;
586 u16 len;
587 u32 err;
588
589 /* clean up tx descriptors */
590 tx_remaining = hip04_tx_reclaim(ndev, false);
591 priv->rx_cnt_remaining += hip04_recv_cnt(priv);
592 while (priv->rx_cnt_remaining && !last) {
593 buf = priv->rx_buf[priv->rx_head];
594 skb = build_skb(buf, priv->rx_buf_size);
595 if (unlikely(!skb)) {
596 net_dbg_ratelimited("build_skb failed\n");
597 goto refill;
598 }
599
600 dma_unmap_single(priv->dev, priv->rx_phys[priv->rx_head],
601 RX_BUF_SIZE, DMA_FROM_DEVICE);
602 priv->rx_phys[priv->rx_head] = 0;
603
604 desc = (struct rx_desc *)skb->data;
605 len = be16_to_cpu((__force __be16)desc->pkt_len);
606 err = be32_to_cpu((__force __be32)desc->pkt_err);
607
608 if (0 == len) {
609 dev_kfree_skb_any(skb);
610 last = true;
611 } else if ((err & RX_PKT_ERR) || (len >= GMAC_MAX_PKT_LEN)) {
612 dev_kfree_skb_any(skb);
613 stats->rx_dropped++;
614 stats->rx_errors++;
615 } else {
616 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
617 skb_put(skb, len);
618 skb->protocol = eth_type_trans(skb, ndev);
619 napi_gro_receive(&priv->napi, skb);
620 stats->rx_packets++;
621 stats->rx_bytes += len;
622 rx++;
623 }
624
625refill:
626 buf = netdev_alloc_frag(priv->rx_buf_size);
627 if (!buf)
628 goto done;
629 phys = dma_map_single(priv->dev, buf,
630 RX_BUF_SIZE, DMA_FROM_DEVICE);
631 if (dma_mapping_error(priv->dev, phys))
632 goto done;
633 priv->rx_buf[priv->rx_head] = buf;
634 priv->rx_phys[priv->rx_head] = phys;
635 hip04_set_recv_desc(priv, phys);
636
637 priv->rx_head = RX_NEXT(priv->rx_head);
638 if (rx >= budget) {
639 --priv->rx_cnt_remaining;
640 goto done;
641 }
642
643 if (--priv->rx_cnt_remaining == 0)
644 priv->rx_cnt_remaining += hip04_recv_cnt(priv);
645 }
646
647 if (!(priv->reg_inten & RCV_INT)) {
648 /* enable rx interrupt */
649 priv->reg_inten |= RCV_INT;
650 writel_relaxed(priv->reg_inten, priv->base + PPE_INTEN);
651 }
652 napi_complete_done(napi, rx);
653done:
654 /* start a new timer if necessary */
655 if (rx < budget && tx_remaining)
656 hip04_start_tx_timer(priv);
657
658 return rx;
659}
660
661static irqreturn_t hip04_mac_interrupt(int irq, void *dev_id)
662{
663 struct net_device *ndev = (struct net_device *)dev_id;
664 struct hip04_priv *priv = netdev_priv(ndev);
665 struct net_device_stats *stats = &ndev->stats;
666 u32 ists = readl_relaxed(priv->base + PPE_INTSTS);
667
668 if (!ists)
669 return IRQ_NONE;
670
671 writel_relaxed(DEF_INT_MASK, priv->base + PPE_RINT);
672
673 if (unlikely(ists & DEF_INT_ERR)) {
674 if (ists & (RCV_NOBUF | RCV_DROP)) {
675 stats->rx_errors++;
676 stats->rx_dropped++;
677 netdev_err(ndev, "rx drop\n");
678 }
679 if (ists & TX_DROP) {
680 stats->tx_dropped++;
681 netdev_err(ndev, "tx drop\n");
682 }
683 }
684
685 if (ists & RCV_INT && napi_schedule_prep(&priv->napi)) {
686 /* disable rx interrupt */
687 priv->reg_inten &= ~(RCV_INT);
688 writel_relaxed(DEF_INT_MASK & ~RCV_INT, priv->base + PPE_INTEN);
689 hrtimer_cancel(&priv->tx_coalesce_timer);
690 __napi_schedule(&priv->napi);
691 }
692
693 return IRQ_HANDLED;
694}
695
696static enum hrtimer_restart tx_done(struct hrtimer *hrtimer)
697{
698 struct hip04_priv *priv;
699
700 priv = container_of(hrtimer, struct hip04_priv, tx_coalesce_timer);
701
702 if (napi_schedule_prep(&priv->napi)) {
703 /* disable rx interrupt */
704 priv->reg_inten &= ~(RCV_INT);
705 writel_relaxed(DEF_INT_MASK & ~RCV_INT, priv->base + PPE_INTEN);
706 __napi_schedule(&priv->napi);
707 }
708
709 return HRTIMER_NORESTART;
710}
711
712static void hip04_adjust_link(struct net_device *ndev)
713{
714 struct hip04_priv *priv = netdev_priv(ndev);
715 struct phy_device *phy = priv->phy;
716
717 if ((priv->speed != phy->speed) || (priv->duplex != phy->duplex)) {
718 hip04_config_port(ndev, phy->speed, phy->duplex);
719 phy_print_status(phy);
720 }
721}
722
723static int hip04_mac_open(struct net_device *ndev)
724{
725 struct hip04_priv *priv = netdev_priv(ndev);
726 int i;
727
728 priv->rx_head = 0;
729 priv->rx_cnt_remaining = 0;
730 priv->tx_head = 0;
731 priv->tx_tail = 0;
732 hip04_reset_ppe(priv);
733
734 for (i = 0; i < RX_DESC_NUM; i++) {
735 dma_addr_t phys;
736
737 phys = dma_map_single(priv->dev, priv->rx_buf[i],
738 RX_BUF_SIZE, DMA_FROM_DEVICE);
739 if (dma_mapping_error(priv->dev, phys))
740 return -EIO;
741
742 priv->rx_phys[i] = phys;
743 hip04_set_recv_desc(priv, phys);
744 }
745
746 if (priv->phy)
747 phy_start(priv->phy);
748
749 netdev_reset_queue(ndev);
750 netif_start_queue(ndev);
751 hip04_mac_enable(ndev);
752 napi_enable(&priv->napi);
753
754 return 0;
755}
756
757static int hip04_mac_stop(struct net_device *ndev)
758{
759 struct hip04_priv *priv = netdev_priv(ndev);
760 int i;
761
762 napi_disable(&priv->napi);
763 netif_stop_queue(ndev);
764 hip04_mac_disable(ndev);
765 hip04_tx_reclaim(ndev, true);
766 hip04_reset_ppe(priv);
767
768 if (priv->phy)
769 phy_stop(priv->phy);
770
771 for (i = 0; i < RX_DESC_NUM; i++) {
772 if (priv->rx_phys[i]) {
773 dma_unmap_single(priv->dev, priv->rx_phys[i],
774 RX_BUF_SIZE, DMA_FROM_DEVICE);
775 priv->rx_phys[i] = 0;
776 }
777 }
778
779 return 0;
780}
781
782static void hip04_timeout(struct net_device *ndev, unsigned int txqueue)
783{
784 struct hip04_priv *priv = netdev_priv(ndev);
785
786 schedule_work(&priv->tx_timeout_task);
787}
788
789static void hip04_tx_timeout_task(struct work_struct *work)
790{
791 struct hip04_priv *priv;
792
793 priv = container_of(work, struct hip04_priv, tx_timeout_task);
794 hip04_mac_stop(priv->ndev);
795 hip04_mac_open(priv->ndev);
796}
797
798static int hip04_get_coalesce(struct net_device *netdev,
799 struct ethtool_coalesce *ec,
800 struct kernel_ethtool_coalesce *kernel_coal,
801 struct netlink_ext_ack *extack)
802{
803 struct hip04_priv *priv = netdev_priv(netdev);
804
805 ec->tx_coalesce_usecs = priv->tx_coalesce_usecs;
806 ec->tx_max_coalesced_frames = priv->tx_coalesce_frames;
807
808 return 0;
809}
810
811static int hip04_set_coalesce(struct net_device *netdev,
812 struct ethtool_coalesce *ec,
813 struct kernel_ethtool_coalesce *kernel_coal,
814 struct netlink_ext_ack *extack)
815{
816 struct hip04_priv *priv = netdev_priv(netdev);
817
818 if ((ec->tx_coalesce_usecs > HIP04_MAX_TX_COALESCE_USECS ||
819 ec->tx_coalesce_usecs < HIP04_MIN_TX_COALESCE_USECS) ||
820 (ec->tx_max_coalesced_frames > HIP04_MAX_TX_COALESCE_FRAMES ||
821 ec->tx_max_coalesced_frames < HIP04_MIN_TX_COALESCE_FRAMES))
822 return -EINVAL;
823
824 priv->tx_coalesce_usecs = ec->tx_coalesce_usecs;
825 priv->tx_coalesce_frames = ec->tx_max_coalesced_frames;
826
827 return 0;
828}
829
830static void hip04_get_drvinfo(struct net_device *netdev,
831 struct ethtool_drvinfo *drvinfo)
832{
833 strscpy(drvinfo->driver, DRV_NAME, sizeof(drvinfo->driver));
834 strscpy(drvinfo->version, DRV_VERSION, sizeof(drvinfo->version));
835}
836
837static const struct ethtool_ops hip04_ethtool_ops = {
838 .supported_coalesce_params = ETHTOOL_COALESCE_TX_USECS |
839 ETHTOOL_COALESCE_TX_MAX_FRAMES,
840 .get_coalesce = hip04_get_coalesce,
841 .set_coalesce = hip04_set_coalesce,
842 .get_drvinfo = hip04_get_drvinfo,
843};
844
845static const struct net_device_ops hip04_netdev_ops = {
846 .ndo_open = hip04_mac_open,
847 .ndo_stop = hip04_mac_stop,
848 .ndo_start_xmit = hip04_mac_start_xmit,
849 .ndo_set_mac_address = hip04_set_mac_address,
850 .ndo_tx_timeout = hip04_timeout,
851 .ndo_validate_addr = eth_validate_addr,
852};
853
854static int hip04_alloc_ring(struct net_device *ndev, struct device *d)
855{
856 struct hip04_priv *priv = netdev_priv(ndev);
857 int i;
858
859 priv->tx_desc = dma_alloc_coherent(d,
860 TX_DESC_NUM * sizeof(struct tx_desc),
861 &priv->tx_desc_dma, GFP_KERNEL);
862 if (!priv->tx_desc)
863 return -ENOMEM;
864
865 priv->rx_buf_size = RX_BUF_SIZE +
866 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
867 for (i = 0; i < RX_DESC_NUM; i++) {
868 priv->rx_buf[i] = netdev_alloc_frag(priv->rx_buf_size);
869 if (!priv->rx_buf[i])
870 return -ENOMEM;
871 }
872
873 return 0;
874}
875
876static void hip04_free_ring(struct net_device *ndev, struct device *d)
877{
878 struct hip04_priv *priv = netdev_priv(ndev);
879 int i;
880
881 for (i = 0; i < RX_DESC_NUM; i++)
882 if (priv->rx_buf[i])
883 skb_free_frag(priv->rx_buf[i]);
884
885 for (i = 0; i < TX_DESC_NUM; i++)
886 if (priv->tx_skb[i])
887 dev_kfree_skb_any(priv->tx_skb[i]);
888
889 dma_free_coherent(d, TX_DESC_NUM * sizeof(struct tx_desc),
890 priv->tx_desc, priv->tx_desc_dma);
891}
892
893static int hip04_mac_probe(struct platform_device *pdev)
894{
895 struct device *d = &pdev->dev;
896 struct device_node *node = d->of_node;
897 struct of_phandle_args arg;
898 struct net_device *ndev;
899 struct hip04_priv *priv;
900 int irq;
901 int ret;
902
903 ndev = alloc_etherdev(sizeof(struct hip04_priv));
904 if (!ndev)
905 return -ENOMEM;
906
907 priv = netdev_priv(ndev);
908 priv->dev = d;
909 priv->ndev = ndev;
910 platform_set_drvdata(pdev, ndev);
911 SET_NETDEV_DEV(ndev, &pdev->dev);
912
913 priv->base = devm_platform_ioremap_resource(pdev, 0);
914 if (IS_ERR(priv->base)) {
915 ret = PTR_ERR(priv->base);
916 goto init_fail;
917 }
918
919#if defined(CONFIG_HI13X1_GMAC)
920 priv->sysctrl_base = devm_platform_ioremap_resource(pdev, 1);
921 if (IS_ERR(priv->sysctrl_base)) {
922 ret = PTR_ERR(priv->sysctrl_base);
923 goto init_fail;
924 }
925#endif
926
927 ret = of_parse_phandle_with_fixed_args(node, "port-handle", 3, 0, &arg);
928 if (ret < 0) {
929 dev_warn(d, "no port-handle\n");
930 goto init_fail;
931 }
932
933 priv->port = arg.args[0];
934 priv->chan = arg.args[1] * RX_DESC_NUM;
935 priv->group = arg.args[2];
936
937 hrtimer_init(&priv->tx_coalesce_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
938
939 /* BQL will try to keep the TX queue as short as possible, but it can't
940 * be faster than tx_coalesce_usecs, so we need a fast timeout here,
941 * but also long enough to gather up enough frames to ensure we don't
942 * get more interrupts than necessary.
943 * 200us is enough for 16 frames of 1500 bytes at gigabit ethernet rate
944 */
945 priv->tx_coalesce_frames = TX_DESC_NUM * 3 / 4;
946 priv->tx_coalesce_usecs = 200;
947 priv->tx_coalesce_timer.function = tx_done;
948
949 priv->map = syscon_node_to_regmap(arg.np);
950 of_node_put(arg.np);
951 if (IS_ERR(priv->map)) {
952 dev_warn(d, "no syscon hisilicon,hip04-ppe\n");
953 ret = PTR_ERR(priv->map);
954 goto init_fail;
955 }
956
957 ret = of_get_phy_mode(node, &priv->phy_mode);
958 if (ret) {
959 dev_warn(d, "not find phy-mode\n");
960 goto init_fail;
961 }
962
963 irq = platform_get_irq(pdev, 0);
964 if (irq < 0) {
965 ret = irq;
966 goto init_fail;
967 }
968
969 ret = devm_request_irq(d, irq, hip04_mac_interrupt,
970 0, pdev->name, ndev);
971 if (ret) {
972 netdev_err(ndev, "devm_request_irq failed\n");
973 goto init_fail;
974 }
975
976 priv->phy_node = of_parse_phandle(node, "phy-handle", 0);
977 if (priv->phy_node) {
978 priv->phy = of_phy_connect(ndev, priv->phy_node,
979 &hip04_adjust_link,
980 0, priv->phy_mode);
981 if (!priv->phy) {
982 ret = -EPROBE_DEFER;
983 goto init_fail;
984 }
985 }
986
987 INIT_WORK(&priv->tx_timeout_task, hip04_tx_timeout_task);
988
989 ndev->netdev_ops = &hip04_netdev_ops;
990 ndev->ethtool_ops = &hip04_ethtool_ops;
991 ndev->watchdog_timeo = TX_TIMEOUT;
992 ndev->priv_flags |= IFF_UNICAST_FLT;
993 ndev->irq = irq;
994 netif_napi_add(ndev, &priv->napi, hip04_rx_poll);
995
996 hip04_reset_dreq(priv);
997 hip04_reset_ppe(priv);
998 if (priv->phy_mode == PHY_INTERFACE_MODE_MII)
999 hip04_config_port(ndev, SPEED_100, DUPLEX_FULL);
1000
1001 hip04_config_fifo(priv);
1002 eth_hw_addr_random(ndev);
1003 hip04_update_mac_address(ndev);
1004
1005 ret = hip04_alloc_ring(ndev, d);
1006 if (ret) {
1007 netdev_err(ndev, "alloc ring fail\n");
1008 goto alloc_fail;
1009 }
1010
1011 ret = register_netdev(ndev);
1012 if (ret)
1013 goto alloc_fail;
1014
1015 return 0;
1016
1017alloc_fail:
1018 hip04_free_ring(ndev, d);
1019init_fail:
1020 of_node_put(priv->phy_node);
1021 free_netdev(ndev);
1022 return ret;
1023}
1024
1025static void hip04_remove(struct platform_device *pdev)
1026{
1027 struct net_device *ndev = platform_get_drvdata(pdev);
1028 struct hip04_priv *priv = netdev_priv(ndev);
1029 struct device *d = &pdev->dev;
1030
1031 if (priv->phy)
1032 phy_disconnect(priv->phy);
1033
1034 hip04_free_ring(ndev, d);
1035 unregister_netdev(ndev);
1036 of_node_put(priv->phy_node);
1037 cancel_work_sync(&priv->tx_timeout_task);
1038 free_netdev(ndev);
1039}
1040
1041static const struct of_device_id hip04_mac_match[] = {
1042 { .compatible = "hisilicon,hip04-mac" },
1043 { }
1044};
1045
1046MODULE_DEVICE_TABLE(of, hip04_mac_match);
1047
1048static struct platform_driver hip04_mac_driver = {
1049 .probe = hip04_mac_probe,
1050 .remove = hip04_remove,
1051 .driver = {
1052 .name = DRV_NAME,
1053 .of_match_table = hip04_mac_match,
1054 },
1055};
1056module_platform_driver(hip04_mac_driver);
1057
1058MODULE_DESCRIPTION("HISILICON P04 Ethernet driver");
1059MODULE_LICENSE("GPL");
1
2/* Copyright (c) 2014 Linaro Ltd.
3 * Copyright (c) 2014 Hisilicon Limited.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 */
10
11#include <linux/module.h>
12#include <linux/etherdevice.h>
13#include <linux/platform_device.h>
14#include <linux/interrupt.h>
15#include <linux/ktime.h>
16#include <linux/of_address.h>
17#include <linux/phy.h>
18#include <linux/of_mdio.h>
19#include <linux/of_net.h>
20#include <linux/mfd/syscon.h>
21#include <linux/regmap.h>
22
23#define PPE_CFG_RX_ADDR 0x100
24#define PPE_CFG_POOL_GRP 0x300
25#define PPE_CFG_RX_BUF_SIZE 0x400
26#define PPE_CFG_RX_FIFO_SIZE 0x500
27#define PPE_CURR_BUF_CNT 0xa200
28
29#define GE_DUPLEX_TYPE 0x08
30#define GE_MAX_FRM_SIZE_REG 0x3c
31#define GE_PORT_MODE 0x40
32#define GE_PORT_EN 0x44
33#define GE_SHORT_RUNTS_THR_REG 0x50
34#define GE_TX_LOCAL_PAGE_REG 0x5c
35#define GE_TRANSMIT_CONTROL_REG 0x60
36#define GE_CF_CRC_STRIP_REG 0x1b0
37#define GE_MODE_CHANGE_REG 0x1b4
38#define GE_RECV_CONTROL_REG 0x1e0
39#define GE_STATION_MAC_ADDRESS 0x210
40#define PPE_CFG_CPU_ADD_ADDR 0x580
41#define PPE_CFG_MAX_FRAME_LEN_REG 0x408
42#define PPE_CFG_BUS_CTRL_REG 0x424
43#define PPE_CFG_RX_CTRL_REG 0x428
44#define PPE_CFG_RX_PKT_MODE_REG 0x438
45#define PPE_CFG_QOS_VMID_GEN 0x500
46#define PPE_CFG_RX_PKT_INT 0x538
47#define PPE_INTEN 0x600
48#define PPE_INTSTS 0x608
49#define PPE_RINT 0x604
50#define PPE_CFG_STS_MODE 0x700
51#define PPE_HIS_RX_PKT_CNT 0x804
52
53/* REG_INTERRUPT */
54#define RCV_INT BIT(10)
55#define RCV_NOBUF BIT(8)
56#define RCV_DROP BIT(7)
57#define TX_DROP BIT(6)
58#define DEF_INT_ERR (RCV_NOBUF | RCV_DROP | TX_DROP)
59#define DEF_INT_MASK (RCV_INT | DEF_INT_ERR)
60
61/* TX descriptor config */
62#define TX_FREE_MEM BIT(0)
63#define TX_READ_ALLOC_L3 BIT(1)
64#define TX_FINISH_CACHE_INV BIT(2)
65#define TX_CLEAR_WB BIT(4)
66#define TX_L3_CHECKSUM BIT(5)
67#define TX_LOOP_BACK BIT(11)
68
69/* RX error */
70#define RX_PKT_DROP BIT(0)
71#define RX_L2_ERR BIT(1)
72#define RX_PKT_ERR (RX_PKT_DROP | RX_L2_ERR)
73
74#define SGMII_SPEED_1000 0x08
75#define SGMII_SPEED_100 0x07
76#define SGMII_SPEED_10 0x06
77#define MII_SPEED_100 0x01
78#define MII_SPEED_10 0x00
79
80#define GE_DUPLEX_FULL BIT(0)
81#define GE_DUPLEX_HALF 0x00
82#define GE_MODE_CHANGE_EN BIT(0)
83
84#define GE_TX_AUTO_NEG BIT(5)
85#define GE_TX_ADD_CRC BIT(6)
86#define GE_TX_SHORT_PAD_THROUGH BIT(7)
87
88#define GE_RX_STRIP_CRC BIT(0)
89#define GE_RX_STRIP_PAD BIT(3)
90#define GE_RX_PAD_EN BIT(4)
91
92#define GE_AUTO_NEG_CTL BIT(0)
93
94#define GE_RX_INT_THRESHOLD BIT(6)
95#define GE_RX_TIMEOUT 0x04
96
97#define GE_RX_PORT_EN BIT(1)
98#define GE_TX_PORT_EN BIT(2)
99
100#define PPE_CFG_STS_RX_PKT_CNT_RC BIT(12)
101
102#define PPE_CFG_RX_PKT_ALIGN BIT(18)
103#define PPE_CFG_QOS_VMID_MODE BIT(14)
104#define PPE_CFG_QOS_VMID_GRP_SHIFT 8
105
106#define PPE_CFG_RX_FIFO_FSFU BIT(11)
107#define PPE_CFG_RX_DEPTH_SHIFT 16
108#define PPE_CFG_RX_START_SHIFT 0
109#define PPE_CFG_RX_CTRL_ALIGN_SHIFT 11
110
111#define PPE_CFG_BUS_LOCAL_REL BIT(14)
112#define PPE_CFG_BUS_BIG_ENDIEN BIT(0)
113
114#define RX_DESC_NUM 128
115#define TX_DESC_NUM 256
116#define TX_NEXT(N) (((N) + 1) & (TX_DESC_NUM-1))
117#define RX_NEXT(N) (((N) + 1) & (RX_DESC_NUM-1))
118
119#define GMAC_PPE_RX_PKT_MAX_LEN 379
120#define GMAC_MAX_PKT_LEN 1516
121#define GMAC_MIN_PKT_LEN 31
122#define RX_BUF_SIZE 1600
123#define RESET_TIMEOUT 1000
124#define TX_TIMEOUT (6 * HZ)
125
126#define DRV_NAME "hip04-ether"
127#define DRV_VERSION "v1.0"
128
129#define HIP04_MAX_TX_COALESCE_USECS 200
130#define HIP04_MIN_TX_COALESCE_USECS 100
131#define HIP04_MAX_TX_COALESCE_FRAMES 200
132#define HIP04_MIN_TX_COALESCE_FRAMES 100
133
134struct tx_desc {
135 u32 send_addr;
136 u32 send_size;
137 u32 next_addr;
138 u32 cfg;
139 u32 wb_addr;
140} __aligned(64);
141
142struct rx_desc {
143 u16 reserved_16;
144 u16 pkt_len;
145 u32 reserve1[3];
146 u32 pkt_err;
147 u32 reserve2[4];
148};
149
150struct hip04_priv {
151 void __iomem *base;
152 int phy_mode;
153 int chan;
154 unsigned int port;
155 unsigned int speed;
156 unsigned int duplex;
157 unsigned int reg_inten;
158
159 struct napi_struct napi;
160 struct net_device *ndev;
161
162 struct tx_desc *tx_desc;
163 dma_addr_t tx_desc_dma;
164 struct sk_buff *tx_skb[TX_DESC_NUM];
165 dma_addr_t tx_phys[TX_DESC_NUM];
166 unsigned int tx_head;
167
168 int tx_coalesce_frames;
169 int tx_coalesce_usecs;
170 struct hrtimer tx_coalesce_timer;
171
172 unsigned char *rx_buf[RX_DESC_NUM];
173 dma_addr_t rx_phys[RX_DESC_NUM];
174 unsigned int rx_head;
175 unsigned int rx_buf_size;
176
177 struct device_node *phy_node;
178 struct phy_device *phy;
179 struct regmap *map;
180 struct work_struct tx_timeout_task;
181
182 /* written only by tx cleanup */
183 unsigned int tx_tail ____cacheline_aligned_in_smp;
184};
185
186static inline unsigned int tx_count(unsigned int head, unsigned int tail)
187{
188 return (head - tail) % (TX_DESC_NUM - 1);
189}
190
191static void hip04_config_port(struct net_device *ndev, u32 speed, u32 duplex)
192{
193 struct hip04_priv *priv = netdev_priv(ndev);
194 u32 val;
195
196 priv->speed = speed;
197 priv->duplex = duplex;
198
199 switch (priv->phy_mode) {
200 case PHY_INTERFACE_MODE_SGMII:
201 if (speed == SPEED_1000)
202 val = SGMII_SPEED_1000;
203 else if (speed == SPEED_100)
204 val = SGMII_SPEED_100;
205 else
206 val = SGMII_SPEED_10;
207 break;
208 case PHY_INTERFACE_MODE_MII:
209 if (speed == SPEED_100)
210 val = MII_SPEED_100;
211 else
212 val = MII_SPEED_10;
213 break;
214 default:
215 netdev_warn(ndev, "not supported mode\n");
216 val = MII_SPEED_10;
217 break;
218 }
219 writel_relaxed(val, priv->base + GE_PORT_MODE);
220
221 val = duplex ? GE_DUPLEX_FULL : GE_DUPLEX_HALF;
222 writel_relaxed(val, priv->base + GE_DUPLEX_TYPE);
223
224 val = GE_MODE_CHANGE_EN;
225 writel_relaxed(val, priv->base + GE_MODE_CHANGE_REG);
226}
227
228static void hip04_reset_ppe(struct hip04_priv *priv)
229{
230 u32 val, tmp, timeout = 0;
231
232 do {
233 regmap_read(priv->map, priv->port * 4 + PPE_CURR_BUF_CNT, &val);
234 regmap_read(priv->map, priv->port * 4 + PPE_CFG_RX_ADDR, &tmp);
235 if (timeout++ > RESET_TIMEOUT)
236 break;
237 } while (val & 0xfff);
238}
239
240static void hip04_config_fifo(struct hip04_priv *priv)
241{
242 u32 val;
243
244 val = readl_relaxed(priv->base + PPE_CFG_STS_MODE);
245 val |= PPE_CFG_STS_RX_PKT_CNT_RC;
246 writel_relaxed(val, priv->base + PPE_CFG_STS_MODE);
247
248 val = BIT(priv->port);
249 regmap_write(priv->map, priv->port * 4 + PPE_CFG_POOL_GRP, val);
250
251 val = priv->port << PPE_CFG_QOS_VMID_GRP_SHIFT;
252 val |= PPE_CFG_QOS_VMID_MODE;
253 writel_relaxed(val, priv->base + PPE_CFG_QOS_VMID_GEN);
254
255 val = RX_BUF_SIZE;
256 regmap_write(priv->map, priv->port * 4 + PPE_CFG_RX_BUF_SIZE, val);
257
258 val = RX_DESC_NUM << PPE_CFG_RX_DEPTH_SHIFT;
259 val |= PPE_CFG_RX_FIFO_FSFU;
260 val |= priv->chan << PPE_CFG_RX_START_SHIFT;
261 regmap_write(priv->map, priv->port * 4 + PPE_CFG_RX_FIFO_SIZE, val);
262
263 val = NET_IP_ALIGN << PPE_CFG_RX_CTRL_ALIGN_SHIFT;
264 writel_relaxed(val, priv->base + PPE_CFG_RX_CTRL_REG);
265
266 val = PPE_CFG_RX_PKT_ALIGN;
267 writel_relaxed(val, priv->base + PPE_CFG_RX_PKT_MODE_REG);
268
269 val = PPE_CFG_BUS_LOCAL_REL | PPE_CFG_BUS_BIG_ENDIEN;
270 writel_relaxed(val, priv->base + PPE_CFG_BUS_CTRL_REG);
271
272 val = GMAC_PPE_RX_PKT_MAX_LEN;
273 writel_relaxed(val, priv->base + PPE_CFG_MAX_FRAME_LEN_REG);
274
275 val = GMAC_MAX_PKT_LEN;
276 writel_relaxed(val, priv->base + GE_MAX_FRM_SIZE_REG);
277
278 val = GMAC_MIN_PKT_LEN;
279 writel_relaxed(val, priv->base + GE_SHORT_RUNTS_THR_REG);
280
281 val = readl_relaxed(priv->base + GE_TRANSMIT_CONTROL_REG);
282 val |= GE_TX_AUTO_NEG | GE_TX_ADD_CRC | GE_TX_SHORT_PAD_THROUGH;
283 writel_relaxed(val, priv->base + GE_TRANSMIT_CONTROL_REG);
284
285 val = GE_RX_STRIP_CRC;
286 writel_relaxed(val, priv->base + GE_CF_CRC_STRIP_REG);
287
288 val = readl_relaxed(priv->base + GE_RECV_CONTROL_REG);
289 val |= GE_RX_STRIP_PAD | GE_RX_PAD_EN;
290 writel_relaxed(val, priv->base + GE_RECV_CONTROL_REG);
291
292 val = GE_AUTO_NEG_CTL;
293 writel_relaxed(val, priv->base + GE_TX_LOCAL_PAGE_REG);
294}
295
296static void hip04_mac_enable(struct net_device *ndev)
297{
298 struct hip04_priv *priv = netdev_priv(ndev);
299 u32 val;
300
301 /* enable tx & rx */
302 val = readl_relaxed(priv->base + GE_PORT_EN);
303 val |= GE_RX_PORT_EN | GE_TX_PORT_EN;
304 writel_relaxed(val, priv->base + GE_PORT_EN);
305
306 /* clear rx int */
307 val = RCV_INT;
308 writel_relaxed(val, priv->base + PPE_RINT);
309
310 /* config recv int */
311 val = GE_RX_INT_THRESHOLD | GE_RX_TIMEOUT;
312 writel_relaxed(val, priv->base + PPE_CFG_RX_PKT_INT);
313
314 /* enable interrupt */
315 priv->reg_inten = DEF_INT_MASK;
316 writel_relaxed(priv->reg_inten, priv->base + PPE_INTEN);
317}
318
319static void hip04_mac_disable(struct net_device *ndev)
320{
321 struct hip04_priv *priv = netdev_priv(ndev);
322 u32 val;
323
324 /* disable int */
325 priv->reg_inten &= ~(DEF_INT_MASK);
326 writel_relaxed(priv->reg_inten, priv->base + PPE_INTEN);
327
328 /* disable tx & rx */
329 val = readl_relaxed(priv->base + GE_PORT_EN);
330 val &= ~(GE_RX_PORT_EN | GE_TX_PORT_EN);
331 writel_relaxed(val, priv->base + GE_PORT_EN);
332}
333
334static void hip04_set_xmit_desc(struct hip04_priv *priv, dma_addr_t phys)
335{
336 writel(phys, priv->base + PPE_CFG_CPU_ADD_ADDR);
337}
338
339static void hip04_set_recv_desc(struct hip04_priv *priv, dma_addr_t phys)
340{
341 regmap_write(priv->map, priv->port * 4 + PPE_CFG_RX_ADDR, phys);
342}
343
344static u32 hip04_recv_cnt(struct hip04_priv *priv)
345{
346 return readl(priv->base + PPE_HIS_RX_PKT_CNT);
347}
348
349static void hip04_update_mac_address(struct net_device *ndev)
350{
351 struct hip04_priv *priv = netdev_priv(ndev);
352
353 writel_relaxed(((ndev->dev_addr[0] << 8) | (ndev->dev_addr[1])),
354 priv->base + GE_STATION_MAC_ADDRESS);
355 writel_relaxed(((ndev->dev_addr[2] << 24) | (ndev->dev_addr[3] << 16) |
356 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5])),
357 priv->base + GE_STATION_MAC_ADDRESS + 4);
358}
359
360static int hip04_set_mac_address(struct net_device *ndev, void *addr)
361{
362 eth_mac_addr(ndev, addr);
363 hip04_update_mac_address(ndev);
364 return 0;
365}
366
367static int hip04_tx_reclaim(struct net_device *ndev, bool force)
368{
369 struct hip04_priv *priv = netdev_priv(ndev);
370 unsigned tx_tail = priv->tx_tail;
371 struct tx_desc *desc;
372 unsigned int bytes_compl = 0, pkts_compl = 0;
373 unsigned int count;
374
375 smp_rmb();
376 count = tx_count(ACCESS_ONCE(priv->tx_head), tx_tail);
377 if (count == 0)
378 goto out;
379
380 while (count) {
381 desc = &priv->tx_desc[tx_tail];
382 if (desc->send_addr != 0) {
383 if (force)
384 desc->send_addr = 0;
385 else
386 break;
387 }
388
389 if (priv->tx_phys[tx_tail]) {
390 dma_unmap_single(&ndev->dev, priv->tx_phys[tx_tail],
391 priv->tx_skb[tx_tail]->len,
392 DMA_TO_DEVICE);
393 priv->tx_phys[tx_tail] = 0;
394 }
395 pkts_compl++;
396 bytes_compl += priv->tx_skb[tx_tail]->len;
397 dev_kfree_skb(priv->tx_skb[tx_tail]);
398 priv->tx_skb[tx_tail] = NULL;
399 tx_tail = TX_NEXT(tx_tail);
400 count--;
401 }
402
403 priv->tx_tail = tx_tail;
404 smp_wmb(); /* Ensure tx_tail visible to xmit */
405
406out:
407 if (pkts_compl || bytes_compl)
408 netdev_completed_queue(ndev, pkts_compl, bytes_compl);
409
410 if (unlikely(netif_queue_stopped(ndev)) && (count < (TX_DESC_NUM - 1)))
411 netif_wake_queue(ndev);
412
413 return count;
414}
415
416static void hip04_start_tx_timer(struct hip04_priv *priv)
417{
418 unsigned long ns = priv->tx_coalesce_usecs * NSEC_PER_USEC / 2;
419
420 /* allow timer to fire after half the time at the earliest */
421 hrtimer_start_range_ns(&priv->tx_coalesce_timer, ns_to_ktime(ns),
422 ns, HRTIMER_MODE_REL);
423}
424
425static int hip04_mac_start_xmit(struct sk_buff *skb, struct net_device *ndev)
426{
427 struct hip04_priv *priv = netdev_priv(ndev);
428 struct net_device_stats *stats = &ndev->stats;
429 unsigned int tx_head = priv->tx_head, count;
430 struct tx_desc *desc = &priv->tx_desc[tx_head];
431 dma_addr_t phys;
432
433 smp_rmb();
434 count = tx_count(tx_head, ACCESS_ONCE(priv->tx_tail));
435 if (count == (TX_DESC_NUM - 1)) {
436 netif_stop_queue(ndev);
437 return NETDEV_TX_BUSY;
438 }
439
440 phys = dma_map_single(&ndev->dev, skb->data, skb->len, DMA_TO_DEVICE);
441 if (dma_mapping_error(&ndev->dev, phys)) {
442 dev_kfree_skb(skb);
443 return NETDEV_TX_OK;
444 }
445
446 priv->tx_skb[tx_head] = skb;
447 priv->tx_phys[tx_head] = phys;
448 desc->send_addr = cpu_to_be32(phys);
449 desc->send_size = cpu_to_be32(skb->len);
450 desc->cfg = cpu_to_be32(TX_CLEAR_WB | TX_FINISH_CACHE_INV);
451 phys = priv->tx_desc_dma + tx_head * sizeof(struct tx_desc);
452 desc->wb_addr = cpu_to_be32(phys);
453 skb_tx_timestamp(skb);
454
455 hip04_set_xmit_desc(priv, phys);
456 priv->tx_head = TX_NEXT(tx_head);
457 count++;
458 netdev_sent_queue(ndev, skb->len);
459
460 stats->tx_bytes += skb->len;
461 stats->tx_packets++;
462
463 /* Ensure tx_head update visible to tx reclaim */
464 smp_wmb();
465
466 /* queue is getting full, better start cleaning up now */
467 if (count >= priv->tx_coalesce_frames) {
468 if (napi_schedule_prep(&priv->napi)) {
469 /* disable rx interrupt and timer */
470 priv->reg_inten &= ~(RCV_INT);
471 writel_relaxed(DEF_INT_MASK & ~RCV_INT,
472 priv->base + PPE_INTEN);
473 hrtimer_cancel(&priv->tx_coalesce_timer);
474 __napi_schedule(&priv->napi);
475 }
476 } else if (!hrtimer_is_queued(&priv->tx_coalesce_timer)) {
477 /* cleanup not pending yet, start a new timer */
478 hip04_start_tx_timer(priv);
479 }
480
481 return NETDEV_TX_OK;
482}
483
484static int hip04_rx_poll(struct napi_struct *napi, int budget)
485{
486 struct hip04_priv *priv = container_of(napi, struct hip04_priv, napi);
487 struct net_device *ndev = priv->ndev;
488 struct net_device_stats *stats = &ndev->stats;
489 unsigned int cnt = hip04_recv_cnt(priv);
490 struct rx_desc *desc;
491 struct sk_buff *skb;
492 unsigned char *buf;
493 bool last = false;
494 dma_addr_t phys;
495 int rx = 0;
496 int tx_remaining;
497 u16 len;
498 u32 err;
499
500 while (cnt && !last) {
501 buf = priv->rx_buf[priv->rx_head];
502 skb = build_skb(buf, priv->rx_buf_size);
503 if (unlikely(!skb)) {
504 net_dbg_ratelimited("build_skb failed\n");
505 goto refill;
506 }
507
508 dma_unmap_single(&ndev->dev, priv->rx_phys[priv->rx_head],
509 RX_BUF_SIZE, DMA_FROM_DEVICE);
510 priv->rx_phys[priv->rx_head] = 0;
511
512 desc = (struct rx_desc *)skb->data;
513 len = be16_to_cpu(desc->pkt_len);
514 err = be32_to_cpu(desc->pkt_err);
515
516 if (0 == len) {
517 dev_kfree_skb_any(skb);
518 last = true;
519 } else if ((err & RX_PKT_ERR) || (len >= GMAC_MAX_PKT_LEN)) {
520 dev_kfree_skb_any(skb);
521 stats->rx_dropped++;
522 stats->rx_errors++;
523 } else {
524 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
525 skb_put(skb, len);
526 skb->protocol = eth_type_trans(skb, ndev);
527 napi_gro_receive(&priv->napi, skb);
528 stats->rx_packets++;
529 stats->rx_bytes += len;
530 rx++;
531 }
532
533refill:
534 buf = netdev_alloc_frag(priv->rx_buf_size);
535 if (!buf)
536 goto done;
537 phys = dma_map_single(&ndev->dev, buf,
538 RX_BUF_SIZE, DMA_FROM_DEVICE);
539 if (dma_mapping_error(&ndev->dev, phys))
540 goto done;
541 priv->rx_buf[priv->rx_head] = buf;
542 priv->rx_phys[priv->rx_head] = phys;
543 hip04_set_recv_desc(priv, phys);
544
545 priv->rx_head = RX_NEXT(priv->rx_head);
546 if (rx >= budget)
547 goto done;
548
549 if (--cnt == 0)
550 cnt = hip04_recv_cnt(priv);
551 }
552
553 if (!(priv->reg_inten & RCV_INT)) {
554 /* enable rx interrupt */
555 priv->reg_inten |= RCV_INT;
556 writel_relaxed(priv->reg_inten, priv->base + PPE_INTEN);
557 }
558 napi_complete(napi);
559done:
560 /* clean up tx descriptors and start a new timer if necessary */
561 tx_remaining = hip04_tx_reclaim(ndev, false);
562 if (rx < budget && tx_remaining)
563 hip04_start_tx_timer(priv);
564
565 return rx;
566}
567
568static irqreturn_t hip04_mac_interrupt(int irq, void *dev_id)
569{
570 struct net_device *ndev = (struct net_device *)dev_id;
571 struct hip04_priv *priv = netdev_priv(ndev);
572 struct net_device_stats *stats = &ndev->stats;
573 u32 ists = readl_relaxed(priv->base + PPE_INTSTS);
574
575 if (!ists)
576 return IRQ_NONE;
577
578 writel_relaxed(DEF_INT_MASK, priv->base + PPE_RINT);
579
580 if (unlikely(ists & DEF_INT_ERR)) {
581 if (ists & (RCV_NOBUF | RCV_DROP)) {
582 stats->rx_errors++;
583 stats->rx_dropped++;
584 netdev_err(ndev, "rx drop\n");
585 }
586 if (ists & TX_DROP) {
587 stats->tx_dropped++;
588 netdev_err(ndev, "tx drop\n");
589 }
590 }
591
592 if (ists & RCV_INT && napi_schedule_prep(&priv->napi)) {
593 /* disable rx interrupt */
594 priv->reg_inten &= ~(RCV_INT);
595 writel_relaxed(DEF_INT_MASK & ~RCV_INT, priv->base + PPE_INTEN);
596 hrtimer_cancel(&priv->tx_coalesce_timer);
597 __napi_schedule(&priv->napi);
598 }
599
600 return IRQ_HANDLED;
601}
602
603static enum hrtimer_restart tx_done(struct hrtimer *hrtimer)
604{
605 struct hip04_priv *priv;
606
607 priv = container_of(hrtimer, struct hip04_priv, tx_coalesce_timer);
608
609 if (napi_schedule_prep(&priv->napi)) {
610 /* disable rx interrupt */
611 priv->reg_inten &= ~(RCV_INT);
612 writel_relaxed(DEF_INT_MASK & ~RCV_INT, priv->base + PPE_INTEN);
613 __napi_schedule(&priv->napi);
614 }
615
616 return HRTIMER_NORESTART;
617}
618
619static void hip04_adjust_link(struct net_device *ndev)
620{
621 struct hip04_priv *priv = netdev_priv(ndev);
622 struct phy_device *phy = priv->phy;
623
624 if ((priv->speed != phy->speed) || (priv->duplex != phy->duplex)) {
625 hip04_config_port(ndev, phy->speed, phy->duplex);
626 phy_print_status(phy);
627 }
628}
629
630static int hip04_mac_open(struct net_device *ndev)
631{
632 struct hip04_priv *priv = netdev_priv(ndev);
633 int i;
634
635 priv->rx_head = 0;
636 priv->tx_head = 0;
637 priv->tx_tail = 0;
638 hip04_reset_ppe(priv);
639
640 for (i = 0; i < RX_DESC_NUM; i++) {
641 dma_addr_t phys;
642
643 phys = dma_map_single(&ndev->dev, priv->rx_buf[i],
644 RX_BUF_SIZE, DMA_FROM_DEVICE);
645 if (dma_mapping_error(&ndev->dev, phys))
646 return -EIO;
647
648 priv->rx_phys[i] = phys;
649 hip04_set_recv_desc(priv, phys);
650 }
651
652 if (priv->phy)
653 phy_start(priv->phy);
654
655 netdev_reset_queue(ndev);
656 netif_start_queue(ndev);
657 hip04_mac_enable(ndev);
658 napi_enable(&priv->napi);
659
660 return 0;
661}
662
663static int hip04_mac_stop(struct net_device *ndev)
664{
665 struct hip04_priv *priv = netdev_priv(ndev);
666 int i;
667
668 napi_disable(&priv->napi);
669 netif_stop_queue(ndev);
670 hip04_mac_disable(ndev);
671 hip04_tx_reclaim(ndev, true);
672 hip04_reset_ppe(priv);
673
674 if (priv->phy)
675 phy_stop(priv->phy);
676
677 for (i = 0; i < RX_DESC_NUM; i++) {
678 if (priv->rx_phys[i]) {
679 dma_unmap_single(&ndev->dev, priv->rx_phys[i],
680 RX_BUF_SIZE, DMA_FROM_DEVICE);
681 priv->rx_phys[i] = 0;
682 }
683 }
684
685 return 0;
686}
687
688static void hip04_timeout(struct net_device *ndev)
689{
690 struct hip04_priv *priv = netdev_priv(ndev);
691
692 schedule_work(&priv->tx_timeout_task);
693}
694
695static void hip04_tx_timeout_task(struct work_struct *work)
696{
697 struct hip04_priv *priv;
698
699 priv = container_of(work, struct hip04_priv, tx_timeout_task);
700 hip04_mac_stop(priv->ndev);
701 hip04_mac_open(priv->ndev);
702}
703
704static struct net_device_stats *hip04_get_stats(struct net_device *ndev)
705{
706 return &ndev->stats;
707}
708
709static int hip04_get_coalesce(struct net_device *netdev,
710 struct ethtool_coalesce *ec)
711{
712 struct hip04_priv *priv = netdev_priv(netdev);
713
714 ec->tx_coalesce_usecs = priv->tx_coalesce_usecs;
715 ec->tx_max_coalesced_frames = priv->tx_coalesce_frames;
716
717 return 0;
718}
719
720static int hip04_set_coalesce(struct net_device *netdev,
721 struct ethtool_coalesce *ec)
722{
723 struct hip04_priv *priv = netdev_priv(netdev);
724
725 /* Check not supported parameters */
726 if ((ec->rx_max_coalesced_frames) || (ec->rx_coalesce_usecs_irq) ||
727 (ec->rx_max_coalesced_frames_irq) || (ec->tx_coalesce_usecs_irq) ||
728 (ec->use_adaptive_rx_coalesce) || (ec->use_adaptive_tx_coalesce) ||
729 (ec->pkt_rate_low) || (ec->rx_coalesce_usecs_low) ||
730 (ec->rx_max_coalesced_frames_low) || (ec->tx_coalesce_usecs_high) ||
731 (ec->tx_max_coalesced_frames_low) || (ec->pkt_rate_high) ||
732 (ec->tx_coalesce_usecs_low) || (ec->rx_coalesce_usecs_high) ||
733 (ec->rx_max_coalesced_frames_high) || (ec->rx_coalesce_usecs) ||
734 (ec->tx_max_coalesced_frames_irq) ||
735 (ec->stats_block_coalesce_usecs) ||
736 (ec->tx_max_coalesced_frames_high) || (ec->rate_sample_interval))
737 return -EOPNOTSUPP;
738
739 if ((ec->tx_coalesce_usecs > HIP04_MAX_TX_COALESCE_USECS ||
740 ec->tx_coalesce_usecs < HIP04_MIN_TX_COALESCE_USECS) ||
741 (ec->tx_max_coalesced_frames > HIP04_MAX_TX_COALESCE_FRAMES ||
742 ec->tx_max_coalesced_frames < HIP04_MIN_TX_COALESCE_FRAMES))
743 return -EINVAL;
744
745 priv->tx_coalesce_usecs = ec->tx_coalesce_usecs;
746 priv->tx_coalesce_frames = ec->tx_max_coalesced_frames;
747
748 return 0;
749}
750
751static void hip04_get_drvinfo(struct net_device *netdev,
752 struct ethtool_drvinfo *drvinfo)
753{
754 strlcpy(drvinfo->driver, DRV_NAME, sizeof(drvinfo->driver));
755 strlcpy(drvinfo->version, DRV_VERSION, sizeof(drvinfo->version));
756}
757
758static const struct ethtool_ops hip04_ethtool_ops = {
759 .get_coalesce = hip04_get_coalesce,
760 .set_coalesce = hip04_set_coalesce,
761 .get_drvinfo = hip04_get_drvinfo,
762};
763
764static const struct net_device_ops hip04_netdev_ops = {
765 .ndo_open = hip04_mac_open,
766 .ndo_stop = hip04_mac_stop,
767 .ndo_get_stats = hip04_get_stats,
768 .ndo_start_xmit = hip04_mac_start_xmit,
769 .ndo_set_mac_address = hip04_set_mac_address,
770 .ndo_tx_timeout = hip04_timeout,
771 .ndo_validate_addr = eth_validate_addr,
772};
773
774static int hip04_alloc_ring(struct net_device *ndev, struct device *d)
775{
776 struct hip04_priv *priv = netdev_priv(ndev);
777 int i;
778
779 priv->tx_desc = dma_alloc_coherent(d,
780 TX_DESC_NUM * sizeof(struct tx_desc),
781 &priv->tx_desc_dma, GFP_KERNEL);
782 if (!priv->tx_desc)
783 return -ENOMEM;
784
785 priv->rx_buf_size = RX_BUF_SIZE +
786 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
787 for (i = 0; i < RX_DESC_NUM; i++) {
788 priv->rx_buf[i] = netdev_alloc_frag(priv->rx_buf_size);
789 if (!priv->rx_buf[i])
790 return -ENOMEM;
791 }
792
793 return 0;
794}
795
796static void hip04_free_ring(struct net_device *ndev, struct device *d)
797{
798 struct hip04_priv *priv = netdev_priv(ndev);
799 int i;
800
801 for (i = 0; i < RX_DESC_NUM; i++)
802 if (priv->rx_buf[i])
803 skb_free_frag(priv->rx_buf[i]);
804
805 for (i = 0; i < TX_DESC_NUM; i++)
806 if (priv->tx_skb[i])
807 dev_kfree_skb_any(priv->tx_skb[i]);
808
809 dma_free_coherent(d, TX_DESC_NUM * sizeof(struct tx_desc),
810 priv->tx_desc, priv->tx_desc_dma);
811}
812
813static int hip04_mac_probe(struct platform_device *pdev)
814{
815 struct device *d = &pdev->dev;
816 struct device_node *node = d->of_node;
817 struct of_phandle_args arg;
818 struct net_device *ndev;
819 struct hip04_priv *priv;
820 struct resource *res;
821 int irq;
822 int ret;
823
824 ndev = alloc_etherdev(sizeof(struct hip04_priv));
825 if (!ndev)
826 return -ENOMEM;
827
828 priv = netdev_priv(ndev);
829 priv->ndev = ndev;
830 platform_set_drvdata(pdev, ndev);
831 SET_NETDEV_DEV(ndev, &pdev->dev);
832
833 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
834 priv->base = devm_ioremap_resource(d, res);
835 if (IS_ERR(priv->base)) {
836 ret = PTR_ERR(priv->base);
837 goto init_fail;
838 }
839
840 ret = of_parse_phandle_with_fixed_args(node, "port-handle", 2, 0, &arg);
841 if (ret < 0) {
842 dev_warn(d, "no port-handle\n");
843 goto init_fail;
844 }
845
846 priv->port = arg.args[0];
847 priv->chan = arg.args[1] * RX_DESC_NUM;
848
849 hrtimer_init(&priv->tx_coalesce_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
850
851 /* BQL will try to keep the TX queue as short as possible, but it can't
852 * be faster than tx_coalesce_usecs, so we need a fast timeout here,
853 * but also long enough to gather up enough frames to ensure we don't
854 * get more interrupts than necessary.
855 * 200us is enough for 16 frames of 1500 bytes at gigabit ethernet rate
856 */
857 priv->tx_coalesce_frames = TX_DESC_NUM * 3 / 4;
858 priv->tx_coalesce_usecs = 200;
859 priv->tx_coalesce_timer.function = tx_done;
860
861 priv->map = syscon_node_to_regmap(arg.np);
862 if (IS_ERR(priv->map)) {
863 dev_warn(d, "no syscon hisilicon,hip04-ppe\n");
864 ret = PTR_ERR(priv->map);
865 goto init_fail;
866 }
867
868 priv->phy_mode = of_get_phy_mode(node);
869 if (priv->phy_mode < 0) {
870 dev_warn(d, "not find phy-mode\n");
871 ret = -EINVAL;
872 goto init_fail;
873 }
874
875 irq = platform_get_irq(pdev, 0);
876 if (irq <= 0) {
877 ret = -EINVAL;
878 goto init_fail;
879 }
880
881 ret = devm_request_irq(d, irq, hip04_mac_interrupt,
882 0, pdev->name, ndev);
883 if (ret) {
884 netdev_err(ndev, "devm_request_irq failed\n");
885 goto init_fail;
886 }
887
888 priv->phy_node = of_parse_phandle(node, "phy-handle", 0);
889 if (priv->phy_node) {
890 priv->phy = of_phy_connect(ndev, priv->phy_node,
891 &hip04_adjust_link,
892 0, priv->phy_mode);
893 if (!priv->phy) {
894 ret = -EPROBE_DEFER;
895 goto init_fail;
896 }
897 }
898
899 INIT_WORK(&priv->tx_timeout_task, hip04_tx_timeout_task);
900
901 ndev->netdev_ops = &hip04_netdev_ops;
902 ndev->ethtool_ops = &hip04_ethtool_ops;
903 ndev->watchdog_timeo = TX_TIMEOUT;
904 ndev->priv_flags |= IFF_UNICAST_FLT;
905 ndev->irq = irq;
906 netif_napi_add(ndev, &priv->napi, hip04_rx_poll, NAPI_POLL_WEIGHT);
907
908 hip04_reset_ppe(priv);
909 if (priv->phy_mode == PHY_INTERFACE_MODE_MII)
910 hip04_config_port(ndev, SPEED_100, DUPLEX_FULL);
911
912 hip04_config_fifo(priv);
913 random_ether_addr(ndev->dev_addr);
914 hip04_update_mac_address(ndev);
915
916 ret = hip04_alloc_ring(ndev, d);
917 if (ret) {
918 netdev_err(ndev, "alloc ring fail\n");
919 goto alloc_fail;
920 }
921
922 ret = register_netdev(ndev);
923 if (ret) {
924 free_netdev(ndev);
925 goto alloc_fail;
926 }
927
928 return 0;
929
930alloc_fail:
931 hip04_free_ring(ndev, d);
932init_fail:
933 of_node_put(priv->phy_node);
934 free_netdev(ndev);
935 return ret;
936}
937
938static int hip04_remove(struct platform_device *pdev)
939{
940 struct net_device *ndev = platform_get_drvdata(pdev);
941 struct hip04_priv *priv = netdev_priv(ndev);
942 struct device *d = &pdev->dev;
943
944 if (priv->phy)
945 phy_disconnect(priv->phy);
946
947 hip04_free_ring(ndev, d);
948 unregister_netdev(ndev);
949 free_irq(ndev->irq, ndev);
950 of_node_put(priv->phy_node);
951 cancel_work_sync(&priv->tx_timeout_task);
952 free_netdev(ndev);
953
954 return 0;
955}
956
957static const struct of_device_id hip04_mac_match[] = {
958 { .compatible = "hisilicon,hip04-mac" },
959 { }
960};
961
962MODULE_DEVICE_TABLE(of, hip04_mac_match);
963
964static struct platform_driver hip04_mac_driver = {
965 .probe = hip04_mac_probe,
966 .remove = hip04_remove,
967 .driver = {
968 .name = DRV_NAME,
969 .of_match_table = hip04_mac_match,
970 },
971};
972module_platform_driver(hip04_mac_driver);
973
974MODULE_DESCRIPTION("HISILICON P04 Ethernet driver");
975MODULE_LICENSE("GPL");