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1/*
2 * linux/drivers/message/fusion/mptbase.c
3 * This is the Fusion MPT base driver which supports multiple
4 * (SCSI + LAN) specialized protocol drivers.
5 * For use with LSI PCI chip/adapter(s)
6 * running LSI Fusion MPT (Message Passing Technology) firmware.
7 *
8 * Copyright (c) 1999-2008 LSI Corporation
9 * (mailto:DL-MPTFusionLinux@lsi.com)
10 *
11 */
12/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
13/*
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; version 2 of the License.
17
18 This program is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
22
23 NO WARRANTY
24 THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
25 CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
26 LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
27 MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
28 solely responsible for determining the appropriateness of using and
29 distributing the Program and assumes all risks associated with its
30 exercise of rights under this Agreement, including but not limited to
31 the risks and costs of program errors, damage to or loss of data,
32 programs or equipment, and unavailability or interruption of operations.
33
34 DISCLAIMER OF LIABILITY
35 NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
36 DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
37 DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
38 ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
39 TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
40 USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
41 HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
42
43 You should have received a copy of the GNU General Public License
44 along with this program; if not, write to the Free Software
45 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
46*/
47/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
48
49#include <linux/kernel.h>
50#include <linux/module.h>
51#include <linux/errno.h>
52#include <linux/init.h>
53#include <linux/seq_file.h>
54#include <linux/slab.h>
55#include <linux/types.h>
56#include <linux/pci.h>
57#include <linux/kdev_t.h>
58#include <linux/blkdev.h>
59#include <linux/delay.h>
60#include <linux/interrupt.h>
61#include <linux/dma-mapping.h>
62#include <linux/kthread.h>
63#include <scsi/scsi_host.h>
64
65#include "mptbase.h"
66#include "lsi/mpi_log_fc.h"
67
68/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
69#define my_NAME "Fusion MPT base driver"
70#define my_VERSION MPT_LINUX_VERSION_COMMON
71#define MYNAM "mptbase"
72
73MODULE_AUTHOR(MODULEAUTHOR);
74MODULE_DESCRIPTION(my_NAME);
75MODULE_LICENSE("GPL");
76MODULE_VERSION(my_VERSION);
77
78/*
79 * cmd line parameters
80 */
81
82static int mpt_msi_enable_spi;
83module_param(mpt_msi_enable_spi, int, 0);
84MODULE_PARM_DESC(mpt_msi_enable_spi,
85 " Enable MSI Support for SPI controllers (default=0)");
86
87static int mpt_msi_enable_fc;
88module_param(mpt_msi_enable_fc, int, 0);
89MODULE_PARM_DESC(mpt_msi_enable_fc,
90 " Enable MSI Support for FC controllers (default=0)");
91
92static int mpt_msi_enable_sas;
93module_param(mpt_msi_enable_sas, int, 0);
94MODULE_PARM_DESC(mpt_msi_enable_sas,
95 " Enable MSI Support for SAS controllers (default=0)");
96
97static int mpt_channel_mapping;
98module_param(mpt_channel_mapping, int, 0);
99MODULE_PARM_DESC(mpt_channel_mapping, " Mapping id's to channels (default=0)");
100
101static int mpt_debug_level;
102static int mpt_set_debug_level(const char *val, const struct kernel_param *kp);
103module_param_call(mpt_debug_level, mpt_set_debug_level, param_get_int,
104 &mpt_debug_level, 0600);
105MODULE_PARM_DESC(mpt_debug_level,
106 " debug level - refer to mptdebug.h - (default=0)");
107
108int mpt_fwfault_debug;
109EXPORT_SYMBOL(mpt_fwfault_debug);
110module_param(mpt_fwfault_debug, int, 0600);
111MODULE_PARM_DESC(mpt_fwfault_debug,
112 "Enable detection of Firmware fault and halt Firmware on fault - (default=0)");
113
114static char MptCallbacksName[MPT_MAX_PROTOCOL_DRIVERS]
115 [MPT_MAX_CALLBACKNAME_LEN+1];
116
117#ifdef MFCNT
118static int mfcounter = 0;
119#define PRINT_MF_COUNT 20000
120#endif
121
122/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
123/*
124 * Public data...
125 */
126
127#define WHOINIT_UNKNOWN 0xAA
128
129/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
130/*
131 * Private data...
132 */
133 /* Adapter link list */
134LIST_HEAD(ioc_list);
135 /* Callback lookup table */
136static MPT_CALLBACK MptCallbacks[MPT_MAX_PROTOCOL_DRIVERS];
137 /* Protocol driver class lookup table */
138static int MptDriverClass[MPT_MAX_PROTOCOL_DRIVERS];
139 /* Event handler lookup table */
140static MPT_EVHANDLER MptEvHandlers[MPT_MAX_PROTOCOL_DRIVERS];
141 /* Reset handler lookup table */
142static MPT_RESETHANDLER MptResetHandlers[MPT_MAX_PROTOCOL_DRIVERS];
143static struct mpt_pci_driver *MptDeviceDriverHandlers[MPT_MAX_PROTOCOL_DRIVERS];
144
145#ifdef CONFIG_PROC_FS
146static struct proc_dir_entry *mpt_proc_root_dir;
147#endif
148
149/*
150 * Driver Callback Index's
151 */
152static u8 mpt_base_index = MPT_MAX_PROTOCOL_DRIVERS;
153static u8 last_drv_idx;
154
155/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
156/*
157 * Forward protos...
158 */
159static irqreturn_t mpt_interrupt(int irq, void *bus_id);
160static int mptbase_reply(MPT_ADAPTER *ioc, MPT_FRAME_HDR *req,
161 MPT_FRAME_HDR *reply);
162static int mpt_handshake_req_reply_wait(MPT_ADAPTER *ioc, int reqBytes,
163 u32 *req, int replyBytes, u16 *u16reply, int maxwait,
164 int sleepFlag);
165static int mpt_do_ioc_recovery(MPT_ADAPTER *ioc, u32 reason, int sleepFlag);
166static void mpt_detect_bound_ports(MPT_ADAPTER *ioc, struct pci_dev *pdev);
167static void mpt_adapter_disable(MPT_ADAPTER *ioc);
168static void mpt_adapter_dispose(MPT_ADAPTER *ioc);
169
170static void MptDisplayIocCapabilities(MPT_ADAPTER *ioc);
171static int MakeIocReady(MPT_ADAPTER *ioc, int force, int sleepFlag);
172static int GetIocFacts(MPT_ADAPTER *ioc, int sleepFlag, int reason);
173static int GetPortFacts(MPT_ADAPTER *ioc, int portnum, int sleepFlag);
174static int SendIocInit(MPT_ADAPTER *ioc, int sleepFlag);
175static int SendPortEnable(MPT_ADAPTER *ioc, int portnum, int sleepFlag);
176static int mpt_do_upload(MPT_ADAPTER *ioc, int sleepFlag);
177static int mpt_downloadboot(MPT_ADAPTER *ioc, MpiFwHeader_t *pFwHeader, int sleepFlag);
178static int mpt_diag_reset(MPT_ADAPTER *ioc, int ignore, int sleepFlag);
179static int KickStart(MPT_ADAPTER *ioc, int ignore, int sleepFlag);
180static int SendIocReset(MPT_ADAPTER *ioc, u8 reset_type, int sleepFlag);
181static int PrimeIocFifos(MPT_ADAPTER *ioc);
182static int WaitForDoorbellAck(MPT_ADAPTER *ioc, int howlong, int sleepFlag);
183static int WaitForDoorbellInt(MPT_ADAPTER *ioc, int howlong, int sleepFlag);
184static int WaitForDoorbellReply(MPT_ADAPTER *ioc, int howlong, int sleepFlag);
185static int GetLanConfigPages(MPT_ADAPTER *ioc);
186static int GetIoUnitPage2(MPT_ADAPTER *ioc);
187int mptbase_sas_persist_operation(MPT_ADAPTER *ioc, u8 persist_opcode);
188static int mpt_GetScsiPortSettings(MPT_ADAPTER *ioc, int portnum);
189static int mpt_readScsiDevicePageHeaders(MPT_ADAPTER *ioc, int portnum);
190static void mpt_read_ioc_pg_1(MPT_ADAPTER *ioc);
191static void mpt_read_ioc_pg_4(MPT_ADAPTER *ioc);
192static void mpt_get_manufacturing_pg_0(MPT_ADAPTER *ioc);
193static int SendEventNotification(MPT_ADAPTER *ioc, u8 EvSwitch,
194 int sleepFlag);
195static int SendEventAck(MPT_ADAPTER *ioc, EventNotificationReply_t *evnp);
196static int mpt_host_page_access_control(MPT_ADAPTER *ioc, u8 access_control_value, int sleepFlag);
197static int mpt_host_page_alloc(MPT_ADAPTER *ioc, pIOCInit_t ioc_init);
198
199#ifdef CONFIG_PROC_FS
200static int mpt_summary_proc_show(struct seq_file *m, void *v);
201static int mpt_version_proc_show(struct seq_file *m, void *v);
202static int mpt_iocinfo_proc_show(struct seq_file *m, void *v);
203#endif
204static void mpt_get_fw_exp_ver(char *buf, MPT_ADAPTER *ioc);
205
206static int ProcessEventNotification(MPT_ADAPTER *ioc,
207 EventNotificationReply_t *evReply, int *evHandlers);
208static void mpt_iocstatus_info(MPT_ADAPTER *ioc, u32 ioc_status, MPT_FRAME_HDR *mf);
209static void mpt_fc_log_info(MPT_ADAPTER *ioc, u32 log_info);
210static void mpt_spi_log_info(MPT_ADAPTER *ioc, u32 log_info);
211static void mpt_sas_log_info(MPT_ADAPTER *ioc, u32 log_info , u8 cb_idx);
212static int mpt_read_ioc_pg_3(MPT_ADAPTER *ioc);
213static void mpt_inactive_raid_list_free(MPT_ADAPTER *ioc);
214
215/* module entry point */
216static int __init fusion_init (void);
217static void __exit fusion_exit (void);
218
219#define CHIPREG_READ32(addr) readl_relaxed(addr)
220#define CHIPREG_READ32_dmasync(addr) readl(addr)
221#define CHIPREG_WRITE32(addr,val) writel(val, addr)
222#define CHIPREG_PIO_WRITE32(addr,val) outl(val, (unsigned long)addr)
223#define CHIPREG_PIO_READ32(addr) inl((unsigned long)addr)
224
225static void
226pci_disable_io_access(struct pci_dev *pdev)
227{
228 u16 command_reg;
229
230 pci_read_config_word(pdev, PCI_COMMAND, &command_reg);
231 command_reg &= ~1;
232 pci_write_config_word(pdev, PCI_COMMAND, command_reg);
233}
234
235static void
236pci_enable_io_access(struct pci_dev *pdev)
237{
238 u16 command_reg;
239
240 pci_read_config_word(pdev, PCI_COMMAND, &command_reg);
241 command_reg |= 1;
242 pci_write_config_word(pdev, PCI_COMMAND, command_reg);
243}
244
245static int mpt_set_debug_level(const char *val, const struct kernel_param *kp)
246{
247 int ret = param_set_int(val, kp);
248 MPT_ADAPTER *ioc;
249
250 if (ret)
251 return ret;
252
253 list_for_each_entry(ioc, &ioc_list, list)
254 ioc->debug_level = mpt_debug_level;
255 return 0;
256}
257
258/**
259 * mpt_get_cb_idx - obtain cb_idx for registered driver
260 * @dclass: class driver enum
261 *
262 * Returns cb_idx, or zero means it wasn't found
263 **/
264static u8
265mpt_get_cb_idx(MPT_DRIVER_CLASS dclass)
266{
267 u8 cb_idx;
268
269 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--)
270 if (MptDriverClass[cb_idx] == dclass)
271 return cb_idx;
272 return 0;
273}
274
275/**
276 * mpt_is_discovery_complete - determine if discovery has completed
277 * @ioc: per adatper instance
278 *
279 * Returns 1 when discovery completed, else zero.
280 */
281static int
282mpt_is_discovery_complete(MPT_ADAPTER *ioc)
283{
284 ConfigExtendedPageHeader_t hdr;
285 CONFIGPARMS cfg;
286 SasIOUnitPage0_t *buffer;
287 dma_addr_t dma_handle;
288 int rc = 0;
289
290 memset(&hdr, 0, sizeof(ConfigExtendedPageHeader_t));
291 memset(&cfg, 0, sizeof(CONFIGPARMS));
292 hdr.PageVersion = MPI_SASIOUNITPAGE0_PAGEVERSION;
293 hdr.PageType = MPI_CONFIG_PAGETYPE_EXTENDED;
294 hdr.ExtPageType = MPI_CONFIG_EXTPAGETYPE_SAS_IO_UNIT;
295 cfg.cfghdr.ehdr = &hdr;
296 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
297
298 if ((mpt_config(ioc, &cfg)))
299 goto out;
300 if (!hdr.ExtPageLength)
301 goto out;
302
303 buffer = dma_alloc_coherent(&ioc->pcidev->dev, hdr.ExtPageLength * 4,
304 &dma_handle, GFP_KERNEL);
305 if (!buffer)
306 goto out;
307
308 cfg.physAddr = dma_handle;
309 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
310
311 if ((mpt_config(ioc, &cfg)))
312 goto out_free_consistent;
313
314 if (!(buffer->PhyData[0].PortFlags &
315 MPI_SAS_IOUNIT0_PORT_FLAGS_DISCOVERY_IN_PROGRESS))
316 rc = 1;
317
318 out_free_consistent:
319 dma_free_coherent(&ioc->pcidev->dev, hdr.ExtPageLength * 4, buffer,
320 dma_handle);
321 out:
322 return rc;
323}
324
325
326/**
327 * mpt_remove_dead_ioc_func - kthread context to remove dead ioc
328 * @arg: input argument, used to derive ioc
329 *
330 * Return 0 if controller is removed from pci subsystem.
331 * Return -1 for other case.
332 */
333static int mpt_remove_dead_ioc_func(void *arg)
334{
335 MPT_ADAPTER *ioc = (MPT_ADAPTER *)arg;
336 struct pci_dev *pdev;
337
338 if (!ioc)
339 return -1;
340
341 pdev = ioc->pcidev;
342 if (!pdev)
343 return -1;
344
345 pci_stop_and_remove_bus_device_locked(pdev);
346 return 0;
347}
348
349
350
351/**
352 * mpt_fault_reset_work - work performed on workq after ioc fault
353 * @work: input argument, used to derive ioc
354 *
355**/
356static void
357mpt_fault_reset_work(struct work_struct *work)
358{
359 MPT_ADAPTER *ioc =
360 container_of(work, MPT_ADAPTER, fault_reset_work.work);
361 u32 ioc_raw_state;
362 int rc;
363 unsigned long flags;
364 MPT_SCSI_HOST *hd;
365 struct task_struct *p;
366
367 if (ioc->ioc_reset_in_progress || !ioc->active)
368 goto out;
369
370
371 ioc_raw_state = mpt_GetIocState(ioc, 0);
372 if ((ioc_raw_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_MASK) {
373 printk(MYIOC_s_INFO_FMT "%s: IOC is non-operational !!!!\n",
374 ioc->name, __func__);
375
376 /*
377 * Call mptscsih_flush_pending_cmds callback so that we
378 * flush all pending commands back to OS.
379 * This call is required to aovid deadlock at block layer.
380 * Dead IOC will fail to do diag reset,and this call is safe
381 * since dead ioc will never return any command back from HW.
382 */
383 hd = shost_priv(ioc->sh);
384 ioc->schedule_dead_ioc_flush_running_cmds(hd);
385
386 /*Remove the Dead Host */
387 p = kthread_run(mpt_remove_dead_ioc_func, ioc,
388 "mpt_dead_ioc_%d", ioc->id);
389 if (IS_ERR(p)) {
390 printk(MYIOC_s_ERR_FMT
391 "%s: Running mpt_dead_ioc thread failed !\n",
392 ioc->name, __func__);
393 } else {
394 printk(MYIOC_s_WARN_FMT
395 "%s: Running mpt_dead_ioc thread success !\n",
396 ioc->name, __func__);
397 }
398 return; /* don't rearm timer */
399 }
400
401 if ((ioc_raw_state & MPI_IOC_STATE_MASK)
402 == MPI_IOC_STATE_FAULT) {
403 printk(MYIOC_s_WARN_FMT "IOC is in FAULT state (%04xh)!!!\n",
404 ioc->name, ioc_raw_state & MPI_DOORBELL_DATA_MASK);
405 printk(MYIOC_s_WARN_FMT "Issuing HardReset from %s!!\n",
406 ioc->name, __func__);
407 rc = mpt_HardResetHandler(ioc, CAN_SLEEP);
408 printk(MYIOC_s_WARN_FMT "%s: HardReset: %s\n", ioc->name,
409 __func__, (rc == 0) ? "success" : "failed");
410 ioc_raw_state = mpt_GetIocState(ioc, 0);
411 if ((ioc_raw_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_FAULT)
412 printk(MYIOC_s_WARN_FMT "IOC is in FAULT state after "
413 "reset (%04xh)\n", ioc->name, ioc_raw_state &
414 MPI_DOORBELL_DATA_MASK);
415 } else if (ioc->bus_type == SAS && ioc->sas_discovery_quiesce_io) {
416 if ((mpt_is_discovery_complete(ioc))) {
417 devtprintk(ioc, printk(MYIOC_s_DEBUG_FMT "clearing "
418 "discovery_quiesce_io flag\n", ioc->name));
419 ioc->sas_discovery_quiesce_io = 0;
420 }
421 }
422
423 out:
424 /*
425 * Take turns polling alternate controller
426 */
427 if (ioc->alt_ioc)
428 ioc = ioc->alt_ioc;
429
430 /* rearm the timer */
431 spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
432 if (ioc->reset_work_q)
433 queue_delayed_work(ioc->reset_work_q, &ioc->fault_reset_work,
434 msecs_to_jiffies(MPT_POLLING_INTERVAL));
435 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
436}
437
438
439/*
440 * Process turbo (context) reply...
441 */
442static void
443mpt_turbo_reply(MPT_ADAPTER *ioc, u32 pa)
444{
445 MPT_FRAME_HDR *mf = NULL;
446 MPT_FRAME_HDR *mr = NULL;
447 u16 req_idx = 0;
448 u8 cb_idx;
449
450 dmfprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Got TURBO reply req_idx=%08x\n",
451 ioc->name, pa));
452
453 switch (pa >> MPI_CONTEXT_REPLY_TYPE_SHIFT) {
454 case MPI_CONTEXT_REPLY_TYPE_SCSI_INIT:
455 req_idx = pa & 0x0000FFFF;
456 cb_idx = (pa & 0x00FF0000) >> 16;
457 mf = MPT_INDEX_2_MFPTR(ioc, req_idx);
458 break;
459 case MPI_CONTEXT_REPLY_TYPE_LAN:
460 cb_idx = mpt_get_cb_idx(MPTLAN_DRIVER);
461 /*
462 * Blind set of mf to NULL here was fatal
463 * after lan_reply says "freeme"
464 * Fix sort of combined with an optimization here;
465 * added explicit check for case where lan_reply
466 * was just returning 1 and doing nothing else.
467 * For this case skip the callback, but set up
468 * proper mf value first here:-)
469 */
470 if ((pa & 0x58000000) == 0x58000000) {
471 req_idx = pa & 0x0000FFFF;
472 mf = MPT_INDEX_2_MFPTR(ioc, req_idx);
473 mpt_free_msg_frame(ioc, mf);
474 mb();
475 return;
476 }
477 mr = (MPT_FRAME_HDR *) CAST_U32_TO_PTR(pa);
478 break;
479 case MPI_CONTEXT_REPLY_TYPE_SCSI_TARGET:
480 cb_idx = mpt_get_cb_idx(MPTSTM_DRIVER);
481 mr = (MPT_FRAME_HDR *) CAST_U32_TO_PTR(pa);
482 break;
483 default:
484 cb_idx = 0;
485 BUG();
486 }
487
488 /* Check for (valid) IO callback! */
489 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS ||
490 MptCallbacks[cb_idx] == NULL) {
491 printk(MYIOC_s_WARN_FMT "%s: Invalid cb_idx (%d)!\n",
492 __func__, ioc->name, cb_idx);
493 goto out;
494 }
495
496 if (MptCallbacks[cb_idx](ioc, mf, mr))
497 mpt_free_msg_frame(ioc, mf);
498 out:
499 mb();
500}
501
502static void
503mpt_reply(MPT_ADAPTER *ioc, u32 pa)
504{
505 MPT_FRAME_HDR *mf;
506 MPT_FRAME_HDR *mr;
507 u16 req_idx;
508 u8 cb_idx;
509 int freeme;
510
511 u32 reply_dma_low;
512 u16 ioc_stat;
513
514 /* non-TURBO reply! Hmmm, something may be up...
515 * Newest turbo reply mechanism; get address
516 * via left shift 1 (get rid of MPI_ADDRESS_REPLY_A_BIT)!
517 */
518
519 /* Map DMA address of reply header to cpu address.
520 * pa is 32 bits - but the dma address may be 32 or 64 bits
521 * get offset based only only the low addresses
522 */
523
524 reply_dma_low = (pa <<= 1);
525 mr = (MPT_FRAME_HDR *)((u8 *)ioc->reply_frames +
526 (reply_dma_low - ioc->reply_frames_low_dma));
527
528 req_idx = le16_to_cpu(mr->u.frame.hwhdr.msgctxu.fld.req_idx);
529 cb_idx = mr->u.frame.hwhdr.msgctxu.fld.cb_idx;
530 mf = MPT_INDEX_2_MFPTR(ioc, req_idx);
531
532 dmfprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Got non-TURBO reply=%p req_idx=%x cb_idx=%x Function=%x\n",
533 ioc->name, mr, req_idx, cb_idx, mr->u.hdr.Function));
534 DBG_DUMP_REPLY_FRAME(ioc, (u32 *)mr);
535
536 /* Check/log IOC log info
537 */
538 ioc_stat = le16_to_cpu(mr->u.reply.IOCStatus);
539 if (ioc_stat & MPI_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) {
540 u32 log_info = le32_to_cpu(mr->u.reply.IOCLogInfo);
541 if (ioc->bus_type == FC)
542 mpt_fc_log_info(ioc, log_info);
543 else if (ioc->bus_type == SPI)
544 mpt_spi_log_info(ioc, log_info);
545 else if (ioc->bus_type == SAS)
546 mpt_sas_log_info(ioc, log_info, cb_idx);
547 }
548
549 if (ioc_stat & MPI_IOCSTATUS_MASK)
550 mpt_iocstatus_info(ioc, (u32)ioc_stat, mf);
551
552 /* Check for (valid) IO callback! */
553 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS ||
554 MptCallbacks[cb_idx] == NULL) {
555 printk(MYIOC_s_WARN_FMT "%s: Invalid cb_idx (%d)!\n",
556 __func__, ioc->name, cb_idx);
557 freeme = 0;
558 goto out;
559 }
560
561 freeme = MptCallbacks[cb_idx](ioc, mf, mr);
562
563 out:
564 /* Flush (non-TURBO) reply with a WRITE! */
565 CHIPREG_WRITE32(&ioc->chip->ReplyFifo, pa);
566
567 if (freeme)
568 mpt_free_msg_frame(ioc, mf);
569 mb();
570}
571
572/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
573/**
574 * mpt_interrupt - MPT adapter (IOC) specific interrupt handler.
575 * @irq: irq number (not used)
576 * @bus_id: bus identifier cookie == pointer to MPT_ADAPTER structure
577 *
578 * This routine is registered via the request_irq() kernel API call,
579 * and handles all interrupts generated from a specific MPT adapter
580 * (also referred to as a IO Controller or IOC).
581 * This routine must clear the interrupt from the adapter and does
582 * so by reading the reply FIFO. Multiple replies may be processed
583 * per single call to this routine.
584 *
585 * This routine handles register-level access of the adapter but
586 * dispatches (calls) a protocol-specific callback routine to handle
587 * the protocol-specific details of the MPT request completion.
588 */
589static irqreturn_t
590mpt_interrupt(int irq, void *bus_id)
591{
592 MPT_ADAPTER *ioc = bus_id;
593 u32 pa = CHIPREG_READ32_dmasync(&ioc->chip->ReplyFifo);
594
595 if (pa == 0xFFFFFFFF)
596 return IRQ_NONE;
597
598 /*
599 * Drain the reply FIFO!
600 */
601 do {
602 if (pa & MPI_ADDRESS_REPLY_A_BIT)
603 mpt_reply(ioc, pa);
604 else
605 mpt_turbo_reply(ioc, pa);
606 pa = CHIPREG_READ32_dmasync(&ioc->chip->ReplyFifo);
607 } while (pa != 0xFFFFFFFF);
608
609 return IRQ_HANDLED;
610}
611
612/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
613/**
614 * mptbase_reply - MPT base driver's callback routine
615 * @ioc: Pointer to MPT_ADAPTER structure
616 * @req: Pointer to original MPT request frame
617 * @reply: Pointer to MPT reply frame (NULL if TurboReply)
618 *
619 * MPT base driver's callback routine; all base driver
620 * "internal" request/reply processing is routed here.
621 * Currently used for EventNotification and EventAck handling.
622 *
623 * Returns 1 indicating original alloc'd request frame ptr
624 * should be freed, or 0 if it shouldn't.
625 */
626static int
627mptbase_reply(MPT_ADAPTER *ioc, MPT_FRAME_HDR *req, MPT_FRAME_HDR *reply)
628{
629 EventNotificationReply_t *pEventReply;
630 u8 event;
631 int evHandlers;
632 int freereq = 1;
633
634 switch (reply->u.hdr.Function) {
635 case MPI_FUNCTION_EVENT_NOTIFICATION:
636 pEventReply = (EventNotificationReply_t *)reply;
637 evHandlers = 0;
638 ProcessEventNotification(ioc, pEventReply, &evHandlers);
639 event = le32_to_cpu(pEventReply->Event) & 0xFF;
640 if (pEventReply->MsgFlags & MPI_MSGFLAGS_CONTINUATION_REPLY)
641 freereq = 0;
642 if (event != MPI_EVENT_EVENT_CHANGE)
643 break;
644 fallthrough;
645 case MPI_FUNCTION_CONFIG:
646 case MPI_FUNCTION_SAS_IO_UNIT_CONTROL:
647 ioc->mptbase_cmds.status |= MPT_MGMT_STATUS_COMMAND_GOOD;
648 ioc->mptbase_cmds.status |= MPT_MGMT_STATUS_RF_VALID;
649 memcpy(ioc->mptbase_cmds.reply, reply,
650 min(MPT_DEFAULT_FRAME_SIZE,
651 4 * reply->u.reply.MsgLength));
652 if (ioc->mptbase_cmds.status & MPT_MGMT_STATUS_PENDING) {
653 ioc->mptbase_cmds.status &= ~MPT_MGMT_STATUS_PENDING;
654 complete(&ioc->mptbase_cmds.done);
655 } else
656 freereq = 0;
657 if (ioc->mptbase_cmds.status & MPT_MGMT_STATUS_FREE_MF)
658 freereq = 1;
659 break;
660 case MPI_FUNCTION_EVENT_ACK:
661 devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT
662 "EventAck reply received\n", ioc->name));
663 break;
664 default:
665 printk(MYIOC_s_ERR_FMT
666 "Unexpected msg function (=%02Xh) reply received!\n",
667 ioc->name, reply->u.hdr.Function);
668 break;
669 }
670
671 /*
672 * Conditionally tell caller to free the original
673 * EventNotification/EventAck/unexpected request frame!
674 */
675 return freereq;
676}
677
678/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
679/**
680 * mpt_register - Register protocol-specific main callback handler.
681 * @cbfunc: callback function pointer
682 * @dclass: Protocol driver's class (%MPT_DRIVER_CLASS enum value)
683 * @func_name: call function's name
684 *
685 * This routine is called by a protocol-specific driver (SCSI host,
686 * LAN, SCSI target) to register its reply callback routine. Each
687 * protocol-specific driver must do this before it will be able to
688 * use any IOC resources, such as obtaining request frames.
689 *
690 * NOTES: The SCSI protocol driver currently calls this routine thrice
691 * in order to register separate callbacks; one for "normal" SCSI IO;
692 * one for MptScsiTaskMgmt requests; one for Scan/DV requests.
693 *
694 * Returns u8 valued "handle" in the range (and S.O.D. order)
695 * {N,...,7,6,5,...,1} if successful.
696 * A return value of MPT_MAX_PROTOCOL_DRIVERS (including zero!) should be
697 * considered an error by the caller.
698 */
699u8
700mpt_register(MPT_CALLBACK cbfunc, MPT_DRIVER_CLASS dclass, char *func_name)
701{
702 u8 cb_idx;
703 last_drv_idx = MPT_MAX_PROTOCOL_DRIVERS;
704
705 /*
706 * Search for empty callback slot in this order: {N,...,7,6,5,...,1}
707 * (slot/handle 0 is reserved!)
708 */
709 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
710 if (MptCallbacks[cb_idx] == NULL) {
711 MptCallbacks[cb_idx] = cbfunc;
712 MptDriverClass[cb_idx] = dclass;
713 MptEvHandlers[cb_idx] = NULL;
714 last_drv_idx = cb_idx;
715 strscpy(MptCallbacksName[cb_idx], func_name,
716 MPT_MAX_CALLBACKNAME_LEN+1);
717 break;
718 }
719 }
720
721 return last_drv_idx;
722}
723
724/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
725/**
726 * mpt_deregister - Deregister a protocol drivers resources.
727 * @cb_idx: previously registered callback handle
728 *
729 * Each protocol-specific driver should call this routine when its
730 * module is unloaded.
731 */
732void
733mpt_deregister(u8 cb_idx)
734{
735 if (cb_idx && (cb_idx < MPT_MAX_PROTOCOL_DRIVERS)) {
736 MptCallbacks[cb_idx] = NULL;
737 MptDriverClass[cb_idx] = MPTUNKNOWN_DRIVER;
738 MptEvHandlers[cb_idx] = NULL;
739
740 last_drv_idx++;
741 }
742}
743
744/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
745/**
746 * mpt_event_register - Register protocol-specific event callback handler.
747 * @cb_idx: previously registered (via mpt_register) callback handle
748 * @ev_cbfunc: callback function
749 *
750 * This routine can be called by one or more protocol-specific drivers
751 * if/when they choose to be notified of MPT events.
752 *
753 * Returns 0 for success.
754 */
755int
756mpt_event_register(u8 cb_idx, MPT_EVHANDLER ev_cbfunc)
757{
758 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS)
759 return -1;
760
761 MptEvHandlers[cb_idx] = ev_cbfunc;
762 return 0;
763}
764
765/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
766/**
767 * mpt_event_deregister - Deregister protocol-specific event callback handler
768 * @cb_idx: previously registered callback handle
769 *
770 * Each protocol-specific driver should call this routine
771 * when it does not (or can no longer) handle events,
772 * or when its module is unloaded.
773 */
774void
775mpt_event_deregister(u8 cb_idx)
776{
777 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS)
778 return;
779
780 MptEvHandlers[cb_idx] = NULL;
781}
782
783/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
784/**
785 * mpt_reset_register - Register protocol-specific IOC reset handler.
786 * @cb_idx: previously registered (via mpt_register) callback handle
787 * @reset_func: reset function
788 *
789 * This routine can be called by one or more protocol-specific drivers
790 * if/when they choose to be notified of IOC resets.
791 *
792 * Returns 0 for success.
793 */
794int
795mpt_reset_register(u8 cb_idx, MPT_RESETHANDLER reset_func)
796{
797 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS)
798 return -1;
799
800 MptResetHandlers[cb_idx] = reset_func;
801 return 0;
802}
803
804/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
805/**
806 * mpt_reset_deregister - Deregister protocol-specific IOC reset handler.
807 * @cb_idx: previously registered callback handle
808 *
809 * Each protocol-specific driver should call this routine
810 * when it does not (or can no longer) handle IOC reset handling,
811 * or when its module is unloaded.
812 */
813void
814mpt_reset_deregister(u8 cb_idx)
815{
816 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS)
817 return;
818
819 MptResetHandlers[cb_idx] = NULL;
820}
821
822/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
823/**
824 * mpt_device_driver_register - Register device driver hooks
825 * @dd_cbfunc: driver callbacks struct
826 * @cb_idx: MPT protocol driver index
827 */
828int
829mpt_device_driver_register(struct mpt_pci_driver * dd_cbfunc, u8 cb_idx)
830{
831 MPT_ADAPTER *ioc;
832
833 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS)
834 return -EINVAL;
835
836 MptDeviceDriverHandlers[cb_idx] = dd_cbfunc;
837
838 /* call per pci device probe entry point */
839 list_for_each_entry(ioc, &ioc_list, list) {
840 if (dd_cbfunc->probe)
841 dd_cbfunc->probe(ioc->pcidev);
842 }
843
844 return 0;
845}
846
847/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
848/**
849 * mpt_device_driver_deregister - DeRegister device driver hooks
850 * @cb_idx: MPT protocol driver index
851 */
852void
853mpt_device_driver_deregister(u8 cb_idx)
854{
855 struct mpt_pci_driver *dd_cbfunc;
856 MPT_ADAPTER *ioc;
857
858 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS)
859 return;
860
861 dd_cbfunc = MptDeviceDriverHandlers[cb_idx];
862
863 list_for_each_entry(ioc, &ioc_list, list) {
864 if (dd_cbfunc->remove)
865 dd_cbfunc->remove(ioc->pcidev);
866 }
867
868 MptDeviceDriverHandlers[cb_idx] = NULL;
869}
870
871
872/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
873/**
874 * mpt_get_msg_frame - Obtain an MPT request frame from the pool
875 * @cb_idx: Handle of registered MPT protocol driver
876 * @ioc: Pointer to MPT adapter structure
877 *
878 * Obtain an MPT request frame from the pool (of 1024) that are
879 * allocated per MPT adapter.
880 *
881 * Returns pointer to a MPT request frame or %NULL if none are available
882 * or IOC is not active.
883 */
884MPT_FRAME_HDR*
885mpt_get_msg_frame(u8 cb_idx, MPT_ADAPTER *ioc)
886{
887 MPT_FRAME_HDR *mf;
888 unsigned long flags;
889 u16 req_idx; /* Request index */
890
891 /* validate handle and ioc identifier */
892
893#ifdef MFCNT
894 if (!ioc->active)
895 printk(MYIOC_s_WARN_FMT "IOC Not Active! mpt_get_msg_frame "
896 "returning NULL!\n", ioc->name);
897#endif
898
899 /* If interrupts are not attached, do not return a request frame */
900 if (!ioc->active)
901 return NULL;
902
903 spin_lock_irqsave(&ioc->FreeQlock, flags);
904 if (!list_empty(&ioc->FreeQ)) {
905 int req_offset;
906
907 mf = list_entry(ioc->FreeQ.next, MPT_FRAME_HDR,
908 u.frame.linkage.list);
909 list_del(&mf->u.frame.linkage.list);
910 mf->u.frame.linkage.arg1 = 0;
911 mf->u.frame.hwhdr.msgctxu.fld.cb_idx = cb_idx; /* byte */
912 req_offset = (u8 *)mf - (u8 *)ioc->req_frames;
913 /* u16! */
914 req_idx = req_offset / ioc->req_sz;
915 mf->u.frame.hwhdr.msgctxu.fld.req_idx = cpu_to_le16(req_idx);
916 mf->u.frame.hwhdr.msgctxu.fld.rsvd = 0;
917 /* Default, will be changed if necessary in SG generation */
918 ioc->RequestNB[req_idx] = ioc->NB_for_64_byte_frame;
919#ifdef MFCNT
920 ioc->mfcnt++;
921#endif
922 }
923 else
924 mf = NULL;
925 spin_unlock_irqrestore(&ioc->FreeQlock, flags);
926
927#ifdef MFCNT
928 if (mf == NULL)
929 printk(MYIOC_s_WARN_FMT "IOC Active. No free Msg Frames! "
930 "Count 0x%x Max 0x%x\n", ioc->name, ioc->mfcnt,
931 ioc->req_depth);
932 mfcounter++;
933 if (mfcounter == PRINT_MF_COUNT)
934 printk(MYIOC_s_INFO_FMT "MF Count 0x%x Max 0x%x \n", ioc->name,
935 ioc->mfcnt, ioc->req_depth);
936#endif
937
938 dmfprintk(ioc, printk(MYIOC_s_DEBUG_FMT "mpt_get_msg_frame(%d,%d), got mf=%p\n",
939 ioc->name, cb_idx, ioc->id, mf));
940 return mf;
941}
942
943/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
944/**
945 * mpt_put_msg_frame - Send a protocol-specific MPT request frame to an IOC
946 * @cb_idx: Handle of registered MPT protocol driver
947 * @ioc: Pointer to MPT adapter structure
948 * @mf: Pointer to MPT request frame
949 *
950 * This routine posts an MPT request frame to the request post FIFO of a
951 * specific MPT adapter.
952 */
953void
954mpt_put_msg_frame(u8 cb_idx, MPT_ADAPTER *ioc, MPT_FRAME_HDR *mf)
955{
956 u32 mf_dma_addr;
957 int req_offset;
958 u16 req_idx; /* Request index */
959
960 /* ensure values are reset properly! */
961 mf->u.frame.hwhdr.msgctxu.fld.cb_idx = cb_idx; /* byte */
962 req_offset = (u8 *)mf - (u8 *)ioc->req_frames;
963 /* u16! */
964 req_idx = req_offset / ioc->req_sz;
965 mf->u.frame.hwhdr.msgctxu.fld.req_idx = cpu_to_le16(req_idx);
966 mf->u.frame.hwhdr.msgctxu.fld.rsvd = 0;
967
968 DBG_DUMP_PUT_MSG_FRAME(ioc, (u32 *)mf);
969
970 mf_dma_addr = (ioc->req_frames_low_dma + req_offset) | ioc->RequestNB[req_idx];
971 dsgprintk(ioc, printk(MYIOC_s_DEBUG_FMT "mf_dma_addr=%x req_idx=%d "
972 "RequestNB=%x\n", ioc->name, mf_dma_addr, req_idx,
973 ioc->RequestNB[req_idx]));
974 CHIPREG_WRITE32(&ioc->chip->RequestFifo, mf_dma_addr);
975}
976
977/**
978 * mpt_put_msg_frame_hi_pri - Send a hi-pri protocol-specific MPT request frame
979 * @cb_idx: Handle of registered MPT protocol driver
980 * @ioc: Pointer to MPT adapter structure
981 * @mf: Pointer to MPT request frame
982 *
983 * Send a protocol-specific MPT request frame to an IOC using
984 * hi-priority request queue.
985 *
986 * This routine posts an MPT request frame to the request post FIFO of a
987 * specific MPT adapter.
988 **/
989void
990mpt_put_msg_frame_hi_pri(u8 cb_idx, MPT_ADAPTER *ioc, MPT_FRAME_HDR *mf)
991{
992 u32 mf_dma_addr;
993 int req_offset;
994 u16 req_idx; /* Request index */
995
996 /* ensure values are reset properly! */
997 mf->u.frame.hwhdr.msgctxu.fld.cb_idx = cb_idx;
998 req_offset = (u8 *)mf - (u8 *)ioc->req_frames;
999 req_idx = req_offset / ioc->req_sz;
1000 mf->u.frame.hwhdr.msgctxu.fld.req_idx = cpu_to_le16(req_idx);
1001 mf->u.frame.hwhdr.msgctxu.fld.rsvd = 0;
1002
1003 DBG_DUMP_PUT_MSG_FRAME(ioc, (u32 *)mf);
1004
1005 mf_dma_addr = (ioc->req_frames_low_dma + req_offset);
1006 dsgprintk(ioc, printk(MYIOC_s_DEBUG_FMT "mf_dma_addr=%x req_idx=%d\n",
1007 ioc->name, mf_dma_addr, req_idx));
1008 CHIPREG_WRITE32(&ioc->chip->RequestHiPriFifo, mf_dma_addr);
1009}
1010
1011/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
1012/**
1013 * mpt_free_msg_frame - Place MPT request frame back on FreeQ.
1014 * @ioc: Pointer to MPT adapter structure
1015 * @mf: Pointer to MPT request frame
1016 *
1017 * This routine places a MPT request frame back on the MPT adapter's
1018 * FreeQ.
1019 */
1020void
1021mpt_free_msg_frame(MPT_ADAPTER *ioc, MPT_FRAME_HDR *mf)
1022{
1023 unsigned long flags;
1024
1025 /* Put Request back on FreeQ! */
1026 spin_lock_irqsave(&ioc->FreeQlock, flags);
1027 if (cpu_to_le32(mf->u.frame.linkage.arg1) == 0xdeadbeaf)
1028 goto out;
1029 /* signature to know if this mf is freed */
1030 mf->u.frame.linkage.arg1 = cpu_to_le32(0xdeadbeaf);
1031 list_add(&mf->u.frame.linkage.list, &ioc->FreeQ);
1032#ifdef MFCNT
1033 ioc->mfcnt--;
1034#endif
1035 out:
1036 spin_unlock_irqrestore(&ioc->FreeQlock, flags);
1037}
1038
1039/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
1040/**
1041 * mpt_add_sge - Place a simple 32 bit SGE at address pAddr.
1042 * @pAddr: virtual address for SGE
1043 * @flagslength: SGE flags and data transfer length
1044 * @dma_addr: Physical address
1045 *
1046 * This routine places a MPT request frame back on the MPT adapter's
1047 * FreeQ.
1048 */
1049static void
1050mpt_add_sge(void *pAddr, u32 flagslength, dma_addr_t dma_addr)
1051{
1052 SGESimple32_t *pSge = (SGESimple32_t *) pAddr;
1053 pSge->FlagsLength = cpu_to_le32(flagslength);
1054 pSge->Address = cpu_to_le32(dma_addr);
1055}
1056
1057/**
1058 * mpt_add_sge_64bit - Place a simple 64 bit SGE at address pAddr.
1059 * @pAddr: virtual address for SGE
1060 * @flagslength: SGE flags and data transfer length
1061 * @dma_addr: Physical address
1062 *
1063 * This routine places a MPT request frame back on the MPT adapter's
1064 * FreeQ.
1065 **/
1066static void
1067mpt_add_sge_64bit(void *pAddr, u32 flagslength, dma_addr_t dma_addr)
1068{
1069 SGESimple64_t *pSge = (SGESimple64_t *) pAddr;
1070 pSge->Address.Low = cpu_to_le32
1071 (lower_32_bits(dma_addr));
1072 pSge->Address.High = cpu_to_le32
1073 (upper_32_bits(dma_addr));
1074 pSge->FlagsLength = cpu_to_le32
1075 ((flagslength | MPT_SGE_FLAGS_64_BIT_ADDRESSING));
1076}
1077
1078/**
1079 * mpt_add_sge_64bit_1078 - Place a simple 64 bit SGE at address pAddr (1078 workaround).
1080 * @pAddr: virtual address for SGE
1081 * @flagslength: SGE flags and data transfer length
1082 * @dma_addr: Physical address
1083 *
1084 * This routine places a MPT request frame back on the MPT adapter's
1085 * FreeQ.
1086 **/
1087static void
1088mpt_add_sge_64bit_1078(void *pAddr, u32 flagslength, dma_addr_t dma_addr)
1089{
1090 SGESimple64_t *pSge = (SGESimple64_t *) pAddr;
1091 u32 tmp;
1092
1093 pSge->Address.Low = cpu_to_le32
1094 (lower_32_bits(dma_addr));
1095 tmp = (u32)(upper_32_bits(dma_addr));
1096
1097 /*
1098 * 1078 errata workaround for the 36GB limitation
1099 */
1100 if ((((u64)dma_addr + MPI_SGE_LENGTH(flagslength)) >> 32) == 9) {
1101 flagslength |=
1102 MPI_SGE_SET_FLAGS(MPI_SGE_FLAGS_LOCAL_ADDRESS);
1103 tmp |= (1<<31);
1104 if (mpt_debug_level & MPT_DEBUG_36GB_MEM)
1105 printk(KERN_DEBUG "1078 P0M2 addressing for "
1106 "addr = 0x%llx len = %d\n",
1107 (unsigned long long)dma_addr,
1108 MPI_SGE_LENGTH(flagslength));
1109 }
1110
1111 pSge->Address.High = cpu_to_le32(tmp);
1112 pSge->FlagsLength = cpu_to_le32(
1113 (flagslength | MPT_SGE_FLAGS_64_BIT_ADDRESSING));
1114}
1115
1116/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
1117/**
1118 * mpt_add_chain - Place a 32 bit chain SGE at address pAddr.
1119 * @pAddr: virtual address for SGE
1120 * @next: nextChainOffset value (u32's)
1121 * @length: length of next SGL segment
1122 * @dma_addr: Physical address
1123 *
1124 */
1125static void
1126mpt_add_chain(void *pAddr, u8 next, u16 length, dma_addr_t dma_addr)
1127{
1128 SGEChain32_t *pChain = (SGEChain32_t *) pAddr;
1129
1130 pChain->Length = cpu_to_le16(length);
1131 pChain->Flags = MPI_SGE_FLAGS_CHAIN_ELEMENT;
1132 pChain->NextChainOffset = next;
1133 pChain->Address = cpu_to_le32(dma_addr);
1134}
1135
1136/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
1137/**
1138 * mpt_add_chain_64bit - Place a 64 bit chain SGE at address pAddr.
1139 * @pAddr: virtual address for SGE
1140 * @next: nextChainOffset value (u32's)
1141 * @length: length of next SGL segment
1142 * @dma_addr: Physical address
1143 *
1144 */
1145static void
1146mpt_add_chain_64bit(void *pAddr, u8 next, u16 length, dma_addr_t dma_addr)
1147{
1148 SGEChain64_t *pChain = (SGEChain64_t *) pAddr;
1149 u32 tmp = dma_addr & 0xFFFFFFFF;
1150
1151 pChain->Length = cpu_to_le16(length);
1152 pChain->Flags = (MPI_SGE_FLAGS_CHAIN_ELEMENT |
1153 MPI_SGE_FLAGS_64_BIT_ADDRESSING);
1154
1155 pChain->NextChainOffset = next;
1156
1157 pChain->Address.Low = cpu_to_le32(tmp);
1158 tmp = (u32)(upper_32_bits(dma_addr));
1159 pChain->Address.High = cpu_to_le32(tmp);
1160}
1161
1162/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
1163/**
1164 * mpt_send_handshake_request - Send MPT request via doorbell handshake method.
1165 * @cb_idx: Handle of registered MPT protocol driver
1166 * @ioc: Pointer to MPT adapter structure
1167 * @reqBytes: Size of the request in bytes
1168 * @req: Pointer to MPT request frame
1169 * @sleepFlag: Use schedule if CAN_SLEEP else use udelay.
1170 *
1171 * This routine is used exclusively to send MptScsiTaskMgmt
1172 * requests since they are required to be sent via doorbell handshake.
1173 *
1174 * NOTE: It is the callers responsibility to byte-swap fields in the
1175 * request which are greater than 1 byte in size.
1176 *
1177 * Returns 0 for success, non-zero for failure.
1178 */
1179int
1180mpt_send_handshake_request(u8 cb_idx, MPT_ADAPTER *ioc, int reqBytes, u32 *req, int sleepFlag)
1181{
1182 int r = 0;
1183 u8 *req_as_bytes;
1184 int ii;
1185
1186 /* State is known to be good upon entering
1187 * this function so issue the bus reset
1188 * request.
1189 */
1190
1191 /*
1192 * Emulate what mpt_put_msg_frame() does /wrt to sanity
1193 * setting cb_idx/req_idx. But ONLY if this request
1194 * is in proper (pre-alloc'd) request buffer range...
1195 */
1196 ii = MFPTR_2_MPT_INDEX(ioc,(MPT_FRAME_HDR*)req);
1197 if (reqBytes >= 12 && ii >= 0 && ii < ioc->req_depth) {
1198 MPT_FRAME_HDR *mf = (MPT_FRAME_HDR*)req;
1199 mf->u.frame.hwhdr.msgctxu.fld.req_idx = cpu_to_le16(ii);
1200 mf->u.frame.hwhdr.msgctxu.fld.cb_idx = cb_idx;
1201 }
1202
1203 /* Make sure there are no doorbells */
1204 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
1205
1206 CHIPREG_WRITE32(&ioc->chip->Doorbell,
1207 ((MPI_FUNCTION_HANDSHAKE<<MPI_DOORBELL_FUNCTION_SHIFT) |
1208 ((reqBytes/4)<<MPI_DOORBELL_ADD_DWORDS_SHIFT)));
1209
1210 /* Wait for IOC doorbell int */
1211 if ((ii = WaitForDoorbellInt(ioc, 5, sleepFlag)) < 0) {
1212 return ii;
1213 }
1214
1215 /* Read doorbell and check for active bit */
1216 if (!(CHIPREG_READ32(&ioc->chip->Doorbell) & MPI_DOORBELL_ACTIVE))
1217 return -5;
1218
1219 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "mpt_send_handshake_request start, WaitCnt=%d\n",
1220 ioc->name, ii));
1221
1222 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
1223
1224 if ((r = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0) {
1225 return -2;
1226 }
1227
1228 /* Send request via doorbell handshake */
1229 req_as_bytes = (u8 *) req;
1230 for (ii = 0; ii < reqBytes/4; ii++) {
1231 u32 word;
1232
1233 word = ((req_as_bytes[(ii*4) + 0] << 0) |
1234 (req_as_bytes[(ii*4) + 1] << 8) |
1235 (req_as_bytes[(ii*4) + 2] << 16) |
1236 (req_as_bytes[(ii*4) + 3] << 24));
1237 CHIPREG_WRITE32(&ioc->chip->Doorbell, word);
1238 if ((r = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0) {
1239 r = -3;
1240 break;
1241 }
1242 }
1243
1244 if (r >= 0 && WaitForDoorbellInt(ioc, 10, sleepFlag) >= 0)
1245 r = 0;
1246 else
1247 r = -4;
1248
1249 /* Make sure there are no doorbells */
1250 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
1251
1252 return r;
1253}
1254
1255/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
1256/**
1257 * mpt_host_page_access_control - control the IOC's Host Page Buffer access
1258 * @ioc: Pointer to MPT adapter structure
1259 * @access_control_value: define bits below
1260 * @sleepFlag: Specifies whether the process can sleep
1261 *
1262 * Provides mechanism for the host driver to control the IOC's
1263 * Host Page Buffer access.
1264 *
1265 * Access Control Value - bits[15:12]
1266 * 0h Reserved
1267 * 1h Enable Access { MPI_DB_HPBAC_ENABLE_ACCESS }
1268 * 2h Disable Access { MPI_DB_HPBAC_DISABLE_ACCESS }
1269 * 3h Free Buffer { MPI_DB_HPBAC_FREE_BUFFER }
1270 *
1271 * Returns 0 for success, non-zero for failure.
1272 */
1273
1274static int
1275mpt_host_page_access_control(MPT_ADAPTER *ioc, u8 access_control_value, int sleepFlag)
1276{
1277 /* return if in use */
1278 if (CHIPREG_READ32(&ioc->chip->Doorbell)
1279 & MPI_DOORBELL_ACTIVE)
1280 return -1;
1281
1282 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
1283
1284 CHIPREG_WRITE32(&ioc->chip->Doorbell,
1285 ((MPI_FUNCTION_HOST_PAGEBUF_ACCESS_CONTROL
1286 <<MPI_DOORBELL_FUNCTION_SHIFT) |
1287 (access_control_value<<12)));
1288
1289 /* Wait for IOC to clear Doorbell Status bit */
1290 if (WaitForDoorbellAck(ioc, 5, sleepFlag) < 0)
1291 return -2;
1292 else
1293 return 0;
1294}
1295
1296/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
1297/**
1298 * mpt_host_page_alloc - allocate system memory for the fw
1299 * @ioc: Pointer to pointer to IOC adapter
1300 * @ioc_init: Pointer to ioc init config page
1301 *
1302 * If we already allocated memory in past, then resend the same pointer.
1303 * Returns 0 for success, non-zero for failure.
1304 */
1305static int
1306mpt_host_page_alloc(MPT_ADAPTER *ioc, pIOCInit_t ioc_init)
1307{
1308 char *psge;
1309 int flags_length;
1310 u32 host_page_buffer_sz=0;
1311
1312 if(!ioc->HostPageBuffer) {
1313
1314 host_page_buffer_sz =
1315 le32_to_cpu(ioc->facts.HostPageBufferSGE.FlagsLength) & 0xFFFFFF;
1316
1317 if(!host_page_buffer_sz)
1318 return 0; /* fw doesn't need any host buffers */
1319
1320 /* spin till we get enough memory */
1321 while (host_page_buffer_sz > 0) {
1322 ioc->HostPageBuffer =
1323 dma_alloc_coherent(&ioc->pcidev->dev,
1324 host_page_buffer_sz,
1325 &ioc->HostPageBuffer_dma,
1326 GFP_KERNEL);
1327 if (ioc->HostPageBuffer) {
1328 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT
1329 "host_page_buffer @ %p, dma @ %x, sz=%d bytes\n",
1330 ioc->name, ioc->HostPageBuffer,
1331 (u32)ioc->HostPageBuffer_dma,
1332 host_page_buffer_sz));
1333 ioc->alloc_total += host_page_buffer_sz;
1334 ioc->HostPageBuffer_sz = host_page_buffer_sz;
1335 break;
1336 }
1337
1338 host_page_buffer_sz -= (4*1024);
1339 }
1340 }
1341
1342 if(!ioc->HostPageBuffer) {
1343 printk(MYIOC_s_ERR_FMT
1344 "Failed to alloc memory for host_page_buffer!\n",
1345 ioc->name);
1346 return -999;
1347 }
1348
1349 psge = (char *)&ioc_init->HostPageBufferSGE;
1350 flags_length = MPI_SGE_FLAGS_SIMPLE_ELEMENT |
1351 MPI_SGE_FLAGS_SYSTEM_ADDRESS |
1352 MPI_SGE_FLAGS_HOST_TO_IOC |
1353 MPI_SGE_FLAGS_END_OF_BUFFER;
1354 flags_length = flags_length << MPI_SGE_FLAGS_SHIFT;
1355 flags_length |= ioc->HostPageBuffer_sz;
1356 ioc->add_sge(psge, flags_length, ioc->HostPageBuffer_dma);
1357 ioc->facts.HostPageBufferSGE = ioc_init->HostPageBufferSGE;
1358
1359 return 0;
1360}
1361
1362/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
1363/**
1364 * mpt_verify_adapter - Given IOC identifier, set pointer to its adapter structure.
1365 * @iocid: IOC unique identifier (integer)
1366 * @iocpp: Pointer to pointer to IOC adapter
1367 *
1368 * Given a unique IOC identifier, set pointer to the associated MPT
1369 * adapter structure.
1370 *
1371 * Returns iocid and sets iocpp if iocid is found.
1372 * Returns -1 if iocid is not found.
1373 */
1374int
1375mpt_verify_adapter(int iocid, MPT_ADAPTER **iocpp)
1376{
1377 MPT_ADAPTER *ioc;
1378
1379 list_for_each_entry(ioc,&ioc_list,list) {
1380 if (ioc->id == iocid) {
1381 *iocpp =ioc;
1382 return iocid;
1383 }
1384 }
1385
1386 *iocpp = NULL;
1387 return -1;
1388}
1389
1390/**
1391 * mpt_get_product_name - returns product string
1392 * @vendor: pci vendor id
1393 * @device: pci device id
1394 * @revision: pci revision id
1395 *
1396 * Returns product string displayed when driver loads,
1397 * in /proc/mpt/summary and /sysfs/class/scsi_host/host<X>/version_product
1398 *
1399 **/
1400static const char*
1401mpt_get_product_name(u16 vendor, u16 device, u8 revision)
1402{
1403 char *product_str = NULL;
1404
1405 if (vendor == PCI_VENDOR_ID_BROCADE) {
1406 switch (device)
1407 {
1408 case MPI_MANUFACTPAGE_DEVICEID_FC949E:
1409 switch (revision)
1410 {
1411 case 0x00:
1412 product_str = "BRE040 A0";
1413 break;
1414 case 0x01:
1415 product_str = "BRE040 A1";
1416 break;
1417 default:
1418 product_str = "BRE040";
1419 break;
1420 }
1421 break;
1422 }
1423 goto out;
1424 }
1425
1426 switch (device)
1427 {
1428 case MPI_MANUFACTPAGE_DEVICEID_FC909:
1429 product_str = "LSIFC909 B1";
1430 break;
1431 case MPI_MANUFACTPAGE_DEVICEID_FC919:
1432 product_str = "LSIFC919 B0";
1433 break;
1434 case MPI_MANUFACTPAGE_DEVICEID_FC929:
1435 product_str = "LSIFC929 B0";
1436 break;
1437 case MPI_MANUFACTPAGE_DEVICEID_FC919X:
1438 if (revision < 0x80)
1439 product_str = "LSIFC919X A0";
1440 else
1441 product_str = "LSIFC919XL A1";
1442 break;
1443 case MPI_MANUFACTPAGE_DEVICEID_FC929X:
1444 if (revision < 0x80)
1445 product_str = "LSIFC929X A0";
1446 else
1447 product_str = "LSIFC929XL A1";
1448 break;
1449 case MPI_MANUFACTPAGE_DEVICEID_FC939X:
1450 product_str = "LSIFC939X A1";
1451 break;
1452 case MPI_MANUFACTPAGE_DEVICEID_FC949X:
1453 product_str = "LSIFC949X A1";
1454 break;
1455 case MPI_MANUFACTPAGE_DEVICEID_FC949E:
1456 switch (revision)
1457 {
1458 case 0x00:
1459 product_str = "LSIFC949E A0";
1460 break;
1461 case 0x01:
1462 product_str = "LSIFC949E A1";
1463 break;
1464 default:
1465 product_str = "LSIFC949E";
1466 break;
1467 }
1468 break;
1469 case MPI_MANUFACTPAGE_DEVID_53C1030:
1470 switch (revision)
1471 {
1472 case 0x00:
1473 product_str = "LSI53C1030 A0";
1474 break;
1475 case 0x01:
1476 product_str = "LSI53C1030 B0";
1477 break;
1478 case 0x03:
1479 product_str = "LSI53C1030 B1";
1480 break;
1481 case 0x07:
1482 product_str = "LSI53C1030 B2";
1483 break;
1484 case 0x08:
1485 product_str = "LSI53C1030 C0";
1486 break;
1487 case 0x80:
1488 product_str = "LSI53C1030T A0";
1489 break;
1490 case 0x83:
1491 product_str = "LSI53C1030T A2";
1492 break;
1493 case 0x87:
1494 product_str = "LSI53C1030T A3";
1495 break;
1496 case 0xc1:
1497 product_str = "LSI53C1020A A1";
1498 break;
1499 default:
1500 product_str = "LSI53C1030";
1501 break;
1502 }
1503 break;
1504 case MPI_MANUFACTPAGE_DEVID_1030_53C1035:
1505 switch (revision)
1506 {
1507 case 0x03:
1508 product_str = "LSI53C1035 A2";
1509 break;
1510 case 0x04:
1511 product_str = "LSI53C1035 B0";
1512 break;
1513 default:
1514 product_str = "LSI53C1035";
1515 break;
1516 }
1517 break;
1518 case MPI_MANUFACTPAGE_DEVID_SAS1064:
1519 switch (revision)
1520 {
1521 case 0x00:
1522 product_str = "LSISAS1064 A1";
1523 break;
1524 case 0x01:
1525 product_str = "LSISAS1064 A2";
1526 break;
1527 case 0x02:
1528 product_str = "LSISAS1064 A3";
1529 break;
1530 case 0x03:
1531 product_str = "LSISAS1064 A4";
1532 break;
1533 default:
1534 product_str = "LSISAS1064";
1535 break;
1536 }
1537 break;
1538 case MPI_MANUFACTPAGE_DEVID_SAS1064E:
1539 switch (revision)
1540 {
1541 case 0x00:
1542 product_str = "LSISAS1064E A0";
1543 break;
1544 case 0x01:
1545 product_str = "LSISAS1064E B0";
1546 break;
1547 case 0x02:
1548 product_str = "LSISAS1064E B1";
1549 break;
1550 case 0x04:
1551 product_str = "LSISAS1064E B2";
1552 break;
1553 case 0x08:
1554 product_str = "LSISAS1064E B3";
1555 break;
1556 default:
1557 product_str = "LSISAS1064E";
1558 break;
1559 }
1560 break;
1561 case MPI_MANUFACTPAGE_DEVID_SAS1068:
1562 switch (revision)
1563 {
1564 case 0x00:
1565 product_str = "LSISAS1068 A0";
1566 break;
1567 case 0x01:
1568 product_str = "LSISAS1068 B0";
1569 break;
1570 case 0x02:
1571 product_str = "LSISAS1068 B1";
1572 break;
1573 default:
1574 product_str = "LSISAS1068";
1575 break;
1576 }
1577 break;
1578 case MPI_MANUFACTPAGE_DEVID_SAS1068E:
1579 switch (revision)
1580 {
1581 case 0x00:
1582 product_str = "LSISAS1068E A0";
1583 break;
1584 case 0x01:
1585 product_str = "LSISAS1068E B0";
1586 break;
1587 case 0x02:
1588 product_str = "LSISAS1068E B1";
1589 break;
1590 case 0x04:
1591 product_str = "LSISAS1068E B2";
1592 break;
1593 case 0x08:
1594 product_str = "LSISAS1068E B3";
1595 break;
1596 default:
1597 product_str = "LSISAS1068E";
1598 break;
1599 }
1600 break;
1601 case MPI_MANUFACTPAGE_DEVID_SAS1078:
1602 switch (revision)
1603 {
1604 case 0x00:
1605 product_str = "LSISAS1078 A0";
1606 break;
1607 case 0x01:
1608 product_str = "LSISAS1078 B0";
1609 break;
1610 case 0x02:
1611 product_str = "LSISAS1078 C0";
1612 break;
1613 case 0x03:
1614 product_str = "LSISAS1078 C1";
1615 break;
1616 case 0x04:
1617 product_str = "LSISAS1078 C2";
1618 break;
1619 default:
1620 product_str = "LSISAS1078";
1621 break;
1622 }
1623 break;
1624 }
1625
1626 out:
1627 return product_str;
1628}
1629
1630/**
1631 * mpt_mapresources - map in memory mapped io
1632 * @ioc: Pointer to pointer to IOC adapter
1633 *
1634 **/
1635static int
1636mpt_mapresources(MPT_ADAPTER *ioc)
1637{
1638 u8 __iomem *mem;
1639 int ii;
1640 resource_size_t mem_phys;
1641 unsigned long port;
1642 u32 msize;
1643 u32 psize;
1644 int r = -ENODEV;
1645 struct pci_dev *pdev;
1646
1647 pdev = ioc->pcidev;
1648 ioc->bars = pci_select_bars(pdev, IORESOURCE_MEM);
1649 if (pci_enable_device_mem(pdev)) {
1650 printk(MYIOC_s_ERR_FMT "pci_enable_device_mem() "
1651 "failed\n", ioc->name);
1652 return r;
1653 }
1654 if (pci_request_selected_regions(pdev, ioc->bars, "mpt")) {
1655 printk(MYIOC_s_ERR_FMT "pci_request_selected_regions() with "
1656 "MEM failed\n", ioc->name);
1657 goto out_pci_disable_device;
1658 }
1659
1660 if (sizeof(dma_addr_t) > 4) {
1661 const uint64_t required_mask = dma_get_required_mask
1662 (&pdev->dev);
1663 if (required_mask > DMA_BIT_MASK(32)
1664 && !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))
1665 && !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
1666 ioc->dma_mask = DMA_BIT_MASK(64);
1667 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT
1668 ": 64 BIT PCI BUS DMA ADDRESSING SUPPORTED\n",
1669 ioc->name));
1670 } else if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))
1671 && !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32))) {
1672 ioc->dma_mask = DMA_BIT_MASK(32);
1673 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT
1674 ": 32 BIT PCI BUS DMA ADDRESSING SUPPORTED\n",
1675 ioc->name));
1676 } else {
1677 printk(MYIOC_s_WARN_FMT "no suitable DMA mask for %s\n",
1678 ioc->name, pci_name(pdev));
1679 goto out_pci_release_region;
1680 }
1681 } else {
1682 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))
1683 && !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32))) {
1684 ioc->dma_mask = DMA_BIT_MASK(32);
1685 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT
1686 ": 32 BIT PCI BUS DMA ADDRESSING SUPPORTED\n",
1687 ioc->name));
1688 } else {
1689 printk(MYIOC_s_WARN_FMT "no suitable DMA mask for %s\n",
1690 ioc->name, pci_name(pdev));
1691 goto out_pci_release_region;
1692 }
1693 }
1694
1695 mem_phys = msize = 0;
1696 port = psize = 0;
1697 for (ii = 0; ii < DEVICE_COUNT_RESOURCE; ii++) {
1698 if (pci_resource_flags(pdev, ii) & PCI_BASE_ADDRESS_SPACE_IO) {
1699 if (psize)
1700 continue;
1701 /* Get I/O space! */
1702 port = pci_resource_start(pdev, ii);
1703 psize = pci_resource_len(pdev, ii);
1704 } else {
1705 if (msize)
1706 continue;
1707 /* Get memmap */
1708 mem_phys = pci_resource_start(pdev, ii);
1709 msize = pci_resource_len(pdev, ii);
1710 }
1711 }
1712 ioc->mem_size = msize;
1713
1714 mem = NULL;
1715 /* Get logical ptr for PciMem0 space */
1716 /*mem = ioremap(mem_phys, msize);*/
1717 mem = ioremap(mem_phys, msize);
1718 if (mem == NULL) {
1719 printk(MYIOC_s_ERR_FMT ": ERROR - Unable to map adapter"
1720 " memory!\n", ioc->name);
1721 r = -EINVAL;
1722 goto out_pci_release_region;
1723 }
1724 ioc->memmap = mem;
1725 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT "mem = %p, mem_phys = %llx\n",
1726 ioc->name, mem, (unsigned long long)mem_phys));
1727
1728 ioc->mem_phys = mem_phys;
1729 ioc->chip = (SYSIF_REGS __iomem *)mem;
1730
1731 /* Save Port IO values in case we need to do downloadboot */
1732 ioc->pio_mem_phys = port;
1733 ioc->pio_chip = (SYSIF_REGS __iomem *)port;
1734
1735 return 0;
1736
1737out_pci_release_region:
1738 pci_release_selected_regions(pdev, ioc->bars);
1739out_pci_disable_device:
1740 pci_disable_device(pdev);
1741 return r;
1742}
1743
1744/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
1745/**
1746 * mpt_attach - Install a PCI intelligent MPT adapter.
1747 * @pdev: Pointer to pci_dev structure
1748 * @id: PCI device ID information
1749 *
1750 * This routine performs all the steps necessary to bring the IOC of
1751 * a MPT adapter to a OPERATIONAL state. This includes registering
1752 * memory regions, registering the interrupt, and allocating request
1753 * and reply memory pools.
1754 *
1755 * This routine also pre-fetches the LAN MAC address of a Fibre Channel
1756 * MPT adapter.
1757 *
1758 * Returns 0 for success, non-zero for failure.
1759 *
1760 * TODO: Add support for polled controllers
1761 */
1762int
1763mpt_attach(struct pci_dev *pdev, const struct pci_device_id *id)
1764{
1765 MPT_ADAPTER *ioc;
1766 u8 cb_idx;
1767 int r = -ENODEV;
1768 u8 pcixcmd;
1769 static int mpt_ids = 0;
1770#ifdef CONFIG_PROC_FS
1771 struct proc_dir_entry *dent;
1772#endif
1773
1774 ioc = kzalloc(sizeof(MPT_ADAPTER), GFP_KERNEL);
1775 if (ioc == NULL) {
1776 printk(KERN_ERR MYNAM ": ERROR - Insufficient memory to add adapter!\n");
1777 return -ENOMEM;
1778 }
1779
1780 ioc->id = mpt_ids++;
1781 sprintf(ioc->name, "ioc%d", ioc->id);
1782 dinitprintk(ioc, printk(KERN_WARNING MYNAM ": mpt_adapter_install\n"));
1783
1784 /*
1785 * set initial debug level
1786 * (refer to mptdebug.h)
1787 *
1788 */
1789 ioc->debug_level = mpt_debug_level;
1790 if (mpt_debug_level)
1791 printk(KERN_INFO "mpt_debug_level=%xh\n", mpt_debug_level);
1792
1793 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT ": mpt_adapter_install\n", ioc->name));
1794
1795 ioc->pcidev = pdev;
1796 if (mpt_mapresources(ioc)) {
1797 goto out_free_ioc;
1798 }
1799
1800 /*
1801 * Setting up proper handlers for scatter gather handling
1802 */
1803 if (ioc->dma_mask == DMA_BIT_MASK(64)) {
1804 if (pdev->device == MPI_MANUFACTPAGE_DEVID_SAS1078)
1805 ioc->add_sge = &mpt_add_sge_64bit_1078;
1806 else
1807 ioc->add_sge = &mpt_add_sge_64bit;
1808 ioc->add_chain = &mpt_add_chain_64bit;
1809 ioc->sg_addr_size = 8;
1810 } else {
1811 ioc->add_sge = &mpt_add_sge;
1812 ioc->add_chain = &mpt_add_chain;
1813 ioc->sg_addr_size = 4;
1814 }
1815 ioc->SGE_size = sizeof(u32) + ioc->sg_addr_size;
1816
1817 ioc->alloc_total = sizeof(MPT_ADAPTER);
1818 ioc->req_sz = MPT_DEFAULT_FRAME_SIZE; /* avoid div by zero! */
1819 ioc->reply_sz = MPT_REPLY_FRAME_SIZE;
1820
1821
1822 spin_lock_init(&ioc->taskmgmt_lock);
1823 mutex_init(&ioc->internal_cmds.mutex);
1824 init_completion(&ioc->internal_cmds.done);
1825 mutex_init(&ioc->mptbase_cmds.mutex);
1826 init_completion(&ioc->mptbase_cmds.done);
1827 mutex_init(&ioc->taskmgmt_cmds.mutex);
1828 init_completion(&ioc->taskmgmt_cmds.done);
1829
1830 /* Initialize the event logging.
1831 */
1832 ioc->eventTypes = 0; /* None */
1833 ioc->eventContext = 0;
1834 ioc->eventLogSize = 0;
1835 ioc->events = NULL;
1836
1837#ifdef MFCNT
1838 ioc->mfcnt = 0;
1839#endif
1840
1841 ioc->sh = NULL;
1842 ioc->cached_fw = NULL;
1843
1844 /* Initialize SCSI Config Data structure
1845 */
1846 memset(&ioc->spi_data, 0, sizeof(SpiCfgData));
1847
1848 /* Initialize the fc rport list head.
1849 */
1850 INIT_LIST_HEAD(&ioc->fc_rports);
1851
1852 /* Find lookup slot. */
1853 INIT_LIST_HEAD(&ioc->list);
1854
1855
1856 /* Initialize workqueue */
1857 INIT_DELAYED_WORK(&ioc->fault_reset_work, mpt_fault_reset_work);
1858
1859 ioc->reset_work_q =
1860 alloc_workqueue("mpt_poll_%d", WQ_MEM_RECLAIM, 0, ioc->id);
1861 if (!ioc->reset_work_q) {
1862 printk(MYIOC_s_ERR_FMT "Insufficient memory to add adapter!\n",
1863 ioc->name);
1864 r = -ENOMEM;
1865 goto out_unmap_resources;
1866 }
1867
1868 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT "facts @ %p, pfacts[0] @ %p\n",
1869 ioc->name, &ioc->facts, &ioc->pfacts[0]));
1870
1871 ioc->prod_name = mpt_get_product_name(pdev->vendor, pdev->device,
1872 pdev->revision);
1873
1874 switch (pdev->device)
1875 {
1876 case MPI_MANUFACTPAGE_DEVICEID_FC939X:
1877 case MPI_MANUFACTPAGE_DEVICEID_FC949X:
1878 ioc->errata_flag_1064 = 1;
1879 fallthrough;
1880 case MPI_MANUFACTPAGE_DEVICEID_FC909:
1881 case MPI_MANUFACTPAGE_DEVICEID_FC929:
1882 case MPI_MANUFACTPAGE_DEVICEID_FC919:
1883 case MPI_MANUFACTPAGE_DEVICEID_FC949E:
1884 ioc->bus_type = FC;
1885 break;
1886
1887 case MPI_MANUFACTPAGE_DEVICEID_FC929X:
1888 if (pdev->revision < XL_929) {
1889 /* 929X Chip Fix. Set Split transactions level
1890 * for PCIX. Set MOST bits to zero.
1891 */
1892 pci_read_config_byte(pdev, 0x6a, &pcixcmd);
1893 pcixcmd &= 0x8F;
1894 pci_write_config_byte(pdev, 0x6a, pcixcmd);
1895 } else {
1896 /* 929XL Chip Fix. Set MMRBC to 0x08.
1897 */
1898 pci_read_config_byte(pdev, 0x6a, &pcixcmd);
1899 pcixcmd |= 0x08;
1900 pci_write_config_byte(pdev, 0x6a, pcixcmd);
1901 }
1902 ioc->bus_type = FC;
1903 break;
1904
1905 case MPI_MANUFACTPAGE_DEVICEID_FC919X:
1906 /* 919X Chip Fix. Set Split transactions level
1907 * for PCIX. Set MOST bits to zero.
1908 */
1909 pci_read_config_byte(pdev, 0x6a, &pcixcmd);
1910 pcixcmd &= 0x8F;
1911 pci_write_config_byte(pdev, 0x6a, pcixcmd);
1912 ioc->bus_type = FC;
1913 break;
1914
1915 case MPI_MANUFACTPAGE_DEVID_53C1030:
1916 /* 1030 Chip Fix. Disable Split transactions
1917 * for PCIX. Set MOST bits to zero if Rev < C0( = 8).
1918 */
1919 if (pdev->revision < C0_1030) {
1920 pci_read_config_byte(pdev, 0x6a, &pcixcmd);
1921 pcixcmd &= 0x8F;
1922 pci_write_config_byte(pdev, 0x6a, pcixcmd);
1923 }
1924 fallthrough;
1925
1926 case MPI_MANUFACTPAGE_DEVID_1030_53C1035:
1927 ioc->bus_type = SPI;
1928 break;
1929
1930 case MPI_MANUFACTPAGE_DEVID_SAS1064:
1931 case MPI_MANUFACTPAGE_DEVID_SAS1068:
1932 ioc->errata_flag_1064 = 1;
1933 ioc->bus_type = SAS;
1934 break;
1935
1936 case MPI_MANUFACTPAGE_DEVID_SAS1064E:
1937 case MPI_MANUFACTPAGE_DEVID_SAS1068E:
1938 case MPI_MANUFACTPAGE_DEVID_SAS1078:
1939 ioc->bus_type = SAS;
1940 break;
1941 }
1942
1943
1944 switch (ioc->bus_type) {
1945
1946 case SAS:
1947 ioc->msi_enable = mpt_msi_enable_sas;
1948 break;
1949
1950 case SPI:
1951 ioc->msi_enable = mpt_msi_enable_spi;
1952 break;
1953
1954 case FC:
1955 ioc->msi_enable = mpt_msi_enable_fc;
1956 break;
1957
1958 default:
1959 ioc->msi_enable = 0;
1960 break;
1961 }
1962
1963 ioc->fw_events_off = 1;
1964
1965 if (ioc->errata_flag_1064)
1966 pci_disable_io_access(pdev);
1967
1968 spin_lock_init(&ioc->FreeQlock);
1969
1970 /* Disable all! */
1971 CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF);
1972 ioc->active = 0;
1973 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
1974
1975 /* Set IOC ptr in the pcidev's driver data. */
1976 pci_set_drvdata(ioc->pcidev, ioc);
1977
1978 /* Set lookup ptr. */
1979 list_add_tail(&ioc->list, &ioc_list);
1980
1981 /* Check for "bound ports" (929, 929X, 1030, 1035) to reduce redundant resets.
1982 */
1983 mpt_detect_bound_ports(ioc, pdev);
1984
1985 INIT_LIST_HEAD(&ioc->fw_event_list);
1986 spin_lock_init(&ioc->fw_event_lock);
1987 ioc->fw_event_q = alloc_workqueue("mpt/%d", WQ_MEM_RECLAIM, 0, ioc->id);
1988 if (!ioc->fw_event_q) {
1989 printk(MYIOC_s_ERR_FMT "Insufficient memory to add adapter!\n",
1990 ioc->name);
1991 r = -ENOMEM;
1992 goto out_remove_ioc;
1993 }
1994
1995 if ((r = mpt_do_ioc_recovery(ioc, MPT_HOSTEVENT_IOC_BRINGUP,
1996 CAN_SLEEP)) != 0){
1997 printk(MYIOC_s_ERR_FMT "didn't initialize properly! (%d)\n",
1998 ioc->name, r);
1999
2000 destroy_workqueue(ioc->fw_event_q);
2001 ioc->fw_event_q = NULL;
2002
2003 list_del(&ioc->list);
2004 if (ioc->alt_ioc)
2005 ioc->alt_ioc->alt_ioc = NULL;
2006 iounmap(ioc->memmap);
2007 if (pci_is_enabled(pdev))
2008 pci_disable_device(pdev);
2009 if (r != -5)
2010 pci_release_selected_regions(pdev, ioc->bars);
2011
2012 destroy_workqueue(ioc->reset_work_q);
2013 ioc->reset_work_q = NULL;
2014
2015 kfree(ioc);
2016 return r;
2017 }
2018
2019 /* call per device driver probe entry point */
2020 for(cb_idx = 0; cb_idx < MPT_MAX_PROTOCOL_DRIVERS; cb_idx++) {
2021 if(MptDeviceDriverHandlers[cb_idx] &&
2022 MptDeviceDriverHandlers[cb_idx]->probe) {
2023 MptDeviceDriverHandlers[cb_idx]->probe(pdev);
2024 }
2025 }
2026
2027#ifdef CONFIG_PROC_FS
2028 /*
2029 * Create "/proc/mpt/iocN" subdirectory entry for each MPT adapter.
2030 */
2031 dent = proc_mkdir(ioc->name, mpt_proc_root_dir);
2032 if (dent) {
2033 proc_create_single_data("info", S_IRUGO, dent,
2034 mpt_iocinfo_proc_show, ioc);
2035 proc_create_single_data("summary", S_IRUGO, dent,
2036 mpt_summary_proc_show, ioc);
2037 }
2038#endif
2039
2040 if (!ioc->alt_ioc)
2041 queue_delayed_work(ioc->reset_work_q, &ioc->fault_reset_work,
2042 msecs_to_jiffies(MPT_POLLING_INTERVAL));
2043
2044 return 0;
2045
2046out_remove_ioc:
2047 list_del(&ioc->list);
2048 if (ioc->alt_ioc)
2049 ioc->alt_ioc->alt_ioc = NULL;
2050
2051 destroy_workqueue(ioc->reset_work_q);
2052 ioc->reset_work_q = NULL;
2053
2054out_unmap_resources:
2055 iounmap(ioc->memmap);
2056 pci_disable_device(pdev);
2057 pci_release_selected_regions(pdev, ioc->bars);
2058
2059out_free_ioc:
2060 kfree(ioc);
2061
2062 return r;
2063}
2064
2065/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
2066/**
2067 * mpt_detach - Remove a PCI intelligent MPT adapter.
2068 * @pdev: Pointer to pci_dev structure
2069 */
2070
2071void
2072mpt_detach(struct pci_dev *pdev)
2073{
2074 MPT_ADAPTER *ioc = pci_get_drvdata(pdev);
2075 char pname[64];
2076 u8 cb_idx;
2077 unsigned long flags;
2078 struct workqueue_struct *wq;
2079
2080 /*
2081 * Stop polling ioc for fault condition
2082 */
2083 spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
2084 wq = ioc->reset_work_q;
2085 ioc->reset_work_q = NULL;
2086 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
2087 cancel_delayed_work(&ioc->fault_reset_work);
2088 destroy_workqueue(wq);
2089
2090 spin_lock_irqsave(&ioc->fw_event_lock, flags);
2091 wq = ioc->fw_event_q;
2092 ioc->fw_event_q = NULL;
2093 spin_unlock_irqrestore(&ioc->fw_event_lock, flags);
2094 destroy_workqueue(wq);
2095
2096 snprintf(pname, sizeof(pname), MPT_PROCFS_MPTBASEDIR "/%s/summary", ioc->name);
2097 remove_proc_entry(pname, NULL);
2098 snprintf(pname, sizeof(pname), MPT_PROCFS_MPTBASEDIR "/%s/info", ioc->name);
2099 remove_proc_entry(pname, NULL);
2100 snprintf(pname, sizeof(pname), MPT_PROCFS_MPTBASEDIR "/%s", ioc->name);
2101 remove_proc_entry(pname, NULL);
2102
2103 /* call per device driver remove entry point */
2104 for(cb_idx = 0; cb_idx < MPT_MAX_PROTOCOL_DRIVERS; cb_idx++) {
2105 if(MptDeviceDriverHandlers[cb_idx] &&
2106 MptDeviceDriverHandlers[cb_idx]->remove) {
2107 MptDeviceDriverHandlers[cb_idx]->remove(pdev);
2108 }
2109 }
2110
2111 /* Disable interrupts! */
2112 CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF);
2113
2114 ioc->active = 0;
2115 synchronize_irq(pdev->irq);
2116
2117 /* Clear any lingering interrupt */
2118 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
2119
2120 CHIPREG_READ32(&ioc->chip->IntStatus);
2121
2122 mpt_adapter_dispose(ioc);
2123
2124}
2125
2126/**************************************************************************
2127 * Power Management
2128 */
2129#ifdef CONFIG_PM
2130/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
2131/**
2132 * mpt_suspend - Fusion MPT base driver suspend routine.
2133 * @pdev: Pointer to pci_dev structure
2134 * @state: new state to enter
2135 */
2136int
2137mpt_suspend(struct pci_dev *pdev, pm_message_t state)
2138{
2139 u32 device_state;
2140 MPT_ADAPTER *ioc = pci_get_drvdata(pdev);
2141
2142 device_state = pci_choose_state(pdev, state);
2143 printk(MYIOC_s_INFO_FMT "pci-suspend: pdev=0x%p, slot=%s, Entering "
2144 "operating state [D%d]\n", ioc->name, pdev, pci_name(pdev),
2145 device_state);
2146
2147 /* put ioc into READY_STATE */
2148 if (SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, CAN_SLEEP)) {
2149 printk(MYIOC_s_ERR_FMT
2150 "pci-suspend: IOC msg unit reset failed!\n", ioc->name);
2151 }
2152
2153 /* disable interrupts */
2154 CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF);
2155 ioc->active = 0;
2156
2157 /* Clear any lingering interrupt */
2158 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
2159
2160 free_irq(ioc->pci_irq, ioc);
2161 if (ioc->msi_enable)
2162 pci_disable_msi(ioc->pcidev);
2163 ioc->pci_irq = -1;
2164 pci_save_state(pdev);
2165 pci_disable_device(pdev);
2166 pci_release_selected_regions(pdev, ioc->bars);
2167 pci_set_power_state(pdev, device_state);
2168 return 0;
2169}
2170
2171/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
2172/**
2173 * mpt_resume - Fusion MPT base driver resume routine.
2174 * @pdev: Pointer to pci_dev structure
2175 */
2176int
2177mpt_resume(struct pci_dev *pdev)
2178{
2179 MPT_ADAPTER *ioc = pci_get_drvdata(pdev);
2180 u32 device_state = pdev->current_state;
2181 int recovery_state;
2182 int err;
2183
2184 printk(MYIOC_s_INFO_FMT "pci-resume: pdev=0x%p, slot=%s, Previous "
2185 "operating state [D%d]\n", ioc->name, pdev, pci_name(pdev),
2186 device_state);
2187
2188 pci_set_power_state(pdev, PCI_D0);
2189 pci_enable_wake(pdev, PCI_D0, 0);
2190 pci_restore_state(pdev);
2191 ioc->pcidev = pdev;
2192 err = mpt_mapresources(ioc);
2193 if (err)
2194 return err;
2195
2196 if (ioc->dma_mask == DMA_BIT_MASK(64)) {
2197 if (pdev->device == MPI_MANUFACTPAGE_DEVID_SAS1078)
2198 ioc->add_sge = &mpt_add_sge_64bit_1078;
2199 else
2200 ioc->add_sge = &mpt_add_sge_64bit;
2201 ioc->add_chain = &mpt_add_chain_64bit;
2202 ioc->sg_addr_size = 8;
2203 } else {
2204
2205 ioc->add_sge = &mpt_add_sge;
2206 ioc->add_chain = &mpt_add_chain;
2207 ioc->sg_addr_size = 4;
2208 }
2209 ioc->SGE_size = sizeof(u32) + ioc->sg_addr_size;
2210
2211 printk(MYIOC_s_INFO_FMT "pci-resume: ioc-state=0x%x,doorbell=0x%x\n",
2212 ioc->name, (mpt_GetIocState(ioc, 1) >> MPI_IOC_STATE_SHIFT),
2213 CHIPREG_READ32(&ioc->chip->Doorbell));
2214
2215 /*
2216 * Errata workaround for SAS pci express:
2217 * Upon returning to the D0 state, the contents of the doorbell will be
2218 * stale data, and this will incorrectly signal to the host driver that
2219 * the firmware is ready to process mpt commands. The workaround is
2220 * to issue a diagnostic reset.
2221 */
2222 if (ioc->bus_type == SAS && (pdev->device ==
2223 MPI_MANUFACTPAGE_DEVID_SAS1068E || pdev->device ==
2224 MPI_MANUFACTPAGE_DEVID_SAS1064E)) {
2225 if (KickStart(ioc, 1, CAN_SLEEP) < 0) {
2226 printk(MYIOC_s_WARN_FMT "pci-resume: Cannot recover\n",
2227 ioc->name);
2228 goto out;
2229 }
2230 }
2231
2232 /* bring ioc to operational state */
2233 printk(MYIOC_s_INFO_FMT "Sending mpt_do_ioc_recovery\n", ioc->name);
2234 recovery_state = mpt_do_ioc_recovery(ioc, MPT_HOSTEVENT_IOC_BRINGUP,
2235 CAN_SLEEP);
2236 if (recovery_state != 0)
2237 printk(MYIOC_s_WARN_FMT "pci-resume: Cannot recover, "
2238 "error:[%x]\n", ioc->name, recovery_state);
2239 else
2240 printk(MYIOC_s_INFO_FMT
2241 "pci-resume: success\n", ioc->name);
2242 out:
2243 return 0;
2244
2245}
2246#endif
2247
2248static int
2249mpt_signal_reset(u8 index, MPT_ADAPTER *ioc, int reset_phase)
2250{
2251 if ((MptDriverClass[index] == MPTSPI_DRIVER &&
2252 ioc->bus_type != SPI) ||
2253 (MptDriverClass[index] == MPTFC_DRIVER &&
2254 ioc->bus_type != FC) ||
2255 (MptDriverClass[index] == MPTSAS_DRIVER &&
2256 ioc->bus_type != SAS))
2257 /* make sure we only call the relevant reset handler
2258 * for the bus */
2259 return 0;
2260 return (MptResetHandlers[index])(ioc, reset_phase);
2261}
2262
2263/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
2264/**
2265 * mpt_do_ioc_recovery - Initialize or recover MPT adapter.
2266 * @ioc: Pointer to MPT adapter structure
2267 * @reason: Event word / reason
2268 * @sleepFlag: Use schedule if CAN_SLEEP else use udelay.
2269 *
2270 * This routine performs all the steps necessary to bring the IOC
2271 * to a OPERATIONAL state.
2272 *
2273 * This routine also pre-fetches the LAN MAC address of a Fibre Channel
2274 * MPT adapter.
2275 *
2276 * Returns:
2277 * 0 for success
2278 * -1 if failed to get board READY
2279 * -2 if READY but IOCFacts Failed
2280 * -3 if READY but PrimeIOCFifos Failed
2281 * -4 if READY but IOCInit Failed
2282 * -5 if failed to enable_device and/or request_selected_regions
2283 * -6 if failed to upload firmware
2284 */
2285static int
2286mpt_do_ioc_recovery(MPT_ADAPTER *ioc, u32 reason, int sleepFlag)
2287{
2288 int hard_reset_done = 0;
2289 int alt_ioc_ready = 0;
2290 int hard;
2291 int rc=0;
2292 int ii;
2293 int ret = 0;
2294 int reset_alt_ioc_active = 0;
2295 int irq_allocated = 0;
2296 u8 *a;
2297
2298 printk(MYIOC_s_INFO_FMT "Initiating %s\n", ioc->name,
2299 reason == MPT_HOSTEVENT_IOC_BRINGUP ? "bringup" : "recovery");
2300
2301 /* Disable reply interrupts (also blocks FreeQ) */
2302 CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF);
2303 ioc->active = 0;
2304
2305 if (ioc->alt_ioc) {
2306 if (ioc->alt_ioc->active ||
2307 reason == MPT_HOSTEVENT_IOC_RECOVER) {
2308 reset_alt_ioc_active = 1;
2309 /* Disable alt-IOC's reply interrupts
2310 * (and FreeQ) for a bit
2311 **/
2312 CHIPREG_WRITE32(&ioc->alt_ioc->chip->IntMask,
2313 0xFFFFFFFF);
2314 ioc->alt_ioc->active = 0;
2315 }
2316 }
2317
2318 hard = 1;
2319 if (reason == MPT_HOSTEVENT_IOC_BRINGUP)
2320 hard = 0;
2321
2322 if ((hard_reset_done = MakeIocReady(ioc, hard, sleepFlag)) < 0) {
2323 if (hard_reset_done == -4) {
2324 printk(MYIOC_s_WARN_FMT "Owned by PEER..skipping!\n",
2325 ioc->name);
2326
2327 if (reset_alt_ioc_active && ioc->alt_ioc) {
2328 /* (re)Enable alt-IOC! (reply interrupt, FreeQ) */
2329 dprintk(ioc, printk(MYIOC_s_INFO_FMT
2330 "alt_ioc reply irq re-enabled\n", ioc->alt_ioc->name));
2331 CHIPREG_WRITE32(&ioc->alt_ioc->chip->IntMask, MPI_HIM_DIM);
2332 ioc->alt_ioc->active = 1;
2333 }
2334
2335 } else {
2336 printk(MYIOC_s_WARN_FMT
2337 "NOT READY WARNING!\n", ioc->name);
2338 }
2339 ret = -1;
2340 goto out;
2341 }
2342
2343 /* hard_reset_done = 0 if a soft reset was performed
2344 * and 1 if a hard reset was performed.
2345 */
2346 if (hard_reset_done && reset_alt_ioc_active && ioc->alt_ioc) {
2347 if ((rc = MakeIocReady(ioc->alt_ioc, 0, sleepFlag)) == 0)
2348 alt_ioc_ready = 1;
2349 else
2350 printk(MYIOC_s_WARN_FMT
2351 ": alt-ioc Not ready WARNING!\n",
2352 ioc->alt_ioc->name);
2353 }
2354
2355 for (ii=0; ii<5; ii++) {
2356 /* Get IOC facts! Allow 5 retries */
2357 if ((rc = GetIocFacts(ioc, sleepFlag, reason)) == 0)
2358 break;
2359 }
2360
2361
2362 if (ii == 5) {
2363 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT
2364 "Retry IocFacts failed rc=%x\n", ioc->name, rc));
2365 ret = -2;
2366 } else if (reason == MPT_HOSTEVENT_IOC_BRINGUP) {
2367 MptDisplayIocCapabilities(ioc);
2368 }
2369
2370 if (alt_ioc_ready) {
2371 if ((rc = GetIocFacts(ioc->alt_ioc, sleepFlag, reason)) != 0) {
2372 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT
2373 "Initial Alt IocFacts failed rc=%x\n",
2374 ioc->name, rc));
2375 /* Retry - alt IOC was initialized once
2376 */
2377 rc = GetIocFacts(ioc->alt_ioc, sleepFlag, reason);
2378 }
2379 if (rc) {
2380 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT
2381 "Retry Alt IocFacts failed rc=%x\n", ioc->name, rc));
2382 alt_ioc_ready = 0;
2383 reset_alt_ioc_active = 0;
2384 } else if (reason == MPT_HOSTEVENT_IOC_BRINGUP) {
2385 MptDisplayIocCapabilities(ioc->alt_ioc);
2386 }
2387 }
2388
2389 if ((ret == 0) && (reason == MPT_HOSTEVENT_IOC_BRINGUP) &&
2390 (ioc->facts.Flags & MPI_IOCFACTS_FLAGS_FW_DOWNLOAD_BOOT)) {
2391 pci_release_selected_regions(ioc->pcidev, ioc->bars);
2392 ioc->bars = pci_select_bars(ioc->pcidev, IORESOURCE_MEM |
2393 IORESOURCE_IO);
2394 if (pci_enable_device(ioc->pcidev))
2395 return -5;
2396 if (pci_request_selected_regions(ioc->pcidev, ioc->bars,
2397 "mpt"))
2398 return -5;
2399 }
2400
2401 /*
2402 * Device is reset now. It must have de-asserted the interrupt line
2403 * (if it was asserted) and it should be safe to register for the
2404 * interrupt now.
2405 */
2406 if ((ret == 0) && (reason == MPT_HOSTEVENT_IOC_BRINGUP)) {
2407 ioc->pci_irq = -1;
2408 if (ioc->pcidev->irq) {
2409 if (ioc->msi_enable && !pci_enable_msi(ioc->pcidev))
2410 printk(MYIOC_s_INFO_FMT "PCI-MSI enabled\n",
2411 ioc->name);
2412 else
2413 ioc->msi_enable = 0;
2414 rc = request_irq(ioc->pcidev->irq, mpt_interrupt,
2415 IRQF_SHARED, ioc->name, ioc);
2416 if (rc < 0) {
2417 printk(MYIOC_s_ERR_FMT "Unable to allocate "
2418 "interrupt %d!\n",
2419 ioc->name, ioc->pcidev->irq);
2420 if (ioc->msi_enable)
2421 pci_disable_msi(ioc->pcidev);
2422 ret = -EBUSY;
2423 goto out;
2424 }
2425 irq_allocated = 1;
2426 ioc->pci_irq = ioc->pcidev->irq;
2427 pci_set_master(ioc->pcidev); /* ?? */
2428 pci_set_drvdata(ioc->pcidev, ioc);
2429 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT
2430 "installed at interrupt %d\n", ioc->name,
2431 ioc->pcidev->irq));
2432 }
2433 }
2434
2435 /* Prime reply & request queues!
2436 * (mucho alloc's) Must be done prior to
2437 * init as upper addresses are needed for init.
2438 * If fails, continue with alt-ioc processing
2439 */
2440 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT "PrimeIocFifos\n",
2441 ioc->name));
2442 if ((ret == 0) && ((rc = PrimeIocFifos(ioc)) != 0))
2443 ret = -3;
2444
2445 /* May need to check/upload firmware & data here!
2446 * If fails, continue with alt-ioc processing
2447 */
2448 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT "SendIocInit\n",
2449 ioc->name));
2450 if ((ret == 0) && ((rc = SendIocInit(ioc, sleepFlag)) != 0))
2451 ret = -4;
2452// NEW!
2453 if (alt_ioc_ready && ((rc = PrimeIocFifos(ioc->alt_ioc)) != 0)) {
2454 printk(MYIOC_s_WARN_FMT
2455 ": alt-ioc (%d) FIFO mgmt alloc WARNING!\n",
2456 ioc->alt_ioc->name, rc);
2457 alt_ioc_ready = 0;
2458 reset_alt_ioc_active = 0;
2459 }
2460
2461 if (alt_ioc_ready) {
2462 if ((rc = SendIocInit(ioc->alt_ioc, sleepFlag)) != 0) {
2463 alt_ioc_ready = 0;
2464 reset_alt_ioc_active = 0;
2465 printk(MYIOC_s_WARN_FMT
2466 ": alt-ioc: (%d) init failure WARNING!\n",
2467 ioc->alt_ioc->name, rc);
2468 }
2469 }
2470
2471 if (reason == MPT_HOSTEVENT_IOC_BRINGUP){
2472 if (ioc->upload_fw) {
2473 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT
2474 "firmware upload required!\n", ioc->name));
2475
2476 /* Controller is not operational, cannot do upload
2477 */
2478 if (ret == 0) {
2479 rc = mpt_do_upload(ioc, sleepFlag);
2480 if (rc == 0) {
2481 if (ioc->alt_ioc && ioc->alt_ioc->cached_fw) {
2482 /*
2483 * Maintain only one pointer to FW memory
2484 * so there will not be two attempt to
2485 * downloadboot onboard dual function
2486 * chips (mpt_adapter_disable,
2487 * mpt_diag_reset)
2488 */
2489 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT
2490 "mpt_upload: alt_%s has cached_fw=%p \n",
2491 ioc->name, ioc->alt_ioc->name, ioc->alt_ioc->cached_fw));
2492 ioc->cached_fw = NULL;
2493 }
2494 } else {
2495 printk(MYIOC_s_WARN_FMT
2496 "firmware upload failure!\n", ioc->name);
2497 ret = -6;
2498 }
2499 }
2500 }
2501 }
2502
2503 /* Enable MPT base driver management of EventNotification
2504 * and EventAck handling.
2505 */
2506 if ((ret == 0) && (!ioc->facts.EventState)) {
2507 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT
2508 "SendEventNotification\n",
2509 ioc->name));
2510 ret = SendEventNotification(ioc, 1, sleepFlag); /* 1=Enable */
2511 }
2512
2513 if (ioc->alt_ioc && alt_ioc_ready && !ioc->alt_ioc->facts.EventState)
2514 rc = SendEventNotification(ioc->alt_ioc, 1, sleepFlag);
2515
2516 if (ret == 0) {
2517 /* Enable! (reply interrupt) */
2518 CHIPREG_WRITE32(&ioc->chip->IntMask, MPI_HIM_DIM);
2519 ioc->active = 1;
2520 }
2521 if (rc == 0) { /* alt ioc */
2522 if (reset_alt_ioc_active && ioc->alt_ioc) {
2523 /* (re)Enable alt-IOC! (reply interrupt) */
2524 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "alt-ioc"
2525 "reply irq re-enabled\n",
2526 ioc->alt_ioc->name));
2527 CHIPREG_WRITE32(&ioc->alt_ioc->chip->IntMask,
2528 MPI_HIM_DIM);
2529 ioc->alt_ioc->active = 1;
2530 }
2531 }
2532
2533
2534 /* Add additional "reason" check before call to GetLanConfigPages
2535 * (combined with GetIoUnitPage2 call). This prevents a somewhat
2536 * recursive scenario; GetLanConfigPages times out, timer expired
2537 * routine calls HardResetHandler, which calls into here again,
2538 * and we try GetLanConfigPages again...
2539 */
2540 if ((ret == 0) && (reason == MPT_HOSTEVENT_IOC_BRINGUP)) {
2541
2542 /*
2543 * Initialize link list for inactive raid volumes.
2544 */
2545 mutex_init(&ioc->raid_data.inactive_list_mutex);
2546 INIT_LIST_HEAD(&ioc->raid_data.inactive_list);
2547
2548 switch (ioc->bus_type) {
2549
2550 case SAS:
2551 /* clear persistency table */
2552 if(ioc->facts.IOCExceptions &
2553 MPI_IOCFACTS_EXCEPT_PERSISTENT_TABLE_FULL) {
2554 ret = mptbase_sas_persist_operation(ioc,
2555 MPI_SAS_OP_CLEAR_NOT_PRESENT);
2556 if(ret != 0)
2557 goto out;
2558 }
2559
2560 /* Find IM volumes
2561 */
2562 mpt_findImVolumes(ioc);
2563
2564 /* Check, and possibly reset, the coalescing value
2565 */
2566 mpt_read_ioc_pg_1(ioc);
2567
2568 break;
2569
2570 case FC:
2571 if ((ioc->pfacts[0].ProtocolFlags &
2572 MPI_PORTFACTS_PROTOCOL_LAN) &&
2573 (ioc->lan_cnfg_page0.Header.PageLength == 0)) {
2574 /*
2575 * Pre-fetch the ports LAN MAC address!
2576 * (LANPage1_t stuff)
2577 */
2578 (void) GetLanConfigPages(ioc);
2579 a = (u8*)&ioc->lan_cnfg_page1.HardwareAddressLow;
2580 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT
2581 "LanAddr = %pMR\n", ioc->name, a));
2582 }
2583 break;
2584
2585 case SPI:
2586 /* Get NVRAM and adapter maximums from SPP 0 and 2
2587 */
2588 mpt_GetScsiPortSettings(ioc, 0);
2589
2590 /* Get version and length of SDP 1
2591 */
2592 mpt_readScsiDevicePageHeaders(ioc, 0);
2593
2594 /* Find IM volumes
2595 */
2596 if (ioc->facts.MsgVersion >= MPI_VERSION_01_02)
2597 mpt_findImVolumes(ioc);
2598
2599 /* Check, and possibly reset, the coalescing value
2600 */
2601 mpt_read_ioc_pg_1(ioc);
2602
2603 mpt_read_ioc_pg_4(ioc);
2604
2605 break;
2606 }
2607
2608 GetIoUnitPage2(ioc);
2609 mpt_get_manufacturing_pg_0(ioc);
2610 }
2611
2612 out:
2613 if ((ret != 0) && irq_allocated) {
2614 free_irq(ioc->pci_irq, ioc);
2615 if (ioc->msi_enable)
2616 pci_disable_msi(ioc->pcidev);
2617 }
2618 return ret;
2619}
2620
2621/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
2622/**
2623 * mpt_detect_bound_ports - Search for matching PCI bus/dev_function
2624 * @ioc: Pointer to MPT adapter structure
2625 * @pdev: Pointer to (struct pci_dev) structure
2626 *
2627 * Search for PCI bus/dev_function which matches
2628 * PCI bus/dev_function (+/-1) for newly discovered 929,
2629 * 929X, 1030 or 1035.
2630 *
2631 * If match on PCI dev_function +/-1 is found, bind the two MPT adapters
2632 * using alt_ioc pointer fields in their %MPT_ADAPTER structures.
2633 */
2634static void
2635mpt_detect_bound_ports(MPT_ADAPTER *ioc, struct pci_dev *pdev)
2636{
2637 struct pci_dev *peer=NULL;
2638 unsigned int slot = PCI_SLOT(pdev->devfn);
2639 unsigned int func = PCI_FUNC(pdev->devfn);
2640 MPT_ADAPTER *ioc_srch;
2641
2642 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "PCI device %s devfn=%x/%x,"
2643 " searching for devfn match on %x or %x\n",
2644 ioc->name, pci_name(pdev), pdev->bus->number,
2645 pdev->devfn, func-1, func+1));
2646
2647 peer = pci_get_slot(pdev->bus, PCI_DEVFN(slot,func-1));
2648 if (!peer) {
2649 peer = pci_get_slot(pdev->bus, PCI_DEVFN(slot,func+1));
2650 if (!peer)
2651 return;
2652 }
2653
2654 list_for_each_entry(ioc_srch, &ioc_list, list) {
2655 struct pci_dev *_pcidev = ioc_srch->pcidev;
2656 if (_pcidev == peer) {
2657 /* Paranoia checks */
2658 if (ioc->alt_ioc != NULL) {
2659 printk(MYIOC_s_WARN_FMT
2660 "Oops, already bound (%s <==> %s)!\n",
2661 ioc->name, ioc->name, ioc->alt_ioc->name);
2662 break;
2663 } else if (ioc_srch->alt_ioc != NULL) {
2664 printk(MYIOC_s_WARN_FMT
2665 "Oops, already bound (%s <==> %s)!\n",
2666 ioc_srch->name, ioc_srch->name,
2667 ioc_srch->alt_ioc->name);
2668 break;
2669 }
2670 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT
2671 "FOUND! binding %s <==> %s\n",
2672 ioc->name, ioc->name, ioc_srch->name));
2673 ioc_srch->alt_ioc = ioc;
2674 ioc->alt_ioc = ioc_srch;
2675 }
2676 }
2677 pci_dev_put(peer);
2678}
2679
2680/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
2681/**
2682 * mpt_adapter_disable - Disable misbehaving MPT adapter.
2683 * @ioc: Pointer to MPT adapter structure
2684 */
2685static void
2686mpt_adapter_disable(MPT_ADAPTER *ioc)
2687{
2688 int sz;
2689 int ret;
2690
2691 if (ioc->cached_fw != NULL) {
2692 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT
2693 "%s: Pushing FW onto adapter\n", __func__, ioc->name));
2694 if ((ret = mpt_downloadboot(ioc, (MpiFwHeader_t *)
2695 ioc->cached_fw, CAN_SLEEP)) < 0) {
2696 printk(MYIOC_s_WARN_FMT
2697 ": firmware downloadboot failure (%d)!\n",
2698 ioc->name, ret);
2699 }
2700 }
2701
2702 /*
2703 * Put the controller into ready state (if its not already)
2704 */
2705 if (mpt_GetIocState(ioc, 1) != MPI_IOC_STATE_READY) {
2706 if (!SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET,
2707 CAN_SLEEP)) {
2708 if (mpt_GetIocState(ioc, 1) != MPI_IOC_STATE_READY)
2709 printk(MYIOC_s_ERR_FMT "%s: IOC msg unit "
2710 "reset failed to put ioc in ready state!\n",
2711 ioc->name, __func__);
2712 } else
2713 printk(MYIOC_s_ERR_FMT "%s: IOC msg unit reset "
2714 "failed!\n", ioc->name, __func__);
2715 }
2716
2717
2718 /* Disable adapter interrupts! */
2719 synchronize_irq(ioc->pcidev->irq);
2720 CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF);
2721 ioc->active = 0;
2722
2723 /* Clear any lingering interrupt */
2724 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
2725 CHIPREG_READ32(&ioc->chip->IntStatus);
2726
2727 if (ioc->alloc != NULL) {
2728 sz = ioc->alloc_sz;
2729 dexitprintk(ioc, printk(MYIOC_s_INFO_FMT "free @ %p, sz=%d bytes\n",
2730 ioc->name, ioc->alloc, ioc->alloc_sz));
2731 dma_free_coherent(&ioc->pcidev->dev, sz, ioc->alloc,
2732 ioc->alloc_dma);
2733 ioc->reply_frames = NULL;
2734 ioc->req_frames = NULL;
2735 ioc->alloc = NULL;
2736 ioc->alloc_total -= sz;
2737 }
2738
2739 if (ioc->sense_buf_pool != NULL) {
2740 sz = (ioc->req_depth * MPT_SENSE_BUFFER_ALLOC);
2741 dma_free_coherent(&ioc->pcidev->dev, sz, ioc->sense_buf_pool,
2742 ioc->sense_buf_pool_dma);
2743 ioc->sense_buf_pool = NULL;
2744 ioc->alloc_total -= sz;
2745 }
2746
2747 if (ioc->events != NULL){
2748 sz = MPTCTL_EVENT_LOG_SIZE * sizeof(MPT_IOCTL_EVENTS);
2749 kfree(ioc->events);
2750 ioc->events = NULL;
2751 ioc->alloc_total -= sz;
2752 }
2753
2754 mpt_free_fw_memory(ioc);
2755
2756 kfree(ioc->spi_data.nvram);
2757 mpt_inactive_raid_list_free(ioc);
2758 kfree(ioc->raid_data.pIocPg2);
2759 kfree(ioc->raid_data.pIocPg3);
2760 ioc->spi_data.nvram = NULL;
2761 ioc->raid_data.pIocPg3 = NULL;
2762
2763 if (ioc->spi_data.pIocPg4 != NULL) {
2764 sz = ioc->spi_data.IocPg4Sz;
2765 dma_free_coherent(&ioc->pcidev->dev, sz,
2766 ioc->spi_data.pIocPg4,
2767 ioc->spi_data.IocPg4_dma);
2768 ioc->spi_data.pIocPg4 = NULL;
2769 ioc->alloc_total -= sz;
2770 }
2771
2772 if (ioc->ReqToChain != NULL) {
2773 kfree(ioc->ReqToChain);
2774 kfree(ioc->RequestNB);
2775 ioc->ReqToChain = NULL;
2776 }
2777
2778 kfree(ioc->ChainToChain);
2779 ioc->ChainToChain = NULL;
2780
2781 if (ioc->HostPageBuffer != NULL) {
2782 if((ret = mpt_host_page_access_control(ioc,
2783 MPI_DB_HPBAC_FREE_BUFFER, NO_SLEEP)) != 0) {
2784 printk(MYIOC_s_ERR_FMT
2785 ": %s: host page buffers free failed (%d)!\n",
2786 ioc->name, __func__, ret);
2787 }
2788 dexitprintk(ioc, printk(MYIOC_s_DEBUG_FMT
2789 "HostPageBuffer free @ %p, sz=%d bytes\n",
2790 ioc->name, ioc->HostPageBuffer,
2791 ioc->HostPageBuffer_sz));
2792 dma_free_coherent(&ioc->pcidev->dev, ioc->HostPageBuffer_sz,
2793 ioc->HostPageBuffer, ioc->HostPageBuffer_dma);
2794 ioc->HostPageBuffer = NULL;
2795 ioc->HostPageBuffer_sz = 0;
2796 ioc->alloc_total -= ioc->HostPageBuffer_sz;
2797 }
2798
2799 pci_set_drvdata(ioc->pcidev, NULL);
2800}
2801/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
2802/**
2803 * mpt_adapter_dispose - Free all resources associated with an MPT adapter
2804 * @ioc: Pointer to MPT adapter structure
2805 *
2806 * This routine unregisters h/w resources and frees all alloc'd memory
2807 * associated with a MPT adapter structure.
2808 */
2809static void
2810mpt_adapter_dispose(MPT_ADAPTER *ioc)
2811{
2812 int sz_first, sz_last;
2813
2814 if (ioc == NULL)
2815 return;
2816
2817 sz_first = ioc->alloc_total;
2818
2819 mpt_adapter_disable(ioc);
2820
2821 if (ioc->pci_irq != -1) {
2822 free_irq(ioc->pci_irq, ioc);
2823 if (ioc->msi_enable)
2824 pci_disable_msi(ioc->pcidev);
2825 ioc->pci_irq = -1;
2826 }
2827
2828 if (ioc->memmap != NULL) {
2829 iounmap(ioc->memmap);
2830 ioc->memmap = NULL;
2831 }
2832
2833 pci_disable_device(ioc->pcidev);
2834 pci_release_selected_regions(ioc->pcidev, ioc->bars);
2835
2836 /* Zap the adapter lookup ptr! */
2837 list_del(&ioc->list);
2838
2839 sz_last = ioc->alloc_total;
2840 dprintk(ioc, printk(MYIOC_s_INFO_FMT "free'd %d of %d bytes\n",
2841 ioc->name, sz_first-sz_last+(int)sizeof(*ioc), sz_first));
2842
2843 if (ioc->alt_ioc)
2844 ioc->alt_ioc->alt_ioc = NULL;
2845
2846 kfree(ioc);
2847}
2848
2849/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
2850/**
2851 * MptDisplayIocCapabilities - Disply IOC's capabilities.
2852 * @ioc: Pointer to MPT adapter structure
2853 */
2854static void
2855MptDisplayIocCapabilities(MPT_ADAPTER *ioc)
2856{
2857 int i = 0;
2858
2859 printk(KERN_INFO "%s: ", ioc->name);
2860 if (ioc->prod_name)
2861 pr_cont("%s: ", ioc->prod_name);
2862 pr_cont("Capabilities={");
2863
2864 if (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_INITIATOR) {
2865 pr_cont("Initiator");
2866 i++;
2867 }
2868
2869 if (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_TARGET) {
2870 pr_cont("%sTarget", i ? "," : "");
2871 i++;
2872 }
2873
2874 if (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_LAN) {
2875 pr_cont("%sLAN", i ? "," : "");
2876 i++;
2877 }
2878
2879#if 0
2880 /*
2881 * This would probably evoke more questions than it's worth
2882 */
2883 if (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_TARGET) {
2884 pr_cont("%sLogBusAddr", i ? "," : "");
2885 i++;
2886 }
2887#endif
2888
2889 pr_cont("}\n");
2890}
2891
2892/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
2893/**
2894 * MakeIocReady - Get IOC to a READY state, using KickStart if needed.
2895 * @ioc: Pointer to MPT_ADAPTER structure
2896 * @force: Force hard KickStart of IOC
2897 * @sleepFlag: Specifies whether the process can sleep
2898 *
2899 * Returns:
2900 * 1 - DIAG reset and READY
2901 * 0 - READY initially OR soft reset and READY
2902 * -1 - Any failure on KickStart
2903 * -2 - Msg Unit Reset Failed
2904 * -3 - IO Unit Reset Failed
2905 * -4 - IOC owned by a PEER
2906 */
2907static int
2908MakeIocReady(MPT_ADAPTER *ioc, int force, int sleepFlag)
2909{
2910 u32 ioc_state;
2911 int statefault = 0;
2912 int cntdn;
2913 int hard_reset_done = 0;
2914 int r;
2915 int ii;
2916 int whoinit;
2917
2918 /* Get current [raw] IOC state */
2919 ioc_state = mpt_GetIocState(ioc, 0);
2920 dhsprintk(ioc, printk(MYIOC_s_INFO_FMT "MakeIocReady [raw] state=%08x\n", ioc->name, ioc_state));
2921
2922 /*
2923 * Check to see if IOC got left/stuck in doorbell handshake
2924 * grip of death. If so, hard reset the IOC.
2925 */
2926 if (ioc_state & MPI_DOORBELL_ACTIVE) {
2927 statefault = 1;
2928 printk(MYIOC_s_WARN_FMT "Unexpected doorbell active!\n",
2929 ioc->name);
2930 }
2931
2932 /* Is it already READY? */
2933 if (!statefault &&
2934 ((ioc_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_READY)) {
2935 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT
2936 "IOC is in READY state\n", ioc->name));
2937 return 0;
2938 }
2939
2940 /*
2941 * Check to see if IOC is in FAULT state.
2942 */
2943 if ((ioc_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_FAULT) {
2944 statefault = 2;
2945 printk(MYIOC_s_WARN_FMT "IOC is in FAULT state!!!\n",
2946 ioc->name);
2947 printk(MYIOC_s_WARN_FMT " FAULT code = %04xh\n",
2948 ioc->name, ioc_state & MPI_DOORBELL_DATA_MASK);
2949 }
2950
2951 /*
2952 * Hmmm... Did it get left operational?
2953 */
2954 if ((ioc_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_OPERATIONAL) {
2955 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "IOC operational unexpected\n",
2956 ioc->name));
2957
2958 /* Check WhoInit.
2959 * If PCI Peer, exit.
2960 * Else, if no fault conditions are present, issue a MessageUnitReset
2961 * Else, fall through to KickStart case
2962 */
2963 whoinit = (ioc_state & MPI_DOORBELL_WHO_INIT_MASK) >> MPI_DOORBELL_WHO_INIT_SHIFT;
2964 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT
2965 "whoinit 0x%x statefault %d force %d\n",
2966 ioc->name, whoinit, statefault, force));
2967 if (whoinit == MPI_WHOINIT_PCI_PEER)
2968 return -4;
2969 else {
2970 if ((statefault == 0 ) && (force == 0)) {
2971 if ((r = SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, sleepFlag)) == 0)
2972 return 0;
2973 }
2974 statefault = 3;
2975 }
2976 }
2977
2978 hard_reset_done = KickStart(ioc, statefault||force, sleepFlag);
2979 if (hard_reset_done < 0)
2980 return -1;
2981
2982 /*
2983 * Loop here waiting for IOC to come READY.
2984 */
2985 ii = 0;
2986 cntdn = ((sleepFlag == CAN_SLEEP) ? HZ : 1000) * 5; /* 5 seconds */
2987
2988 while ((ioc_state = mpt_GetIocState(ioc, 1)) != MPI_IOC_STATE_READY) {
2989 if (ioc_state == MPI_IOC_STATE_OPERATIONAL) {
2990 /*
2991 * BIOS or previous driver load left IOC in OP state.
2992 * Reset messaging FIFOs.
2993 */
2994 if ((r = SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, sleepFlag)) != 0) {
2995 printk(MYIOC_s_ERR_FMT "IOC msg unit reset failed!\n", ioc->name);
2996 return -2;
2997 }
2998 } else if (ioc_state == MPI_IOC_STATE_RESET) {
2999 /*
3000 * Something is wrong. Try to get IOC back
3001 * to a known state.
3002 */
3003 if ((r = SendIocReset(ioc, MPI_FUNCTION_IO_UNIT_RESET, sleepFlag)) != 0) {
3004 printk(MYIOC_s_ERR_FMT "IO unit reset failed!\n", ioc->name);
3005 return -3;
3006 }
3007 }
3008
3009 ii++; cntdn--;
3010 if (!cntdn) {
3011 printk(MYIOC_s_ERR_FMT
3012 "Wait IOC_READY state (0x%x) timeout(%d)!\n",
3013 ioc->name, ioc_state, (int)((ii+5)/HZ));
3014 return -ETIME;
3015 }
3016
3017 if (sleepFlag == CAN_SLEEP) {
3018 msleep(1);
3019 } else {
3020 mdelay (1); /* 1 msec delay */
3021 }
3022
3023 }
3024
3025 if (statefault < 3) {
3026 printk(MYIOC_s_INFO_FMT "Recovered from %s\n", ioc->name,
3027 statefault == 1 ? "stuck handshake" : "IOC FAULT");
3028 }
3029
3030 return hard_reset_done;
3031}
3032
3033/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
3034/**
3035 * mpt_GetIocState - Get the current state of a MPT adapter.
3036 * @ioc: Pointer to MPT_ADAPTER structure
3037 * @cooked: Request raw or cooked IOC state
3038 *
3039 * Returns all IOC Doorbell register bits if cooked==0, else just the
3040 * Doorbell bits in MPI_IOC_STATE_MASK.
3041 */
3042u32
3043mpt_GetIocState(MPT_ADAPTER *ioc, int cooked)
3044{
3045 u32 s, sc;
3046
3047 /* Get! */
3048 s = CHIPREG_READ32(&ioc->chip->Doorbell);
3049 sc = s & MPI_IOC_STATE_MASK;
3050
3051 /* Save! */
3052 ioc->last_state = sc;
3053
3054 return cooked ? sc : s;
3055}
3056
3057/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
3058/**
3059 * GetIocFacts - Send IOCFacts request to MPT adapter.
3060 * @ioc: Pointer to MPT_ADAPTER structure
3061 * @sleepFlag: Specifies whether the process can sleep
3062 * @reason: If recovery, only update facts.
3063 *
3064 * Returns 0 for success, non-zero for failure.
3065 */
3066static int
3067GetIocFacts(MPT_ADAPTER *ioc, int sleepFlag, int reason)
3068{
3069 IOCFacts_t get_facts;
3070 IOCFactsReply_t *facts;
3071 int r;
3072 int req_sz;
3073 int reply_sz;
3074 int sz;
3075 u32 vv;
3076 u8 shiftFactor=1;
3077
3078 /* IOC *must* NOT be in RESET state! */
3079 if (ioc->last_state == MPI_IOC_STATE_RESET) {
3080 printk(KERN_ERR MYNAM
3081 ": ERROR - Can't get IOCFacts, %s NOT READY! (%08x)\n",
3082 ioc->name, ioc->last_state);
3083 return -44;
3084 }
3085
3086 facts = &ioc->facts;
3087
3088 /* Destination (reply area)... */
3089 reply_sz = sizeof(*facts);
3090 memset(facts, 0, reply_sz);
3091
3092 /* Request area (get_facts on the stack right now!) */
3093 req_sz = sizeof(get_facts);
3094 memset(&get_facts, 0, req_sz);
3095
3096 get_facts.Function = MPI_FUNCTION_IOC_FACTS;
3097 /* Assert: All other get_facts fields are zero! */
3098
3099 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT
3100 "Sending get IocFacts request req_sz=%d reply_sz=%d\n",
3101 ioc->name, req_sz, reply_sz));
3102
3103 /* No non-zero fields in the get_facts request are greater than
3104 * 1 byte in size, so we can just fire it off as is.
3105 */
3106 r = mpt_handshake_req_reply_wait(ioc, req_sz, (u32*)&get_facts,
3107 reply_sz, (u16*)facts, 5 /*seconds*/, sleepFlag);
3108 if (r != 0)
3109 return r;
3110
3111 /*
3112 * Now byte swap (GRRR) the necessary fields before any further
3113 * inspection of reply contents.
3114 *
3115 * But need to do some sanity checks on MsgLength (byte) field
3116 * to make sure we don't zero IOC's req_sz!
3117 */
3118 /* Did we get a valid reply? */
3119 if (facts->MsgLength > offsetof(IOCFactsReply_t, RequestFrameSize)/sizeof(u32)) {
3120 if (reason == MPT_HOSTEVENT_IOC_BRINGUP) {
3121 /*
3122 * If not been here, done that, save off first WhoInit value
3123 */
3124 if (ioc->FirstWhoInit == WHOINIT_UNKNOWN)
3125 ioc->FirstWhoInit = facts->WhoInit;
3126 }
3127
3128 facts->MsgVersion = le16_to_cpu(facts->MsgVersion);
3129 facts->MsgContext = le32_to_cpu(facts->MsgContext);
3130 facts->IOCExceptions = le16_to_cpu(facts->IOCExceptions);
3131 facts->IOCStatus = le16_to_cpu(facts->IOCStatus);
3132 facts->IOCLogInfo = le32_to_cpu(facts->IOCLogInfo);
3133 /* CHECKME! IOCStatus, IOCLogInfo */
3134
3135 facts->ReplyQueueDepth = le16_to_cpu(facts->ReplyQueueDepth);
3136 facts->RequestFrameSize = le16_to_cpu(facts->RequestFrameSize);
3137
3138 /*
3139 * FC f/w version changed between 1.1 and 1.2
3140 * Old: u16{Major(4),Minor(4),SubMinor(8)}
3141 * New: u32{Major(8),Minor(8),Unit(8),Dev(8)}
3142 */
3143 if (facts->MsgVersion < MPI_VERSION_01_02) {
3144 /*
3145 * Handle old FC f/w style, convert to new...
3146 */
3147 u16 oldv = le16_to_cpu(facts->Reserved_0101_FWVersion);
3148 facts->FWVersion.Word =
3149 ((oldv<<12) & 0xFF000000) |
3150 ((oldv<<8) & 0x000FFF00);
3151 } else
3152 facts->FWVersion.Word = le32_to_cpu(facts->FWVersion.Word);
3153
3154 facts->ProductID = le16_to_cpu(facts->ProductID);
3155
3156 if ((ioc->facts.ProductID & MPI_FW_HEADER_PID_PROD_MASK)
3157 > MPI_FW_HEADER_PID_PROD_TARGET_SCSI)
3158 ioc->ir_firmware = 1;
3159
3160 facts->CurrentHostMfaHighAddr =
3161 le32_to_cpu(facts->CurrentHostMfaHighAddr);
3162 facts->GlobalCredits = le16_to_cpu(facts->GlobalCredits);
3163 facts->CurrentSenseBufferHighAddr =
3164 le32_to_cpu(facts->CurrentSenseBufferHighAddr);
3165 facts->CurReplyFrameSize =
3166 le16_to_cpu(facts->CurReplyFrameSize);
3167 facts->IOCCapabilities = le32_to_cpu(facts->IOCCapabilities);
3168
3169 /*
3170 * Handle NEW (!) IOCFactsReply fields in MPI-1.01.xx
3171 * Older MPI-1.00.xx struct had 13 dwords, and enlarged
3172 * to 14 in MPI-1.01.0x.
3173 */
3174 if (facts->MsgLength >= (offsetof(IOCFactsReply_t,FWImageSize) + 7)/4 &&
3175 facts->MsgVersion > MPI_VERSION_01_00) {
3176 facts->FWImageSize = le32_to_cpu(facts->FWImageSize);
3177 }
3178
3179 facts->FWImageSize = ALIGN(facts->FWImageSize, 4);
3180
3181 if (!facts->RequestFrameSize) {
3182 /* Something is wrong! */
3183 printk(MYIOC_s_ERR_FMT "IOC reported invalid 0 request size!\n",
3184 ioc->name);
3185 return -55;
3186 }
3187
3188 r = sz = facts->BlockSize;
3189 vv = ((63 / (sz * 4)) + 1) & 0x03;
3190 ioc->NB_for_64_byte_frame = vv;
3191 while ( sz )
3192 {
3193 shiftFactor++;
3194 sz = sz >> 1;
3195 }
3196 ioc->NBShiftFactor = shiftFactor;
3197 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT
3198 "NB_for_64_byte_frame=%x NBShiftFactor=%x BlockSize=%x\n",
3199 ioc->name, vv, shiftFactor, r));
3200
3201 if (reason == MPT_HOSTEVENT_IOC_BRINGUP) {
3202 /*
3203 * Set values for this IOC's request & reply frame sizes,
3204 * and request & reply queue depths...
3205 */
3206 ioc->req_sz = min(MPT_DEFAULT_FRAME_SIZE, facts->RequestFrameSize * 4);
3207 ioc->req_depth = min_t(int, MPT_MAX_REQ_DEPTH, facts->GlobalCredits);
3208 ioc->reply_sz = MPT_REPLY_FRAME_SIZE;
3209 ioc->reply_depth = min_t(int, MPT_DEFAULT_REPLY_DEPTH, facts->ReplyQueueDepth);
3210
3211 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "reply_sz=%3d, reply_depth=%4d\n",
3212 ioc->name, ioc->reply_sz, ioc->reply_depth));
3213 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "req_sz =%3d, req_depth =%4d\n",
3214 ioc->name, ioc->req_sz, ioc->req_depth));
3215
3216 /* Get port facts! */
3217 if ( (r = GetPortFacts(ioc, 0, sleepFlag)) != 0 )
3218 return r;
3219 }
3220 } else {
3221 printk(MYIOC_s_ERR_FMT
3222 "Invalid IOC facts reply, msgLength=%d offsetof=%zd!\n",
3223 ioc->name, facts->MsgLength, (offsetof(IOCFactsReply_t,
3224 RequestFrameSize)/sizeof(u32)));
3225 return -66;
3226 }
3227
3228 return 0;
3229}
3230
3231/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
3232/**
3233 * GetPortFacts - Send PortFacts request to MPT adapter.
3234 * @ioc: Pointer to MPT_ADAPTER structure
3235 * @portnum: Port number
3236 * @sleepFlag: Specifies whether the process can sleep
3237 *
3238 * Returns 0 for success, non-zero for failure.
3239 */
3240static int
3241GetPortFacts(MPT_ADAPTER *ioc, int portnum, int sleepFlag)
3242{
3243 PortFacts_t get_pfacts;
3244 PortFactsReply_t *pfacts;
3245 int ii;
3246 int req_sz;
3247 int reply_sz;
3248 int max_id;
3249
3250 /* IOC *must* NOT be in RESET state! */
3251 if (ioc->last_state == MPI_IOC_STATE_RESET) {
3252 printk(MYIOC_s_ERR_FMT "Can't get PortFacts NOT READY! (%08x)\n",
3253 ioc->name, ioc->last_state );
3254 return -4;
3255 }
3256
3257 pfacts = &ioc->pfacts[portnum];
3258
3259 /* Destination (reply area)... */
3260 reply_sz = sizeof(*pfacts);
3261 memset(pfacts, 0, reply_sz);
3262
3263 /* Request area (get_pfacts on the stack right now!) */
3264 req_sz = sizeof(get_pfacts);
3265 memset(&get_pfacts, 0, req_sz);
3266
3267 get_pfacts.Function = MPI_FUNCTION_PORT_FACTS;
3268 get_pfacts.PortNumber = portnum;
3269 /* Assert: All other get_pfacts fields are zero! */
3270
3271 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending get PortFacts(%d) request\n",
3272 ioc->name, portnum));
3273
3274 /* No non-zero fields in the get_pfacts request are greater than
3275 * 1 byte in size, so we can just fire it off as is.
3276 */
3277 ii = mpt_handshake_req_reply_wait(ioc, req_sz, (u32*)&get_pfacts,
3278 reply_sz, (u16*)pfacts, 5 /*seconds*/, sleepFlag);
3279 if (ii != 0)
3280 return ii;
3281
3282 /* Did we get a valid reply? */
3283
3284 /* Now byte swap the necessary fields in the response. */
3285 pfacts->MsgContext = le32_to_cpu(pfacts->MsgContext);
3286 pfacts->IOCStatus = le16_to_cpu(pfacts->IOCStatus);
3287 pfacts->IOCLogInfo = le32_to_cpu(pfacts->IOCLogInfo);
3288 pfacts->MaxDevices = le16_to_cpu(pfacts->MaxDevices);
3289 pfacts->PortSCSIID = le16_to_cpu(pfacts->PortSCSIID);
3290 pfacts->ProtocolFlags = le16_to_cpu(pfacts->ProtocolFlags);
3291 pfacts->MaxPostedCmdBuffers = le16_to_cpu(pfacts->MaxPostedCmdBuffers);
3292 pfacts->MaxPersistentIDs = le16_to_cpu(pfacts->MaxPersistentIDs);
3293 pfacts->MaxLanBuckets = le16_to_cpu(pfacts->MaxLanBuckets);
3294
3295 max_id = (ioc->bus_type == SAS) ? pfacts->PortSCSIID :
3296 pfacts->MaxDevices;
3297 ioc->devices_per_bus = (max_id > 255) ? 256 : max_id;
3298 ioc->number_of_buses = (ioc->devices_per_bus < 256) ? 1 : max_id/256;
3299
3300 /*
3301 * Place all the devices on channels
3302 *
3303 * (for debuging)
3304 */
3305 if (mpt_channel_mapping) {
3306 ioc->devices_per_bus = 1;
3307 ioc->number_of_buses = (max_id > 255) ? 255 : max_id;
3308 }
3309
3310 return 0;
3311}
3312
3313/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
3314/**
3315 * SendIocInit - Send IOCInit request to MPT adapter.
3316 * @ioc: Pointer to MPT_ADAPTER structure
3317 * @sleepFlag: Specifies whether the process can sleep
3318 *
3319 * Send IOCInit followed by PortEnable to bring IOC to OPERATIONAL state.
3320 *
3321 * Returns 0 for success, non-zero for failure.
3322 */
3323static int
3324SendIocInit(MPT_ADAPTER *ioc, int sleepFlag)
3325{
3326 IOCInit_t ioc_init;
3327 MPIDefaultReply_t init_reply;
3328 u32 state;
3329 int r;
3330 int count;
3331 int cntdn;
3332
3333 memset(&ioc_init, 0, sizeof(ioc_init));
3334 memset(&init_reply, 0, sizeof(init_reply));
3335
3336 ioc_init.WhoInit = MPI_WHOINIT_HOST_DRIVER;
3337 ioc_init.Function = MPI_FUNCTION_IOC_INIT;
3338
3339 /* If we are in a recovery mode and we uploaded the FW image,
3340 * then this pointer is not NULL. Skip the upload a second time.
3341 * Set this flag if cached_fw set for either IOC.
3342 */
3343 if (ioc->facts.Flags & MPI_IOCFACTS_FLAGS_FW_DOWNLOAD_BOOT)
3344 ioc->upload_fw = 1;
3345 else
3346 ioc->upload_fw = 0;
3347 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "upload_fw %d facts.Flags=%x\n",
3348 ioc->name, ioc->upload_fw, ioc->facts.Flags));
3349
3350 ioc_init.MaxDevices = (U8)ioc->devices_per_bus;
3351 ioc_init.MaxBuses = (U8)ioc->number_of_buses;
3352
3353 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "facts.MsgVersion=%x\n",
3354 ioc->name, ioc->facts.MsgVersion));
3355 if (ioc->facts.MsgVersion >= MPI_VERSION_01_05) {
3356 // set MsgVersion and HeaderVersion host driver was built with
3357 ioc_init.MsgVersion = cpu_to_le16(MPI_VERSION);
3358 ioc_init.HeaderVersion = cpu_to_le16(MPI_HEADER_VERSION);
3359
3360 if (ioc->facts.Flags & MPI_IOCFACTS_FLAGS_HOST_PAGE_BUFFER_PERSISTENT) {
3361 ioc_init.HostPageBufferSGE = ioc->facts.HostPageBufferSGE;
3362 } else if(mpt_host_page_alloc(ioc, &ioc_init))
3363 return -99;
3364 }
3365 ioc_init.ReplyFrameSize = cpu_to_le16(ioc->reply_sz); /* in BYTES */
3366
3367 if (ioc->sg_addr_size == sizeof(u64)) {
3368 /* Save the upper 32-bits of the request
3369 * (reply) and sense buffers.
3370 */
3371 ioc_init.HostMfaHighAddr = cpu_to_le32((u32)((u64)ioc->alloc_dma >> 32));
3372 ioc_init.SenseBufferHighAddr = cpu_to_le32((u32)((u64)ioc->sense_buf_pool_dma >> 32));
3373 } else {
3374 /* Force 32-bit addressing */
3375 ioc_init.HostMfaHighAddr = cpu_to_le32(0);
3376 ioc_init.SenseBufferHighAddr = cpu_to_le32(0);
3377 }
3378
3379 ioc->facts.CurrentHostMfaHighAddr = ioc_init.HostMfaHighAddr;
3380 ioc->facts.CurrentSenseBufferHighAddr = ioc_init.SenseBufferHighAddr;
3381 ioc->facts.MaxDevices = ioc_init.MaxDevices;
3382 ioc->facts.MaxBuses = ioc_init.MaxBuses;
3383
3384 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending IOCInit (req @ %p)\n",
3385 ioc->name, &ioc_init));
3386
3387 r = mpt_handshake_req_reply_wait(ioc, sizeof(IOCInit_t), (u32*)&ioc_init,
3388 sizeof(MPIDefaultReply_t), (u16*)&init_reply, 10 /*seconds*/, sleepFlag);
3389 if (r != 0) {
3390 printk(MYIOC_s_ERR_FMT "Sending IOCInit failed(%d)!\n",ioc->name, r);
3391 return r;
3392 }
3393
3394 /* No need to byte swap the multibyte fields in the reply
3395 * since we don't even look at its contents.
3396 */
3397
3398 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending PortEnable (req @ %p)\n",
3399 ioc->name, &ioc_init));
3400
3401 if ((r = SendPortEnable(ioc, 0, sleepFlag)) != 0) {
3402 printk(MYIOC_s_ERR_FMT "Sending PortEnable failed(%d)!\n",ioc->name, r);
3403 return r;
3404 }
3405
3406 /* YIKES! SUPER IMPORTANT!!!
3407 * Poll IocState until _OPERATIONAL while IOC is doing
3408 * LoopInit and TargetDiscovery!
3409 */
3410 count = 0;
3411 cntdn = ((sleepFlag == CAN_SLEEP) ? HZ : 1000) * 60; /* 60 seconds */
3412 state = mpt_GetIocState(ioc, 1);
3413 while (state != MPI_IOC_STATE_OPERATIONAL && --cntdn) {
3414 if (sleepFlag == CAN_SLEEP) {
3415 msleep(1);
3416 } else {
3417 mdelay(1);
3418 }
3419
3420 if (!cntdn) {
3421 printk(MYIOC_s_ERR_FMT "Wait IOC_OP state timeout(%d)!\n",
3422 ioc->name, (int)((count+5)/HZ));
3423 return -9;
3424 }
3425
3426 state = mpt_GetIocState(ioc, 1);
3427 count++;
3428 }
3429 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Wait IOC_OPERATIONAL state (cnt=%d)\n",
3430 ioc->name, count));
3431
3432 ioc->aen_event_read_flag=0;
3433 return r;
3434}
3435
3436/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
3437/**
3438 * SendPortEnable - Send PortEnable request to MPT adapter port.
3439 * @ioc: Pointer to MPT_ADAPTER structure
3440 * @portnum: Port number to enable
3441 * @sleepFlag: Specifies whether the process can sleep
3442 *
3443 * Send PortEnable to bring IOC to OPERATIONAL state.
3444 *
3445 * Returns 0 for success, non-zero for failure.
3446 */
3447static int
3448SendPortEnable(MPT_ADAPTER *ioc, int portnum, int sleepFlag)
3449{
3450 PortEnable_t port_enable;
3451 MPIDefaultReply_t reply_buf;
3452 int rc;
3453 int req_sz;
3454 int reply_sz;
3455
3456 /* Destination... */
3457 reply_sz = sizeof(MPIDefaultReply_t);
3458 memset(&reply_buf, 0, reply_sz);
3459
3460 req_sz = sizeof(PortEnable_t);
3461 memset(&port_enable, 0, req_sz);
3462
3463 port_enable.Function = MPI_FUNCTION_PORT_ENABLE;
3464 port_enable.PortNumber = portnum;
3465/* port_enable.ChainOffset = 0; */
3466/* port_enable.MsgFlags = 0; */
3467/* port_enable.MsgContext = 0; */
3468
3469 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending Port(%d)Enable (req @ %p)\n",
3470 ioc->name, portnum, &port_enable));
3471
3472 /* RAID FW may take a long time to enable
3473 */
3474 if (ioc->ir_firmware || ioc->bus_type == SAS) {
3475 rc = mpt_handshake_req_reply_wait(ioc, req_sz,
3476 (u32*)&port_enable, reply_sz, (u16*)&reply_buf,
3477 300 /*seconds*/, sleepFlag);
3478 } else {
3479 rc = mpt_handshake_req_reply_wait(ioc, req_sz,
3480 (u32*)&port_enable, reply_sz, (u16*)&reply_buf,
3481 30 /*seconds*/, sleepFlag);
3482 }
3483 return rc;
3484}
3485
3486/**
3487 * mpt_alloc_fw_memory - allocate firmware memory
3488 * @ioc: Pointer to MPT_ADAPTER structure
3489 * @size: total FW bytes
3490 *
3491 * If memory has already been allocated, the same (cached) value
3492 * is returned.
3493 *
3494 * Return 0 if successful, or non-zero for failure
3495 **/
3496int
3497mpt_alloc_fw_memory(MPT_ADAPTER *ioc, int size)
3498{
3499 int rc;
3500
3501 if (ioc->cached_fw) {
3502 rc = 0; /* use already allocated memory */
3503 goto out;
3504 }
3505 else if (ioc->alt_ioc && ioc->alt_ioc->cached_fw) {
3506 ioc->cached_fw = ioc->alt_ioc->cached_fw; /* use alt_ioc's memory */
3507 ioc->cached_fw_dma = ioc->alt_ioc->cached_fw_dma;
3508 rc = 0;
3509 goto out;
3510 }
3511 ioc->cached_fw = dma_alloc_coherent(&ioc->pcidev->dev, size,
3512 &ioc->cached_fw_dma, GFP_ATOMIC);
3513 if (!ioc->cached_fw) {
3514 printk(MYIOC_s_ERR_FMT "Unable to allocate memory for the cached firmware image!\n",
3515 ioc->name);
3516 rc = -1;
3517 } else {
3518 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "FW Image @ %p[%p], sz=%d[%x] bytes\n",
3519 ioc->name, ioc->cached_fw, (void *)(ulong)ioc->cached_fw_dma, size, size));
3520 ioc->alloc_total += size;
3521 rc = 0;
3522 }
3523 out:
3524 return rc;
3525}
3526
3527/**
3528 * mpt_free_fw_memory - free firmware memory
3529 * @ioc: Pointer to MPT_ADAPTER structure
3530 *
3531 * If alt_img is NULL, delete from ioc structure.
3532 * Else, delete a secondary image in same format.
3533 **/
3534void
3535mpt_free_fw_memory(MPT_ADAPTER *ioc)
3536{
3537 int sz;
3538
3539 if (!ioc->cached_fw)
3540 return;
3541
3542 sz = ioc->facts.FWImageSize;
3543 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "free_fw_memory: FW Image @ %p[%p], sz=%d[%x] bytes\n",
3544 ioc->name, ioc->cached_fw, (void *)(ulong)ioc->cached_fw_dma, sz, sz));
3545 dma_free_coherent(&ioc->pcidev->dev, sz, ioc->cached_fw,
3546 ioc->cached_fw_dma);
3547 ioc->alloc_total -= sz;
3548 ioc->cached_fw = NULL;
3549}
3550
3551/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
3552/**
3553 * mpt_do_upload - Construct and Send FWUpload request to MPT adapter port.
3554 * @ioc: Pointer to MPT_ADAPTER structure
3555 * @sleepFlag: Specifies whether the process can sleep
3556 *
3557 * Returns 0 for success, >0 for handshake failure
3558 * <0 for fw upload failure.
3559 *
3560 * Remark: If bound IOC and a successful FWUpload was performed
3561 * on the bound IOC, the second image is discarded
3562 * and memory is free'd. Both channels must upload to prevent
3563 * IOC from running in degraded mode.
3564 */
3565static int
3566mpt_do_upload(MPT_ADAPTER *ioc, int sleepFlag)
3567{
3568 u8 reply[sizeof(FWUploadReply_t)];
3569 FWUpload_t *prequest;
3570 FWUploadReply_t *preply;
3571 FWUploadTCSGE_t *ptcsge;
3572 u32 flagsLength;
3573 int ii, sz, reply_sz;
3574 int cmdStatus;
3575 int request_size;
3576 /* If the image size is 0, we are done.
3577 */
3578 if ((sz = ioc->facts.FWImageSize) == 0)
3579 return 0;
3580
3581 if (mpt_alloc_fw_memory(ioc, ioc->facts.FWImageSize) != 0)
3582 return -ENOMEM;
3583
3584 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT ": FW Image @ %p[%p], sz=%d[%x] bytes\n",
3585 ioc->name, ioc->cached_fw, (void *)(ulong)ioc->cached_fw_dma, sz, sz));
3586
3587 prequest = (sleepFlag == NO_SLEEP) ? kzalloc(ioc->req_sz, GFP_ATOMIC) :
3588 kzalloc(ioc->req_sz, GFP_KERNEL);
3589 if (!prequest) {
3590 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "fw upload failed "
3591 "while allocating memory \n", ioc->name));
3592 mpt_free_fw_memory(ioc);
3593 return -ENOMEM;
3594 }
3595
3596 preply = (FWUploadReply_t *)&reply;
3597
3598 reply_sz = sizeof(reply);
3599 memset(preply, 0, reply_sz);
3600
3601 prequest->ImageType = MPI_FW_UPLOAD_ITYPE_FW_IOC_MEM;
3602 prequest->Function = MPI_FUNCTION_FW_UPLOAD;
3603
3604 ptcsge = (FWUploadTCSGE_t *) &prequest->SGL;
3605 ptcsge->DetailsLength = 12;
3606 ptcsge->Flags = MPI_SGE_FLAGS_TRANSACTION_ELEMENT;
3607 ptcsge->ImageSize = cpu_to_le32(sz);
3608 ptcsge++;
3609
3610 flagsLength = MPT_SGE_FLAGS_SSIMPLE_READ | sz;
3611 ioc->add_sge((char *)ptcsge, flagsLength, ioc->cached_fw_dma);
3612 request_size = offsetof(FWUpload_t, SGL) + sizeof(FWUploadTCSGE_t) +
3613 ioc->SGE_size;
3614 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending FW Upload "
3615 " (req @ %p) fw_size=%d mf_request_size=%d\n", ioc->name, prequest,
3616 ioc->facts.FWImageSize, request_size));
3617 DBG_DUMP_FW_REQUEST_FRAME(ioc, (u32 *)prequest);
3618
3619 ii = mpt_handshake_req_reply_wait(ioc, request_size, (u32 *)prequest,
3620 reply_sz, (u16 *)preply, 65 /*seconds*/, sleepFlag);
3621
3622 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "FW Upload completed "
3623 "rc=%x \n", ioc->name, ii));
3624
3625 cmdStatus = -EFAULT;
3626 if (ii == 0) {
3627 /* Handshake transfer was complete and successful.
3628 * Check the Reply Frame.
3629 */
3630 int status;
3631 status = le16_to_cpu(preply->IOCStatus) &
3632 MPI_IOCSTATUS_MASK;
3633 if (status == MPI_IOCSTATUS_SUCCESS &&
3634 ioc->facts.FWImageSize ==
3635 le32_to_cpu(preply->ActualImageSize))
3636 cmdStatus = 0;
3637 }
3638 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT ": do_upload cmdStatus=%d \n",
3639 ioc->name, cmdStatus));
3640
3641
3642 if (cmdStatus) {
3643 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "fw upload failed, "
3644 "freeing image \n", ioc->name));
3645 mpt_free_fw_memory(ioc);
3646 }
3647 kfree(prequest);
3648
3649 return cmdStatus;
3650}
3651
3652/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
3653/**
3654 * mpt_downloadboot - DownloadBoot code
3655 * @ioc: Pointer to MPT_ADAPTER structure
3656 * @pFwHeader: Pointer to firmware header info
3657 * @sleepFlag: Specifies whether the process can sleep
3658 *
3659 * FwDownloadBoot requires Programmed IO access.
3660 *
3661 * Returns 0 for success
3662 * -1 FW Image size is 0
3663 * -2 No valid cached_fw Pointer
3664 * <0 for fw upload failure.
3665 */
3666static int
3667mpt_downloadboot(MPT_ADAPTER *ioc, MpiFwHeader_t *pFwHeader, int sleepFlag)
3668{
3669 MpiExtImageHeader_t *pExtImage;
3670 u32 fwSize;
3671 u32 diag0val;
3672 int count;
3673 u32 *ptrFw;
3674 u32 diagRwData;
3675 u32 nextImage;
3676 u32 load_addr;
3677 u32 ioc_state=0;
3678
3679 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "downloadboot: fw size 0x%x (%d), FW Ptr %p\n",
3680 ioc->name, pFwHeader->ImageSize, pFwHeader->ImageSize, pFwHeader));
3681
3682 CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF);
3683 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_1ST_KEY_VALUE);
3684 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_2ND_KEY_VALUE);
3685 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_3RD_KEY_VALUE);
3686 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_4TH_KEY_VALUE);
3687 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_5TH_KEY_VALUE);
3688
3689 CHIPREG_WRITE32(&ioc->chip->Diagnostic, (MPI_DIAG_PREVENT_IOC_BOOT | MPI_DIAG_DISABLE_ARM));
3690
3691 /* wait 1 msec */
3692 if (sleepFlag == CAN_SLEEP) {
3693 msleep(1);
3694 } else {
3695 mdelay (1);
3696 }
3697
3698 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
3699 CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val | MPI_DIAG_RESET_ADAPTER);
3700
3701 for (count = 0; count < 30; count ++) {
3702 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
3703 if (!(diag0val & MPI_DIAG_RESET_ADAPTER)) {
3704 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "RESET_ADAPTER cleared, count=%d\n",
3705 ioc->name, count));
3706 break;
3707 }
3708 /* wait .1 sec */
3709 if (sleepFlag == CAN_SLEEP) {
3710 msleep (100);
3711 } else {
3712 mdelay (100);
3713 }
3714 }
3715
3716 if ( count == 30 ) {
3717 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "downloadboot failed! "
3718 "Unable to get MPI_DIAG_DRWE mode, diag0val=%x\n",
3719 ioc->name, diag0val));
3720 return -3;
3721 }
3722
3723 CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF);
3724 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_1ST_KEY_VALUE);
3725 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_2ND_KEY_VALUE);
3726 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_3RD_KEY_VALUE);
3727 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_4TH_KEY_VALUE);
3728 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_5TH_KEY_VALUE);
3729
3730 /* Set the DiagRwEn and Disable ARM bits */
3731 CHIPREG_WRITE32(&ioc->chip->Diagnostic, (MPI_DIAG_RW_ENABLE | MPI_DIAG_DISABLE_ARM));
3732
3733 fwSize = (pFwHeader->ImageSize + 3)/4;
3734 ptrFw = (u32 *) pFwHeader;
3735
3736 /* Write the LoadStartAddress to the DiagRw Address Register
3737 * using Programmed IO
3738 */
3739 if (ioc->errata_flag_1064)
3740 pci_enable_io_access(ioc->pcidev);
3741
3742 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, pFwHeader->LoadStartAddress);
3743 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "LoadStart addr written 0x%x \n",
3744 ioc->name, pFwHeader->LoadStartAddress));
3745
3746 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Write FW Image: 0x%x bytes @ %p\n",
3747 ioc->name, fwSize*4, ptrFw));
3748 while (fwSize--) {
3749 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, *ptrFw++);
3750 }
3751
3752 nextImage = pFwHeader->NextImageHeaderOffset;
3753 while (nextImage) {
3754 pExtImage = (MpiExtImageHeader_t *) ((char *)pFwHeader + nextImage);
3755
3756 load_addr = pExtImage->LoadStartAddress;
3757
3758 fwSize = (pExtImage->ImageSize + 3) >> 2;
3759 ptrFw = (u32 *)pExtImage;
3760
3761 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Write Ext Image: 0x%x (%d) bytes @ %p load_addr=%x\n",
3762 ioc->name, fwSize*4, fwSize*4, ptrFw, load_addr));
3763 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, load_addr);
3764
3765 while (fwSize--) {
3766 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, *ptrFw++);
3767 }
3768 nextImage = pExtImage->NextImageHeaderOffset;
3769 }
3770
3771 /* Write the IopResetVectorRegAddr */
3772 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Write IopResetVector Addr=%x! \n", ioc->name, pFwHeader->IopResetRegAddr));
3773 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, pFwHeader->IopResetRegAddr);
3774
3775 /* Write the IopResetVectorValue */
3776 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Write IopResetVector Value=%x! \n", ioc->name, pFwHeader->IopResetVectorValue));
3777 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, pFwHeader->IopResetVectorValue);
3778
3779 /* Clear the internal flash bad bit - autoincrementing register,
3780 * so must do two writes.
3781 */
3782 if (ioc->bus_type == SPI) {
3783 /*
3784 * 1030 and 1035 H/W errata, workaround to access
3785 * the ClearFlashBadSignatureBit
3786 */
3787 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, 0x3F000000);
3788 diagRwData = CHIPREG_PIO_READ32(&ioc->pio_chip->DiagRwData);
3789 diagRwData |= 0x40000000;
3790 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, 0x3F000000);
3791 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, diagRwData);
3792
3793 } else /* if((ioc->bus_type == SAS) || (ioc->bus_type == FC)) */ {
3794 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
3795 CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val |
3796 MPI_DIAG_CLEAR_FLASH_BAD_SIG);
3797
3798 /* wait 1 msec */
3799 if (sleepFlag == CAN_SLEEP) {
3800 msleep (1);
3801 } else {
3802 mdelay (1);
3803 }
3804 }
3805
3806 if (ioc->errata_flag_1064)
3807 pci_disable_io_access(ioc->pcidev);
3808
3809 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
3810 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "downloadboot diag0val=%x, "
3811 "turning off PREVENT_IOC_BOOT, DISABLE_ARM, RW_ENABLE\n",
3812 ioc->name, diag0val));
3813 diag0val &= ~(MPI_DIAG_PREVENT_IOC_BOOT | MPI_DIAG_DISABLE_ARM | MPI_DIAG_RW_ENABLE);
3814 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "downloadboot now diag0val=%x\n",
3815 ioc->name, diag0val));
3816 CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val);
3817
3818 /* Write 0xFF to reset the sequencer */
3819 CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF);
3820
3821 if (ioc->bus_type == SAS) {
3822 ioc_state = mpt_GetIocState(ioc, 0);
3823 if ( (GetIocFacts(ioc, sleepFlag,
3824 MPT_HOSTEVENT_IOC_BRINGUP)) != 0 ) {
3825 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "GetIocFacts failed: IocState=%x\n",
3826 ioc->name, ioc_state));
3827 return -EFAULT;
3828 }
3829 }
3830
3831 for (count=0; count<HZ*20; count++) {
3832 if ((ioc_state = mpt_GetIocState(ioc, 0)) & MPI_IOC_STATE_READY) {
3833 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT
3834 "downloadboot successful! (count=%d) IocState=%x\n",
3835 ioc->name, count, ioc_state));
3836 if (ioc->bus_type == SAS) {
3837 return 0;
3838 }
3839 if ((SendIocInit(ioc, sleepFlag)) != 0) {
3840 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT
3841 "downloadboot: SendIocInit failed\n",
3842 ioc->name));
3843 return -EFAULT;
3844 }
3845 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT
3846 "downloadboot: SendIocInit successful\n",
3847 ioc->name));
3848 return 0;
3849 }
3850 if (sleepFlag == CAN_SLEEP) {
3851 msleep (10);
3852 } else {
3853 mdelay (10);
3854 }
3855 }
3856 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT
3857 "downloadboot failed! IocState=%x\n",ioc->name, ioc_state));
3858 return -EFAULT;
3859}
3860
3861/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
3862/**
3863 * KickStart - Perform hard reset of MPT adapter.
3864 * @ioc: Pointer to MPT_ADAPTER structure
3865 * @force: Force hard reset
3866 * @sleepFlag: Specifies whether the process can sleep
3867 *
3868 * This routine places MPT adapter in diagnostic mode via the
3869 * WriteSequence register, and then performs a hard reset of adapter
3870 * via the Diagnostic register.
3871 *
3872 * Inputs: sleepflag - CAN_SLEEP (non-interrupt thread)
3873 * or NO_SLEEP (interrupt thread, use mdelay)
3874 * force - 1 if doorbell active, board fault state
3875 * board operational, IOC_RECOVERY or
3876 * IOC_BRINGUP and there is an alt_ioc.
3877 * 0 else
3878 *
3879 * Returns:
3880 * 1 - hard reset, READY
3881 * 0 - no reset due to History bit, READY
3882 * -1 - no reset due to History bit but not READY
3883 * OR reset but failed to come READY
3884 * -2 - no reset, could not enter DIAG mode
3885 * -3 - reset but bad FW bit
3886 */
3887static int
3888KickStart(MPT_ADAPTER *ioc, int force, int sleepFlag)
3889{
3890 int hard_reset_done = 0;
3891 u32 ioc_state=0;
3892 int cnt,cntdn;
3893
3894 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "KickStarting!\n", ioc->name));
3895 if (ioc->bus_type == SPI) {
3896 /* Always issue a Msg Unit Reset first. This will clear some
3897 * SCSI bus hang conditions.
3898 */
3899 SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, sleepFlag);
3900
3901 if (sleepFlag == CAN_SLEEP) {
3902 msleep (1000);
3903 } else {
3904 mdelay (1000);
3905 }
3906 }
3907
3908 hard_reset_done = mpt_diag_reset(ioc, force, sleepFlag);
3909 if (hard_reset_done < 0)
3910 return hard_reset_done;
3911
3912 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Diagnostic reset successful!\n",
3913 ioc->name));
3914
3915 cntdn = ((sleepFlag == CAN_SLEEP) ? HZ : 1000) * 2; /* 2 seconds */
3916 for (cnt=0; cnt<cntdn; cnt++) {
3917 ioc_state = mpt_GetIocState(ioc, 1);
3918 if ((ioc_state == MPI_IOC_STATE_READY) || (ioc_state == MPI_IOC_STATE_OPERATIONAL)) {
3919 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "KickStart successful! (cnt=%d)\n",
3920 ioc->name, cnt));
3921 return hard_reset_done;
3922 }
3923 if (sleepFlag == CAN_SLEEP) {
3924 msleep (10);
3925 } else {
3926 mdelay (10);
3927 }
3928 }
3929
3930 dinitprintk(ioc, printk(MYIOC_s_ERR_FMT "Failed to come READY after reset! IocState=%x\n",
3931 ioc->name, mpt_GetIocState(ioc, 0)));
3932 return -1;
3933}
3934
3935/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
3936/**
3937 * mpt_diag_reset - Perform hard reset of the adapter.
3938 * @ioc: Pointer to MPT_ADAPTER structure
3939 * @ignore: Set if to honor and clear to ignore
3940 * the reset history bit
3941 * @sleepFlag: CAN_SLEEP if called in a non-interrupt thread,
3942 * else set to NO_SLEEP (use mdelay instead)
3943 *
3944 * This routine places the adapter in diagnostic mode via the
3945 * WriteSequence register and then performs a hard reset of adapter
3946 * via the Diagnostic register. Adapter should be in ready state
3947 * upon successful completion.
3948 *
3949 * Returns: 1 hard reset successful
3950 * 0 no reset performed because reset history bit set
3951 * -2 enabling diagnostic mode failed
3952 * -3 diagnostic reset failed
3953 */
3954static int
3955mpt_diag_reset(MPT_ADAPTER *ioc, int ignore, int sleepFlag)
3956{
3957 u32 diag0val;
3958 u32 doorbell;
3959 int hard_reset_done = 0;
3960 int count = 0;
3961 u32 diag1val = 0;
3962 MpiFwHeader_t *cached_fw; /* Pointer to FW */
3963 u8 cb_idx;
3964
3965 /* Clear any existing interrupts */
3966 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
3967
3968 if (ioc->pcidev->device == MPI_MANUFACTPAGE_DEVID_SAS1078) {
3969
3970 if (!ignore)
3971 return 0;
3972
3973 drsprintk(ioc, printk(MYIOC_s_WARN_FMT "%s: Doorbell=%p; 1078 reset "
3974 "address=%p\n", ioc->name, __func__,
3975 &ioc->chip->Doorbell, &ioc->chip->Reset_1078));
3976 CHIPREG_WRITE32(&ioc->chip->Reset_1078, 0x07);
3977 if (sleepFlag == CAN_SLEEP)
3978 msleep(1);
3979 else
3980 mdelay(1);
3981
3982 /*
3983 * Call each currently registered protocol IOC reset handler
3984 * with pre-reset indication.
3985 * NOTE: If we're doing _IOC_BRINGUP, there can be no
3986 * MptResetHandlers[] registered yet.
3987 */
3988 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
3989 if (MptResetHandlers[cb_idx])
3990 (*(MptResetHandlers[cb_idx]))(ioc,
3991 MPT_IOC_PRE_RESET);
3992 }
3993
3994 for (count = 0; count < 60; count ++) {
3995 doorbell = CHIPREG_READ32(&ioc->chip->Doorbell);
3996 doorbell &= MPI_IOC_STATE_MASK;
3997
3998 drsprintk(ioc, printk(MYIOC_s_DEBUG_FMT
3999 "looking for READY STATE: doorbell=%x"
4000 " count=%d\n",
4001 ioc->name, doorbell, count));
4002
4003 if (doorbell == MPI_IOC_STATE_READY) {
4004 return 1;
4005 }
4006
4007 /* wait 1 sec */
4008 if (sleepFlag == CAN_SLEEP)
4009 msleep(1000);
4010 else
4011 mdelay(1000);
4012 }
4013 return -1;
4014 }
4015
4016 /* Use "Diagnostic reset" method! (only thing available!) */
4017 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
4018
4019 if (ioc->debug_level & MPT_DEBUG) {
4020 if (ioc->alt_ioc)
4021 diag1val = CHIPREG_READ32(&ioc->alt_ioc->chip->Diagnostic);
4022 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "DbG1: diag0=%08x, diag1=%08x\n",
4023 ioc->name, diag0val, diag1val));
4024 }
4025
4026 /* Do the reset if we are told to ignore the reset history
4027 * or if the reset history is 0
4028 */
4029 if (ignore || !(diag0val & MPI_DIAG_RESET_HISTORY)) {
4030 while ((diag0val & MPI_DIAG_DRWE) == 0) {
4031 /* Write magic sequence to WriteSequence register
4032 * Loop until in diagnostic mode
4033 */
4034 CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF);
4035 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_1ST_KEY_VALUE);
4036 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_2ND_KEY_VALUE);
4037 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_3RD_KEY_VALUE);
4038 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_4TH_KEY_VALUE);
4039 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_5TH_KEY_VALUE);
4040
4041 /* wait 100 msec */
4042 if (sleepFlag == CAN_SLEEP) {
4043 msleep (100);
4044 } else {
4045 mdelay (100);
4046 }
4047
4048 count++;
4049 if (count > 20) {
4050 printk(MYIOC_s_ERR_FMT "Enable Diagnostic mode FAILED! (%02xh)\n",
4051 ioc->name, diag0val);
4052 return -2;
4053
4054 }
4055
4056 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
4057
4058 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Wrote magic DiagWriteEn sequence (%x)\n",
4059 ioc->name, diag0val));
4060 }
4061
4062 if (ioc->debug_level & MPT_DEBUG) {
4063 if (ioc->alt_ioc)
4064 diag1val = CHIPREG_READ32(&ioc->alt_ioc->chip->Diagnostic);
4065 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "DbG2: diag0=%08x, diag1=%08x\n",
4066 ioc->name, diag0val, diag1val));
4067 }
4068 /*
4069 * Disable the ARM (Bug fix)
4070 *
4071 */
4072 CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val | MPI_DIAG_DISABLE_ARM);
4073 mdelay(1);
4074
4075 /*
4076 * Now hit the reset bit in the Diagnostic register
4077 * (THE BIG HAMMER!) (Clears DRWE bit).
4078 */
4079 CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val | MPI_DIAG_RESET_ADAPTER);
4080 hard_reset_done = 1;
4081 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Diagnostic reset performed\n",
4082 ioc->name));
4083
4084 /*
4085 * Call each currently registered protocol IOC reset handler
4086 * with pre-reset indication.
4087 * NOTE: If we're doing _IOC_BRINGUP, there can be no
4088 * MptResetHandlers[] registered yet.
4089 */
4090 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
4091 if (MptResetHandlers[cb_idx]) {
4092 mpt_signal_reset(cb_idx,
4093 ioc, MPT_IOC_PRE_RESET);
4094 if (ioc->alt_ioc) {
4095 mpt_signal_reset(cb_idx,
4096 ioc->alt_ioc, MPT_IOC_PRE_RESET);
4097 }
4098 }
4099 }
4100
4101 if (ioc->cached_fw)
4102 cached_fw = (MpiFwHeader_t *)ioc->cached_fw;
4103 else if (ioc->alt_ioc && ioc->alt_ioc->cached_fw)
4104 cached_fw = (MpiFwHeader_t *)ioc->alt_ioc->cached_fw;
4105 else
4106 cached_fw = NULL;
4107 if (cached_fw) {
4108 /* If the DownloadBoot operation fails, the
4109 * IOC will be left unusable. This is a fatal error
4110 * case. _diag_reset will return < 0
4111 */
4112 for (count = 0; count < 30; count ++) {
4113 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
4114 if (!(diag0val & MPI_DIAG_RESET_ADAPTER)) {
4115 break;
4116 }
4117
4118 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "cached_fw: diag0val=%x count=%d\n",
4119 ioc->name, diag0val, count));
4120 /* wait 1 sec */
4121 if (sleepFlag == CAN_SLEEP) {
4122 msleep (1000);
4123 } else {
4124 mdelay (1000);
4125 }
4126 }
4127 if ((count = mpt_downloadboot(ioc, cached_fw, sleepFlag)) < 0) {
4128 printk(MYIOC_s_WARN_FMT
4129 "firmware downloadboot failure (%d)!\n", ioc->name, count);
4130 }
4131
4132 } else {
4133 /* Wait for FW to reload and for board
4134 * to go to the READY state.
4135 * Maximum wait is 60 seconds.
4136 * If fail, no error will check again
4137 * with calling program.
4138 */
4139 for (count = 0; count < 60; count ++) {
4140 doorbell = CHIPREG_READ32(&ioc->chip->Doorbell);
4141 doorbell &= MPI_IOC_STATE_MASK;
4142
4143 drsprintk(ioc, printk(MYIOC_s_DEBUG_FMT
4144 "looking for READY STATE: doorbell=%x"
4145 " count=%d\n", ioc->name, doorbell, count));
4146
4147 if (doorbell == MPI_IOC_STATE_READY) {
4148 break;
4149 }
4150
4151 /* wait 1 sec */
4152 if (sleepFlag == CAN_SLEEP) {
4153 msleep (1000);
4154 } else {
4155 mdelay (1000);
4156 }
4157 }
4158
4159 if (doorbell != MPI_IOC_STATE_READY)
4160 printk(MYIOC_s_ERR_FMT "Failed to come READY "
4161 "after reset! IocState=%x", ioc->name,
4162 doorbell);
4163 }
4164 }
4165
4166 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
4167 if (ioc->debug_level & MPT_DEBUG) {
4168 if (ioc->alt_ioc)
4169 diag1val = CHIPREG_READ32(&ioc->alt_ioc->chip->Diagnostic);
4170 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "DbG3: diag0=%08x, diag1=%08x\n",
4171 ioc->name, diag0val, diag1val));
4172 }
4173
4174 /* Clear RESET_HISTORY bit! Place board in the
4175 * diagnostic mode to update the diag register.
4176 */
4177 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
4178 count = 0;
4179 while ((diag0val & MPI_DIAG_DRWE) == 0) {
4180 /* Write magic sequence to WriteSequence register
4181 * Loop until in diagnostic mode
4182 */
4183 CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF);
4184 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_1ST_KEY_VALUE);
4185 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_2ND_KEY_VALUE);
4186 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_3RD_KEY_VALUE);
4187 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_4TH_KEY_VALUE);
4188 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_5TH_KEY_VALUE);
4189
4190 /* wait 100 msec */
4191 if (sleepFlag == CAN_SLEEP) {
4192 msleep (100);
4193 } else {
4194 mdelay (100);
4195 }
4196
4197 count++;
4198 if (count > 20) {
4199 printk(MYIOC_s_ERR_FMT "Enable Diagnostic mode FAILED! (%02xh)\n",
4200 ioc->name, diag0val);
4201 break;
4202 }
4203 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
4204 }
4205 diag0val &= ~MPI_DIAG_RESET_HISTORY;
4206 CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val);
4207 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
4208 if (diag0val & MPI_DIAG_RESET_HISTORY) {
4209 printk(MYIOC_s_WARN_FMT "ResetHistory bit failed to clear!\n",
4210 ioc->name);
4211 }
4212
4213 /* Disable Diagnostic Mode
4214 */
4215 CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFFFFFFFF);
4216
4217 /* Check FW reload status flags.
4218 */
4219 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
4220 if (diag0val & (MPI_DIAG_FLASH_BAD_SIG | MPI_DIAG_RESET_ADAPTER | MPI_DIAG_DISABLE_ARM)) {
4221 printk(MYIOC_s_ERR_FMT "Diagnostic reset FAILED! (%02xh)\n",
4222 ioc->name, diag0val);
4223 return -3;
4224 }
4225
4226 if (ioc->debug_level & MPT_DEBUG) {
4227 if (ioc->alt_ioc)
4228 diag1val = CHIPREG_READ32(&ioc->alt_ioc->chip->Diagnostic);
4229 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "DbG4: diag0=%08x, diag1=%08x\n",
4230 ioc->name, diag0val, diag1val));
4231 }
4232
4233 /*
4234 * Reset flag that says we've enabled event notification
4235 */
4236 ioc->facts.EventState = 0;
4237
4238 if (ioc->alt_ioc)
4239 ioc->alt_ioc->facts.EventState = 0;
4240
4241 return hard_reset_done;
4242}
4243
4244/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
4245/**
4246 * SendIocReset - Send IOCReset request to MPT adapter.
4247 * @ioc: Pointer to MPT_ADAPTER structure
4248 * @reset_type: reset type, expected values are
4249 * %MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET or %MPI_FUNCTION_IO_UNIT_RESET
4250 * @sleepFlag: Specifies whether the process can sleep
4251 *
4252 * Send IOCReset request to the MPT adapter.
4253 *
4254 * Returns 0 for success, non-zero for failure.
4255 */
4256static int
4257SendIocReset(MPT_ADAPTER *ioc, u8 reset_type, int sleepFlag)
4258{
4259 int r;
4260 u32 state;
4261 int cntdn, count;
4262
4263 drsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending IOC reset(0x%02x)!\n",
4264 ioc->name, reset_type));
4265 CHIPREG_WRITE32(&ioc->chip->Doorbell, reset_type<<MPI_DOORBELL_FUNCTION_SHIFT);
4266 if ((r = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0)
4267 return r;
4268
4269 /* FW ACK'd request, wait for READY state
4270 */
4271 count = 0;
4272 cntdn = ((sleepFlag == CAN_SLEEP) ? HZ : 1000) * 15; /* 15 seconds */
4273
4274 while ((state = mpt_GetIocState(ioc, 1)) != MPI_IOC_STATE_READY) {
4275 cntdn--;
4276 count++;
4277 if (!cntdn) {
4278 if (sleepFlag != CAN_SLEEP)
4279 count *= 10;
4280
4281 printk(MYIOC_s_ERR_FMT
4282 "Wait IOC_READY state (0x%x) timeout(%d)!\n",
4283 ioc->name, state, (int)((count+5)/HZ));
4284 return -ETIME;
4285 }
4286
4287 if (sleepFlag == CAN_SLEEP) {
4288 msleep(1);
4289 } else {
4290 mdelay (1); /* 1 msec delay */
4291 }
4292 }
4293
4294 /* TODO!
4295 * Cleanup all event stuff for this IOC; re-issue EventNotification
4296 * request if needed.
4297 */
4298 if (ioc->facts.Function)
4299 ioc->facts.EventState = 0;
4300
4301 return 0;
4302}
4303
4304/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
4305/**
4306 * initChainBuffers - Allocate memory for and initialize chain buffers
4307 * @ioc: Pointer to MPT_ADAPTER structure
4308 *
4309 * Allocates memory for and initializes chain buffers,
4310 * chain buffer control arrays and spinlock.
4311 */
4312static int
4313initChainBuffers(MPT_ADAPTER *ioc)
4314{
4315 u8 *mem;
4316 int sz, ii, num_chain;
4317 int scale, num_sge, numSGE;
4318
4319 /* ReqToChain size must equal the req_depth
4320 * index = req_idx
4321 */
4322 if (ioc->ReqToChain == NULL) {
4323 sz = ioc->req_depth * sizeof(int);
4324 mem = kmalloc(sz, GFP_ATOMIC);
4325 if (mem == NULL)
4326 return -1;
4327
4328 ioc->ReqToChain = (int *) mem;
4329 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ReqToChain alloc @ %p, sz=%d bytes\n",
4330 ioc->name, mem, sz));
4331 mem = kmalloc(sz, GFP_ATOMIC);
4332 if (mem == NULL)
4333 return -1;
4334
4335 ioc->RequestNB = (int *) mem;
4336 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "RequestNB alloc @ %p, sz=%d bytes\n",
4337 ioc->name, mem, sz));
4338 }
4339 for (ii = 0; ii < ioc->req_depth; ii++) {
4340 ioc->ReqToChain[ii] = MPT_HOST_NO_CHAIN;
4341 }
4342
4343 /* ChainToChain size must equal the total number
4344 * of chain buffers to be allocated.
4345 * index = chain_idx
4346 *
4347 * Calculate the number of chain buffers needed(plus 1) per I/O
4348 * then multiply the maximum number of simultaneous cmds
4349 *
4350 * num_sge = num sge in request frame + last chain buffer
4351 * scale = num sge per chain buffer if no chain element
4352 */
4353 scale = ioc->req_sz / ioc->SGE_size;
4354 if (ioc->sg_addr_size == sizeof(u64))
4355 num_sge = scale + (ioc->req_sz - 60) / ioc->SGE_size;
4356 else
4357 num_sge = 1 + scale + (ioc->req_sz - 64) / ioc->SGE_size;
4358
4359 if (ioc->sg_addr_size == sizeof(u64)) {
4360 numSGE = (scale - 1) * (ioc->facts.MaxChainDepth-1) + scale +
4361 (ioc->req_sz - 60) / ioc->SGE_size;
4362 } else {
4363 numSGE = 1 + (scale - 1) * (ioc->facts.MaxChainDepth-1) +
4364 scale + (ioc->req_sz - 64) / ioc->SGE_size;
4365 }
4366 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "num_sge=%d numSGE=%d\n",
4367 ioc->name, num_sge, numSGE));
4368
4369 if (ioc->bus_type == FC) {
4370 if (numSGE > MPT_SCSI_FC_SG_DEPTH)
4371 numSGE = MPT_SCSI_FC_SG_DEPTH;
4372 } else {
4373 if (numSGE > MPT_SCSI_SG_DEPTH)
4374 numSGE = MPT_SCSI_SG_DEPTH;
4375 }
4376
4377 num_chain = 1;
4378 while (numSGE - num_sge > 0) {
4379 num_chain++;
4380 num_sge += (scale - 1);
4381 }
4382 num_chain++;
4383
4384 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Now numSGE=%d num_sge=%d num_chain=%d\n",
4385 ioc->name, numSGE, num_sge, num_chain));
4386
4387 if (ioc->bus_type == SPI)
4388 num_chain *= MPT_SCSI_CAN_QUEUE;
4389 else if (ioc->bus_type == SAS)
4390 num_chain *= MPT_SAS_CAN_QUEUE;
4391 else
4392 num_chain *= MPT_FC_CAN_QUEUE;
4393
4394 ioc->num_chain = num_chain;
4395
4396 sz = num_chain * sizeof(int);
4397 if (ioc->ChainToChain == NULL) {
4398 mem = kmalloc(sz, GFP_ATOMIC);
4399 if (mem == NULL)
4400 return -1;
4401
4402 ioc->ChainToChain = (int *) mem;
4403 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ChainToChain alloc @ %p, sz=%d bytes\n",
4404 ioc->name, mem, sz));
4405 } else {
4406 mem = (u8 *) ioc->ChainToChain;
4407 }
4408 memset(mem, 0xFF, sz);
4409 return num_chain;
4410}
4411
4412/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
4413/**
4414 * PrimeIocFifos - Initialize IOC request and reply FIFOs.
4415 * @ioc: Pointer to MPT_ADAPTER structure
4416 *
4417 * This routine allocates memory for the MPT reply and request frame
4418 * pools (if necessary), and primes the IOC reply FIFO with
4419 * reply frames.
4420 *
4421 * Returns 0 for success, non-zero for failure.
4422 */
4423static int
4424PrimeIocFifos(MPT_ADAPTER *ioc)
4425{
4426 MPT_FRAME_HDR *mf;
4427 unsigned long flags;
4428 dma_addr_t alloc_dma;
4429 u8 *mem;
4430 int i, reply_sz, sz, total_size, num_chain;
4431 u64 dma_mask;
4432
4433 dma_mask = 0;
4434
4435 /* Prime reply FIFO... */
4436
4437 if (ioc->reply_frames == NULL) {
4438 if ( (num_chain = initChainBuffers(ioc)) < 0)
4439 return -1;
4440 /*
4441 * 1078 errata workaround for the 36GB limitation
4442 */
4443 if (ioc->pcidev->device == MPI_MANUFACTPAGE_DEVID_SAS1078 &&
4444 ioc->dma_mask > DMA_BIT_MASK(35)) {
4445 if (!dma_set_mask(&ioc->pcidev->dev, DMA_BIT_MASK(32))
4446 && !dma_set_coherent_mask(&ioc->pcidev->dev, DMA_BIT_MASK(32))) {
4447 dma_mask = DMA_BIT_MASK(35);
4448 d36memprintk(ioc, printk(MYIOC_s_DEBUG_FMT
4449 "setting 35 bit addressing for "
4450 "Request/Reply/Chain and Sense Buffers\n",
4451 ioc->name));
4452 } else {
4453 /*Reseting DMA mask to 64 bit*/
4454 dma_set_mask(&ioc->pcidev->dev,
4455 DMA_BIT_MASK(64));
4456 dma_set_coherent_mask(&ioc->pcidev->dev,
4457 DMA_BIT_MASK(64));
4458
4459 printk(MYIOC_s_ERR_FMT
4460 "failed setting 35 bit addressing for "
4461 "Request/Reply/Chain and Sense Buffers\n",
4462 ioc->name);
4463 return -1;
4464 }
4465 }
4466
4467 total_size = reply_sz = (ioc->reply_sz * ioc->reply_depth);
4468 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ReplyBuffer sz=%d bytes, ReplyDepth=%d\n",
4469 ioc->name, ioc->reply_sz, ioc->reply_depth));
4470 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ReplyBuffer sz=%d[%x] bytes\n",
4471 ioc->name, reply_sz, reply_sz));
4472
4473 sz = (ioc->req_sz * ioc->req_depth);
4474 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "RequestBuffer sz=%d bytes, RequestDepth=%d\n",
4475 ioc->name, ioc->req_sz, ioc->req_depth));
4476 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "RequestBuffer sz=%d[%x] bytes\n",
4477 ioc->name, sz, sz));
4478 total_size += sz;
4479
4480 sz = num_chain * ioc->req_sz; /* chain buffer pool size */
4481 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ChainBuffer sz=%d bytes, ChainDepth=%d\n",
4482 ioc->name, ioc->req_sz, num_chain));
4483 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ChainBuffer sz=%d[%x] bytes num_chain=%d\n",
4484 ioc->name, sz, sz, num_chain));
4485
4486 total_size += sz;
4487 mem = dma_alloc_coherent(&ioc->pcidev->dev, total_size,
4488 &alloc_dma, GFP_KERNEL);
4489 if (mem == NULL) {
4490 printk(MYIOC_s_ERR_FMT "Unable to allocate Reply, Request, Chain Buffers!\n",
4491 ioc->name);
4492 goto out_fail;
4493 }
4494
4495 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Total alloc @ %p[%p], sz=%d[%x] bytes\n",
4496 ioc->name, mem, (void *)(ulong)alloc_dma, total_size, total_size));
4497
4498 memset(mem, 0, total_size);
4499 ioc->alloc_total += total_size;
4500 ioc->alloc = mem;
4501 ioc->alloc_dma = alloc_dma;
4502 ioc->alloc_sz = total_size;
4503 ioc->reply_frames = (MPT_FRAME_HDR *) mem;
4504 ioc->reply_frames_low_dma = (u32) (alloc_dma & 0xFFFFFFFF);
4505
4506 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ReplyBuffers @ %p[%p]\n",
4507 ioc->name, ioc->reply_frames, (void *)(ulong)alloc_dma));
4508
4509 alloc_dma += reply_sz;
4510 mem += reply_sz;
4511
4512 /* Request FIFO - WE manage this! */
4513
4514 ioc->req_frames = (MPT_FRAME_HDR *) mem;
4515 ioc->req_frames_dma = alloc_dma;
4516
4517 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "RequestBuffers @ %p[%p]\n",
4518 ioc->name, mem, (void *)(ulong)alloc_dma));
4519
4520 ioc->req_frames_low_dma = (u32) (alloc_dma & 0xFFFFFFFF);
4521
4522 for (i = 0; i < ioc->req_depth; i++) {
4523 alloc_dma += ioc->req_sz;
4524 mem += ioc->req_sz;
4525 }
4526
4527 ioc->ChainBuffer = mem;
4528 ioc->ChainBufferDMA = alloc_dma;
4529
4530 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ChainBuffers @ %p(%p)\n",
4531 ioc->name, ioc->ChainBuffer, (void *)(ulong)ioc->ChainBufferDMA));
4532
4533 /* Initialize the free chain Q.
4534 */
4535
4536 INIT_LIST_HEAD(&ioc->FreeChainQ);
4537
4538 /* Post the chain buffers to the FreeChainQ.
4539 */
4540 mem = (u8 *)ioc->ChainBuffer;
4541 for (i=0; i < num_chain; i++) {
4542 mf = (MPT_FRAME_HDR *) mem;
4543 list_add_tail(&mf->u.frame.linkage.list, &ioc->FreeChainQ);
4544 mem += ioc->req_sz;
4545 }
4546
4547 /* Initialize Request frames linked list
4548 */
4549 alloc_dma = ioc->req_frames_dma;
4550 mem = (u8 *) ioc->req_frames;
4551
4552 spin_lock_irqsave(&ioc->FreeQlock, flags);
4553 INIT_LIST_HEAD(&ioc->FreeQ);
4554 for (i = 0; i < ioc->req_depth; i++) {
4555 mf = (MPT_FRAME_HDR *) mem;
4556
4557 /* Queue REQUESTs *internally*! */
4558 list_add_tail(&mf->u.frame.linkage.list, &ioc->FreeQ);
4559
4560 mem += ioc->req_sz;
4561 }
4562 spin_unlock_irqrestore(&ioc->FreeQlock, flags);
4563
4564 sz = (ioc->req_depth * MPT_SENSE_BUFFER_ALLOC);
4565 ioc->sense_buf_pool = dma_alloc_coherent(&ioc->pcidev->dev, sz,
4566 &ioc->sense_buf_pool_dma, GFP_KERNEL);
4567 if (ioc->sense_buf_pool == NULL) {
4568 printk(MYIOC_s_ERR_FMT "Unable to allocate Sense Buffers!\n",
4569 ioc->name);
4570 goto out_fail;
4571 }
4572
4573 ioc->sense_buf_low_dma = (u32) (ioc->sense_buf_pool_dma & 0xFFFFFFFF);
4574 ioc->alloc_total += sz;
4575 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "SenseBuffers @ %p[%p]\n",
4576 ioc->name, ioc->sense_buf_pool, (void *)(ulong)ioc->sense_buf_pool_dma));
4577
4578 }
4579
4580 /* Post Reply frames to FIFO
4581 */
4582 alloc_dma = ioc->alloc_dma;
4583 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ReplyBuffers @ %p[%p]\n",
4584 ioc->name, ioc->reply_frames, (void *)(ulong)alloc_dma));
4585
4586 for (i = 0; i < ioc->reply_depth; i++) {
4587 /* Write each address to the IOC! */
4588 CHIPREG_WRITE32(&ioc->chip->ReplyFifo, alloc_dma);
4589 alloc_dma += ioc->reply_sz;
4590 }
4591
4592 if (dma_mask == DMA_BIT_MASK(35) && !dma_set_mask(&ioc->pcidev->dev,
4593 ioc->dma_mask) && !dma_set_coherent_mask(&ioc->pcidev->dev,
4594 ioc->dma_mask))
4595 d36memprintk(ioc, printk(MYIOC_s_DEBUG_FMT
4596 "restoring 64 bit addressing\n", ioc->name));
4597
4598 return 0;
4599
4600out_fail:
4601
4602 if (ioc->alloc != NULL) {
4603 sz = ioc->alloc_sz;
4604 dma_free_coherent(&ioc->pcidev->dev, sz, ioc->alloc,
4605 ioc->alloc_dma);
4606 ioc->reply_frames = NULL;
4607 ioc->req_frames = NULL;
4608 ioc->alloc_total -= sz;
4609 }
4610 if (ioc->sense_buf_pool != NULL) {
4611 sz = (ioc->req_depth * MPT_SENSE_BUFFER_ALLOC);
4612 dma_free_coherent(&ioc->pcidev->dev, sz, ioc->sense_buf_pool,
4613 ioc->sense_buf_pool_dma);
4614 ioc->sense_buf_pool = NULL;
4615 }
4616
4617 if (dma_mask == DMA_BIT_MASK(35) && !dma_set_mask(&ioc->pcidev->dev,
4618 DMA_BIT_MASK(64)) && !dma_set_coherent_mask(&ioc->pcidev->dev,
4619 DMA_BIT_MASK(64)))
4620 d36memprintk(ioc, printk(MYIOC_s_DEBUG_FMT
4621 "restoring 64 bit addressing\n", ioc->name));
4622
4623 return -1;
4624}
4625
4626/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
4627/**
4628 * mpt_handshake_req_reply_wait - Send MPT request to and receive reply
4629 * from IOC via doorbell handshake method.
4630 * @ioc: Pointer to MPT_ADAPTER structure
4631 * @reqBytes: Size of the request in bytes
4632 * @req: Pointer to MPT request frame
4633 * @replyBytes: Expected size of the reply in bytes
4634 * @u16reply: Pointer to area where reply should be written
4635 * @maxwait: Max wait time for a reply (in seconds)
4636 * @sleepFlag: Specifies whether the process can sleep
4637 *
4638 * NOTES: It is the callers responsibility to byte-swap fields in the
4639 * request which are greater than 1 byte in size. It is also the
4640 * callers responsibility to byte-swap response fields which are
4641 * greater than 1 byte in size.
4642 *
4643 * Returns 0 for success, non-zero for failure.
4644 */
4645static int
4646mpt_handshake_req_reply_wait(MPT_ADAPTER *ioc, int reqBytes, u32 *req,
4647 int replyBytes, u16 *u16reply, int maxwait, int sleepFlag)
4648{
4649 MPIDefaultReply_t *mptReply;
4650 int failcnt = 0;
4651 int t;
4652
4653 /*
4654 * Get ready to cache a handshake reply
4655 */
4656 ioc->hs_reply_idx = 0;
4657 mptReply = (MPIDefaultReply_t *) ioc->hs_reply;
4658 mptReply->MsgLength = 0;
4659
4660 /*
4661 * Make sure there are no doorbells (WRITE 0 to IntStatus reg),
4662 * then tell IOC that we want to handshake a request of N words.
4663 * (WRITE u32val to Doorbell reg).
4664 */
4665 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
4666 CHIPREG_WRITE32(&ioc->chip->Doorbell,
4667 ((MPI_FUNCTION_HANDSHAKE<<MPI_DOORBELL_FUNCTION_SHIFT) |
4668 ((reqBytes/4)<<MPI_DOORBELL_ADD_DWORDS_SHIFT)));
4669
4670 /*
4671 * Wait for IOC's doorbell handshake int
4672 */
4673 if ((t = WaitForDoorbellInt(ioc, 5, sleepFlag)) < 0)
4674 failcnt++;
4675
4676 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "HandShake request start reqBytes=%d, WaitCnt=%d%s\n",
4677 ioc->name, reqBytes, t, failcnt ? " - MISSING DOORBELL HANDSHAKE!" : ""));
4678
4679 /* Read doorbell and check for active bit */
4680 if (!(CHIPREG_READ32(&ioc->chip->Doorbell) & MPI_DOORBELL_ACTIVE))
4681 return -1;
4682
4683 /*
4684 * Clear doorbell int (WRITE 0 to IntStatus reg),
4685 * then wait for IOC to ACKnowledge that it's ready for
4686 * our handshake request.
4687 */
4688 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
4689 if (!failcnt && (t = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0)
4690 failcnt++;
4691
4692 if (!failcnt) {
4693 int ii;
4694 u8 *req_as_bytes = (u8 *) req;
4695
4696 /*
4697 * Stuff request words via doorbell handshake,
4698 * with ACK from IOC for each.
4699 */
4700 for (ii = 0; !failcnt && ii < reqBytes/4; ii++) {
4701 u32 word = ((req_as_bytes[(ii*4) + 0] << 0) |
4702 (req_as_bytes[(ii*4) + 1] << 8) |
4703 (req_as_bytes[(ii*4) + 2] << 16) |
4704 (req_as_bytes[(ii*4) + 3] << 24));
4705
4706 CHIPREG_WRITE32(&ioc->chip->Doorbell, word);
4707 if ((t = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0)
4708 failcnt++;
4709 }
4710
4711 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Handshake request frame (@%p) header\n", ioc->name, req));
4712 DBG_DUMP_REQUEST_FRAME_HDR(ioc, (u32 *)req);
4713
4714 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "HandShake request post done, WaitCnt=%d%s\n",
4715 ioc->name, t, failcnt ? " - MISSING DOORBELL ACK!" : ""));
4716
4717 /*
4718 * Wait for completion of doorbell handshake reply from the IOC
4719 */
4720 if (!failcnt && (t = WaitForDoorbellReply(ioc, maxwait, sleepFlag)) < 0)
4721 failcnt++;
4722
4723 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "HandShake reply count=%d%s\n",
4724 ioc->name, t, failcnt ? " - MISSING DOORBELL REPLY!" : ""));
4725
4726 /*
4727 * Copy out the cached reply...
4728 */
4729 for (ii=0; ii < min(replyBytes/2,mptReply->MsgLength*2); ii++)
4730 u16reply[ii] = ioc->hs_reply[ii];
4731 } else {
4732 return -99;
4733 }
4734
4735 return -failcnt;
4736}
4737
4738/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
4739/**
4740 * WaitForDoorbellAck - Wait for IOC doorbell handshake acknowledge
4741 * @ioc: Pointer to MPT_ADAPTER structure
4742 * @howlong: How long to wait (in seconds)
4743 * @sleepFlag: Specifies whether the process can sleep
4744 *
4745 * This routine waits (up to ~2 seconds max) for IOC doorbell
4746 * handshake ACKnowledge, indicated by the IOP_DOORBELL_STATUS
4747 * bit in its IntStatus register being clear.
4748 *
4749 * Returns a negative value on failure, else wait loop count.
4750 */
4751static int
4752WaitForDoorbellAck(MPT_ADAPTER *ioc, int howlong, int sleepFlag)
4753{
4754 int cntdn;
4755 int count = 0;
4756 u32 intstat=0;
4757
4758 cntdn = 1000 * howlong;
4759
4760 if (sleepFlag == CAN_SLEEP) {
4761 while (--cntdn) {
4762 msleep (1);
4763 intstat = CHIPREG_READ32(&ioc->chip->IntStatus);
4764 if (! (intstat & MPI_HIS_IOP_DOORBELL_STATUS))
4765 break;
4766 count++;
4767 }
4768 } else {
4769 while (--cntdn) {
4770 udelay (1000);
4771 intstat = CHIPREG_READ32(&ioc->chip->IntStatus);
4772 if (! (intstat & MPI_HIS_IOP_DOORBELL_STATUS))
4773 break;
4774 count++;
4775 }
4776 }
4777
4778 if (cntdn) {
4779 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "WaitForDoorbell ACK (count=%d)\n",
4780 ioc->name, count));
4781 return count;
4782 }
4783
4784 printk(MYIOC_s_ERR_FMT "Doorbell ACK timeout (count=%d), IntStatus=%x!\n",
4785 ioc->name, count, intstat);
4786 return -1;
4787}
4788
4789/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
4790/**
4791 * WaitForDoorbellInt - Wait for IOC to set its doorbell interrupt bit
4792 * @ioc: Pointer to MPT_ADAPTER structure
4793 * @howlong: How long to wait (in seconds)
4794 * @sleepFlag: Specifies whether the process can sleep
4795 *
4796 * This routine waits (up to ~2 seconds max) for IOC doorbell interrupt
4797 * (MPI_HIS_DOORBELL_INTERRUPT) to be set in the IntStatus register.
4798 *
4799 * Returns a negative value on failure, else wait loop count.
4800 */
4801static int
4802WaitForDoorbellInt(MPT_ADAPTER *ioc, int howlong, int sleepFlag)
4803{
4804 int cntdn;
4805 int count = 0;
4806 u32 intstat=0;
4807
4808 cntdn = 1000 * howlong;
4809 if (sleepFlag == CAN_SLEEP) {
4810 while (--cntdn) {
4811 intstat = CHIPREG_READ32(&ioc->chip->IntStatus);
4812 if (intstat & MPI_HIS_DOORBELL_INTERRUPT)
4813 break;
4814 msleep(1);
4815 count++;
4816 }
4817 } else {
4818 while (--cntdn) {
4819 intstat = CHIPREG_READ32(&ioc->chip->IntStatus);
4820 if (intstat & MPI_HIS_DOORBELL_INTERRUPT)
4821 break;
4822 udelay (1000);
4823 count++;
4824 }
4825 }
4826
4827 if (cntdn) {
4828 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "WaitForDoorbell INT (cnt=%d) howlong=%d\n",
4829 ioc->name, count, howlong));
4830 return count;
4831 }
4832
4833 printk(MYIOC_s_ERR_FMT "Doorbell INT timeout (count=%d), IntStatus=%x!\n",
4834 ioc->name, count, intstat);
4835 return -1;
4836}
4837
4838/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
4839/**
4840 * WaitForDoorbellReply - Wait for and capture an IOC handshake reply.
4841 * @ioc: Pointer to MPT_ADAPTER structure
4842 * @howlong: How long to wait (in seconds)
4843 * @sleepFlag: Specifies whether the process can sleep
4844 *
4845 * This routine polls the IOC for a handshake reply, 16 bits at a time.
4846 * Reply is cached to IOC private area large enough to hold a maximum
4847 * of 128 bytes of reply data.
4848 *
4849 * Returns a negative value on failure, else size of reply in WORDS.
4850 */
4851static int
4852WaitForDoorbellReply(MPT_ADAPTER *ioc, int howlong, int sleepFlag)
4853{
4854 int u16cnt = 0;
4855 int failcnt = 0;
4856 int t;
4857 u16 *hs_reply = ioc->hs_reply;
4858 volatile MPIDefaultReply_t *mptReply = (MPIDefaultReply_t *) ioc->hs_reply;
4859 u16 hword;
4860
4861 hs_reply[0] = hs_reply[1] = hs_reply[7] = 0;
4862
4863 /*
4864 * Get first two u16's so we can look at IOC's intended reply MsgLength
4865 */
4866 u16cnt=0;
4867 if ((t = WaitForDoorbellInt(ioc, howlong, sleepFlag)) < 0) {
4868 failcnt++;
4869 } else {
4870 hs_reply[u16cnt++] = le16_to_cpu(CHIPREG_READ32(&ioc->chip->Doorbell) & 0x0000FFFF);
4871 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
4872 if ((t = WaitForDoorbellInt(ioc, 5, sleepFlag)) < 0)
4873 failcnt++;
4874 else {
4875 hs_reply[u16cnt++] = le16_to_cpu(CHIPREG_READ32(&ioc->chip->Doorbell) & 0x0000FFFF);
4876 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
4877 }
4878 }
4879
4880 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "WaitCnt=%d First handshake reply word=%08x%s\n",
4881 ioc->name, t, le32_to_cpu(*(u32 *)hs_reply),
4882 failcnt ? " - MISSING DOORBELL HANDSHAKE!" : ""));
4883
4884 /*
4885 * If no error (and IOC said MsgLength is > 0), piece together
4886 * reply 16 bits at a time.
4887 */
4888 for (u16cnt=2; !failcnt && u16cnt < (2 * mptReply->MsgLength); u16cnt++) {
4889 if ((t = WaitForDoorbellInt(ioc, 5, sleepFlag)) < 0)
4890 failcnt++;
4891 hword = le16_to_cpu(CHIPREG_READ32(&ioc->chip->Doorbell) & 0x0000FFFF);
4892 /* don't overflow our IOC hs_reply[] buffer! */
4893 if (u16cnt < ARRAY_SIZE(ioc->hs_reply))
4894 hs_reply[u16cnt] = hword;
4895 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
4896 }
4897
4898 if (!failcnt && (t = WaitForDoorbellInt(ioc, 5, sleepFlag)) < 0)
4899 failcnt++;
4900 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
4901
4902 if (failcnt) {
4903 printk(MYIOC_s_ERR_FMT "Handshake reply failure!\n",
4904 ioc->name);
4905 return -failcnt;
4906 }
4907#if 0
4908 else if (u16cnt != (2 * mptReply->MsgLength)) {
4909 return -101;
4910 }
4911 else if ((mptReply->IOCStatus & MPI_IOCSTATUS_MASK) != MPI_IOCSTATUS_SUCCESS) {
4912 return -102;
4913 }
4914#endif
4915
4916 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Got Handshake reply:\n", ioc->name));
4917 DBG_DUMP_REPLY_FRAME(ioc, (u32 *)mptReply);
4918
4919 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "WaitForDoorbell REPLY WaitCnt=%d (sz=%d)\n",
4920 ioc->name, t, u16cnt/2));
4921 return u16cnt/2;
4922}
4923
4924/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
4925/**
4926 * GetLanConfigPages - Fetch LANConfig pages.
4927 * @ioc: Pointer to MPT_ADAPTER structure
4928 *
4929 * Return: 0 for success
4930 * -ENOMEM if no memory available
4931 * -EPERM if not allowed due to ISR context
4932 * -EAGAIN if no msg frames currently available
4933 * -EFAULT for non-successful reply or no reply (timeout)
4934 */
4935static int
4936GetLanConfigPages(MPT_ADAPTER *ioc)
4937{
4938 ConfigPageHeader_t hdr;
4939 CONFIGPARMS cfg;
4940 LANPage0_t *ppage0_alloc;
4941 dma_addr_t page0_dma;
4942 LANPage1_t *ppage1_alloc;
4943 dma_addr_t page1_dma;
4944 int rc = 0;
4945 int data_sz;
4946 int copy_sz;
4947
4948 /* Get LAN Page 0 header */
4949 hdr.PageVersion = 0;
4950 hdr.PageLength = 0;
4951 hdr.PageNumber = 0;
4952 hdr.PageType = MPI_CONFIG_PAGETYPE_LAN;
4953 cfg.cfghdr.hdr = &hdr;
4954 cfg.physAddr = -1;
4955 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
4956 cfg.dir = 0;
4957 cfg.pageAddr = 0;
4958 cfg.timeout = 0;
4959
4960 if ((rc = mpt_config(ioc, &cfg)) != 0)
4961 return rc;
4962
4963 if (hdr.PageLength > 0) {
4964 data_sz = hdr.PageLength * 4;
4965 ppage0_alloc = dma_alloc_coherent(&ioc->pcidev->dev, data_sz,
4966 &page0_dma, GFP_KERNEL);
4967 rc = -ENOMEM;
4968 if (ppage0_alloc) {
4969 memset((u8 *)ppage0_alloc, 0, data_sz);
4970 cfg.physAddr = page0_dma;
4971 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
4972
4973 if ((rc = mpt_config(ioc, &cfg)) == 0) {
4974 /* save the data */
4975 copy_sz = min_t(int, sizeof(LANPage0_t), data_sz);
4976 memcpy(&ioc->lan_cnfg_page0, ppage0_alloc, copy_sz);
4977
4978 }
4979
4980 dma_free_coherent(&ioc->pcidev->dev, data_sz,
4981 (u8 *)ppage0_alloc, page0_dma);
4982
4983 /* FIXME!
4984 * Normalize endianness of structure data,
4985 * by byte-swapping all > 1 byte fields!
4986 */
4987
4988 }
4989
4990 if (rc)
4991 return rc;
4992 }
4993
4994 /* Get LAN Page 1 header */
4995 hdr.PageVersion = 0;
4996 hdr.PageLength = 0;
4997 hdr.PageNumber = 1;
4998 hdr.PageType = MPI_CONFIG_PAGETYPE_LAN;
4999 cfg.cfghdr.hdr = &hdr;
5000 cfg.physAddr = -1;
5001 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
5002 cfg.dir = 0;
5003 cfg.pageAddr = 0;
5004
5005 if ((rc = mpt_config(ioc, &cfg)) != 0)
5006 return rc;
5007
5008 if (hdr.PageLength == 0)
5009 return 0;
5010
5011 data_sz = hdr.PageLength * 4;
5012 rc = -ENOMEM;
5013 ppage1_alloc = dma_alloc_coherent(&ioc->pcidev->dev, data_sz,
5014 &page1_dma, GFP_KERNEL);
5015 if (ppage1_alloc) {
5016 memset((u8 *)ppage1_alloc, 0, data_sz);
5017 cfg.physAddr = page1_dma;
5018 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
5019
5020 if ((rc = mpt_config(ioc, &cfg)) == 0) {
5021 /* save the data */
5022 copy_sz = min_t(int, sizeof(LANPage1_t), data_sz);
5023 memcpy(&ioc->lan_cnfg_page1, ppage1_alloc, copy_sz);
5024 }
5025
5026 dma_free_coherent(&ioc->pcidev->dev, data_sz,
5027 (u8 *)ppage1_alloc, page1_dma);
5028
5029 /* FIXME!
5030 * Normalize endianness of structure data,
5031 * by byte-swapping all > 1 byte fields!
5032 */
5033
5034 }
5035
5036 return rc;
5037}
5038
5039/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
5040/**
5041 * mptbase_sas_persist_operation - Perform operation on SAS Persistent Table
5042 * @ioc: Pointer to MPT_ADAPTER structure
5043 * @persist_opcode: see below
5044 *
5045 * =============================== ======================================
5046 * MPI_SAS_OP_CLEAR_NOT_PRESENT Free all persist TargetID mappings for
5047 * devices not currently present.
5048 * MPI_SAS_OP_CLEAR_ALL_PERSISTENT Clear al persist TargetID mappings
5049 * =============================== ======================================
5050 *
5051 * NOTE: Don't use not this function during interrupt time.
5052 *
5053 * Returns 0 for success, non-zero error
5054 */
5055
5056/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
5057int
5058mptbase_sas_persist_operation(MPT_ADAPTER *ioc, u8 persist_opcode)
5059{
5060 SasIoUnitControlRequest_t *sasIoUnitCntrReq;
5061 SasIoUnitControlReply_t *sasIoUnitCntrReply;
5062 MPT_FRAME_HDR *mf = NULL;
5063 MPIHeader_t *mpi_hdr;
5064 int ret = 0;
5065 unsigned long timeleft;
5066
5067 mutex_lock(&ioc->mptbase_cmds.mutex);
5068
5069 /* init the internal cmd struct */
5070 memset(ioc->mptbase_cmds.reply, 0 , MPT_DEFAULT_FRAME_SIZE);
5071 INITIALIZE_MGMT_STATUS(ioc->mptbase_cmds.status)
5072
5073 /* insure garbage is not sent to fw */
5074 switch(persist_opcode) {
5075
5076 case MPI_SAS_OP_CLEAR_NOT_PRESENT:
5077 case MPI_SAS_OP_CLEAR_ALL_PERSISTENT:
5078 break;
5079
5080 default:
5081 ret = -1;
5082 goto out;
5083 }
5084
5085 printk(KERN_DEBUG "%s: persist_opcode=%x\n",
5086 __func__, persist_opcode);
5087
5088 /* Get a MF for this command.
5089 */
5090 if ((mf = mpt_get_msg_frame(mpt_base_index, ioc)) == NULL) {
5091 printk(KERN_DEBUG "%s: no msg frames!\n", __func__);
5092 ret = -1;
5093 goto out;
5094 }
5095
5096 mpi_hdr = (MPIHeader_t *) mf;
5097 sasIoUnitCntrReq = (SasIoUnitControlRequest_t *)mf;
5098 memset(sasIoUnitCntrReq,0,sizeof(SasIoUnitControlRequest_t));
5099 sasIoUnitCntrReq->Function = MPI_FUNCTION_SAS_IO_UNIT_CONTROL;
5100 sasIoUnitCntrReq->MsgContext = mpi_hdr->MsgContext;
5101 sasIoUnitCntrReq->Operation = persist_opcode;
5102
5103 mpt_put_msg_frame(mpt_base_index, ioc, mf);
5104 timeleft = wait_for_completion_timeout(&ioc->mptbase_cmds.done, 10*HZ);
5105 if (!(ioc->mptbase_cmds.status & MPT_MGMT_STATUS_COMMAND_GOOD)) {
5106 ret = -ETIME;
5107 printk(KERN_DEBUG "%s: failed\n", __func__);
5108 if (ioc->mptbase_cmds.status & MPT_MGMT_STATUS_DID_IOCRESET)
5109 goto out;
5110 if (!timeleft) {
5111 printk(MYIOC_s_WARN_FMT
5112 "Issuing Reset from %s!!, doorbell=0x%08x\n",
5113 ioc->name, __func__, mpt_GetIocState(ioc, 0));
5114 mpt_Soft_Hard_ResetHandler(ioc, CAN_SLEEP);
5115 mpt_free_msg_frame(ioc, mf);
5116 }
5117 goto out;
5118 }
5119
5120 if (!(ioc->mptbase_cmds.status & MPT_MGMT_STATUS_RF_VALID)) {
5121 ret = -1;
5122 goto out;
5123 }
5124
5125 sasIoUnitCntrReply =
5126 (SasIoUnitControlReply_t *)ioc->mptbase_cmds.reply;
5127 if (le16_to_cpu(sasIoUnitCntrReply->IOCStatus) != MPI_IOCSTATUS_SUCCESS) {
5128 printk(KERN_DEBUG "%s: IOCStatus=0x%X IOCLogInfo=0x%X\n",
5129 __func__, sasIoUnitCntrReply->IOCStatus,
5130 sasIoUnitCntrReply->IOCLogInfo);
5131 printk(KERN_DEBUG "%s: failed\n", __func__);
5132 ret = -1;
5133 } else
5134 printk(KERN_DEBUG "%s: success\n", __func__);
5135 out:
5136
5137 CLEAR_MGMT_STATUS(ioc->mptbase_cmds.status)
5138 mutex_unlock(&ioc->mptbase_cmds.mutex);
5139 return ret;
5140}
5141
5142/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
5143
5144static void
5145mptbase_raid_process_event_data(MPT_ADAPTER *ioc,
5146 MpiEventDataRaid_t * pRaidEventData)
5147{
5148 int volume;
5149 int reason;
5150 int disk;
5151 int status;
5152 int flags;
5153 int state;
5154
5155 volume = pRaidEventData->VolumeID;
5156 reason = pRaidEventData->ReasonCode;
5157 disk = pRaidEventData->PhysDiskNum;
5158 status = le32_to_cpu(pRaidEventData->SettingsStatus);
5159 flags = (status >> 0) & 0xff;
5160 state = (status >> 8) & 0xff;
5161
5162 if (reason == MPI_EVENT_RAID_RC_DOMAIN_VAL_NEEDED) {
5163 return;
5164 }
5165
5166 if ((reason >= MPI_EVENT_RAID_RC_PHYSDISK_CREATED &&
5167 reason <= MPI_EVENT_RAID_RC_PHYSDISK_STATUS_CHANGED) ||
5168 (reason == MPI_EVENT_RAID_RC_SMART_DATA)) {
5169 printk(MYIOC_s_INFO_FMT "RAID STATUS CHANGE for PhysDisk %d id=%d\n",
5170 ioc->name, disk, volume);
5171 } else {
5172 printk(MYIOC_s_INFO_FMT "RAID STATUS CHANGE for VolumeID %d\n",
5173 ioc->name, volume);
5174 }
5175
5176 switch(reason) {
5177 case MPI_EVENT_RAID_RC_VOLUME_CREATED:
5178 printk(MYIOC_s_INFO_FMT " volume has been created\n",
5179 ioc->name);
5180 break;
5181
5182 case MPI_EVENT_RAID_RC_VOLUME_DELETED:
5183
5184 printk(MYIOC_s_INFO_FMT " volume has been deleted\n",
5185 ioc->name);
5186 break;
5187
5188 case MPI_EVENT_RAID_RC_VOLUME_SETTINGS_CHANGED:
5189 printk(MYIOC_s_INFO_FMT " volume settings have been changed\n",
5190 ioc->name);
5191 break;
5192
5193 case MPI_EVENT_RAID_RC_VOLUME_STATUS_CHANGED:
5194 printk(MYIOC_s_INFO_FMT " volume is now %s%s%s%s\n",
5195 ioc->name,
5196 state == MPI_RAIDVOL0_STATUS_STATE_OPTIMAL
5197 ? "optimal"
5198 : state == MPI_RAIDVOL0_STATUS_STATE_DEGRADED
5199 ? "degraded"
5200 : state == MPI_RAIDVOL0_STATUS_STATE_FAILED
5201 ? "failed"
5202 : "state unknown",
5203 flags & MPI_RAIDVOL0_STATUS_FLAG_ENABLED
5204 ? ", enabled" : "",
5205 flags & MPI_RAIDVOL0_STATUS_FLAG_QUIESCED
5206 ? ", quiesced" : "",
5207 flags & MPI_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS
5208 ? ", resync in progress" : "" );
5209 break;
5210
5211 case MPI_EVENT_RAID_RC_VOLUME_PHYSDISK_CHANGED:
5212 printk(MYIOC_s_INFO_FMT " volume membership of PhysDisk %d has changed\n",
5213 ioc->name, disk);
5214 break;
5215
5216 case MPI_EVENT_RAID_RC_PHYSDISK_CREATED:
5217 printk(MYIOC_s_INFO_FMT " PhysDisk has been created\n",
5218 ioc->name);
5219 break;
5220
5221 case MPI_EVENT_RAID_RC_PHYSDISK_DELETED:
5222 printk(MYIOC_s_INFO_FMT " PhysDisk has been deleted\n",
5223 ioc->name);
5224 break;
5225
5226 case MPI_EVENT_RAID_RC_PHYSDISK_SETTINGS_CHANGED:
5227 printk(MYIOC_s_INFO_FMT " PhysDisk settings have been changed\n",
5228 ioc->name);
5229 break;
5230
5231 case MPI_EVENT_RAID_RC_PHYSDISK_STATUS_CHANGED:
5232 printk(MYIOC_s_INFO_FMT " PhysDisk is now %s%s%s\n",
5233 ioc->name,
5234 state == MPI_PHYSDISK0_STATUS_ONLINE
5235 ? "online"
5236 : state == MPI_PHYSDISK0_STATUS_MISSING
5237 ? "missing"
5238 : state == MPI_PHYSDISK0_STATUS_NOT_COMPATIBLE
5239 ? "not compatible"
5240 : state == MPI_PHYSDISK0_STATUS_FAILED
5241 ? "failed"
5242 : state == MPI_PHYSDISK0_STATUS_INITIALIZING
5243 ? "initializing"
5244 : state == MPI_PHYSDISK0_STATUS_OFFLINE_REQUESTED
5245 ? "offline requested"
5246 : state == MPI_PHYSDISK0_STATUS_FAILED_REQUESTED
5247 ? "failed requested"
5248 : state == MPI_PHYSDISK0_STATUS_OTHER_OFFLINE
5249 ? "offline"
5250 : "state unknown",
5251 flags & MPI_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC
5252 ? ", out of sync" : "",
5253 flags & MPI_PHYSDISK0_STATUS_FLAG_QUIESCED
5254 ? ", quiesced" : "" );
5255 break;
5256
5257 case MPI_EVENT_RAID_RC_DOMAIN_VAL_NEEDED:
5258 printk(MYIOC_s_INFO_FMT " Domain Validation needed for PhysDisk %d\n",
5259 ioc->name, disk);
5260 break;
5261
5262 case MPI_EVENT_RAID_RC_SMART_DATA:
5263 printk(MYIOC_s_INFO_FMT " SMART data received, ASC/ASCQ = %02xh/%02xh\n",
5264 ioc->name, pRaidEventData->ASC, pRaidEventData->ASCQ);
5265 break;
5266
5267 case MPI_EVENT_RAID_RC_REPLACE_ACTION_STARTED:
5268 printk(MYIOC_s_INFO_FMT " replacement of PhysDisk %d has started\n",
5269 ioc->name, disk);
5270 break;
5271 }
5272}
5273
5274/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
5275/**
5276 * GetIoUnitPage2 - Retrieve BIOS version and boot order information.
5277 * @ioc: Pointer to MPT_ADAPTER structure
5278 *
5279 * Returns: 0 for success
5280 * -ENOMEM if no memory available
5281 * -EPERM if not allowed due to ISR context
5282 * -EAGAIN if no msg frames currently available
5283 * -EFAULT for non-successful reply or no reply (timeout)
5284 */
5285static int
5286GetIoUnitPage2(MPT_ADAPTER *ioc)
5287{
5288 ConfigPageHeader_t hdr;
5289 CONFIGPARMS cfg;
5290 IOUnitPage2_t *ppage_alloc;
5291 dma_addr_t page_dma;
5292 int data_sz;
5293 int rc;
5294
5295 /* Get the page header */
5296 hdr.PageVersion = 0;
5297 hdr.PageLength = 0;
5298 hdr.PageNumber = 2;
5299 hdr.PageType = MPI_CONFIG_PAGETYPE_IO_UNIT;
5300 cfg.cfghdr.hdr = &hdr;
5301 cfg.physAddr = -1;
5302 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
5303 cfg.dir = 0;
5304 cfg.pageAddr = 0;
5305 cfg.timeout = 0;
5306
5307 if ((rc = mpt_config(ioc, &cfg)) != 0)
5308 return rc;
5309
5310 if (hdr.PageLength == 0)
5311 return 0;
5312
5313 /* Read the config page */
5314 data_sz = hdr.PageLength * 4;
5315 rc = -ENOMEM;
5316 ppage_alloc = dma_alloc_coherent(&ioc->pcidev->dev, data_sz,
5317 &page_dma, GFP_KERNEL);
5318 if (ppage_alloc) {
5319 memset((u8 *)ppage_alloc, 0, data_sz);
5320 cfg.physAddr = page_dma;
5321 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
5322
5323 /* If Good, save data */
5324 if ((rc = mpt_config(ioc, &cfg)) == 0)
5325 ioc->biosVersion = le32_to_cpu(ppage_alloc->BiosVersion);
5326
5327 dma_free_coherent(&ioc->pcidev->dev, data_sz,
5328 (u8 *)ppage_alloc, page_dma);
5329 }
5330
5331 return rc;
5332}
5333
5334/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
5335/**
5336 * mpt_GetScsiPortSettings - read SCSI Port Page 0 and 2
5337 * @ioc: Pointer to a Adapter Strucutre
5338 * @portnum: IOC port number
5339 *
5340 * Return: -EFAULT if read of config page header fails
5341 * or if no nvram
5342 * If read of SCSI Port Page 0 fails,
5343 * NVRAM = MPT_HOST_NVRAM_INVALID (0xFFFFFFFF)
5344 * Adapter settings: async, narrow
5345 * Return 1
5346 * If read of SCSI Port Page 2 fails,
5347 * Adapter settings valid
5348 * NVRAM = MPT_HOST_NVRAM_INVALID (0xFFFFFFFF)
5349 * Return 1
5350 * Else
5351 * Both valid
5352 * Return 0
5353 * CHECK - what type of locking mechanisms should be used????
5354 */
5355static int
5356mpt_GetScsiPortSettings(MPT_ADAPTER *ioc, int portnum)
5357{
5358 u8 *pbuf;
5359 dma_addr_t buf_dma;
5360 CONFIGPARMS cfg;
5361 ConfigPageHeader_t header;
5362 int ii;
5363 int data, rc = 0;
5364
5365 /* Allocate memory
5366 */
5367 if (!ioc->spi_data.nvram) {
5368 int sz;
5369 u8 *mem;
5370 sz = MPT_MAX_SCSI_DEVICES * sizeof(int);
5371 mem = kmalloc(sz, GFP_ATOMIC);
5372 if (mem == NULL)
5373 return -EFAULT;
5374
5375 ioc->spi_data.nvram = (int *) mem;
5376
5377 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "SCSI device NVRAM settings @ %p, sz=%d\n",
5378 ioc->name, ioc->spi_data.nvram, sz));
5379 }
5380
5381 /* Invalidate NVRAM information
5382 */
5383 for (ii=0; ii < MPT_MAX_SCSI_DEVICES; ii++) {
5384 ioc->spi_data.nvram[ii] = MPT_HOST_NVRAM_INVALID;
5385 }
5386
5387 /* Read SPP0 header, allocate memory, then read page.
5388 */
5389 header.PageVersion = 0;
5390 header.PageLength = 0;
5391 header.PageNumber = 0;
5392 header.PageType = MPI_CONFIG_PAGETYPE_SCSI_PORT;
5393 cfg.cfghdr.hdr = &header;
5394 cfg.physAddr = -1;
5395 cfg.pageAddr = portnum;
5396 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
5397 cfg.dir = 0;
5398 cfg.timeout = 0; /* use default */
5399 if (mpt_config(ioc, &cfg) != 0)
5400 return -EFAULT;
5401
5402 if (header.PageLength > 0) {
5403 pbuf = dma_alloc_coherent(&ioc->pcidev->dev,
5404 header.PageLength * 4, &buf_dma,
5405 GFP_KERNEL);
5406 if (pbuf) {
5407 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
5408 cfg.physAddr = buf_dma;
5409 if (mpt_config(ioc, &cfg) != 0) {
5410 ioc->spi_data.maxBusWidth = MPT_NARROW;
5411 ioc->spi_data.maxSyncOffset = 0;
5412 ioc->spi_data.minSyncFactor = MPT_ASYNC;
5413 ioc->spi_data.busType = MPT_HOST_BUS_UNKNOWN;
5414 rc = 1;
5415 ddvprintk(ioc, printk(MYIOC_s_DEBUG_FMT
5416 "Unable to read PortPage0 minSyncFactor=%x\n",
5417 ioc->name, ioc->spi_data.minSyncFactor));
5418 } else {
5419 /* Save the Port Page 0 data
5420 */
5421 SCSIPortPage0_t *pPP0 = (SCSIPortPage0_t *) pbuf;
5422 pPP0->Capabilities = le32_to_cpu(pPP0->Capabilities);
5423 pPP0->PhysicalInterface = le32_to_cpu(pPP0->PhysicalInterface);
5424
5425 if ( (pPP0->Capabilities & MPI_SCSIPORTPAGE0_CAP_QAS) == 0 ) {
5426 ioc->spi_data.noQas |= MPT_TARGET_NO_NEGO_QAS;
5427 ddvprintk(ioc, printk(MYIOC_s_DEBUG_FMT
5428 "noQas due to Capabilities=%x\n",
5429 ioc->name, pPP0->Capabilities));
5430 }
5431 ioc->spi_data.maxBusWidth = pPP0->Capabilities & MPI_SCSIPORTPAGE0_CAP_WIDE ? 1 : 0;
5432 data = pPP0->Capabilities & MPI_SCSIPORTPAGE0_CAP_MAX_SYNC_OFFSET_MASK;
5433 if (data) {
5434 ioc->spi_data.maxSyncOffset = (u8) (data >> 16);
5435 data = pPP0->Capabilities & MPI_SCSIPORTPAGE0_CAP_MIN_SYNC_PERIOD_MASK;
5436 ioc->spi_data.minSyncFactor = (u8) (data >> 8);
5437 ddvprintk(ioc, printk(MYIOC_s_DEBUG_FMT
5438 "PortPage0 minSyncFactor=%x\n",
5439 ioc->name, ioc->spi_data.minSyncFactor));
5440 } else {
5441 ioc->spi_data.maxSyncOffset = 0;
5442 ioc->spi_data.minSyncFactor = MPT_ASYNC;
5443 }
5444
5445 ioc->spi_data.busType = pPP0->PhysicalInterface & MPI_SCSIPORTPAGE0_PHY_SIGNAL_TYPE_MASK;
5446
5447 /* Update the minSyncFactor based on bus type.
5448 */
5449 if ((ioc->spi_data.busType == MPI_SCSIPORTPAGE0_PHY_SIGNAL_HVD) ||
5450 (ioc->spi_data.busType == MPI_SCSIPORTPAGE0_PHY_SIGNAL_SE)) {
5451
5452 if (ioc->spi_data.minSyncFactor < MPT_ULTRA) {
5453 ioc->spi_data.minSyncFactor = MPT_ULTRA;
5454 ddvprintk(ioc, printk(MYIOC_s_DEBUG_FMT
5455 "HVD or SE detected, minSyncFactor=%x\n",
5456 ioc->name, ioc->spi_data.minSyncFactor));
5457 }
5458 }
5459 }
5460 if (pbuf) {
5461 dma_free_coherent(&ioc->pcidev->dev,
5462 header.PageLength * 4, pbuf,
5463 buf_dma);
5464 }
5465 }
5466 }
5467
5468 /* SCSI Port Page 2 - Read the header then the page.
5469 */
5470 header.PageVersion = 0;
5471 header.PageLength = 0;
5472 header.PageNumber = 2;
5473 header.PageType = MPI_CONFIG_PAGETYPE_SCSI_PORT;
5474 cfg.cfghdr.hdr = &header;
5475 cfg.physAddr = -1;
5476 cfg.pageAddr = portnum;
5477 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
5478 cfg.dir = 0;
5479 if (mpt_config(ioc, &cfg) != 0)
5480 return -EFAULT;
5481
5482 if (header.PageLength > 0) {
5483 /* Allocate memory and read SCSI Port Page 2
5484 */
5485 pbuf = dma_alloc_coherent(&ioc->pcidev->dev,
5486 header.PageLength * 4, &buf_dma,
5487 GFP_KERNEL);
5488 if (pbuf) {
5489 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_NVRAM;
5490 cfg.physAddr = buf_dma;
5491 if (mpt_config(ioc, &cfg) != 0) {
5492 /* Nvram data is left with INVALID mark
5493 */
5494 rc = 1;
5495 } else if (ioc->pcidev->vendor == PCI_VENDOR_ID_ATTO) {
5496
5497 /* This is an ATTO adapter, read Page2 accordingly
5498 */
5499 ATTO_SCSIPortPage2_t *pPP2 = (ATTO_SCSIPortPage2_t *) pbuf;
5500 ATTODeviceInfo_t *pdevice = NULL;
5501 u16 ATTOFlags;
5502
5503 /* Save the Port Page 2 data
5504 * (reformat into a 32bit quantity)
5505 */
5506 for (ii=0; ii < MPT_MAX_SCSI_DEVICES; ii++) {
5507 pdevice = &pPP2->DeviceSettings[ii];
5508 ATTOFlags = le16_to_cpu(pdevice->ATTOFlags);
5509 data = 0;
5510
5511 /* Translate ATTO device flags to LSI format
5512 */
5513 if (ATTOFlags & ATTOFLAG_DISC)
5514 data |= (MPI_SCSIPORTPAGE2_DEVICE_DISCONNECT_ENABLE);
5515 if (ATTOFlags & ATTOFLAG_ID_ENB)
5516 data |= (MPI_SCSIPORTPAGE2_DEVICE_ID_SCAN_ENABLE);
5517 if (ATTOFlags & ATTOFLAG_LUN_ENB)
5518 data |= (MPI_SCSIPORTPAGE2_DEVICE_LUN_SCAN_ENABLE);
5519 if (ATTOFlags & ATTOFLAG_TAGGED)
5520 data |= (MPI_SCSIPORTPAGE2_DEVICE_TAG_QUEUE_ENABLE);
5521 if (!(ATTOFlags & ATTOFLAG_WIDE_ENB))
5522 data |= (MPI_SCSIPORTPAGE2_DEVICE_WIDE_DISABLE);
5523
5524 data = (data << 16) | (pdevice->Period << 8) | 10;
5525 ioc->spi_data.nvram[ii] = data;
5526 }
5527 } else {
5528 SCSIPortPage2_t *pPP2 = (SCSIPortPage2_t *) pbuf;
5529 MpiDeviceInfo_t *pdevice = NULL;
5530
5531 /*
5532 * Save "Set to Avoid SCSI Bus Resets" flag
5533 */
5534 ioc->spi_data.bus_reset =
5535 (le32_to_cpu(pPP2->PortFlags) &
5536 MPI_SCSIPORTPAGE2_PORT_FLAGS_AVOID_SCSI_RESET) ?
5537 0 : 1 ;
5538
5539 /* Save the Port Page 2 data
5540 * (reformat into a 32bit quantity)
5541 */
5542 data = le32_to_cpu(pPP2->PortFlags) & MPI_SCSIPORTPAGE2_PORT_FLAGS_DV_MASK;
5543 ioc->spi_data.PortFlags = data;
5544 for (ii=0; ii < MPT_MAX_SCSI_DEVICES; ii++) {
5545 pdevice = &pPP2->DeviceSettings[ii];
5546 data = (le16_to_cpu(pdevice->DeviceFlags) << 16) |
5547 (pdevice->SyncFactor << 8) | pdevice->Timeout;
5548 ioc->spi_data.nvram[ii] = data;
5549 }
5550 }
5551
5552 dma_free_coherent(&ioc->pcidev->dev,
5553 header.PageLength * 4, pbuf,
5554 buf_dma);
5555 }
5556 }
5557
5558 /* Update Adapter limits with those from NVRAM
5559 * Comment: Don't need to do this. Target performance
5560 * parameters will never exceed the adapters limits.
5561 */
5562
5563 return rc;
5564}
5565
5566/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
5567/**
5568 * mpt_readScsiDevicePageHeaders - save version and length of SDP1
5569 * @ioc: Pointer to a Adapter Strucutre
5570 * @portnum: IOC port number
5571 *
5572 * Return: -EFAULT if read of config page header fails
5573 * or 0 if success.
5574 */
5575static int
5576mpt_readScsiDevicePageHeaders(MPT_ADAPTER *ioc, int portnum)
5577{
5578 CONFIGPARMS cfg;
5579 ConfigPageHeader_t header;
5580
5581 /* Read the SCSI Device Page 1 header
5582 */
5583 header.PageVersion = 0;
5584 header.PageLength = 0;
5585 header.PageNumber = 1;
5586 header.PageType = MPI_CONFIG_PAGETYPE_SCSI_DEVICE;
5587 cfg.cfghdr.hdr = &header;
5588 cfg.physAddr = -1;
5589 cfg.pageAddr = portnum;
5590 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
5591 cfg.dir = 0;
5592 cfg.timeout = 0;
5593 if (mpt_config(ioc, &cfg) != 0)
5594 return -EFAULT;
5595
5596 ioc->spi_data.sdp1version = cfg.cfghdr.hdr->PageVersion;
5597 ioc->spi_data.sdp1length = cfg.cfghdr.hdr->PageLength;
5598
5599 header.PageVersion = 0;
5600 header.PageLength = 0;
5601 header.PageNumber = 0;
5602 header.PageType = MPI_CONFIG_PAGETYPE_SCSI_DEVICE;
5603 if (mpt_config(ioc, &cfg) != 0)
5604 return -EFAULT;
5605
5606 ioc->spi_data.sdp0version = cfg.cfghdr.hdr->PageVersion;
5607 ioc->spi_data.sdp0length = cfg.cfghdr.hdr->PageLength;
5608
5609 dcprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Headers: 0: version %d length %d\n",
5610 ioc->name, ioc->spi_data.sdp0version, ioc->spi_data.sdp0length));
5611
5612 dcprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Headers: 1: version %d length %d\n",
5613 ioc->name, ioc->spi_data.sdp1version, ioc->spi_data.sdp1length));
5614 return 0;
5615}
5616
5617/**
5618 * mpt_inactive_raid_list_free - This clears this link list.
5619 * @ioc : pointer to per adapter structure
5620 **/
5621static void
5622mpt_inactive_raid_list_free(MPT_ADAPTER *ioc)
5623{
5624 struct inactive_raid_component_info *component_info, *pNext;
5625
5626 if (list_empty(&ioc->raid_data.inactive_list))
5627 return;
5628
5629 mutex_lock(&ioc->raid_data.inactive_list_mutex);
5630 list_for_each_entry_safe(component_info, pNext,
5631 &ioc->raid_data.inactive_list, list) {
5632 list_del(&component_info->list);
5633 kfree(component_info);
5634 }
5635 mutex_unlock(&ioc->raid_data.inactive_list_mutex);
5636}
5637
5638/**
5639 * mpt_inactive_raid_volumes - sets up link list of phy_disk_nums for devices belonging in an inactive volume
5640 *
5641 * @ioc : pointer to per adapter structure
5642 * @channel : volume channel
5643 * @id : volume target id
5644 **/
5645static void
5646mpt_inactive_raid_volumes(MPT_ADAPTER *ioc, u8 channel, u8 id)
5647{
5648 CONFIGPARMS cfg;
5649 ConfigPageHeader_t hdr;
5650 dma_addr_t dma_handle;
5651 pRaidVolumePage0_t buffer = NULL;
5652 int i;
5653 RaidPhysDiskPage0_t phys_disk;
5654 struct inactive_raid_component_info *component_info;
5655 int handle_inactive_volumes;
5656
5657 memset(&cfg, 0 , sizeof(CONFIGPARMS));
5658 memset(&hdr, 0 , sizeof(ConfigPageHeader_t));
5659 hdr.PageType = MPI_CONFIG_PAGETYPE_RAID_VOLUME;
5660 cfg.pageAddr = (channel << 8) + id;
5661 cfg.cfghdr.hdr = &hdr;
5662 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
5663
5664 if (mpt_config(ioc, &cfg) != 0)
5665 goto out;
5666
5667 if (!hdr.PageLength)
5668 goto out;
5669
5670 buffer = dma_alloc_coherent(&ioc->pcidev->dev, hdr.PageLength * 4,
5671 &dma_handle, GFP_KERNEL);
5672
5673 if (!buffer)
5674 goto out;
5675
5676 cfg.physAddr = dma_handle;
5677 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
5678
5679 if (mpt_config(ioc, &cfg) != 0)
5680 goto out;
5681
5682 if (!buffer->NumPhysDisks)
5683 goto out;
5684
5685 handle_inactive_volumes =
5686 (buffer->VolumeStatus.Flags & MPI_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE ||
5687 (buffer->VolumeStatus.Flags & MPI_RAIDVOL0_STATUS_FLAG_ENABLED) == 0 ||
5688 buffer->VolumeStatus.State == MPI_RAIDVOL0_STATUS_STATE_FAILED ||
5689 buffer->VolumeStatus.State == MPI_RAIDVOL0_STATUS_STATE_MISSING) ? 1 : 0;
5690
5691 if (!handle_inactive_volumes)
5692 goto out;
5693
5694 mutex_lock(&ioc->raid_data.inactive_list_mutex);
5695 for (i = 0; i < buffer->NumPhysDisks; i++) {
5696 if(mpt_raid_phys_disk_pg0(ioc,
5697 buffer->PhysDisk[i].PhysDiskNum, &phys_disk) != 0)
5698 continue;
5699
5700 if ((component_info = kmalloc(sizeof (*component_info),
5701 GFP_KERNEL)) == NULL)
5702 continue;
5703
5704 component_info->volumeID = id;
5705 component_info->volumeBus = channel;
5706 component_info->d.PhysDiskNum = phys_disk.PhysDiskNum;
5707 component_info->d.PhysDiskBus = phys_disk.PhysDiskBus;
5708 component_info->d.PhysDiskID = phys_disk.PhysDiskID;
5709 component_info->d.PhysDiskIOC = phys_disk.PhysDiskIOC;
5710
5711 list_add_tail(&component_info->list,
5712 &ioc->raid_data.inactive_list);
5713 }
5714 mutex_unlock(&ioc->raid_data.inactive_list_mutex);
5715
5716 out:
5717 if (buffer)
5718 dma_free_coherent(&ioc->pcidev->dev, hdr.PageLength * 4,
5719 buffer, dma_handle);
5720}
5721
5722/**
5723 * mpt_raid_phys_disk_pg0 - returns phys disk page zero
5724 * @ioc: Pointer to a Adapter Structure
5725 * @phys_disk_num: io unit unique phys disk num generated by the ioc
5726 * @phys_disk: requested payload data returned
5727 *
5728 * Return:
5729 * 0 on success
5730 * -EFAULT if read of config page header fails or data pointer not NULL
5731 * -ENOMEM if pci_alloc failed
5732 **/
5733int
5734mpt_raid_phys_disk_pg0(MPT_ADAPTER *ioc, u8 phys_disk_num,
5735 RaidPhysDiskPage0_t *phys_disk)
5736{
5737 CONFIGPARMS cfg;
5738 ConfigPageHeader_t hdr;
5739 dma_addr_t dma_handle;
5740 pRaidPhysDiskPage0_t buffer = NULL;
5741 int rc;
5742
5743 memset(&cfg, 0 , sizeof(CONFIGPARMS));
5744 memset(&hdr, 0 , sizeof(ConfigPageHeader_t));
5745 memset(phys_disk, 0, sizeof(RaidPhysDiskPage0_t));
5746
5747 hdr.PageVersion = MPI_RAIDPHYSDISKPAGE0_PAGEVERSION;
5748 hdr.PageType = MPI_CONFIG_PAGETYPE_RAID_PHYSDISK;
5749 cfg.cfghdr.hdr = &hdr;
5750 cfg.physAddr = -1;
5751 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
5752
5753 if (mpt_config(ioc, &cfg) != 0) {
5754 rc = -EFAULT;
5755 goto out;
5756 }
5757
5758 if (!hdr.PageLength) {
5759 rc = -EFAULT;
5760 goto out;
5761 }
5762
5763 buffer = dma_alloc_coherent(&ioc->pcidev->dev, hdr.PageLength * 4,
5764 &dma_handle, GFP_KERNEL);
5765
5766 if (!buffer) {
5767 rc = -ENOMEM;
5768 goto out;
5769 }
5770
5771 cfg.physAddr = dma_handle;
5772 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
5773 cfg.pageAddr = phys_disk_num;
5774
5775 if (mpt_config(ioc, &cfg) != 0) {
5776 rc = -EFAULT;
5777 goto out;
5778 }
5779
5780 rc = 0;
5781 memcpy(phys_disk, buffer, sizeof(*buffer));
5782 phys_disk->MaxLBA = le32_to_cpu(buffer->MaxLBA);
5783
5784 out:
5785
5786 if (buffer)
5787 dma_free_coherent(&ioc->pcidev->dev, hdr.PageLength * 4,
5788 buffer, dma_handle);
5789
5790 return rc;
5791}
5792
5793/**
5794 * mpt_raid_phys_disk_get_num_paths - returns number paths associated to this phys_num
5795 * @ioc: Pointer to a Adapter Structure
5796 * @phys_disk_num: io unit unique phys disk num generated by the ioc
5797 *
5798 * Return:
5799 * returns number paths
5800 **/
5801int
5802mpt_raid_phys_disk_get_num_paths(MPT_ADAPTER *ioc, u8 phys_disk_num)
5803{
5804 CONFIGPARMS cfg;
5805 ConfigPageHeader_t hdr;
5806 dma_addr_t dma_handle;
5807 pRaidPhysDiskPage1_t buffer = NULL;
5808 int rc;
5809
5810 memset(&cfg, 0 , sizeof(CONFIGPARMS));
5811 memset(&hdr, 0 , sizeof(ConfigPageHeader_t));
5812
5813 hdr.PageVersion = MPI_RAIDPHYSDISKPAGE1_PAGEVERSION;
5814 hdr.PageType = MPI_CONFIG_PAGETYPE_RAID_PHYSDISK;
5815 hdr.PageNumber = 1;
5816 cfg.cfghdr.hdr = &hdr;
5817 cfg.physAddr = -1;
5818 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
5819
5820 if (mpt_config(ioc, &cfg) != 0) {
5821 rc = 0;
5822 goto out;
5823 }
5824
5825 if (!hdr.PageLength) {
5826 rc = 0;
5827 goto out;
5828 }
5829
5830 buffer = dma_alloc_coherent(&ioc->pcidev->dev, hdr.PageLength * 4,
5831 &dma_handle, GFP_KERNEL);
5832
5833 if (!buffer) {
5834 rc = 0;
5835 goto out;
5836 }
5837
5838 cfg.physAddr = dma_handle;
5839 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
5840 cfg.pageAddr = phys_disk_num;
5841
5842 if (mpt_config(ioc, &cfg) != 0) {
5843 rc = 0;
5844 goto out;
5845 }
5846
5847 rc = buffer->NumPhysDiskPaths;
5848 out:
5849
5850 if (buffer)
5851 dma_free_coherent(&ioc->pcidev->dev, hdr.PageLength * 4,
5852 buffer, dma_handle);
5853
5854 return rc;
5855}
5856EXPORT_SYMBOL(mpt_raid_phys_disk_get_num_paths);
5857
5858/**
5859 * mpt_raid_phys_disk_pg1 - returns phys disk page 1
5860 * @ioc: Pointer to a Adapter Structure
5861 * @phys_disk_num: io unit unique phys disk num generated by the ioc
5862 * @phys_disk: requested payload data returned
5863 *
5864 * Return:
5865 * 0 on success
5866 * -EFAULT if read of config page header fails or data pointer not NULL
5867 * -ENOMEM if pci_alloc failed
5868 **/
5869int
5870mpt_raid_phys_disk_pg1(MPT_ADAPTER *ioc, u8 phys_disk_num,
5871 RaidPhysDiskPage1_t *phys_disk)
5872{
5873 CONFIGPARMS cfg;
5874 ConfigPageHeader_t hdr;
5875 dma_addr_t dma_handle;
5876 pRaidPhysDiskPage1_t buffer = NULL;
5877 int rc;
5878 int i;
5879 __le64 sas_address;
5880
5881 memset(&cfg, 0 , sizeof(CONFIGPARMS));
5882 memset(&hdr, 0 , sizeof(ConfigPageHeader_t));
5883 rc = 0;
5884
5885 hdr.PageVersion = MPI_RAIDPHYSDISKPAGE1_PAGEVERSION;
5886 hdr.PageType = MPI_CONFIG_PAGETYPE_RAID_PHYSDISK;
5887 hdr.PageNumber = 1;
5888 cfg.cfghdr.hdr = &hdr;
5889 cfg.physAddr = -1;
5890 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
5891
5892 if (mpt_config(ioc, &cfg) != 0) {
5893 rc = -EFAULT;
5894 goto out;
5895 }
5896
5897 if (!hdr.PageLength) {
5898 rc = -EFAULT;
5899 goto out;
5900 }
5901
5902 buffer = dma_alloc_coherent(&ioc->pcidev->dev, hdr.PageLength * 4,
5903 &dma_handle, GFP_KERNEL);
5904
5905 if (!buffer) {
5906 rc = -ENOMEM;
5907 goto out;
5908 }
5909
5910 cfg.physAddr = dma_handle;
5911 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
5912 cfg.pageAddr = phys_disk_num;
5913
5914 if (mpt_config(ioc, &cfg) != 0) {
5915 rc = -EFAULT;
5916 goto out;
5917 }
5918
5919 phys_disk->NumPhysDiskPaths = buffer->NumPhysDiskPaths;
5920 phys_disk->PhysDiskNum = phys_disk_num;
5921 for (i = 0; i < phys_disk->NumPhysDiskPaths; i++) {
5922 phys_disk->Path[i].PhysDiskID = buffer->Path[i].PhysDiskID;
5923 phys_disk->Path[i].PhysDiskBus = buffer->Path[i].PhysDiskBus;
5924 phys_disk->Path[i].OwnerIdentifier =
5925 buffer->Path[i].OwnerIdentifier;
5926 phys_disk->Path[i].Flags = le16_to_cpu(buffer->Path[i].Flags);
5927 memcpy(&sas_address, &buffer->Path[i].WWID, sizeof(__le64));
5928 sas_address = le64_to_cpu(sas_address);
5929 memcpy(&phys_disk->Path[i].WWID, &sas_address, sizeof(__le64));
5930 memcpy(&sas_address,
5931 &buffer->Path[i].OwnerWWID, sizeof(__le64));
5932 sas_address = le64_to_cpu(sas_address);
5933 memcpy(&phys_disk->Path[i].OwnerWWID,
5934 &sas_address, sizeof(__le64));
5935 }
5936
5937 out:
5938
5939 if (buffer)
5940 dma_free_coherent(&ioc->pcidev->dev, hdr.PageLength * 4,
5941 buffer, dma_handle);
5942
5943 return rc;
5944}
5945EXPORT_SYMBOL(mpt_raid_phys_disk_pg1);
5946
5947
5948/**
5949 * mpt_findImVolumes - Identify IDs of hidden disks and RAID Volumes
5950 * @ioc: Pointer to a Adapter Strucutre
5951 *
5952 * Return:
5953 * 0 on success
5954 * -EFAULT if read of config page header fails or data pointer not NULL
5955 * -ENOMEM if pci_alloc failed
5956 **/
5957int
5958mpt_findImVolumes(MPT_ADAPTER *ioc)
5959{
5960 IOCPage2_t *pIoc2;
5961 u8 *mem;
5962 dma_addr_t ioc2_dma;
5963 CONFIGPARMS cfg;
5964 ConfigPageHeader_t header;
5965 int rc = 0;
5966 int iocpage2sz;
5967 int i;
5968
5969 if (!ioc->ir_firmware)
5970 return 0;
5971
5972 /* Free the old page
5973 */
5974 kfree(ioc->raid_data.pIocPg2);
5975 ioc->raid_data.pIocPg2 = NULL;
5976 mpt_inactive_raid_list_free(ioc);
5977
5978 /* Read IOCP2 header then the page.
5979 */
5980 header.PageVersion = 0;
5981 header.PageLength = 0;
5982 header.PageNumber = 2;
5983 header.PageType = MPI_CONFIG_PAGETYPE_IOC;
5984 cfg.cfghdr.hdr = &header;
5985 cfg.physAddr = -1;
5986 cfg.pageAddr = 0;
5987 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
5988 cfg.dir = 0;
5989 cfg.timeout = 0;
5990 if (mpt_config(ioc, &cfg) != 0)
5991 return -EFAULT;
5992
5993 if (header.PageLength == 0)
5994 return -EFAULT;
5995
5996 iocpage2sz = header.PageLength * 4;
5997 pIoc2 = dma_alloc_coherent(&ioc->pcidev->dev, iocpage2sz, &ioc2_dma,
5998 GFP_KERNEL);
5999 if (!pIoc2)
6000 return -ENOMEM;
6001
6002 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
6003 cfg.physAddr = ioc2_dma;
6004 if (mpt_config(ioc, &cfg) != 0)
6005 goto out;
6006
6007 mem = kmemdup(pIoc2, iocpage2sz, GFP_KERNEL);
6008 if (!mem) {
6009 rc = -ENOMEM;
6010 goto out;
6011 }
6012
6013 ioc->raid_data.pIocPg2 = (IOCPage2_t *) mem;
6014
6015 mpt_read_ioc_pg_3(ioc);
6016
6017 for (i = 0; i < pIoc2->NumActiveVolumes ; i++)
6018 mpt_inactive_raid_volumes(ioc,
6019 pIoc2->RaidVolume[i].VolumeBus,
6020 pIoc2->RaidVolume[i].VolumeID);
6021
6022 out:
6023 dma_free_coherent(&ioc->pcidev->dev, iocpage2sz, pIoc2, ioc2_dma);
6024
6025 return rc;
6026}
6027
6028static int
6029mpt_read_ioc_pg_3(MPT_ADAPTER *ioc)
6030{
6031 IOCPage3_t *pIoc3;
6032 u8 *mem;
6033 CONFIGPARMS cfg;
6034 ConfigPageHeader_t header;
6035 dma_addr_t ioc3_dma;
6036 int iocpage3sz = 0;
6037
6038 /* Free the old page
6039 */
6040 kfree(ioc->raid_data.pIocPg3);
6041 ioc->raid_data.pIocPg3 = NULL;
6042
6043 /* There is at least one physical disk.
6044 * Read and save IOC Page 3
6045 */
6046 header.PageVersion = 0;
6047 header.PageLength = 0;
6048 header.PageNumber = 3;
6049 header.PageType = MPI_CONFIG_PAGETYPE_IOC;
6050 cfg.cfghdr.hdr = &header;
6051 cfg.physAddr = -1;
6052 cfg.pageAddr = 0;
6053 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
6054 cfg.dir = 0;
6055 cfg.timeout = 0;
6056 if (mpt_config(ioc, &cfg) != 0)
6057 return 0;
6058
6059 if (header.PageLength == 0)
6060 return 0;
6061
6062 /* Read Header good, alloc memory
6063 */
6064 iocpage3sz = header.PageLength * 4;
6065 pIoc3 = dma_alloc_coherent(&ioc->pcidev->dev, iocpage3sz, &ioc3_dma,
6066 GFP_KERNEL);
6067 if (!pIoc3)
6068 return 0;
6069
6070 /* Read the Page and save the data
6071 * into malloc'd memory.
6072 */
6073 cfg.physAddr = ioc3_dma;
6074 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
6075 if (mpt_config(ioc, &cfg) == 0) {
6076 mem = kmalloc(iocpage3sz, GFP_KERNEL);
6077 if (mem) {
6078 memcpy(mem, (u8 *)pIoc3, iocpage3sz);
6079 ioc->raid_data.pIocPg3 = (IOCPage3_t *) mem;
6080 }
6081 }
6082
6083 dma_free_coherent(&ioc->pcidev->dev, iocpage3sz, pIoc3, ioc3_dma);
6084
6085 return 0;
6086}
6087
6088static void
6089mpt_read_ioc_pg_4(MPT_ADAPTER *ioc)
6090{
6091 IOCPage4_t *pIoc4;
6092 CONFIGPARMS cfg;
6093 ConfigPageHeader_t header;
6094 dma_addr_t ioc4_dma;
6095 int iocpage4sz;
6096
6097 /* Read and save IOC Page 4
6098 */
6099 header.PageVersion = 0;
6100 header.PageLength = 0;
6101 header.PageNumber = 4;
6102 header.PageType = MPI_CONFIG_PAGETYPE_IOC;
6103 cfg.cfghdr.hdr = &header;
6104 cfg.physAddr = -1;
6105 cfg.pageAddr = 0;
6106 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
6107 cfg.dir = 0;
6108 cfg.timeout = 0;
6109 if (mpt_config(ioc, &cfg) != 0)
6110 return;
6111
6112 if (header.PageLength == 0)
6113 return;
6114
6115 if ( (pIoc4 = ioc->spi_data.pIocPg4) == NULL ) {
6116 iocpage4sz = (header.PageLength + 4) * 4; /* Allow 4 additional SEP's */
6117 pIoc4 = dma_alloc_coherent(&ioc->pcidev->dev, iocpage4sz,
6118 &ioc4_dma, GFP_KERNEL);
6119 if (!pIoc4)
6120 return;
6121 ioc->alloc_total += iocpage4sz;
6122 } else {
6123 ioc4_dma = ioc->spi_data.IocPg4_dma;
6124 iocpage4sz = ioc->spi_data.IocPg4Sz;
6125 }
6126
6127 /* Read the Page into dma memory.
6128 */
6129 cfg.physAddr = ioc4_dma;
6130 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
6131 if (mpt_config(ioc, &cfg) == 0) {
6132 ioc->spi_data.pIocPg4 = (IOCPage4_t *) pIoc4;
6133 ioc->spi_data.IocPg4_dma = ioc4_dma;
6134 ioc->spi_data.IocPg4Sz = iocpage4sz;
6135 } else {
6136 dma_free_coherent(&ioc->pcidev->dev, iocpage4sz, pIoc4,
6137 ioc4_dma);
6138 ioc->spi_data.pIocPg4 = NULL;
6139 ioc->alloc_total -= iocpage4sz;
6140 }
6141}
6142
6143static void
6144mpt_read_ioc_pg_1(MPT_ADAPTER *ioc)
6145{
6146 IOCPage1_t *pIoc1;
6147 CONFIGPARMS cfg;
6148 ConfigPageHeader_t header;
6149 dma_addr_t ioc1_dma;
6150 int iocpage1sz = 0;
6151 u32 tmp;
6152
6153 /* Check the Coalescing Timeout in IOC Page 1
6154 */
6155 header.PageVersion = 0;
6156 header.PageLength = 0;
6157 header.PageNumber = 1;
6158 header.PageType = MPI_CONFIG_PAGETYPE_IOC;
6159 cfg.cfghdr.hdr = &header;
6160 cfg.physAddr = -1;
6161 cfg.pageAddr = 0;
6162 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
6163 cfg.dir = 0;
6164 cfg.timeout = 0;
6165 if (mpt_config(ioc, &cfg) != 0)
6166 return;
6167
6168 if (header.PageLength == 0)
6169 return;
6170
6171 /* Read Header good, alloc memory
6172 */
6173 iocpage1sz = header.PageLength * 4;
6174 pIoc1 = dma_alloc_coherent(&ioc->pcidev->dev, iocpage1sz, &ioc1_dma,
6175 GFP_KERNEL);
6176 if (!pIoc1)
6177 return;
6178
6179 /* Read the Page and check coalescing timeout
6180 */
6181 cfg.physAddr = ioc1_dma;
6182 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
6183 if (mpt_config(ioc, &cfg) == 0) {
6184
6185 tmp = le32_to_cpu(pIoc1->Flags) & MPI_IOCPAGE1_REPLY_COALESCING;
6186 if (tmp == MPI_IOCPAGE1_REPLY_COALESCING) {
6187 tmp = le32_to_cpu(pIoc1->CoalescingTimeout);
6188
6189 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Coalescing Enabled Timeout = %d\n",
6190 ioc->name, tmp));
6191
6192 if (tmp > MPT_COALESCING_TIMEOUT) {
6193 pIoc1->CoalescingTimeout = cpu_to_le32(MPT_COALESCING_TIMEOUT);
6194
6195 /* Write NVRAM and current
6196 */
6197 cfg.dir = 1;
6198 cfg.action = MPI_CONFIG_ACTION_PAGE_WRITE_CURRENT;
6199 if (mpt_config(ioc, &cfg) == 0) {
6200 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Reset Current Coalescing Timeout to = %d\n",
6201 ioc->name, MPT_COALESCING_TIMEOUT));
6202
6203 cfg.action = MPI_CONFIG_ACTION_PAGE_WRITE_NVRAM;
6204 if (mpt_config(ioc, &cfg) == 0) {
6205 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT
6206 "Reset NVRAM Coalescing Timeout to = %d\n",
6207 ioc->name, MPT_COALESCING_TIMEOUT));
6208 } else {
6209 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT
6210 "Reset NVRAM Coalescing Timeout Failed\n",
6211 ioc->name));
6212 }
6213
6214 } else {
6215 dprintk(ioc, printk(MYIOC_s_WARN_FMT
6216 "Reset of Current Coalescing Timeout Failed!\n",
6217 ioc->name));
6218 }
6219 }
6220
6221 } else {
6222 dprintk(ioc, printk(MYIOC_s_WARN_FMT "Coalescing Disabled\n", ioc->name));
6223 }
6224 }
6225
6226 dma_free_coherent(&ioc->pcidev->dev, iocpage1sz, pIoc1, ioc1_dma);
6227
6228 return;
6229}
6230
6231static void
6232mpt_get_manufacturing_pg_0(MPT_ADAPTER *ioc)
6233{
6234 CONFIGPARMS cfg;
6235 ConfigPageHeader_t hdr;
6236 dma_addr_t buf_dma;
6237 ManufacturingPage0_t *pbuf = NULL;
6238
6239 memset(&cfg, 0 , sizeof(CONFIGPARMS));
6240 memset(&hdr, 0 , sizeof(ConfigPageHeader_t));
6241
6242 hdr.PageType = MPI_CONFIG_PAGETYPE_MANUFACTURING;
6243 cfg.cfghdr.hdr = &hdr;
6244 cfg.physAddr = -1;
6245 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
6246 cfg.timeout = 10;
6247
6248 if (mpt_config(ioc, &cfg) != 0)
6249 goto out;
6250
6251 if (!cfg.cfghdr.hdr->PageLength)
6252 goto out;
6253
6254 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
6255 pbuf = dma_alloc_coherent(&ioc->pcidev->dev, hdr.PageLength * 4,
6256 &buf_dma, GFP_KERNEL);
6257 if (!pbuf)
6258 goto out;
6259
6260 cfg.physAddr = buf_dma;
6261
6262 if (mpt_config(ioc, &cfg) != 0)
6263 goto out;
6264
6265 memcpy(ioc->board_name, pbuf->BoardName, sizeof(ioc->board_name));
6266 memcpy(ioc->board_assembly, pbuf->BoardAssembly, sizeof(ioc->board_assembly));
6267 memcpy(ioc->board_tracer, pbuf->BoardTracerNumber, sizeof(ioc->board_tracer));
6268
6269out:
6270
6271 if (pbuf)
6272 dma_free_coherent(&ioc->pcidev->dev, hdr.PageLength * 4, pbuf,
6273 buf_dma);
6274}
6275
6276/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
6277/**
6278 * SendEventNotification - Send EventNotification (on or off) request to adapter
6279 * @ioc: Pointer to MPT_ADAPTER structure
6280 * @EvSwitch: Event switch flags
6281 * @sleepFlag: Specifies whether the process can sleep
6282 */
6283static int
6284SendEventNotification(MPT_ADAPTER *ioc, u8 EvSwitch, int sleepFlag)
6285{
6286 EventNotification_t evn;
6287 MPIDefaultReply_t reply_buf;
6288
6289 memset(&evn, 0, sizeof(EventNotification_t));
6290 memset(&reply_buf, 0, sizeof(MPIDefaultReply_t));
6291
6292 evn.Function = MPI_FUNCTION_EVENT_NOTIFICATION;
6293 evn.Switch = EvSwitch;
6294 evn.MsgContext = cpu_to_le32(mpt_base_index << 16);
6295
6296 devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT
6297 "Sending EventNotification (%d) request %p\n",
6298 ioc->name, EvSwitch, &evn));
6299
6300 return mpt_handshake_req_reply_wait(ioc, sizeof(EventNotification_t),
6301 (u32 *)&evn, sizeof(MPIDefaultReply_t), (u16 *)&reply_buf, 30,
6302 sleepFlag);
6303}
6304
6305/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
6306/**
6307 * SendEventAck - Send EventAck request to MPT adapter.
6308 * @ioc: Pointer to MPT_ADAPTER structure
6309 * @evnp: Pointer to original EventNotification request
6310 */
6311static int
6312SendEventAck(MPT_ADAPTER *ioc, EventNotificationReply_t *evnp)
6313{
6314 EventAck_t *pAck;
6315
6316 if ((pAck = (EventAck_t *) mpt_get_msg_frame(mpt_base_index, ioc)) == NULL) {
6317 dfailprintk(ioc, printk(MYIOC_s_WARN_FMT "%s, no msg frames!!\n",
6318 ioc->name, __func__));
6319 return -1;
6320 }
6321
6322 devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending EventAck\n", ioc->name));
6323
6324 pAck->Function = MPI_FUNCTION_EVENT_ACK;
6325 pAck->ChainOffset = 0;
6326 pAck->Reserved[0] = pAck->Reserved[1] = 0;
6327 pAck->MsgFlags = 0;
6328 pAck->Reserved1[0] = pAck->Reserved1[1] = pAck->Reserved1[2] = 0;
6329 pAck->Event = evnp->Event;
6330 pAck->EventContext = evnp->EventContext;
6331
6332 mpt_put_msg_frame(mpt_base_index, ioc, (MPT_FRAME_HDR *)pAck);
6333
6334 return 0;
6335}
6336
6337/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
6338/**
6339 * mpt_config - Generic function to issue config message
6340 * @ioc: Pointer to an adapter structure
6341 * @pCfg: Pointer to a configuration structure. Struct contains
6342 * action, page address, direction, physical address
6343 * and pointer to a configuration page header
6344 * Page header is updated.
6345 *
6346 * Returns 0 for success
6347 * -EAGAIN if no msg frames currently available
6348 * -EFAULT for non-successful reply or no reply (timeout)
6349 */
6350int
6351mpt_config(MPT_ADAPTER *ioc, CONFIGPARMS *pCfg)
6352{
6353 Config_t *pReq;
6354 ConfigReply_t *pReply;
6355 ConfigExtendedPageHeader_t *pExtHdr = NULL;
6356 MPT_FRAME_HDR *mf;
6357 int ii;
6358 int flagsLength;
6359 long timeout;
6360 int ret;
6361 u8 page_type = 0, extend_page;
6362 unsigned long timeleft;
6363 unsigned long flags;
6364 u8 issue_hard_reset = 0;
6365 u8 retry_count = 0;
6366
6367 might_sleep();
6368
6369 /* don't send a config page during diag reset */
6370 spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
6371 if (ioc->ioc_reset_in_progress) {
6372 dfailprintk(ioc, printk(MYIOC_s_DEBUG_FMT
6373 "%s: busy with host reset\n", ioc->name, __func__));
6374 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
6375 return -EBUSY;
6376 }
6377 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
6378
6379 /* don't send if no chance of success */
6380 if (!ioc->active ||
6381 mpt_GetIocState(ioc, 1) != MPI_IOC_STATE_OPERATIONAL) {
6382 dfailprintk(ioc, printk(MYIOC_s_DEBUG_FMT
6383 "%s: ioc not operational, %d, %xh\n",
6384 ioc->name, __func__, ioc->active,
6385 mpt_GetIocState(ioc, 0)));
6386 return -EFAULT;
6387 }
6388
6389 retry_config:
6390 mutex_lock(&ioc->mptbase_cmds.mutex);
6391 /* init the internal cmd struct */
6392 memset(ioc->mptbase_cmds.reply, 0 , MPT_DEFAULT_FRAME_SIZE);
6393 INITIALIZE_MGMT_STATUS(ioc->mptbase_cmds.status)
6394
6395 /* Get and Populate a free Frame
6396 */
6397 if ((mf = mpt_get_msg_frame(mpt_base_index, ioc)) == NULL) {
6398 dcprintk(ioc, printk(MYIOC_s_WARN_FMT
6399 "mpt_config: no msg frames!\n", ioc->name));
6400 ret = -EAGAIN;
6401 goto out;
6402 }
6403
6404 pReq = (Config_t *)mf;
6405 pReq->Action = pCfg->action;
6406 pReq->Reserved = 0;
6407 pReq->ChainOffset = 0;
6408 pReq->Function = MPI_FUNCTION_CONFIG;
6409
6410 /* Assume page type is not extended and clear "reserved" fields. */
6411 pReq->ExtPageLength = 0;
6412 pReq->ExtPageType = 0;
6413 pReq->MsgFlags = 0;
6414
6415 for (ii=0; ii < 8; ii++)
6416 pReq->Reserved2[ii] = 0;
6417
6418 pReq->Header.PageVersion = pCfg->cfghdr.hdr->PageVersion;
6419 pReq->Header.PageLength = pCfg->cfghdr.hdr->PageLength;
6420 pReq->Header.PageNumber = pCfg->cfghdr.hdr->PageNumber;
6421 pReq->Header.PageType = (pCfg->cfghdr.hdr->PageType & MPI_CONFIG_PAGETYPE_MASK);
6422
6423 if ((pCfg->cfghdr.hdr->PageType & MPI_CONFIG_PAGETYPE_MASK) == MPI_CONFIG_PAGETYPE_EXTENDED) {
6424 pExtHdr = (ConfigExtendedPageHeader_t *)pCfg->cfghdr.ehdr;
6425 pReq->ExtPageLength = cpu_to_le16(pExtHdr->ExtPageLength);
6426 pReq->ExtPageType = pExtHdr->ExtPageType;
6427 pReq->Header.PageType = MPI_CONFIG_PAGETYPE_EXTENDED;
6428
6429 /* Page Length must be treated as a reserved field for the
6430 * extended header.
6431 */
6432 pReq->Header.PageLength = 0;
6433 }
6434
6435 pReq->PageAddress = cpu_to_le32(pCfg->pageAddr);
6436
6437 /* Add a SGE to the config request.
6438 */
6439 if (pCfg->dir)
6440 flagsLength = MPT_SGE_FLAGS_SSIMPLE_WRITE;
6441 else
6442 flagsLength = MPT_SGE_FLAGS_SSIMPLE_READ;
6443
6444 if ((pCfg->cfghdr.hdr->PageType & MPI_CONFIG_PAGETYPE_MASK) ==
6445 MPI_CONFIG_PAGETYPE_EXTENDED) {
6446 flagsLength |= pExtHdr->ExtPageLength * 4;
6447 page_type = pReq->ExtPageType;
6448 extend_page = 1;
6449 } else {
6450 flagsLength |= pCfg->cfghdr.hdr->PageLength * 4;
6451 page_type = pReq->Header.PageType;
6452 extend_page = 0;
6453 }
6454
6455 dcprintk(ioc, printk(MYIOC_s_DEBUG_FMT
6456 "Sending Config request type 0x%x, page 0x%x and action %d\n",
6457 ioc->name, page_type, pReq->Header.PageNumber, pReq->Action));
6458
6459 ioc->add_sge((char *)&pReq->PageBufferSGE, flagsLength, pCfg->physAddr);
6460 timeout = (pCfg->timeout < 15) ? HZ*15 : HZ*pCfg->timeout;
6461 mpt_put_msg_frame(mpt_base_index, ioc, mf);
6462 timeleft = wait_for_completion_timeout(&ioc->mptbase_cmds.done,
6463 timeout);
6464 if (!(ioc->mptbase_cmds.status & MPT_MGMT_STATUS_COMMAND_GOOD)) {
6465 ret = -ETIME;
6466 dfailprintk(ioc, printk(MYIOC_s_DEBUG_FMT
6467 "Failed Sending Config request type 0x%x, page 0x%x,"
6468 " action %d, status %xh, time left %ld\n\n",
6469 ioc->name, page_type, pReq->Header.PageNumber,
6470 pReq->Action, ioc->mptbase_cmds.status, timeleft));
6471 if (ioc->mptbase_cmds.status & MPT_MGMT_STATUS_DID_IOCRESET)
6472 goto out;
6473 if (!timeleft) {
6474 spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
6475 if (ioc->ioc_reset_in_progress) {
6476 spin_unlock_irqrestore(&ioc->taskmgmt_lock,
6477 flags);
6478 printk(MYIOC_s_INFO_FMT "%s: host reset in"
6479 " progress mpt_config timed out.!!\n",
6480 __func__, ioc->name);
6481 mutex_unlock(&ioc->mptbase_cmds.mutex);
6482 return -EFAULT;
6483 }
6484 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
6485 issue_hard_reset = 1;
6486 }
6487 goto out;
6488 }
6489
6490 if (!(ioc->mptbase_cmds.status & MPT_MGMT_STATUS_RF_VALID)) {
6491 ret = -1;
6492 goto out;
6493 }
6494 pReply = (ConfigReply_t *)ioc->mptbase_cmds.reply;
6495 ret = le16_to_cpu(pReply->IOCStatus) & MPI_IOCSTATUS_MASK;
6496 if (ret == MPI_IOCSTATUS_SUCCESS) {
6497 if (extend_page) {
6498 pCfg->cfghdr.ehdr->ExtPageLength =
6499 le16_to_cpu(pReply->ExtPageLength);
6500 pCfg->cfghdr.ehdr->ExtPageType =
6501 pReply->ExtPageType;
6502 }
6503 pCfg->cfghdr.hdr->PageVersion = pReply->Header.PageVersion;
6504 pCfg->cfghdr.hdr->PageLength = pReply->Header.PageLength;
6505 pCfg->cfghdr.hdr->PageNumber = pReply->Header.PageNumber;
6506 pCfg->cfghdr.hdr->PageType = pReply->Header.PageType;
6507
6508 }
6509
6510 if (retry_count)
6511 printk(MYIOC_s_INFO_FMT "Retry completed "
6512 "ret=0x%x timeleft=%ld\n",
6513 ioc->name, ret, timeleft);
6514
6515 dcprintk(ioc, printk(KERN_DEBUG "IOCStatus=%04xh, IOCLogInfo=%08xh\n",
6516 ret, le32_to_cpu(pReply->IOCLogInfo)));
6517
6518out:
6519
6520 CLEAR_MGMT_STATUS(ioc->mptbase_cmds.status)
6521 mutex_unlock(&ioc->mptbase_cmds.mutex);
6522 if (issue_hard_reset) {
6523 issue_hard_reset = 0;
6524 printk(MYIOC_s_WARN_FMT
6525 "Issuing Reset from %s!!, doorbell=0x%08x\n",
6526 ioc->name, __func__, mpt_GetIocState(ioc, 0));
6527 if (retry_count == 0) {
6528 if (mpt_Soft_Hard_ResetHandler(ioc, CAN_SLEEP) != 0)
6529 retry_count++;
6530 } else
6531 mpt_HardResetHandler(ioc, CAN_SLEEP);
6532
6533 mpt_free_msg_frame(ioc, mf);
6534 /* attempt one retry for a timed out command */
6535 if (retry_count < 2) {
6536 printk(MYIOC_s_INFO_FMT
6537 "Attempting Retry Config request"
6538 " type 0x%x, page 0x%x,"
6539 " action %d\n", ioc->name, page_type,
6540 pCfg->cfghdr.hdr->PageNumber, pCfg->action);
6541 retry_count++;
6542 goto retry_config;
6543 }
6544 }
6545 return ret;
6546
6547}
6548
6549/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
6550/**
6551 * mpt_ioc_reset - Base cleanup for hard reset
6552 * @ioc: Pointer to the adapter structure
6553 * @reset_phase: Indicates pre- or post-reset functionality
6554 *
6555 * Remark: Frees resources with internally generated commands.
6556 */
6557static int
6558mpt_ioc_reset(MPT_ADAPTER *ioc, int reset_phase)
6559{
6560 switch (reset_phase) {
6561 case MPT_IOC_SETUP_RESET:
6562 ioc->taskmgmt_quiesce_io = 1;
6563 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT
6564 "%s: MPT_IOC_SETUP_RESET\n", ioc->name, __func__));
6565 break;
6566 case MPT_IOC_PRE_RESET:
6567 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT
6568 "%s: MPT_IOC_PRE_RESET\n", ioc->name, __func__));
6569 break;
6570 case MPT_IOC_POST_RESET:
6571 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT
6572 "%s: MPT_IOC_POST_RESET\n", ioc->name, __func__));
6573/* wake up mptbase_cmds */
6574 if (ioc->mptbase_cmds.status & MPT_MGMT_STATUS_PENDING) {
6575 ioc->mptbase_cmds.status |=
6576 MPT_MGMT_STATUS_DID_IOCRESET;
6577 complete(&ioc->mptbase_cmds.done);
6578 }
6579/* wake up taskmgmt_cmds */
6580 if (ioc->taskmgmt_cmds.status & MPT_MGMT_STATUS_PENDING) {
6581 ioc->taskmgmt_cmds.status |=
6582 MPT_MGMT_STATUS_DID_IOCRESET;
6583 complete(&ioc->taskmgmt_cmds.done);
6584 }
6585 break;
6586 default:
6587 break;
6588 }
6589
6590 return 1; /* currently means nothing really */
6591}
6592
6593
6594#ifdef CONFIG_PROC_FS /* { */
6595/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
6596/*
6597 * procfs (%MPT_PROCFS_MPTBASEDIR/...) support stuff...
6598 */
6599/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
6600/**
6601 * procmpt_create - Create %MPT_PROCFS_MPTBASEDIR entries.
6602 *
6603 * Returns 0 for success, non-zero for failure.
6604 */
6605static int
6606procmpt_create(void)
6607{
6608 mpt_proc_root_dir = proc_mkdir(MPT_PROCFS_MPTBASEDIR, NULL);
6609 if (mpt_proc_root_dir == NULL)
6610 return -ENOTDIR;
6611
6612 proc_create_single("summary", S_IRUGO, mpt_proc_root_dir,
6613 mpt_summary_proc_show);
6614 proc_create_single("version", S_IRUGO, mpt_proc_root_dir,
6615 mpt_version_proc_show);
6616 return 0;
6617}
6618
6619/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
6620/**
6621 * procmpt_destroy - Tear down %MPT_PROCFS_MPTBASEDIR entries.
6622 *
6623 * Returns 0 for success, non-zero for failure.
6624 */
6625static void
6626procmpt_destroy(void)
6627{
6628 remove_proc_entry("version", mpt_proc_root_dir);
6629 remove_proc_entry("summary", mpt_proc_root_dir);
6630 remove_proc_entry(MPT_PROCFS_MPTBASEDIR, NULL);
6631}
6632
6633/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
6634/*
6635 * Handles read request from /proc/mpt/summary or /proc/mpt/iocN/summary.
6636 */
6637static void seq_mpt_print_ioc_summary(MPT_ADAPTER *ioc, struct seq_file *m, int showlan);
6638
6639static int mpt_summary_proc_show(struct seq_file *m, void *v)
6640{
6641 MPT_ADAPTER *ioc = m->private;
6642
6643 if (ioc) {
6644 seq_mpt_print_ioc_summary(ioc, m, 1);
6645 } else {
6646 list_for_each_entry(ioc, &ioc_list, list) {
6647 seq_mpt_print_ioc_summary(ioc, m, 1);
6648 }
6649 }
6650
6651 return 0;
6652}
6653
6654static int mpt_version_proc_show(struct seq_file *m, void *v)
6655{
6656 u8 cb_idx;
6657 int scsi, fc, sas, lan, ctl, targ;
6658 char *drvname;
6659
6660 seq_printf(m, "%s-%s\n", "mptlinux", MPT_LINUX_VERSION_COMMON);
6661 seq_printf(m, " Fusion MPT base driver\n");
6662
6663 scsi = fc = sas = lan = ctl = targ = 0;
6664 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
6665 drvname = NULL;
6666 if (MptCallbacks[cb_idx]) {
6667 switch (MptDriverClass[cb_idx]) {
6668 case MPTSPI_DRIVER:
6669 if (!scsi++) drvname = "SPI host";
6670 break;
6671 case MPTFC_DRIVER:
6672 if (!fc++) drvname = "FC host";
6673 break;
6674 case MPTSAS_DRIVER:
6675 if (!sas++) drvname = "SAS host";
6676 break;
6677 case MPTLAN_DRIVER:
6678 if (!lan++) drvname = "LAN";
6679 break;
6680 case MPTSTM_DRIVER:
6681 if (!targ++) drvname = "SCSI target";
6682 break;
6683 case MPTCTL_DRIVER:
6684 if (!ctl++) drvname = "ioctl";
6685 break;
6686 }
6687
6688 if (drvname)
6689 seq_printf(m, " Fusion MPT %s driver\n", drvname);
6690 }
6691 }
6692
6693 return 0;
6694}
6695
6696static int mpt_iocinfo_proc_show(struct seq_file *m, void *v)
6697{
6698 MPT_ADAPTER *ioc = m->private;
6699 char expVer[32];
6700 int sz;
6701 int p;
6702
6703 mpt_get_fw_exp_ver(expVer, ioc);
6704
6705 seq_printf(m, "%s:", ioc->name);
6706 if (ioc->facts.Flags & MPI_IOCFACTS_FLAGS_FW_DOWNLOAD_BOOT)
6707 seq_printf(m, " (f/w download boot flag set)");
6708// if (ioc->facts.IOCExceptions & MPI_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL)
6709// seq_printf(m, " CONFIG_CHECKSUM_FAIL!");
6710
6711 seq_printf(m, "\n ProductID = 0x%04x (%s)\n",
6712 ioc->facts.ProductID,
6713 ioc->prod_name);
6714 seq_printf(m, " FWVersion = 0x%08x%s", ioc->facts.FWVersion.Word, expVer);
6715 if (ioc->facts.FWImageSize)
6716 seq_printf(m, " (fw_size=%d)", ioc->facts.FWImageSize);
6717 seq_printf(m, "\n MsgVersion = 0x%04x\n", ioc->facts.MsgVersion);
6718 seq_printf(m, " FirstWhoInit = 0x%02x\n", ioc->FirstWhoInit);
6719 seq_printf(m, " EventState = 0x%02x\n", ioc->facts.EventState);
6720
6721 seq_printf(m, " CurrentHostMfaHighAddr = 0x%08x\n",
6722 ioc->facts.CurrentHostMfaHighAddr);
6723 seq_printf(m, " CurrentSenseBufferHighAddr = 0x%08x\n",
6724 ioc->facts.CurrentSenseBufferHighAddr);
6725
6726 seq_printf(m, " MaxChainDepth = 0x%02x frames\n", ioc->facts.MaxChainDepth);
6727 seq_printf(m, " MinBlockSize = 0x%02x bytes\n", 4*ioc->facts.BlockSize);
6728
6729 seq_printf(m, " RequestFrames @ 0x%p (Dma @ 0x%p)\n",
6730 (void *)ioc->req_frames, (void *)(ulong)ioc->req_frames_dma);
6731 /*
6732 * Rounding UP to nearest 4-kB boundary here...
6733 */
6734 sz = (ioc->req_sz * ioc->req_depth) + 128;
6735 sz = ((sz + 0x1000UL - 1UL) / 0x1000) * 0x1000;
6736 seq_printf(m, " {CurReqSz=%d} x {CurReqDepth=%d} = %d bytes ^= 0x%x\n",
6737 ioc->req_sz, ioc->req_depth, ioc->req_sz*ioc->req_depth, sz);
6738 seq_printf(m, " {MaxReqSz=%d} {MaxReqDepth=%d}\n",
6739 4*ioc->facts.RequestFrameSize,
6740 ioc->facts.GlobalCredits);
6741
6742 seq_printf(m, " Frames @ 0x%p (Dma @ 0x%p)\n",
6743 (void *)ioc->alloc, (void *)(ulong)ioc->alloc_dma);
6744 sz = (ioc->reply_sz * ioc->reply_depth) + 128;
6745 seq_printf(m, " {CurRepSz=%d} x {CurRepDepth=%d} = %d bytes ^= 0x%x\n",
6746 ioc->reply_sz, ioc->reply_depth, ioc->reply_sz*ioc->reply_depth, sz);
6747 seq_printf(m, " {MaxRepSz=%d} {MaxRepDepth=%d}\n",
6748 ioc->facts.CurReplyFrameSize,
6749 ioc->facts.ReplyQueueDepth);
6750
6751 seq_printf(m, " MaxDevices = %d\n",
6752 (ioc->facts.MaxDevices==0) ? 255 : ioc->facts.MaxDevices);
6753 seq_printf(m, " MaxBuses = %d\n", ioc->facts.MaxBuses);
6754
6755 /* per-port info */
6756 for (p=0; p < ioc->facts.NumberOfPorts; p++) {
6757 seq_printf(m, " PortNumber = %d (of %d)\n",
6758 p+1,
6759 ioc->facts.NumberOfPorts);
6760 if (ioc->bus_type == FC) {
6761 if (ioc->pfacts[p].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_LAN) {
6762 u8 *a = (u8*)&ioc->lan_cnfg_page1.HardwareAddressLow;
6763 seq_printf(m, " LanAddr = %pMR\n", a);
6764 }
6765 seq_printf(m, " WWN = %08X%08X:%08X%08X\n",
6766 ioc->fc_port_page0[p].WWNN.High,
6767 ioc->fc_port_page0[p].WWNN.Low,
6768 ioc->fc_port_page0[p].WWPN.High,
6769 ioc->fc_port_page0[p].WWPN.Low);
6770 }
6771 }
6772
6773 return 0;
6774}
6775#endif /* CONFIG_PROC_FS } */
6776
6777/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
6778static void
6779mpt_get_fw_exp_ver(char *buf, MPT_ADAPTER *ioc)
6780{
6781 buf[0] ='\0';
6782 if ((ioc->facts.FWVersion.Word >> 24) == 0x0E) {
6783 sprintf(buf, " (Exp %02d%02d)",
6784 (ioc->facts.FWVersion.Word >> 16) & 0x00FF, /* Month */
6785 (ioc->facts.FWVersion.Word >> 8) & 0x1F); /* Day */
6786
6787 /* insider hack! */
6788 if ((ioc->facts.FWVersion.Word >> 8) & 0x80)
6789 strcat(buf, " [MDBG]");
6790 }
6791}
6792
6793/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
6794/**
6795 * mpt_print_ioc_summary - Write ASCII summary of IOC to a buffer.
6796 * @ioc: Pointer to MPT_ADAPTER structure
6797 * @buffer: Pointer to buffer where IOC summary info should be written
6798 * @size: Pointer to number of bytes we wrote (set by this routine)
6799 * @len: Offset at which to start writing in buffer
6800 * @showlan: Display LAN stuff?
6801 *
6802 * This routine writes (english readable) ASCII text, which represents
6803 * a summary of IOC information, to a buffer.
6804 */
6805void
6806mpt_print_ioc_summary(MPT_ADAPTER *ioc, char *buffer, int *size, int len, int showlan)
6807{
6808 char expVer[32];
6809 int y;
6810
6811 mpt_get_fw_exp_ver(expVer, ioc);
6812
6813 /*
6814 * Shorter summary of attached ioc's...
6815 */
6816 y = sprintf(buffer+len, "%s: %s, %s%08xh%s, Ports=%d, MaxQ=%d",
6817 ioc->name,
6818 ioc->prod_name,
6819 MPT_FW_REV_MAGIC_ID_STRING, /* "FwRev=" or somesuch */
6820 ioc->facts.FWVersion.Word,
6821 expVer,
6822 ioc->facts.NumberOfPorts,
6823 ioc->req_depth);
6824
6825 if (showlan && (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_LAN)) {
6826 u8 *a = (u8*)&ioc->lan_cnfg_page1.HardwareAddressLow;
6827 y += sprintf(buffer+len+y, ", LanAddr=%pMR", a);
6828 }
6829
6830 y += sprintf(buffer+len+y, ", IRQ=%d", ioc->pci_irq);
6831
6832 if (!ioc->active)
6833 y += sprintf(buffer+len+y, " (disabled)");
6834
6835 y += sprintf(buffer+len+y, "\n");
6836
6837 *size = y;
6838}
6839
6840#ifdef CONFIG_PROC_FS
6841static void seq_mpt_print_ioc_summary(MPT_ADAPTER *ioc, struct seq_file *m, int showlan)
6842{
6843 char expVer[32];
6844
6845 mpt_get_fw_exp_ver(expVer, ioc);
6846
6847 /*
6848 * Shorter summary of attached ioc's...
6849 */
6850 seq_printf(m, "%s: %s, %s%08xh%s, Ports=%d, MaxQ=%d",
6851 ioc->name,
6852 ioc->prod_name,
6853 MPT_FW_REV_MAGIC_ID_STRING, /* "FwRev=" or somesuch */
6854 ioc->facts.FWVersion.Word,
6855 expVer,
6856 ioc->facts.NumberOfPorts,
6857 ioc->req_depth);
6858
6859 if (showlan && (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_LAN)) {
6860 u8 *a = (u8*)&ioc->lan_cnfg_page1.HardwareAddressLow;
6861 seq_printf(m, ", LanAddr=%pMR", a);
6862 }
6863
6864 seq_printf(m, ", IRQ=%d", ioc->pci_irq);
6865
6866 if (!ioc->active)
6867 seq_printf(m, " (disabled)");
6868
6869 seq_putc(m, '\n');
6870}
6871#endif
6872
6873/**
6874 * mpt_set_taskmgmt_in_progress_flag - set flags associated with task management
6875 * @ioc: Pointer to MPT_ADAPTER structure
6876 *
6877 * Returns 0 for SUCCESS or -1 if FAILED.
6878 *
6879 * If -1 is return, then it was not possible to set the flags
6880 **/
6881int
6882mpt_set_taskmgmt_in_progress_flag(MPT_ADAPTER *ioc)
6883{
6884 unsigned long flags;
6885 int retval;
6886
6887 spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
6888 if (ioc->ioc_reset_in_progress || ioc->taskmgmt_in_progress ||
6889 (ioc->alt_ioc && ioc->alt_ioc->taskmgmt_in_progress)) {
6890 retval = -1;
6891 goto out;
6892 }
6893 retval = 0;
6894 ioc->taskmgmt_in_progress = 1;
6895 ioc->taskmgmt_quiesce_io = 1;
6896 if (ioc->alt_ioc) {
6897 ioc->alt_ioc->taskmgmt_in_progress = 1;
6898 ioc->alt_ioc->taskmgmt_quiesce_io = 1;
6899 }
6900 out:
6901 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
6902 return retval;
6903}
6904EXPORT_SYMBOL(mpt_set_taskmgmt_in_progress_flag);
6905
6906/**
6907 * mpt_clear_taskmgmt_in_progress_flag - clear flags associated with task management
6908 * @ioc: Pointer to MPT_ADAPTER structure
6909 *
6910 **/
6911void
6912mpt_clear_taskmgmt_in_progress_flag(MPT_ADAPTER *ioc)
6913{
6914 unsigned long flags;
6915
6916 spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
6917 ioc->taskmgmt_in_progress = 0;
6918 ioc->taskmgmt_quiesce_io = 0;
6919 if (ioc->alt_ioc) {
6920 ioc->alt_ioc->taskmgmt_in_progress = 0;
6921 ioc->alt_ioc->taskmgmt_quiesce_io = 0;
6922 }
6923 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
6924}
6925EXPORT_SYMBOL(mpt_clear_taskmgmt_in_progress_flag);
6926
6927
6928/**
6929 * mpt_halt_firmware - Halts the firmware if it is operational and panic
6930 * the kernel
6931 * @ioc: Pointer to MPT_ADAPTER structure
6932 *
6933 **/
6934void __noreturn
6935mpt_halt_firmware(MPT_ADAPTER *ioc)
6936{
6937 u32 ioc_raw_state;
6938
6939 ioc_raw_state = mpt_GetIocState(ioc, 0);
6940
6941 if ((ioc_raw_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_FAULT) {
6942 printk(MYIOC_s_ERR_FMT "IOC is in FAULT state (%04xh)!!!\n",
6943 ioc->name, ioc_raw_state & MPI_DOORBELL_DATA_MASK);
6944 panic("%s: IOC Fault (%04xh)!!!\n", ioc->name,
6945 ioc_raw_state & MPI_DOORBELL_DATA_MASK);
6946 } else {
6947 CHIPREG_WRITE32(&ioc->chip->Doorbell, 0xC0FFEE00);
6948 panic("%s: Firmware is halted due to command timeout\n",
6949 ioc->name);
6950 }
6951}
6952EXPORT_SYMBOL(mpt_halt_firmware);
6953
6954/**
6955 * mpt_SoftResetHandler - Issues a less expensive reset
6956 * @ioc: Pointer to MPT_ADAPTER structure
6957 * @sleepFlag: Indicates if sleep or schedule must be called.
6958 *
6959 * Returns 0 for SUCCESS or -1 if FAILED.
6960 *
6961 * Message Unit Reset - instructs the IOC to reset the Reply Post and
6962 * Free FIFO's. All the Message Frames on Reply Free FIFO are discarded.
6963 * All posted buffers are freed, and event notification is turned off.
6964 * IOC doesn't reply to any outstanding request. This will transfer IOC
6965 * to READY state.
6966 **/
6967static int
6968mpt_SoftResetHandler(MPT_ADAPTER *ioc, int sleepFlag)
6969{
6970 int rc;
6971 int ii;
6972 u8 cb_idx;
6973 unsigned long flags;
6974 u32 ioc_state;
6975 unsigned long time_count;
6976
6977 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT "SoftResetHandler Entered!\n",
6978 ioc->name));
6979
6980 ioc_state = mpt_GetIocState(ioc, 0) & MPI_IOC_STATE_MASK;
6981
6982 if (mpt_fwfault_debug)
6983 mpt_halt_firmware(ioc);
6984
6985 if (ioc_state == MPI_IOC_STATE_FAULT ||
6986 ioc_state == MPI_IOC_STATE_RESET) {
6987 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT
6988 "skipping, either in FAULT or RESET state!\n", ioc->name));
6989 return -1;
6990 }
6991
6992 if (ioc->bus_type == FC) {
6993 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT
6994 "skipping, because the bus type is FC!\n", ioc->name));
6995 return -1;
6996 }
6997
6998 spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
6999 if (ioc->ioc_reset_in_progress) {
7000 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
7001 return -1;
7002 }
7003 ioc->ioc_reset_in_progress = 1;
7004 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
7005
7006 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
7007 if (MptResetHandlers[cb_idx])
7008 mpt_signal_reset(cb_idx, ioc, MPT_IOC_SETUP_RESET);
7009 }
7010
7011 spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
7012 if (ioc->taskmgmt_in_progress) {
7013 ioc->ioc_reset_in_progress = 0;
7014 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
7015 return -1;
7016 }
7017 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
7018 /* Disable reply interrupts (also blocks FreeQ) */
7019 CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF);
7020 ioc->active = 0;
7021 time_count = jiffies;
7022
7023 rc = SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, sleepFlag);
7024
7025 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
7026 if (MptResetHandlers[cb_idx])
7027 mpt_signal_reset(cb_idx, ioc, MPT_IOC_PRE_RESET);
7028 }
7029
7030 if (rc)
7031 goto out;
7032
7033 ioc_state = mpt_GetIocState(ioc, 0) & MPI_IOC_STATE_MASK;
7034 if (ioc_state != MPI_IOC_STATE_READY)
7035 goto out;
7036
7037 for (ii = 0; ii < 5; ii++) {
7038 /* Get IOC facts! Allow 5 retries */
7039 rc = GetIocFacts(ioc, sleepFlag,
7040 MPT_HOSTEVENT_IOC_RECOVER);
7041 if (rc == 0)
7042 break;
7043 if (sleepFlag == CAN_SLEEP)
7044 msleep(100);
7045 else
7046 mdelay(100);
7047 }
7048 if (ii == 5)
7049 goto out;
7050
7051 rc = PrimeIocFifos(ioc);
7052 if (rc != 0)
7053 goto out;
7054
7055 rc = SendIocInit(ioc, sleepFlag);
7056 if (rc != 0)
7057 goto out;
7058
7059 rc = SendEventNotification(ioc, 1, sleepFlag);
7060 if (rc != 0)
7061 goto out;
7062
7063 if (ioc->hard_resets < -1)
7064 ioc->hard_resets++;
7065
7066 /*
7067 * At this point, we know soft reset succeeded.
7068 */
7069
7070 ioc->active = 1;
7071 CHIPREG_WRITE32(&ioc->chip->IntMask, MPI_HIM_DIM);
7072
7073 out:
7074 spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
7075 ioc->ioc_reset_in_progress = 0;
7076 ioc->taskmgmt_quiesce_io = 0;
7077 ioc->taskmgmt_in_progress = 0;
7078 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
7079
7080 if (ioc->active) { /* otherwise, hard reset coming */
7081 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
7082 if (MptResetHandlers[cb_idx])
7083 mpt_signal_reset(cb_idx, ioc,
7084 MPT_IOC_POST_RESET);
7085 }
7086 }
7087
7088 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT
7089 "SoftResetHandler: completed (%d seconds): %s\n",
7090 ioc->name, jiffies_to_msecs(jiffies - time_count)/1000,
7091 ((rc == 0) ? "SUCCESS" : "FAILED")));
7092
7093 return rc;
7094}
7095
7096/**
7097 * mpt_Soft_Hard_ResetHandler - Try less expensive reset
7098 * @ioc: Pointer to MPT_ADAPTER structure
7099 * @sleepFlag: Indicates if sleep or schedule must be called.
7100 *
7101 * Returns 0 for SUCCESS or -1 if FAILED.
7102 * Try for softreset first, only if it fails go for expensive
7103 * HardReset.
7104 **/
7105int
7106mpt_Soft_Hard_ResetHandler(MPT_ADAPTER *ioc, int sleepFlag) {
7107 int ret = -1;
7108
7109 ret = mpt_SoftResetHandler(ioc, sleepFlag);
7110 if (ret == 0)
7111 return ret;
7112 ret = mpt_HardResetHandler(ioc, sleepFlag);
7113 return ret;
7114}
7115EXPORT_SYMBOL(mpt_Soft_Hard_ResetHandler);
7116
7117/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
7118/*
7119 * Reset Handling
7120 */
7121/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
7122/**
7123 * mpt_HardResetHandler - Generic reset handler
7124 * @ioc: Pointer to MPT_ADAPTER structure
7125 * @sleepFlag: Indicates if sleep or schedule must be called.
7126 *
7127 * Issues SCSI Task Management call based on input arg values.
7128 * If TaskMgmt fails, returns associated SCSI request.
7129 *
7130 * Remark: _HardResetHandler can be invoked from an interrupt thread (timer)
7131 * or a non-interrupt thread. In the former, must not call schedule().
7132 *
7133 * Note: A return of -1 is a FATAL error case, as it means a
7134 * FW reload/initialization failed.
7135 *
7136 * Returns 0 for SUCCESS or -1 if FAILED.
7137 */
7138int
7139mpt_HardResetHandler(MPT_ADAPTER *ioc, int sleepFlag)
7140{
7141 int rc;
7142 u8 cb_idx;
7143 unsigned long flags;
7144 unsigned long time_count;
7145
7146 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT "HardResetHandler Entered!\n", ioc->name));
7147#ifdef MFCNT
7148 printk(MYIOC_s_INFO_FMT "HardResetHandler Entered!\n", ioc->name);
7149 printk("MF count 0x%x !\n", ioc->mfcnt);
7150#endif
7151 if (mpt_fwfault_debug)
7152 mpt_halt_firmware(ioc);
7153
7154 /* Reset the adapter. Prevent more than 1 call to
7155 * mpt_do_ioc_recovery at any instant in time.
7156 */
7157 spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
7158 if (ioc->ioc_reset_in_progress) {
7159 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
7160 ioc->wait_on_reset_completion = 1;
7161 do {
7162 ssleep(1);
7163 } while (ioc->ioc_reset_in_progress == 1);
7164 ioc->wait_on_reset_completion = 0;
7165 return ioc->reset_status;
7166 }
7167 if (ioc->wait_on_reset_completion) {
7168 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
7169 rc = 0;
7170 time_count = jiffies;
7171 goto exit;
7172 }
7173 ioc->ioc_reset_in_progress = 1;
7174 if (ioc->alt_ioc)
7175 ioc->alt_ioc->ioc_reset_in_progress = 1;
7176 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
7177
7178
7179 /* The SCSI driver needs to adjust timeouts on all current
7180 * commands prior to the diagnostic reset being issued.
7181 * Prevents timeouts occurring during a diagnostic reset...very bad.
7182 * For all other protocol drivers, this is a no-op.
7183 */
7184 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
7185 if (MptResetHandlers[cb_idx]) {
7186 mpt_signal_reset(cb_idx, ioc, MPT_IOC_SETUP_RESET);
7187 if (ioc->alt_ioc)
7188 mpt_signal_reset(cb_idx, ioc->alt_ioc,
7189 MPT_IOC_SETUP_RESET);
7190 }
7191 }
7192
7193 time_count = jiffies;
7194 rc = mpt_do_ioc_recovery(ioc, MPT_HOSTEVENT_IOC_RECOVER, sleepFlag);
7195 if (rc != 0) {
7196 printk(KERN_WARNING MYNAM
7197 ": WARNING - (%d) Cannot recover %s, doorbell=0x%08x\n",
7198 rc, ioc->name, mpt_GetIocState(ioc, 0));
7199 } else {
7200 if (ioc->hard_resets < -1)
7201 ioc->hard_resets++;
7202 }
7203
7204 spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
7205 ioc->ioc_reset_in_progress = 0;
7206 ioc->taskmgmt_quiesce_io = 0;
7207 ioc->taskmgmt_in_progress = 0;
7208 ioc->reset_status = rc;
7209 if (ioc->alt_ioc) {
7210 ioc->alt_ioc->ioc_reset_in_progress = 0;
7211 ioc->alt_ioc->taskmgmt_quiesce_io = 0;
7212 ioc->alt_ioc->taskmgmt_in_progress = 0;
7213 }
7214 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
7215
7216 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
7217 if (MptResetHandlers[cb_idx]) {
7218 mpt_signal_reset(cb_idx, ioc, MPT_IOC_POST_RESET);
7219 if (ioc->alt_ioc)
7220 mpt_signal_reset(cb_idx,
7221 ioc->alt_ioc, MPT_IOC_POST_RESET);
7222 }
7223 }
7224exit:
7225 dtmprintk(ioc,
7226 printk(MYIOC_s_DEBUG_FMT
7227 "HardResetHandler: completed (%d seconds): %s\n", ioc->name,
7228 jiffies_to_msecs(jiffies - time_count)/1000, ((rc == 0) ?
7229 "SUCCESS" : "FAILED")));
7230
7231 return rc;
7232}
7233
7234#ifdef CONFIG_FUSION_LOGGING
7235static void
7236mpt_display_event_info(MPT_ADAPTER *ioc, EventNotificationReply_t *pEventReply)
7237{
7238 char *ds = NULL;
7239 u32 evData0;
7240 int ii;
7241 u8 event;
7242 char *evStr = ioc->evStr;
7243
7244 event = le32_to_cpu(pEventReply->Event) & 0xFF;
7245 evData0 = le32_to_cpu(pEventReply->Data[0]);
7246
7247 switch(event) {
7248 case MPI_EVENT_NONE:
7249 ds = "None";
7250 break;
7251 case MPI_EVENT_LOG_DATA:
7252 ds = "Log Data";
7253 break;
7254 case MPI_EVENT_STATE_CHANGE:
7255 ds = "State Change";
7256 break;
7257 case MPI_EVENT_UNIT_ATTENTION:
7258 ds = "Unit Attention";
7259 break;
7260 case MPI_EVENT_IOC_BUS_RESET:
7261 ds = "IOC Bus Reset";
7262 break;
7263 case MPI_EVENT_EXT_BUS_RESET:
7264 ds = "External Bus Reset";
7265 break;
7266 case MPI_EVENT_RESCAN:
7267 ds = "Bus Rescan Event";
7268 break;
7269 case MPI_EVENT_LINK_STATUS_CHANGE:
7270 if (evData0 == MPI_EVENT_LINK_STATUS_FAILURE)
7271 ds = "Link Status(FAILURE) Change";
7272 else
7273 ds = "Link Status(ACTIVE) Change";
7274 break;
7275 case MPI_EVENT_LOOP_STATE_CHANGE:
7276 if (evData0 == MPI_EVENT_LOOP_STATE_CHANGE_LIP)
7277 ds = "Loop State(LIP) Change";
7278 else if (evData0 == MPI_EVENT_LOOP_STATE_CHANGE_LPE)
7279 ds = "Loop State(LPE) Change";
7280 else
7281 ds = "Loop State(LPB) Change";
7282 break;
7283 case MPI_EVENT_LOGOUT:
7284 ds = "Logout";
7285 break;
7286 case MPI_EVENT_EVENT_CHANGE:
7287 if (evData0)
7288 ds = "Events ON";
7289 else
7290 ds = "Events OFF";
7291 break;
7292 case MPI_EVENT_INTEGRATED_RAID:
7293 {
7294 u8 ReasonCode = (u8)(evData0 >> 16);
7295 switch (ReasonCode) {
7296 case MPI_EVENT_RAID_RC_VOLUME_CREATED :
7297 ds = "Integrated Raid: Volume Created";
7298 break;
7299 case MPI_EVENT_RAID_RC_VOLUME_DELETED :
7300 ds = "Integrated Raid: Volume Deleted";
7301 break;
7302 case MPI_EVENT_RAID_RC_VOLUME_SETTINGS_CHANGED :
7303 ds = "Integrated Raid: Volume Settings Changed";
7304 break;
7305 case MPI_EVENT_RAID_RC_VOLUME_STATUS_CHANGED :
7306 ds = "Integrated Raid: Volume Status Changed";
7307 break;
7308 case MPI_EVENT_RAID_RC_VOLUME_PHYSDISK_CHANGED :
7309 ds = "Integrated Raid: Volume Physdisk Changed";
7310 break;
7311 case MPI_EVENT_RAID_RC_PHYSDISK_CREATED :
7312 ds = "Integrated Raid: Physdisk Created";
7313 break;
7314 case MPI_EVENT_RAID_RC_PHYSDISK_DELETED :
7315 ds = "Integrated Raid: Physdisk Deleted";
7316 break;
7317 case MPI_EVENT_RAID_RC_PHYSDISK_SETTINGS_CHANGED :
7318 ds = "Integrated Raid: Physdisk Settings Changed";
7319 break;
7320 case MPI_EVENT_RAID_RC_PHYSDISK_STATUS_CHANGED :
7321 ds = "Integrated Raid: Physdisk Status Changed";
7322 break;
7323 case MPI_EVENT_RAID_RC_DOMAIN_VAL_NEEDED :
7324 ds = "Integrated Raid: Domain Validation Needed";
7325 break;
7326 case MPI_EVENT_RAID_RC_SMART_DATA :
7327 ds = "Integrated Raid; Smart Data";
7328 break;
7329 case MPI_EVENT_RAID_RC_REPLACE_ACTION_STARTED :
7330 ds = "Integrated Raid: Replace Action Started";
7331 break;
7332 default:
7333 ds = "Integrated Raid";
7334 break;
7335 }
7336 break;
7337 }
7338 case MPI_EVENT_SCSI_DEVICE_STATUS_CHANGE:
7339 ds = "SCSI Device Status Change";
7340 break;
7341 case MPI_EVENT_SAS_DEVICE_STATUS_CHANGE:
7342 {
7343 u8 id = (u8)(evData0);
7344 u8 channel = (u8)(evData0 >> 8);
7345 u8 ReasonCode = (u8)(evData0 >> 16);
7346 switch (ReasonCode) {
7347 case MPI_EVENT_SAS_DEV_STAT_RC_ADDED:
7348 snprintf(evStr, EVENT_DESCR_STR_SZ,
7349 "SAS Device Status Change: Added: "
7350 "id=%d channel=%d", id, channel);
7351 break;
7352 case MPI_EVENT_SAS_DEV_STAT_RC_NOT_RESPONDING:
7353 snprintf(evStr, EVENT_DESCR_STR_SZ,
7354 "SAS Device Status Change: Deleted: "
7355 "id=%d channel=%d", id, channel);
7356 break;
7357 case MPI_EVENT_SAS_DEV_STAT_RC_SMART_DATA:
7358 snprintf(evStr, EVENT_DESCR_STR_SZ,
7359 "SAS Device Status Change: SMART Data: "
7360 "id=%d channel=%d", id, channel);
7361 break;
7362 case MPI_EVENT_SAS_DEV_STAT_RC_NO_PERSIST_ADDED:
7363 snprintf(evStr, EVENT_DESCR_STR_SZ,
7364 "SAS Device Status Change: No Persistency: "
7365 "id=%d channel=%d", id, channel);
7366 break;
7367 case MPI_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED:
7368 snprintf(evStr, EVENT_DESCR_STR_SZ,
7369 "SAS Device Status Change: Unsupported Device "
7370 "Discovered : id=%d channel=%d", id, channel);
7371 break;
7372 case MPI_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET:
7373 snprintf(evStr, EVENT_DESCR_STR_SZ,
7374 "SAS Device Status Change: Internal Device "
7375 "Reset : id=%d channel=%d", id, channel);
7376 break;
7377 case MPI_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL:
7378 snprintf(evStr, EVENT_DESCR_STR_SZ,
7379 "SAS Device Status Change: Internal Task "
7380 "Abort : id=%d channel=%d", id, channel);
7381 break;
7382 case MPI_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL:
7383 snprintf(evStr, EVENT_DESCR_STR_SZ,
7384 "SAS Device Status Change: Internal Abort "
7385 "Task Set : id=%d channel=%d", id, channel);
7386 break;
7387 case MPI_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL:
7388 snprintf(evStr, EVENT_DESCR_STR_SZ,
7389 "SAS Device Status Change: Internal Clear "
7390 "Task Set : id=%d channel=%d", id, channel);
7391 break;
7392 case MPI_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL:
7393 snprintf(evStr, EVENT_DESCR_STR_SZ,
7394 "SAS Device Status Change: Internal Query "
7395 "Task : id=%d channel=%d", id, channel);
7396 break;
7397 default:
7398 snprintf(evStr, EVENT_DESCR_STR_SZ,
7399 "SAS Device Status Change: Unknown: "
7400 "id=%d channel=%d", id, channel);
7401 break;
7402 }
7403 break;
7404 }
7405 case MPI_EVENT_ON_BUS_TIMER_EXPIRED:
7406 ds = "Bus Timer Expired";
7407 break;
7408 case MPI_EVENT_QUEUE_FULL:
7409 {
7410 u16 curr_depth = (u16)(evData0 >> 16);
7411 u8 channel = (u8)(evData0 >> 8);
7412 u8 id = (u8)(evData0);
7413
7414 snprintf(evStr, EVENT_DESCR_STR_SZ,
7415 "Queue Full: channel=%d id=%d depth=%d",
7416 channel, id, curr_depth);
7417 break;
7418 }
7419 case MPI_EVENT_SAS_SES:
7420 ds = "SAS SES Event";
7421 break;
7422 case MPI_EVENT_PERSISTENT_TABLE_FULL:
7423 ds = "Persistent Table Full";
7424 break;
7425 case MPI_EVENT_SAS_PHY_LINK_STATUS:
7426 {
7427 u8 LinkRates = (u8)(evData0 >> 8);
7428 u8 PhyNumber = (u8)(evData0);
7429 LinkRates = (LinkRates & MPI_EVENT_SAS_PLS_LR_CURRENT_MASK) >>
7430 MPI_EVENT_SAS_PLS_LR_CURRENT_SHIFT;
7431 switch (LinkRates) {
7432 case MPI_EVENT_SAS_PLS_LR_RATE_UNKNOWN:
7433 snprintf(evStr, EVENT_DESCR_STR_SZ,
7434 "SAS PHY Link Status: Phy=%d:"
7435 " Rate Unknown",PhyNumber);
7436 break;
7437 case MPI_EVENT_SAS_PLS_LR_RATE_PHY_DISABLED:
7438 snprintf(evStr, EVENT_DESCR_STR_SZ,
7439 "SAS PHY Link Status: Phy=%d:"
7440 " Phy Disabled",PhyNumber);
7441 break;
7442 case MPI_EVENT_SAS_PLS_LR_RATE_FAILED_SPEED_NEGOTIATION:
7443 snprintf(evStr, EVENT_DESCR_STR_SZ,
7444 "SAS PHY Link Status: Phy=%d:"
7445 " Failed Speed Nego",PhyNumber);
7446 break;
7447 case MPI_EVENT_SAS_PLS_LR_RATE_SATA_OOB_COMPLETE:
7448 snprintf(evStr, EVENT_DESCR_STR_SZ,
7449 "SAS PHY Link Status: Phy=%d:"
7450 " Sata OOB Completed",PhyNumber);
7451 break;
7452 case MPI_EVENT_SAS_PLS_LR_RATE_1_5:
7453 snprintf(evStr, EVENT_DESCR_STR_SZ,
7454 "SAS PHY Link Status: Phy=%d:"
7455 " Rate 1.5 Gbps",PhyNumber);
7456 break;
7457 case MPI_EVENT_SAS_PLS_LR_RATE_3_0:
7458 snprintf(evStr, EVENT_DESCR_STR_SZ,
7459 "SAS PHY Link Status: Phy=%d:"
7460 " Rate 3.0 Gbps", PhyNumber);
7461 break;
7462 case MPI_EVENT_SAS_PLS_LR_RATE_6_0:
7463 snprintf(evStr, EVENT_DESCR_STR_SZ,
7464 "SAS PHY Link Status: Phy=%d:"
7465 " Rate 6.0 Gbps", PhyNumber);
7466 break;
7467 default:
7468 snprintf(evStr, EVENT_DESCR_STR_SZ,
7469 "SAS PHY Link Status: Phy=%d", PhyNumber);
7470 break;
7471 }
7472 break;
7473 }
7474 case MPI_EVENT_SAS_DISCOVERY_ERROR:
7475 ds = "SAS Discovery Error";
7476 break;
7477 case MPI_EVENT_IR_RESYNC_UPDATE:
7478 {
7479 u8 resync_complete = (u8)(evData0 >> 16);
7480 snprintf(evStr, EVENT_DESCR_STR_SZ,
7481 "IR Resync Update: Complete = %d:",resync_complete);
7482 break;
7483 }
7484 case MPI_EVENT_IR2:
7485 {
7486 u8 id = (u8)(evData0);
7487 u8 channel = (u8)(evData0 >> 8);
7488 u8 phys_num = (u8)(evData0 >> 24);
7489 u8 ReasonCode = (u8)(evData0 >> 16);
7490
7491 switch (ReasonCode) {
7492 case MPI_EVENT_IR2_RC_LD_STATE_CHANGED:
7493 snprintf(evStr, EVENT_DESCR_STR_SZ,
7494 "IR2: LD State Changed: "
7495 "id=%d channel=%d phys_num=%d",
7496 id, channel, phys_num);
7497 break;
7498 case MPI_EVENT_IR2_RC_PD_STATE_CHANGED:
7499 snprintf(evStr, EVENT_DESCR_STR_SZ,
7500 "IR2: PD State Changed "
7501 "id=%d channel=%d phys_num=%d",
7502 id, channel, phys_num);
7503 break;
7504 case MPI_EVENT_IR2_RC_BAD_BLOCK_TABLE_FULL:
7505 snprintf(evStr, EVENT_DESCR_STR_SZ,
7506 "IR2: Bad Block Table Full: "
7507 "id=%d channel=%d phys_num=%d",
7508 id, channel, phys_num);
7509 break;
7510 case MPI_EVENT_IR2_RC_PD_INSERTED:
7511 snprintf(evStr, EVENT_DESCR_STR_SZ,
7512 "IR2: PD Inserted: "
7513 "id=%d channel=%d phys_num=%d",
7514 id, channel, phys_num);
7515 break;
7516 case MPI_EVENT_IR2_RC_PD_REMOVED:
7517 snprintf(evStr, EVENT_DESCR_STR_SZ,
7518 "IR2: PD Removed: "
7519 "id=%d channel=%d phys_num=%d",
7520 id, channel, phys_num);
7521 break;
7522 case MPI_EVENT_IR2_RC_FOREIGN_CFG_DETECTED:
7523 snprintf(evStr, EVENT_DESCR_STR_SZ,
7524 "IR2: Foreign CFG Detected: "
7525 "id=%d channel=%d phys_num=%d",
7526 id, channel, phys_num);
7527 break;
7528 case MPI_EVENT_IR2_RC_REBUILD_MEDIUM_ERROR:
7529 snprintf(evStr, EVENT_DESCR_STR_SZ,
7530 "IR2: Rebuild Medium Error: "
7531 "id=%d channel=%d phys_num=%d",
7532 id, channel, phys_num);
7533 break;
7534 case MPI_EVENT_IR2_RC_DUAL_PORT_ADDED:
7535 snprintf(evStr, EVENT_DESCR_STR_SZ,
7536 "IR2: Dual Port Added: "
7537 "id=%d channel=%d phys_num=%d",
7538 id, channel, phys_num);
7539 break;
7540 case MPI_EVENT_IR2_RC_DUAL_PORT_REMOVED:
7541 snprintf(evStr, EVENT_DESCR_STR_SZ,
7542 "IR2: Dual Port Removed: "
7543 "id=%d channel=%d phys_num=%d",
7544 id, channel, phys_num);
7545 break;
7546 default:
7547 ds = "IR2";
7548 break;
7549 }
7550 break;
7551 }
7552 case MPI_EVENT_SAS_DISCOVERY:
7553 {
7554 if (evData0)
7555 ds = "SAS Discovery: Start";
7556 else
7557 ds = "SAS Discovery: Stop";
7558 break;
7559 }
7560 case MPI_EVENT_LOG_ENTRY_ADDED:
7561 ds = "SAS Log Entry Added";
7562 break;
7563
7564 case MPI_EVENT_SAS_BROADCAST_PRIMITIVE:
7565 {
7566 u8 phy_num = (u8)(evData0);
7567 u8 port_num = (u8)(evData0 >> 8);
7568 u8 port_width = (u8)(evData0 >> 16);
7569 u8 primitive = (u8)(evData0 >> 24);
7570 snprintf(evStr, EVENT_DESCR_STR_SZ,
7571 "SAS Broadcast Primitive: phy=%d port=%d "
7572 "width=%d primitive=0x%02x",
7573 phy_num, port_num, port_width, primitive);
7574 break;
7575 }
7576
7577 case MPI_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE:
7578 {
7579 u8 reason = (u8)(evData0);
7580
7581 switch (reason) {
7582 case MPI_EVENT_SAS_INIT_RC_ADDED:
7583 ds = "SAS Initiator Status Change: Added";
7584 break;
7585 case MPI_EVENT_SAS_INIT_RC_REMOVED:
7586 ds = "SAS Initiator Status Change: Deleted";
7587 break;
7588 default:
7589 ds = "SAS Initiator Status Change";
7590 break;
7591 }
7592 break;
7593 }
7594
7595 case MPI_EVENT_SAS_INIT_TABLE_OVERFLOW:
7596 {
7597 u8 max_init = (u8)(evData0);
7598 u8 current_init = (u8)(evData0 >> 8);
7599
7600 snprintf(evStr, EVENT_DESCR_STR_SZ,
7601 "SAS Initiator Device Table Overflow: max initiators=%02d "
7602 "current initiators=%02d",
7603 max_init, current_init);
7604 break;
7605 }
7606 case MPI_EVENT_SAS_SMP_ERROR:
7607 {
7608 u8 status = (u8)(evData0);
7609 u8 port_num = (u8)(evData0 >> 8);
7610 u8 result = (u8)(evData0 >> 16);
7611
7612 if (status == MPI_EVENT_SAS_SMP_FUNCTION_RESULT_VALID)
7613 snprintf(evStr, EVENT_DESCR_STR_SZ,
7614 "SAS SMP Error: port=%d result=0x%02x",
7615 port_num, result);
7616 else if (status == MPI_EVENT_SAS_SMP_CRC_ERROR)
7617 snprintf(evStr, EVENT_DESCR_STR_SZ,
7618 "SAS SMP Error: port=%d : CRC Error",
7619 port_num);
7620 else if (status == MPI_EVENT_SAS_SMP_TIMEOUT)
7621 snprintf(evStr, EVENT_DESCR_STR_SZ,
7622 "SAS SMP Error: port=%d : Timeout",
7623 port_num);
7624 else if (status == MPI_EVENT_SAS_SMP_NO_DESTINATION)
7625 snprintf(evStr, EVENT_DESCR_STR_SZ,
7626 "SAS SMP Error: port=%d : No Destination",
7627 port_num);
7628 else if (status == MPI_EVENT_SAS_SMP_BAD_DESTINATION)
7629 snprintf(evStr, EVENT_DESCR_STR_SZ,
7630 "SAS SMP Error: port=%d : Bad Destination",
7631 port_num);
7632 else
7633 snprintf(evStr, EVENT_DESCR_STR_SZ,
7634 "SAS SMP Error: port=%d : status=0x%02x",
7635 port_num, status);
7636 break;
7637 }
7638
7639 case MPI_EVENT_SAS_EXPANDER_STATUS_CHANGE:
7640 {
7641 u8 reason = (u8)(evData0);
7642
7643 switch (reason) {
7644 case MPI_EVENT_SAS_EXP_RC_ADDED:
7645 ds = "Expander Status Change: Added";
7646 break;
7647 case MPI_EVENT_SAS_EXP_RC_NOT_RESPONDING:
7648 ds = "Expander Status Change: Deleted";
7649 break;
7650 default:
7651 ds = "Expander Status Change";
7652 break;
7653 }
7654 break;
7655 }
7656
7657 /*
7658 * MPT base "custom" events may be added here...
7659 */
7660 default:
7661 ds = "Unknown";
7662 break;
7663 }
7664 if (ds)
7665 strscpy(evStr, ds, EVENT_DESCR_STR_SZ);
7666
7667
7668 devtprintk(ioc, printk(MYIOC_s_DEBUG_FMT
7669 "MPT event:(%02Xh) : %s\n",
7670 ioc->name, event, evStr));
7671
7672 devtverboseprintk(ioc, printk(KERN_DEBUG MYNAM
7673 ": Event data:\n"));
7674 for (ii = 0; ii < le16_to_cpu(pEventReply->EventDataLength); ii++)
7675 devtverboseprintk(ioc, printk(" %08x",
7676 le32_to_cpu(pEventReply->Data[ii])));
7677 devtverboseprintk(ioc, printk(KERN_DEBUG "\n"));
7678}
7679#endif
7680/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
7681/**
7682 * ProcessEventNotification - Route EventNotificationReply to all event handlers
7683 * @ioc: Pointer to MPT_ADAPTER structure
7684 * @pEventReply: Pointer to EventNotification reply frame
7685 * @evHandlers: Pointer to integer, number of event handlers
7686 *
7687 * Routes a received EventNotificationReply to all currently registered
7688 * event handlers.
7689 * Returns sum of event handlers return values.
7690 */
7691static int
7692ProcessEventNotification(MPT_ADAPTER *ioc, EventNotificationReply_t *pEventReply, int *evHandlers)
7693{
7694 u16 evDataLen;
7695 u32 evData0 = 0;
7696 int ii;
7697 u8 cb_idx;
7698 int r = 0;
7699 int handlers = 0;
7700 u8 event;
7701
7702 /*
7703 * Do platform normalization of values
7704 */
7705 event = le32_to_cpu(pEventReply->Event) & 0xFF;
7706 evDataLen = le16_to_cpu(pEventReply->EventDataLength);
7707 if (evDataLen) {
7708 evData0 = le32_to_cpu(pEventReply->Data[0]);
7709 }
7710
7711#ifdef CONFIG_FUSION_LOGGING
7712 if (evDataLen)
7713 mpt_display_event_info(ioc, pEventReply);
7714#endif
7715
7716 /*
7717 * Do general / base driver event processing
7718 */
7719 switch(event) {
7720 case MPI_EVENT_EVENT_CHANGE: /* 0A */
7721 if (evDataLen) {
7722 u8 evState = evData0 & 0xFF;
7723
7724 /* CHECKME! What if evState unexpectedly says OFF (0)? */
7725
7726 /* Update EventState field in cached IocFacts */
7727 if (ioc->facts.Function) {
7728 ioc->facts.EventState = evState;
7729 }
7730 }
7731 break;
7732 case MPI_EVENT_INTEGRATED_RAID:
7733 mptbase_raid_process_event_data(ioc,
7734 (MpiEventDataRaid_t *)pEventReply->Data);
7735 break;
7736 default:
7737 break;
7738 }
7739
7740 /*
7741 * Should this event be logged? Events are written sequentially.
7742 * When buffer is full, start again at the top.
7743 */
7744 if (ioc->events && (ioc->eventTypes & ( 1 << event))) {
7745 int idx;
7746
7747 idx = ioc->eventContext % MPTCTL_EVENT_LOG_SIZE;
7748
7749 ioc->events[idx].event = event;
7750 ioc->events[idx].eventContext = ioc->eventContext;
7751
7752 for (ii = 0; ii < 2; ii++) {
7753 if (ii < evDataLen)
7754 ioc->events[idx].data[ii] = le32_to_cpu(pEventReply->Data[ii]);
7755 else
7756 ioc->events[idx].data[ii] = 0;
7757 }
7758
7759 ioc->eventContext++;
7760 }
7761
7762
7763 /*
7764 * Call each currently registered protocol event handler.
7765 */
7766 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
7767 if (MptEvHandlers[cb_idx]) {
7768 devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT
7769 "Routing Event to event handler #%d\n",
7770 ioc->name, cb_idx));
7771 r += (*(MptEvHandlers[cb_idx]))(ioc, pEventReply);
7772 handlers++;
7773 }
7774 }
7775 /* FIXME? Examine results here? */
7776
7777 /*
7778 * If needed, send (a single) EventAck.
7779 */
7780 if (pEventReply->AckRequired == MPI_EVENT_NOTIFICATION_ACK_REQUIRED) {
7781 devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT
7782 "EventAck required\n",ioc->name));
7783 if ((ii = SendEventAck(ioc, pEventReply)) != 0) {
7784 devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT "SendEventAck returned %d\n",
7785 ioc->name, ii));
7786 }
7787 }
7788
7789 *evHandlers = handlers;
7790 return r;
7791}
7792
7793/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
7794/**
7795 * mpt_fc_log_info - Log information returned from Fibre Channel IOC.
7796 * @ioc: Pointer to MPT_ADAPTER structure
7797 * @log_info: U32 LogInfo reply word from the IOC
7798 *
7799 * Refer to lsi/mpi_log_fc.h.
7800 */
7801static void
7802mpt_fc_log_info(MPT_ADAPTER *ioc, u32 log_info)
7803{
7804 char *desc = "unknown";
7805
7806 switch (log_info & 0xFF000000) {
7807 case MPI_IOCLOGINFO_FC_INIT_BASE:
7808 desc = "FCP Initiator";
7809 break;
7810 case MPI_IOCLOGINFO_FC_TARGET_BASE:
7811 desc = "FCP Target";
7812 break;
7813 case MPI_IOCLOGINFO_FC_LAN_BASE:
7814 desc = "LAN";
7815 break;
7816 case MPI_IOCLOGINFO_FC_MSG_BASE:
7817 desc = "MPI Message Layer";
7818 break;
7819 case MPI_IOCLOGINFO_FC_LINK_BASE:
7820 desc = "FC Link";
7821 break;
7822 case MPI_IOCLOGINFO_FC_CTX_BASE:
7823 desc = "Context Manager";
7824 break;
7825 case MPI_IOCLOGINFO_FC_INVALID_FIELD_BYTE_OFFSET:
7826 desc = "Invalid Field Offset";
7827 break;
7828 case MPI_IOCLOGINFO_FC_STATE_CHANGE:
7829 desc = "State Change Info";
7830 break;
7831 }
7832
7833 printk(MYIOC_s_INFO_FMT "LogInfo(0x%08x): SubClass={%s}, Value=(0x%06x)\n",
7834 ioc->name, log_info, desc, (log_info & 0xFFFFFF));
7835}
7836
7837/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
7838/**
7839 * mpt_spi_log_info - Log information returned from SCSI Parallel IOC.
7840 * @ioc: Pointer to MPT_ADAPTER structure
7841 * @log_info: U32 LogInfo word from the IOC
7842 *
7843 * Refer to lsi/sp_log.h.
7844 */
7845static void
7846mpt_spi_log_info(MPT_ADAPTER *ioc, u32 log_info)
7847{
7848 u32 info = log_info & 0x00FF0000;
7849 char *desc = "unknown";
7850
7851 switch (info) {
7852 case 0x00010000:
7853 desc = "bug! MID not found";
7854 break;
7855
7856 case 0x00020000:
7857 desc = "Parity Error";
7858 break;
7859
7860 case 0x00030000:
7861 desc = "ASYNC Outbound Overrun";
7862 break;
7863
7864 case 0x00040000:
7865 desc = "SYNC Offset Error";
7866 break;
7867
7868 case 0x00050000:
7869 desc = "BM Change";
7870 break;
7871
7872 case 0x00060000:
7873 desc = "Msg In Overflow";
7874 break;
7875
7876 case 0x00070000:
7877 desc = "DMA Error";
7878 break;
7879
7880 case 0x00080000:
7881 desc = "Outbound DMA Overrun";
7882 break;
7883
7884 case 0x00090000:
7885 desc = "Task Management";
7886 break;
7887
7888 case 0x000A0000:
7889 desc = "Device Problem";
7890 break;
7891
7892 case 0x000B0000:
7893 desc = "Invalid Phase Change";
7894 break;
7895
7896 case 0x000C0000:
7897 desc = "Untagged Table Size";
7898 break;
7899
7900 }
7901
7902 printk(MYIOC_s_INFO_FMT "LogInfo(0x%08x): F/W: %s\n", ioc->name, log_info, desc);
7903}
7904
7905/* strings for sas loginfo */
7906 static char *originator_str[] = {
7907 "IOP", /* 00h */
7908 "PL", /* 01h */
7909 "IR" /* 02h */
7910 };
7911 static char *iop_code_str[] = {
7912 NULL, /* 00h */
7913 "Invalid SAS Address", /* 01h */
7914 NULL, /* 02h */
7915 "Invalid Page", /* 03h */
7916 "Diag Message Error", /* 04h */
7917 "Task Terminated", /* 05h */
7918 "Enclosure Management", /* 06h */
7919 "Target Mode" /* 07h */
7920 };
7921 static char *pl_code_str[] = {
7922 NULL, /* 00h */
7923 "Open Failure", /* 01h */
7924 "Invalid Scatter Gather List", /* 02h */
7925 "Wrong Relative Offset or Frame Length", /* 03h */
7926 "Frame Transfer Error", /* 04h */
7927 "Transmit Frame Connected Low", /* 05h */
7928 "SATA Non-NCQ RW Error Bit Set", /* 06h */
7929 "SATA Read Log Receive Data Error", /* 07h */
7930 "SATA NCQ Fail All Commands After Error", /* 08h */
7931 "SATA Error in Receive Set Device Bit FIS", /* 09h */
7932 "Receive Frame Invalid Message", /* 0Ah */
7933 "Receive Context Message Valid Error", /* 0Bh */
7934 "Receive Frame Current Frame Error", /* 0Ch */
7935 "SATA Link Down", /* 0Dh */
7936 "Discovery SATA Init W IOS", /* 0Eh */
7937 "Config Invalid Page", /* 0Fh */
7938 "Discovery SATA Init Timeout", /* 10h */
7939 "Reset", /* 11h */
7940 "Abort", /* 12h */
7941 "IO Not Yet Executed", /* 13h */
7942 "IO Executed", /* 14h */
7943 "Persistent Reservation Out Not Affiliation "
7944 "Owner", /* 15h */
7945 "Open Transmit DMA Abort", /* 16h */
7946 "IO Device Missing Delay Retry", /* 17h */
7947 "IO Cancelled Due to Receive Error", /* 18h */
7948 NULL, /* 19h */
7949 NULL, /* 1Ah */
7950 NULL, /* 1Bh */
7951 NULL, /* 1Ch */
7952 NULL, /* 1Dh */
7953 NULL, /* 1Eh */
7954 NULL, /* 1Fh */
7955 "Enclosure Management" /* 20h */
7956 };
7957 static char *ir_code_str[] = {
7958 "Raid Action Error", /* 00h */
7959 NULL, /* 00h */
7960 NULL, /* 01h */
7961 NULL, /* 02h */
7962 NULL, /* 03h */
7963 NULL, /* 04h */
7964 NULL, /* 05h */
7965 NULL, /* 06h */
7966 NULL /* 07h */
7967 };
7968 static char *raid_sub_code_str[] = {
7969 NULL, /* 00h */
7970 "Volume Creation Failed: Data Passed too "
7971 "Large", /* 01h */
7972 "Volume Creation Failed: Duplicate Volumes "
7973 "Attempted", /* 02h */
7974 "Volume Creation Failed: Max Number "
7975 "Supported Volumes Exceeded", /* 03h */
7976 "Volume Creation Failed: DMA Error", /* 04h */
7977 "Volume Creation Failed: Invalid Volume Type", /* 05h */
7978 "Volume Creation Failed: Error Reading "
7979 "MFG Page 4", /* 06h */
7980 "Volume Creation Failed: Creating Internal "
7981 "Structures", /* 07h */
7982 NULL, /* 08h */
7983 NULL, /* 09h */
7984 NULL, /* 0Ah */
7985 NULL, /* 0Bh */
7986 NULL, /* 0Ch */
7987 NULL, /* 0Dh */
7988 NULL, /* 0Eh */
7989 NULL, /* 0Fh */
7990 "Activation failed: Already Active Volume", /* 10h */
7991 "Activation failed: Unsupported Volume Type", /* 11h */
7992 "Activation failed: Too Many Active Volumes", /* 12h */
7993 "Activation failed: Volume ID in Use", /* 13h */
7994 "Activation failed: Reported Failure", /* 14h */
7995 "Activation failed: Importing a Volume", /* 15h */
7996 NULL, /* 16h */
7997 NULL, /* 17h */
7998 NULL, /* 18h */
7999 NULL, /* 19h */
8000 NULL, /* 1Ah */
8001 NULL, /* 1Bh */
8002 NULL, /* 1Ch */
8003 NULL, /* 1Dh */
8004 NULL, /* 1Eh */
8005 NULL, /* 1Fh */
8006 "Phys Disk failed: Too Many Phys Disks", /* 20h */
8007 "Phys Disk failed: Data Passed too Large", /* 21h */
8008 "Phys Disk failed: DMA Error", /* 22h */
8009 "Phys Disk failed: Invalid <channel:id>", /* 23h */
8010 "Phys Disk failed: Creating Phys Disk Config "
8011 "Page", /* 24h */
8012 NULL, /* 25h */
8013 NULL, /* 26h */
8014 NULL, /* 27h */
8015 NULL, /* 28h */
8016 NULL, /* 29h */
8017 NULL, /* 2Ah */
8018 NULL, /* 2Bh */
8019 NULL, /* 2Ch */
8020 NULL, /* 2Dh */
8021 NULL, /* 2Eh */
8022 NULL, /* 2Fh */
8023 "Compatibility Error: IR Disabled", /* 30h */
8024 "Compatibility Error: Inquiry Command Failed", /* 31h */
8025 "Compatibility Error: Device not Direct Access "
8026 "Device ", /* 32h */
8027 "Compatibility Error: Removable Device Found", /* 33h */
8028 "Compatibility Error: Device SCSI Version not "
8029 "2 or Higher", /* 34h */
8030 "Compatibility Error: SATA Device, 48 BIT LBA "
8031 "not Supported", /* 35h */
8032 "Compatibility Error: Device doesn't have "
8033 "512 Byte Block Sizes", /* 36h */
8034 "Compatibility Error: Volume Type Check Failed", /* 37h */
8035 "Compatibility Error: Volume Type is "
8036 "Unsupported by FW", /* 38h */
8037 "Compatibility Error: Disk Drive too Small for "
8038 "use in Volume", /* 39h */
8039 "Compatibility Error: Phys Disk for Create "
8040 "Volume not Found", /* 3Ah */
8041 "Compatibility Error: Too Many or too Few "
8042 "Disks for Volume Type", /* 3Bh */
8043 "Compatibility Error: Disk stripe Sizes "
8044 "Must be 64KB", /* 3Ch */
8045 "Compatibility Error: IME Size Limited to < 2TB", /* 3Dh */
8046 };
8047
8048/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
8049/**
8050 * mpt_sas_log_info - Log information returned from SAS IOC.
8051 * @ioc: Pointer to MPT_ADAPTER structure
8052 * @log_info: U32 LogInfo reply word from the IOC
8053 * @cb_idx: callback function's handle
8054 *
8055 * Refer to lsi/mpi_log_sas.h.
8056 **/
8057static void
8058mpt_sas_log_info(MPT_ADAPTER *ioc, u32 log_info, u8 cb_idx)
8059{
8060 union loginfo_type {
8061 u32 loginfo;
8062 struct {
8063 u32 subcode:16;
8064 u32 code:8;
8065 u32 originator:4;
8066 u32 bus_type:4;
8067 } dw;
8068 };
8069 union loginfo_type sas_loginfo;
8070 char *originator_desc = NULL;
8071 char *code_desc = NULL;
8072 char *sub_code_desc = NULL;
8073
8074 sas_loginfo.loginfo = log_info;
8075 if ((sas_loginfo.dw.bus_type != 3 /*SAS*/) &&
8076 (sas_loginfo.dw.originator < ARRAY_SIZE(originator_str)))
8077 return;
8078
8079 originator_desc = originator_str[sas_loginfo.dw.originator];
8080
8081 switch (sas_loginfo.dw.originator) {
8082
8083 case 0: /* IOP */
8084 if (sas_loginfo.dw.code <
8085 ARRAY_SIZE(iop_code_str))
8086 code_desc = iop_code_str[sas_loginfo.dw.code];
8087 break;
8088 case 1: /* PL */
8089 if (sas_loginfo.dw.code <
8090 ARRAY_SIZE(pl_code_str))
8091 code_desc = pl_code_str[sas_loginfo.dw.code];
8092 break;
8093 case 2: /* IR */
8094 if (sas_loginfo.dw.code >=
8095 ARRAY_SIZE(ir_code_str))
8096 break;
8097 code_desc = ir_code_str[sas_loginfo.dw.code];
8098 if (sas_loginfo.dw.subcode >=
8099 ARRAY_SIZE(raid_sub_code_str))
8100 break;
8101 if (sas_loginfo.dw.code == 0)
8102 sub_code_desc =
8103 raid_sub_code_str[sas_loginfo.dw.subcode];
8104 break;
8105 default:
8106 return;
8107 }
8108
8109 if (sub_code_desc != NULL)
8110 printk(MYIOC_s_INFO_FMT
8111 "LogInfo(0x%08x): Originator={%s}, Code={%s},"
8112 " SubCode={%s} cb_idx %s\n",
8113 ioc->name, log_info, originator_desc, code_desc,
8114 sub_code_desc, MptCallbacksName[cb_idx]);
8115 else if (code_desc != NULL)
8116 printk(MYIOC_s_INFO_FMT
8117 "LogInfo(0x%08x): Originator={%s}, Code={%s},"
8118 " SubCode(0x%04x) cb_idx %s\n",
8119 ioc->name, log_info, originator_desc, code_desc,
8120 sas_loginfo.dw.subcode, MptCallbacksName[cb_idx]);
8121 else
8122 printk(MYIOC_s_INFO_FMT
8123 "LogInfo(0x%08x): Originator={%s}, Code=(0x%02x),"
8124 " SubCode(0x%04x) cb_idx %s\n",
8125 ioc->name, log_info, originator_desc,
8126 sas_loginfo.dw.code, sas_loginfo.dw.subcode,
8127 MptCallbacksName[cb_idx]);
8128}
8129
8130/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
8131/**
8132 * mpt_iocstatus_info_config - IOCSTATUS information for config pages
8133 * @ioc: Pointer to MPT_ADAPTER structure
8134 * @ioc_status: U32 IOCStatus word from IOC
8135 * @mf: Pointer to MPT request frame
8136 *
8137 * Refer to lsi/mpi.h.
8138 **/
8139static void
8140mpt_iocstatus_info_config(MPT_ADAPTER *ioc, u32 ioc_status, MPT_FRAME_HDR *mf)
8141{
8142 Config_t *pReq = (Config_t *)mf;
8143 char extend_desc[EVENT_DESCR_STR_SZ];
8144 char *desc = NULL;
8145 u32 form;
8146 u8 page_type;
8147
8148 if (pReq->Header.PageType == MPI_CONFIG_PAGETYPE_EXTENDED)
8149 page_type = pReq->ExtPageType;
8150 else
8151 page_type = pReq->Header.PageType;
8152
8153 /*
8154 * ignore invalid page messages for GET_NEXT_HANDLE
8155 */
8156 form = le32_to_cpu(pReq->PageAddress);
8157 if (ioc_status == MPI_IOCSTATUS_CONFIG_INVALID_PAGE) {
8158 if (page_type == MPI_CONFIG_EXTPAGETYPE_SAS_DEVICE ||
8159 page_type == MPI_CONFIG_EXTPAGETYPE_SAS_EXPANDER ||
8160 page_type == MPI_CONFIG_EXTPAGETYPE_ENCLOSURE) {
8161 if ((form >> MPI_SAS_DEVICE_PGAD_FORM_SHIFT) ==
8162 MPI_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE)
8163 return;
8164 }
8165 if (page_type == MPI_CONFIG_PAGETYPE_FC_DEVICE)
8166 if ((form & MPI_FC_DEVICE_PGAD_FORM_MASK) ==
8167 MPI_FC_DEVICE_PGAD_FORM_NEXT_DID)
8168 return;
8169 }
8170
8171 snprintf(extend_desc, EVENT_DESCR_STR_SZ,
8172 "type=%02Xh, page=%02Xh, action=%02Xh, form=%08Xh",
8173 page_type, pReq->Header.PageNumber, pReq->Action, form);
8174
8175 switch (ioc_status) {
8176
8177 case MPI_IOCSTATUS_CONFIG_INVALID_ACTION: /* 0x0020 */
8178 desc = "Config Page Invalid Action";
8179 break;
8180
8181 case MPI_IOCSTATUS_CONFIG_INVALID_TYPE: /* 0x0021 */
8182 desc = "Config Page Invalid Type";
8183 break;
8184
8185 case MPI_IOCSTATUS_CONFIG_INVALID_PAGE: /* 0x0022 */
8186 desc = "Config Page Invalid Page";
8187 break;
8188
8189 case MPI_IOCSTATUS_CONFIG_INVALID_DATA: /* 0x0023 */
8190 desc = "Config Page Invalid Data";
8191 break;
8192
8193 case MPI_IOCSTATUS_CONFIG_NO_DEFAULTS: /* 0x0024 */
8194 desc = "Config Page No Defaults";
8195 break;
8196
8197 case MPI_IOCSTATUS_CONFIG_CANT_COMMIT: /* 0x0025 */
8198 desc = "Config Page Can't Commit";
8199 break;
8200 }
8201
8202 if (!desc)
8203 return;
8204
8205 dreplyprintk(ioc, printk(MYIOC_s_DEBUG_FMT "IOCStatus(0x%04X): %s: %s\n",
8206 ioc->name, ioc_status, desc, extend_desc));
8207}
8208
8209/**
8210 * mpt_iocstatus_info - IOCSTATUS information returned from IOC.
8211 * @ioc: Pointer to MPT_ADAPTER structure
8212 * @ioc_status: U32 IOCStatus word from IOC
8213 * @mf: Pointer to MPT request frame
8214 *
8215 * Refer to lsi/mpi.h.
8216 **/
8217static void
8218mpt_iocstatus_info(MPT_ADAPTER *ioc, u32 ioc_status, MPT_FRAME_HDR *mf)
8219{
8220 u32 status = ioc_status & MPI_IOCSTATUS_MASK;
8221 char *desc = NULL;
8222
8223 switch (status) {
8224
8225/****************************************************************************/
8226/* Common IOCStatus values for all replies */
8227/****************************************************************************/
8228
8229 case MPI_IOCSTATUS_INVALID_FUNCTION: /* 0x0001 */
8230 desc = "Invalid Function";
8231 break;
8232
8233 case MPI_IOCSTATUS_BUSY: /* 0x0002 */
8234 desc = "Busy";
8235 break;
8236
8237 case MPI_IOCSTATUS_INVALID_SGL: /* 0x0003 */
8238 desc = "Invalid SGL";
8239 break;
8240
8241 case MPI_IOCSTATUS_INTERNAL_ERROR: /* 0x0004 */
8242 desc = "Internal Error";
8243 break;
8244
8245 case MPI_IOCSTATUS_RESERVED: /* 0x0005 */
8246 desc = "Reserved";
8247 break;
8248
8249 case MPI_IOCSTATUS_INSUFFICIENT_RESOURCES: /* 0x0006 */
8250 desc = "Insufficient Resources";
8251 break;
8252
8253 case MPI_IOCSTATUS_INVALID_FIELD: /* 0x0007 */
8254 desc = "Invalid Field";
8255 break;
8256
8257 case MPI_IOCSTATUS_INVALID_STATE: /* 0x0008 */
8258 desc = "Invalid State";
8259 break;
8260
8261/****************************************************************************/
8262/* Config IOCStatus values */
8263/****************************************************************************/
8264
8265 case MPI_IOCSTATUS_CONFIG_INVALID_ACTION: /* 0x0020 */
8266 case MPI_IOCSTATUS_CONFIG_INVALID_TYPE: /* 0x0021 */
8267 case MPI_IOCSTATUS_CONFIG_INVALID_PAGE: /* 0x0022 */
8268 case MPI_IOCSTATUS_CONFIG_INVALID_DATA: /* 0x0023 */
8269 case MPI_IOCSTATUS_CONFIG_NO_DEFAULTS: /* 0x0024 */
8270 case MPI_IOCSTATUS_CONFIG_CANT_COMMIT: /* 0x0025 */
8271 mpt_iocstatus_info_config(ioc, status, mf);
8272 break;
8273
8274/****************************************************************************/
8275/* SCSIIO Reply (SPI, FCP, SAS) initiator values */
8276/* */
8277/* Look at mptscsih_iocstatus_info_scsiio in mptscsih.c */
8278/* */
8279/****************************************************************************/
8280
8281 case MPI_IOCSTATUS_SCSI_RECOVERED_ERROR: /* 0x0040 */
8282 case MPI_IOCSTATUS_SCSI_DATA_UNDERRUN: /* 0x0045 */
8283 case MPI_IOCSTATUS_SCSI_INVALID_BUS: /* 0x0041 */
8284 case MPI_IOCSTATUS_SCSI_INVALID_TARGETID: /* 0x0042 */
8285 case MPI_IOCSTATUS_SCSI_DEVICE_NOT_THERE: /* 0x0043 */
8286 case MPI_IOCSTATUS_SCSI_DATA_OVERRUN: /* 0x0044 */
8287 case MPI_IOCSTATUS_SCSI_IO_DATA_ERROR: /* 0x0046 */
8288 case MPI_IOCSTATUS_SCSI_PROTOCOL_ERROR: /* 0x0047 */
8289 case MPI_IOCSTATUS_SCSI_TASK_TERMINATED: /* 0x0048 */
8290 case MPI_IOCSTATUS_SCSI_RESIDUAL_MISMATCH: /* 0x0049 */
8291 case MPI_IOCSTATUS_SCSI_TASK_MGMT_FAILED: /* 0x004A */
8292 case MPI_IOCSTATUS_SCSI_IOC_TERMINATED: /* 0x004B */
8293 case MPI_IOCSTATUS_SCSI_EXT_TERMINATED: /* 0x004C */
8294 break;
8295
8296/****************************************************************************/
8297/* SCSI Target values */
8298/****************************************************************************/
8299
8300 case MPI_IOCSTATUS_TARGET_PRIORITY_IO: /* 0x0060 */
8301 desc = "Target: Priority IO";
8302 break;
8303
8304 case MPI_IOCSTATUS_TARGET_INVALID_PORT: /* 0x0061 */
8305 desc = "Target: Invalid Port";
8306 break;
8307
8308 case MPI_IOCSTATUS_TARGET_INVALID_IO_INDEX: /* 0x0062 */
8309 desc = "Target Invalid IO Index:";
8310 break;
8311
8312 case MPI_IOCSTATUS_TARGET_ABORTED: /* 0x0063 */
8313 desc = "Target: Aborted";
8314 break;
8315
8316 case MPI_IOCSTATUS_TARGET_NO_CONN_RETRYABLE: /* 0x0064 */
8317 desc = "Target: No Conn Retryable";
8318 break;
8319
8320 case MPI_IOCSTATUS_TARGET_NO_CONNECTION: /* 0x0065 */
8321 desc = "Target: No Connection";
8322 break;
8323
8324 case MPI_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH: /* 0x006A */
8325 desc = "Target: Transfer Count Mismatch";
8326 break;
8327
8328 case MPI_IOCSTATUS_TARGET_STS_DATA_NOT_SENT: /* 0x006B */
8329 desc = "Target: STS Data not Sent";
8330 break;
8331
8332 case MPI_IOCSTATUS_TARGET_DATA_OFFSET_ERROR: /* 0x006D */
8333 desc = "Target: Data Offset Error";
8334 break;
8335
8336 case MPI_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA: /* 0x006E */
8337 desc = "Target: Too Much Write Data";
8338 break;
8339
8340 case MPI_IOCSTATUS_TARGET_IU_TOO_SHORT: /* 0x006F */
8341 desc = "Target: IU Too Short";
8342 break;
8343
8344 case MPI_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT: /* 0x0070 */
8345 desc = "Target: ACK NAK Timeout";
8346 break;
8347
8348 case MPI_IOCSTATUS_TARGET_NAK_RECEIVED: /* 0x0071 */
8349 desc = "Target: Nak Received";
8350 break;
8351
8352/****************************************************************************/
8353/* Fibre Channel Direct Access values */
8354/****************************************************************************/
8355
8356 case MPI_IOCSTATUS_FC_ABORTED: /* 0x0066 */
8357 desc = "FC: Aborted";
8358 break;
8359
8360 case MPI_IOCSTATUS_FC_RX_ID_INVALID: /* 0x0067 */
8361 desc = "FC: RX ID Invalid";
8362 break;
8363
8364 case MPI_IOCSTATUS_FC_DID_INVALID: /* 0x0068 */
8365 desc = "FC: DID Invalid";
8366 break;
8367
8368 case MPI_IOCSTATUS_FC_NODE_LOGGED_OUT: /* 0x0069 */
8369 desc = "FC: Node Logged Out";
8370 break;
8371
8372 case MPI_IOCSTATUS_FC_EXCHANGE_CANCELED: /* 0x006C */
8373 desc = "FC: Exchange Canceled";
8374 break;
8375
8376/****************************************************************************/
8377/* LAN values */
8378/****************************************************************************/
8379
8380 case MPI_IOCSTATUS_LAN_DEVICE_NOT_FOUND: /* 0x0080 */
8381 desc = "LAN: Device not Found";
8382 break;
8383
8384 case MPI_IOCSTATUS_LAN_DEVICE_FAILURE: /* 0x0081 */
8385 desc = "LAN: Device Failure";
8386 break;
8387
8388 case MPI_IOCSTATUS_LAN_TRANSMIT_ERROR: /* 0x0082 */
8389 desc = "LAN: Transmit Error";
8390 break;
8391
8392 case MPI_IOCSTATUS_LAN_TRANSMIT_ABORTED: /* 0x0083 */
8393 desc = "LAN: Transmit Aborted";
8394 break;
8395
8396 case MPI_IOCSTATUS_LAN_RECEIVE_ERROR: /* 0x0084 */
8397 desc = "LAN: Receive Error";
8398 break;
8399
8400 case MPI_IOCSTATUS_LAN_RECEIVE_ABORTED: /* 0x0085 */
8401 desc = "LAN: Receive Aborted";
8402 break;
8403
8404 case MPI_IOCSTATUS_LAN_PARTIAL_PACKET: /* 0x0086 */
8405 desc = "LAN: Partial Packet";
8406 break;
8407
8408 case MPI_IOCSTATUS_LAN_CANCELED: /* 0x0087 */
8409 desc = "LAN: Canceled";
8410 break;
8411
8412/****************************************************************************/
8413/* Serial Attached SCSI values */
8414/****************************************************************************/
8415
8416 case MPI_IOCSTATUS_SAS_SMP_REQUEST_FAILED: /* 0x0090 */
8417 desc = "SAS: SMP Request Failed";
8418 break;
8419
8420 case MPI_IOCSTATUS_SAS_SMP_DATA_OVERRUN: /* 0x0090 */
8421 desc = "SAS: SMP Data Overrun";
8422 break;
8423
8424 default:
8425 desc = "Others";
8426 break;
8427 }
8428
8429 if (!desc)
8430 return;
8431
8432 dreplyprintk(ioc, printk(MYIOC_s_DEBUG_FMT "IOCStatus(0x%04X): %s\n",
8433 ioc->name, status, desc));
8434}
8435
8436/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
8437EXPORT_SYMBOL(mpt_attach);
8438EXPORT_SYMBOL(mpt_detach);
8439#ifdef CONFIG_PM
8440EXPORT_SYMBOL(mpt_resume);
8441EXPORT_SYMBOL(mpt_suspend);
8442#endif
8443EXPORT_SYMBOL(ioc_list);
8444EXPORT_SYMBOL(mpt_register);
8445EXPORT_SYMBOL(mpt_deregister);
8446EXPORT_SYMBOL(mpt_event_register);
8447EXPORT_SYMBOL(mpt_event_deregister);
8448EXPORT_SYMBOL(mpt_reset_register);
8449EXPORT_SYMBOL(mpt_reset_deregister);
8450EXPORT_SYMBOL(mpt_device_driver_register);
8451EXPORT_SYMBOL(mpt_device_driver_deregister);
8452EXPORT_SYMBOL(mpt_get_msg_frame);
8453EXPORT_SYMBOL(mpt_put_msg_frame);
8454EXPORT_SYMBOL(mpt_put_msg_frame_hi_pri);
8455EXPORT_SYMBOL(mpt_free_msg_frame);
8456EXPORT_SYMBOL(mpt_send_handshake_request);
8457EXPORT_SYMBOL(mpt_verify_adapter);
8458EXPORT_SYMBOL(mpt_GetIocState);
8459EXPORT_SYMBOL(mpt_print_ioc_summary);
8460EXPORT_SYMBOL(mpt_HardResetHandler);
8461EXPORT_SYMBOL(mpt_config);
8462EXPORT_SYMBOL(mpt_findImVolumes);
8463EXPORT_SYMBOL(mpt_alloc_fw_memory);
8464EXPORT_SYMBOL(mpt_free_fw_memory);
8465EXPORT_SYMBOL(mptbase_sas_persist_operation);
8466EXPORT_SYMBOL(mpt_raid_phys_disk_pg0);
8467
8468/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
8469/**
8470 * fusion_init - Fusion MPT base driver initialization routine.
8471 *
8472 * Returns 0 for success, non-zero for failure.
8473 */
8474static int __init
8475fusion_init(void)
8476{
8477 u8 cb_idx;
8478
8479 show_mptmod_ver(my_NAME, my_VERSION);
8480 printk(KERN_INFO COPYRIGHT "\n");
8481
8482 for (cb_idx = 0; cb_idx < MPT_MAX_PROTOCOL_DRIVERS; cb_idx++) {
8483 MptCallbacks[cb_idx] = NULL;
8484 MptDriverClass[cb_idx] = MPTUNKNOWN_DRIVER;
8485 MptEvHandlers[cb_idx] = NULL;
8486 MptResetHandlers[cb_idx] = NULL;
8487 }
8488
8489 /* Register ourselves (mptbase) in order to facilitate
8490 * EventNotification handling.
8491 */
8492 mpt_base_index = mpt_register(mptbase_reply, MPTBASE_DRIVER,
8493 "mptbase_reply");
8494
8495 /* Register for hard reset handling callbacks.
8496 */
8497 mpt_reset_register(mpt_base_index, mpt_ioc_reset);
8498
8499#ifdef CONFIG_PROC_FS
8500 (void) procmpt_create();
8501#endif
8502 return 0;
8503}
8504
8505/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
8506/**
8507 * fusion_exit - Perform driver unload cleanup.
8508 *
8509 * This routine frees all resources associated with each MPT adapter
8510 * and removes all %MPT_PROCFS_MPTBASEDIR entries.
8511 */
8512static void __exit
8513fusion_exit(void)
8514{
8515
8516 mpt_reset_deregister(mpt_base_index);
8517
8518#ifdef CONFIG_PROC_FS
8519 procmpt_destroy();
8520#endif
8521}
8522
8523module_init(fusion_init);
8524module_exit(fusion_exit);
1/*
2 * linux/drivers/message/fusion/mptbase.c
3 * This is the Fusion MPT base driver which supports multiple
4 * (SCSI + LAN) specialized protocol drivers.
5 * For use with LSI PCI chip/adapter(s)
6 * running LSI Fusion MPT (Message Passing Technology) firmware.
7 *
8 * Copyright (c) 1999-2008 LSI Corporation
9 * (mailto:DL-MPTFusionLinux@lsi.com)
10 *
11 */
12/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
13/*
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; version 2 of the License.
17
18 This program is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
22
23 NO WARRANTY
24 THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
25 CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
26 LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
27 MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
28 solely responsible for determining the appropriateness of using and
29 distributing the Program and assumes all risks associated with its
30 exercise of rights under this Agreement, including but not limited to
31 the risks and costs of program errors, damage to or loss of data,
32 programs or equipment, and unavailability or interruption of operations.
33
34 DISCLAIMER OF LIABILITY
35 NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
36 DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
37 DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
38 ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
39 TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
40 USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
41 HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
42
43 You should have received a copy of the GNU General Public License
44 along with this program; if not, write to the Free Software
45 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
46*/
47/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
48
49#include <linux/kernel.h>
50#include <linux/module.h>
51#include <linux/errno.h>
52#include <linux/init.h>
53#include <linux/seq_file.h>
54#include <linux/slab.h>
55#include <linux/types.h>
56#include <linux/pci.h>
57#include <linux/kdev_t.h>
58#include <linux/blkdev.h>
59#include <linux/delay.h>
60#include <linux/interrupt.h> /* needed for in_interrupt() proto */
61#include <linux/dma-mapping.h>
62#include <linux/kthread.h>
63#include <scsi/scsi_host.h>
64
65#include "mptbase.h"
66#include "lsi/mpi_log_fc.h"
67
68/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
69#define my_NAME "Fusion MPT base driver"
70#define my_VERSION MPT_LINUX_VERSION_COMMON
71#define MYNAM "mptbase"
72
73MODULE_AUTHOR(MODULEAUTHOR);
74MODULE_DESCRIPTION(my_NAME);
75MODULE_LICENSE("GPL");
76MODULE_VERSION(my_VERSION);
77
78/*
79 * cmd line parameters
80 */
81
82static int mpt_msi_enable_spi;
83module_param(mpt_msi_enable_spi, int, 0);
84MODULE_PARM_DESC(mpt_msi_enable_spi,
85 " Enable MSI Support for SPI controllers (default=0)");
86
87static int mpt_msi_enable_fc;
88module_param(mpt_msi_enable_fc, int, 0);
89MODULE_PARM_DESC(mpt_msi_enable_fc,
90 " Enable MSI Support for FC controllers (default=0)");
91
92static int mpt_msi_enable_sas;
93module_param(mpt_msi_enable_sas, int, 0);
94MODULE_PARM_DESC(mpt_msi_enable_sas,
95 " Enable MSI Support for SAS controllers (default=0)");
96
97static int mpt_channel_mapping;
98module_param(mpt_channel_mapping, int, 0);
99MODULE_PARM_DESC(mpt_channel_mapping, " Mapping id's to channels (default=0)");
100
101static int mpt_debug_level;
102static int mpt_set_debug_level(const char *val, struct kernel_param *kp);
103module_param_call(mpt_debug_level, mpt_set_debug_level, param_get_int,
104 &mpt_debug_level, 0600);
105MODULE_PARM_DESC(mpt_debug_level,
106 " debug level - refer to mptdebug.h - (default=0)");
107
108int mpt_fwfault_debug;
109EXPORT_SYMBOL(mpt_fwfault_debug);
110module_param(mpt_fwfault_debug, int, 0600);
111MODULE_PARM_DESC(mpt_fwfault_debug,
112 "Enable detection of Firmware fault and halt Firmware on fault - (default=0)");
113
114static char MptCallbacksName[MPT_MAX_PROTOCOL_DRIVERS]
115 [MPT_MAX_CALLBACKNAME_LEN+1];
116
117#ifdef MFCNT
118static int mfcounter = 0;
119#define PRINT_MF_COUNT 20000
120#endif
121
122/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
123/*
124 * Public data...
125 */
126
127#define WHOINIT_UNKNOWN 0xAA
128
129/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
130/*
131 * Private data...
132 */
133 /* Adapter link list */
134LIST_HEAD(ioc_list);
135 /* Callback lookup table */
136static MPT_CALLBACK MptCallbacks[MPT_MAX_PROTOCOL_DRIVERS];
137 /* Protocol driver class lookup table */
138static int MptDriverClass[MPT_MAX_PROTOCOL_DRIVERS];
139 /* Event handler lookup table */
140static MPT_EVHANDLER MptEvHandlers[MPT_MAX_PROTOCOL_DRIVERS];
141 /* Reset handler lookup table */
142static MPT_RESETHANDLER MptResetHandlers[MPT_MAX_PROTOCOL_DRIVERS];
143static struct mpt_pci_driver *MptDeviceDriverHandlers[MPT_MAX_PROTOCOL_DRIVERS];
144
145#ifdef CONFIG_PROC_FS
146static struct proc_dir_entry *mpt_proc_root_dir;
147#endif
148
149/*
150 * Driver Callback Index's
151 */
152static u8 mpt_base_index = MPT_MAX_PROTOCOL_DRIVERS;
153static u8 last_drv_idx;
154
155/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
156/*
157 * Forward protos...
158 */
159static irqreturn_t mpt_interrupt(int irq, void *bus_id);
160static int mptbase_reply(MPT_ADAPTER *ioc, MPT_FRAME_HDR *req,
161 MPT_FRAME_HDR *reply);
162static int mpt_handshake_req_reply_wait(MPT_ADAPTER *ioc, int reqBytes,
163 u32 *req, int replyBytes, u16 *u16reply, int maxwait,
164 int sleepFlag);
165static int mpt_do_ioc_recovery(MPT_ADAPTER *ioc, u32 reason, int sleepFlag);
166static void mpt_detect_bound_ports(MPT_ADAPTER *ioc, struct pci_dev *pdev);
167static void mpt_adapter_disable(MPT_ADAPTER *ioc);
168static void mpt_adapter_dispose(MPT_ADAPTER *ioc);
169
170static void MptDisplayIocCapabilities(MPT_ADAPTER *ioc);
171static int MakeIocReady(MPT_ADAPTER *ioc, int force, int sleepFlag);
172static int GetIocFacts(MPT_ADAPTER *ioc, int sleepFlag, int reason);
173static int GetPortFacts(MPT_ADAPTER *ioc, int portnum, int sleepFlag);
174static int SendIocInit(MPT_ADAPTER *ioc, int sleepFlag);
175static int SendPortEnable(MPT_ADAPTER *ioc, int portnum, int sleepFlag);
176static int mpt_do_upload(MPT_ADAPTER *ioc, int sleepFlag);
177static int mpt_downloadboot(MPT_ADAPTER *ioc, MpiFwHeader_t *pFwHeader, int sleepFlag);
178static int mpt_diag_reset(MPT_ADAPTER *ioc, int ignore, int sleepFlag);
179static int KickStart(MPT_ADAPTER *ioc, int ignore, int sleepFlag);
180static int SendIocReset(MPT_ADAPTER *ioc, u8 reset_type, int sleepFlag);
181static int PrimeIocFifos(MPT_ADAPTER *ioc);
182static int WaitForDoorbellAck(MPT_ADAPTER *ioc, int howlong, int sleepFlag);
183static int WaitForDoorbellInt(MPT_ADAPTER *ioc, int howlong, int sleepFlag);
184static int WaitForDoorbellReply(MPT_ADAPTER *ioc, int howlong, int sleepFlag);
185static int GetLanConfigPages(MPT_ADAPTER *ioc);
186static int GetIoUnitPage2(MPT_ADAPTER *ioc);
187int mptbase_sas_persist_operation(MPT_ADAPTER *ioc, u8 persist_opcode);
188static int mpt_GetScsiPortSettings(MPT_ADAPTER *ioc, int portnum);
189static int mpt_readScsiDevicePageHeaders(MPT_ADAPTER *ioc, int portnum);
190static void mpt_read_ioc_pg_1(MPT_ADAPTER *ioc);
191static void mpt_read_ioc_pg_4(MPT_ADAPTER *ioc);
192static void mpt_get_manufacturing_pg_0(MPT_ADAPTER *ioc);
193static int SendEventNotification(MPT_ADAPTER *ioc, u8 EvSwitch,
194 int sleepFlag);
195static int SendEventAck(MPT_ADAPTER *ioc, EventNotificationReply_t *evnp);
196static int mpt_host_page_access_control(MPT_ADAPTER *ioc, u8 access_control_value, int sleepFlag);
197static int mpt_host_page_alloc(MPT_ADAPTER *ioc, pIOCInit_t ioc_init);
198
199#ifdef CONFIG_PROC_FS
200static const struct file_operations mpt_summary_proc_fops;
201static const struct file_operations mpt_version_proc_fops;
202static const struct file_operations mpt_iocinfo_proc_fops;
203#endif
204static void mpt_get_fw_exp_ver(char *buf, MPT_ADAPTER *ioc);
205
206static int ProcessEventNotification(MPT_ADAPTER *ioc,
207 EventNotificationReply_t *evReply, int *evHandlers);
208static void mpt_iocstatus_info(MPT_ADAPTER *ioc, u32 ioc_status, MPT_FRAME_HDR *mf);
209static void mpt_fc_log_info(MPT_ADAPTER *ioc, u32 log_info);
210static void mpt_spi_log_info(MPT_ADAPTER *ioc, u32 log_info);
211static void mpt_sas_log_info(MPT_ADAPTER *ioc, u32 log_info , u8 cb_idx);
212static int mpt_read_ioc_pg_3(MPT_ADAPTER *ioc);
213static void mpt_inactive_raid_list_free(MPT_ADAPTER *ioc);
214
215/* module entry point */
216static int __init fusion_init (void);
217static void __exit fusion_exit (void);
218
219#define CHIPREG_READ32(addr) readl_relaxed(addr)
220#define CHIPREG_READ32_dmasync(addr) readl(addr)
221#define CHIPREG_WRITE32(addr,val) writel(val, addr)
222#define CHIPREG_PIO_WRITE32(addr,val) outl(val, (unsigned long)addr)
223#define CHIPREG_PIO_READ32(addr) inl((unsigned long)addr)
224
225static void
226pci_disable_io_access(struct pci_dev *pdev)
227{
228 u16 command_reg;
229
230 pci_read_config_word(pdev, PCI_COMMAND, &command_reg);
231 command_reg &= ~1;
232 pci_write_config_word(pdev, PCI_COMMAND, command_reg);
233}
234
235static void
236pci_enable_io_access(struct pci_dev *pdev)
237{
238 u16 command_reg;
239
240 pci_read_config_word(pdev, PCI_COMMAND, &command_reg);
241 command_reg |= 1;
242 pci_write_config_word(pdev, PCI_COMMAND, command_reg);
243}
244
245static int mpt_set_debug_level(const char *val, struct kernel_param *kp)
246{
247 int ret = param_set_int(val, kp);
248 MPT_ADAPTER *ioc;
249
250 if (ret)
251 return ret;
252
253 list_for_each_entry(ioc, &ioc_list, list)
254 ioc->debug_level = mpt_debug_level;
255 return 0;
256}
257
258/**
259 * mpt_get_cb_idx - obtain cb_idx for registered driver
260 * @dclass: class driver enum
261 *
262 * Returns cb_idx, or zero means it wasn't found
263 **/
264static u8
265mpt_get_cb_idx(MPT_DRIVER_CLASS dclass)
266{
267 u8 cb_idx;
268
269 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--)
270 if (MptDriverClass[cb_idx] == dclass)
271 return cb_idx;
272 return 0;
273}
274
275/**
276 * mpt_is_discovery_complete - determine if discovery has completed
277 * @ioc: per adatper instance
278 *
279 * Returns 1 when discovery completed, else zero.
280 */
281static int
282mpt_is_discovery_complete(MPT_ADAPTER *ioc)
283{
284 ConfigExtendedPageHeader_t hdr;
285 CONFIGPARMS cfg;
286 SasIOUnitPage0_t *buffer;
287 dma_addr_t dma_handle;
288 int rc = 0;
289
290 memset(&hdr, 0, sizeof(ConfigExtendedPageHeader_t));
291 memset(&cfg, 0, sizeof(CONFIGPARMS));
292 hdr.PageVersion = MPI_SASIOUNITPAGE0_PAGEVERSION;
293 hdr.PageType = MPI_CONFIG_PAGETYPE_EXTENDED;
294 hdr.ExtPageType = MPI_CONFIG_EXTPAGETYPE_SAS_IO_UNIT;
295 cfg.cfghdr.ehdr = &hdr;
296 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
297
298 if ((mpt_config(ioc, &cfg)))
299 goto out;
300 if (!hdr.ExtPageLength)
301 goto out;
302
303 buffer = pci_alloc_consistent(ioc->pcidev, hdr.ExtPageLength * 4,
304 &dma_handle);
305 if (!buffer)
306 goto out;
307
308 cfg.physAddr = dma_handle;
309 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
310
311 if ((mpt_config(ioc, &cfg)))
312 goto out_free_consistent;
313
314 if (!(buffer->PhyData[0].PortFlags &
315 MPI_SAS_IOUNIT0_PORT_FLAGS_DISCOVERY_IN_PROGRESS))
316 rc = 1;
317
318 out_free_consistent:
319 pci_free_consistent(ioc->pcidev, hdr.ExtPageLength * 4,
320 buffer, dma_handle);
321 out:
322 return rc;
323}
324
325
326/**
327 * mpt_remove_dead_ioc_func - kthread context to remove dead ioc
328 * @arg: input argument, used to derive ioc
329 *
330 * Return 0 if controller is removed from pci subsystem.
331 * Return -1 for other case.
332 */
333static int mpt_remove_dead_ioc_func(void *arg)
334{
335 MPT_ADAPTER *ioc = (MPT_ADAPTER *)arg;
336 struct pci_dev *pdev;
337
338 if ((ioc == NULL))
339 return -1;
340
341 pdev = ioc->pcidev;
342 if ((pdev == NULL))
343 return -1;
344
345 pci_stop_and_remove_bus_device_locked(pdev);
346 return 0;
347}
348
349
350
351/**
352 * mpt_fault_reset_work - work performed on workq after ioc fault
353 * @work: input argument, used to derive ioc
354 *
355**/
356static void
357mpt_fault_reset_work(struct work_struct *work)
358{
359 MPT_ADAPTER *ioc =
360 container_of(work, MPT_ADAPTER, fault_reset_work.work);
361 u32 ioc_raw_state;
362 int rc;
363 unsigned long flags;
364 MPT_SCSI_HOST *hd;
365 struct task_struct *p;
366
367 if (ioc->ioc_reset_in_progress || !ioc->active)
368 goto out;
369
370
371 ioc_raw_state = mpt_GetIocState(ioc, 0);
372 if ((ioc_raw_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_MASK) {
373 printk(MYIOC_s_INFO_FMT "%s: IOC is non-operational !!!!\n",
374 ioc->name, __func__);
375
376 /*
377 * Call mptscsih_flush_pending_cmds callback so that we
378 * flush all pending commands back to OS.
379 * This call is required to aovid deadlock at block layer.
380 * Dead IOC will fail to do diag reset,and this call is safe
381 * since dead ioc will never return any command back from HW.
382 */
383 hd = shost_priv(ioc->sh);
384 ioc->schedule_dead_ioc_flush_running_cmds(hd);
385
386 /*Remove the Dead Host */
387 p = kthread_run(mpt_remove_dead_ioc_func, ioc,
388 "mpt_dead_ioc_%d", ioc->id);
389 if (IS_ERR(p)) {
390 printk(MYIOC_s_ERR_FMT
391 "%s: Running mpt_dead_ioc thread failed !\n",
392 ioc->name, __func__);
393 } else {
394 printk(MYIOC_s_WARN_FMT
395 "%s: Running mpt_dead_ioc thread success !\n",
396 ioc->name, __func__);
397 }
398 return; /* don't rearm timer */
399 }
400
401 if ((ioc_raw_state & MPI_IOC_STATE_MASK)
402 == MPI_IOC_STATE_FAULT) {
403 printk(MYIOC_s_WARN_FMT "IOC is in FAULT state (%04xh)!!!\n",
404 ioc->name, ioc_raw_state & MPI_DOORBELL_DATA_MASK);
405 printk(MYIOC_s_WARN_FMT "Issuing HardReset from %s!!\n",
406 ioc->name, __func__);
407 rc = mpt_HardResetHandler(ioc, CAN_SLEEP);
408 printk(MYIOC_s_WARN_FMT "%s: HardReset: %s\n", ioc->name,
409 __func__, (rc == 0) ? "success" : "failed");
410 ioc_raw_state = mpt_GetIocState(ioc, 0);
411 if ((ioc_raw_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_FAULT)
412 printk(MYIOC_s_WARN_FMT "IOC is in FAULT state after "
413 "reset (%04xh)\n", ioc->name, ioc_raw_state &
414 MPI_DOORBELL_DATA_MASK);
415 } else if (ioc->bus_type == SAS && ioc->sas_discovery_quiesce_io) {
416 if ((mpt_is_discovery_complete(ioc))) {
417 devtprintk(ioc, printk(MYIOC_s_DEBUG_FMT "clearing "
418 "discovery_quiesce_io flag\n", ioc->name));
419 ioc->sas_discovery_quiesce_io = 0;
420 }
421 }
422
423 out:
424 /*
425 * Take turns polling alternate controller
426 */
427 if (ioc->alt_ioc)
428 ioc = ioc->alt_ioc;
429
430 /* rearm the timer */
431 spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
432 if (ioc->reset_work_q)
433 queue_delayed_work(ioc->reset_work_q, &ioc->fault_reset_work,
434 msecs_to_jiffies(MPT_POLLING_INTERVAL));
435 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
436}
437
438
439/*
440 * Process turbo (context) reply...
441 */
442static void
443mpt_turbo_reply(MPT_ADAPTER *ioc, u32 pa)
444{
445 MPT_FRAME_HDR *mf = NULL;
446 MPT_FRAME_HDR *mr = NULL;
447 u16 req_idx = 0;
448 u8 cb_idx;
449
450 dmfprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Got TURBO reply req_idx=%08x\n",
451 ioc->name, pa));
452
453 switch (pa >> MPI_CONTEXT_REPLY_TYPE_SHIFT) {
454 case MPI_CONTEXT_REPLY_TYPE_SCSI_INIT:
455 req_idx = pa & 0x0000FFFF;
456 cb_idx = (pa & 0x00FF0000) >> 16;
457 mf = MPT_INDEX_2_MFPTR(ioc, req_idx);
458 break;
459 case MPI_CONTEXT_REPLY_TYPE_LAN:
460 cb_idx = mpt_get_cb_idx(MPTLAN_DRIVER);
461 /*
462 * Blind set of mf to NULL here was fatal
463 * after lan_reply says "freeme"
464 * Fix sort of combined with an optimization here;
465 * added explicit check for case where lan_reply
466 * was just returning 1 and doing nothing else.
467 * For this case skip the callback, but set up
468 * proper mf value first here:-)
469 */
470 if ((pa & 0x58000000) == 0x58000000) {
471 req_idx = pa & 0x0000FFFF;
472 mf = MPT_INDEX_2_MFPTR(ioc, req_idx);
473 mpt_free_msg_frame(ioc, mf);
474 mb();
475 return;
476 break;
477 }
478 mr = (MPT_FRAME_HDR *) CAST_U32_TO_PTR(pa);
479 break;
480 case MPI_CONTEXT_REPLY_TYPE_SCSI_TARGET:
481 cb_idx = mpt_get_cb_idx(MPTSTM_DRIVER);
482 mr = (MPT_FRAME_HDR *) CAST_U32_TO_PTR(pa);
483 break;
484 default:
485 cb_idx = 0;
486 BUG();
487 }
488
489 /* Check for (valid) IO callback! */
490 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS ||
491 MptCallbacks[cb_idx] == NULL) {
492 printk(MYIOC_s_WARN_FMT "%s: Invalid cb_idx (%d)!\n",
493 __func__, ioc->name, cb_idx);
494 goto out;
495 }
496
497 if (MptCallbacks[cb_idx](ioc, mf, mr))
498 mpt_free_msg_frame(ioc, mf);
499 out:
500 mb();
501}
502
503static void
504mpt_reply(MPT_ADAPTER *ioc, u32 pa)
505{
506 MPT_FRAME_HDR *mf;
507 MPT_FRAME_HDR *mr;
508 u16 req_idx;
509 u8 cb_idx;
510 int freeme;
511
512 u32 reply_dma_low;
513 u16 ioc_stat;
514
515 /* non-TURBO reply! Hmmm, something may be up...
516 * Newest turbo reply mechanism; get address
517 * via left shift 1 (get rid of MPI_ADDRESS_REPLY_A_BIT)!
518 */
519
520 /* Map DMA address of reply header to cpu address.
521 * pa is 32 bits - but the dma address may be 32 or 64 bits
522 * get offset based only only the low addresses
523 */
524
525 reply_dma_low = (pa <<= 1);
526 mr = (MPT_FRAME_HDR *)((u8 *)ioc->reply_frames +
527 (reply_dma_low - ioc->reply_frames_low_dma));
528
529 req_idx = le16_to_cpu(mr->u.frame.hwhdr.msgctxu.fld.req_idx);
530 cb_idx = mr->u.frame.hwhdr.msgctxu.fld.cb_idx;
531 mf = MPT_INDEX_2_MFPTR(ioc, req_idx);
532
533 dmfprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Got non-TURBO reply=%p req_idx=%x cb_idx=%x Function=%x\n",
534 ioc->name, mr, req_idx, cb_idx, mr->u.hdr.Function));
535 DBG_DUMP_REPLY_FRAME(ioc, (u32 *)mr);
536
537 /* Check/log IOC log info
538 */
539 ioc_stat = le16_to_cpu(mr->u.reply.IOCStatus);
540 if (ioc_stat & MPI_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) {
541 u32 log_info = le32_to_cpu(mr->u.reply.IOCLogInfo);
542 if (ioc->bus_type == FC)
543 mpt_fc_log_info(ioc, log_info);
544 else if (ioc->bus_type == SPI)
545 mpt_spi_log_info(ioc, log_info);
546 else if (ioc->bus_type == SAS)
547 mpt_sas_log_info(ioc, log_info, cb_idx);
548 }
549
550 if (ioc_stat & MPI_IOCSTATUS_MASK)
551 mpt_iocstatus_info(ioc, (u32)ioc_stat, mf);
552
553 /* Check for (valid) IO callback! */
554 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS ||
555 MptCallbacks[cb_idx] == NULL) {
556 printk(MYIOC_s_WARN_FMT "%s: Invalid cb_idx (%d)!\n",
557 __func__, ioc->name, cb_idx);
558 freeme = 0;
559 goto out;
560 }
561
562 freeme = MptCallbacks[cb_idx](ioc, mf, mr);
563
564 out:
565 /* Flush (non-TURBO) reply with a WRITE! */
566 CHIPREG_WRITE32(&ioc->chip->ReplyFifo, pa);
567
568 if (freeme)
569 mpt_free_msg_frame(ioc, mf);
570 mb();
571}
572
573/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
574/**
575 * mpt_interrupt - MPT adapter (IOC) specific interrupt handler.
576 * @irq: irq number (not used)
577 * @bus_id: bus identifier cookie == pointer to MPT_ADAPTER structure
578 *
579 * This routine is registered via the request_irq() kernel API call,
580 * and handles all interrupts generated from a specific MPT adapter
581 * (also referred to as a IO Controller or IOC).
582 * This routine must clear the interrupt from the adapter and does
583 * so by reading the reply FIFO. Multiple replies may be processed
584 * per single call to this routine.
585 *
586 * This routine handles register-level access of the adapter but
587 * dispatches (calls) a protocol-specific callback routine to handle
588 * the protocol-specific details of the MPT request completion.
589 */
590static irqreturn_t
591mpt_interrupt(int irq, void *bus_id)
592{
593 MPT_ADAPTER *ioc = bus_id;
594 u32 pa = CHIPREG_READ32_dmasync(&ioc->chip->ReplyFifo);
595
596 if (pa == 0xFFFFFFFF)
597 return IRQ_NONE;
598
599 /*
600 * Drain the reply FIFO!
601 */
602 do {
603 if (pa & MPI_ADDRESS_REPLY_A_BIT)
604 mpt_reply(ioc, pa);
605 else
606 mpt_turbo_reply(ioc, pa);
607 pa = CHIPREG_READ32_dmasync(&ioc->chip->ReplyFifo);
608 } while (pa != 0xFFFFFFFF);
609
610 return IRQ_HANDLED;
611}
612
613/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
614/**
615 * mptbase_reply - MPT base driver's callback routine
616 * @ioc: Pointer to MPT_ADAPTER structure
617 * @req: Pointer to original MPT request frame
618 * @reply: Pointer to MPT reply frame (NULL if TurboReply)
619 *
620 * MPT base driver's callback routine; all base driver
621 * "internal" request/reply processing is routed here.
622 * Currently used for EventNotification and EventAck handling.
623 *
624 * Returns 1 indicating original alloc'd request frame ptr
625 * should be freed, or 0 if it shouldn't.
626 */
627static int
628mptbase_reply(MPT_ADAPTER *ioc, MPT_FRAME_HDR *req, MPT_FRAME_HDR *reply)
629{
630 EventNotificationReply_t *pEventReply;
631 u8 event;
632 int evHandlers;
633 int freereq = 1;
634
635 switch (reply->u.hdr.Function) {
636 case MPI_FUNCTION_EVENT_NOTIFICATION:
637 pEventReply = (EventNotificationReply_t *)reply;
638 evHandlers = 0;
639 ProcessEventNotification(ioc, pEventReply, &evHandlers);
640 event = le32_to_cpu(pEventReply->Event) & 0xFF;
641 if (pEventReply->MsgFlags & MPI_MSGFLAGS_CONTINUATION_REPLY)
642 freereq = 0;
643 if (event != MPI_EVENT_EVENT_CHANGE)
644 break;
645 case MPI_FUNCTION_CONFIG:
646 case MPI_FUNCTION_SAS_IO_UNIT_CONTROL:
647 ioc->mptbase_cmds.status |= MPT_MGMT_STATUS_COMMAND_GOOD;
648 ioc->mptbase_cmds.status |= MPT_MGMT_STATUS_RF_VALID;
649 memcpy(ioc->mptbase_cmds.reply, reply,
650 min(MPT_DEFAULT_FRAME_SIZE,
651 4 * reply->u.reply.MsgLength));
652 if (ioc->mptbase_cmds.status & MPT_MGMT_STATUS_PENDING) {
653 ioc->mptbase_cmds.status &= ~MPT_MGMT_STATUS_PENDING;
654 complete(&ioc->mptbase_cmds.done);
655 } else
656 freereq = 0;
657 if (ioc->mptbase_cmds.status & MPT_MGMT_STATUS_FREE_MF)
658 freereq = 1;
659 break;
660 case MPI_FUNCTION_EVENT_ACK:
661 devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT
662 "EventAck reply received\n", ioc->name));
663 break;
664 default:
665 printk(MYIOC_s_ERR_FMT
666 "Unexpected msg function (=%02Xh) reply received!\n",
667 ioc->name, reply->u.hdr.Function);
668 break;
669 }
670
671 /*
672 * Conditionally tell caller to free the original
673 * EventNotification/EventAck/unexpected request frame!
674 */
675 return freereq;
676}
677
678/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
679/**
680 * mpt_register - Register protocol-specific main callback handler.
681 * @cbfunc: callback function pointer
682 * @dclass: Protocol driver's class (%MPT_DRIVER_CLASS enum value)
683 * @func_name: call function's name
684 *
685 * This routine is called by a protocol-specific driver (SCSI host,
686 * LAN, SCSI target) to register its reply callback routine. Each
687 * protocol-specific driver must do this before it will be able to
688 * use any IOC resources, such as obtaining request frames.
689 *
690 * NOTES: The SCSI protocol driver currently calls this routine thrice
691 * in order to register separate callbacks; one for "normal" SCSI IO;
692 * one for MptScsiTaskMgmt requests; one for Scan/DV requests.
693 *
694 * Returns u8 valued "handle" in the range (and S.O.D. order)
695 * {N,...,7,6,5,...,1} if successful.
696 * A return value of MPT_MAX_PROTOCOL_DRIVERS (including zero!) should be
697 * considered an error by the caller.
698 */
699u8
700mpt_register(MPT_CALLBACK cbfunc, MPT_DRIVER_CLASS dclass, char *func_name)
701{
702 u8 cb_idx;
703 last_drv_idx = MPT_MAX_PROTOCOL_DRIVERS;
704
705 /*
706 * Search for empty callback slot in this order: {N,...,7,6,5,...,1}
707 * (slot/handle 0 is reserved!)
708 */
709 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
710 if (MptCallbacks[cb_idx] == NULL) {
711 MptCallbacks[cb_idx] = cbfunc;
712 MptDriverClass[cb_idx] = dclass;
713 MptEvHandlers[cb_idx] = NULL;
714 last_drv_idx = cb_idx;
715 strlcpy(MptCallbacksName[cb_idx], func_name,
716 MPT_MAX_CALLBACKNAME_LEN+1);
717 break;
718 }
719 }
720
721 return last_drv_idx;
722}
723
724/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
725/**
726 * mpt_deregister - Deregister a protocol drivers resources.
727 * @cb_idx: previously registered callback handle
728 *
729 * Each protocol-specific driver should call this routine when its
730 * module is unloaded.
731 */
732void
733mpt_deregister(u8 cb_idx)
734{
735 if (cb_idx && (cb_idx < MPT_MAX_PROTOCOL_DRIVERS)) {
736 MptCallbacks[cb_idx] = NULL;
737 MptDriverClass[cb_idx] = MPTUNKNOWN_DRIVER;
738 MptEvHandlers[cb_idx] = NULL;
739
740 last_drv_idx++;
741 }
742}
743
744/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
745/**
746 * mpt_event_register - Register protocol-specific event callback handler.
747 * @cb_idx: previously registered (via mpt_register) callback handle
748 * @ev_cbfunc: callback function
749 *
750 * This routine can be called by one or more protocol-specific drivers
751 * if/when they choose to be notified of MPT events.
752 *
753 * Returns 0 for success.
754 */
755int
756mpt_event_register(u8 cb_idx, MPT_EVHANDLER ev_cbfunc)
757{
758 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS)
759 return -1;
760
761 MptEvHandlers[cb_idx] = ev_cbfunc;
762 return 0;
763}
764
765/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
766/**
767 * mpt_event_deregister - Deregister protocol-specific event callback handler
768 * @cb_idx: previously registered callback handle
769 *
770 * Each protocol-specific driver should call this routine
771 * when it does not (or can no longer) handle events,
772 * or when its module is unloaded.
773 */
774void
775mpt_event_deregister(u8 cb_idx)
776{
777 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS)
778 return;
779
780 MptEvHandlers[cb_idx] = NULL;
781}
782
783/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
784/**
785 * mpt_reset_register - Register protocol-specific IOC reset handler.
786 * @cb_idx: previously registered (via mpt_register) callback handle
787 * @reset_func: reset function
788 *
789 * This routine can be called by one or more protocol-specific drivers
790 * if/when they choose to be notified of IOC resets.
791 *
792 * Returns 0 for success.
793 */
794int
795mpt_reset_register(u8 cb_idx, MPT_RESETHANDLER reset_func)
796{
797 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS)
798 return -1;
799
800 MptResetHandlers[cb_idx] = reset_func;
801 return 0;
802}
803
804/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
805/**
806 * mpt_reset_deregister - Deregister protocol-specific IOC reset handler.
807 * @cb_idx: previously registered callback handle
808 *
809 * Each protocol-specific driver should call this routine
810 * when it does not (or can no longer) handle IOC reset handling,
811 * or when its module is unloaded.
812 */
813void
814mpt_reset_deregister(u8 cb_idx)
815{
816 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS)
817 return;
818
819 MptResetHandlers[cb_idx] = NULL;
820}
821
822/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
823/**
824 * mpt_device_driver_register - Register device driver hooks
825 * @dd_cbfunc: driver callbacks struct
826 * @cb_idx: MPT protocol driver index
827 */
828int
829mpt_device_driver_register(struct mpt_pci_driver * dd_cbfunc, u8 cb_idx)
830{
831 MPT_ADAPTER *ioc;
832 const struct pci_device_id *id;
833
834 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS)
835 return -EINVAL;
836
837 MptDeviceDriverHandlers[cb_idx] = dd_cbfunc;
838
839 /* call per pci device probe entry point */
840 list_for_each_entry(ioc, &ioc_list, list) {
841 id = ioc->pcidev->driver ?
842 ioc->pcidev->driver->id_table : NULL;
843 if (dd_cbfunc->probe)
844 dd_cbfunc->probe(ioc->pcidev, id);
845 }
846
847 return 0;
848}
849
850/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
851/**
852 * mpt_device_driver_deregister - DeRegister device driver hooks
853 * @cb_idx: MPT protocol driver index
854 */
855void
856mpt_device_driver_deregister(u8 cb_idx)
857{
858 struct mpt_pci_driver *dd_cbfunc;
859 MPT_ADAPTER *ioc;
860
861 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS)
862 return;
863
864 dd_cbfunc = MptDeviceDriverHandlers[cb_idx];
865
866 list_for_each_entry(ioc, &ioc_list, list) {
867 if (dd_cbfunc->remove)
868 dd_cbfunc->remove(ioc->pcidev);
869 }
870
871 MptDeviceDriverHandlers[cb_idx] = NULL;
872}
873
874
875/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
876/**
877 * mpt_get_msg_frame - Obtain an MPT request frame from the pool
878 * @cb_idx: Handle of registered MPT protocol driver
879 * @ioc: Pointer to MPT adapter structure
880 *
881 * Obtain an MPT request frame from the pool (of 1024) that are
882 * allocated per MPT adapter.
883 *
884 * Returns pointer to a MPT request frame or %NULL if none are available
885 * or IOC is not active.
886 */
887MPT_FRAME_HDR*
888mpt_get_msg_frame(u8 cb_idx, MPT_ADAPTER *ioc)
889{
890 MPT_FRAME_HDR *mf;
891 unsigned long flags;
892 u16 req_idx; /* Request index */
893
894 /* validate handle and ioc identifier */
895
896#ifdef MFCNT
897 if (!ioc->active)
898 printk(MYIOC_s_WARN_FMT "IOC Not Active! mpt_get_msg_frame "
899 "returning NULL!\n", ioc->name);
900#endif
901
902 /* If interrupts are not attached, do not return a request frame */
903 if (!ioc->active)
904 return NULL;
905
906 spin_lock_irqsave(&ioc->FreeQlock, flags);
907 if (!list_empty(&ioc->FreeQ)) {
908 int req_offset;
909
910 mf = list_entry(ioc->FreeQ.next, MPT_FRAME_HDR,
911 u.frame.linkage.list);
912 list_del(&mf->u.frame.linkage.list);
913 mf->u.frame.linkage.arg1 = 0;
914 mf->u.frame.hwhdr.msgctxu.fld.cb_idx = cb_idx; /* byte */
915 req_offset = (u8 *)mf - (u8 *)ioc->req_frames;
916 /* u16! */
917 req_idx = req_offset / ioc->req_sz;
918 mf->u.frame.hwhdr.msgctxu.fld.req_idx = cpu_to_le16(req_idx);
919 mf->u.frame.hwhdr.msgctxu.fld.rsvd = 0;
920 /* Default, will be changed if necessary in SG generation */
921 ioc->RequestNB[req_idx] = ioc->NB_for_64_byte_frame;
922#ifdef MFCNT
923 ioc->mfcnt++;
924#endif
925 }
926 else
927 mf = NULL;
928 spin_unlock_irqrestore(&ioc->FreeQlock, flags);
929
930#ifdef MFCNT
931 if (mf == NULL)
932 printk(MYIOC_s_WARN_FMT "IOC Active. No free Msg Frames! "
933 "Count 0x%x Max 0x%x\n", ioc->name, ioc->mfcnt,
934 ioc->req_depth);
935 mfcounter++;
936 if (mfcounter == PRINT_MF_COUNT)
937 printk(MYIOC_s_INFO_FMT "MF Count 0x%x Max 0x%x \n", ioc->name,
938 ioc->mfcnt, ioc->req_depth);
939#endif
940
941 dmfprintk(ioc, printk(MYIOC_s_DEBUG_FMT "mpt_get_msg_frame(%d,%d), got mf=%p\n",
942 ioc->name, cb_idx, ioc->id, mf));
943 return mf;
944}
945
946/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
947/**
948 * mpt_put_msg_frame - Send a protocol-specific MPT request frame to an IOC
949 * @cb_idx: Handle of registered MPT protocol driver
950 * @ioc: Pointer to MPT adapter structure
951 * @mf: Pointer to MPT request frame
952 *
953 * This routine posts an MPT request frame to the request post FIFO of a
954 * specific MPT adapter.
955 */
956void
957mpt_put_msg_frame(u8 cb_idx, MPT_ADAPTER *ioc, MPT_FRAME_HDR *mf)
958{
959 u32 mf_dma_addr;
960 int req_offset;
961 u16 req_idx; /* Request index */
962
963 /* ensure values are reset properly! */
964 mf->u.frame.hwhdr.msgctxu.fld.cb_idx = cb_idx; /* byte */
965 req_offset = (u8 *)mf - (u8 *)ioc->req_frames;
966 /* u16! */
967 req_idx = req_offset / ioc->req_sz;
968 mf->u.frame.hwhdr.msgctxu.fld.req_idx = cpu_to_le16(req_idx);
969 mf->u.frame.hwhdr.msgctxu.fld.rsvd = 0;
970
971 DBG_DUMP_PUT_MSG_FRAME(ioc, (u32 *)mf);
972
973 mf_dma_addr = (ioc->req_frames_low_dma + req_offset) | ioc->RequestNB[req_idx];
974 dsgprintk(ioc, printk(MYIOC_s_DEBUG_FMT "mf_dma_addr=%x req_idx=%d "
975 "RequestNB=%x\n", ioc->name, mf_dma_addr, req_idx,
976 ioc->RequestNB[req_idx]));
977 CHIPREG_WRITE32(&ioc->chip->RequestFifo, mf_dma_addr);
978}
979
980/**
981 * mpt_put_msg_frame_hi_pri - Send a hi-pri protocol-specific MPT request frame
982 * @cb_idx: Handle of registered MPT protocol driver
983 * @ioc: Pointer to MPT adapter structure
984 * @mf: Pointer to MPT request frame
985 *
986 * Send a protocol-specific MPT request frame to an IOC using
987 * hi-priority request queue.
988 *
989 * This routine posts an MPT request frame to the request post FIFO of a
990 * specific MPT adapter.
991 **/
992void
993mpt_put_msg_frame_hi_pri(u8 cb_idx, MPT_ADAPTER *ioc, MPT_FRAME_HDR *mf)
994{
995 u32 mf_dma_addr;
996 int req_offset;
997 u16 req_idx; /* Request index */
998
999 /* ensure values are reset properly! */
1000 mf->u.frame.hwhdr.msgctxu.fld.cb_idx = cb_idx;
1001 req_offset = (u8 *)mf - (u8 *)ioc->req_frames;
1002 req_idx = req_offset / ioc->req_sz;
1003 mf->u.frame.hwhdr.msgctxu.fld.req_idx = cpu_to_le16(req_idx);
1004 mf->u.frame.hwhdr.msgctxu.fld.rsvd = 0;
1005
1006 DBG_DUMP_PUT_MSG_FRAME(ioc, (u32 *)mf);
1007
1008 mf_dma_addr = (ioc->req_frames_low_dma + req_offset);
1009 dsgprintk(ioc, printk(MYIOC_s_DEBUG_FMT "mf_dma_addr=%x req_idx=%d\n",
1010 ioc->name, mf_dma_addr, req_idx));
1011 CHIPREG_WRITE32(&ioc->chip->RequestHiPriFifo, mf_dma_addr);
1012}
1013
1014/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
1015/**
1016 * mpt_free_msg_frame - Place MPT request frame back on FreeQ.
1017 * @ioc: Pointer to MPT adapter structure
1018 * @mf: Pointer to MPT request frame
1019 *
1020 * This routine places a MPT request frame back on the MPT adapter's
1021 * FreeQ.
1022 */
1023void
1024mpt_free_msg_frame(MPT_ADAPTER *ioc, MPT_FRAME_HDR *mf)
1025{
1026 unsigned long flags;
1027
1028 /* Put Request back on FreeQ! */
1029 spin_lock_irqsave(&ioc->FreeQlock, flags);
1030 if (cpu_to_le32(mf->u.frame.linkage.arg1) == 0xdeadbeaf)
1031 goto out;
1032 /* signature to know if this mf is freed */
1033 mf->u.frame.linkage.arg1 = cpu_to_le32(0xdeadbeaf);
1034 list_add(&mf->u.frame.linkage.list, &ioc->FreeQ);
1035#ifdef MFCNT
1036 ioc->mfcnt--;
1037#endif
1038 out:
1039 spin_unlock_irqrestore(&ioc->FreeQlock, flags);
1040}
1041
1042/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
1043/**
1044 * mpt_add_sge - Place a simple 32 bit SGE at address pAddr.
1045 * @pAddr: virtual address for SGE
1046 * @flagslength: SGE flags and data transfer length
1047 * @dma_addr: Physical address
1048 *
1049 * This routine places a MPT request frame back on the MPT adapter's
1050 * FreeQ.
1051 */
1052static void
1053mpt_add_sge(void *pAddr, u32 flagslength, dma_addr_t dma_addr)
1054{
1055 SGESimple32_t *pSge = (SGESimple32_t *) pAddr;
1056 pSge->FlagsLength = cpu_to_le32(flagslength);
1057 pSge->Address = cpu_to_le32(dma_addr);
1058}
1059
1060/**
1061 * mpt_add_sge_64bit - Place a simple 64 bit SGE at address pAddr.
1062 * @pAddr: virtual address for SGE
1063 * @flagslength: SGE flags and data transfer length
1064 * @dma_addr: Physical address
1065 *
1066 * This routine places a MPT request frame back on the MPT adapter's
1067 * FreeQ.
1068 **/
1069static void
1070mpt_add_sge_64bit(void *pAddr, u32 flagslength, dma_addr_t dma_addr)
1071{
1072 SGESimple64_t *pSge = (SGESimple64_t *) pAddr;
1073 pSge->Address.Low = cpu_to_le32
1074 (lower_32_bits(dma_addr));
1075 pSge->Address.High = cpu_to_le32
1076 (upper_32_bits(dma_addr));
1077 pSge->FlagsLength = cpu_to_le32
1078 ((flagslength | MPT_SGE_FLAGS_64_BIT_ADDRESSING));
1079}
1080
1081/**
1082 * mpt_add_sge_64bit_1078 - Place a simple 64 bit SGE at address pAddr (1078 workaround).
1083 * @pAddr: virtual address for SGE
1084 * @flagslength: SGE flags and data transfer length
1085 * @dma_addr: Physical address
1086 *
1087 * This routine places a MPT request frame back on the MPT adapter's
1088 * FreeQ.
1089 **/
1090static void
1091mpt_add_sge_64bit_1078(void *pAddr, u32 flagslength, dma_addr_t dma_addr)
1092{
1093 SGESimple64_t *pSge = (SGESimple64_t *) pAddr;
1094 u32 tmp;
1095
1096 pSge->Address.Low = cpu_to_le32
1097 (lower_32_bits(dma_addr));
1098 tmp = (u32)(upper_32_bits(dma_addr));
1099
1100 /*
1101 * 1078 errata workaround for the 36GB limitation
1102 */
1103 if ((((u64)dma_addr + MPI_SGE_LENGTH(flagslength)) >> 32) == 9) {
1104 flagslength |=
1105 MPI_SGE_SET_FLAGS(MPI_SGE_FLAGS_LOCAL_ADDRESS);
1106 tmp |= (1<<31);
1107 if (mpt_debug_level & MPT_DEBUG_36GB_MEM)
1108 printk(KERN_DEBUG "1078 P0M2 addressing for "
1109 "addr = 0x%llx len = %d\n",
1110 (unsigned long long)dma_addr,
1111 MPI_SGE_LENGTH(flagslength));
1112 }
1113
1114 pSge->Address.High = cpu_to_le32(tmp);
1115 pSge->FlagsLength = cpu_to_le32(
1116 (flagslength | MPT_SGE_FLAGS_64_BIT_ADDRESSING));
1117}
1118
1119/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
1120/**
1121 * mpt_add_chain - Place a 32 bit chain SGE at address pAddr.
1122 * @pAddr: virtual address for SGE
1123 * @next: nextChainOffset value (u32's)
1124 * @length: length of next SGL segment
1125 * @dma_addr: Physical address
1126 *
1127 */
1128static void
1129mpt_add_chain(void *pAddr, u8 next, u16 length, dma_addr_t dma_addr)
1130{
1131 SGEChain32_t *pChain = (SGEChain32_t *) pAddr;
1132 pChain->Length = cpu_to_le16(length);
1133 pChain->Flags = MPI_SGE_FLAGS_CHAIN_ELEMENT;
1134 pChain->NextChainOffset = next;
1135 pChain->Address = cpu_to_le32(dma_addr);
1136}
1137
1138/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
1139/**
1140 * mpt_add_chain_64bit - Place a 64 bit chain SGE at address pAddr.
1141 * @pAddr: virtual address for SGE
1142 * @next: nextChainOffset value (u32's)
1143 * @length: length of next SGL segment
1144 * @dma_addr: Physical address
1145 *
1146 */
1147static void
1148mpt_add_chain_64bit(void *pAddr, u8 next, u16 length, dma_addr_t dma_addr)
1149{
1150 SGEChain64_t *pChain = (SGEChain64_t *) pAddr;
1151 u32 tmp = dma_addr & 0xFFFFFFFF;
1152
1153 pChain->Length = cpu_to_le16(length);
1154 pChain->Flags = (MPI_SGE_FLAGS_CHAIN_ELEMENT |
1155 MPI_SGE_FLAGS_64_BIT_ADDRESSING);
1156
1157 pChain->NextChainOffset = next;
1158
1159 pChain->Address.Low = cpu_to_le32(tmp);
1160 tmp = (u32)(upper_32_bits(dma_addr));
1161 pChain->Address.High = cpu_to_le32(tmp);
1162}
1163
1164/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
1165/**
1166 * mpt_send_handshake_request - Send MPT request via doorbell handshake method.
1167 * @cb_idx: Handle of registered MPT protocol driver
1168 * @ioc: Pointer to MPT adapter structure
1169 * @reqBytes: Size of the request in bytes
1170 * @req: Pointer to MPT request frame
1171 * @sleepFlag: Use schedule if CAN_SLEEP else use udelay.
1172 *
1173 * This routine is used exclusively to send MptScsiTaskMgmt
1174 * requests since they are required to be sent via doorbell handshake.
1175 *
1176 * NOTE: It is the callers responsibility to byte-swap fields in the
1177 * request which are greater than 1 byte in size.
1178 *
1179 * Returns 0 for success, non-zero for failure.
1180 */
1181int
1182mpt_send_handshake_request(u8 cb_idx, MPT_ADAPTER *ioc, int reqBytes, u32 *req, int sleepFlag)
1183{
1184 int r = 0;
1185 u8 *req_as_bytes;
1186 int ii;
1187
1188 /* State is known to be good upon entering
1189 * this function so issue the bus reset
1190 * request.
1191 */
1192
1193 /*
1194 * Emulate what mpt_put_msg_frame() does /wrt to sanity
1195 * setting cb_idx/req_idx. But ONLY if this request
1196 * is in proper (pre-alloc'd) request buffer range...
1197 */
1198 ii = MFPTR_2_MPT_INDEX(ioc,(MPT_FRAME_HDR*)req);
1199 if (reqBytes >= 12 && ii >= 0 && ii < ioc->req_depth) {
1200 MPT_FRAME_HDR *mf = (MPT_FRAME_HDR*)req;
1201 mf->u.frame.hwhdr.msgctxu.fld.req_idx = cpu_to_le16(ii);
1202 mf->u.frame.hwhdr.msgctxu.fld.cb_idx = cb_idx;
1203 }
1204
1205 /* Make sure there are no doorbells */
1206 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
1207
1208 CHIPREG_WRITE32(&ioc->chip->Doorbell,
1209 ((MPI_FUNCTION_HANDSHAKE<<MPI_DOORBELL_FUNCTION_SHIFT) |
1210 ((reqBytes/4)<<MPI_DOORBELL_ADD_DWORDS_SHIFT)));
1211
1212 /* Wait for IOC doorbell int */
1213 if ((ii = WaitForDoorbellInt(ioc, 5, sleepFlag)) < 0) {
1214 return ii;
1215 }
1216
1217 /* Read doorbell and check for active bit */
1218 if (!(CHIPREG_READ32(&ioc->chip->Doorbell) & MPI_DOORBELL_ACTIVE))
1219 return -5;
1220
1221 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "mpt_send_handshake_request start, WaitCnt=%d\n",
1222 ioc->name, ii));
1223
1224 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
1225
1226 if ((r = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0) {
1227 return -2;
1228 }
1229
1230 /* Send request via doorbell handshake */
1231 req_as_bytes = (u8 *) req;
1232 for (ii = 0; ii < reqBytes/4; ii++) {
1233 u32 word;
1234
1235 word = ((req_as_bytes[(ii*4) + 0] << 0) |
1236 (req_as_bytes[(ii*4) + 1] << 8) |
1237 (req_as_bytes[(ii*4) + 2] << 16) |
1238 (req_as_bytes[(ii*4) + 3] << 24));
1239 CHIPREG_WRITE32(&ioc->chip->Doorbell, word);
1240 if ((r = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0) {
1241 r = -3;
1242 break;
1243 }
1244 }
1245
1246 if (r >= 0 && WaitForDoorbellInt(ioc, 10, sleepFlag) >= 0)
1247 r = 0;
1248 else
1249 r = -4;
1250
1251 /* Make sure there are no doorbells */
1252 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
1253
1254 return r;
1255}
1256
1257/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
1258/**
1259 * mpt_host_page_access_control - control the IOC's Host Page Buffer access
1260 * @ioc: Pointer to MPT adapter structure
1261 * @access_control_value: define bits below
1262 * @sleepFlag: Specifies whether the process can sleep
1263 *
1264 * Provides mechanism for the host driver to control the IOC's
1265 * Host Page Buffer access.
1266 *
1267 * Access Control Value - bits[15:12]
1268 * 0h Reserved
1269 * 1h Enable Access { MPI_DB_HPBAC_ENABLE_ACCESS }
1270 * 2h Disable Access { MPI_DB_HPBAC_DISABLE_ACCESS }
1271 * 3h Free Buffer { MPI_DB_HPBAC_FREE_BUFFER }
1272 *
1273 * Returns 0 for success, non-zero for failure.
1274 */
1275
1276static int
1277mpt_host_page_access_control(MPT_ADAPTER *ioc, u8 access_control_value, int sleepFlag)
1278{
1279 int r = 0;
1280
1281 /* return if in use */
1282 if (CHIPREG_READ32(&ioc->chip->Doorbell)
1283 & MPI_DOORBELL_ACTIVE)
1284 return -1;
1285
1286 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
1287
1288 CHIPREG_WRITE32(&ioc->chip->Doorbell,
1289 ((MPI_FUNCTION_HOST_PAGEBUF_ACCESS_CONTROL
1290 <<MPI_DOORBELL_FUNCTION_SHIFT) |
1291 (access_control_value<<12)));
1292
1293 /* Wait for IOC to clear Doorbell Status bit */
1294 if ((r = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0) {
1295 return -2;
1296 }else
1297 return 0;
1298}
1299
1300/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
1301/**
1302 * mpt_host_page_alloc - allocate system memory for the fw
1303 * @ioc: Pointer to pointer to IOC adapter
1304 * @ioc_init: Pointer to ioc init config page
1305 *
1306 * If we already allocated memory in past, then resend the same pointer.
1307 * Returns 0 for success, non-zero for failure.
1308 */
1309static int
1310mpt_host_page_alloc(MPT_ADAPTER *ioc, pIOCInit_t ioc_init)
1311{
1312 char *psge;
1313 int flags_length;
1314 u32 host_page_buffer_sz=0;
1315
1316 if(!ioc->HostPageBuffer) {
1317
1318 host_page_buffer_sz =
1319 le32_to_cpu(ioc->facts.HostPageBufferSGE.FlagsLength) & 0xFFFFFF;
1320
1321 if(!host_page_buffer_sz)
1322 return 0; /* fw doesn't need any host buffers */
1323
1324 /* spin till we get enough memory */
1325 while(host_page_buffer_sz > 0) {
1326
1327 if((ioc->HostPageBuffer = pci_alloc_consistent(
1328 ioc->pcidev,
1329 host_page_buffer_sz,
1330 &ioc->HostPageBuffer_dma)) != NULL) {
1331
1332 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT
1333 "host_page_buffer @ %p, dma @ %x, sz=%d bytes\n",
1334 ioc->name, ioc->HostPageBuffer,
1335 (u32)ioc->HostPageBuffer_dma,
1336 host_page_buffer_sz));
1337 ioc->alloc_total += host_page_buffer_sz;
1338 ioc->HostPageBuffer_sz = host_page_buffer_sz;
1339 break;
1340 }
1341
1342 host_page_buffer_sz -= (4*1024);
1343 }
1344 }
1345
1346 if(!ioc->HostPageBuffer) {
1347 printk(MYIOC_s_ERR_FMT
1348 "Failed to alloc memory for host_page_buffer!\n",
1349 ioc->name);
1350 return -999;
1351 }
1352
1353 psge = (char *)&ioc_init->HostPageBufferSGE;
1354 flags_length = MPI_SGE_FLAGS_SIMPLE_ELEMENT |
1355 MPI_SGE_FLAGS_SYSTEM_ADDRESS |
1356 MPI_SGE_FLAGS_HOST_TO_IOC |
1357 MPI_SGE_FLAGS_END_OF_BUFFER;
1358 flags_length = flags_length << MPI_SGE_FLAGS_SHIFT;
1359 flags_length |= ioc->HostPageBuffer_sz;
1360 ioc->add_sge(psge, flags_length, ioc->HostPageBuffer_dma);
1361 ioc->facts.HostPageBufferSGE = ioc_init->HostPageBufferSGE;
1362
1363return 0;
1364}
1365
1366/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
1367/**
1368 * mpt_verify_adapter - Given IOC identifier, set pointer to its adapter structure.
1369 * @iocid: IOC unique identifier (integer)
1370 * @iocpp: Pointer to pointer to IOC adapter
1371 *
1372 * Given a unique IOC identifier, set pointer to the associated MPT
1373 * adapter structure.
1374 *
1375 * Returns iocid and sets iocpp if iocid is found.
1376 * Returns -1 if iocid is not found.
1377 */
1378int
1379mpt_verify_adapter(int iocid, MPT_ADAPTER **iocpp)
1380{
1381 MPT_ADAPTER *ioc;
1382
1383 list_for_each_entry(ioc,&ioc_list,list) {
1384 if (ioc->id == iocid) {
1385 *iocpp =ioc;
1386 return iocid;
1387 }
1388 }
1389
1390 *iocpp = NULL;
1391 return -1;
1392}
1393
1394/**
1395 * mpt_get_product_name - returns product string
1396 * @vendor: pci vendor id
1397 * @device: pci device id
1398 * @revision: pci revision id
1399 *
1400 * Returns product string displayed when driver loads,
1401 * in /proc/mpt/summary and /sysfs/class/scsi_host/host<X>/version_product
1402 *
1403 **/
1404static const char*
1405mpt_get_product_name(u16 vendor, u16 device, u8 revision)
1406{
1407 char *product_str = NULL;
1408
1409 if (vendor == PCI_VENDOR_ID_BROCADE) {
1410 switch (device)
1411 {
1412 case MPI_MANUFACTPAGE_DEVICEID_FC949E:
1413 switch (revision)
1414 {
1415 case 0x00:
1416 product_str = "BRE040 A0";
1417 break;
1418 case 0x01:
1419 product_str = "BRE040 A1";
1420 break;
1421 default:
1422 product_str = "BRE040";
1423 break;
1424 }
1425 break;
1426 }
1427 goto out;
1428 }
1429
1430 switch (device)
1431 {
1432 case MPI_MANUFACTPAGE_DEVICEID_FC909:
1433 product_str = "LSIFC909 B1";
1434 break;
1435 case MPI_MANUFACTPAGE_DEVICEID_FC919:
1436 product_str = "LSIFC919 B0";
1437 break;
1438 case MPI_MANUFACTPAGE_DEVICEID_FC929:
1439 product_str = "LSIFC929 B0";
1440 break;
1441 case MPI_MANUFACTPAGE_DEVICEID_FC919X:
1442 if (revision < 0x80)
1443 product_str = "LSIFC919X A0";
1444 else
1445 product_str = "LSIFC919XL A1";
1446 break;
1447 case MPI_MANUFACTPAGE_DEVICEID_FC929X:
1448 if (revision < 0x80)
1449 product_str = "LSIFC929X A0";
1450 else
1451 product_str = "LSIFC929XL A1";
1452 break;
1453 case MPI_MANUFACTPAGE_DEVICEID_FC939X:
1454 product_str = "LSIFC939X A1";
1455 break;
1456 case MPI_MANUFACTPAGE_DEVICEID_FC949X:
1457 product_str = "LSIFC949X A1";
1458 break;
1459 case MPI_MANUFACTPAGE_DEVICEID_FC949E:
1460 switch (revision)
1461 {
1462 case 0x00:
1463 product_str = "LSIFC949E A0";
1464 break;
1465 case 0x01:
1466 product_str = "LSIFC949E A1";
1467 break;
1468 default:
1469 product_str = "LSIFC949E";
1470 break;
1471 }
1472 break;
1473 case MPI_MANUFACTPAGE_DEVID_53C1030:
1474 switch (revision)
1475 {
1476 case 0x00:
1477 product_str = "LSI53C1030 A0";
1478 break;
1479 case 0x01:
1480 product_str = "LSI53C1030 B0";
1481 break;
1482 case 0x03:
1483 product_str = "LSI53C1030 B1";
1484 break;
1485 case 0x07:
1486 product_str = "LSI53C1030 B2";
1487 break;
1488 case 0x08:
1489 product_str = "LSI53C1030 C0";
1490 break;
1491 case 0x80:
1492 product_str = "LSI53C1030T A0";
1493 break;
1494 case 0x83:
1495 product_str = "LSI53C1030T A2";
1496 break;
1497 case 0x87:
1498 product_str = "LSI53C1030T A3";
1499 break;
1500 case 0xc1:
1501 product_str = "LSI53C1020A A1";
1502 break;
1503 default:
1504 product_str = "LSI53C1030";
1505 break;
1506 }
1507 break;
1508 case MPI_MANUFACTPAGE_DEVID_1030_53C1035:
1509 switch (revision)
1510 {
1511 case 0x03:
1512 product_str = "LSI53C1035 A2";
1513 break;
1514 case 0x04:
1515 product_str = "LSI53C1035 B0";
1516 break;
1517 default:
1518 product_str = "LSI53C1035";
1519 break;
1520 }
1521 break;
1522 case MPI_MANUFACTPAGE_DEVID_SAS1064:
1523 switch (revision)
1524 {
1525 case 0x00:
1526 product_str = "LSISAS1064 A1";
1527 break;
1528 case 0x01:
1529 product_str = "LSISAS1064 A2";
1530 break;
1531 case 0x02:
1532 product_str = "LSISAS1064 A3";
1533 break;
1534 case 0x03:
1535 product_str = "LSISAS1064 A4";
1536 break;
1537 default:
1538 product_str = "LSISAS1064";
1539 break;
1540 }
1541 break;
1542 case MPI_MANUFACTPAGE_DEVID_SAS1064E:
1543 switch (revision)
1544 {
1545 case 0x00:
1546 product_str = "LSISAS1064E A0";
1547 break;
1548 case 0x01:
1549 product_str = "LSISAS1064E B0";
1550 break;
1551 case 0x02:
1552 product_str = "LSISAS1064E B1";
1553 break;
1554 case 0x04:
1555 product_str = "LSISAS1064E B2";
1556 break;
1557 case 0x08:
1558 product_str = "LSISAS1064E B3";
1559 break;
1560 default:
1561 product_str = "LSISAS1064E";
1562 break;
1563 }
1564 break;
1565 case MPI_MANUFACTPAGE_DEVID_SAS1068:
1566 switch (revision)
1567 {
1568 case 0x00:
1569 product_str = "LSISAS1068 A0";
1570 break;
1571 case 0x01:
1572 product_str = "LSISAS1068 B0";
1573 break;
1574 case 0x02:
1575 product_str = "LSISAS1068 B1";
1576 break;
1577 default:
1578 product_str = "LSISAS1068";
1579 break;
1580 }
1581 break;
1582 case MPI_MANUFACTPAGE_DEVID_SAS1068E:
1583 switch (revision)
1584 {
1585 case 0x00:
1586 product_str = "LSISAS1068E A0";
1587 break;
1588 case 0x01:
1589 product_str = "LSISAS1068E B0";
1590 break;
1591 case 0x02:
1592 product_str = "LSISAS1068E B1";
1593 break;
1594 case 0x04:
1595 product_str = "LSISAS1068E B2";
1596 break;
1597 case 0x08:
1598 product_str = "LSISAS1068E B3";
1599 break;
1600 default:
1601 product_str = "LSISAS1068E";
1602 break;
1603 }
1604 break;
1605 case MPI_MANUFACTPAGE_DEVID_SAS1078:
1606 switch (revision)
1607 {
1608 case 0x00:
1609 product_str = "LSISAS1078 A0";
1610 break;
1611 case 0x01:
1612 product_str = "LSISAS1078 B0";
1613 break;
1614 case 0x02:
1615 product_str = "LSISAS1078 C0";
1616 break;
1617 case 0x03:
1618 product_str = "LSISAS1078 C1";
1619 break;
1620 case 0x04:
1621 product_str = "LSISAS1078 C2";
1622 break;
1623 default:
1624 product_str = "LSISAS1078";
1625 break;
1626 }
1627 break;
1628 }
1629
1630 out:
1631 return product_str;
1632}
1633
1634/**
1635 * mpt_mapresources - map in memory mapped io
1636 * @ioc: Pointer to pointer to IOC adapter
1637 *
1638 **/
1639static int
1640mpt_mapresources(MPT_ADAPTER *ioc)
1641{
1642 u8 __iomem *mem;
1643 int ii;
1644 resource_size_t mem_phys;
1645 unsigned long port;
1646 u32 msize;
1647 u32 psize;
1648 int r = -ENODEV;
1649 struct pci_dev *pdev;
1650
1651 pdev = ioc->pcidev;
1652 ioc->bars = pci_select_bars(pdev, IORESOURCE_MEM);
1653 if (pci_enable_device_mem(pdev)) {
1654 printk(MYIOC_s_ERR_FMT "pci_enable_device_mem() "
1655 "failed\n", ioc->name);
1656 return r;
1657 }
1658 if (pci_request_selected_regions(pdev, ioc->bars, "mpt")) {
1659 printk(MYIOC_s_ERR_FMT "pci_request_selected_regions() with "
1660 "MEM failed\n", ioc->name);
1661 goto out_pci_disable_device;
1662 }
1663
1664 if (sizeof(dma_addr_t) > 4) {
1665 const uint64_t required_mask = dma_get_required_mask
1666 (&pdev->dev);
1667 if (required_mask > DMA_BIT_MASK(32)
1668 && !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
1669 && !pci_set_consistent_dma_mask(pdev,
1670 DMA_BIT_MASK(64))) {
1671 ioc->dma_mask = DMA_BIT_MASK(64);
1672 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT
1673 ": 64 BIT PCI BUS DMA ADDRESSING SUPPORTED\n",
1674 ioc->name));
1675 } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))
1676 && !pci_set_consistent_dma_mask(pdev,
1677 DMA_BIT_MASK(32))) {
1678 ioc->dma_mask = DMA_BIT_MASK(32);
1679 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT
1680 ": 32 BIT PCI BUS DMA ADDRESSING SUPPORTED\n",
1681 ioc->name));
1682 } else {
1683 printk(MYIOC_s_WARN_FMT "no suitable DMA mask for %s\n",
1684 ioc->name, pci_name(pdev));
1685 goto out_pci_release_region;
1686 }
1687 } else {
1688 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))
1689 && !pci_set_consistent_dma_mask(pdev,
1690 DMA_BIT_MASK(32))) {
1691 ioc->dma_mask = DMA_BIT_MASK(32);
1692 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT
1693 ": 32 BIT PCI BUS DMA ADDRESSING SUPPORTED\n",
1694 ioc->name));
1695 } else {
1696 printk(MYIOC_s_WARN_FMT "no suitable DMA mask for %s\n",
1697 ioc->name, pci_name(pdev));
1698 goto out_pci_release_region;
1699 }
1700 }
1701
1702 mem_phys = msize = 0;
1703 port = psize = 0;
1704 for (ii = 0; ii < DEVICE_COUNT_RESOURCE; ii++) {
1705 if (pci_resource_flags(pdev, ii) & PCI_BASE_ADDRESS_SPACE_IO) {
1706 if (psize)
1707 continue;
1708 /* Get I/O space! */
1709 port = pci_resource_start(pdev, ii);
1710 psize = pci_resource_len(pdev, ii);
1711 } else {
1712 if (msize)
1713 continue;
1714 /* Get memmap */
1715 mem_phys = pci_resource_start(pdev, ii);
1716 msize = pci_resource_len(pdev, ii);
1717 }
1718 }
1719 ioc->mem_size = msize;
1720
1721 mem = NULL;
1722 /* Get logical ptr for PciMem0 space */
1723 /*mem = ioremap(mem_phys, msize);*/
1724 mem = ioremap(mem_phys, msize);
1725 if (mem == NULL) {
1726 printk(MYIOC_s_ERR_FMT ": ERROR - Unable to map adapter"
1727 " memory!\n", ioc->name);
1728 r = -EINVAL;
1729 goto out_pci_release_region;
1730 }
1731 ioc->memmap = mem;
1732 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT "mem = %p, mem_phys = %llx\n",
1733 ioc->name, mem, (unsigned long long)mem_phys));
1734
1735 ioc->mem_phys = mem_phys;
1736 ioc->chip = (SYSIF_REGS __iomem *)mem;
1737
1738 /* Save Port IO values in case we need to do downloadboot */
1739 ioc->pio_mem_phys = port;
1740 ioc->pio_chip = (SYSIF_REGS __iomem *)port;
1741
1742 return 0;
1743
1744out_pci_release_region:
1745 pci_release_selected_regions(pdev, ioc->bars);
1746out_pci_disable_device:
1747 pci_disable_device(pdev);
1748 return r;
1749}
1750
1751/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
1752/**
1753 * mpt_attach - Install a PCI intelligent MPT adapter.
1754 * @pdev: Pointer to pci_dev structure
1755 * @id: PCI device ID information
1756 *
1757 * This routine performs all the steps necessary to bring the IOC of
1758 * a MPT adapter to a OPERATIONAL state. This includes registering
1759 * memory regions, registering the interrupt, and allocating request
1760 * and reply memory pools.
1761 *
1762 * This routine also pre-fetches the LAN MAC address of a Fibre Channel
1763 * MPT adapter.
1764 *
1765 * Returns 0 for success, non-zero for failure.
1766 *
1767 * TODO: Add support for polled controllers
1768 */
1769int
1770mpt_attach(struct pci_dev *pdev, const struct pci_device_id *id)
1771{
1772 MPT_ADAPTER *ioc;
1773 u8 cb_idx;
1774 int r = -ENODEV;
1775 u8 pcixcmd;
1776 static int mpt_ids = 0;
1777#ifdef CONFIG_PROC_FS
1778 struct proc_dir_entry *dent;
1779#endif
1780
1781 ioc = kzalloc(sizeof(MPT_ADAPTER), GFP_ATOMIC);
1782 if (ioc == NULL) {
1783 printk(KERN_ERR MYNAM ": ERROR - Insufficient memory to add adapter!\n");
1784 return -ENOMEM;
1785 }
1786
1787 ioc->id = mpt_ids++;
1788 sprintf(ioc->name, "ioc%d", ioc->id);
1789 dinitprintk(ioc, printk(KERN_WARNING MYNAM ": mpt_adapter_install\n"));
1790
1791 /*
1792 * set initial debug level
1793 * (refer to mptdebug.h)
1794 *
1795 */
1796 ioc->debug_level = mpt_debug_level;
1797 if (mpt_debug_level)
1798 printk(KERN_INFO "mpt_debug_level=%xh\n", mpt_debug_level);
1799
1800 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT ": mpt_adapter_install\n", ioc->name));
1801
1802 ioc->pcidev = pdev;
1803 if (mpt_mapresources(ioc)) {
1804 goto out_free_ioc;
1805 }
1806
1807 /*
1808 * Setting up proper handlers for scatter gather handling
1809 */
1810 if (ioc->dma_mask == DMA_BIT_MASK(64)) {
1811 if (pdev->device == MPI_MANUFACTPAGE_DEVID_SAS1078)
1812 ioc->add_sge = &mpt_add_sge_64bit_1078;
1813 else
1814 ioc->add_sge = &mpt_add_sge_64bit;
1815 ioc->add_chain = &mpt_add_chain_64bit;
1816 ioc->sg_addr_size = 8;
1817 } else {
1818 ioc->add_sge = &mpt_add_sge;
1819 ioc->add_chain = &mpt_add_chain;
1820 ioc->sg_addr_size = 4;
1821 }
1822 ioc->SGE_size = sizeof(u32) + ioc->sg_addr_size;
1823
1824 ioc->alloc_total = sizeof(MPT_ADAPTER);
1825 ioc->req_sz = MPT_DEFAULT_FRAME_SIZE; /* avoid div by zero! */
1826 ioc->reply_sz = MPT_REPLY_FRAME_SIZE;
1827
1828
1829 spin_lock_init(&ioc->taskmgmt_lock);
1830 mutex_init(&ioc->internal_cmds.mutex);
1831 init_completion(&ioc->internal_cmds.done);
1832 mutex_init(&ioc->mptbase_cmds.mutex);
1833 init_completion(&ioc->mptbase_cmds.done);
1834 mutex_init(&ioc->taskmgmt_cmds.mutex);
1835 init_completion(&ioc->taskmgmt_cmds.done);
1836
1837 /* Initialize the event logging.
1838 */
1839 ioc->eventTypes = 0; /* None */
1840 ioc->eventContext = 0;
1841 ioc->eventLogSize = 0;
1842 ioc->events = NULL;
1843
1844#ifdef MFCNT
1845 ioc->mfcnt = 0;
1846#endif
1847
1848 ioc->sh = NULL;
1849 ioc->cached_fw = NULL;
1850
1851 /* Initialize SCSI Config Data structure
1852 */
1853 memset(&ioc->spi_data, 0, sizeof(SpiCfgData));
1854
1855 /* Initialize the fc rport list head.
1856 */
1857 INIT_LIST_HEAD(&ioc->fc_rports);
1858
1859 /* Find lookup slot. */
1860 INIT_LIST_HEAD(&ioc->list);
1861
1862
1863 /* Initialize workqueue */
1864 INIT_DELAYED_WORK(&ioc->fault_reset_work, mpt_fault_reset_work);
1865
1866 snprintf(ioc->reset_work_q_name, MPT_KOBJ_NAME_LEN,
1867 "mpt_poll_%d", ioc->id);
1868 ioc->reset_work_q = alloc_workqueue(ioc->reset_work_q_name,
1869 WQ_MEM_RECLAIM, 0);
1870 if (!ioc->reset_work_q) {
1871 printk(MYIOC_s_ERR_FMT "Insufficient memory to add adapter!\n",
1872 ioc->name);
1873 r = -ENOMEM;
1874 goto out_unmap_resources;
1875 }
1876
1877 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT "facts @ %p, pfacts[0] @ %p\n",
1878 ioc->name, &ioc->facts, &ioc->pfacts[0]));
1879
1880 ioc->prod_name = mpt_get_product_name(pdev->vendor, pdev->device,
1881 pdev->revision);
1882
1883 switch (pdev->device)
1884 {
1885 case MPI_MANUFACTPAGE_DEVICEID_FC939X:
1886 case MPI_MANUFACTPAGE_DEVICEID_FC949X:
1887 ioc->errata_flag_1064 = 1;
1888 case MPI_MANUFACTPAGE_DEVICEID_FC909:
1889 case MPI_MANUFACTPAGE_DEVICEID_FC929:
1890 case MPI_MANUFACTPAGE_DEVICEID_FC919:
1891 case MPI_MANUFACTPAGE_DEVICEID_FC949E:
1892 ioc->bus_type = FC;
1893 break;
1894
1895 case MPI_MANUFACTPAGE_DEVICEID_FC929X:
1896 if (pdev->revision < XL_929) {
1897 /* 929X Chip Fix. Set Split transactions level
1898 * for PCIX. Set MOST bits to zero.
1899 */
1900 pci_read_config_byte(pdev, 0x6a, &pcixcmd);
1901 pcixcmd &= 0x8F;
1902 pci_write_config_byte(pdev, 0x6a, pcixcmd);
1903 } else {
1904 /* 929XL Chip Fix. Set MMRBC to 0x08.
1905 */
1906 pci_read_config_byte(pdev, 0x6a, &pcixcmd);
1907 pcixcmd |= 0x08;
1908 pci_write_config_byte(pdev, 0x6a, pcixcmd);
1909 }
1910 ioc->bus_type = FC;
1911 break;
1912
1913 case MPI_MANUFACTPAGE_DEVICEID_FC919X:
1914 /* 919X Chip Fix. Set Split transactions level
1915 * for PCIX. Set MOST bits to zero.
1916 */
1917 pci_read_config_byte(pdev, 0x6a, &pcixcmd);
1918 pcixcmd &= 0x8F;
1919 pci_write_config_byte(pdev, 0x6a, pcixcmd);
1920 ioc->bus_type = FC;
1921 break;
1922
1923 case MPI_MANUFACTPAGE_DEVID_53C1030:
1924 /* 1030 Chip Fix. Disable Split transactions
1925 * for PCIX. Set MOST bits to zero if Rev < C0( = 8).
1926 */
1927 if (pdev->revision < C0_1030) {
1928 pci_read_config_byte(pdev, 0x6a, &pcixcmd);
1929 pcixcmd &= 0x8F;
1930 pci_write_config_byte(pdev, 0x6a, pcixcmd);
1931 }
1932
1933 case MPI_MANUFACTPAGE_DEVID_1030_53C1035:
1934 ioc->bus_type = SPI;
1935 break;
1936
1937 case MPI_MANUFACTPAGE_DEVID_SAS1064:
1938 case MPI_MANUFACTPAGE_DEVID_SAS1068:
1939 ioc->errata_flag_1064 = 1;
1940 ioc->bus_type = SAS;
1941 break;
1942
1943 case MPI_MANUFACTPAGE_DEVID_SAS1064E:
1944 case MPI_MANUFACTPAGE_DEVID_SAS1068E:
1945 case MPI_MANUFACTPAGE_DEVID_SAS1078:
1946 ioc->bus_type = SAS;
1947 break;
1948 }
1949
1950
1951 switch (ioc->bus_type) {
1952
1953 case SAS:
1954 ioc->msi_enable = mpt_msi_enable_sas;
1955 break;
1956
1957 case SPI:
1958 ioc->msi_enable = mpt_msi_enable_spi;
1959 break;
1960
1961 case FC:
1962 ioc->msi_enable = mpt_msi_enable_fc;
1963 break;
1964
1965 default:
1966 ioc->msi_enable = 0;
1967 break;
1968 }
1969
1970 ioc->fw_events_off = 1;
1971
1972 if (ioc->errata_flag_1064)
1973 pci_disable_io_access(pdev);
1974
1975 spin_lock_init(&ioc->FreeQlock);
1976
1977 /* Disable all! */
1978 CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF);
1979 ioc->active = 0;
1980 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
1981
1982 /* Set IOC ptr in the pcidev's driver data. */
1983 pci_set_drvdata(ioc->pcidev, ioc);
1984
1985 /* Set lookup ptr. */
1986 list_add_tail(&ioc->list, &ioc_list);
1987
1988 /* Check for "bound ports" (929, 929X, 1030, 1035) to reduce redundant resets.
1989 */
1990 mpt_detect_bound_ports(ioc, pdev);
1991
1992 INIT_LIST_HEAD(&ioc->fw_event_list);
1993 spin_lock_init(&ioc->fw_event_lock);
1994 snprintf(ioc->fw_event_q_name, MPT_KOBJ_NAME_LEN, "mpt/%d", ioc->id);
1995 ioc->fw_event_q = alloc_workqueue(ioc->fw_event_q_name,
1996 WQ_MEM_RECLAIM, 0);
1997 if (!ioc->fw_event_q) {
1998 printk(MYIOC_s_ERR_FMT "Insufficient memory to add adapter!\n",
1999 ioc->name);
2000 r = -ENOMEM;
2001 goto out_remove_ioc;
2002 }
2003
2004 if ((r = mpt_do_ioc_recovery(ioc, MPT_HOSTEVENT_IOC_BRINGUP,
2005 CAN_SLEEP)) != 0){
2006 printk(MYIOC_s_ERR_FMT "didn't initialize properly! (%d)\n",
2007 ioc->name, r);
2008
2009 destroy_workqueue(ioc->fw_event_q);
2010 ioc->fw_event_q = NULL;
2011
2012 list_del(&ioc->list);
2013 if (ioc->alt_ioc)
2014 ioc->alt_ioc->alt_ioc = NULL;
2015 iounmap(ioc->memmap);
2016 if (pci_is_enabled(pdev))
2017 pci_disable_device(pdev);
2018 if (r != -5)
2019 pci_release_selected_regions(pdev, ioc->bars);
2020
2021 destroy_workqueue(ioc->reset_work_q);
2022 ioc->reset_work_q = NULL;
2023
2024 kfree(ioc);
2025 return r;
2026 }
2027
2028 /* call per device driver probe entry point */
2029 for(cb_idx = 0; cb_idx < MPT_MAX_PROTOCOL_DRIVERS; cb_idx++) {
2030 if(MptDeviceDriverHandlers[cb_idx] &&
2031 MptDeviceDriverHandlers[cb_idx]->probe) {
2032 MptDeviceDriverHandlers[cb_idx]->probe(pdev,id);
2033 }
2034 }
2035
2036#ifdef CONFIG_PROC_FS
2037 /*
2038 * Create "/proc/mpt/iocN" subdirectory entry for each MPT adapter.
2039 */
2040 dent = proc_mkdir(ioc->name, mpt_proc_root_dir);
2041 if (dent) {
2042 proc_create_data("info", S_IRUGO, dent, &mpt_iocinfo_proc_fops, ioc);
2043 proc_create_data("summary", S_IRUGO, dent, &mpt_summary_proc_fops, ioc);
2044 }
2045#endif
2046
2047 if (!ioc->alt_ioc)
2048 queue_delayed_work(ioc->reset_work_q, &ioc->fault_reset_work,
2049 msecs_to_jiffies(MPT_POLLING_INTERVAL));
2050
2051 return 0;
2052
2053out_remove_ioc:
2054 list_del(&ioc->list);
2055 if (ioc->alt_ioc)
2056 ioc->alt_ioc->alt_ioc = NULL;
2057
2058 destroy_workqueue(ioc->reset_work_q);
2059 ioc->reset_work_q = NULL;
2060
2061out_unmap_resources:
2062 iounmap(ioc->memmap);
2063 pci_disable_device(pdev);
2064 pci_release_selected_regions(pdev, ioc->bars);
2065
2066out_free_ioc:
2067 kfree(ioc);
2068
2069 return r;
2070}
2071
2072/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
2073/**
2074 * mpt_detach - Remove a PCI intelligent MPT adapter.
2075 * @pdev: Pointer to pci_dev structure
2076 */
2077
2078void
2079mpt_detach(struct pci_dev *pdev)
2080{
2081 MPT_ADAPTER *ioc = pci_get_drvdata(pdev);
2082 char pname[32];
2083 u8 cb_idx;
2084 unsigned long flags;
2085 struct workqueue_struct *wq;
2086
2087 /*
2088 * Stop polling ioc for fault condition
2089 */
2090 spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
2091 wq = ioc->reset_work_q;
2092 ioc->reset_work_q = NULL;
2093 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
2094 cancel_delayed_work(&ioc->fault_reset_work);
2095 destroy_workqueue(wq);
2096
2097 spin_lock_irqsave(&ioc->fw_event_lock, flags);
2098 wq = ioc->fw_event_q;
2099 ioc->fw_event_q = NULL;
2100 spin_unlock_irqrestore(&ioc->fw_event_lock, flags);
2101 destroy_workqueue(wq);
2102
2103 sprintf(pname, MPT_PROCFS_MPTBASEDIR "/%s/summary", ioc->name);
2104 remove_proc_entry(pname, NULL);
2105 sprintf(pname, MPT_PROCFS_MPTBASEDIR "/%s/info", ioc->name);
2106 remove_proc_entry(pname, NULL);
2107 sprintf(pname, MPT_PROCFS_MPTBASEDIR "/%s", ioc->name);
2108 remove_proc_entry(pname, NULL);
2109
2110 /* call per device driver remove entry point */
2111 for(cb_idx = 0; cb_idx < MPT_MAX_PROTOCOL_DRIVERS; cb_idx++) {
2112 if(MptDeviceDriverHandlers[cb_idx] &&
2113 MptDeviceDriverHandlers[cb_idx]->remove) {
2114 MptDeviceDriverHandlers[cb_idx]->remove(pdev);
2115 }
2116 }
2117
2118 /* Disable interrupts! */
2119 CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF);
2120
2121 ioc->active = 0;
2122 synchronize_irq(pdev->irq);
2123
2124 /* Clear any lingering interrupt */
2125 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
2126
2127 CHIPREG_READ32(&ioc->chip->IntStatus);
2128
2129 mpt_adapter_dispose(ioc);
2130
2131}
2132
2133/**************************************************************************
2134 * Power Management
2135 */
2136#ifdef CONFIG_PM
2137/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
2138/**
2139 * mpt_suspend - Fusion MPT base driver suspend routine.
2140 * @pdev: Pointer to pci_dev structure
2141 * @state: new state to enter
2142 */
2143int
2144mpt_suspend(struct pci_dev *pdev, pm_message_t state)
2145{
2146 u32 device_state;
2147 MPT_ADAPTER *ioc = pci_get_drvdata(pdev);
2148
2149 device_state = pci_choose_state(pdev, state);
2150 printk(MYIOC_s_INFO_FMT "pci-suspend: pdev=0x%p, slot=%s, Entering "
2151 "operating state [D%d]\n", ioc->name, pdev, pci_name(pdev),
2152 device_state);
2153
2154 /* put ioc into READY_STATE */
2155 if(SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, CAN_SLEEP)) {
2156 printk(MYIOC_s_ERR_FMT
2157 "pci-suspend: IOC msg unit reset failed!\n", ioc->name);
2158 }
2159
2160 /* disable interrupts */
2161 CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF);
2162 ioc->active = 0;
2163
2164 /* Clear any lingering interrupt */
2165 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
2166
2167 free_irq(ioc->pci_irq, ioc);
2168 if (ioc->msi_enable)
2169 pci_disable_msi(ioc->pcidev);
2170 ioc->pci_irq = -1;
2171 pci_save_state(pdev);
2172 pci_disable_device(pdev);
2173 pci_release_selected_regions(pdev, ioc->bars);
2174 pci_set_power_state(pdev, device_state);
2175 return 0;
2176}
2177
2178/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
2179/**
2180 * mpt_resume - Fusion MPT base driver resume routine.
2181 * @pdev: Pointer to pci_dev structure
2182 */
2183int
2184mpt_resume(struct pci_dev *pdev)
2185{
2186 MPT_ADAPTER *ioc = pci_get_drvdata(pdev);
2187 u32 device_state = pdev->current_state;
2188 int recovery_state;
2189 int err;
2190
2191 printk(MYIOC_s_INFO_FMT "pci-resume: pdev=0x%p, slot=%s, Previous "
2192 "operating state [D%d]\n", ioc->name, pdev, pci_name(pdev),
2193 device_state);
2194
2195 pci_set_power_state(pdev, PCI_D0);
2196 pci_enable_wake(pdev, PCI_D0, 0);
2197 pci_restore_state(pdev);
2198 ioc->pcidev = pdev;
2199 err = mpt_mapresources(ioc);
2200 if (err)
2201 return err;
2202
2203 if (ioc->dma_mask == DMA_BIT_MASK(64)) {
2204 if (pdev->device == MPI_MANUFACTPAGE_DEVID_SAS1078)
2205 ioc->add_sge = &mpt_add_sge_64bit_1078;
2206 else
2207 ioc->add_sge = &mpt_add_sge_64bit;
2208 ioc->add_chain = &mpt_add_chain_64bit;
2209 ioc->sg_addr_size = 8;
2210 } else {
2211
2212 ioc->add_sge = &mpt_add_sge;
2213 ioc->add_chain = &mpt_add_chain;
2214 ioc->sg_addr_size = 4;
2215 }
2216 ioc->SGE_size = sizeof(u32) + ioc->sg_addr_size;
2217
2218 printk(MYIOC_s_INFO_FMT "pci-resume: ioc-state=0x%x,doorbell=0x%x\n",
2219 ioc->name, (mpt_GetIocState(ioc, 1) >> MPI_IOC_STATE_SHIFT),
2220 CHIPREG_READ32(&ioc->chip->Doorbell));
2221
2222 /*
2223 * Errata workaround for SAS pci express:
2224 * Upon returning to the D0 state, the contents of the doorbell will be
2225 * stale data, and this will incorrectly signal to the host driver that
2226 * the firmware is ready to process mpt commands. The workaround is
2227 * to issue a diagnostic reset.
2228 */
2229 if (ioc->bus_type == SAS && (pdev->device ==
2230 MPI_MANUFACTPAGE_DEVID_SAS1068E || pdev->device ==
2231 MPI_MANUFACTPAGE_DEVID_SAS1064E)) {
2232 if (KickStart(ioc, 1, CAN_SLEEP) < 0) {
2233 printk(MYIOC_s_WARN_FMT "pci-resume: Cannot recover\n",
2234 ioc->name);
2235 goto out;
2236 }
2237 }
2238
2239 /* bring ioc to operational state */
2240 printk(MYIOC_s_INFO_FMT "Sending mpt_do_ioc_recovery\n", ioc->name);
2241 recovery_state = mpt_do_ioc_recovery(ioc, MPT_HOSTEVENT_IOC_BRINGUP,
2242 CAN_SLEEP);
2243 if (recovery_state != 0)
2244 printk(MYIOC_s_WARN_FMT "pci-resume: Cannot recover, "
2245 "error:[%x]\n", ioc->name, recovery_state);
2246 else
2247 printk(MYIOC_s_INFO_FMT
2248 "pci-resume: success\n", ioc->name);
2249 out:
2250 return 0;
2251
2252}
2253#endif
2254
2255static int
2256mpt_signal_reset(u8 index, MPT_ADAPTER *ioc, int reset_phase)
2257{
2258 if ((MptDriverClass[index] == MPTSPI_DRIVER &&
2259 ioc->bus_type != SPI) ||
2260 (MptDriverClass[index] == MPTFC_DRIVER &&
2261 ioc->bus_type != FC) ||
2262 (MptDriverClass[index] == MPTSAS_DRIVER &&
2263 ioc->bus_type != SAS))
2264 /* make sure we only call the relevant reset handler
2265 * for the bus */
2266 return 0;
2267 return (MptResetHandlers[index])(ioc, reset_phase);
2268}
2269
2270/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
2271/**
2272 * mpt_do_ioc_recovery - Initialize or recover MPT adapter.
2273 * @ioc: Pointer to MPT adapter structure
2274 * @reason: Event word / reason
2275 * @sleepFlag: Use schedule if CAN_SLEEP else use udelay.
2276 *
2277 * This routine performs all the steps necessary to bring the IOC
2278 * to a OPERATIONAL state.
2279 *
2280 * This routine also pre-fetches the LAN MAC address of a Fibre Channel
2281 * MPT adapter.
2282 *
2283 * Returns:
2284 * 0 for success
2285 * -1 if failed to get board READY
2286 * -2 if READY but IOCFacts Failed
2287 * -3 if READY but PrimeIOCFifos Failed
2288 * -4 if READY but IOCInit Failed
2289 * -5 if failed to enable_device and/or request_selected_regions
2290 * -6 if failed to upload firmware
2291 */
2292static int
2293mpt_do_ioc_recovery(MPT_ADAPTER *ioc, u32 reason, int sleepFlag)
2294{
2295 int hard_reset_done = 0;
2296 int alt_ioc_ready = 0;
2297 int hard;
2298 int rc=0;
2299 int ii;
2300 int ret = 0;
2301 int reset_alt_ioc_active = 0;
2302 int irq_allocated = 0;
2303 u8 *a;
2304
2305 printk(MYIOC_s_INFO_FMT "Initiating %s\n", ioc->name,
2306 reason == MPT_HOSTEVENT_IOC_BRINGUP ? "bringup" : "recovery");
2307
2308 /* Disable reply interrupts (also blocks FreeQ) */
2309 CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF);
2310 ioc->active = 0;
2311
2312 if (ioc->alt_ioc) {
2313 if (ioc->alt_ioc->active ||
2314 reason == MPT_HOSTEVENT_IOC_RECOVER) {
2315 reset_alt_ioc_active = 1;
2316 /* Disable alt-IOC's reply interrupts
2317 * (and FreeQ) for a bit
2318 **/
2319 CHIPREG_WRITE32(&ioc->alt_ioc->chip->IntMask,
2320 0xFFFFFFFF);
2321 ioc->alt_ioc->active = 0;
2322 }
2323 }
2324
2325 hard = 1;
2326 if (reason == MPT_HOSTEVENT_IOC_BRINGUP)
2327 hard = 0;
2328
2329 if ((hard_reset_done = MakeIocReady(ioc, hard, sleepFlag)) < 0) {
2330 if (hard_reset_done == -4) {
2331 printk(MYIOC_s_WARN_FMT "Owned by PEER..skipping!\n",
2332 ioc->name);
2333
2334 if (reset_alt_ioc_active && ioc->alt_ioc) {
2335 /* (re)Enable alt-IOC! (reply interrupt, FreeQ) */
2336 dprintk(ioc, printk(MYIOC_s_INFO_FMT
2337 "alt_ioc reply irq re-enabled\n", ioc->alt_ioc->name));
2338 CHIPREG_WRITE32(&ioc->alt_ioc->chip->IntMask, MPI_HIM_DIM);
2339 ioc->alt_ioc->active = 1;
2340 }
2341
2342 } else {
2343 printk(MYIOC_s_WARN_FMT
2344 "NOT READY WARNING!\n", ioc->name);
2345 }
2346 ret = -1;
2347 goto out;
2348 }
2349
2350 /* hard_reset_done = 0 if a soft reset was performed
2351 * and 1 if a hard reset was performed.
2352 */
2353 if (hard_reset_done && reset_alt_ioc_active && ioc->alt_ioc) {
2354 if ((rc = MakeIocReady(ioc->alt_ioc, 0, sleepFlag)) == 0)
2355 alt_ioc_ready = 1;
2356 else
2357 printk(MYIOC_s_WARN_FMT
2358 ": alt-ioc Not ready WARNING!\n",
2359 ioc->alt_ioc->name);
2360 }
2361
2362 for (ii=0; ii<5; ii++) {
2363 /* Get IOC facts! Allow 5 retries */
2364 if ((rc = GetIocFacts(ioc, sleepFlag, reason)) == 0)
2365 break;
2366 }
2367
2368
2369 if (ii == 5) {
2370 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT
2371 "Retry IocFacts failed rc=%x\n", ioc->name, rc));
2372 ret = -2;
2373 } else if (reason == MPT_HOSTEVENT_IOC_BRINGUP) {
2374 MptDisplayIocCapabilities(ioc);
2375 }
2376
2377 if (alt_ioc_ready) {
2378 if ((rc = GetIocFacts(ioc->alt_ioc, sleepFlag, reason)) != 0) {
2379 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT
2380 "Initial Alt IocFacts failed rc=%x\n",
2381 ioc->name, rc));
2382 /* Retry - alt IOC was initialized once
2383 */
2384 rc = GetIocFacts(ioc->alt_ioc, sleepFlag, reason);
2385 }
2386 if (rc) {
2387 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT
2388 "Retry Alt IocFacts failed rc=%x\n", ioc->name, rc));
2389 alt_ioc_ready = 0;
2390 reset_alt_ioc_active = 0;
2391 } else if (reason == MPT_HOSTEVENT_IOC_BRINGUP) {
2392 MptDisplayIocCapabilities(ioc->alt_ioc);
2393 }
2394 }
2395
2396 if ((ret == 0) && (reason == MPT_HOSTEVENT_IOC_BRINGUP) &&
2397 (ioc->facts.Flags & MPI_IOCFACTS_FLAGS_FW_DOWNLOAD_BOOT)) {
2398 pci_release_selected_regions(ioc->pcidev, ioc->bars);
2399 ioc->bars = pci_select_bars(ioc->pcidev, IORESOURCE_MEM |
2400 IORESOURCE_IO);
2401 if (pci_enable_device(ioc->pcidev))
2402 return -5;
2403 if (pci_request_selected_regions(ioc->pcidev, ioc->bars,
2404 "mpt"))
2405 return -5;
2406 }
2407
2408 /*
2409 * Device is reset now. It must have de-asserted the interrupt line
2410 * (if it was asserted) and it should be safe to register for the
2411 * interrupt now.
2412 */
2413 if ((ret == 0) && (reason == MPT_HOSTEVENT_IOC_BRINGUP)) {
2414 ioc->pci_irq = -1;
2415 if (ioc->pcidev->irq) {
2416 if (ioc->msi_enable && !pci_enable_msi(ioc->pcidev))
2417 printk(MYIOC_s_INFO_FMT "PCI-MSI enabled\n",
2418 ioc->name);
2419 else
2420 ioc->msi_enable = 0;
2421 rc = request_irq(ioc->pcidev->irq, mpt_interrupt,
2422 IRQF_SHARED, ioc->name, ioc);
2423 if (rc < 0) {
2424 printk(MYIOC_s_ERR_FMT "Unable to allocate "
2425 "interrupt %d!\n",
2426 ioc->name, ioc->pcidev->irq);
2427 if (ioc->msi_enable)
2428 pci_disable_msi(ioc->pcidev);
2429 ret = -EBUSY;
2430 goto out;
2431 }
2432 irq_allocated = 1;
2433 ioc->pci_irq = ioc->pcidev->irq;
2434 pci_set_master(ioc->pcidev); /* ?? */
2435 pci_set_drvdata(ioc->pcidev, ioc);
2436 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT
2437 "installed at interrupt %d\n", ioc->name,
2438 ioc->pcidev->irq));
2439 }
2440 }
2441
2442 /* Prime reply & request queues!
2443 * (mucho alloc's) Must be done prior to
2444 * init as upper addresses are needed for init.
2445 * If fails, continue with alt-ioc processing
2446 */
2447 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT "PrimeIocFifos\n",
2448 ioc->name));
2449 if ((ret == 0) && ((rc = PrimeIocFifos(ioc)) != 0))
2450 ret = -3;
2451
2452 /* May need to check/upload firmware & data here!
2453 * If fails, continue with alt-ioc processing
2454 */
2455 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT "SendIocInit\n",
2456 ioc->name));
2457 if ((ret == 0) && ((rc = SendIocInit(ioc, sleepFlag)) != 0))
2458 ret = -4;
2459// NEW!
2460 if (alt_ioc_ready && ((rc = PrimeIocFifos(ioc->alt_ioc)) != 0)) {
2461 printk(MYIOC_s_WARN_FMT
2462 ": alt-ioc (%d) FIFO mgmt alloc WARNING!\n",
2463 ioc->alt_ioc->name, rc);
2464 alt_ioc_ready = 0;
2465 reset_alt_ioc_active = 0;
2466 }
2467
2468 if (alt_ioc_ready) {
2469 if ((rc = SendIocInit(ioc->alt_ioc, sleepFlag)) != 0) {
2470 alt_ioc_ready = 0;
2471 reset_alt_ioc_active = 0;
2472 printk(MYIOC_s_WARN_FMT
2473 ": alt-ioc: (%d) init failure WARNING!\n",
2474 ioc->alt_ioc->name, rc);
2475 }
2476 }
2477
2478 if (reason == MPT_HOSTEVENT_IOC_BRINGUP){
2479 if (ioc->upload_fw) {
2480 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT
2481 "firmware upload required!\n", ioc->name));
2482
2483 /* Controller is not operational, cannot do upload
2484 */
2485 if (ret == 0) {
2486 rc = mpt_do_upload(ioc, sleepFlag);
2487 if (rc == 0) {
2488 if (ioc->alt_ioc && ioc->alt_ioc->cached_fw) {
2489 /*
2490 * Maintain only one pointer to FW memory
2491 * so there will not be two attempt to
2492 * downloadboot onboard dual function
2493 * chips (mpt_adapter_disable,
2494 * mpt_diag_reset)
2495 */
2496 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT
2497 "mpt_upload: alt_%s has cached_fw=%p \n",
2498 ioc->name, ioc->alt_ioc->name, ioc->alt_ioc->cached_fw));
2499 ioc->cached_fw = NULL;
2500 }
2501 } else {
2502 printk(MYIOC_s_WARN_FMT
2503 "firmware upload failure!\n", ioc->name);
2504 ret = -6;
2505 }
2506 }
2507 }
2508 }
2509
2510 /* Enable MPT base driver management of EventNotification
2511 * and EventAck handling.
2512 */
2513 if ((ret == 0) && (!ioc->facts.EventState)) {
2514 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT
2515 "SendEventNotification\n",
2516 ioc->name));
2517 ret = SendEventNotification(ioc, 1, sleepFlag); /* 1=Enable */
2518 }
2519
2520 if (ioc->alt_ioc && alt_ioc_ready && !ioc->alt_ioc->facts.EventState)
2521 rc = SendEventNotification(ioc->alt_ioc, 1, sleepFlag);
2522
2523 if (ret == 0) {
2524 /* Enable! (reply interrupt) */
2525 CHIPREG_WRITE32(&ioc->chip->IntMask, MPI_HIM_DIM);
2526 ioc->active = 1;
2527 }
2528 if (rc == 0) { /* alt ioc */
2529 if (reset_alt_ioc_active && ioc->alt_ioc) {
2530 /* (re)Enable alt-IOC! (reply interrupt) */
2531 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "alt-ioc"
2532 "reply irq re-enabled\n",
2533 ioc->alt_ioc->name));
2534 CHIPREG_WRITE32(&ioc->alt_ioc->chip->IntMask,
2535 MPI_HIM_DIM);
2536 ioc->alt_ioc->active = 1;
2537 }
2538 }
2539
2540
2541 /* Add additional "reason" check before call to GetLanConfigPages
2542 * (combined with GetIoUnitPage2 call). This prevents a somewhat
2543 * recursive scenario; GetLanConfigPages times out, timer expired
2544 * routine calls HardResetHandler, which calls into here again,
2545 * and we try GetLanConfigPages again...
2546 */
2547 if ((ret == 0) && (reason == MPT_HOSTEVENT_IOC_BRINGUP)) {
2548
2549 /*
2550 * Initialize link list for inactive raid volumes.
2551 */
2552 mutex_init(&ioc->raid_data.inactive_list_mutex);
2553 INIT_LIST_HEAD(&ioc->raid_data.inactive_list);
2554
2555 switch (ioc->bus_type) {
2556
2557 case SAS:
2558 /* clear persistency table */
2559 if(ioc->facts.IOCExceptions &
2560 MPI_IOCFACTS_EXCEPT_PERSISTENT_TABLE_FULL) {
2561 ret = mptbase_sas_persist_operation(ioc,
2562 MPI_SAS_OP_CLEAR_NOT_PRESENT);
2563 if(ret != 0)
2564 goto out;
2565 }
2566
2567 /* Find IM volumes
2568 */
2569 mpt_findImVolumes(ioc);
2570
2571 /* Check, and possibly reset, the coalescing value
2572 */
2573 mpt_read_ioc_pg_1(ioc);
2574
2575 break;
2576
2577 case FC:
2578 if ((ioc->pfacts[0].ProtocolFlags &
2579 MPI_PORTFACTS_PROTOCOL_LAN) &&
2580 (ioc->lan_cnfg_page0.Header.PageLength == 0)) {
2581 /*
2582 * Pre-fetch the ports LAN MAC address!
2583 * (LANPage1_t stuff)
2584 */
2585 (void) GetLanConfigPages(ioc);
2586 a = (u8*)&ioc->lan_cnfg_page1.HardwareAddressLow;
2587 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT
2588 "LanAddr = %pMR\n", ioc->name, a));
2589 }
2590 break;
2591
2592 case SPI:
2593 /* Get NVRAM and adapter maximums from SPP 0 and 2
2594 */
2595 mpt_GetScsiPortSettings(ioc, 0);
2596
2597 /* Get version and length of SDP 1
2598 */
2599 mpt_readScsiDevicePageHeaders(ioc, 0);
2600
2601 /* Find IM volumes
2602 */
2603 if (ioc->facts.MsgVersion >= MPI_VERSION_01_02)
2604 mpt_findImVolumes(ioc);
2605
2606 /* Check, and possibly reset, the coalescing value
2607 */
2608 mpt_read_ioc_pg_1(ioc);
2609
2610 mpt_read_ioc_pg_4(ioc);
2611
2612 break;
2613 }
2614
2615 GetIoUnitPage2(ioc);
2616 mpt_get_manufacturing_pg_0(ioc);
2617 }
2618
2619 out:
2620 if ((ret != 0) && irq_allocated) {
2621 free_irq(ioc->pci_irq, ioc);
2622 if (ioc->msi_enable)
2623 pci_disable_msi(ioc->pcidev);
2624 }
2625 return ret;
2626}
2627
2628/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
2629/**
2630 * mpt_detect_bound_ports - Search for matching PCI bus/dev_function
2631 * @ioc: Pointer to MPT adapter structure
2632 * @pdev: Pointer to (struct pci_dev) structure
2633 *
2634 * Search for PCI bus/dev_function which matches
2635 * PCI bus/dev_function (+/-1) for newly discovered 929,
2636 * 929X, 1030 or 1035.
2637 *
2638 * If match on PCI dev_function +/-1 is found, bind the two MPT adapters
2639 * using alt_ioc pointer fields in their %MPT_ADAPTER structures.
2640 */
2641static void
2642mpt_detect_bound_ports(MPT_ADAPTER *ioc, struct pci_dev *pdev)
2643{
2644 struct pci_dev *peer=NULL;
2645 unsigned int slot = PCI_SLOT(pdev->devfn);
2646 unsigned int func = PCI_FUNC(pdev->devfn);
2647 MPT_ADAPTER *ioc_srch;
2648
2649 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "PCI device %s devfn=%x/%x,"
2650 " searching for devfn match on %x or %x\n",
2651 ioc->name, pci_name(pdev), pdev->bus->number,
2652 pdev->devfn, func-1, func+1));
2653
2654 peer = pci_get_slot(pdev->bus, PCI_DEVFN(slot,func-1));
2655 if (!peer) {
2656 peer = pci_get_slot(pdev->bus, PCI_DEVFN(slot,func+1));
2657 if (!peer)
2658 return;
2659 }
2660
2661 list_for_each_entry(ioc_srch, &ioc_list, list) {
2662 struct pci_dev *_pcidev = ioc_srch->pcidev;
2663 if (_pcidev == peer) {
2664 /* Paranoia checks */
2665 if (ioc->alt_ioc != NULL) {
2666 printk(MYIOC_s_WARN_FMT
2667 "Oops, already bound (%s <==> %s)!\n",
2668 ioc->name, ioc->name, ioc->alt_ioc->name);
2669 break;
2670 } else if (ioc_srch->alt_ioc != NULL) {
2671 printk(MYIOC_s_WARN_FMT
2672 "Oops, already bound (%s <==> %s)!\n",
2673 ioc_srch->name, ioc_srch->name,
2674 ioc_srch->alt_ioc->name);
2675 break;
2676 }
2677 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT
2678 "FOUND! binding %s <==> %s\n",
2679 ioc->name, ioc->name, ioc_srch->name));
2680 ioc_srch->alt_ioc = ioc;
2681 ioc->alt_ioc = ioc_srch;
2682 }
2683 }
2684 pci_dev_put(peer);
2685}
2686
2687/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
2688/**
2689 * mpt_adapter_disable - Disable misbehaving MPT adapter.
2690 * @ioc: Pointer to MPT adapter structure
2691 */
2692static void
2693mpt_adapter_disable(MPT_ADAPTER *ioc)
2694{
2695 int sz;
2696 int ret;
2697
2698 if (ioc->cached_fw != NULL) {
2699 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT
2700 "%s: Pushing FW onto adapter\n", __func__, ioc->name));
2701 if ((ret = mpt_downloadboot(ioc, (MpiFwHeader_t *)
2702 ioc->cached_fw, CAN_SLEEP)) < 0) {
2703 printk(MYIOC_s_WARN_FMT
2704 ": firmware downloadboot failure (%d)!\n",
2705 ioc->name, ret);
2706 }
2707 }
2708
2709 /*
2710 * Put the controller into ready state (if its not already)
2711 */
2712 if (mpt_GetIocState(ioc, 1) != MPI_IOC_STATE_READY) {
2713 if (!SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET,
2714 CAN_SLEEP)) {
2715 if (mpt_GetIocState(ioc, 1) != MPI_IOC_STATE_READY)
2716 printk(MYIOC_s_ERR_FMT "%s: IOC msg unit "
2717 "reset failed to put ioc in ready state!\n",
2718 ioc->name, __func__);
2719 } else
2720 printk(MYIOC_s_ERR_FMT "%s: IOC msg unit reset "
2721 "failed!\n", ioc->name, __func__);
2722 }
2723
2724
2725 /* Disable adapter interrupts! */
2726 synchronize_irq(ioc->pcidev->irq);
2727 CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF);
2728 ioc->active = 0;
2729
2730 /* Clear any lingering interrupt */
2731 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
2732 CHIPREG_READ32(&ioc->chip->IntStatus);
2733
2734 if (ioc->alloc != NULL) {
2735 sz = ioc->alloc_sz;
2736 dexitprintk(ioc, printk(MYIOC_s_INFO_FMT "free @ %p, sz=%d bytes\n",
2737 ioc->name, ioc->alloc, ioc->alloc_sz));
2738 pci_free_consistent(ioc->pcidev, sz,
2739 ioc->alloc, ioc->alloc_dma);
2740 ioc->reply_frames = NULL;
2741 ioc->req_frames = NULL;
2742 ioc->alloc = NULL;
2743 ioc->alloc_total -= sz;
2744 }
2745
2746 if (ioc->sense_buf_pool != NULL) {
2747 sz = (ioc->req_depth * MPT_SENSE_BUFFER_ALLOC);
2748 pci_free_consistent(ioc->pcidev, sz,
2749 ioc->sense_buf_pool, ioc->sense_buf_pool_dma);
2750 ioc->sense_buf_pool = NULL;
2751 ioc->alloc_total -= sz;
2752 }
2753
2754 if (ioc->events != NULL){
2755 sz = MPTCTL_EVENT_LOG_SIZE * sizeof(MPT_IOCTL_EVENTS);
2756 kfree(ioc->events);
2757 ioc->events = NULL;
2758 ioc->alloc_total -= sz;
2759 }
2760
2761 mpt_free_fw_memory(ioc);
2762
2763 kfree(ioc->spi_data.nvram);
2764 mpt_inactive_raid_list_free(ioc);
2765 kfree(ioc->raid_data.pIocPg2);
2766 kfree(ioc->raid_data.pIocPg3);
2767 ioc->spi_data.nvram = NULL;
2768 ioc->raid_data.pIocPg3 = NULL;
2769
2770 if (ioc->spi_data.pIocPg4 != NULL) {
2771 sz = ioc->spi_data.IocPg4Sz;
2772 pci_free_consistent(ioc->pcidev, sz,
2773 ioc->spi_data.pIocPg4,
2774 ioc->spi_data.IocPg4_dma);
2775 ioc->spi_data.pIocPg4 = NULL;
2776 ioc->alloc_total -= sz;
2777 }
2778
2779 if (ioc->ReqToChain != NULL) {
2780 kfree(ioc->ReqToChain);
2781 kfree(ioc->RequestNB);
2782 ioc->ReqToChain = NULL;
2783 }
2784
2785 kfree(ioc->ChainToChain);
2786 ioc->ChainToChain = NULL;
2787
2788 if (ioc->HostPageBuffer != NULL) {
2789 if((ret = mpt_host_page_access_control(ioc,
2790 MPI_DB_HPBAC_FREE_BUFFER, NO_SLEEP)) != 0) {
2791 printk(MYIOC_s_ERR_FMT
2792 ": %s: host page buffers free failed (%d)!\n",
2793 ioc->name, __func__, ret);
2794 }
2795 dexitprintk(ioc, printk(MYIOC_s_DEBUG_FMT
2796 "HostPageBuffer free @ %p, sz=%d bytes\n",
2797 ioc->name, ioc->HostPageBuffer,
2798 ioc->HostPageBuffer_sz));
2799 pci_free_consistent(ioc->pcidev, ioc->HostPageBuffer_sz,
2800 ioc->HostPageBuffer, ioc->HostPageBuffer_dma);
2801 ioc->HostPageBuffer = NULL;
2802 ioc->HostPageBuffer_sz = 0;
2803 ioc->alloc_total -= ioc->HostPageBuffer_sz;
2804 }
2805
2806 pci_set_drvdata(ioc->pcidev, NULL);
2807}
2808/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
2809/**
2810 * mpt_adapter_dispose - Free all resources associated with an MPT adapter
2811 * @ioc: Pointer to MPT adapter structure
2812 *
2813 * This routine unregisters h/w resources and frees all alloc'd memory
2814 * associated with a MPT adapter structure.
2815 */
2816static void
2817mpt_adapter_dispose(MPT_ADAPTER *ioc)
2818{
2819 int sz_first, sz_last;
2820
2821 if (ioc == NULL)
2822 return;
2823
2824 sz_first = ioc->alloc_total;
2825
2826 mpt_adapter_disable(ioc);
2827
2828 if (ioc->pci_irq != -1) {
2829 free_irq(ioc->pci_irq, ioc);
2830 if (ioc->msi_enable)
2831 pci_disable_msi(ioc->pcidev);
2832 ioc->pci_irq = -1;
2833 }
2834
2835 if (ioc->memmap != NULL) {
2836 iounmap(ioc->memmap);
2837 ioc->memmap = NULL;
2838 }
2839
2840 pci_disable_device(ioc->pcidev);
2841 pci_release_selected_regions(ioc->pcidev, ioc->bars);
2842
2843 /* Zap the adapter lookup ptr! */
2844 list_del(&ioc->list);
2845
2846 sz_last = ioc->alloc_total;
2847 dprintk(ioc, printk(MYIOC_s_INFO_FMT "free'd %d of %d bytes\n",
2848 ioc->name, sz_first-sz_last+(int)sizeof(*ioc), sz_first));
2849
2850 if (ioc->alt_ioc)
2851 ioc->alt_ioc->alt_ioc = NULL;
2852
2853 kfree(ioc);
2854}
2855
2856/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
2857/**
2858 * MptDisplayIocCapabilities - Disply IOC's capabilities.
2859 * @ioc: Pointer to MPT adapter structure
2860 */
2861static void
2862MptDisplayIocCapabilities(MPT_ADAPTER *ioc)
2863{
2864 int i = 0;
2865
2866 printk(KERN_INFO "%s: ", ioc->name);
2867 if (ioc->prod_name)
2868 pr_cont("%s: ", ioc->prod_name);
2869 pr_cont("Capabilities={");
2870
2871 if (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_INITIATOR) {
2872 pr_cont("Initiator");
2873 i++;
2874 }
2875
2876 if (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_TARGET) {
2877 pr_cont("%sTarget", i ? "," : "");
2878 i++;
2879 }
2880
2881 if (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_LAN) {
2882 pr_cont("%sLAN", i ? "," : "");
2883 i++;
2884 }
2885
2886#if 0
2887 /*
2888 * This would probably evoke more questions than it's worth
2889 */
2890 if (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_TARGET) {
2891 pr_cont("%sLogBusAddr", i ? "," : "");
2892 i++;
2893 }
2894#endif
2895
2896 pr_cont("}\n");
2897}
2898
2899/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
2900/**
2901 * MakeIocReady - Get IOC to a READY state, using KickStart if needed.
2902 * @ioc: Pointer to MPT_ADAPTER structure
2903 * @force: Force hard KickStart of IOC
2904 * @sleepFlag: Specifies whether the process can sleep
2905 *
2906 * Returns:
2907 * 1 - DIAG reset and READY
2908 * 0 - READY initially OR soft reset and READY
2909 * -1 - Any failure on KickStart
2910 * -2 - Msg Unit Reset Failed
2911 * -3 - IO Unit Reset Failed
2912 * -4 - IOC owned by a PEER
2913 */
2914static int
2915MakeIocReady(MPT_ADAPTER *ioc, int force, int sleepFlag)
2916{
2917 u32 ioc_state;
2918 int statefault = 0;
2919 int cntdn;
2920 int hard_reset_done = 0;
2921 int r;
2922 int ii;
2923 int whoinit;
2924
2925 /* Get current [raw] IOC state */
2926 ioc_state = mpt_GetIocState(ioc, 0);
2927 dhsprintk(ioc, printk(MYIOC_s_INFO_FMT "MakeIocReady [raw] state=%08x\n", ioc->name, ioc_state));
2928
2929 /*
2930 * Check to see if IOC got left/stuck in doorbell handshake
2931 * grip of death. If so, hard reset the IOC.
2932 */
2933 if (ioc_state & MPI_DOORBELL_ACTIVE) {
2934 statefault = 1;
2935 printk(MYIOC_s_WARN_FMT "Unexpected doorbell active!\n",
2936 ioc->name);
2937 }
2938
2939 /* Is it already READY? */
2940 if (!statefault &&
2941 ((ioc_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_READY)) {
2942 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT
2943 "IOC is in READY state\n", ioc->name));
2944 return 0;
2945 }
2946
2947 /*
2948 * Check to see if IOC is in FAULT state.
2949 */
2950 if ((ioc_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_FAULT) {
2951 statefault = 2;
2952 printk(MYIOC_s_WARN_FMT "IOC is in FAULT state!!!\n",
2953 ioc->name);
2954 printk(MYIOC_s_WARN_FMT " FAULT code = %04xh\n",
2955 ioc->name, ioc_state & MPI_DOORBELL_DATA_MASK);
2956 }
2957
2958 /*
2959 * Hmmm... Did it get left operational?
2960 */
2961 if ((ioc_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_OPERATIONAL) {
2962 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "IOC operational unexpected\n",
2963 ioc->name));
2964
2965 /* Check WhoInit.
2966 * If PCI Peer, exit.
2967 * Else, if no fault conditions are present, issue a MessageUnitReset
2968 * Else, fall through to KickStart case
2969 */
2970 whoinit = (ioc_state & MPI_DOORBELL_WHO_INIT_MASK) >> MPI_DOORBELL_WHO_INIT_SHIFT;
2971 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT
2972 "whoinit 0x%x statefault %d force %d\n",
2973 ioc->name, whoinit, statefault, force));
2974 if (whoinit == MPI_WHOINIT_PCI_PEER)
2975 return -4;
2976 else {
2977 if ((statefault == 0 ) && (force == 0)) {
2978 if ((r = SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, sleepFlag)) == 0)
2979 return 0;
2980 }
2981 statefault = 3;
2982 }
2983 }
2984
2985 hard_reset_done = KickStart(ioc, statefault||force, sleepFlag);
2986 if (hard_reset_done < 0)
2987 return -1;
2988
2989 /*
2990 * Loop here waiting for IOC to come READY.
2991 */
2992 ii = 0;
2993 cntdn = ((sleepFlag == CAN_SLEEP) ? HZ : 1000) * 5; /* 5 seconds */
2994
2995 while ((ioc_state = mpt_GetIocState(ioc, 1)) != MPI_IOC_STATE_READY) {
2996 if (ioc_state == MPI_IOC_STATE_OPERATIONAL) {
2997 /*
2998 * BIOS or previous driver load left IOC in OP state.
2999 * Reset messaging FIFOs.
3000 */
3001 if ((r = SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, sleepFlag)) != 0) {
3002 printk(MYIOC_s_ERR_FMT "IOC msg unit reset failed!\n", ioc->name);
3003 return -2;
3004 }
3005 } else if (ioc_state == MPI_IOC_STATE_RESET) {
3006 /*
3007 * Something is wrong. Try to get IOC back
3008 * to a known state.
3009 */
3010 if ((r = SendIocReset(ioc, MPI_FUNCTION_IO_UNIT_RESET, sleepFlag)) != 0) {
3011 printk(MYIOC_s_ERR_FMT "IO unit reset failed!\n", ioc->name);
3012 return -3;
3013 }
3014 }
3015
3016 ii++; cntdn--;
3017 if (!cntdn) {
3018 printk(MYIOC_s_ERR_FMT
3019 "Wait IOC_READY state (0x%x) timeout(%d)!\n",
3020 ioc->name, ioc_state, (int)((ii+5)/HZ));
3021 return -ETIME;
3022 }
3023
3024 if (sleepFlag == CAN_SLEEP) {
3025 msleep(1);
3026 } else {
3027 mdelay (1); /* 1 msec delay */
3028 }
3029
3030 }
3031
3032 if (statefault < 3) {
3033 printk(MYIOC_s_INFO_FMT "Recovered from %s\n", ioc->name,
3034 statefault == 1 ? "stuck handshake" : "IOC FAULT");
3035 }
3036
3037 return hard_reset_done;
3038}
3039
3040/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
3041/**
3042 * mpt_GetIocState - Get the current state of a MPT adapter.
3043 * @ioc: Pointer to MPT_ADAPTER structure
3044 * @cooked: Request raw or cooked IOC state
3045 *
3046 * Returns all IOC Doorbell register bits if cooked==0, else just the
3047 * Doorbell bits in MPI_IOC_STATE_MASK.
3048 */
3049u32
3050mpt_GetIocState(MPT_ADAPTER *ioc, int cooked)
3051{
3052 u32 s, sc;
3053
3054 /* Get! */
3055 s = CHIPREG_READ32(&ioc->chip->Doorbell);
3056 sc = s & MPI_IOC_STATE_MASK;
3057
3058 /* Save! */
3059 ioc->last_state = sc;
3060
3061 return cooked ? sc : s;
3062}
3063
3064/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
3065/**
3066 * GetIocFacts - Send IOCFacts request to MPT adapter.
3067 * @ioc: Pointer to MPT_ADAPTER structure
3068 * @sleepFlag: Specifies whether the process can sleep
3069 * @reason: If recovery, only update facts.
3070 *
3071 * Returns 0 for success, non-zero for failure.
3072 */
3073static int
3074GetIocFacts(MPT_ADAPTER *ioc, int sleepFlag, int reason)
3075{
3076 IOCFacts_t get_facts;
3077 IOCFactsReply_t *facts;
3078 int r;
3079 int req_sz;
3080 int reply_sz;
3081 int sz;
3082 u32 status, vv;
3083 u8 shiftFactor=1;
3084
3085 /* IOC *must* NOT be in RESET state! */
3086 if (ioc->last_state == MPI_IOC_STATE_RESET) {
3087 printk(KERN_ERR MYNAM
3088 ": ERROR - Can't get IOCFacts, %s NOT READY! (%08x)\n",
3089 ioc->name, ioc->last_state);
3090 return -44;
3091 }
3092
3093 facts = &ioc->facts;
3094
3095 /* Destination (reply area)... */
3096 reply_sz = sizeof(*facts);
3097 memset(facts, 0, reply_sz);
3098
3099 /* Request area (get_facts on the stack right now!) */
3100 req_sz = sizeof(get_facts);
3101 memset(&get_facts, 0, req_sz);
3102
3103 get_facts.Function = MPI_FUNCTION_IOC_FACTS;
3104 /* Assert: All other get_facts fields are zero! */
3105
3106 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT
3107 "Sending get IocFacts request req_sz=%d reply_sz=%d\n",
3108 ioc->name, req_sz, reply_sz));
3109
3110 /* No non-zero fields in the get_facts request are greater than
3111 * 1 byte in size, so we can just fire it off as is.
3112 */
3113 r = mpt_handshake_req_reply_wait(ioc, req_sz, (u32*)&get_facts,
3114 reply_sz, (u16*)facts, 5 /*seconds*/, sleepFlag);
3115 if (r != 0)
3116 return r;
3117
3118 /*
3119 * Now byte swap (GRRR) the necessary fields before any further
3120 * inspection of reply contents.
3121 *
3122 * But need to do some sanity checks on MsgLength (byte) field
3123 * to make sure we don't zero IOC's req_sz!
3124 */
3125 /* Did we get a valid reply? */
3126 if (facts->MsgLength > offsetof(IOCFactsReply_t, RequestFrameSize)/sizeof(u32)) {
3127 if (reason == MPT_HOSTEVENT_IOC_BRINGUP) {
3128 /*
3129 * If not been here, done that, save off first WhoInit value
3130 */
3131 if (ioc->FirstWhoInit == WHOINIT_UNKNOWN)
3132 ioc->FirstWhoInit = facts->WhoInit;
3133 }
3134
3135 facts->MsgVersion = le16_to_cpu(facts->MsgVersion);
3136 facts->MsgContext = le32_to_cpu(facts->MsgContext);
3137 facts->IOCExceptions = le16_to_cpu(facts->IOCExceptions);
3138 facts->IOCStatus = le16_to_cpu(facts->IOCStatus);
3139 facts->IOCLogInfo = le32_to_cpu(facts->IOCLogInfo);
3140 status = le16_to_cpu(facts->IOCStatus) & MPI_IOCSTATUS_MASK;
3141 /* CHECKME! IOCStatus, IOCLogInfo */
3142
3143 facts->ReplyQueueDepth = le16_to_cpu(facts->ReplyQueueDepth);
3144 facts->RequestFrameSize = le16_to_cpu(facts->RequestFrameSize);
3145
3146 /*
3147 * FC f/w version changed between 1.1 and 1.2
3148 * Old: u16{Major(4),Minor(4),SubMinor(8)}
3149 * New: u32{Major(8),Minor(8),Unit(8),Dev(8)}
3150 */
3151 if (facts->MsgVersion < MPI_VERSION_01_02) {
3152 /*
3153 * Handle old FC f/w style, convert to new...
3154 */
3155 u16 oldv = le16_to_cpu(facts->Reserved_0101_FWVersion);
3156 facts->FWVersion.Word =
3157 ((oldv<<12) & 0xFF000000) |
3158 ((oldv<<8) & 0x000FFF00);
3159 } else
3160 facts->FWVersion.Word = le32_to_cpu(facts->FWVersion.Word);
3161
3162 facts->ProductID = le16_to_cpu(facts->ProductID);
3163
3164 if ((ioc->facts.ProductID & MPI_FW_HEADER_PID_PROD_MASK)
3165 > MPI_FW_HEADER_PID_PROD_TARGET_SCSI)
3166 ioc->ir_firmware = 1;
3167
3168 facts->CurrentHostMfaHighAddr =
3169 le32_to_cpu(facts->CurrentHostMfaHighAddr);
3170 facts->GlobalCredits = le16_to_cpu(facts->GlobalCredits);
3171 facts->CurrentSenseBufferHighAddr =
3172 le32_to_cpu(facts->CurrentSenseBufferHighAddr);
3173 facts->CurReplyFrameSize =
3174 le16_to_cpu(facts->CurReplyFrameSize);
3175 facts->IOCCapabilities = le32_to_cpu(facts->IOCCapabilities);
3176
3177 /*
3178 * Handle NEW (!) IOCFactsReply fields in MPI-1.01.xx
3179 * Older MPI-1.00.xx struct had 13 dwords, and enlarged
3180 * to 14 in MPI-1.01.0x.
3181 */
3182 if (facts->MsgLength >= (offsetof(IOCFactsReply_t,FWImageSize) + 7)/4 &&
3183 facts->MsgVersion > MPI_VERSION_01_00) {
3184 facts->FWImageSize = le32_to_cpu(facts->FWImageSize);
3185 }
3186
3187 facts->FWImageSize = ALIGN(facts->FWImageSize, 4);
3188
3189 if (!facts->RequestFrameSize) {
3190 /* Something is wrong! */
3191 printk(MYIOC_s_ERR_FMT "IOC reported invalid 0 request size!\n",
3192 ioc->name);
3193 return -55;
3194 }
3195
3196 r = sz = facts->BlockSize;
3197 vv = ((63 / (sz * 4)) + 1) & 0x03;
3198 ioc->NB_for_64_byte_frame = vv;
3199 while ( sz )
3200 {
3201 shiftFactor++;
3202 sz = sz >> 1;
3203 }
3204 ioc->NBShiftFactor = shiftFactor;
3205 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT
3206 "NB_for_64_byte_frame=%x NBShiftFactor=%x BlockSize=%x\n",
3207 ioc->name, vv, shiftFactor, r));
3208
3209 if (reason == MPT_HOSTEVENT_IOC_BRINGUP) {
3210 /*
3211 * Set values for this IOC's request & reply frame sizes,
3212 * and request & reply queue depths...
3213 */
3214 ioc->req_sz = min(MPT_DEFAULT_FRAME_SIZE, facts->RequestFrameSize * 4);
3215 ioc->req_depth = min_t(int, MPT_MAX_REQ_DEPTH, facts->GlobalCredits);
3216 ioc->reply_sz = MPT_REPLY_FRAME_SIZE;
3217 ioc->reply_depth = min_t(int, MPT_DEFAULT_REPLY_DEPTH, facts->ReplyQueueDepth);
3218
3219 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "reply_sz=%3d, reply_depth=%4d\n",
3220 ioc->name, ioc->reply_sz, ioc->reply_depth));
3221 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "req_sz =%3d, req_depth =%4d\n",
3222 ioc->name, ioc->req_sz, ioc->req_depth));
3223
3224 /* Get port facts! */
3225 if ( (r = GetPortFacts(ioc, 0, sleepFlag)) != 0 )
3226 return r;
3227 }
3228 } else {
3229 printk(MYIOC_s_ERR_FMT
3230 "Invalid IOC facts reply, msgLength=%d offsetof=%zd!\n",
3231 ioc->name, facts->MsgLength, (offsetof(IOCFactsReply_t,
3232 RequestFrameSize)/sizeof(u32)));
3233 return -66;
3234 }
3235
3236 return 0;
3237}
3238
3239/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
3240/**
3241 * GetPortFacts - Send PortFacts request to MPT adapter.
3242 * @ioc: Pointer to MPT_ADAPTER structure
3243 * @portnum: Port number
3244 * @sleepFlag: Specifies whether the process can sleep
3245 *
3246 * Returns 0 for success, non-zero for failure.
3247 */
3248static int
3249GetPortFacts(MPT_ADAPTER *ioc, int portnum, int sleepFlag)
3250{
3251 PortFacts_t get_pfacts;
3252 PortFactsReply_t *pfacts;
3253 int ii;
3254 int req_sz;
3255 int reply_sz;
3256 int max_id;
3257
3258 /* IOC *must* NOT be in RESET state! */
3259 if (ioc->last_state == MPI_IOC_STATE_RESET) {
3260 printk(MYIOC_s_ERR_FMT "Can't get PortFacts NOT READY! (%08x)\n",
3261 ioc->name, ioc->last_state );
3262 return -4;
3263 }
3264
3265 pfacts = &ioc->pfacts[portnum];
3266
3267 /* Destination (reply area)... */
3268 reply_sz = sizeof(*pfacts);
3269 memset(pfacts, 0, reply_sz);
3270
3271 /* Request area (get_pfacts on the stack right now!) */
3272 req_sz = sizeof(get_pfacts);
3273 memset(&get_pfacts, 0, req_sz);
3274
3275 get_pfacts.Function = MPI_FUNCTION_PORT_FACTS;
3276 get_pfacts.PortNumber = portnum;
3277 /* Assert: All other get_pfacts fields are zero! */
3278
3279 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending get PortFacts(%d) request\n",
3280 ioc->name, portnum));
3281
3282 /* No non-zero fields in the get_pfacts request are greater than
3283 * 1 byte in size, so we can just fire it off as is.
3284 */
3285 ii = mpt_handshake_req_reply_wait(ioc, req_sz, (u32*)&get_pfacts,
3286 reply_sz, (u16*)pfacts, 5 /*seconds*/, sleepFlag);
3287 if (ii != 0)
3288 return ii;
3289
3290 /* Did we get a valid reply? */
3291
3292 /* Now byte swap the necessary fields in the response. */
3293 pfacts->MsgContext = le32_to_cpu(pfacts->MsgContext);
3294 pfacts->IOCStatus = le16_to_cpu(pfacts->IOCStatus);
3295 pfacts->IOCLogInfo = le32_to_cpu(pfacts->IOCLogInfo);
3296 pfacts->MaxDevices = le16_to_cpu(pfacts->MaxDevices);
3297 pfacts->PortSCSIID = le16_to_cpu(pfacts->PortSCSIID);
3298 pfacts->ProtocolFlags = le16_to_cpu(pfacts->ProtocolFlags);
3299 pfacts->MaxPostedCmdBuffers = le16_to_cpu(pfacts->MaxPostedCmdBuffers);
3300 pfacts->MaxPersistentIDs = le16_to_cpu(pfacts->MaxPersistentIDs);
3301 pfacts->MaxLanBuckets = le16_to_cpu(pfacts->MaxLanBuckets);
3302
3303 max_id = (ioc->bus_type == SAS) ? pfacts->PortSCSIID :
3304 pfacts->MaxDevices;
3305 ioc->devices_per_bus = (max_id > 255) ? 256 : max_id;
3306 ioc->number_of_buses = (ioc->devices_per_bus < 256) ? 1 : max_id/256;
3307
3308 /*
3309 * Place all the devices on channels
3310 *
3311 * (for debuging)
3312 */
3313 if (mpt_channel_mapping) {
3314 ioc->devices_per_bus = 1;
3315 ioc->number_of_buses = (max_id > 255) ? 255 : max_id;
3316 }
3317
3318 return 0;
3319}
3320
3321/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
3322/**
3323 * SendIocInit - Send IOCInit request to MPT adapter.
3324 * @ioc: Pointer to MPT_ADAPTER structure
3325 * @sleepFlag: Specifies whether the process can sleep
3326 *
3327 * Send IOCInit followed by PortEnable to bring IOC to OPERATIONAL state.
3328 *
3329 * Returns 0 for success, non-zero for failure.
3330 */
3331static int
3332SendIocInit(MPT_ADAPTER *ioc, int sleepFlag)
3333{
3334 IOCInit_t ioc_init;
3335 MPIDefaultReply_t init_reply;
3336 u32 state;
3337 int r;
3338 int count;
3339 int cntdn;
3340
3341 memset(&ioc_init, 0, sizeof(ioc_init));
3342 memset(&init_reply, 0, sizeof(init_reply));
3343
3344 ioc_init.WhoInit = MPI_WHOINIT_HOST_DRIVER;
3345 ioc_init.Function = MPI_FUNCTION_IOC_INIT;
3346
3347 /* If we are in a recovery mode and we uploaded the FW image,
3348 * then this pointer is not NULL. Skip the upload a second time.
3349 * Set this flag if cached_fw set for either IOC.
3350 */
3351 if (ioc->facts.Flags & MPI_IOCFACTS_FLAGS_FW_DOWNLOAD_BOOT)
3352 ioc->upload_fw = 1;
3353 else
3354 ioc->upload_fw = 0;
3355 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "upload_fw %d facts.Flags=%x\n",
3356 ioc->name, ioc->upload_fw, ioc->facts.Flags));
3357
3358 ioc_init.MaxDevices = (U8)ioc->devices_per_bus;
3359 ioc_init.MaxBuses = (U8)ioc->number_of_buses;
3360
3361 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "facts.MsgVersion=%x\n",
3362 ioc->name, ioc->facts.MsgVersion));
3363 if (ioc->facts.MsgVersion >= MPI_VERSION_01_05) {
3364 // set MsgVersion and HeaderVersion host driver was built with
3365 ioc_init.MsgVersion = cpu_to_le16(MPI_VERSION);
3366 ioc_init.HeaderVersion = cpu_to_le16(MPI_HEADER_VERSION);
3367
3368 if (ioc->facts.Flags & MPI_IOCFACTS_FLAGS_HOST_PAGE_BUFFER_PERSISTENT) {
3369 ioc_init.HostPageBufferSGE = ioc->facts.HostPageBufferSGE;
3370 } else if(mpt_host_page_alloc(ioc, &ioc_init))
3371 return -99;
3372 }
3373 ioc_init.ReplyFrameSize = cpu_to_le16(ioc->reply_sz); /* in BYTES */
3374
3375 if (ioc->sg_addr_size == sizeof(u64)) {
3376 /* Save the upper 32-bits of the request
3377 * (reply) and sense buffers.
3378 */
3379 ioc_init.HostMfaHighAddr = cpu_to_le32((u32)((u64)ioc->alloc_dma >> 32));
3380 ioc_init.SenseBufferHighAddr = cpu_to_le32((u32)((u64)ioc->sense_buf_pool_dma >> 32));
3381 } else {
3382 /* Force 32-bit addressing */
3383 ioc_init.HostMfaHighAddr = cpu_to_le32(0);
3384 ioc_init.SenseBufferHighAddr = cpu_to_le32(0);
3385 }
3386
3387 ioc->facts.CurrentHostMfaHighAddr = ioc_init.HostMfaHighAddr;
3388 ioc->facts.CurrentSenseBufferHighAddr = ioc_init.SenseBufferHighAddr;
3389 ioc->facts.MaxDevices = ioc_init.MaxDevices;
3390 ioc->facts.MaxBuses = ioc_init.MaxBuses;
3391
3392 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending IOCInit (req @ %p)\n",
3393 ioc->name, &ioc_init));
3394
3395 r = mpt_handshake_req_reply_wait(ioc, sizeof(IOCInit_t), (u32*)&ioc_init,
3396 sizeof(MPIDefaultReply_t), (u16*)&init_reply, 10 /*seconds*/, sleepFlag);
3397 if (r != 0) {
3398 printk(MYIOC_s_ERR_FMT "Sending IOCInit failed(%d)!\n",ioc->name, r);
3399 return r;
3400 }
3401
3402 /* No need to byte swap the multibyte fields in the reply
3403 * since we don't even look at its contents.
3404 */
3405
3406 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending PortEnable (req @ %p)\n",
3407 ioc->name, &ioc_init));
3408
3409 if ((r = SendPortEnable(ioc, 0, sleepFlag)) != 0) {
3410 printk(MYIOC_s_ERR_FMT "Sending PortEnable failed(%d)!\n",ioc->name, r);
3411 return r;
3412 }
3413
3414 /* YIKES! SUPER IMPORTANT!!!
3415 * Poll IocState until _OPERATIONAL while IOC is doing
3416 * LoopInit and TargetDiscovery!
3417 */
3418 count = 0;
3419 cntdn = ((sleepFlag == CAN_SLEEP) ? HZ : 1000) * 60; /* 60 seconds */
3420 state = mpt_GetIocState(ioc, 1);
3421 while (state != MPI_IOC_STATE_OPERATIONAL && --cntdn) {
3422 if (sleepFlag == CAN_SLEEP) {
3423 msleep(1);
3424 } else {
3425 mdelay(1);
3426 }
3427
3428 if (!cntdn) {
3429 printk(MYIOC_s_ERR_FMT "Wait IOC_OP state timeout(%d)!\n",
3430 ioc->name, (int)((count+5)/HZ));
3431 return -9;
3432 }
3433
3434 state = mpt_GetIocState(ioc, 1);
3435 count++;
3436 }
3437 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Wait IOC_OPERATIONAL state (cnt=%d)\n",
3438 ioc->name, count));
3439
3440 ioc->aen_event_read_flag=0;
3441 return r;
3442}
3443
3444/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
3445/**
3446 * SendPortEnable - Send PortEnable request to MPT adapter port.
3447 * @ioc: Pointer to MPT_ADAPTER structure
3448 * @portnum: Port number to enable
3449 * @sleepFlag: Specifies whether the process can sleep
3450 *
3451 * Send PortEnable to bring IOC to OPERATIONAL state.
3452 *
3453 * Returns 0 for success, non-zero for failure.
3454 */
3455static int
3456SendPortEnable(MPT_ADAPTER *ioc, int portnum, int sleepFlag)
3457{
3458 PortEnable_t port_enable;
3459 MPIDefaultReply_t reply_buf;
3460 int rc;
3461 int req_sz;
3462 int reply_sz;
3463
3464 /* Destination... */
3465 reply_sz = sizeof(MPIDefaultReply_t);
3466 memset(&reply_buf, 0, reply_sz);
3467
3468 req_sz = sizeof(PortEnable_t);
3469 memset(&port_enable, 0, req_sz);
3470
3471 port_enable.Function = MPI_FUNCTION_PORT_ENABLE;
3472 port_enable.PortNumber = portnum;
3473/* port_enable.ChainOffset = 0; */
3474/* port_enable.MsgFlags = 0; */
3475/* port_enable.MsgContext = 0; */
3476
3477 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending Port(%d)Enable (req @ %p)\n",
3478 ioc->name, portnum, &port_enable));
3479
3480 /* RAID FW may take a long time to enable
3481 */
3482 if (ioc->ir_firmware || ioc->bus_type == SAS) {
3483 rc = mpt_handshake_req_reply_wait(ioc, req_sz,
3484 (u32*)&port_enable, reply_sz, (u16*)&reply_buf,
3485 300 /*seconds*/, sleepFlag);
3486 } else {
3487 rc = mpt_handshake_req_reply_wait(ioc, req_sz,
3488 (u32*)&port_enable, reply_sz, (u16*)&reply_buf,
3489 30 /*seconds*/, sleepFlag);
3490 }
3491 return rc;
3492}
3493
3494/**
3495 * mpt_alloc_fw_memory - allocate firmware memory
3496 * @ioc: Pointer to MPT_ADAPTER structure
3497 * @size: total FW bytes
3498 *
3499 * If memory has already been allocated, the same (cached) value
3500 * is returned.
3501 *
3502 * Return 0 if successful, or non-zero for failure
3503 **/
3504int
3505mpt_alloc_fw_memory(MPT_ADAPTER *ioc, int size)
3506{
3507 int rc;
3508
3509 if (ioc->cached_fw) {
3510 rc = 0; /* use already allocated memory */
3511 goto out;
3512 }
3513 else if (ioc->alt_ioc && ioc->alt_ioc->cached_fw) {
3514 ioc->cached_fw = ioc->alt_ioc->cached_fw; /* use alt_ioc's memory */
3515 ioc->cached_fw_dma = ioc->alt_ioc->cached_fw_dma;
3516 rc = 0;
3517 goto out;
3518 }
3519 ioc->cached_fw = pci_alloc_consistent(ioc->pcidev, size, &ioc->cached_fw_dma);
3520 if (!ioc->cached_fw) {
3521 printk(MYIOC_s_ERR_FMT "Unable to allocate memory for the cached firmware image!\n",
3522 ioc->name);
3523 rc = -1;
3524 } else {
3525 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "FW Image @ %p[%p], sz=%d[%x] bytes\n",
3526 ioc->name, ioc->cached_fw, (void *)(ulong)ioc->cached_fw_dma, size, size));
3527 ioc->alloc_total += size;
3528 rc = 0;
3529 }
3530 out:
3531 return rc;
3532}
3533
3534/**
3535 * mpt_free_fw_memory - free firmware memory
3536 * @ioc: Pointer to MPT_ADAPTER structure
3537 *
3538 * If alt_img is NULL, delete from ioc structure.
3539 * Else, delete a secondary image in same format.
3540 **/
3541void
3542mpt_free_fw_memory(MPT_ADAPTER *ioc)
3543{
3544 int sz;
3545
3546 if (!ioc->cached_fw)
3547 return;
3548
3549 sz = ioc->facts.FWImageSize;
3550 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "free_fw_memory: FW Image @ %p[%p], sz=%d[%x] bytes\n",
3551 ioc->name, ioc->cached_fw, (void *)(ulong)ioc->cached_fw_dma, sz, sz));
3552 pci_free_consistent(ioc->pcidev, sz, ioc->cached_fw, ioc->cached_fw_dma);
3553 ioc->alloc_total -= sz;
3554 ioc->cached_fw = NULL;
3555}
3556
3557/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
3558/**
3559 * mpt_do_upload - Construct and Send FWUpload request to MPT adapter port.
3560 * @ioc: Pointer to MPT_ADAPTER structure
3561 * @sleepFlag: Specifies whether the process can sleep
3562 *
3563 * Returns 0 for success, >0 for handshake failure
3564 * <0 for fw upload failure.
3565 *
3566 * Remark: If bound IOC and a successful FWUpload was performed
3567 * on the bound IOC, the second image is discarded
3568 * and memory is free'd. Both channels must upload to prevent
3569 * IOC from running in degraded mode.
3570 */
3571static int
3572mpt_do_upload(MPT_ADAPTER *ioc, int sleepFlag)
3573{
3574 u8 reply[sizeof(FWUploadReply_t)];
3575 FWUpload_t *prequest;
3576 FWUploadReply_t *preply;
3577 FWUploadTCSGE_t *ptcsge;
3578 u32 flagsLength;
3579 int ii, sz, reply_sz;
3580 int cmdStatus;
3581 int request_size;
3582 /* If the image size is 0, we are done.
3583 */
3584 if ((sz = ioc->facts.FWImageSize) == 0)
3585 return 0;
3586
3587 if (mpt_alloc_fw_memory(ioc, ioc->facts.FWImageSize) != 0)
3588 return -ENOMEM;
3589
3590 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT ": FW Image @ %p[%p], sz=%d[%x] bytes\n",
3591 ioc->name, ioc->cached_fw, (void *)(ulong)ioc->cached_fw_dma, sz, sz));
3592
3593 prequest = (sleepFlag == NO_SLEEP) ? kzalloc(ioc->req_sz, GFP_ATOMIC) :
3594 kzalloc(ioc->req_sz, GFP_KERNEL);
3595 if (!prequest) {
3596 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "fw upload failed "
3597 "while allocating memory \n", ioc->name));
3598 mpt_free_fw_memory(ioc);
3599 return -ENOMEM;
3600 }
3601
3602 preply = (FWUploadReply_t *)&reply;
3603
3604 reply_sz = sizeof(reply);
3605 memset(preply, 0, reply_sz);
3606
3607 prequest->ImageType = MPI_FW_UPLOAD_ITYPE_FW_IOC_MEM;
3608 prequest->Function = MPI_FUNCTION_FW_UPLOAD;
3609
3610 ptcsge = (FWUploadTCSGE_t *) &prequest->SGL;
3611 ptcsge->DetailsLength = 12;
3612 ptcsge->Flags = MPI_SGE_FLAGS_TRANSACTION_ELEMENT;
3613 ptcsge->ImageSize = cpu_to_le32(sz);
3614 ptcsge++;
3615
3616 flagsLength = MPT_SGE_FLAGS_SSIMPLE_READ | sz;
3617 ioc->add_sge((char *)ptcsge, flagsLength, ioc->cached_fw_dma);
3618 request_size = offsetof(FWUpload_t, SGL) + sizeof(FWUploadTCSGE_t) +
3619 ioc->SGE_size;
3620 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending FW Upload "
3621 " (req @ %p) fw_size=%d mf_request_size=%d\n", ioc->name, prequest,
3622 ioc->facts.FWImageSize, request_size));
3623 DBG_DUMP_FW_REQUEST_FRAME(ioc, (u32 *)prequest);
3624
3625 ii = mpt_handshake_req_reply_wait(ioc, request_size, (u32 *)prequest,
3626 reply_sz, (u16 *)preply, 65 /*seconds*/, sleepFlag);
3627
3628 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "FW Upload completed "
3629 "rc=%x \n", ioc->name, ii));
3630
3631 cmdStatus = -EFAULT;
3632 if (ii == 0) {
3633 /* Handshake transfer was complete and successful.
3634 * Check the Reply Frame.
3635 */
3636 int status;
3637 status = le16_to_cpu(preply->IOCStatus) &
3638 MPI_IOCSTATUS_MASK;
3639 if (status == MPI_IOCSTATUS_SUCCESS &&
3640 ioc->facts.FWImageSize ==
3641 le32_to_cpu(preply->ActualImageSize))
3642 cmdStatus = 0;
3643 }
3644 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT ": do_upload cmdStatus=%d \n",
3645 ioc->name, cmdStatus));
3646
3647
3648 if (cmdStatus) {
3649 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "fw upload failed, "
3650 "freeing image \n", ioc->name));
3651 mpt_free_fw_memory(ioc);
3652 }
3653 kfree(prequest);
3654
3655 return cmdStatus;
3656}
3657
3658/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
3659/**
3660 * mpt_downloadboot - DownloadBoot code
3661 * @ioc: Pointer to MPT_ADAPTER structure
3662 * @pFwHeader: Pointer to firmware header info
3663 * @sleepFlag: Specifies whether the process can sleep
3664 *
3665 * FwDownloadBoot requires Programmed IO access.
3666 *
3667 * Returns 0 for success
3668 * -1 FW Image size is 0
3669 * -2 No valid cached_fw Pointer
3670 * <0 for fw upload failure.
3671 */
3672static int
3673mpt_downloadboot(MPT_ADAPTER *ioc, MpiFwHeader_t *pFwHeader, int sleepFlag)
3674{
3675 MpiExtImageHeader_t *pExtImage;
3676 u32 fwSize;
3677 u32 diag0val;
3678 int count;
3679 u32 *ptrFw;
3680 u32 diagRwData;
3681 u32 nextImage;
3682 u32 load_addr;
3683 u32 ioc_state=0;
3684
3685 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "downloadboot: fw size 0x%x (%d), FW Ptr %p\n",
3686 ioc->name, pFwHeader->ImageSize, pFwHeader->ImageSize, pFwHeader));
3687
3688 CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF);
3689 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_1ST_KEY_VALUE);
3690 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_2ND_KEY_VALUE);
3691 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_3RD_KEY_VALUE);
3692 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_4TH_KEY_VALUE);
3693 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_5TH_KEY_VALUE);
3694
3695 CHIPREG_WRITE32(&ioc->chip->Diagnostic, (MPI_DIAG_PREVENT_IOC_BOOT | MPI_DIAG_DISABLE_ARM));
3696
3697 /* wait 1 msec */
3698 if (sleepFlag == CAN_SLEEP) {
3699 msleep(1);
3700 } else {
3701 mdelay (1);
3702 }
3703
3704 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
3705 CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val | MPI_DIAG_RESET_ADAPTER);
3706
3707 for (count = 0; count < 30; count ++) {
3708 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
3709 if (!(diag0val & MPI_DIAG_RESET_ADAPTER)) {
3710 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "RESET_ADAPTER cleared, count=%d\n",
3711 ioc->name, count));
3712 break;
3713 }
3714 /* wait .1 sec */
3715 if (sleepFlag == CAN_SLEEP) {
3716 msleep (100);
3717 } else {
3718 mdelay (100);
3719 }
3720 }
3721
3722 if ( count == 30 ) {
3723 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "downloadboot failed! "
3724 "Unable to get MPI_DIAG_DRWE mode, diag0val=%x\n",
3725 ioc->name, diag0val));
3726 return -3;
3727 }
3728
3729 CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF);
3730 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_1ST_KEY_VALUE);
3731 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_2ND_KEY_VALUE);
3732 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_3RD_KEY_VALUE);
3733 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_4TH_KEY_VALUE);
3734 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_5TH_KEY_VALUE);
3735
3736 /* Set the DiagRwEn and Disable ARM bits */
3737 CHIPREG_WRITE32(&ioc->chip->Diagnostic, (MPI_DIAG_RW_ENABLE | MPI_DIAG_DISABLE_ARM));
3738
3739 fwSize = (pFwHeader->ImageSize + 3)/4;
3740 ptrFw = (u32 *) pFwHeader;
3741
3742 /* Write the LoadStartAddress to the DiagRw Address Register
3743 * using Programmed IO
3744 */
3745 if (ioc->errata_flag_1064)
3746 pci_enable_io_access(ioc->pcidev);
3747
3748 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, pFwHeader->LoadStartAddress);
3749 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "LoadStart addr written 0x%x \n",
3750 ioc->name, pFwHeader->LoadStartAddress));
3751
3752 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Write FW Image: 0x%x bytes @ %p\n",
3753 ioc->name, fwSize*4, ptrFw));
3754 while (fwSize--) {
3755 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, *ptrFw++);
3756 }
3757
3758 nextImage = pFwHeader->NextImageHeaderOffset;
3759 while (nextImage) {
3760 pExtImage = (MpiExtImageHeader_t *) ((char *)pFwHeader + nextImage);
3761
3762 load_addr = pExtImage->LoadStartAddress;
3763
3764 fwSize = (pExtImage->ImageSize + 3) >> 2;
3765 ptrFw = (u32 *)pExtImage;
3766
3767 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Write Ext Image: 0x%x (%d) bytes @ %p load_addr=%x\n",
3768 ioc->name, fwSize*4, fwSize*4, ptrFw, load_addr));
3769 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, load_addr);
3770
3771 while (fwSize--) {
3772 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, *ptrFw++);
3773 }
3774 nextImage = pExtImage->NextImageHeaderOffset;
3775 }
3776
3777 /* Write the IopResetVectorRegAddr */
3778 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Write IopResetVector Addr=%x! \n", ioc->name, pFwHeader->IopResetRegAddr));
3779 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, pFwHeader->IopResetRegAddr);
3780
3781 /* Write the IopResetVectorValue */
3782 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Write IopResetVector Value=%x! \n", ioc->name, pFwHeader->IopResetVectorValue));
3783 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, pFwHeader->IopResetVectorValue);
3784
3785 /* Clear the internal flash bad bit - autoincrementing register,
3786 * so must do two writes.
3787 */
3788 if (ioc->bus_type == SPI) {
3789 /*
3790 * 1030 and 1035 H/W errata, workaround to access
3791 * the ClearFlashBadSignatureBit
3792 */
3793 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, 0x3F000000);
3794 diagRwData = CHIPREG_PIO_READ32(&ioc->pio_chip->DiagRwData);
3795 diagRwData |= 0x40000000;
3796 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, 0x3F000000);
3797 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, diagRwData);
3798
3799 } else /* if((ioc->bus_type == SAS) || (ioc->bus_type == FC)) */ {
3800 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
3801 CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val |
3802 MPI_DIAG_CLEAR_FLASH_BAD_SIG);
3803
3804 /* wait 1 msec */
3805 if (sleepFlag == CAN_SLEEP) {
3806 msleep (1);
3807 } else {
3808 mdelay (1);
3809 }
3810 }
3811
3812 if (ioc->errata_flag_1064)
3813 pci_disable_io_access(ioc->pcidev);
3814
3815 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
3816 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "downloadboot diag0val=%x, "
3817 "turning off PREVENT_IOC_BOOT, DISABLE_ARM, RW_ENABLE\n",
3818 ioc->name, diag0val));
3819 diag0val &= ~(MPI_DIAG_PREVENT_IOC_BOOT | MPI_DIAG_DISABLE_ARM | MPI_DIAG_RW_ENABLE);
3820 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "downloadboot now diag0val=%x\n",
3821 ioc->name, diag0val));
3822 CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val);
3823
3824 /* Write 0xFF to reset the sequencer */
3825 CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF);
3826
3827 if (ioc->bus_type == SAS) {
3828 ioc_state = mpt_GetIocState(ioc, 0);
3829 if ( (GetIocFacts(ioc, sleepFlag,
3830 MPT_HOSTEVENT_IOC_BRINGUP)) != 0 ) {
3831 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "GetIocFacts failed: IocState=%x\n",
3832 ioc->name, ioc_state));
3833 return -EFAULT;
3834 }
3835 }
3836
3837 for (count=0; count<HZ*20; count++) {
3838 if ((ioc_state = mpt_GetIocState(ioc, 0)) & MPI_IOC_STATE_READY) {
3839 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT
3840 "downloadboot successful! (count=%d) IocState=%x\n",
3841 ioc->name, count, ioc_state));
3842 if (ioc->bus_type == SAS) {
3843 return 0;
3844 }
3845 if ((SendIocInit(ioc, sleepFlag)) != 0) {
3846 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT
3847 "downloadboot: SendIocInit failed\n",
3848 ioc->name));
3849 return -EFAULT;
3850 }
3851 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT
3852 "downloadboot: SendIocInit successful\n",
3853 ioc->name));
3854 return 0;
3855 }
3856 if (sleepFlag == CAN_SLEEP) {
3857 msleep (10);
3858 } else {
3859 mdelay (10);
3860 }
3861 }
3862 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT
3863 "downloadboot failed! IocState=%x\n",ioc->name, ioc_state));
3864 return -EFAULT;
3865}
3866
3867/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
3868/**
3869 * KickStart - Perform hard reset of MPT adapter.
3870 * @ioc: Pointer to MPT_ADAPTER structure
3871 * @force: Force hard reset
3872 * @sleepFlag: Specifies whether the process can sleep
3873 *
3874 * This routine places MPT adapter in diagnostic mode via the
3875 * WriteSequence register, and then performs a hard reset of adapter
3876 * via the Diagnostic register.
3877 *
3878 * Inputs: sleepflag - CAN_SLEEP (non-interrupt thread)
3879 * or NO_SLEEP (interrupt thread, use mdelay)
3880 * force - 1 if doorbell active, board fault state
3881 * board operational, IOC_RECOVERY or
3882 * IOC_BRINGUP and there is an alt_ioc.
3883 * 0 else
3884 *
3885 * Returns:
3886 * 1 - hard reset, READY
3887 * 0 - no reset due to History bit, READY
3888 * -1 - no reset due to History bit but not READY
3889 * OR reset but failed to come READY
3890 * -2 - no reset, could not enter DIAG mode
3891 * -3 - reset but bad FW bit
3892 */
3893static int
3894KickStart(MPT_ADAPTER *ioc, int force, int sleepFlag)
3895{
3896 int hard_reset_done = 0;
3897 u32 ioc_state=0;
3898 int cnt,cntdn;
3899
3900 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "KickStarting!\n", ioc->name));
3901 if (ioc->bus_type == SPI) {
3902 /* Always issue a Msg Unit Reset first. This will clear some
3903 * SCSI bus hang conditions.
3904 */
3905 SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, sleepFlag);
3906
3907 if (sleepFlag == CAN_SLEEP) {
3908 msleep (1000);
3909 } else {
3910 mdelay (1000);
3911 }
3912 }
3913
3914 hard_reset_done = mpt_diag_reset(ioc, force, sleepFlag);
3915 if (hard_reset_done < 0)
3916 return hard_reset_done;
3917
3918 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Diagnostic reset successful!\n",
3919 ioc->name));
3920
3921 cntdn = ((sleepFlag == CAN_SLEEP) ? HZ : 1000) * 2; /* 2 seconds */
3922 for (cnt=0; cnt<cntdn; cnt++) {
3923 ioc_state = mpt_GetIocState(ioc, 1);
3924 if ((ioc_state == MPI_IOC_STATE_READY) || (ioc_state == MPI_IOC_STATE_OPERATIONAL)) {
3925 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "KickStart successful! (cnt=%d)\n",
3926 ioc->name, cnt));
3927 return hard_reset_done;
3928 }
3929 if (sleepFlag == CAN_SLEEP) {
3930 msleep (10);
3931 } else {
3932 mdelay (10);
3933 }
3934 }
3935
3936 dinitprintk(ioc, printk(MYIOC_s_ERR_FMT "Failed to come READY after reset! IocState=%x\n",
3937 ioc->name, mpt_GetIocState(ioc, 0)));
3938 return -1;
3939}
3940
3941/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
3942/**
3943 * mpt_diag_reset - Perform hard reset of the adapter.
3944 * @ioc: Pointer to MPT_ADAPTER structure
3945 * @ignore: Set if to honor and clear to ignore
3946 * the reset history bit
3947 * @sleepFlag: CAN_SLEEP if called in a non-interrupt thread,
3948 * else set to NO_SLEEP (use mdelay instead)
3949 *
3950 * This routine places the adapter in diagnostic mode via the
3951 * WriteSequence register and then performs a hard reset of adapter
3952 * via the Diagnostic register. Adapter should be in ready state
3953 * upon successful completion.
3954 *
3955 * Returns: 1 hard reset successful
3956 * 0 no reset performed because reset history bit set
3957 * -2 enabling diagnostic mode failed
3958 * -3 diagnostic reset failed
3959 */
3960static int
3961mpt_diag_reset(MPT_ADAPTER *ioc, int ignore, int sleepFlag)
3962{
3963 u32 diag0val;
3964 u32 doorbell;
3965 int hard_reset_done = 0;
3966 int count = 0;
3967 u32 diag1val = 0;
3968 MpiFwHeader_t *cached_fw; /* Pointer to FW */
3969 u8 cb_idx;
3970
3971 /* Clear any existing interrupts */
3972 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
3973
3974 if (ioc->pcidev->device == MPI_MANUFACTPAGE_DEVID_SAS1078) {
3975
3976 if (!ignore)
3977 return 0;
3978
3979 drsprintk(ioc, printk(MYIOC_s_WARN_FMT "%s: Doorbell=%p; 1078 reset "
3980 "address=%p\n", ioc->name, __func__,
3981 &ioc->chip->Doorbell, &ioc->chip->Reset_1078));
3982 CHIPREG_WRITE32(&ioc->chip->Reset_1078, 0x07);
3983 if (sleepFlag == CAN_SLEEP)
3984 msleep(1);
3985 else
3986 mdelay(1);
3987
3988 /*
3989 * Call each currently registered protocol IOC reset handler
3990 * with pre-reset indication.
3991 * NOTE: If we're doing _IOC_BRINGUP, there can be no
3992 * MptResetHandlers[] registered yet.
3993 */
3994 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
3995 if (MptResetHandlers[cb_idx])
3996 (*(MptResetHandlers[cb_idx]))(ioc,
3997 MPT_IOC_PRE_RESET);
3998 }
3999
4000 for (count = 0; count < 60; count ++) {
4001 doorbell = CHIPREG_READ32(&ioc->chip->Doorbell);
4002 doorbell &= MPI_IOC_STATE_MASK;
4003
4004 drsprintk(ioc, printk(MYIOC_s_DEBUG_FMT
4005 "looking for READY STATE: doorbell=%x"
4006 " count=%d\n",
4007 ioc->name, doorbell, count));
4008
4009 if (doorbell == MPI_IOC_STATE_READY) {
4010 return 1;
4011 }
4012
4013 /* wait 1 sec */
4014 if (sleepFlag == CAN_SLEEP)
4015 msleep(1000);
4016 else
4017 mdelay(1000);
4018 }
4019 return -1;
4020 }
4021
4022 /* Use "Diagnostic reset" method! (only thing available!) */
4023 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
4024
4025 if (ioc->debug_level & MPT_DEBUG) {
4026 if (ioc->alt_ioc)
4027 diag1val = CHIPREG_READ32(&ioc->alt_ioc->chip->Diagnostic);
4028 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "DbG1: diag0=%08x, diag1=%08x\n",
4029 ioc->name, diag0val, diag1val));
4030 }
4031
4032 /* Do the reset if we are told to ignore the reset history
4033 * or if the reset history is 0
4034 */
4035 if (ignore || !(diag0val & MPI_DIAG_RESET_HISTORY)) {
4036 while ((diag0val & MPI_DIAG_DRWE) == 0) {
4037 /* Write magic sequence to WriteSequence register
4038 * Loop until in diagnostic mode
4039 */
4040 CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF);
4041 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_1ST_KEY_VALUE);
4042 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_2ND_KEY_VALUE);
4043 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_3RD_KEY_VALUE);
4044 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_4TH_KEY_VALUE);
4045 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_5TH_KEY_VALUE);
4046
4047 /* wait 100 msec */
4048 if (sleepFlag == CAN_SLEEP) {
4049 msleep (100);
4050 } else {
4051 mdelay (100);
4052 }
4053
4054 count++;
4055 if (count > 20) {
4056 printk(MYIOC_s_ERR_FMT "Enable Diagnostic mode FAILED! (%02xh)\n",
4057 ioc->name, diag0val);
4058 return -2;
4059
4060 }
4061
4062 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
4063
4064 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Wrote magic DiagWriteEn sequence (%x)\n",
4065 ioc->name, diag0val));
4066 }
4067
4068 if (ioc->debug_level & MPT_DEBUG) {
4069 if (ioc->alt_ioc)
4070 diag1val = CHIPREG_READ32(&ioc->alt_ioc->chip->Diagnostic);
4071 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "DbG2: diag0=%08x, diag1=%08x\n",
4072 ioc->name, diag0val, diag1val));
4073 }
4074 /*
4075 * Disable the ARM (Bug fix)
4076 *
4077 */
4078 CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val | MPI_DIAG_DISABLE_ARM);
4079 mdelay(1);
4080
4081 /*
4082 * Now hit the reset bit in the Diagnostic register
4083 * (THE BIG HAMMER!) (Clears DRWE bit).
4084 */
4085 CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val | MPI_DIAG_RESET_ADAPTER);
4086 hard_reset_done = 1;
4087 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Diagnostic reset performed\n",
4088 ioc->name));
4089
4090 /*
4091 * Call each currently registered protocol IOC reset handler
4092 * with pre-reset indication.
4093 * NOTE: If we're doing _IOC_BRINGUP, there can be no
4094 * MptResetHandlers[] registered yet.
4095 */
4096 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
4097 if (MptResetHandlers[cb_idx]) {
4098 mpt_signal_reset(cb_idx,
4099 ioc, MPT_IOC_PRE_RESET);
4100 if (ioc->alt_ioc) {
4101 mpt_signal_reset(cb_idx,
4102 ioc->alt_ioc, MPT_IOC_PRE_RESET);
4103 }
4104 }
4105 }
4106
4107 if (ioc->cached_fw)
4108 cached_fw = (MpiFwHeader_t *)ioc->cached_fw;
4109 else if (ioc->alt_ioc && ioc->alt_ioc->cached_fw)
4110 cached_fw = (MpiFwHeader_t *)ioc->alt_ioc->cached_fw;
4111 else
4112 cached_fw = NULL;
4113 if (cached_fw) {
4114 /* If the DownloadBoot operation fails, the
4115 * IOC will be left unusable. This is a fatal error
4116 * case. _diag_reset will return < 0
4117 */
4118 for (count = 0; count < 30; count ++) {
4119 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
4120 if (!(diag0val & MPI_DIAG_RESET_ADAPTER)) {
4121 break;
4122 }
4123
4124 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "cached_fw: diag0val=%x count=%d\n",
4125 ioc->name, diag0val, count));
4126 /* wait 1 sec */
4127 if (sleepFlag == CAN_SLEEP) {
4128 msleep (1000);
4129 } else {
4130 mdelay (1000);
4131 }
4132 }
4133 if ((count = mpt_downloadboot(ioc, cached_fw, sleepFlag)) < 0) {
4134 printk(MYIOC_s_WARN_FMT
4135 "firmware downloadboot failure (%d)!\n", ioc->name, count);
4136 }
4137
4138 } else {
4139 /* Wait for FW to reload and for board
4140 * to go to the READY state.
4141 * Maximum wait is 60 seconds.
4142 * If fail, no error will check again
4143 * with calling program.
4144 */
4145 for (count = 0; count < 60; count ++) {
4146 doorbell = CHIPREG_READ32(&ioc->chip->Doorbell);
4147 doorbell &= MPI_IOC_STATE_MASK;
4148
4149 drsprintk(ioc, printk(MYIOC_s_DEBUG_FMT
4150 "looking for READY STATE: doorbell=%x"
4151 " count=%d\n", ioc->name, doorbell, count));
4152
4153 if (doorbell == MPI_IOC_STATE_READY) {
4154 break;
4155 }
4156
4157 /* wait 1 sec */
4158 if (sleepFlag == CAN_SLEEP) {
4159 msleep (1000);
4160 } else {
4161 mdelay (1000);
4162 }
4163 }
4164
4165 if (doorbell != MPI_IOC_STATE_READY)
4166 printk(MYIOC_s_ERR_FMT "Failed to come READY "
4167 "after reset! IocState=%x", ioc->name,
4168 doorbell);
4169 }
4170 }
4171
4172 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
4173 if (ioc->debug_level & MPT_DEBUG) {
4174 if (ioc->alt_ioc)
4175 diag1val = CHIPREG_READ32(&ioc->alt_ioc->chip->Diagnostic);
4176 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "DbG3: diag0=%08x, diag1=%08x\n",
4177 ioc->name, diag0val, diag1val));
4178 }
4179
4180 /* Clear RESET_HISTORY bit! Place board in the
4181 * diagnostic mode to update the diag register.
4182 */
4183 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
4184 count = 0;
4185 while ((diag0val & MPI_DIAG_DRWE) == 0) {
4186 /* Write magic sequence to WriteSequence register
4187 * Loop until in diagnostic mode
4188 */
4189 CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF);
4190 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_1ST_KEY_VALUE);
4191 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_2ND_KEY_VALUE);
4192 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_3RD_KEY_VALUE);
4193 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_4TH_KEY_VALUE);
4194 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_5TH_KEY_VALUE);
4195
4196 /* wait 100 msec */
4197 if (sleepFlag == CAN_SLEEP) {
4198 msleep (100);
4199 } else {
4200 mdelay (100);
4201 }
4202
4203 count++;
4204 if (count > 20) {
4205 printk(MYIOC_s_ERR_FMT "Enable Diagnostic mode FAILED! (%02xh)\n",
4206 ioc->name, diag0val);
4207 break;
4208 }
4209 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
4210 }
4211 diag0val &= ~MPI_DIAG_RESET_HISTORY;
4212 CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val);
4213 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
4214 if (diag0val & MPI_DIAG_RESET_HISTORY) {
4215 printk(MYIOC_s_WARN_FMT "ResetHistory bit failed to clear!\n",
4216 ioc->name);
4217 }
4218
4219 /* Disable Diagnostic Mode
4220 */
4221 CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFFFFFFFF);
4222
4223 /* Check FW reload status flags.
4224 */
4225 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
4226 if (diag0val & (MPI_DIAG_FLASH_BAD_SIG | MPI_DIAG_RESET_ADAPTER | MPI_DIAG_DISABLE_ARM)) {
4227 printk(MYIOC_s_ERR_FMT "Diagnostic reset FAILED! (%02xh)\n",
4228 ioc->name, diag0val);
4229 return -3;
4230 }
4231
4232 if (ioc->debug_level & MPT_DEBUG) {
4233 if (ioc->alt_ioc)
4234 diag1val = CHIPREG_READ32(&ioc->alt_ioc->chip->Diagnostic);
4235 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "DbG4: diag0=%08x, diag1=%08x\n",
4236 ioc->name, diag0val, diag1val));
4237 }
4238
4239 /*
4240 * Reset flag that says we've enabled event notification
4241 */
4242 ioc->facts.EventState = 0;
4243
4244 if (ioc->alt_ioc)
4245 ioc->alt_ioc->facts.EventState = 0;
4246
4247 return hard_reset_done;
4248}
4249
4250/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
4251/**
4252 * SendIocReset - Send IOCReset request to MPT adapter.
4253 * @ioc: Pointer to MPT_ADAPTER structure
4254 * @reset_type: reset type, expected values are
4255 * %MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET or %MPI_FUNCTION_IO_UNIT_RESET
4256 * @sleepFlag: Specifies whether the process can sleep
4257 *
4258 * Send IOCReset request to the MPT adapter.
4259 *
4260 * Returns 0 for success, non-zero for failure.
4261 */
4262static int
4263SendIocReset(MPT_ADAPTER *ioc, u8 reset_type, int sleepFlag)
4264{
4265 int r;
4266 u32 state;
4267 int cntdn, count;
4268
4269 drsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending IOC reset(0x%02x)!\n",
4270 ioc->name, reset_type));
4271 CHIPREG_WRITE32(&ioc->chip->Doorbell, reset_type<<MPI_DOORBELL_FUNCTION_SHIFT);
4272 if ((r = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0)
4273 return r;
4274
4275 /* FW ACK'd request, wait for READY state
4276 */
4277 count = 0;
4278 cntdn = ((sleepFlag == CAN_SLEEP) ? HZ : 1000) * 15; /* 15 seconds */
4279
4280 while ((state = mpt_GetIocState(ioc, 1)) != MPI_IOC_STATE_READY) {
4281 cntdn--;
4282 count++;
4283 if (!cntdn) {
4284 if (sleepFlag != CAN_SLEEP)
4285 count *= 10;
4286
4287 printk(MYIOC_s_ERR_FMT
4288 "Wait IOC_READY state (0x%x) timeout(%d)!\n",
4289 ioc->name, state, (int)((count+5)/HZ));
4290 return -ETIME;
4291 }
4292
4293 if (sleepFlag == CAN_SLEEP) {
4294 msleep(1);
4295 } else {
4296 mdelay (1); /* 1 msec delay */
4297 }
4298 }
4299
4300 /* TODO!
4301 * Cleanup all event stuff for this IOC; re-issue EventNotification
4302 * request if needed.
4303 */
4304 if (ioc->facts.Function)
4305 ioc->facts.EventState = 0;
4306
4307 return 0;
4308}
4309
4310/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
4311/**
4312 * initChainBuffers - Allocate memory for and initialize chain buffers
4313 * @ioc: Pointer to MPT_ADAPTER structure
4314 *
4315 * Allocates memory for and initializes chain buffers,
4316 * chain buffer control arrays and spinlock.
4317 */
4318static int
4319initChainBuffers(MPT_ADAPTER *ioc)
4320{
4321 u8 *mem;
4322 int sz, ii, num_chain;
4323 int scale, num_sge, numSGE;
4324
4325 /* ReqToChain size must equal the req_depth
4326 * index = req_idx
4327 */
4328 if (ioc->ReqToChain == NULL) {
4329 sz = ioc->req_depth * sizeof(int);
4330 mem = kmalloc(sz, GFP_ATOMIC);
4331 if (mem == NULL)
4332 return -1;
4333
4334 ioc->ReqToChain = (int *) mem;
4335 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ReqToChain alloc @ %p, sz=%d bytes\n",
4336 ioc->name, mem, sz));
4337 mem = kmalloc(sz, GFP_ATOMIC);
4338 if (mem == NULL)
4339 return -1;
4340
4341 ioc->RequestNB = (int *) mem;
4342 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "RequestNB alloc @ %p, sz=%d bytes\n",
4343 ioc->name, mem, sz));
4344 }
4345 for (ii = 0; ii < ioc->req_depth; ii++) {
4346 ioc->ReqToChain[ii] = MPT_HOST_NO_CHAIN;
4347 }
4348
4349 /* ChainToChain size must equal the total number
4350 * of chain buffers to be allocated.
4351 * index = chain_idx
4352 *
4353 * Calculate the number of chain buffers needed(plus 1) per I/O
4354 * then multiply the maximum number of simultaneous cmds
4355 *
4356 * num_sge = num sge in request frame + last chain buffer
4357 * scale = num sge per chain buffer if no chain element
4358 */
4359 scale = ioc->req_sz / ioc->SGE_size;
4360 if (ioc->sg_addr_size == sizeof(u64))
4361 num_sge = scale + (ioc->req_sz - 60) / ioc->SGE_size;
4362 else
4363 num_sge = 1 + scale + (ioc->req_sz - 64) / ioc->SGE_size;
4364
4365 if (ioc->sg_addr_size == sizeof(u64)) {
4366 numSGE = (scale - 1) * (ioc->facts.MaxChainDepth-1) + scale +
4367 (ioc->req_sz - 60) / ioc->SGE_size;
4368 } else {
4369 numSGE = 1 + (scale - 1) * (ioc->facts.MaxChainDepth-1) +
4370 scale + (ioc->req_sz - 64) / ioc->SGE_size;
4371 }
4372 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "num_sge=%d numSGE=%d\n",
4373 ioc->name, num_sge, numSGE));
4374
4375 if (ioc->bus_type == FC) {
4376 if (numSGE > MPT_SCSI_FC_SG_DEPTH)
4377 numSGE = MPT_SCSI_FC_SG_DEPTH;
4378 } else {
4379 if (numSGE > MPT_SCSI_SG_DEPTH)
4380 numSGE = MPT_SCSI_SG_DEPTH;
4381 }
4382
4383 num_chain = 1;
4384 while (numSGE - num_sge > 0) {
4385 num_chain++;
4386 num_sge += (scale - 1);
4387 }
4388 num_chain++;
4389
4390 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Now numSGE=%d num_sge=%d num_chain=%d\n",
4391 ioc->name, numSGE, num_sge, num_chain));
4392
4393 if (ioc->bus_type == SPI)
4394 num_chain *= MPT_SCSI_CAN_QUEUE;
4395 else if (ioc->bus_type == SAS)
4396 num_chain *= MPT_SAS_CAN_QUEUE;
4397 else
4398 num_chain *= MPT_FC_CAN_QUEUE;
4399
4400 ioc->num_chain = num_chain;
4401
4402 sz = num_chain * sizeof(int);
4403 if (ioc->ChainToChain == NULL) {
4404 mem = kmalloc(sz, GFP_ATOMIC);
4405 if (mem == NULL)
4406 return -1;
4407
4408 ioc->ChainToChain = (int *) mem;
4409 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ChainToChain alloc @ %p, sz=%d bytes\n",
4410 ioc->name, mem, sz));
4411 } else {
4412 mem = (u8 *) ioc->ChainToChain;
4413 }
4414 memset(mem, 0xFF, sz);
4415 return num_chain;
4416}
4417
4418/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
4419/**
4420 * PrimeIocFifos - Initialize IOC request and reply FIFOs.
4421 * @ioc: Pointer to MPT_ADAPTER structure
4422 *
4423 * This routine allocates memory for the MPT reply and request frame
4424 * pools (if necessary), and primes the IOC reply FIFO with
4425 * reply frames.
4426 *
4427 * Returns 0 for success, non-zero for failure.
4428 */
4429static int
4430PrimeIocFifos(MPT_ADAPTER *ioc)
4431{
4432 MPT_FRAME_HDR *mf;
4433 unsigned long flags;
4434 dma_addr_t alloc_dma;
4435 u8 *mem;
4436 int i, reply_sz, sz, total_size, num_chain;
4437 u64 dma_mask;
4438
4439 dma_mask = 0;
4440
4441 /* Prime reply FIFO... */
4442
4443 if (ioc->reply_frames == NULL) {
4444 if ( (num_chain = initChainBuffers(ioc)) < 0)
4445 return -1;
4446 /*
4447 * 1078 errata workaround for the 36GB limitation
4448 */
4449 if (ioc->pcidev->device == MPI_MANUFACTPAGE_DEVID_SAS1078 &&
4450 ioc->dma_mask > DMA_BIT_MASK(35)) {
4451 if (!pci_set_dma_mask(ioc->pcidev, DMA_BIT_MASK(32))
4452 && !pci_set_consistent_dma_mask(ioc->pcidev,
4453 DMA_BIT_MASK(32))) {
4454 dma_mask = DMA_BIT_MASK(35);
4455 d36memprintk(ioc, printk(MYIOC_s_DEBUG_FMT
4456 "setting 35 bit addressing for "
4457 "Request/Reply/Chain and Sense Buffers\n",
4458 ioc->name));
4459 } else {
4460 /*Reseting DMA mask to 64 bit*/
4461 pci_set_dma_mask(ioc->pcidev,
4462 DMA_BIT_MASK(64));
4463 pci_set_consistent_dma_mask(ioc->pcidev,
4464 DMA_BIT_MASK(64));
4465
4466 printk(MYIOC_s_ERR_FMT
4467 "failed setting 35 bit addressing for "
4468 "Request/Reply/Chain and Sense Buffers\n",
4469 ioc->name);
4470 return -1;
4471 }
4472 }
4473
4474 total_size = reply_sz = (ioc->reply_sz * ioc->reply_depth);
4475 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ReplyBuffer sz=%d bytes, ReplyDepth=%d\n",
4476 ioc->name, ioc->reply_sz, ioc->reply_depth));
4477 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ReplyBuffer sz=%d[%x] bytes\n",
4478 ioc->name, reply_sz, reply_sz));
4479
4480 sz = (ioc->req_sz * ioc->req_depth);
4481 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "RequestBuffer sz=%d bytes, RequestDepth=%d\n",
4482 ioc->name, ioc->req_sz, ioc->req_depth));
4483 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "RequestBuffer sz=%d[%x] bytes\n",
4484 ioc->name, sz, sz));
4485 total_size += sz;
4486
4487 sz = num_chain * ioc->req_sz; /* chain buffer pool size */
4488 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ChainBuffer sz=%d bytes, ChainDepth=%d\n",
4489 ioc->name, ioc->req_sz, num_chain));
4490 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ChainBuffer sz=%d[%x] bytes num_chain=%d\n",
4491 ioc->name, sz, sz, num_chain));
4492
4493 total_size += sz;
4494 mem = pci_alloc_consistent(ioc->pcidev, total_size, &alloc_dma);
4495 if (mem == NULL) {
4496 printk(MYIOC_s_ERR_FMT "Unable to allocate Reply, Request, Chain Buffers!\n",
4497 ioc->name);
4498 goto out_fail;
4499 }
4500
4501 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Total alloc @ %p[%p], sz=%d[%x] bytes\n",
4502 ioc->name, mem, (void *)(ulong)alloc_dma, total_size, total_size));
4503
4504 memset(mem, 0, total_size);
4505 ioc->alloc_total += total_size;
4506 ioc->alloc = mem;
4507 ioc->alloc_dma = alloc_dma;
4508 ioc->alloc_sz = total_size;
4509 ioc->reply_frames = (MPT_FRAME_HDR *) mem;
4510 ioc->reply_frames_low_dma = (u32) (alloc_dma & 0xFFFFFFFF);
4511
4512 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ReplyBuffers @ %p[%p]\n",
4513 ioc->name, ioc->reply_frames, (void *)(ulong)alloc_dma));
4514
4515 alloc_dma += reply_sz;
4516 mem += reply_sz;
4517
4518 /* Request FIFO - WE manage this! */
4519
4520 ioc->req_frames = (MPT_FRAME_HDR *) mem;
4521 ioc->req_frames_dma = alloc_dma;
4522
4523 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "RequestBuffers @ %p[%p]\n",
4524 ioc->name, mem, (void *)(ulong)alloc_dma));
4525
4526 ioc->req_frames_low_dma = (u32) (alloc_dma & 0xFFFFFFFF);
4527
4528 for (i = 0; i < ioc->req_depth; i++) {
4529 alloc_dma += ioc->req_sz;
4530 mem += ioc->req_sz;
4531 }
4532
4533 ioc->ChainBuffer = mem;
4534 ioc->ChainBufferDMA = alloc_dma;
4535
4536 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ChainBuffers @ %p(%p)\n",
4537 ioc->name, ioc->ChainBuffer, (void *)(ulong)ioc->ChainBufferDMA));
4538
4539 /* Initialize the free chain Q.
4540 */
4541
4542 INIT_LIST_HEAD(&ioc->FreeChainQ);
4543
4544 /* Post the chain buffers to the FreeChainQ.
4545 */
4546 mem = (u8 *)ioc->ChainBuffer;
4547 for (i=0; i < num_chain; i++) {
4548 mf = (MPT_FRAME_HDR *) mem;
4549 list_add_tail(&mf->u.frame.linkage.list, &ioc->FreeChainQ);
4550 mem += ioc->req_sz;
4551 }
4552
4553 /* Initialize Request frames linked list
4554 */
4555 alloc_dma = ioc->req_frames_dma;
4556 mem = (u8 *) ioc->req_frames;
4557
4558 spin_lock_irqsave(&ioc->FreeQlock, flags);
4559 INIT_LIST_HEAD(&ioc->FreeQ);
4560 for (i = 0; i < ioc->req_depth; i++) {
4561 mf = (MPT_FRAME_HDR *) mem;
4562
4563 /* Queue REQUESTs *internally*! */
4564 list_add_tail(&mf->u.frame.linkage.list, &ioc->FreeQ);
4565
4566 mem += ioc->req_sz;
4567 }
4568 spin_unlock_irqrestore(&ioc->FreeQlock, flags);
4569
4570 sz = (ioc->req_depth * MPT_SENSE_BUFFER_ALLOC);
4571 ioc->sense_buf_pool =
4572 pci_alloc_consistent(ioc->pcidev, sz, &ioc->sense_buf_pool_dma);
4573 if (ioc->sense_buf_pool == NULL) {
4574 printk(MYIOC_s_ERR_FMT "Unable to allocate Sense Buffers!\n",
4575 ioc->name);
4576 goto out_fail;
4577 }
4578
4579 ioc->sense_buf_low_dma = (u32) (ioc->sense_buf_pool_dma & 0xFFFFFFFF);
4580 ioc->alloc_total += sz;
4581 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "SenseBuffers @ %p[%p]\n",
4582 ioc->name, ioc->sense_buf_pool, (void *)(ulong)ioc->sense_buf_pool_dma));
4583
4584 }
4585
4586 /* Post Reply frames to FIFO
4587 */
4588 alloc_dma = ioc->alloc_dma;
4589 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ReplyBuffers @ %p[%p]\n",
4590 ioc->name, ioc->reply_frames, (void *)(ulong)alloc_dma));
4591
4592 for (i = 0; i < ioc->reply_depth; i++) {
4593 /* Write each address to the IOC! */
4594 CHIPREG_WRITE32(&ioc->chip->ReplyFifo, alloc_dma);
4595 alloc_dma += ioc->reply_sz;
4596 }
4597
4598 if (dma_mask == DMA_BIT_MASK(35) && !pci_set_dma_mask(ioc->pcidev,
4599 ioc->dma_mask) && !pci_set_consistent_dma_mask(ioc->pcidev,
4600 ioc->dma_mask))
4601 d36memprintk(ioc, printk(MYIOC_s_DEBUG_FMT
4602 "restoring 64 bit addressing\n", ioc->name));
4603
4604 return 0;
4605
4606out_fail:
4607
4608 if (ioc->alloc != NULL) {
4609 sz = ioc->alloc_sz;
4610 pci_free_consistent(ioc->pcidev,
4611 sz,
4612 ioc->alloc, ioc->alloc_dma);
4613 ioc->reply_frames = NULL;
4614 ioc->req_frames = NULL;
4615 ioc->alloc_total -= sz;
4616 }
4617 if (ioc->sense_buf_pool != NULL) {
4618 sz = (ioc->req_depth * MPT_SENSE_BUFFER_ALLOC);
4619 pci_free_consistent(ioc->pcidev,
4620 sz,
4621 ioc->sense_buf_pool, ioc->sense_buf_pool_dma);
4622 ioc->sense_buf_pool = NULL;
4623 }
4624
4625 if (dma_mask == DMA_BIT_MASK(35) && !pci_set_dma_mask(ioc->pcidev,
4626 DMA_BIT_MASK(64)) && !pci_set_consistent_dma_mask(ioc->pcidev,
4627 DMA_BIT_MASK(64)))
4628 d36memprintk(ioc, printk(MYIOC_s_DEBUG_FMT
4629 "restoring 64 bit addressing\n", ioc->name));
4630
4631 return -1;
4632}
4633
4634/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
4635/**
4636 * mpt_handshake_req_reply_wait - Send MPT request to and receive reply
4637 * from IOC via doorbell handshake method.
4638 * @ioc: Pointer to MPT_ADAPTER structure
4639 * @reqBytes: Size of the request in bytes
4640 * @req: Pointer to MPT request frame
4641 * @replyBytes: Expected size of the reply in bytes
4642 * @u16reply: Pointer to area where reply should be written
4643 * @maxwait: Max wait time for a reply (in seconds)
4644 * @sleepFlag: Specifies whether the process can sleep
4645 *
4646 * NOTES: It is the callers responsibility to byte-swap fields in the
4647 * request which are greater than 1 byte in size. It is also the
4648 * callers responsibility to byte-swap response fields which are
4649 * greater than 1 byte in size.
4650 *
4651 * Returns 0 for success, non-zero for failure.
4652 */
4653static int
4654mpt_handshake_req_reply_wait(MPT_ADAPTER *ioc, int reqBytes, u32 *req,
4655 int replyBytes, u16 *u16reply, int maxwait, int sleepFlag)
4656{
4657 MPIDefaultReply_t *mptReply;
4658 int failcnt = 0;
4659 int t;
4660
4661 /*
4662 * Get ready to cache a handshake reply
4663 */
4664 ioc->hs_reply_idx = 0;
4665 mptReply = (MPIDefaultReply_t *) ioc->hs_reply;
4666 mptReply->MsgLength = 0;
4667
4668 /*
4669 * Make sure there are no doorbells (WRITE 0 to IntStatus reg),
4670 * then tell IOC that we want to handshake a request of N words.
4671 * (WRITE u32val to Doorbell reg).
4672 */
4673 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
4674 CHIPREG_WRITE32(&ioc->chip->Doorbell,
4675 ((MPI_FUNCTION_HANDSHAKE<<MPI_DOORBELL_FUNCTION_SHIFT) |
4676 ((reqBytes/4)<<MPI_DOORBELL_ADD_DWORDS_SHIFT)));
4677
4678 /*
4679 * Wait for IOC's doorbell handshake int
4680 */
4681 if ((t = WaitForDoorbellInt(ioc, 5, sleepFlag)) < 0)
4682 failcnt++;
4683
4684 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "HandShake request start reqBytes=%d, WaitCnt=%d%s\n",
4685 ioc->name, reqBytes, t, failcnt ? " - MISSING DOORBELL HANDSHAKE!" : ""));
4686
4687 /* Read doorbell and check for active bit */
4688 if (!(CHIPREG_READ32(&ioc->chip->Doorbell) & MPI_DOORBELL_ACTIVE))
4689 return -1;
4690
4691 /*
4692 * Clear doorbell int (WRITE 0 to IntStatus reg),
4693 * then wait for IOC to ACKnowledge that it's ready for
4694 * our handshake request.
4695 */
4696 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
4697 if (!failcnt && (t = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0)
4698 failcnt++;
4699
4700 if (!failcnt) {
4701 int ii;
4702 u8 *req_as_bytes = (u8 *) req;
4703
4704 /*
4705 * Stuff request words via doorbell handshake,
4706 * with ACK from IOC for each.
4707 */
4708 for (ii = 0; !failcnt && ii < reqBytes/4; ii++) {
4709 u32 word = ((req_as_bytes[(ii*4) + 0] << 0) |
4710 (req_as_bytes[(ii*4) + 1] << 8) |
4711 (req_as_bytes[(ii*4) + 2] << 16) |
4712 (req_as_bytes[(ii*4) + 3] << 24));
4713
4714 CHIPREG_WRITE32(&ioc->chip->Doorbell, word);
4715 if ((t = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0)
4716 failcnt++;
4717 }
4718
4719 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Handshake request frame (@%p) header\n", ioc->name, req));
4720 DBG_DUMP_REQUEST_FRAME_HDR(ioc, (u32 *)req);
4721
4722 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "HandShake request post done, WaitCnt=%d%s\n",
4723 ioc->name, t, failcnt ? " - MISSING DOORBELL ACK!" : ""));
4724
4725 /*
4726 * Wait for completion of doorbell handshake reply from the IOC
4727 */
4728 if (!failcnt && (t = WaitForDoorbellReply(ioc, maxwait, sleepFlag)) < 0)
4729 failcnt++;
4730
4731 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "HandShake reply count=%d%s\n",
4732 ioc->name, t, failcnt ? " - MISSING DOORBELL REPLY!" : ""));
4733
4734 /*
4735 * Copy out the cached reply...
4736 */
4737 for (ii=0; ii < min(replyBytes/2,mptReply->MsgLength*2); ii++)
4738 u16reply[ii] = ioc->hs_reply[ii];
4739 } else {
4740 return -99;
4741 }
4742
4743 return -failcnt;
4744}
4745
4746/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
4747/**
4748 * WaitForDoorbellAck - Wait for IOC doorbell handshake acknowledge
4749 * @ioc: Pointer to MPT_ADAPTER structure
4750 * @howlong: How long to wait (in seconds)
4751 * @sleepFlag: Specifies whether the process can sleep
4752 *
4753 * This routine waits (up to ~2 seconds max) for IOC doorbell
4754 * handshake ACKnowledge, indicated by the IOP_DOORBELL_STATUS
4755 * bit in its IntStatus register being clear.
4756 *
4757 * Returns a negative value on failure, else wait loop count.
4758 */
4759static int
4760WaitForDoorbellAck(MPT_ADAPTER *ioc, int howlong, int sleepFlag)
4761{
4762 int cntdn;
4763 int count = 0;
4764 u32 intstat=0;
4765
4766 cntdn = 1000 * howlong;
4767
4768 if (sleepFlag == CAN_SLEEP) {
4769 while (--cntdn) {
4770 msleep (1);
4771 intstat = CHIPREG_READ32(&ioc->chip->IntStatus);
4772 if (! (intstat & MPI_HIS_IOP_DOORBELL_STATUS))
4773 break;
4774 count++;
4775 }
4776 } else {
4777 while (--cntdn) {
4778 udelay (1000);
4779 intstat = CHIPREG_READ32(&ioc->chip->IntStatus);
4780 if (! (intstat & MPI_HIS_IOP_DOORBELL_STATUS))
4781 break;
4782 count++;
4783 }
4784 }
4785
4786 if (cntdn) {
4787 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "WaitForDoorbell ACK (count=%d)\n",
4788 ioc->name, count));
4789 return count;
4790 }
4791
4792 printk(MYIOC_s_ERR_FMT "Doorbell ACK timeout (count=%d), IntStatus=%x!\n",
4793 ioc->name, count, intstat);
4794 return -1;
4795}
4796
4797/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
4798/**
4799 * WaitForDoorbellInt - Wait for IOC to set its doorbell interrupt bit
4800 * @ioc: Pointer to MPT_ADAPTER structure
4801 * @howlong: How long to wait (in seconds)
4802 * @sleepFlag: Specifies whether the process can sleep
4803 *
4804 * This routine waits (up to ~2 seconds max) for IOC doorbell interrupt
4805 * (MPI_HIS_DOORBELL_INTERRUPT) to be set in the IntStatus register.
4806 *
4807 * Returns a negative value on failure, else wait loop count.
4808 */
4809static int
4810WaitForDoorbellInt(MPT_ADAPTER *ioc, int howlong, int sleepFlag)
4811{
4812 int cntdn;
4813 int count = 0;
4814 u32 intstat=0;
4815
4816 cntdn = 1000 * howlong;
4817 if (sleepFlag == CAN_SLEEP) {
4818 while (--cntdn) {
4819 intstat = CHIPREG_READ32(&ioc->chip->IntStatus);
4820 if (intstat & MPI_HIS_DOORBELL_INTERRUPT)
4821 break;
4822 msleep(1);
4823 count++;
4824 }
4825 } else {
4826 while (--cntdn) {
4827 intstat = CHIPREG_READ32(&ioc->chip->IntStatus);
4828 if (intstat & MPI_HIS_DOORBELL_INTERRUPT)
4829 break;
4830 udelay (1000);
4831 count++;
4832 }
4833 }
4834
4835 if (cntdn) {
4836 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "WaitForDoorbell INT (cnt=%d) howlong=%d\n",
4837 ioc->name, count, howlong));
4838 return count;
4839 }
4840
4841 printk(MYIOC_s_ERR_FMT "Doorbell INT timeout (count=%d), IntStatus=%x!\n",
4842 ioc->name, count, intstat);
4843 return -1;
4844}
4845
4846/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
4847/**
4848 * WaitForDoorbellReply - Wait for and capture an IOC handshake reply.
4849 * @ioc: Pointer to MPT_ADAPTER structure
4850 * @howlong: How long to wait (in seconds)
4851 * @sleepFlag: Specifies whether the process can sleep
4852 *
4853 * This routine polls the IOC for a handshake reply, 16 bits at a time.
4854 * Reply is cached to IOC private area large enough to hold a maximum
4855 * of 128 bytes of reply data.
4856 *
4857 * Returns a negative value on failure, else size of reply in WORDS.
4858 */
4859static int
4860WaitForDoorbellReply(MPT_ADAPTER *ioc, int howlong, int sleepFlag)
4861{
4862 int u16cnt = 0;
4863 int failcnt = 0;
4864 int t;
4865 u16 *hs_reply = ioc->hs_reply;
4866 volatile MPIDefaultReply_t *mptReply = (MPIDefaultReply_t *) ioc->hs_reply;
4867 u16 hword;
4868
4869 hs_reply[0] = hs_reply[1] = hs_reply[7] = 0;
4870
4871 /*
4872 * Get first two u16's so we can look at IOC's intended reply MsgLength
4873 */
4874 u16cnt=0;
4875 if ((t = WaitForDoorbellInt(ioc, howlong, sleepFlag)) < 0) {
4876 failcnt++;
4877 } else {
4878 hs_reply[u16cnt++] = le16_to_cpu(CHIPREG_READ32(&ioc->chip->Doorbell) & 0x0000FFFF);
4879 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
4880 if ((t = WaitForDoorbellInt(ioc, 5, sleepFlag)) < 0)
4881 failcnt++;
4882 else {
4883 hs_reply[u16cnt++] = le16_to_cpu(CHIPREG_READ32(&ioc->chip->Doorbell) & 0x0000FFFF);
4884 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
4885 }
4886 }
4887
4888 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "WaitCnt=%d First handshake reply word=%08x%s\n",
4889 ioc->name, t, le32_to_cpu(*(u32 *)hs_reply),
4890 failcnt ? " - MISSING DOORBELL HANDSHAKE!" : ""));
4891
4892 /*
4893 * If no error (and IOC said MsgLength is > 0), piece together
4894 * reply 16 bits at a time.
4895 */
4896 for (u16cnt=2; !failcnt && u16cnt < (2 * mptReply->MsgLength); u16cnt++) {
4897 if ((t = WaitForDoorbellInt(ioc, 5, sleepFlag)) < 0)
4898 failcnt++;
4899 hword = le16_to_cpu(CHIPREG_READ32(&ioc->chip->Doorbell) & 0x0000FFFF);
4900 /* don't overflow our IOC hs_reply[] buffer! */
4901 if (u16cnt < ARRAY_SIZE(ioc->hs_reply))
4902 hs_reply[u16cnt] = hword;
4903 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
4904 }
4905
4906 if (!failcnt && (t = WaitForDoorbellInt(ioc, 5, sleepFlag)) < 0)
4907 failcnt++;
4908 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
4909
4910 if (failcnt) {
4911 printk(MYIOC_s_ERR_FMT "Handshake reply failure!\n",
4912 ioc->name);
4913 return -failcnt;
4914 }
4915#if 0
4916 else if (u16cnt != (2 * mptReply->MsgLength)) {
4917 return -101;
4918 }
4919 else if ((mptReply->IOCStatus & MPI_IOCSTATUS_MASK) != MPI_IOCSTATUS_SUCCESS) {
4920 return -102;
4921 }
4922#endif
4923
4924 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Got Handshake reply:\n", ioc->name));
4925 DBG_DUMP_REPLY_FRAME(ioc, (u32 *)mptReply);
4926
4927 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "WaitForDoorbell REPLY WaitCnt=%d (sz=%d)\n",
4928 ioc->name, t, u16cnt/2));
4929 return u16cnt/2;
4930}
4931
4932/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
4933/**
4934 * GetLanConfigPages - Fetch LANConfig pages.
4935 * @ioc: Pointer to MPT_ADAPTER structure
4936 *
4937 * Return: 0 for success
4938 * -ENOMEM if no memory available
4939 * -EPERM if not allowed due to ISR context
4940 * -EAGAIN if no msg frames currently available
4941 * -EFAULT for non-successful reply or no reply (timeout)
4942 */
4943static int
4944GetLanConfigPages(MPT_ADAPTER *ioc)
4945{
4946 ConfigPageHeader_t hdr;
4947 CONFIGPARMS cfg;
4948 LANPage0_t *ppage0_alloc;
4949 dma_addr_t page0_dma;
4950 LANPage1_t *ppage1_alloc;
4951 dma_addr_t page1_dma;
4952 int rc = 0;
4953 int data_sz;
4954 int copy_sz;
4955
4956 /* Get LAN Page 0 header */
4957 hdr.PageVersion = 0;
4958 hdr.PageLength = 0;
4959 hdr.PageNumber = 0;
4960 hdr.PageType = MPI_CONFIG_PAGETYPE_LAN;
4961 cfg.cfghdr.hdr = &hdr;
4962 cfg.physAddr = -1;
4963 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
4964 cfg.dir = 0;
4965 cfg.pageAddr = 0;
4966 cfg.timeout = 0;
4967
4968 if ((rc = mpt_config(ioc, &cfg)) != 0)
4969 return rc;
4970
4971 if (hdr.PageLength > 0) {
4972 data_sz = hdr.PageLength * 4;
4973 ppage0_alloc = (LANPage0_t *) pci_alloc_consistent(ioc->pcidev, data_sz, &page0_dma);
4974 rc = -ENOMEM;
4975 if (ppage0_alloc) {
4976 memset((u8 *)ppage0_alloc, 0, data_sz);
4977 cfg.physAddr = page0_dma;
4978 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
4979
4980 if ((rc = mpt_config(ioc, &cfg)) == 0) {
4981 /* save the data */
4982 copy_sz = min_t(int, sizeof(LANPage0_t), data_sz);
4983 memcpy(&ioc->lan_cnfg_page0, ppage0_alloc, copy_sz);
4984
4985 }
4986
4987 pci_free_consistent(ioc->pcidev, data_sz, (u8 *) ppage0_alloc, page0_dma);
4988
4989 /* FIXME!
4990 * Normalize endianness of structure data,
4991 * by byte-swapping all > 1 byte fields!
4992 */
4993
4994 }
4995
4996 if (rc)
4997 return rc;
4998 }
4999
5000 /* Get LAN Page 1 header */
5001 hdr.PageVersion = 0;
5002 hdr.PageLength = 0;
5003 hdr.PageNumber = 1;
5004 hdr.PageType = MPI_CONFIG_PAGETYPE_LAN;
5005 cfg.cfghdr.hdr = &hdr;
5006 cfg.physAddr = -1;
5007 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
5008 cfg.dir = 0;
5009 cfg.pageAddr = 0;
5010
5011 if ((rc = mpt_config(ioc, &cfg)) != 0)
5012 return rc;
5013
5014 if (hdr.PageLength == 0)
5015 return 0;
5016
5017 data_sz = hdr.PageLength * 4;
5018 rc = -ENOMEM;
5019 ppage1_alloc = (LANPage1_t *) pci_alloc_consistent(ioc->pcidev, data_sz, &page1_dma);
5020 if (ppage1_alloc) {
5021 memset((u8 *)ppage1_alloc, 0, data_sz);
5022 cfg.physAddr = page1_dma;
5023 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
5024
5025 if ((rc = mpt_config(ioc, &cfg)) == 0) {
5026 /* save the data */
5027 copy_sz = min_t(int, sizeof(LANPage1_t), data_sz);
5028 memcpy(&ioc->lan_cnfg_page1, ppage1_alloc, copy_sz);
5029 }
5030
5031 pci_free_consistent(ioc->pcidev, data_sz, (u8 *) ppage1_alloc, page1_dma);
5032
5033 /* FIXME!
5034 * Normalize endianness of structure data,
5035 * by byte-swapping all > 1 byte fields!
5036 */
5037
5038 }
5039
5040 return rc;
5041}
5042
5043/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
5044/**
5045 * mptbase_sas_persist_operation - Perform operation on SAS Persistent Table
5046 * @ioc: Pointer to MPT_ADAPTER structure
5047 * @persist_opcode: see below
5048 *
5049 * MPI_SAS_OP_CLEAR_NOT_PRESENT - Free all persist TargetID mappings for
5050 * devices not currently present.
5051 * MPI_SAS_OP_CLEAR_ALL_PERSISTENT - Clear al persist TargetID mappings
5052 *
5053 * NOTE: Don't use not this function during interrupt time.
5054 *
5055 * Returns 0 for success, non-zero error
5056 */
5057
5058/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
5059int
5060mptbase_sas_persist_operation(MPT_ADAPTER *ioc, u8 persist_opcode)
5061{
5062 SasIoUnitControlRequest_t *sasIoUnitCntrReq;
5063 SasIoUnitControlReply_t *sasIoUnitCntrReply;
5064 MPT_FRAME_HDR *mf = NULL;
5065 MPIHeader_t *mpi_hdr;
5066 int ret = 0;
5067 unsigned long timeleft;
5068
5069 mutex_lock(&ioc->mptbase_cmds.mutex);
5070
5071 /* init the internal cmd struct */
5072 memset(ioc->mptbase_cmds.reply, 0 , MPT_DEFAULT_FRAME_SIZE);
5073 INITIALIZE_MGMT_STATUS(ioc->mptbase_cmds.status)
5074
5075 /* insure garbage is not sent to fw */
5076 switch(persist_opcode) {
5077
5078 case MPI_SAS_OP_CLEAR_NOT_PRESENT:
5079 case MPI_SAS_OP_CLEAR_ALL_PERSISTENT:
5080 break;
5081
5082 default:
5083 ret = -1;
5084 goto out;
5085 }
5086
5087 printk(KERN_DEBUG "%s: persist_opcode=%x\n",
5088 __func__, persist_opcode);
5089
5090 /* Get a MF for this command.
5091 */
5092 if ((mf = mpt_get_msg_frame(mpt_base_index, ioc)) == NULL) {
5093 printk(KERN_DEBUG "%s: no msg frames!\n", __func__);
5094 ret = -1;
5095 goto out;
5096 }
5097
5098 mpi_hdr = (MPIHeader_t *) mf;
5099 sasIoUnitCntrReq = (SasIoUnitControlRequest_t *)mf;
5100 memset(sasIoUnitCntrReq,0,sizeof(SasIoUnitControlRequest_t));
5101 sasIoUnitCntrReq->Function = MPI_FUNCTION_SAS_IO_UNIT_CONTROL;
5102 sasIoUnitCntrReq->MsgContext = mpi_hdr->MsgContext;
5103 sasIoUnitCntrReq->Operation = persist_opcode;
5104
5105 mpt_put_msg_frame(mpt_base_index, ioc, mf);
5106 timeleft = wait_for_completion_timeout(&ioc->mptbase_cmds.done, 10*HZ);
5107 if (!(ioc->mptbase_cmds.status & MPT_MGMT_STATUS_COMMAND_GOOD)) {
5108 ret = -ETIME;
5109 printk(KERN_DEBUG "%s: failed\n", __func__);
5110 if (ioc->mptbase_cmds.status & MPT_MGMT_STATUS_DID_IOCRESET)
5111 goto out;
5112 if (!timeleft) {
5113 printk(MYIOC_s_WARN_FMT
5114 "Issuing Reset from %s!!, doorbell=0x%08x\n",
5115 ioc->name, __func__, mpt_GetIocState(ioc, 0));
5116 mpt_Soft_Hard_ResetHandler(ioc, CAN_SLEEP);
5117 mpt_free_msg_frame(ioc, mf);
5118 }
5119 goto out;
5120 }
5121
5122 if (!(ioc->mptbase_cmds.status & MPT_MGMT_STATUS_RF_VALID)) {
5123 ret = -1;
5124 goto out;
5125 }
5126
5127 sasIoUnitCntrReply =
5128 (SasIoUnitControlReply_t *)ioc->mptbase_cmds.reply;
5129 if (le16_to_cpu(sasIoUnitCntrReply->IOCStatus) != MPI_IOCSTATUS_SUCCESS) {
5130 printk(KERN_DEBUG "%s: IOCStatus=0x%X IOCLogInfo=0x%X\n",
5131 __func__, sasIoUnitCntrReply->IOCStatus,
5132 sasIoUnitCntrReply->IOCLogInfo);
5133 printk(KERN_DEBUG "%s: failed\n", __func__);
5134 ret = -1;
5135 } else
5136 printk(KERN_DEBUG "%s: success\n", __func__);
5137 out:
5138
5139 CLEAR_MGMT_STATUS(ioc->mptbase_cmds.status)
5140 mutex_unlock(&ioc->mptbase_cmds.mutex);
5141 return ret;
5142}
5143
5144/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
5145
5146static void
5147mptbase_raid_process_event_data(MPT_ADAPTER *ioc,
5148 MpiEventDataRaid_t * pRaidEventData)
5149{
5150 int volume;
5151 int reason;
5152 int disk;
5153 int status;
5154 int flags;
5155 int state;
5156
5157 volume = pRaidEventData->VolumeID;
5158 reason = pRaidEventData->ReasonCode;
5159 disk = pRaidEventData->PhysDiskNum;
5160 status = le32_to_cpu(pRaidEventData->SettingsStatus);
5161 flags = (status >> 0) & 0xff;
5162 state = (status >> 8) & 0xff;
5163
5164 if (reason == MPI_EVENT_RAID_RC_DOMAIN_VAL_NEEDED) {
5165 return;
5166 }
5167
5168 if ((reason >= MPI_EVENT_RAID_RC_PHYSDISK_CREATED &&
5169 reason <= MPI_EVENT_RAID_RC_PHYSDISK_STATUS_CHANGED) ||
5170 (reason == MPI_EVENT_RAID_RC_SMART_DATA)) {
5171 printk(MYIOC_s_INFO_FMT "RAID STATUS CHANGE for PhysDisk %d id=%d\n",
5172 ioc->name, disk, volume);
5173 } else {
5174 printk(MYIOC_s_INFO_FMT "RAID STATUS CHANGE for VolumeID %d\n",
5175 ioc->name, volume);
5176 }
5177
5178 switch(reason) {
5179 case MPI_EVENT_RAID_RC_VOLUME_CREATED:
5180 printk(MYIOC_s_INFO_FMT " volume has been created\n",
5181 ioc->name);
5182 break;
5183
5184 case MPI_EVENT_RAID_RC_VOLUME_DELETED:
5185
5186 printk(MYIOC_s_INFO_FMT " volume has been deleted\n",
5187 ioc->name);
5188 break;
5189
5190 case MPI_EVENT_RAID_RC_VOLUME_SETTINGS_CHANGED:
5191 printk(MYIOC_s_INFO_FMT " volume settings have been changed\n",
5192 ioc->name);
5193 break;
5194
5195 case MPI_EVENT_RAID_RC_VOLUME_STATUS_CHANGED:
5196 printk(MYIOC_s_INFO_FMT " volume is now %s%s%s%s\n",
5197 ioc->name,
5198 state == MPI_RAIDVOL0_STATUS_STATE_OPTIMAL
5199 ? "optimal"
5200 : state == MPI_RAIDVOL0_STATUS_STATE_DEGRADED
5201 ? "degraded"
5202 : state == MPI_RAIDVOL0_STATUS_STATE_FAILED
5203 ? "failed"
5204 : "state unknown",
5205 flags & MPI_RAIDVOL0_STATUS_FLAG_ENABLED
5206 ? ", enabled" : "",
5207 flags & MPI_RAIDVOL0_STATUS_FLAG_QUIESCED
5208 ? ", quiesced" : "",
5209 flags & MPI_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS
5210 ? ", resync in progress" : "" );
5211 break;
5212
5213 case MPI_EVENT_RAID_RC_VOLUME_PHYSDISK_CHANGED:
5214 printk(MYIOC_s_INFO_FMT " volume membership of PhysDisk %d has changed\n",
5215 ioc->name, disk);
5216 break;
5217
5218 case MPI_EVENT_RAID_RC_PHYSDISK_CREATED:
5219 printk(MYIOC_s_INFO_FMT " PhysDisk has been created\n",
5220 ioc->name);
5221 break;
5222
5223 case MPI_EVENT_RAID_RC_PHYSDISK_DELETED:
5224 printk(MYIOC_s_INFO_FMT " PhysDisk has been deleted\n",
5225 ioc->name);
5226 break;
5227
5228 case MPI_EVENT_RAID_RC_PHYSDISK_SETTINGS_CHANGED:
5229 printk(MYIOC_s_INFO_FMT " PhysDisk settings have been changed\n",
5230 ioc->name);
5231 break;
5232
5233 case MPI_EVENT_RAID_RC_PHYSDISK_STATUS_CHANGED:
5234 printk(MYIOC_s_INFO_FMT " PhysDisk is now %s%s%s\n",
5235 ioc->name,
5236 state == MPI_PHYSDISK0_STATUS_ONLINE
5237 ? "online"
5238 : state == MPI_PHYSDISK0_STATUS_MISSING
5239 ? "missing"
5240 : state == MPI_PHYSDISK0_STATUS_NOT_COMPATIBLE
5241 ? "not compatible"
5242 : state == MPI_PHYSDISK0_STATUS_FAILED
5243 ? "failed"
5244 : state == MPI_PHYSDISK0_STATUS_INITIALIZING
5245 ? "initializing"
5246 : state == MPI_PHYSDISK0_STATUS_OFFLINE_REQUESTED
5247 ? "offline requested"
5248 : state == MPI_PHYSDISK0_STATUS_FAILED_REQUESTED
5249 ? "failed requested"
5250 : state == MPI_PHYSDISK0_STATUS_OTHER_OFFLINE
5251 ? "offline"
5252 : "state unknown",
5253 flags & MPI_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC
5254 ? ", out of sync" : "",
5255 flags & MPI_PHYSDISK0_STATUS_FLAG_QUIESCED
5256 ? ", quiesced" : "" );
5257 break;
5258
5259 case MPI_EVENT_RAID_RC_DOMAIN_VAL_NEEDED:
5260 printk(MYIOC_s_INFO_FMT " Domain Validation needed for PhysDisk %d\n",
5261 ioc->name, disk);
5262 break;
5263
5264 case MPI_EVENT_RAID_RC_SMART_DATA:
5265 printk(MYIOC_s_INFO_FMT " SMART data received, ASC/ASCQ = %02xh/%02xh\n",
5266 ioc->name, pRaidEventData->ASC, pRaidEventData->ASCQ);
5267 break;
5268
5269 case MPI_EVENT_RAID_RC_REPLACE_ACTION_STARTED:
5270 printk(MYIOC_s_INFO_FMT " replacement of PhysDisk %d has started\n",
5271 ioc->name, disk);
5272 break;
5273 }
5274}
5275
5276/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
5277/**
5278 * GetIoUnitPage2 - Retrieve BIOS version and boot order information.
5279 * @ioc: Pointer to MPT_ADAPTER structure
5280 *
5281 * Returns: 0 for success
5282 * -ENOMEM if no memory available
5283 * -EPERM if not allowed due to ISR context
5284 * -EAGAIN if no msg frames currently available
5285 * -EFAULT for non-successful reply or no reply (timeout)
5286 */
5287static int
5288GetIoUnitPage2(MPT_ADAPTER *ioc)
5289{
5290 ConfigPageHeader_t hdr;
5291 CONFIGPARMS cfg;
5292 IOUnitPage2_t *ppage_alloc;
5293 dma_addr_t page_dma;
5294 int data_sz;
5295 int rc;
5296
5297 /* Get the page header */
5298 hdr.PageVersion = 0;
5299 hdr.PageLength = 0;
5300 hdr.PageNumber = 2;
5301 hdr.PageType = MPI_CONFIG_PAGETYPE_IO_UNIT;
5302 cfg.cfghdr.hdr = &hdr;
5303 cfg.physAddr = -1;
5304 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
5305 cfg.dir = 0;
5306 cfg.pageAddr = 0;
5307 cfg.timeout = 0;
5308
5309 if ((rc = mpt_config(ioc, &cfg)) != 0)
5310 return rc;
5311
5312 if (hdr.PageLength == 0)
5313 return 0;
5314
5315 /* Read the config page */
5316 data_sz = hdr.PageLength * 4;
5317 rc = -ENOMEM;
5318 ppage_alloc = (IOUnitPage2_t *) pci_alloc_consistent(ioc->pcidev, data_sz, &page_dma);
5319 if (ppage_alloc) {
5320 memset((u8 *)ppage_alloc, 0, data_sz);
5321 cfg.physAddr = page_dma;
5322 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
5323
5324 /* If Good, save data */
5325 if ((rc = mpt_config(ioc, &cfg)) == 0)
5326 ioc->biosVersion = le32_to_cpu(ppage_alloc->BiosVersion);
5327
5328 pci_free_consistent(ioc->pcidev, data_sz, (u8 *) ppage_alloc, page_dma);
5329 }
5330
5331 return rc;
5332}
5333
5334/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
5335/**
5336 * mpt_GetScsiPortSettings - read SCSI Port Page 0 and 2
5337 * @ioc: Pointer to a Adapter Strucutre
5338 * @portnum: IOC port number
5339 *
5340 * Return: -EFAULT if read of config page header fails
5341 * or if no nvram
5342 * If read of SCSI Port Page 0 fails,
5343 * NVRAM = MPT_HOST_NVRAM_INVALID (0xFFFFFFFF)
5344 * Adapter settings: async, narrow
5345 * Return 1
5346 * If read of SCSI Port Page 2 fails,
5347 * Adapter settings valid
5348 * NVRAM = MPT_HOST_NVRAM_INVALID (0xFFFFFFFF)
5349 * Return 1
5350 * Else
5351 * Both valid
5352 * Return 0
5353 * CHECK - what type of locking mechanisms should be used????
5354 */
5355static int
5356mpt_GetScsiPortSettings(MPT_ADAPTER *ioc, int portnum)
5357{
5358 u8 *pbuf;
5359 dma_addr_t buf_dma;
5360 CONFIGPARMS cfg;
5361 ConfigPageHeader_t header;
5362 int ii;
5363 int data, rc = 0;
5364
5365 /* Allocate memory
5366 */
5367 if (!ioc->spi_data.nvram) {
5368 int sz;
5369 u8 *mem;
5370 sz = MPT_MAX_SCSI_DEVICES * sizeof(int);
5371 mem = kmalloc(sz, GFP_ATOMIC);
5372 if (mem == NULL)
5373 return -EFAULT;
5374
5375 ioc->spi_data.nvram = (int *) mem;
5376
5377 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "SCSI device NVRAM settings @ %p, sz=%d\n",
5378 ioc->name, ioc->spi_data.nvram, sz));
5379 }
5380
5381 /* Invalidate NVRAM information
5382 */
5383 for (ii=0; ii < MPT_MAX_SCSI_DEVICES; ii++) {
5384 ioc->spi_data.nvram[ii] = MPT_HOST_NVRAM_INVALID;
5385 }
5386
5387 /* Read SPP0 header, allocate memory, then read page.
5388 */
5389 header.PageVersion = 0;
5390 header.PageLength = 0;
5391 header.PageNumber = 0;
5392 header.PageType = MPI_CONFIG_PAGETYPE_SCSI_PORT;
5393 cfg.cfghdr.hdr = &header;
5394 cfg.physAddr = -1;
5395 cfg.pageAddr = portnum;
5396 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
5397 cfg.dir = 0;
5398 cfg.timeout = 0; /* use default */
5399 if (mpt_config(ioc, &cfg) != 0)
5400 return -EFAULT;
5401
5402 if (header.PageLength > 0) {
5403 pbuf = pci_alloc_consistent(ioc->pcidev, header.PageLength * 4, &buf_dma);
5404 if (pbuf) {
5405 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
5406 cfg.physAddr = buf_dma;
5407 if (mpt_config(ioc, &cfg) != 0) {
5408 ioc->spi_data.maxBusWidth = MPT_NARROW;
5409 ioc->spi_data.maxSyncOffset = 0;
5410 ioc->spi_data.minSyncFactor = MPT_ASYNC;
5411 ioc->spi_data.busType = MPT_HOST_BUS_UNKNOWN;
5412 rc = 1;
5413 ddvprintk(ioc, printk(MYIOC_s_DEBUG_FMT
5414 "Unable to read PortPage0 minSyncFactor=%x\n",
5415 ioc->name, ioc->spi_data.minSyncFactor));
5416 } else {
5417 /* Save the Port Page 0 data
5418 */
5419 SCSIPortPage0_t *pPP0 = (SCSIPortPage0_t *) pbuf;
5420 pPP0->Capabilities = le32_to_cpu(pPP0->Capabilities);
5421 pPP0->PhysicalInterface = le32_to_cpu(pPP0->PhysicalInterface);
5422
5423 if ( (pPP0->Capabilities & MPI_SCSIPORTPAGE0_CAP_QAS) == 0 ) {
5424 ioc->spi_data.noQas |= MPT_TARGET_NO_NEGO_QAS;
5425 ddvprintk(ioc, printk(MYIOC_s_DEBUG_FMT
5426 "noQas due to Capabilities=%x\n",
5427 ioc->name, pPP0->Capabilities));
5428 }
5429 ioc->spi_data.maxBusWidth = pPP0->Capabilities & MPI_SCSIPORTPAGE0_CAP_WIDE ? 1 : 0;
5430 data = pPP0->Capabilities & MPI_SCSIPORTPAGE0_CAP_MAX_SYNC_OFFSET_MASK;
5431 if (data) {
5432 ioc->spi_data.maxSyncOffset = (u8) (data >> 16);
5433 data = pPP0->Capabilities & MPI_SCSIPORTPAGE0_CAP_MIN_SYNC_PERIOD_MASK;
5434 ioc->spi_data.minSyncFactor = (u8) (data >> 8);
5435 ddvprintk(ioc, printk(MYIOC_s_DEBUG_FMT
5436 "PortPage0 minSyncFactor=%x\n",
5437 ioc->name, ioc->spi_data.minSyncFactor));
5438 } else {
5439 ioc->spi_data.maxSyncOffset = 0;
5440 ioc->spi_data.minSyncFactor = MPT_ASYNC;
5441 }
5442
5443 ioc->spi_data.busType = pPP0->PhysicalInterface & MPI_SCSIPORTPAGE0_PHY_SIGNAL_TYPE_MASK;
5444
5445 /* Update the minSyncFactor based on bus type.
5446 */
5447 if ((ioc->spi_data.busType == MPI_SCSIPORTPAGE0_PHY_SIGNAL_HVD) ||
5448 (ioc->spi_data.busType == MPI_SCSIPORTPAGE0_PHY_SIGNAL_SE)) {
5449
5450 if (ioc->spi_data.minSyncFactor < MPT_ULTRA) {
5451 ioc->spi_data.minSyncFactor = MPT_ULTRA;
5452 ddvprintk(ioc, printk(MYIOC_s_DEBUG_FMT
5453 "HVD or SE detected, minSyncFactor=%x\n",
5454 ioc->name, ioc->spi_data.minSyncFactor));
5455 }
5456 }
5457 }
5458 if (pbuf) {
5459 pci_free_consistent(ioc->pcidev, header.PageLength * 4, pbuf, buf_dma);
5460 }
5461 }
5462 }
5463
5464 /* SCSI Port Page 2 - Read the header then the page.
5465 */
5466 header.PageVersion = 0;
5467 header.PageLength = 0;
5468 header.PageNumber = 2;
5469 header.PageType = MPI_CONFIG_PAGETYPE_SCSI_PORT;
5470 cfg.cfghdr.hdr = &header;
5471 cfg.physAddr = -1;
5472 cfg.pageAddr = portnum;
5473 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
5474 cfg.dir = 0;
5475 if (mpt_config(ioc, &cfg) != 0)
5476 return -EFAULT;
5477
5478 if (header.PageLength > 0) {
5479 /* Allocate memory and read SCSI Port Page 2
5480 */
5481 pbuf = pci_alloc_consistent(ioc->pcidev, header.PageLength * 4, &buf_dma);
5482 if (pbuf) {
5483 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_NVRAM;
5484 cfg.physAddr = buf_dma;
5485 if (mpt_config(ioc, &cfg) != 0) {
5486 /* Nvram data is left with INVALID mark
5487 */
5488 rc = 1;
5489 } else if (ioc->pcidev->vendor == PCI_VENDOR_ID_ATTO) {
5490
5491 /* This is an ATTO adapter, read Page2 accordingly
5492 */
5493 ATTO_SCSIPortPage2_t *pPP2 = (ATTO_SCSIPortPage2_t *) pbuf;
5494 ATTODeviceInfo_t *pdevice = NULL;
5495 u16 ATTOFlags;
5496
5497 /* Save the Port Page 2 data
5498 * (reformat into a 32bit quantity)
5499 */
5500 for (ii=0; ii < MPT_MAX_SCSI_DEVICES; ii++) {
5501 pdevice = &pPP2->DeviceSettings[ii];
5502 ATTOFlags = le16_to_cpu(pdevice->ATTOFlags);
5503 data = 0;
5504
5505 /* Translate ATTO device flags to LSI format
5506 */
5507 if (ATTOFlags & ATTOFLAG_DISC)
5508 data |= (MPI_SCSIPORTPAGE2_DEVICE_DISCONNECT_ENABLE);
5509 if (ATTOFlags & ATTOFLAG_ID_ENB)
5510 data |= (MPI_SCSIPORTPAGE2_DEVICE_ID_SCAN_ENABLE);
5511 if (ATTOFlags & ATTOFLAG_LUN_ENB)
5512 data |= (MPI_SCSIPORTPAGE2_DEVICE_LUN_SCAN_ENABLE);
5513 if (ATTOFlags & ATTOFLAG_TAGGED)
5514 data |= (MPI_SCSIPORTPAGE2_DEVICE_TAG_QUEUE_ENABLE);
5515 if (!(ATTOFlags & ATTOFLAG_WIDE_ENB))
5516 data |= (MPI_SCSIPORTPAGE2_DEVICE_WIDE_DISABLE);
5517
5518 data = (data << 16) | (pdevice->Period << 8) | 10;
5519 ioc->spi_data.nvram[ii] = data;
5520 }
5521 } else {
5522 SCSIPortPage2_t *pPP2 = (SCSIPortPage2_t *) pbuf;
5523 MpiDeviceInfo_t *pdevice = NULL;
5524
5525 /*
5526 * Save "Set to Avoid SCSI Bus Resets" flag
5527 */
5528 ioc->spi_data.bus_reset =
5529 (le32_to_cpu(pPP2->PortFlags) &
5530 MPI_SCSIPORTPAGE2_PORT_FLAGS_AVOID_SCSI_RESET) ?
5531 0 : 1 ;
5532
5533 /* Save the Port Page 2 data
5534 * (reformat into a 32bit quantity)
5535 */
5536 data = le32_to_cpu(pPP2->PortFlags) & MPI_SCSIPORTPAGE2_PORT_FLAGS_DV_MASK;
5537 ioc->spi_data.PortFlags = data;
5538 for (ii=0; ii < MPT_MAX_SCSI_DEVICES; ii++) {
5539 pdevice = &pPP2->DeviceSettings[ii];
5540 data = (le16_to_cpu(pdevice->DeviceFlags) << 16) |
5541 (pdevice->SyncFactor << 8) | pdevice->Timeout;
5542 ioc->spi_data.nvram[ii] = data;
5543 }
5544 }
5545
5546 pci_free_consistent(ioc->pcidev, header.PageLength * 4, pbuf, buf_dma);
5547 }
5548 }
5549
5550 /* Update Adapter limits with those from NVRAM
5551 * Comment: Don't need to do this. Target performance
5552 * parameters will never exceed the adapters limits.
5553 */
5554
5555 return rc;
5556}
5557
5558/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
5559/**
5560 * mpt_readScsiDevicePageHeaders - save version and length of SDP1
5561 * @ioc: Pointer to a Adapter Strucutre
5562 * @portnum: IOC port number
5563 *
5564 * Return: -EFAULT if read of config page header fails
5565 * or 0 if success.
5566 */
5567static int
5568mpt_readScsiDevicePageHeaders(MPT_ADAPTER *ioc, int portnum)
5569{
5570 CONFIGPARMS cfg;
5571 ConfigPageHeader_t header;
5572
5573 /* Read the SCSI Device Page 1 header
5574 */
5575 header.PageVersion = 0;
5576 header.PageLength = 0;
5577 header.PageNumber = 1;
5578 header.PageType = MPI_CONFIG_PAGETYPE_SCSI_DEVICE;
5579 cfg.cfghdr.hdr = &header;
5580 cfg.physAddr = -1;
5581 cfg.pageAddr = portnum;
5582 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
5583 cfg.dir = 0;
5584 cfg.timeout = 0;
5585 if (mpt_config(ioc, &cfg) != 0)
5586 return -EFAULT;
5587
5588 ioc->spi_data.sdp1version = cfg.cfghdr.hdr->PageVersion;
5589 ioc->spi_data.sdp1length = cfg.cfghdr.hdr->PageLength;
5590
5591 header.PageVersion = 0;
5592 header.PageLength = 0;
5593 header.PageNumber = 0;
5594 header.PageType = MPI_CONFIG_PAGETYPE_SCSI_DEVICE;
5595 if (mpt_config(ioc, &cfg) != 0)
5596 return -EFAULT;
5597
5598 ioc->spi_data.sdp0version = cfg.cfghdr.hdr->PageVersion;
5599 ioc->spi_data.sdp0length = cfg.cfghdr.hdr->PageLength;
5600
5601 dcprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Headers: 0: version %d length %d\n",
5602 ioc->name, ioc->spi_data.sdp0version, ioc->spi_data.sdp0length));
5603
5604 dcprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Headers: 1: version %d length %d\n",
5605 ioc->name, ioc->spi_data.sdp1version, ioc->spi_data.sdp1length));
5606 return 0;
5607}
5608
5609/**
5610 * mpt_inactive_raid_list_free - This clears this link list.
5611 * @ioc : pointer to per adapter structure
5612 **/
5613static void
5614mpt_inactive_raid_list_free(MPT_ADAPTER *ioc)
5615{
5616 struct inactive_raid_component_info *component_info, *pNext;
5617
5618 if (list_empty(&ioc->raid_data.inactive_list))
5619 return;
5620
5621 mutex_lock(&ioc->raid_data.inactive_list_mutex);
5622 list_for_each_entry_safe(component_info, pNext,
5623 &ioc->raid_data.inactive_list, list) {
5624 list_del(&component_info->list);
5625 kfree(component_info);
5626 }
5627 mutex_unlock(&ioc->raid_data.inactive_list_mutex);
5628}
5629
5630/**
5631 * mpt_inactive_raid_volumes - sets up link list of phy_disk_nums for devices belonging in an inactive volume
5632 *
5633 * @ioc : pointer to per adapter structure
5634 * @channel : volume channel
5635 * @id : volume target id
5636 **/
5637static void
5638mpt_inactive_raid_volumes(MPT_ADAPTER *ioc, u8 channel, u8 id)
5639{
5640 CONFIGPARMS cfg;
5641 ConfigPageHeader_t hdr;
5642 dma_addr_t dma_handle;
5643 pRaidVolumePage0_t buffer = NULL;
5644 int i;
5645 RaidPhysDiskPage0_t phys_disk;
5646 struct inactive_raid_component_info *component_info;
5647 int handle_inactive_volumes;
5648
5649 memset(&cfg, 0 , sizeof(CONFIGPARMS));
5650 memset(&hdr, 0 , sizeof(ConfigPageHeader_t));
5651 hdr.PageType = MPI_CONFIG_PAGETYPE_RAID_VOLUME;
5652 cfg.pageAddr = (channel << 8) + id;
5653 cfg.cfghdr.hdr = &hdr;
5654 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
5655
5656 if (mpt_config(ioc, &cfg) != 0)
5657 goto out;
5658
5659 if (!hdr.PageLength)
5660 goto out;
5661
5662 buffer = pci_alloc_consistent(ioc->pcidev, hdr.PageLength * 4,
5663 &dma_handle);
5664
5665 if (!buffer)
5666 goto out;
5667
5668 cfg.physAddr = dma_handle;
5669 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
5670
5671 if (mpt_config(ioc, &cfg) != 0)
5672 goto out;
5673
5674 if (!buffer->NumPhysDisks)
5675 goto out;
5676
5677 handle_inactive_volumes =
5678 (buffer->VolumeStatus.Flags & MPI_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE ||
5679 (buffer->VolumeStatus.Flags & MPI_RAIDVOL0_STATUS_FLAG_ENABLED) == 0 ||
5680 buffer->VolumeStatus.State == MPI_RAIDVOL0_STATUS_STATE_FAILED ||
5681 buffer->VolumeStatus.State == MPI_RAIDVOL0_STATUS_STATE_MISSING) ? 1 : 0;
5682
5683 if (!handle_inactive_volumes)
5684 goto out;
5685
5686 mutex_lock(&ioc->raid_data.inactive_list_mutex);
5687 for (i = 0; i < buffer->NumPhysDisks; i++) {
5688 if(mpt_raid_phys_disk_pg0(ioc,
5689 buffer->PhysDisk[i].PhysDiskNum, &phys_disk) != 0)
5690 continue;
5691
5692 if ((component_info = kmalloc(sizeof (*component_info),
5693 GFP_KERNEL)) == NULL)
5694 continue;
5695
5696 component_info->volumeID = id;
5697 component_info->volumeBus = channel;
5698 component_info->d.PhysDiskNum = phys_disk.PhysDiskNum;
5699 component_info->d.PhysDiskBus = phys_disk.PhysDiskBus;
5700 component_info->d.PhysDiskID = phys_disk.PhysDiskID;
5701 component_info->d.PhysDiskIOC = phys_disk.PhysDiskIOC;
5702
5703 list_add_tail(&component_info->list,
5704 &ioc->raid_data.inactive_list);
5705 }
5706 mutex_unlock(&ioc->raid_data.inactive_list_mutex);
5707
5708 out:
5709 if (buffer)
5710 pci_free_consistent(ioc->pcidev, hdr.PageLength * 4, buffer,
5711 dma_handle);
5712}
5713
5714/**
5715 * mpt_raid_phys_disk_pg0 - returns phys disk page zero
5716 * @ioc: Pointer to a Adapter Structure
5717 * @phys_disk_num: io unit unique phys disk num generated by the ioc
5718 * @phys_disk: requested payload data returned
5719 *
5720 * Return:
5721 * 0 on success
5722 * -EFAULT if read of config page header fails or data pointer not NULL
5723 * -ENOMEM if pci_alloc failed
5724 **/
5725int
5726mpt_raid_phys_disk_pg0(MPT_ADAPTER *ioc, u8 phys_disk_num,
5727 RaidPhysDiskPage0_t *phys_disk)
5728{
5729 CONFIGPARMS cfg;
5730 ConfigPageHeader_t hdr;
5731 dma_addr_t dma_handle;
5732 pRaidPhysDiskPage0_t buffer = NULL;
5733 int rc;
5734
5735 memset(&cfg, 0 , sizeof(CONFIGPARMS));
5736 memset(&hdr, 0 , sizeof(ConfigPageHeader_t));
5737 memset(phys_disk, 0, sizeof(RaidPhysDiskPage0_t));
5738
5739 hdr.PageVersion = MPI_RAIDPHYSDISKPAGE0_PAGEVERSION;
5740 hdr.PageType = MPI_CONFIG_PAGETYPE_RAID_PHYSDISK;
5741 cfg.cfghdr.hdr = &hdr;
5742 cfg.physAddr = -1;
5743 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
5744
5745 if (mpt_config(ioc, &cfg) != 0) {
5746 rc = -EFAULT;
5747 goto out;
5748 }
5749
5750 if (!hdr.PageLength) {
5751 rc = -EFAULT;
5752 goto out;
5753 }
5754
5755 buffer = pci_alloc_consistent(ioc->pcidev, hdr.PageLength * 4,
5756 &dma_handle);
5757
5758 if (!buffer) {
5759 rc = -ENOMEM;
5760 goto out;
5761 }
5762
5763 cfg.physAddr = dma_handle;
5764 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
5765 cfg.pageAddr = phys_disk_num;
5766
5767 if (mpt_config(ioc, &cfg) != 0) {
5768 rc = -EFAULT;
5769 goto out;
5770 }
5771
5772 rc = 0;
5773 memcpy(phys_disk, buffer, sizeof(*buffer));
5774 phys_disk->MaxLBA = le32_to_cpu(buffer->MaxLBA);
5775
5776 out:
5777
5778 if (buffer)
5779 pci_free_consistent(ioc->pcidev, hdr.PageLength * 4, buffer,
5780 dma_handle);
5781
5782 return rc;
5783}
5784
5785/**
5786 * mpt_raid_phys_disk_get_num_paths - returns number paths associated to this phys_num
5787 * @ioc: Pointer to a Adapter Structure
5788 * @phys_disk_num: io unit unique phys disk num generated by the ioc
5789 *
5790 * Return:
5791 * returns number paths
5792 **/
5793int
5794mpt_raid_phys_disk_get_num_paths(MPT_ADAPTER *ioc, u8 phys_disk_num)
5795{
5796 CONFIGPARMS cfg;
5797 ConfigPageHeader_t hdr;
5798 dma_addr_t dma_handle;
5799 pRaidPhysDiskPage1_t buffer = NULL;
5800 int rc;
5801
5802 memset(&cfg, 0 , sizeof(CONFIGPARMS));
5803 memset(&hdr, 0 , sizeof(ConfigPageHeader_t));
5804
5805 hdr.PageVersion = MPI_RAIDPHYSDISKPAGE1_PAGEVERSION;
5806 hdr.PageType = MPI_CONFIG_PAGETYPE_RAID_PHYSDISK;
5807 hdr.PageNumber = 1;
5808 cfg.cfghdr.hdr = &hdr;
5809 cfg.physAddr = -1;
5810 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
5811
5812 if (mpt_config(ioc, &cfg) != 0) {
5813 rc = 0;
5814 goto out;
5815 }
5816
5817 if (!hdr.PageLength) {
5818 rc = 0;
5819 goto out;
5820 }
5821
5822 buffer = pci_alloc_consistent(ioc->pcidev, hdr.PageLength * 4,
5823 &dma_handle);
5824
5825 if (!buffer) {
5826 rc = 0;
5827 goto out;
5828 }
5829
5830 cfg.physAddr = dma_handle;
5831 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
5832 cfg.pageAddr = phys_disk_num;
5833
5834 if (mpt_config(ioc, &cfg) != 0) {
5835 rc = 0;
5836 goto out;
5837 }
5838
5839 rc = buffer->NumPhysDiskPaths;
5840 out:
5841
5842 if (buffer)
5843 pci_free_consistent(ioc->pcidev, hdr.PageLength * 4, buffer,
5844 dma_handle);
5845
5846 return rc;
5847}
5848EXPORT_SYMBOL(mpt_raid_phys_disk_get_num_paths);
5849
5850/**
5851 * mpt_raid_phys_disk_pg1 - returns phys disk page 1
5852 * @ioc: Pointer to a Adapter Structure
5853 * @phys_disk_num: io unit unique phys disk num generated by the ioc
5854 * @phys_disk: requested payload data returned
5855 *
5856 * Return:
5857 * 0 on success
5858 * -EFAULT if read of config page header fails or data pointer not NULL
5859 * -ENOMEM if pci_alloc failed
5860 **/
5861int
5862mpt_raid_phys_disk_pg1(MPT_ADAPTER *ioc, u8 phys_disk_num,
5863 RaidPhysDiskPage1_t *phys_disk)
5864{
5865 CONFIGPARMS cfg;
5866 ConfigPageHeader_t hdr;
5867 dma_addr_t dma_handle;
5868 pRaidPhysDiskPage1_t buffer = NULL;
5869 int rc;
5870 int i;
5871 __le64 sas_address;
5872
5873 memset(&cfg, 0 , sizeof(CONFIGPARMS));
5874 memset(&hdr, 0 , sizeof(ConfigPageHeader_t));
5875 rc = 0;
5876
5877 hdr.PageVersion = MPI_RAIDPHYSDISKPAGE1_PAGEVERSION;
5878 hdr.PageType = MPI_CONFIG_PAGETYPE_RAID_PHYSDISK;
5879 hdr.PageNumber = 1;
5880 cfg.cfghdr.hdr = &hdr;
5881 cfg.physAddr = -1;
5882 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
5883
5884 if (mpt_config(ioc, &cfg) != 0) {
5885 rc = -EFAULT;
5886 goto out;
5887 }
5888
5889 if (!hdr.PageLength) {
5890 rc = -EFAULT;
5891 goto out;
5892 }
5893
5894 buffer = pci_alloc_consistent(ioc->pcidev, hdr.PageLength * 4,
5895 &dma_handle);
5896
5897 if (!buffer) {
5898 rc = -ENOMEM;
5899 goto out;
5900 }
5901
5902 cfg.physAddr = dma_handle;
5903 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
5904 cfg.pageAddr = phys_disk_num;
5905
5906 if (mpt_config(ioc, &cfg) != 0) {
5907 rc = -EFAULT;
5908 goto out;
5909 }
5910
5911 phys_disk->NumPhysDiskPaths = buffer->NumPhysDiskPaths;
5912 phys_disk->PhysDiskNum = phys_disk_num;
5913 for (i = 0; i < phys_disk->NumPhysDiskPaths; i++) {
5914 phys_disk->Path[i].PhysDiskID = buffer->Path[i].PhysDiskID;
5915 phys_disk->Path[i].PhysDiskBus = buffer->Path[i].PhysDiskBus;
5916 phys_disk->Path[i].OwnerIdentifier =
5917 buffer->Path[i].OwnerIdentifier;
5918 phys_disk->Path[i].Flags = le16_to_cpu(buffer->Path[i].Flags);
5919 memcpy(&sas_address, &buffer->Path[i].WWID, sizeof(__le64));
5920 sas_address = le64_to_cpu(sas_address);
5921 memcpy(&phys_disk->Path[i].WWID, &sas_address, sizeof(__le64));
5922 memcpy(&sas_address,
5923 &buffer->Path[i].OwnerWWID, sizeof(__le64));
5924 sas_address = le64_to_cpu(sas_address);
5925 memcpy(&phys_disk->Path[i].OwnerWWID,
5926 &sas_address, sizeof(__le64));
5927 }
5928
5929 out:
5930
5931 if (buffer)
5932 pci_free_consistent(ioc->pcidev, hdr.PageLength * 4, buffer,
5933 dma_handle);
5934
5935 return rc;
5936}
5937EXPORT_SYMBOL(mpt_raid_phys_disk_pg1);
5938
5939
5940/**
5941 * mpt_findImVolumes - Identify IDs of hidden disks and RAID Volumes
5942 * @ioc: Pointer to a Adapter Strucutre
5943 *
5944 * Return:
5945 * 0 on success
5946 * -EFAULT if read of config page header fails or data pointer not NULL
5947 * -ENOMEM if pci_alloc failed
5948 **/
5949int
5950mpt_findImVolumes(MPT_ADAPTER *ioc)
5951{
5952 IOCPage2_t *pIoc2;
5953 u8 *mem;
5954 dma_addr_t ioc2_dma;
5955 CONFIGPARMS cfg;
5956 ConfigPageHeader_t header;
5957 int rc = 0;
5958 int iocpage2sz;
5959 int i;
5960
5961 if (!ioc->ir_firmware)
5962 return 0;
5963
5964 /* Free the old page
5965 */
5966 kfree(ioc->raid_data.pIocPg2);
5967 ioc->raid_data.pIocPg2 = NULL;
5968 mpt_inactive_raid_list_free(ioc);
5969
5970 /* Read IOCP2 header then the page.
5971 */
5972 header.PageVersion = 0;
5973 header.PageLength = 0;
5974 header.PageNumber = 2;
5975 header.PageType = MPI_CONFIG_PAGETYPE_IOC;
5976 cfg.cfghdr.hdr = &header;
5977 cfg.physAddr = -1;
5978 cfg.pageAddr = 0;
5979 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
5980 cfg.dir = 0;
5981 cfg.timeout = 0;
5982 if (mpt_config(ioc, &cfg) != 0)
5983 return -EFAULT;
5984
5985 if (header.PageLength == 0)
5986 return -EFAULT;
5987
5988 iocpage2sz = header.PageLength * 4;
5989 pIoc2 = pci_alloc_consistent(ioc->pcidev, iocpage2sz, &ioc2_dma);
5990 if (!pIoc2)
5991 return -ENOMEM;
5992
5993 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
5994 cfg.physAddr = ioc2_dma;
5995 if (mpt_config(ioc, &cfg) != 0)
5996 goto out;
5997
5998 mem = kmalloc(iocpage2sz, GFP_KERNEL);
5999 if (!mem) {
6000 rc = -ENOMEM;
6001 goto out;
6002 }
6003
6004 memcpy(mem, (u8 *)pIoc2, iocpage2sz);
6005 ioc->raid_data.pIocPg2 = (IOCPage2_t *) mem;
6006
6007 mpt_read_ioc_pg_3(ioc);
6008
6009 for (i = 0; i < pIoc2->NumActiveVolumes ; i++)
6010 mpt_inactive_raid_volumes(ioc,
6011 pIoc2->RaidVolume[i].VolumeBus,
6012 pIoc2->RaidVolume[i].VolumeID);
6013
6014 out:
6015 pci_free_consistent(ioc->pcidev, iocpage2sz, pIoc2, ioc2_dma);
6016
6017 return rc;
6018}
6019
6020static int
6021mpt_read_ioc_pg_3(MPT_ADAPTER *ioc)
6022{
6023 IOCPage3_t *pIoc3;
6024 u8 *mem;
6025 CONFIGPARMS cfg;
6026 ConfigPageHeader_t header;
6027 dma_addr_t ioc3_dma;
6028 int iocpage3sz = 0;
6029
6030 /* Free the old page
6031 */
6032 kfree(ioc->raid_data.pIocPg3);
6033 ioc->raid_data.pIocPg3 = NULL;
6034
6035 /* There is at least one physical disk.
6036 * Read and save IOC Page 3
6037 */
6038 header.PageVersion = 0;
6039 header.PageLength = 0;
6040 header.PageNumber = 3;
6041 header.PageType = MPI_CONFIG_PAGETYPE_IOC;
6042 cfg.cfghdr.hdr = &header;
6043 cfg.physAddr = -1;
6044 cfg.pageAddr = 0;
6045 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
6046 cfg.dir = 0;
6047 cfg.timeout = 0;
6048 if (mpt_config(ioc, &cfg) != 0)
6049 return 0;
6050
6051 if (header.PageLength == 0)
6052 return 0;
6053
6054 /* Read Header good, alloc memory
6055 */
6056 iocpage3sz = header.PageLength * 4;
6057 pIoc3 = pci_alloc_consistent(ioc->pcidev, iocpage3sz, &ioc3_dma);
6058 if (!pIoc3)
6059 return 0;
6060
6061 /* Read the Page and save the data
6062 * into malloc'd memory.
6063 */
6064 cfg.physAddr = ioc3_dma;
6065 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
6066 if (mpt_config(ioc, &cfg) == 0) {
6067 mem = kmalloc(iocpage3sz, GFP_KERNEL);
6068 if (mem) {
6069 memcpy(mem, (u8 *)pIoc3, iocpage3sz);
6070 ioc->raid_data.pIocPg3 = (IOCPage3_t *) mem;
6071 }
6072 }
6073
6074 pci_free_consistent(ioc->pcidev, iocpage3sz, pIoc3, ioc3_dma);
6075
6076 return 0;
6077}
6078
6079static void
6080mpt_read_ioc_pg_4(MPT_ADAPTER *ioc)
6081{
6082 IOCPage4_t *pIoc4;
6083 CONFIGPARMS cfg;
6084 ConfigPageHeader_t header;
6085 dma_addr_t ioc4_dma;
6086 int iocpage4sz;
6087
6088 /* Read and save IOC Page 4
6089 */
6090 header.PageVersion = 0;
6091 header.PageLength = 0;
6092 header.PageNumber = 4;
6093 header.PageType = MPI_CONFIG_PAGETYPE_IOC;
6094 cfg.cfghdr.hdr = &header;
6095 cfg.physAddr = -1;
6096 cfg.pageAddr = 0;
6097 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
6098 cfg.dir = 0;
6099 cfg.timeout = 0;
6100 if (mpt_config(ioc, &cfg) != 0)
6101 return;
6102
6103 if (header.PageLength == 0)
6104 return;
6105
6106 if ( (pIoc4 = ioc->spi_data.pIocPg4) == NULL ) {
6107 iocpage4sz = (header.PageLength + 4) * 4; /* Allow 4 additional SEP's */
6108 pIoc4 = pci_alloc_consistent(ioc->pcidev, iocpage4sz, &ioc4_dma);
6109 if (!pIoc4)
6110 return;
6111 ioc->alloc_total += iocpage4sz;
6112 } else {
6113 ioc4_dma = ioc->spi_data.IocPg4_dma;
6114 iocpage4sz = ioc->spi_data.IocPg4Sz;
6115 }
6116
6117 /* Read the Page into dma memory.
6118 */
6119 cfg.physAddr = ioc4_dma;
6120 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
6121 if (mpt_config(ioc, &cfg) == 0) {
6122 ioc->spi_data.pIocPg4 = (IOCPage4_t *) pIoc4;
6123 ioc->spi_data.IocPg4_dma = ioc4_dma;
6124 ioc->spi_data.IocPg4Sz = iocpage4sz;
6125 } else {
6126 pci_free_consistent(ioc->pcidev, iocpage4sz, pIoc4, ioc4_dma);
6127 ioc->spi_data.pIocPg4 = NULL;
6128 ioc->alloc_total -= iocpage4sz;
6129 }
6130}
6131
6132static void
6133mpt_read_ioc_pg_1(MPT_ADAPTER *ioc)
6134{
6135 IOCPage1_t *pIoc1;
6136 CONFIGPARMS cfg;
6137 ConfigPageHeader_t header;
6138 dma_addr_t ioc1_dma;
6139 int iocpage1sz = 0;
6140 u32 tmp;
6141
6142 /* Check the Coalescing Timeout in IOC Page 1
6143 */
6144 header.PageVersion = 0;
6145 header.PageLength = 0;
6146 header.PageNumber = 1;
6147 header.PageType = MPI_CONFIG_PAGETYPE_IOC;
6148 cfg.cfghdr.hdr = &header;
6149 cfg.physAddr = -1;
6150 cfg.pageAddr = 0;
6151 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
6152 cfg.dir = 0;
6153 cfg.timeout = 0;
6154 if (mpt_config(ioc, &cfg) != 0)
6155 return;
6156
6157 if (header.PageLength == 0)
6158 return;
6159
6160 /* Read Header good, alloc memory
6161 */
6162 iocpage1sz = header.PageLength * 4;
6163 pIoc1 = pci_alloc_consistent(ioc->pcidev, iocpage1sz, &ioc1_dma);
6164 if (!pIoc1)
6165 return;
6166
6167 /* Read the Page and check coalescing timeout
6168 */
6169 cfg.physAddr = ioc1_dma;
6170 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
6171 if (mpt_config(ioc, &cfg) == 0) {
6172
6173 tmp = le32_to_cpu(pIoc1->Flags) & MPI_IOCPAGE1_REPLY_COALESCING;
6174 if (tmp == MPI_IOCPAGE1_REPLY_COALESCING) {
6175 tmp = le32_to_cpu(pIoc1->CoalescingTimeout);
6176
6177 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Coalescing Enabled Timeout = %d\n",
6178 ioc->name, tmp));
6179
6180 if (tmp > MPT_COALESCING_TIMEOUT) {
6181 pIoc1->CoalescingTimeout = cpu_to_le32(MPT_COALESCING_TIMEOUT);
6182
6183 /* Write NVRAM and current
6184 */
6185 cfg.dir = 1;
6186 cfg.action = MPI_CONFIG_ACTION_PAGE_WRITE_CURRENT;
6187 if (mpt_config(ioc, &cfg) == 0) {
6188 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Reset Current Coalescing Timeout to = %d\n",
6189 ioc->name, MPT_COALESCING_TIMEOUT));
6190
6191 cfg.action = MPI_CONFIG_ACTION_PAGE_WRITE_NVRAM;
6192 if (mpt_config(ioc, &cfg) == 0) {
6193 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT
6194 "Reset NVRAM Coalescing Timeout to = %d\n",
6195 ioc->name, MPT_COALESCING_TIMEOUT));
6196 } else {
6197 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT
6198 "Reset NVRAM Coalescing Timeout Failed\n",
6199 ioc->name));
6200 }
6201
6202 } else {
6203 dprintk(ioc, printk(MYIOC_s_WARN_FMT
6204 "Reset of Current Coalescing Timeout Failed!\n",
6205 ioc->name));
6206 }
6207 }
6208
6209 } else {
6210 dprintk(ioc, printk(MYIOC_s_WARN_FMT "Coalescing Disabled\n", ioc->name));
6211 }
6212 }
6213
6214 pci_free_consistent(ioc->pcidev, iocpage1sz, pIoc1, ioc1_dma);
6215
6216 return;
6217}
6218
6219static void
6220mpt_get_manufacturing_pg_0(MPT_ADAPTER *ioc)
6221{
6222 CONFIGPARMS cfg;
6223 ConfigPageHeader_t hdr;
6224 dma_addr_t buf_dma;
6225 ManufacturingPage0_t *pbuf = NULL;
6226
6227 memset(&cfg, 0 , sizeof(CONFIGPARMS));
6228 memset(&hdr, 0 , sizeof(ConfigPageHeader_t));
6229
6230 hdr.PageType = MPI_CONFIG_PAGETYPE_MANUFACTURING;
6231 cfg.cfghdr.hdr = &hdr;
6232 cfg.physAddr = -1;
6233 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
6234 cfg.timeout = 10;
6235
6236 if (mpt_config(ioc, &cfg) != 0)
6237 goto out;
6238
6239 if (!cfg.cfghdr.hdr->PageLength)
6240 goto out;
6241
6242 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
6243 pbuf = pci_alloc_consistent(ioc->pcidev, hdr.PageLength * 4, &buf_dma);
6244 if (!pbuf)
6245 goto out;
6246
6247 cfg.physAddr = buf_dma;
6248
6249 if (mpt_config(ioc, &cfg) != 0)
6250 goto out;
6251
6252 memcpy(ioc->board_name, pbuf->BoardName, sizeof(ioc->board_name));
6253 memcpy(ioc->board_assembly, pbuf->BoardAssembly, sizeof(ioc->board_assembly));
6254 memcpy(ioc->board_tracer, pbuf->BoardTracerNumber, sizeof(ioc->board_tracer));
6255
6256out:
6257
6258 if (pbuf)
6259 pci_free_consistent(ioc->pcidev, hdr.PageLength * 4, pbuf, buf_dma);
6260}
6261
6262/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
6263/**
6264 * SendEventNotification - Send EventNotification (on or off) request to adapter
6265 * @ioc: Pointer to MPT_ADAPTER structure
6266 * @EvSwitch: Event switch flags
6267 * @sleepFlag: Specifies whether the process can sleep
6268 */
6269static int
6270SendEventNotification(MPT_ADAPTER *ioc, u8 EvSwitch, int sleepFlag)
6271{
6272 EventNotification_t evn;
6273 MPIDefaultReply_t reply_buf;
6274
6275 memset(&evn, 0, sizeof(EventNotification_t));
6276 memset(&reply_buf, 0, sizeof(MPIDefaultReply_t));
6277
6278 evn.Function = MPI_FUNCTION_EVENT_NOTIFICATION;
6279 evn.Switch = EvSwitch;
6280 evn.MsgContext = cpu_to_le32(mpt_base_index << 16);
6281
6282 devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT
6283 "Sending EventNotification (%d) request %p\n",
6284 ioc->name, EvSwitch, &evn));
6285
6286 return mpt_handshake_req_reply_wait(ioc, sizeof(EventNotification_t),
6287 (u32 *)&evn, sizeof(MPIDefaultReply_t), (u16 *)&reply_buf, 30,
6288 sleepFlag);
6289}
6290
6291/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
6292/**
6293 * SendEventAck - Send EventAck request to MPT adapter.
6294 * @ioc: Pointer to MPT_ADAPTER structure
6295 * @evnp: Pointer to original EventNotification request
6296 */
6297static int
6298SendEventAck(MPT_ADAPTER *ioc, EventNotificationReply_t *evnp)
6299{
6300 EventAck_t *pAck;
6301
6302 if ((pAck = (EventAck_t *) mpt_get_msg_frame(mpt_base_index, ioc)) == NULL) {
6303 dfailprintk(ioc, printk(MYIOC_s_WARN_FMT "%s, no msg frames!!\n",
6304 ioc->name, __func__));
6305 return -1;
6306 }
6307
6308 devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending EventAck\n", ioc->name));
6309
6310 pAck->Function = MPI_FUNCTION_EVENT_ACK;
6311 pAck->ChainOffset = 0;
6312 pAck->Reserved[0] = pAck->Reserved[1] = 0;
6313 pAck->MsgFlags = 0;
6314 pAck->Reserved1[0] = pAck->Reserved1[1] = pAck->Reserved1[2] = 0;
6315 pAck->Event = evnp->Event;
6316 pAck->EventContext = evnp->EventContext;
6317
6318 mpt_put_msg_frame(mpt_base_index, ioc, (MPT_FRAME_HDR *)pAck);
6319
6320 return 0;
6321}
6322
6323/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
6324/**
6325 * mpt_config - Generic function to issue config message
6326 * @ioc: Pointer to an adapter structure
6327 * @pCfg: Pointer to a configuration structure. Struct contains
6328 * action, page address, direction, physical address
6329 * and pointer to a configuration page header
6330 * Page header is updated.
6331 *
6332 * Returns 0 for success
6333 * -EPERM if not allowed due to ISR context
6334 * -EAGAIN if no msg frames currently available
6335 * -EFAULT for non-successful reply or no reply (timeout)
6336 */
6337int
6338mpt_config(MPT_ADAPTER *ioc, CONFIGPARMS *pCfg)
6339{
6340 Config_t *pReq;
6341 ConfigReply_t *pReply;
6342 ConfigExtendedPageHeader_t *pExtHdr = NULL;
6343 MPT_FRAME_HDR *mf;
6344 int ii;
6345 int flagsLength;
6346 long timeout;
6347 int ret;
6348 u8 page_type = 0, extend_page;
6349 unsigned long timeleft;
6350 unsigned long flags;
6351 int in_isr;
6352 u8 issue_hard_reset = 0;
6353 u8 retry_count = 0;
6354
6355 /* Prevent calling wait_event() (below), if caller happens
6356 * to be in ISR context, because that is fatal!
6357 */
6358 in_isr = in_interrupt();
6359 if (in_isr) {
6360 dcprintk(ioc, printk(MYIOC_s_WARN_FMT "Config request not allowed in ISR context!\n",
6361 ioc->name));
6362 return -EPERM;
6363 }
6364
6365 /* don't send a config page during diag reset */
6366 spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
6367 if (ioc->ioc_reset_in_progress) {
6368 dfailprintk(ioc, printk(MYIOC_s_DEBUG_FMT
6369 "%s: busy with host reset\n", ioc->name, __func__));
6370 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
6371 return -EBUSY;
6372 }
6373 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
6374
6375 /* don't send if no chance of success */
6376 if (!ioc->active ||
6377 mpt_GetIocState(ioc, 1) != MPI_IOC_STATE_OPERATIONAL) {
6378 dfailprintk(ioc, printk(MYIOC_s_DEBUG_FMT
6379 "%s: ioc not operational, %d, %xh\n",
6380 ioc->name, __func__, ioc->active,
6381 mpt_GetIocState(ioc, 0)));
6382 return -EFAULT;
6383 }
6384
6385 retry_config:
6386 mutex_lock(&ioc->mptbase_cmds.mutex);
6387 /* init the internal cmd struct */
6388 memset(ioc->mptbase_cmds.reply, 0 , MPT_DEFAULT_FRAME_SIZE);
6389 INITIALIZE_MGMT_STATUS(ioc->mptbase_cmds.status)
6390
6391 /* Get and Populate a free Frame
6392 */
6393 if ((mf = mpt_get_msg_frame(mpt_base_index, ioc)) == NULL) {
6394 dcprintk(ioc, printk(MYIOC_s_WARN_FMT
6395 "mpt_config: no msg frames!\n", ioc->name));
6396 ret = -EAGAIN;
6397 goto out;
6398 }
6399
6400 pReq = (Config_t *)mf;
6401 pReq->Action = pCfg->action;
6402 pReq->Reserved = 0;
6403 pReq->ChainOffset = 0;
6404 pReq->Function = MPI_FUNCTION_CONFIG;
6405
6406 /* Assume page type is not extended and clear "reserved" fields. */
6407 pReq->ExtPageLength = 0;
6408 pReq->ExtPageType = 0;
6409 pReq->MsgFlags = 0;
6410
6411 for (ii=0; ii < 8; ii++)
6412 pReq->Reserved2[ii] = 0;
6413
6414 pReq->Header.PageVersion = pCfg->cfghdr.hdr->PageVersion;
6415 pReq->Header.PageLength = pCfg->cfghdr.hdr->PageLength;
6416 pReq->Header.PageNumber = pCfg->cfghdr.hdr->PageNumber;
6417 pReq->Header.PageType = (pCfg->cfghdr.hdr->PageType & MPI_CONFIG_PAGETYPE_MASK);
6418
6419 if ((pCfg->cfghdr.hdr->PageType & MPI_CONFIG_PAGETYPE_MASK) == MPI_CONFIG_PAGETYPE_EXTENDED) {
6420 pExtHdr = (ConfigExtendedPageHeader_t *)pCfg->cfghdr.ehdr;
6421 pReq->ExtPageLength = cpu_to_le16(pExtHdr->ExtPageLength);
6422 pReq->ExtPageType = pExtHdr->ExtPageType;
6423 pReq->Header.PageType = MPI_CONFIG_PAGETYPE_EXTENDED;
6424
6425 /* Page Length must be treated as a reserved field for the
6426 * extended header.
6427 */
6428 pReq->Header.PageLength = 0;
6429 }
6430
6431 pReq->PageAddress = cpu_to_le32(pCfg->pageAddr);
6432
6433 /* Add a SGE to the config request.
6434 */
6435 if (pCfg->dir)
6436 flagsLength = MPT_SGE_FLAGS_SSIMPLE_WRITE;
6437 else
6438 flagsLength = MPT_SGE_FLAGS_SSIMPLE_READ;
6439
6440 if ((pCfg->cfghdr.hdr->PageType & MPI_CONFIG_PAGETYPE_MASK) ==
6441 MPI_CONFIG_PAGETYPE_EXTENDED) {
6442 flagsLength |= pExtHdr->ExtPageLength * 4;
6443 page_type = pReq->ExtPageType;
6444 extend_page = 1;
6445 } else {
6446 flagsLength |= pCfg->cfghdr.hdr->PageLength * 4;
6447 page_type = pReq->Header.PageType;
6448 extend_page = 0;
6449 }
6450
6451 dcprintk(ioc, printk(MYIOC_s_DEBUG_FMT
6452 "Sending Config request type 0x%x, page 0x%x and action %d\n",
6453 ioc->name, page_type, pReq->Header.PageNumber, pReq->Action));
6454
6455 ioc->add_sge((char *)&pReq->PageBufferSGE, flagsLength, pCfg->physAddr);
6456 timeout = (pCfg->timeout < 15) ? HZ*15 : HZ*pCfg->timeout;
6457 mpt_put_msg_frame(mpt_base_index, ioc, mf);
6458 timeleft = wait_for_completion_timeout(&ioc->mptbase_cmds.done,
6459 timeout);
6460 if (!(ioc->mptbase_cmds.status & MPT_MGMT_STATUS_COMMAND_GOOD)) {
6461 ret = -ETIME;
6462 dfailprintk(ioc, printk(MYIOC_s_DEBUG_FMT
6463 "Failed Sending Config request type 0x%x, page 0x%x,"
6464 " action %d, status %xh, time left %ld\n\n",
6465 ioc->name, page_type, pReq->Header.PageNumber,
6466 pReq->Action, ioc->mptbase_cmds.status, timeleft));
6467 if (ioc->mptbase_cmds.status & MPT_MGMT_STATUS_DID_IOCRESET)
6468 goto out;
6469 if (!timeleft) {
6470 spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
6471 if (ioc->ioc_reset_in_progress) {
6472 spin_unlock_irqrestore(&ioc->taskmgmt_lock,
6473 flags);
6474 printk(MYIOC_s_INFO_FMT "%s: host reset in"
6475 " progress mpt_config timed out.!!\n",
6476 __func__, ioc->name);
6477 mutex_unlock(&ioc->mptbase_cmds.mutex);
6478 return -EFAULT;
6479 }
6480 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
6481 issue_hard_reset = 1;
6482 }
6483 goto out;
6484 }
6485
6486 if (!(ioc->mptbase_cmds.status & MPT_MGMT_STATUS_RF_VALID)) {
6487 ret = -1;
6488 goto out;
6489 }
6490 pReply = (ConfigReply_t *)ioc->mptbase_cmds.reply;
6491 ret = le16_to_cpu(pReply->IOCStatus) & MPI_IOCSTATUS_MASK;
6492 if (ret == MPI_IOCSTATUS_SUCCESS) {
6493 if (extend_page) {
6494 pCfg->cfghdr.ehdr->ExtPageLength =
6495 le16_to_cpu(pReply->ExtPageLength);
6496 pCfg->cfghdr.ehdr->ExtPageType =
6497 pReply->ExtPageType;
6498 }
6499 pCfg->cfghdr.hdr->PageVersion = pReply->Header.PageVersion;
6500 pCfg->cfghdr.hdr->PageLength = pReply->Header.PageLength;
6501 pCfg->cfghdr.hdr->PageNumber = pReply->Header.PageNumber;
6502 pCfg->cfghdr.hdr->PageType = pReply->Header.PageType;
6503
6504 }
6505
6506 if (retry_count)
6507 printk(MYIOC_s_INFO_FMT "Retry completed "
6508 "ret=0x%x timeleft=%ld\n",
6509 ioc->name, ret, timeleft);
6510
6511 dcprintk(ioc, printk(KERN_DEBUG "IOCStatus=%04xh, IOCLogInfo=%08xh\n",
6512 ret, le32_to_cpu(pReply->IOCLogInfo)));
6513
6514out:
6515
6516 CLEAR_MGMT_STATUS(ioc->mptbase_cmds.status)
6517 mutex_unlock(&ioc->mptbase_cmds.mutex);
6518 if (issue_hard_reset) {
6519 issue_hard_reset = 0;
6520 printk(MYIOC_s_WARN_FMT
6521 "Issuing Reset from %s!!, doorbell=0x%08x\n",
6522 ioc->name, __func__, mpt_GetIocState(ioc, 0));
6523 if (retry_count == 0) {
6524 if (mpt_Soft_Hard_ResetHandler(ioc, CAN_SLEEP) != 0)
6525 retry_count++;
6526 } else
6527 mpt_HardResetHandler(ioc, CAN_SLEEP);
6528
6529 mpt_free_msg_frame(ioc, mf);
6530 /* attempt one retry for a timed out command */
6531 if (retry_count < 2) {
6532 printk(MYIOC_s_INFO_FMT
6533 "Attempting Retry Config request"
6534 " type 0x%x, page 0x%x,"
6535 " action %d\n", ioc->name, page_type,
6536 pCfg->cfghdr.hdr->PageNumber, pCfg->action);
6537 retry_count++;
6538 goto retry_config;
6539 }
6540 }
6541 return ret;
6542
6543}
6544
6545/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
6546/**
6547 * mpt_ioc_reset - Base cleanup for hard reset
6548 * @ioc: Pointer to the adapter structure
6549 * @reset_phase: Indicates pre- or post-reset functionality
6550 *
6551 * Remark: Frees resources with internally generated commands.
6552 */
6553static int
6554mpt_ioc_reset(MPT_ADAPTER *ioc, int reset_phase)
6555{
6556 switch (reset_phase) {
6557 case MPT_IOC_SETUP_RESET:
6558 ioc->taskmgmt_quiesce_io = 1;
6559 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT
6560 "%s: MPT_IOC_SETUP_RESET\n", ioc->name, __func__));
6561 break;
6562 case MPT_IOC_PRE_RESET:
6563 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT
6564 "%s: MPT_IOC_PRE_RESET\n", ioc->name, __func__));
6565 break;
6566 case MPT_IOC_POST_RESET:
6567 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT
6568 "%s: MPT_IOC_POST_RESET\n", ioc->name, __func__));
6569/* wake up mptbase_cmds */
6570 if (ioc->mptbase_cmds.status & MPT_MGMT_STATUS_PENDING) {
6571 ioc->mptbase_cmds.status |=
6572 MPT_MGMT_STATUS_DID_IOCRESET;
6573 complete(&ioc->mptbase_cmds.done);
6574 }
6575/* wake up taskmgmt_cmds */
6576 if (ioc->taskmgmt_cmds.status & MPT_MGMT_STATUS_PENDING) {
6577 ioc->taskmgmt_cmds.status |=
6578 MPT_MGMT_STATUS_DID_IOCRESET;
6579 complete(&ioc->taskmgmt_cmds.done);
6580 }
6581 break;
6582 default:
6583 break;
6584 }
6585
6586 return 1; /* currently means nothing really */
6587}
6588
6589
6590#ifdef CONFIG_PROC_FS /* { */
6591/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
6592/*
6593 * procfs (%MPT_PROCFS_MPTBASEDIR/...) support stuff...
6594 */
6595/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
6596/**
6597 * procmpt_create - Create %MPT_PROCFS_MPTBASEDIR entries.
6598 *
6599 * Returns 0 for success, non-zero for failure.
6600 */
6601static int
6602procmpt_create(void)
6603{
6604 mpt_proc_root_dir = proc_mkdir(MPT_PROCFS_MPTBASEDIR, NULL);
6605 if (mpt_proc_root_dir == NULL)
6606 return -ENOTDIR;
6607
6608 proc_create("summary", S_IRUGO, mpt_proc_root_dir, &mpt_summary_proc_fops);
6609 proc_create("version", S_IRUGO, mpt_proc_root_dir, &mpt_version_proc_fops);
6610 return 0;
6611}
6612
6613/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
6614/**
6615 * procmpt_destroy - Tear down %MPT_PROCFS_MPTBASEDIR entries.
6616 *
6617 * Returns 0 for success, non-zero for failure.
6618 */
6619static void
6620procmpt_destroy(void)
6621{
6622 remove_proc_entry("version", mpt_proc_root_dir);
6623 remove_proc_entry("summary", mpt_proc_root_dir);
6624 remove_proc_entry(MPT_PROCFS_MPTBASEDIR, NULL);
6625}
6626
6627/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
6628/*
6629 * Handles read request from /proc/mpt/summary or /proc/mpt/iocN/summary.
6630 */
6631static void seq_mpt_print_ioc_summary(MPT_ADAPTER *ioc, struct seq_file *m, int showlan);
6632
6633static int mpt_summary_proc_show(struct seq_file *m, void *v)
6634{
6635 MPT_ADAPTER *ioc = m->private;
6636
6637 if (ioc) {
6638 seq_mpt_print_ioc_summary(ioc, m, 1);
6639 } else {
6640 list_for_each_entry(ioc, &ioc_list, list) {
6641 seq_mpt_print_ioc_summary(ioc, m, 1);
6642 }
6643 }
6644
6645 return 0;
6646}
6647
6648static int mpt_summary_proc_open(struct inode *inode, struct file *file)
6649{
6650 return single_open(file, mpt_summary_proc_show, PDE_DATA(inode));
6651}
6652
6653static const struct file_operations mpt_summary_proc_fops = {
6654 .owner = THIS_MODULE,
6655 .open = mpt_summary_proc_open,
6656 .read = seq_read,
6657 .llseek = seq_lseek,
6658 .release = single_release,
6659};
6660
6661static int mpt_version_proc_show(struct seq_file *m, void *v)
6662{
6663 u8 cb_idx;
6664 int scsi, fc, sas, lan, ctl, targ, dmp;
6665 char *drvname;
6666
6667 seq_printf(m, "%s-%s\n", "mptlinux", MPT_LINUX_VERSION_COMMON);
6668 seq_printf(m, " Fusion MPT base driver\n");
6669
6670 scsi = fc = sas = lan = ctl = targ = dmp = 0;
6671 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
6672 drvname = NULL;
6673 if (MptCallbacks[cb_idx]) {
6674 switch (MptDriverClass[cb_idx]) {
6675 case MPTSPI_DRIVER:
6676 if (!scsi++) drvname = "SPI host";
6677 break;
6678 case MPTFC_DRIVER:
6679 if (!fc++) drvname = "FC host";
6680 break;
6681 case MPTSAS_DRIVER:
6682 if (!sas++) drvname = "SAS host";
6683 break;
6684 case MPTLAN_DRIVER:
6685 if (!lan++) drvname = "LAN";
6686 break;
6687 case MPTSTM_DRIVER:
6688 if (!targ++) drvname = "SCSI target";
6689 break;
6690 case MPTCTL_DRIVER:
6691 if (!ctl++) drvname = "ioctl";
6692 break;
6693 }
6694
6695 if (drvname)
6696 seq_printf(m, " Fusion MPT %s driver\n", drvname);
6697 }
6698 }
6699
6700 return 0;
6701}
6702
6703static int mpt_version_proc_open(struct inode *inode, struct file *file)
6704{
6705 return single_open(file, mpt_version_proc_show, NULL);
6706}
6707
6708static const struct file_operations mpt_version_proc_fops = {
6709 .owner = THIS_MODULE,
6710 .open = mpt_version_proc_open,
6711 .read = seq_read,
6712 .llseek = seq_lseek,
6713 .release = single_release,
6714};
6715
6716static int mpt_iocinfo_proc_show(struct seq_file *m, void *v)
6717{
6718 MPT_ADAPTER *ioc = m->private;
6719 char expVer[32];
6720 int sz;
6721 int p;
6722
6723 mpt_get_fw_exp_ver(expVer, ioc);
6724
6725 seq_printf(m, "%s:", ioc->name);
6726 if (ioc->facts.Flags & MPI_IOCFACTS_FLAGS_FW_DOWNLOAD_BOOT)
6727 seq_printf(m, " (f/w download boot flag set)");
6728// if (ioc->facts.IOCExceptions & MPI_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL)
6729// seq_printf(m, " CONFIG_CHECKSUM_FAIL!");
6730
6731 seq_printf(m, "\n ProductID = 0x%04x (%s)\n",
6732 ioc->facts.ProductID,
6733 ioc->prod_name);
6734 seq_printf(m, " FWVersion = 0x%08x%s", ioc->facts.FWVersion.Word, expVer);
6735 if (ioc->facts.FWImageSize)
6736 seq_printf(m, " (fw_size=%d)", ioc->facts.FWImageSize);
6737 seq_printf(m, "\n MsgVersion = 0x%04x\n", ioc->facts.MsgVersion);
6738 seq_printf(m, " FirstWhoInit = 0x%02x\n", ioc->FirstWhoInit);
6739 seq_printf(m, " EventState = 0x%02x\n", ioc->facts.EventState);
6740
6741 seq_printf(m, " CurrentHostMfaHighAddr = 0x%08x\n",
6742 ioc->facts.CurrentHostMfaHighAddr);
6743 seq_printf(m, " CurrentSenseBufferHighAddr = 0x%08x\n",
6744 ioc->facts.CurrentSenseBufferHighAddr);
6745
6746 seq_printf(m, " MaxChainDepth = 0x%02x frames\n", ioc->facts.MaxChainDepth);
6747 seq_printf(m, " MinBlockSize = 0x%02x bytes\n", 4*ioc->facts.BlockSize);
6748
6749 seq_printf(m, " RequestFrames @ 0x%p (Dma @ 0x%p)\n",
6750 (void *)ioc->req_frames, (void *)(ulong)ioc->req_frames_dma);
6751 /*
6752 * Rounding UP to nearest 4-kB boundary here...
6753 */
6754 sz = (ioc->req_sz * ioc->req_depth) + 128;
6755 sz = ((sz + 0x1000UL - 1UL) / 0x1000) * 0x1000;
6756 seq_printf(m, " {CurReqSz=%d} x {CurReqDepth=%d} = %d bytes ^= 0x%x\n",
6757 ioc->req_sz, ioc->req_depth, ioc->req_sz*ioc->req_depth, sz);
6758 seq_printf(m, " {MaxReqSz=%d} {MaxReqDepth=%d}\n",
6759 4*ioc->facts.RequestFrameSize,
6760 ioc->facts.GlobalCredits);
6761
6762 seq_printf(m, " Frames @ 0x%p (Dma @ 0x%p)\n",
6763 (void *)ioc->alloc, (void *)(ulong)ioc->alloc_dma);
6764 sz = (ioc->reply_sz * ioc->reply_depth) + 128;
6765 seq_printf(m, " {CurRepSz=%d} x {CurRepDepth=%d} = %d bytes ^= 0x%x\n",
6766 ioc->reply_sz, ioc->reply_depth, ioc->reply_sz*ioc->reply_depth, sz);
6767 seq_printf(m, " {MaxRepSz=%d} {MaxRepDepth=%d}\n",
6768 ioc->facts.CurReplyFrameSize,
6769 ioc->facts.ReplyQueueDepth);
6770
6771 seq_printf(m, " MaxDevices = %d\n",
6772 (ioc->facts.MaxDevices==0) ? 255 : ioc->facts.MaxDevices);
6773 seq_printf(m, " MaxBuses = %d\n", ioc->facts.MaxBuses);
6774
6775 /* per-port info */
6776 for (p=0; p < ioc->facts.NumberOfPorts; p++) {
6777 seq_printf(m, " PortNumber = %d (of %d)\n",
6778 p+1,
6779 ioc->facts.NumberOfPorts);
6780 if (ioc->bus_type == FC) {
6781 if (ioc->pfacts[p].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_LAN) {
6782 u8 *a = (u8*)&ioc->lan_cnfg_page1.HardwareAddressLow;
6783 seq_printf(m, " LanAddr = %pMR\n", a);
6784 }
6785 seq_printf(m, " WWN = %08X%08X:%08X%08X\n",
6786 ioc->fc_port_page0[p].WWNN.High,
6787 ioc->fc_port_page0[p].WWNN.Low,
6788 ioc->fc_port_page0[p].WWPN.High,
6789 ioc->fc_port_page0[p].WWPN.Low);
6790 }
6791 }
6792
6793 return 0;
6794}
6795
6796static int mpt_iocinfo_proc_open(struct inode *inode, struct file *file)
6797{
6798 return single_open(file, mpt_iocinfo_proc_show, PDE_DATA(inode));
6799}
6800
6801static const struct file_operations mpt_iocinfo_proc_fops = {
6802 .owner = THIS_MODULE,
6803 .open = mpt_iocinfo_proc_open,
6804 .read = seq_read,
6805 .llseek = seq_lseek,
6806 .release = single_release,
6807};
6808#endif /* CONFIG_PROC_FS } */
6809
6810/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
6811static void
6812mpt_get_fw_exp_ver(char *buf, MPT_ADAPTER *ioc)
6813{
6814 buf[0] ='\0';
6815 if ((ioc->facts.FWVersion.Word >> 24) == 0x0E) {
6816 sprintf(buf, " (Exp %02d%02d)",
6817 (ioc->facts.FWVersion.Word >> 16) & 0x00FF, /* Month */
6818 (ioc->facts.FWVersion.Word >> 8) & 0x1F); /* Day */
6819
6820 /* insider hack! */
6821 if ((ioc->facts.FWVersion.Word >> 8) & 0x80)
6822 strcat(buf, " [MDBG]");
6823 }
6824}
6825
6826/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
6827/**
6828 * mpt_print_ioc_summary - Write ASCII summary of IOC to a buffer.
6829 * @ioc: Pointer to MPT_ADAPTER structure
6830 * @buffer: Pointer to buffer where IOC summary info should be written
6831 * @size: Pointer to number of bytes we wrote (set by this routine)
6832 * @len: Offset at which to start writing in buffer
6833 * @showlan: Display LAN stuff?
6834 *
6835 * This routine writes (english readable) ASCII text, which represents
6836 * a summary of IOC information, to a buffer.
6837 */
6838void
6839mpt_print_ioc_summary(MPT_ADAPTER *ioc, char *buffer, int *size, int len, int showlan)
6840{
6841 char expVer[32];
6842 int y;
6843
6844 mpt_get_fw_exp_ver(expVer, ioc);
6845
6846 /*
6847 * Shorter summary of attached ioc's...
6848 */
6849 y = sprintf(buffer+len, "%s: %s, %s%08xh%s, Ports=%d, MaxQ=%d",
6850 ioc->name,
6851 ioc->prod_name,
6852 MPT_FW_REV_MAGIC_ID_STRING, /* "FwRev=" or somesuch */
6853 ioc->facts.FWVersion.Word,
6854 expVer,
6855 ioc->facts.NumberOfPorts,
6856 ioc->req_depth);
6857
6858 if (showlan && (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_LAN)) {
6859 u8 *a = (u8*)&ioc->lan_cnfg_page1.HardwareAddressLow;
6860 y += sprintf(buffer+len+y, ", LanAddr=%pMR", a);
6861 }
6862
6863 y += sprintf(buffer+len+y, ", IRQ=%d", ioc->pci_irq);
6864
6865 if (!ioc->active)
6866 y += sprintf(buffer+len+y, " (disabled)");
6867
6868 y += sprintf(buffer+len+y, "\n");
6869
6870 *size = y;
6871}
6872
6873#ifdef CONFIG_PROC_FS
6874static void seq_mpt_print_ioc_summary(MPT_ADAPTER *ioc, struct seq_file *m, int showlan)
6875{
6876 char expVer[32];
6877
6878 mpt_get_fw_exp_ver(expVer, ioc);
6879
6880 /*
6881 * Shorter summary of attached ioc's...
6882 */
6883 seq_printf(m, "%s: %s, %s%08xh%s, Ports=%d, MaxQ=%d",
6884 ioc->name,
6885 ioc->prod_name,
6886 MPT_FW_REV_MAGIC_ID_STRING, /* "FwRev=" or somesuch */
6887 ioc->facts.FWVersion.Word,
6888 expVer,
6889 ioc->facts.NumberOfPorts,
6890 ioc->req_depth);
6891
6892 if (showlan && (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_LAN)) {
6893 u8 *a = (u8*)&ioc->lan_cnfg_page1.HardwareAddressLow;
6894 seq_printf(m, ", LanAddr=%pMR", a);
6895 }
6896
6897 seq_printf(m, ", IRQ=%d", ioc->pci_irq);
6898
6899 if (!ioc->active)
6900 seq_printf(m, " (disabled)");
6901
6902 seq_putc(m, '\n');
6903}
6904#endif
6905
6906/**
6907 * mpt_set_taskmgmt_in_progress_flag - set flags associated with task management
6908 * @ioc: Pointer to MPT_ADAPTER structure
6909 *
6910 * Returns 0 for SUCCESS or -1 if FAILED.
6911 *
6912 * If -1 is return, then it was not possible to set the flags
6913 **/
6914int
6915mpt_set_taskmgmt_in_progress_flag(MPT_ADAPTER *ioc)
6916{
6917 unsigned long flags;
6918 int retval;
6919
6920 spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
6921 if (ioc->ioc_reset_in_progress || ioc->taskmgmt_in_progress ||
6922 (ioc->alt_ioc && ioc->alt_ioc->taskmgmt_in_progress)) {
6923 retval = -1;
6924 goto out;
6925 }
6926 retval = 0;
6927 ioc->taskmgmt_in_progress = 1;
6928 ioc->taskmgmt_quiesce_io = 1;
6929 if (ioc->alt_ioc) {
6930 ioc->alt_ioc->taskmgmt_in_progress = 1;
6931 ioc->alt_ioc->taskmgmt_quiesce_io = 1;
6932 }
6933 out:
6934 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
6935 return retval;
6936}
6937EXPORT_SYMBOL(mpt_set_taskmgmt_in_progress_flag);
6938
6939/**
6940 * mpt_clear_taskmgmt_in_progress_flag - clear flags associated with task management
6941 * @ioc: Pointer to MPT_ADAPTER structure
6942 *
6943 **/
6944void
6945mpt_clear_taskmgmt_in_progress_flag(MPT_ADAPTER *ioc)
6946{
6947 unsigned long flags;
6948
6949 spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
6950 ioc->taskmgmt_in_progress = 0;
6951 ioc->taskmgmt_quiesce_io = 0;
6952 if (ioc->alt_ioc) {
6953 ioc->alt_ioc->taskmgmt_in_progress = 0;
6954 ioc->alt_ioc->taskmgmt_quiesce_io = 0;
6955 }
6956 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
6957}
6958EXPORT_SYMBOL(mpt_clear_taskmgmt_in_progress_flag);
6959
6960
6961/**
6962 * mpt_halt_firmware - Halts the firmware if it is operational and panic
6963 * the kernel
6964 * @ioc: Pointer to MPT_ADAPTER structure
6965 *
6966 **/
6967void
6968mpt_halt_firmware(MPT_ADAPTER *ioc)
6969{
6970 u32 ioc_raw_state;
6971
6972 ioc_raw_state = mpt_GetIocState(ioc, 0);
6973
6974 if ((ioc_raw_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_FAULT) {
6975 printk(MYIOC_s_ERR_FMT "IOC is in FAULT state (%04xh)!!!\n",
6976 ioc->name, ioc_raw_state & MPI_DOORBELL_DATA_MASK);
6977 panic("%s: IOC Fault (%04xh)!!!\n", ioc->name,
6978 ioc_raw_state & MPI_DOORBELL_DATA_MASK);
6979 } else {
6980 CHIPREG_WRITE32(&ioc->chip->Doorbell, 0xC0FFEE00);
6981 panic("%s: Firmware is halted due to command timeout\n",
6982 ioc->name);
6983 }
6984}
6985EXPORT_SYMBOL(mpt_halt_firmware);
6986
6987/**
6988 * mpt_SoftResetHandler - Issues a less expensive reset
6989 * @ioc: Pointer to MPT_ADAPTER structure
6990 * @sleepFlag: Indicates if sleep or schedule must be called.
6991 *
6992 * Returns 0 for SUCCESS or -1 if FAILED.
6993 *
6994 * Message Unit Reset - instructs the IOC to reset the Reply Post and
6995 * Free FIFO's. All the Message Frames on Reply Free FIFO are discarded.
6996 * All posted buffers are freed, and event notification is turned off.
6997 * IOC doesn't reply to any outstanding request. This will transfer IOC
6998 * to READY state.
6999 **/
7000static int
7001mpt_SoftResetHandler(MPT_ADAPTER *ioc, int sleepFlag)
7002{
7003 int rc;
7004 int ii;
7005 u8 cb_idx;
7006 unsigned long flags;
7007 u32 ioc_state;
7008 unsigned long time_count;
7009
7010 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT "SoftResetHandler Entered!\n",
7011 ioc->name));
7012
7013 ioc_state = mpt_GetIocState(ioc, 0) & MPI_IOC_STATE_MASK;
7014
7015 if (mpt_fwfault_debug)
7016 mpt_halt_firmware(ioc);
7017
7018 if (ioc_state == MPI_IOC_STATE_FAULT ||
7019 ioc_state == MPI_IOC_STATE_RESET) {
7020 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT
7021 "skipping, either in FAULT or RESET state!\n", ioc->name));
7022 return -1;
7023 }
7024
7025 if (ioc->bus_type == FC) {
7026 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT
7027 "skipping, because the bus type is FC!\n", ioc->name));
7028 return -1;
7029 }
7030
7031 spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
7032 if (ioc->ioc_reset_in_progress) {
7033 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
7034 return -1;
7035 }
7036 ioc->ioc_reset_in_progress = 1;
7037 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
7038
7039 rc = -1;
7040
7041 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
7042 if (MptResetHandlers[cb_idx])
7043 mpt_signal_reset(cb_idx, ioc, MPT_IOC_SETUP_RESET);
7044 }
7045
7046 spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
7047 if (ioc->taskmgmt_in_progress) {
7048 ioc->ioc_reset_in_progress = 0;
7049 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
7050 return -1;
7051 }
7052 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
7053 /* Disable reply interrupts (also blocks FreeQ) */
7054 CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF);
7055 ioc->active = 0;
7056 time_count = jiffies;
7057
7058 rc = SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, sleepFlag);
7059
7060 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
7061 if (MptResetHandlers[cb_idx])
7062 mpt_signal_reset(cb_idx, ioc, MPT_IOC_PRE_RESET);
7063 }
7064
7065 if (rc)
7066 goto out;
7067
7068 ioc_state = mpt_GetIocState(ioc, 0) & MPI_IOC_STATE_MASK;
7069 if (ioc_state != MPI_IOC_STATE_READY)
7070 goto out;
7071
7072 for (ii = 0; ii < 5; ii++) {
7073 /* Get IOC facts! Allow 5 retries */
7074 rc = GetIocFacts(ioc, sleepFlag,
7075 MPT_HOSTEVENT_IOC_RECOVER);
7076 if (rc == 0)
7077 break;
7078 if (sleepFlag == CAN_SLEEP)
7079 msleep(100);
7080 else
7081 mdelay(100);
7082 }
7083 if (ii == 5)
7084 goto out;
7085
7086 rc = PrimeIocFifos(ioc);
7087 if (rc != 0)
7088 goto out;
7089
7090 rc = SendIocInit(ioc, sleepFlag);
7091 if (rc != 0)
7092 goto out;
7093
7094 rc = SendEventNotification(ioc, 1, sleepFlag);
7095 if (rc != 0)
7096 goto out;
7097
7098 if (ioc->hard_resets < -1)
7099 ioc->hard_resets++;
7100
7101 /*
7102 * At this point, we know soft reset succeeded.
7103 */
7104
7105 ioc->active = 1;
7106 CHIPREG_WRITE32(&ioc->chip->IntMask, MPI_HIM_DIM);
7107
7108 out:
7109 spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
7110 ioc->ioc_reset_in_progress = 0;
7111 ioc->taskmgmt_quiesce_io = 0;
7112 ioc->taskmgmt_in_progress = 0;
7113 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
7114
7115 if (ioc->active) { /* otherwise, hard reset coming */
7116 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
7117 if (MptResetHandlers[cb_idx])
7118 mpt_signal_reset(cb_idx, ioc,
7119 MPT_IOC_POST_RESET);
7120 }
7121 }
7122
7123 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT
7124 "SoftResetHandler: completed (%d seconds): %s\n",
7125 ioc->name, jiffies_to_msecs(jiffies - time_count)/1000,
7126 ((rc == 0) ? "SUCCESS" : "FAILED")));
7127
7128 return rc;
7129}
7130
7131/**
7132 * mpt_Soft_Hard_ResetHandler - Try less expensive reset
7133 * @ioc: Pointer to MPT_ADAPTER structure
7134 * @sleepFlag: Indicates if sleep or schedule must be called.
7135 *
7136 * Returns 0 for SUCCESS or -1 if FAILED.
7137 * Try for softreset first, only if it fails go for expensive
7138 * HardReset.
7139 **/
7140int
7141mpt_Soft_Hard_ResetHandler(MPT_ADAPTER *ioc, int sleepFlag) {
7142 int ret = -1;
7143
7144 ret = mpt_SoftResetHandler(ioc, sleepFlag);
7145 if (ret == 0)
7146 return ret;
7147 ret = mpt_HardResetHandler(ioc, sleepFlag);
7148 return ret;
7149}
7150EXPORT_SYMBOL(mpt_Soft_Hard_ResetHandler);
7151
7152/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
7153/*
7154 * Reset Handling
7155 */
7156/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
7157/**
7158 * mpt_HardResetHandler - Generic reset handler
7159 * @ioc: Pointer to MPT_ADAPTER structure
7160 * @sleepFlag: Indicates if sleep or schedule must be called.
7161 *
7162 * Issues SCSI Task Management call based on input arg values.
7163 * If TaskMgmt fails, returns associated SCSI request.
7164 *
7165 * Remark: _HardResetHandler can be invoked from an interrupt thread (timer)
7166 * or a non-interrupt thread. In the former, must not call schedule().
7167 *
7168 * Note: A return of -1 is a FATAL error case, as it means a
7169 * FW reload/initialization failed.
7170 *
7171 * Returns 0 for SUCCESS or -1 if FAILED.
7172 */
7173int
7174mpt_HardResetHandler(MPT_ADAPTER *ioc, int sleepFlag)
7175{
7176 int rc;
7177 u8 cb_idx;
7178 unsigned long flags;
7179 unsigned long time_count;
7180
7181 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT "HardResetHandler Entered!\n", ioc->name));
7182#ifdef MFCNT
7183 printk(MYIOC_s_INFO_FMT "HardResetHandler Entered!\n", ioc->name);
7184 printk("MF count 0x%x !\n", ioc->mfcnt);
7185#endif
7186 if (mpt_fwfault_debug)
7187 mpt_halt_firmware(ioc);
7188
7189 /* Reset the adapter. Prevent more than 1 call to
7190 * mpt_do_ioc_recovery at any instant in time.
7191 */
7192 spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
7193 if (ioc->ioc_reset_in_progress) {
7194 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
7195 ioc->wait_on_reset_completion = 1;
7196 do {
7197 ssleep(1);
7198 } while (ioc->ioc_reset_in_progress == 1);
7199 ioc->wait_on_reset_completion = 0;
7200 return ioc->reset_status;
7201 }
7202 if (ioc->wait_on_reset_completion) {
7203 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
7204 rc = 0;
7205 time_count = jiffies;
7206 goto exit;
7207 }
7208 ioc->ioc_reset_in_progress = 1;
7209 if (ioc->alt_ioc)
7210 ioc->alt_ioc->ioc_reset_in_progress = 1;
7211 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
7212
7213
7214 /* The SCSI driver needs to adjust timeouts on all current
7215 * commands prior to the diagnostic reset being issued.
7216 * Prevents timeouts occurring during a diagnostic reset...very bad.
7217 * For all other protocol drivers, this is a no-op.
7218 */
7219 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
7220 if (MptResetHandlers[cb_idx]) {
7221 mpt_signal_reset(cb_idx, ioc, MPT_IOC_SETUP_RESET);
7222 if (ioc->alt_ioc)
7223 mpt_signal_reset(cb_idx, ioc->alt_ioc,
7224 MPT_IOC_SETUP_RESET);
7225 }
7226 }
7227
7228 time_count = jiffies;
7229 rc = mpt_do_ioc_recovery(ioc, MPT_HOSTEVENT_IOC_RECOVER, sleepFlag);
7230 if (rc != 0) {
7231 printk(KERN_WARNING MYNAM
7232 ": WARNING - (%d) Cannot recover %s, doorbell=0x%08x\n",
7233 rc, ioc->name, mpt_GetIocState(ioc, 0));
7234 } else {
7235 if (ioc->hard_resets < -1)
7236 ioc->hard_resets++;
7237 }
7238
7239 spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
7240 ioc->ioc_reset_in_progress = 0;
7241 ioc->taskmgmt_quiesce_io = 0;
7242 ioc->taskmgmt_in_progress = 0;
7243 ioc->reset_status = rc;
7244 if (ioc->alt_ioc) {
7245 ioc->alt_ioc->ioc_reset_in_progress = 0;
7246 ioc->alt_ioc->taskmgmt_quiesce_io = 0;
7247 ioc->alt_ioc->taskmgmt_in_progress = 0;
7248 }
7249 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
7250
7251 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
7252 if (MptResetHandlers[cb_idx]) {
7253 mpt_signal_reset(cb_idx, ioc, MPT_IOC_POST_RESET);
7254 if (ioc->alt_ioc)
7255 mpt_signal_reset(cb_idx,
7256 ioc->alt_ioc, MPT_IOC_POST_RESET);
7257 }
7258 }
7259exit:
7260 dtmprintk(ioc,
7261 printk(MYIOC_s_DEBUG_FMT
7262 "HardResetHandler: completed (%d seconds): %s\n", ioc->name,
7263 jiffies_to_msecs(jiffies - time_count)/1000, ((rc == 0) ?
7264 "SUCCESS" : "FAILED")));
7265
7266 return rc;
7267}
7268
7269#ifdef CONFIG_FUSION_LOGGING
7270static void
7271mpt_display_event_info(MPT_ADAPTER *ioc, EventNotificationReply_t *pEventReply)
7272{
7273 char *ds = NULL;
7274 u32 evData0;
7275 int ii;
7276 u8 event;
7277 char *evStr = ioc->evStr;
7278
7279 event = le32_to_cpu(pEventReply->Event) & 0xFF;
7280 evData0 = le32_to_cpu(pEventReply->Data[0]);
7281
7282 switch(event) {
7283 case MPI_EVENT_NONE:
7284 ds = "None";
7285 break;
7286 case MPI_EVENT_LOG_DATA:
7287 ds = "Log Data";
7288 break;
7289 case MPI_EVENT_STATE_CHANGE:
7290 ds = "State Change";
7291 break;
7292 case MPI_EVENT_UNIT_ATTENTION:
7293 ds = "Unit Attention";
7294 break;
7295 case MPI_EVENT_IOC_BUS_RESET:
7296 ds = "IOC Bus Reset";
7297 break;
7298 case MPI_EVENT_EXT_BUS_RESET:
7299 ds = "External Bus Reset";
7300 break;
7301 case MPI_EVENT_RESCAN:
7302 ds = "Bus Rescan Event";
7303 break;
7304 case MPI_EVENT_LINK_STATUS_CHANGE:
7305 if (evData0 == MPI_EVENT_LINK_STATUS_FAILURE)
7306 ds = "Link Status(FAILURE) Change";
7307 else
7308 ds = "Link Status(ACTIVE) Change";
7309 break;
7310 case MPI_EVENT_LOOP_STATE_CHANGE:
7311 if (evData0 == MPI_EVENT_LOOP_STATE_CHANGE_LIP)
7312 ds = "Loop State(LIP) Change";
7313 else if (evData0 == MPI_EVENT_LOOP_STATE_CHANGE_LPE)
7314 ds = "Loop State(LPE) Change";
7315 else
7316 ds = "Loop State(LPB) Change";
7317 break;
7318 case MPI_EVENT_LOGOUT:
7319 ds = "Logout";
7320 break;
7321 case MPI_EVENT_EVENT_CHANGE:
7322 if (evData0)
7323 ds = "Events ON";
7324 else
7325 ds = "Events OFF";
7326 break;
7327 case MPI_EVENT_INTEGRATED_RAID:
7328 {
7329 u8 ReasonCode = (u8)(evData0 >> 16);
7330 switch (ReasonCode) {
7331 case MPI_EVENT_RAID_RC_VOLUME_CREATED :
7332 ds = "Integrated Raid: Volume Created";
7333 break;
7334 case MPI_EVENT_RAID_RC_VOLUME_DELETED :
7335 ds = "Integrated Raid: Volume Deleted";
7336 break;
7337 case MPI_EVENT_RAID_RC_VOLUME_SETTINGS_CHANGED :
7338 ds = "Integrated Raid: Volume Settings Changed";
7339 break;
7340 case MPI_EVENT_RAID_RC_VOLUME_STATUS_CHANGED :
7341 ds = "Integrated Raid: Volume Status Changed";
7342 break;
7343 case MPI_EVENT_RAID_RC_VOLUME_PHYSDISK_CHANGED :
7344 ds = "Integrated Raid: Volume Physdisk Changed";
7345 break;
7346 case MPI_EVENT_RAID_RC_PHYSDISK_CREATED :
7347 ds = "Integrated Raid: Physdisk Created";
7348 break;
7349 case MPI_EVENT_RAID_RC_PHYSDISK_DELETED :
7350 ds = "Integrated Raid: Physdisk Deleted";
7351 break;
7352 case MPI_EVENT_RAID_RC_PHYSDISK_SETTINGS_CHANGED :
7353 ds = "Integrated Raid: Physdisk Settings Changed";
7354 break;
7355 case MPI_EVENT_RAID_RC_PHYSDISK_STATUS_CHANGED :
7356 ds = "Integrated Raid: Physdisk Status Changed";
7357 break;
7358 case MPI_EVENT_RAID_RC_DOMAIN_VAL_NEEDED :
7359 ds = "Integrated Raid: Domain Validation Needed";
7360 break;
7361 case MPI_EVENT_RAID_RC_SMART_DATA :
7362 ds = "Integrated Raid; Smart Data";
7363 break;
7364 case MPI_EVENT_RAID_RC_REPLACE_ACTION_STARTED :
7365 ds = "Integrated Raid: Replace Action Started";
7366 break;
7367 default:
7368 ds = "Integrated Raid";
7369 break;
7370 }
7371 break;
7372 }
7373 case MPI_EVENT_SCSI_DEVICE_STATUS_CHANGE:
7374 ds = "SCSI Device Status Change";
7375 break;
7376 case MPI_EVENT_SAS_DEVICE_STATUS_CHANGE:
7377 {
7378 u8 id = (u8)(evData0);
7379 u8 channel = (u8)(evData0 >> 8);
7380 u8 ReasonCode = (u8)(evData0 >> 16);
7381 switch (ReasonCode) {
7382 case MPI_EVENT_SAS_DEV_STAT_RC_ADDED:
7383 snprintf(evStr, EVENT_DESCR_STR_SZ,
7384 "SAS Device Status Change: Added: "
7385 "id=%d channel=%d", id, channel);
7386 break;
7387 case MPI_EVENT_SAS_DEV_STAT_RC_NOT_RESPONDING:
7388 snprintf(evStr, EVENT_DESCR_STR_SZ,
7389 "SAS Device Status Change: Deleted: "
7390 "id=%d channel=%d", id, channel);
7391 break;
7392 case MPI_EVENT_SAS_DEV_STAT_RC_SMART_DATA:
7393 snprintf(evStr, EVENT_DESCR_STR_SZ,
7394 "SAS Device Status Change: SMART Data: "
7395 "id=%d channel=%d", id, channel);
7396 break;
7397 case MPI_EVENT_SAS_DEV_STAT_RC_NO_PERSIST_ADDED:
7398 snprintf(evStr, EVENT_DESCR_STR_SZ,
7399 "SAS Device Status Change: No Persistancy: "
7400 "id=%d channel=%d", id, channel);
7401 break;
7402 case MPI_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED:
7403 snprintf(evStr, EVENT_DESCR_STR_SZ,
7404 "SAS Device Status Change: Unsupported Device "
7405 "Discovered : id=%d channel=%d", id, channel);
7406 break;
7407 case MPI_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET:
7408 snprintf(evStr, EVENT_DESCR_STR_SZ,
7409 "SAS Device Status Change: Internal Device "
7410 "Reset : id=%d channel=%d", id, channel);
7411 break;
7412 case MPI_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL:
7413 snprintf(evStr, EVENT_DESCR_STR_SZ,
7414 "SAS Device Status Change: Internal Task "
7415 "Abort : id=%d channel=%d", id, channel);
7416 break;
7417 case MPI_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL:
7418 snprintf(evStr, EVENT_DESCR_STR_SZ,
7419 "SAS Device Status Change: Internal Abort "
7420 "Task Set : id=%d channel=%d", id, channel);
7421 break;
7422 case MPI_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL:
7423 snprintf(evStr, EVENT_DESCR_STR_SZ,
7424 "SAS Device Status Change: Internal Clear "
7425 "Task Set : id=%d channel=%d", id, channel);
7426 break;
7427 case MPI_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL:
7428 snprintf(evStr, EVENT_DESCR_STR_SZ,
7429 "SAS Device Status Change: Internal Query "
7430 "Task : id=%d channel=%d", id, channel);
7431 break;
7432 default:
7433 snprintf(evStr, EVENT_DESCR_STR_SZ,
7434 "SAS Device Status Change: Unknown: "
7435 "id=%d channel=%d", id, channel);
7436 break;
7437 }
7438 break;
7439 }
7440 case MPI_EVENT_ON_BUS_TIMER_EXPIRED:
7441 ds = "Bus Timer Expired";
7442 break;
7443 case MPI_EVENT_QUEUE_FULL:
7444 {
7445 u16 curr_depth = (u16)(evData0 >> 16);
7446 u8 channel = (u8)(evData0 >> 8);
7447 u8 id = (u8)(evData0);
7448
7449 snprintf(evStr, EVENT_DESCR_STR_SZ,
7450 "Queue Full: channel=%d id=%d depth=%d",
7451 channel, id, curr_depth);
7452 break;
7453 }
7454 case MPI_EVENT_SAS_SES:
7455 ds = "SAS SES Event";
7456 break;
7457 case MPI_EVENT_PERSISTENT_TABLE_FULL:
7458 ds = "Persistent Table Full";
7459 break;
7460 case MPI_EVENT_SAS_PHY_LINK_STATUS:
7461 {
7462 u8 LinkRates = (u8)(evData0 >> 8);
7463 u8 PhyNumber = (u8)(evData0);
7464 LinkRates = (LinkRates & MPI_EVENT_SAS_PLS_LR_CURRENT_MASK) >>
7465 MPI_EVENT_SAS_PLS_LR_CURRENT_SHIFT;
7466 switch (LinkRates) {
7467 case MPI_EVENT_SAS_PLS_LR_RATE_UNKNOWN:
7468 snprintf(evStr, EVENT_DESCR_STR_SZ,
7469 "SAS PHY Link Status: Phy=%d:"
7470 " Rate Unknown",PhyNumber);
7471 break;
7472 case MPI_EVENT_SAS_PLS_LR_RATE_PHY_DISABLED:
7473 snprintf(evStr, EVENT_DESCR_STR_SZ,
7474 "SAS PHY Link Status: Phy=%d:"
7475 " Phy Disabled",PhyNumber);
7476 break;
7477 case MPI_EVENT_SAS_PLS_LR_RATE_FAILED_SPEED_NEGOTIATION:
7478 snprintf(evStr, EVENT_DESCR_STR_SZ,
7479 "SAS PHY Link Status: Phy=%d:"
7480 " Failed Speed Nego",PhyNumber);
7481 break;
7482 case MPI_EVENT_SAS_PLS_LR_RATE_SATA_OOB_COMPLETE:
7483 snprintf(evStr, EVENT_DESCR_STR_SZ,
7484 "SAS PHY Link Status: Phy=%d:"
7485 " Sata OOB Completed",PhyNumber);
7486 break;
7487 case MPI_EVENT_SAS_PLS_LR_RATE_1_5:
7488 snprintf(evStr, EVENT_DESCR_STR_SZ,
7489 "SAS PHY Link Status: Phy=%d:"
7490 " Rate 1.5 Gbps",PhyNumber);
7491 break;
7492 case MPI_EVENT_SAS_PLS_LR_RATE_3_0:
7493 snprintf(evStr, EVENT_DESCR_STR_SZ,
7494 "SAS PHY Link Status: Phy=%d:"
7495 " Rate 3.0 Gbps", PhyNumber);
7496 break;
7497 case MPI_EVENT_SAS_PLS_LR_RATE_6_0:
7498 snprintf(evStr, EVENT_DESCR_STR_SZ,
7499 "SAS PHY Link Status: Phy=%d:"
7500 " Rate 6.0 Gbps", PhyNumber);
7501 break;
7502 default:
7503 snprintf(evStr, EVENT_DESCR_STR_SZ,
7504 "SAS PHY Link Status: Phy=%d", PhyNumber);
7505 break;
7506 }
7507 break;
7508 }
7509 case MPI_EVENT_SAS_DISCOVERY_ERROR:
7510 ds = "SAS Discovery Error";
7511 break;
7512 case MPI_EVENT_IR_RESYNC_UPDATE:
7513 {
7514 u8 resync_complete = (u8)(evData0 >> 16);
7515 snprintf(evStr, EVENT_DESCR_STR_SZ,
7516 "IR Resync Update: Complete = %d:",resync_complete);
7517 break;
7518 }
7519 case MPI_EVENT_IR2:
7520 {
7521 u8 id = (u8)(evData0);
7522 u8 channel = (u8)(evData0 >> 8);
7523 u8 phys_num = (u8)(evData0 >> 24);
7524 u8 ReasonCode = (u8)(evData0 >> 16);
7525
7526 switch (ReasonCode) {
7527 case MPI_EVENT_IR2_RC_LD_STATE_CHANGED:
7528 snprintf(evStr, EVENT_DESCR_STR_SZ,
7529 "IR2: LD State Changed: "
7530 "id=%d channel=%d phys_num=%d",
7531 id, channel, phys_num);
7532 break;
7533 case MPI_EVENT_IR2_RC_PD_STATE_CHANGED:
7534 snprintf(evStr, EVENT_DESCR_STR_SZ,
7535 "IR2: PD State Changed "
7536 "id=%d channel=%d phys_num=%d",
7537 id, channel, phys_num);
7538 break;
7539 case MPI_EVENT_IR2_RC_BAD_BLOCK_TABLE_FULL:
7540 snprintf(evStr, EVENT_DESCR_STR_SZ,
7541 "IR2: Bad Block Table Full: "
7542 "id=%d channel=%d phys_num=%d",
7543 id, channel, phys_num);
7544 break;
7545 case MPI_EVENT_IR2_RC_PD_INSERTED:
7546 snprintf(evStr, EVENT_DESCR_STR_SZ,
7547 "IR2: PD Inserted: "
7548 "id=%d channel=%d phys_num=%d",
7549 id, channel, phys_num);
7550 break;
7551 case MPI_EVENT_IR2_RC_PD_REMOVED:
7552 snprintf(evStr, EVENT_DESCR_STR_SZ,
7553 "IR2: PD Removed: "
7554 "id=%d channel=%d phys_num=%d",
7555 id, channel, phys_num);
7556 break;
7557 case MPI_EVENT_IR2_RC_FOREIGN_CFG_DETECTED:
7558 snprintf(evStr, EVENT_DESCR_STR_SZ,
7559 "IR2: Foreign CFG Detected: "
7560 "id=%d channel=%d phys_num=%d",
7561 id, channel, phys_num);
7562 break;
7563 case MPI_EVENT_IR2_RC_REBUILD_MEDIUM_ERROR:
7564 snprintf(evStr, EVENT_DESCR_STR_SZ,
7565 "IR2: Rebuild Medium Error: "
7566 "id=%d channel=%d phys_num=%d",
7567 id, channel, phys_num);
7568 break;
7569 case MPI_EVENT_IR2_RC_DUAL_PORT_ADDED:
7570 snprintf(evStr, EVENT_DESCR_STR_SZ,
7571 "IR2: Dual Port Added: "
7572 "id=%d channel=%d phys_num=%d",
7573 id, channel, phys_num);
7574 break;
7575 case MPI_EVENT_IR2_RC_DUAL_PORT_REMOVED:
7576 snprintf(evStr, EVENT_DESCR_STR_SZ,
7577 "IR2: Dual Port Removed: "
7578 "id=%d channel=%d phys_num=%d",
7579 id, channel, phys_num);
7580 break;
7581 default:
7582 ds = "IR2";
7583 break;
7584 }
7585 break;
7586 }
7587 case MPI_EVENT_SAS_DISCOVERY:
7588 {
7589 if (evData0)
7590 ds = "SAS Discovery: Start";
7591 else
7592 ds = "SAS Discovery: Stop";
7593 break;
7594 }
7595 case MPI_EVENT_LOG_ENTRY_ADDED:
7596 ds = "SAS Log Entry Added";
7597 break;
7598
7599 case MPI_EVENT_SAS_BROADCAST_PRIMITIVE:
7600 {
7601 u8 phy_num = (u8)(evData0);
7602 u8 port_num = (u8)(evData0 >> 8);
7603 u8 port_width = (u8)(evData0 >> 16);
7604 u8 primative = (u8)(evData0 >> 24);
7605 snprintf(evStr, EVENT_DESCR_STR_SZ,
7606 "SAS Broadcase Primative: phy=%d port=%d "
7607 "width=%d primative=0x%02x",
7608 phy_num, port_num, port_width, primative);
7609 break;
7610 }
7611
7612 case MPI_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE:
7613 {
7614 u8 reason = (u8)(evData0);
7615
7616 switch (reason) {
7617 case MPI_EVENT_SAS_INIT_RC_ADDED:
7618 ds = "SAS Initiator Status Change: Added";
7619 break;
7620 case MPI_EVENT_SAS_INIT_RC_REMOVED:
7621 ds = "SAS Initiator Status Change: Deleted";
7622 break;
7623 default:
7624 ds = "SAS Initiator Status Change";
7625 break;
7626 }
7627 break;
7628 }
7629
7630 case MPI_EVENT_SAS_INIT_TABLE_OVERFLOW:
7631 {
7632 u8 max_init = (u8)(evData0);
7633 u8 current_init = (u8)(evData0 >> 8);
7634
7635 snprintf(evStr, EVENT_DESCR_STR_SZ,
7636 "SAS Initiator Device Table Overflow: max initiators=%02d "
7637 "current initators=%02d",
7638 max_init, current_init);
7639 break;
7640 }
7641 case MPI_EVENT_SAS_SMP_ERROR:
7642 {
7643 u8 status = (u8)(evData0);
7644 u8 port_num = (u8)(evData0 >> 8);
7645 u8 result = (u8)(evData0 >> 16);
7646
7647 if (status == MPI_EVENT_SAS_SMP_FUNCTION_RESULT_VALID)
7648 snprintf(evStr, EVENT_DESCR_STR_SZ,
7649 "SAS SMP Error: port=%d result=0x%02x",
7650 port_num, result);
7651 else if (status == MPI_EVENT_SAS_SMP_CRC_ERROR)
7652 snprintf(evStr, EVENT_DESCR_STR_SZ,
7653 "SAS SMP Error: port=%d : CRC Error",
7654 port_num);
7655 else if (status == MPI_EVENT_SAS_SMP_TIMEOUT)
7656 snprintf(evStr, EVENT_DESCR_STR_SZ,
7657 "SAS SMP Error: port=%d : Timeout",
7658 port_num);
7659 else if (status == MPI_EVENT_SAS_SMP_NO_DESTINATION)
7660 snprintf(evStr, EVENT_DESCR_STR_SZ,
7661 "SAS SMP Error: port=%d : No Destination",
7662 port_num);
7663 else if (status == MPI_EVENT_SAS_SMP_BAD_DESTINATION)
7664 snprintf(evStr, EVENT_DESCR_STR_SZ,
7665 "SAS SMP Error: port=%d : Bad Destination",
7666 port_num);
7667 else
7668 snprintf(evStr, EVENT_DESCR_STR_SZ,
7669 "SAS SMP Error: port=%d : status=0x%02x",
7670 port_num, status);
7671 break;
7672 }
7673
7674 case MPI_EVENT_SAS_EXPANDER_STATUS_CHANGE:
7675 {
7676 u8 reason = (u8)(evData0);
7677
7678 switch (reason) {
7679 case MPI_EVENT_SAS_EXP_RC_ADDED:
7680 ds = "Expander Status Change: Added";
7681 break;
7682 case MPI_EVENT_SAS_EXP_RC_NOT_RESPONDING:
7683 ds = "Expander Status Change: Deleted";
7684 break;
7685 default:
7686 ds = "Expander Status Change";
7687 break;
7688 }
7689 break;
7690 }
7691
7692 /*
7693 * MPT base "custom" events may be added here...
7694 */
7695 default:
7696 ds = "Unknown";
7697 break;
7698 }
7699 if (ds)
7700 strncpy(evStr, ds, EVENT_DESCR_STR_SZ);
7701
7702
7703 devtprintk(ioc, printk(MYIOC_s_DEBUG_FMT
7704 "MPT event:(%02Xh) : %s\n",
7705 ioc->name, event, evStr));
7706
7707 devtverboseprintk(ioc, printk(KERN_DEBUG MYNAM
7708 ": Event data:\n"));
7709 for (ii = 0; ii < le16_to_cpu(pEventReply->EventDataLength); ii++)
7710 devtverboseprintk(ioc, printk(" %08x",
7711 le32_to_cpu(pEventReply->Data[ii])));
7712 devtverboseprintk(ioc, printk(KERN_DEBUG "\n"));
7713}
7714#endif
7715/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
7716/**
7717 * ProcessEventNotification - Route EventNotificationReply to all event handlers
7718 * @ioc: Pointer to MPT_ADAPTER structure
7719 * @pEventReply: Pointer to EventNotification reply frame
7720 * @evHandlers: Pointer to integer, number of event handlers
7721 *
7722 * Routes a received EventNotificationReply to all currently registered
7723 * event handlers.
7724 * Returns sum of event handlers return values.
7725 */
7726static int
7727ProcessEventNotification(MPT_ADAPTER *ioc, EventNotificationReply_t *pEventReply, int *evHandlers)
7728{
7729 u16 evDataLen;
7730 u32 evData0 = 0;
7731 int ii;
7732 u8 cb_idx;
7733 int r = 0;
7734 int handlers = 0;
7735 u8 event;
7736
7737 /*
7738 * Do platform normalization of values
7739 */
7740 event = le32_to_cpu(pEventReply->Event) & 0xFF;
7741 evDataLen = le16_to_cpu(pEventReply->EventDataLength);
7742 if (evDataLen) {
7743 evData0 = le32_to_cpu(pEventReply->Data[0]);
7744 }
7745
7746#ifdef CONFIG_FUSION_LOGGING
7747 if (evDataLen)
7748 mpt_display_event_info(ioc, pEventReply);
7749#endif
7750
7751 /*
7752 * Do general / base driver event processing
7753 */
7754 switch(event) {
7755 case MPI_EVENT_EVENT_CHANGE: /* 0A */
7756 if (evDataLen) {
7757 u8 evState = evData0 & 0xFF;
7758
7759 /* CHECKME! What if evState unexpectedly says OFF (0)? */
7760
7761 /* Update EventState field in cached IocFacts */
7762 if (ioc->facts.Function) {
7763 ioc->facts.EventState = evState;
7764 }
7765 }
7766 break;
7767 case MPI_EVENT_INTEGRATED_RAID:
7768 mptbase_raid_process_event_data(ioc,
7769 (MpiEventDataRaid_t *)pEventReply->Data);
7770 break;
7771 default:
7772 break;
7773 }
7774
7775 /*
7776 * Should this event be logged? Events are written sequentially.
7777 * When buffer is full, start again at the top.
7778 */
7779 if (ioc->events && (ioc->eventTypes & ( 1 << event))) {
7780 int idx;
7781
7782 idx = ioc->eventContext % MPTCTL_EVENT_LOG_SIZE;
7783
7784 ioc->events[idx].event = event;
7785 ioc->events[idx].eventContext = ioc->eventContext;
7786
7787 for (ii = 0; ii < 2; ii++) {
7788 if (ii < evDataLen)
7789 ioc->events[idx].data[ii] = le32_to_cpu(pEventReply->Data[ii]);
7790 else
7791 ioc->events[idx].data[ii] = 0;
7792 }
7793
7794 ioc->eventContext++;
7795 }
7796
7797
7798 /*
7799 * Call each currently registered protocol event handler.
7800 */
7801 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
7802 if (MptEvHandlers[cb_idx]) {
7803 devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT
7804 "Routing Event to event handler #%d\n",
7805 ioc->name, cb_idx));
7806 r += (*(MptEvHandlers[cb_idx]))(ioc, pEventReply);
7807 handlers++;
7808 }
7809 }
7810 /* FIXME? Examine results here? */
7811
7812 /*
7813 * If needed, send (a single) EventAck.
7814 */
7815 if (pEventReply->AckRequired == MPI_EVENT_NOTIFICATION_ACK_REQUIRED) {
7816 devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT
7817 "EventAck required\n",ioc->name));
7818 if ((ii = SendEventAck(ioc, pEventReply)) != 0) {
7819 devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT "SendEventAck returned %d\n",
7820 ioc->name, ii));
7821 }
7822 }
7823
7824 *evHandlers = handlers;
7825 return r;
7826}
7827
7828/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
7829/**
7830 * mpt_fc_log_info - Log information returned from Fibre Channel IOC.
7831 * @ioc: Pointer to MPT_ADAPTER structure
7832 * @log_info: U32 LogInfo reply word from the IOC
7833 *
7834 * Refer to lsi/mpi_log_fc.h.
7835 */
7836static void
7837mpt_fc_log_info(MPT_ADAPTER *ioc, u32 log_info)
7838{
7839 char *desc = "unknown";
7840
7841 switch (log_info & 0xFF000000) {
7842 case MPI_IOCLOGINFO_FC_INIT_BASE:
7843 desc = "FCP Initiator";
7844 break;
7845 case MPI_IOCLOGINFO_FC_TARGET_BASE:
7846 desc = "FCP Target";
7847 break;
7848 case MPI_IOCLOGINFO_FC_LAN_BASE:
7849 desc = "LAN";
7850 break;
7851 case MPI_IOCLOGINFO_FC_MSG_BASE:
7852 desc = "MPI Message Layer";
7853 break;
7854 case MPI_IOCLOGINFO_FC_LINK_BASE:
7855 desc = "FC Link";
7856 break;
7857 case MPI_IOCLOGINFO_FC_CTX_BASE:
7858 desc = "Context Manager";
7859 break;
7860 case MPI_IOCLOGINFO_FC_INVALID_FIELD_BYTE_OFFSET:
7861 desc = "Invalid Field Offset";
7862 break;
7863 case MPI_IOCLOGINFO_FC_STATE_CHANGE:
7864 desc = "State Change Info";
7865 break;
7866 }
7867
7868 printk(MYIOC_s_INFO_FMT "LogInfo(0x%08x): SubClass={%s}, Value=(0x%06x)\n",
7869 ioc->name, log_info, desc, (log_info & 0xFFFFFF));
7870}
7871
7872/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
7873/**
7874 * mpt_spi_log_info - Log information returned from SCSI Parallel IOC.
7875 * @ioc: Pointer to MPT_ADAPTER structure
7876 * @log_info: U32 LogInfo word from the IOC
7877 *
7878 * Refer to lsi/sp_log.h.
7879 */
7880static void
7881mpt_spi_log_info(MPT_ADAPTER *ioc, u32 log_info)
7882{
7883 u32 info = log_info & 0x00FF0000;
7884 char *desc = "unknown";
7885
7886 switch (info) {
7887 case 0x00010000:
7888 desc = "bug! MID not found";
7889 break;
7890
7891 case 0x00020000:
7892 desc = "Parity Error";
7893 break;
7894
7895 case 0x00030000:
7896 desc = "ASYNC Outbound Overrun";
7897 break;
7898
7899 case 0x00040000:
7900 desc = "SYNC Offset Error";
7901 break;
7902
7903 case 0x00050000:
7904 desc = "BM Change";
7905 break;
7906
7907 case 0x00060000:
7908 desc = "Msg In Overflow";
7909 break;
7910
7911 case 0x00070000:
7912 desc = "DMA Error";
7913 break;
7914
7915 case 0x00080000:
7916 desc = "Outbound DMA Overrun";
7917 break;
7918
7919 case 0x00090000:
7920 desc = "Task Management";
7921 break;
7922
7923 case 0x000A0000:
7924 desc = "Device Problem";
7925 break;
7926
7927 case 0x000B0000:
7928 desc = "Invalid Phase Change";
7929 break;
7930
7931 case 0x000C0000:
7932 desc = "Untagged Table Size";
7933 break;
7934
7935 }
7936
7937 printk(MYIOC_s_INFO_FMT "LogInfo(0x%08x): F/W: %s\n", ioc->name, log_info, desc);
7938}
7939
7940/* strings for sas loginfo */
7941 static char *originator_str[] = {
7942 "IOP", /* 00h */
7943 "PL", /* 01h */
7944 "IR" /* 02h */
7945 };
7946 static char *iop_code_str[] = {
7947 NULL, /* 00h */
7948 "Invalid SAS Address", /* 01h */
7949 NULL, /* 02h */
7950 "Invalid Page", /* 03h */
7951 "Diag Message Error", /* 04h */
7952 "Task Terminated", /* 05h */
7953 "Enclosure Management", /* 06h */
7954 "Target Mode" /* 07h */
7955 };
7956 static char *pl_code_str[] = {
7957 NULL, /* 00h */
7958 "Open Failure", /* 01h */
7959 "Invalid Scatter Gather List", /* 02h */
7960 "Wrong Relative Offset or Frame Length", /* 03h */
7961 "Frame Transfer Error", /* 04h */
7962 "Transmit Frame Connected Low", /* 05h */
7963 "SATA Non-NCQ RW Error Bit Set", /* 06h */
7964 "SATA Read Log Receive Data Error", /* 07h */
7965 "SATA NCQ Fail All Commands After Error", /* 08h */
7966 "SATA Error in Receive Set Device Bit FIS", /* 09h */
7967 "Receive Frame Invalid Message", /* 0Ah */
7968 "Receive Context Message Valid Error", /* 0Bh */
7969 "Receive Frame Current Frame Error", /* 0Ch */
7970 "SATA Link Down", /* 0Dh */
7971 "Discovery SATA Init W IOS", /* 0Eh */
7972 "Config Invalid Page", /* 0Fh */
7973 "Discovery SATA Init Timeout", /* 10h */
7974 "Reset", /* 11h */
7975 "Abort", /* 12h */
7976 "IO Not Yet Executed", /* 13h */
7977 "IO Executed", /* 14h */
7978 "Persistent Reservation Out Not Affiliation "
7979 "Owner", /* 15h */
7980 "Open Transmit DMA Abort", /* 16h */
7981 "IO Device Missing Delay Retry", /* 17h */
7982 "IO Cancelled Due to Receive Error", /* 18h */
7983 NULL, /* 19h */
7984 NULL, /* 1Ah */
7985 NULL, /* 1Bh */
7986 NULL, /* 1Ch */
7987 NULL, /* 1Dh */
7988 NULL, /* 1Eh */
7989 NULL, /* 1Fh */
7990 "Enclosure Management" /* 20h */
7991 };
7992 static char *ir_code_str[] = {
7993 "Raid Action Error", /* 00h */
7994 NULL, /* 00h */
7995 NULL, /* 01h */
7996 NULL, /* 02h */
7997 NULL, /* 03h */
7998 NULL, /* 04h */
7999 NULL, /* 05h */
8000 NULL, /* 06h */
8001 NULL /* 07h */
8002 };
8003 static char *raid_sub_code_str[] = {
8004 NULL, /* 00h */
8005 "Volume Creation Failed: Data Passed too "
8006 "Large", /* 01h */
8007 "Volume Creation Failed: Duplicate Volumes "
8008 "Attempted", /* 02h */
8009 "Volume Creation Failed: Max Number "
8010 "Supported Volumes Exceeded", /* 03h */
8011 "Volume Creation Failed: DMA Error", /* 04h */
8012 "Volume Creation Failed: Invalid Volume Type", /* 05h */
8013 "Volume Creation Failed: Error Reading "
8014 "MFG Page 4", /* 06h */
8015 "Volume Creation Failed: Creating Internal "
8016 "Structures", /* 07h */
8017 NULL, /* 08h */
8018 NULL, /* 09h */
8019 NULL, /* 0Ah */
8020 NULL, /* 0Bh */
8021 NULL, /* 0Ch */
8022 NULL, /* 0Dh */
8023 NULL, /* 0Eh */
8024 NULL, /* 0Fh */
8025 "Activation failed: Already Active Volume", /* 10h */
8026 "Activation failed: Unsupported Volume Type", /* 11h */
8027 "Activation failed: Too Many Active Volumes", /* 12h */
8028 "Activation failed: Volume ID in Use", /* 13h */
8029 "Activation failed: Reported Failure", /* 14h */
8030 "Activation failed: Importing a Volume", /* 15h */
8031 NULL, /* 16h */
8032 NULL, /* 17h */
8033 NULL, /* 18h */
8034 NULL, /* 19h */
8035 NULL, /* 1Ah */
8036 NULL, /* 1Bh */
8037 NULL, /* 1Ch */
8038 NULL, /* 1Dh */
8039 NULL, /* 1Eh */
8040 NULL, /* 1Fh */
8041 "Phys Disk failed: Too Many Phys Disks", /* 20h */
8042 "Phys Disk failed: Data Passed too Large", /* 21h */
8043 "Phys Disk failed: DMA Error", /* 22h */
8044 "Phys Disk failed: Invalid <channel:id>", /* 23h */
8045 "Phys Disk failed: Creating Phys Disk Config "
8046 "Page", /* 24h */
8047 NULL, /* 25h */
8048 NULL, /* 26h */
8049 NULL, /* 27h */
8050 NULL, /* 28h */
8051 NULL, /* 29h */
8052 NULL, /* 2Ah */
8053 NULL, /* 2Bh */
8054 NULL, /* 2Ch */
8055 NULL, /* 2Dh */
8056 NULL, /* 2Eh */
8057 NULL, /* 2Fh */
8058 "Compatibility Error: IR Disabled", /* 30h */
8059 "Compatibility Error: Inquiry Command Failed", /* 31h */
8060 "Compatibility Error: Device not Direct Access "
8061 "Device ", /* 32h */
8062 "Compatibility Error: Removable Device Found", /* 33h */
8063 "Compatibility Error: Device SCSI Version not "
8064 "2 or Higher", /* 34h */
8065 "Compatibility Error: SATA Device, 48 BIT LBA "
8066 "not Supported", /* 35h */
8067 "Compatibility Error: Device doesn't have "
8068 "512 Byte Block Sizes", /* 36h */
8069 "Compatibility Error: Volume Type Check Failed", /* 37h */
8070 "Compatibility Error: Volume Type is "
8071 "Unsupported by FW", /* 38h */
8072 "Compatibility Error: Disk Drive too Small for "
8073 "use in Volume", /* 39h */
8074 "Compatibility Error: Phys Disk for Create "
8075 "Volume not Found", /* 3Ah */
8076 "Compatibility Error: Too Many or too Few "
8077 "Disks for Volume Type", /* 3Bh */
8078 "Compatibility Error: Disk stripe Sizes "
8079 "Must be 64KB", /* 3Ch */
8080 "Compatibility Error: IME Size Limited to < 2TB", /* 3Dh */
8081 };
8082
8083/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
8084/**
8085 * mpt_sas_log_info - Log information returned from SAS IOC.
8086 * @ioc: Pointer to MPT_ADAPTER structure
8087 * @log_info: U32 LogInfo reply word from the IOC
8088 * @cb_idx: callback function's handle
8089 *
8090 * Refer to lsi/mpi_log_sas.h.
8091 **/
8092static void
8093mpt_sas_log_info(MPT_ADAPTER *ioc, u32 log_info, u8 cb_idx)
8094{
8095union loginfo_type {
8096 u32 loginfo;
8097 struct {
8098 u32 subcode:16;
8099 u32 code:8;
8100 u32 originator:4;
8101 u32 bus_type:4;
8102 }dw;
8103};
8104 union loginfo_type sas_loginfo;
8105 char *originator_desc = NULL;
8106 char *code_desc = NULL;
8107 char *sub_code_desc = NULL;
8108
8109 sas_loginfo.loginfo = log_info;
8110 if ((sas_loginfo.dw.bus_type != 3 /*SAS*/) &&
8111 (sas_loginfo.dw.originator < ARRAY_SIZE(originator_str)))
8112 return;
8113
8114 originator_desc = originator_str[sas_loginfo.dw.originator];
8115
8116 switch (sas_loginfo.dw.originator) {
8117
8118 case 0: /* IOP */
8119 if (sas_loginfo.dw.code <
8120 ARRAY_SIZE(iop_code_str))
8121 code_desc = iop_code_str[sas_loginfo.dw.code];
8122 break;
8123 case 1: /* PL */
8124 if (sas_loginfo.dw.code <
8125 ARRAY_SIZE(pl_code_str))
8126 code_desc = pl_code_str[sas_loginfo.dw.code];
8127 break;
8128 case 2: /* IR */
8129 if (sas_loginfo.dw.code >=
8130 ARRAY_SIZE(ir_code_str))
8131 break;
8132 code_desc = ir_code_str[sas_loginfo.dw.code];
8133 if (sas_loginfo.dw.subcode >=
8134 ARRAY_SIZE(raid_sub_code_str))
8135 break;
8136 if (sas_loginfo.dw.code == 0)
8137 sub_code_desc =
8138 raid_sub_code_str[sas_loginfo.dw.subcode];
8139 break;
8140 default:
8141 return;
8142 }
8143
8144 if (sub_code_desc != NULL)
8145 printk(MYIOC_s_INFO_FMT
8146 "LogInfo(0x%08x): Originator={%s}, Code={%s},"
8147 " SubCode={%s} cb_idx %s\n",
8148 ioc->name, log_info, originator_desc, code_desc,
8149 sub_code_desc, MptCallbacksName[cb_idx]);
8150 else if (code_desc != NULL)
8151 printk(MYIOC_s_INFO_FMT
8152 "LogInfo(0x%08x): Originator={%s}, Code={%s},"
8153 " SubCode(0x%04x) cb_idx %s\n",
8154 ioc->name, log_info, originator_desc, code_desc,
8155 sas_loginfo.dw.subcode, MptCallbacksName[cb_idx]);
8156 else
8157 printk(MYIOC_s_INFO_FMT
8158 "LogInfo(0x%08x): Originator={%s}, Code=(0x%02x),"
8159 " SubCode(0x%04x) cb_idx %s\n",
8160 ioc->name, log_info, originator_desc,
8161 sas_loginfo.dw.code, sas_loginfo.dw.subcode,
8162 MptCallbacksName[cb_idx]);
8163}
8164
8165/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
8166/**
8167 * mpt_iocstatus_info_config - IOCSTATUS information for config pages
8168 * @ioc: Pointer to MPT_ADAPTER structure
8169 * @ioc_status: U32 IOCStatus word from IOC
8170 * @mf: Pointer to MPT request frame
8171 *
8172 * Refer to lsi/mpi.h.
8173 **/
8174static void
8175mpt_iocstatus_info_config(MPT_ADAPTER *ioc, u32 ioc_status, MPT_FRAME_HDR *mf)
8176{
8177 Config_t *pReq = (Config_t *)mf;
8178 char extend_desc[EVENT_DESCR_STR_SZ];
8179 char *desc = NULL;
8180 u32 form;
8181 u8 page_type;
8182
8183 if (pReq->Header.PageType == MPI_CONFIG_PAGETYPE_EXTENDED)
8184 page_type = pReq->ExtPageType;
8185 else
8186 page_type = pReq->Header.PageType;
8187
8188 /*
8189 * ignore invalid page messages for GET_NEXT_HANDLE
8190 */
8191 form = le32_to_cpu(pReq->PageAddress);
8192 if (ioc_status == MPI_IOCSTATUS_CONFIG_INVALID_PAGE) {
8193 if (page_type == MPI_CONFIG_EXTPAGETYPE_SAS_DEVICE ||
8194 page_type == MPI_CONFIG_EXTPAGETYPE_SAS_EXPANDER ||
8195 page_type == MPI_CONFIG_EXTPAGETYPE_ENCLOSURE) {
8196 if ((form >> MPI_SAS_DEVICE_PGAD_FORM_SHIFT) ==
8197 MPI_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE)
8198 return;
8199 }
8200 if (page_type == MPI_CONFIG_PAGETYPE_FC_DEVICE)
8201 if ((form & MPI_FC_DEVICE_PGAD_FORM_MASK) ==
8202 MPI_FC_DEVICE_PGAD_FORM_NEXT_DID)
8203 return;
8204 }
8205
8206 snprintf(extend_desc, EVENT_DESCR_STR_SZ,
8207 "type=%02Xh, page=%02Xh, action=%02Xh, form=%08Xh",
8208 page_type, pReq->Header.PageNumber, pReq->Action, form);
8209
8210 switch (ioc_status) {
8211
8212 case MPI_IOCSTATUS_CONFIG_INVALID_ACTION: /* 0x0020 */
8213 desc = "Config Page Invalid Action";
8214 break;
8215
8216 case MPI_IOCSTATUS_CONFIG_INVALID_TYPE: /* 0x0021 */
8217 desc = "Config Page Invalid Type";
8218 break;
8219
8220 case MPI_IOCSTATUS_CONFIG_INVALID_PAGE: /* 0x0022 */
8221 desc = "Config Page Invalid Page";
8222 break;
8223
8224 case MPI_IOCSTATUS_CONFIG_INVALID_DATA: /* 0x0023 */
8225 desc = "Config Page Invalid Data";
8226 break;
8227
8228 case MPI_IOCSTATUS_CONFIG_NO_DEFAULTS: /* 0x0024 */
8229 desc = "Config Page No Defaults";
8230 break;
8231
8232 case MPI_IOCSTATUS_CONFIG_CANT_COMMIT: /* 0x0025 */
8233 desc = "Config Page Can't Commit";
8234 break;
8235 }
8236
8237 if (!desc)
8238 return;
8239
8240 dreplyprintk(ioc, printk(MYIOC_s_DEBUG_FMT "IOCStatus(0x%04X): %s: %s\n",
8241 ioc->name, ioc_status, desc, extend_desc));
8242}
8243
8244/**
8245 * mpt_iocstatus_info - IOCSTATUS information returned from IOC.
8246 * @ioc: Pointer to MPT_ADAPTER structure
8247 * @ioc_status: U32 IOCStatus word from IOC
8248 * @mf: Pointer to MPT request frame
8249 *
8250 * Refer to lsi/mpi.h.
8251 **/
8252static void
8253mpt_iocstatus_info(MPT_ADAPTER *ioc, u32 ioc_status, MPT_FRAME_HDR *mf)
8254{
8255 u32 status = ioc_status & MPI_IOCSTATUS_MASK;
8256 char *desc = NULL;
8257
8258 switch (status) {
8259
8260/****************************************************************************/
8261/* Common IOCStatus values for all replies */
8262/****************************************************************************/
8263
8264 case MPI_IOCSTATUS_INVALID_FUNCTION: /* 0x0001 */
8265 desc = "Invalid Function";
8266 break;
8267
8268 case MPI_IOCSTATUS_BUSY: /* 0x0002 */
8269 desc = "Busy";
8270 break;
8271
8272 case MPI_IOCSTATUS_INVALID_SGL: /* 0x0003 */
8273 desc = "Invalid SGL";
8274 break;
8275
8276 case MPI_IOCSTATUS_INTERNAL_ERROR: /* 0x0004 */
8277 desc = "Internal Error";
8278 break;
8279
8280 case MPI_IOCSTATUS_RESERVED: /* 0x0005 */
8281 desc = "Reserved";
8282 break;
8283
8284 case MPI_IOCSTATUS_INSUFFICIENT_RESOURCES: /* 0x0006 */
8285 desc = "Insufficient Resources";
8286 break;
8287
8288 case MPI_IOCSTATUS_INVALID_FIELD: /* 0x0007 */
8289 desc = "Invalid Field";
8290 break;
8291
8292 case MPI_IOCSTATUS_INVALID_STATE: /* 0x0008 */
8293 desc = "Invalid State";
8294 break;
8295
8296/****************************************************************************/
8297/* Config IOCStatus values */
8298/****************************************************************************/
8299
8300 case MPI_IOCSTATUS_CONFIG_INVALID_ACTION: /* 0x0020 */
8301 case MPI_IOCSTATUS_CONFIG_INVALID_TYPE: /* 0x0021 */
8302 case MPI_IOCSTATUS_CONFIG_INVALID_PAGE: /* 0x0022 */
8303 case MPI_IOCSTATUS_CONFIG_INVALID_DATA: /* 0x0023 */
8304 case MPI_IOCSTATUS_CONFIG_NO_DEFAULTS: /* 0x0024 */
8305 case MPI_IOCSTATUS_CONFIG_CANT_COMMIT: /* 0x0025 */
8306 mpt_iocstatus_info_config(ioc, status, mf);
8307 break;
8308
8309/****************************************************************************/
8310/* SCSIIO Reply (SPI, FCP, SAS) initiator values */
8311/* */
8312/* Look at mptscsih_iocstatus_info_scsiio in mptscsih.c */
8313/* */
8314/****************************************************************************/
8315
8316 case MPI_IOCSTATUS_SCSI_RECOVERED_ERROR: /* 0x0040 */
8317 case MPI_IOCSTATUS_SCSI_DATA_UNDERRUN: /* 0x0045 */
8318 case MPI_IOCSTATUS_SCSI_INVALID_BUS: /* 0x0041 */
8319 case MPI_IOCSTATUS_SCSI_INVALID_TARGETID: /* 0x0042 */
8320 case MPI_IOCSTATUS_SCSI_DEVICE_NOT_THERE: /* 0x0043 */
8321 case MPI_IOCSTATUS_SCSI_DATA_OVERRUN: /* 0x0044 */
8322 case MPI_IOCSTATUS_SCSI_IO_DATA_ERROR: /* 0x0046 */
8323 case MPI_IOCSTATUS_SCSI_PROTOCOL_ERROR: /* 0x0047 */
8324 case MPI_IOCSTATUS_SCSI_TASK_TERMINATED: /* 0x0048 */
8325 case MPI_IOCSTATUS_SCSI_RESIDUAL_MISMATCH: /* 0x0049 */
8326 case MPI_IOCSTATUS_SCSI_TASK_MGMT_FAILED: /* 0x004A */
8327 case MPI_IOCSTATUS_SCSI_IOC_TERMINATED: /* 0x004B */
8328 case MPI_IOCSTATUS_SCSI_EXT_TERMINATED: /* 0x004C */
8329 break;
8330
8331/****************************************************************************/
8332/* SCSI Target values */
8333/****************************************************************************/
8334
8335 case MPI_IOCSTATUS_TARGET_PRIORITY_IO: /* 0x0060 */
8336 desc = "Target: Priority IO";
8337 break;
8338
8339 case MPI_IOCSTATUS_TARGET_INVALID_PORT: /* 0x0061 */
8340 desc = "Target: Invalid Port";
8341 break;
8342
8343 case MPI_IOCSTATUS_TARGET_INVALID_IO_INDEX: /* 0x0062 */
8344 desc = "Target Invalid IO Index:";
8345 break;
8346
8347 case MPI_IOCSTATUS_TARGET_ABORTED: /* 0x0063 */
8348 desc = "Target: Aborted";
8349 break;
8350
8351 case MPI_IOCSTATUS_TARGET_NO_CONN_RETRYABLE: /* 0x0064 */
8352 desc = "Target: No Conn Retryable";
8353 break;
8354
8355 case MPI_IOCSTATUS_TARGET_NO_CONNECTION: /* 0x0065 */
8356 desc = "Target: No Connection";
8357 break;
8358
8359 case MPI_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH: /* 0x006A */
8360 desc = "Target: Transfer Count Mismatch";
8361 break;
8362
8363 case MPI_IOCSTATUS_TARGET_STS_DATA_NOT_SENT: /* 0x006B */
8364 desc = "Target: STS Data not Sent";
8365 break;
8366
8367 case MPI_IOCSTATUS_TARGET_DATA_OFFSET_ERROR: /* 0x006D */
8368 desc = "Target: Data Offset Error";
8369 break;
8370
8371 case MPI_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA: /* 0x006E */
8372 desc = "Target: Too Much Write Data";
8373 break;
8374
8375 case MPI_IOCSTATUS_TARGET_IU_TOO_SHORT: /* 0x006F */
8376 desc = "Target: IU Too Short";
8377 break;
8378
8379 case MPI_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT: /* 0x0070 */
8380 desc = "Target: ACK NAK Timeout";
8381 break;
8382
8383 case MPI_IOCSTATUS_TARGET_NAK_RECEIVED: /* 0x0071 */
8384 desc = "Target: Nak Received";
8385 break;
8386
8387/****************************************************************************/
8388/* Fibre Channel Direct Access values */
8389/****************************************************************************/
8390
8391 case MPI_IOCSTATUS_FC_ABORTED: /* 0x0066 */
8392 desc = "FC: Aborted";
8393 break;
8394
8395 case MPI_IOCSTATUS_FC_RX_ID_INVALID: /* 0x0067 */
8396 desc = "FC: RX ID Invalid";
8397 break;
8398
8399 case MPI_IOCSTATUS_FC_DID_INVALID: /* 0x0068 */
8400 desc = "FC: DID Invalid";
8401 break;
8402
8403 case MPI_IOCSTATUS_FC_NODE_LOGGED_OUT: /* 0x0069 */
8404 desc = "FC: Node Logged Out";
8405 break;
8406
8407 case MPI_IOCSTATUS_FC_EXCHANGE_CANCELED: /* 0x006C */
8408 desc = "FC: Exchange Canceled";
8409 break;
8410
8411/****************************************************************************/
8412/* LAN values */
8413/****************************************************************************/
8414
8415 case MPI_IOCSTATUS_LAN_DEVICE_NOT_FOUND: /* 0x0080 */
8416 desc = "LAN: Device not Found";
8417 break;
8418
8419 case MPI_IOCSTATUS_LAN_DEVICE_FAILURE: /* 0x0081 */
8420 desc = "LAN: Device Failure";
8421 break;
8422
8423 case MPI_IOCSTATUS_LAN_TRANSMIT_ERROR: /* 0x0082 */
8424 desc = "LAN: Transmit Error";
8425 break;
8426
8427 case MPI_IOCSTATUS_LAN_TRANSMIT_ABORTED: /* 0x0083 */
8428 desc = "LAN: Transmit Aborted";
8429 break;
8430
8431 case MPI_IOCSTATUS_LAN_RECEIVE_ERROR: /* 0x0084 */
8432 desc = "LAN: Receive Error";
8433 break;
8434
8435 case MPI_IOCSTATUS_LAN_RECEIVE_ABORTED: /* 0x0085 */
8436 desc = "LAN: Receive Aborted";
8437 break;
8438
8439 case MPI_IOCSTATUS_LAN_PARTIAL_PACKET: /* 0x0086 */
8440 desc = "LAN: Partial Packet";
8441 break;
8442
8443 case MPI_IOCSTATUS_LAN_CANCELED: /* 0x0087 */
8444 desc = "LAN: Canceled";
8445 break;
8446
8447/****************************************************************************/
8448/* Serial Attached SCSI values */
8449/****************************************************************************/
8450
8451 case MPI_IOCSTATUS_SAS_SMP_REQUEST_FAILED: /* 0x0090 */
8452 desc = "SAS: SMP Request Failed";
8453 break;
8454
8455 case MPI_IOCSTATUS_SAS_SMP_DATA_OVERRUN: /* 0x0090 */
8456 desc = "SAS: SMP Data Overrun";
8457 break;
8458
8459 default:
8460 desc = "Others";
8461 break;
8462 }
8463
8464 if (!desc)
8465 return;
8466
8467 dreplyprintk(ioc, printk(MYIOC_s_DEBUG_FMT "IOCStatus(0x%04X): %s\n",
8468 ioc->name, status, desc));
8469}
8470
8471/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
8472EXPORT_SYMBOL(mpt_attach);
8473EXPORT_SYMBOL(mpt_detach);
8474#ifdef CONFIG_PM
8475EXPORT_SYMBOL(mpt_resume);
8476EXPORT_SYMBOL(mpt_suspend);
8477#endif
8478EXPORT_SYMBOL(ioc_list);
8479EXPORT_SYMBOL(mpt_register);
8480EXPORT_SYMBOL(mpt_deregister);
8481EXPORT_SYMBOL(mpt_event_register);
8482EXPORT_SYMBOL(mpt_event_deregister);
8483EXPORT_SYMBOL(mpt_reset_register);
8484EXPORT_SYMBOL(mpt_reset_deregister);
8485EXPORT_SYMBOL(mpt_device_driver_register);
8486EXPORT_SYMBOL(mpt_device_driver_deregister);
8487EXPORT_SYMBOL(mpt_get_msg_frame);
8488EXPORT_SYMBOL(mpt_put_msg_frame);
8489EXPORT_SYMBOL(mpt_put_msg_frame_hi_pri);
8490EXPORT_SYMBOL(mpt_free_msg_frame);
8491EXPORT_SYMBOL(mpt_send_handshake_request);
8492EXPORT_SYMBOL(mpt_verify_adapter);
8493EXPORT_SYMBOL(mpt_GetIocState);
8494EXPORT_SYMBOL(mpt_print_ioc_summary);
8495EXPORT_SYMBOL(mpt_HardResetHandler);
8496EXPORT_SYMBOL(mpt_config);
8497EXPORT_SYMBOL(mpt_findImVolumes);
8498EXPORT_SYMBOL(mpt_alloc_fw_memory);
8499EXPORT_SYMBOL(mpt_free_fw_memory);
8500EXPORT_SYMBOL(mptbase_sas_persist_operation);
8501EXPORT_SYMBOL(mpt_raid_phys_disk_pg0);
8502
8503/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
8504/**
8505 * fusion_init - Fusion MPT base driver initialization routine.
8506 *
8507 * Returns 0 for success, non-zero for failure.
8508 */
8509static int __init
8510fusion_init(void)
8511{
8512 u8 cb_idx;
8513
8514 show_mptmod_ver(my_NAME, my_VERSION);
8515 printk(KERN_INFO COPYRIGHT "\n");
8516
8517 for (cb_idx = 0; cb_idx < MPT_MAX_PROTOCOL_DRIVERS; cb_idx++) {
8518 MptCallbacks[cb_idx] = NULL;
8519 MptDriverClass[cb_idx] = MPTUNKNOWN_DRIVER;
8520 MptEvHandlers[cb_idx] = NULL;
8521 MptResetHandlers[cb_idx] = NULL;
8522 }
8523
8524 /* Register ourselves (mptbase) in order to facilitate
8525 * EventNotification handling.
8526 */
8527 mpt_base_index = mpt_register(mptbase_reply, MPTBASE_DRIVER,
8528 "mptbase_reply");
8529
8530 /* Register for hard reset handling callbacks.
8531 */
8532 mpt_reset_register(mpt_base_index, mpt_ioc_reset);
8533
8534#ifdef CONFIG_PROC_FS
8535 (void) procmpt_create();
8536#endif
8537 return 0;
8538}
8539
8540/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
8541/**
8542 * fusion_exit - Perform driver unload cleanup.
8543 *
8544 * This routine frees all resources associated with each MPT adapter
8545 * and removes all %MPT_PROCFS_MPTBASEDIR entries.
8546 */
8547static void __exit
8548fusion_exit(void)
8549{
8550
8551 mpt_reset_deregister(mpt_base_index);
8552
8553#ifdef CONFIG_PROC_FS
8554 procmpt_destroy();
8555#endif
8556}
8557
8558module_init(fusion_init);
8559module_exit(fusion_exit);