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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2014 Traphandler
4 * Copyright (C) 2014 Free Electrons
5 * Copyright (C) 2014 Atmel
6 *
7 * Author: Jean-Jacques Hiblot <jjhiblot@traphandler.com>
8 * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
9 */
10
11#include <linux/clk.h>
12#include <linux/irq.h>
13#include <linux/irqchip.h>
14#include <linux/mfd/atmel-hlcdc.h>
15#include <linux/module.h>
16#include <linux/pm_runtime.h>
17#include <linux/platform_device.h>
18
19#include <drm/drm_atomic.h>
20#include <drm/drm_atomic_helper.h>
21#include <drm/drm_client_setup.h>
22#include <drm/drm_drv.h>
23#include <drm/drm_fbdev_dma.h>
24#include <drm/drm_fourcc.h>
25#include <drm/drm_gem_dma_helper.h>
26#include <drm/drm_gem_framebuffer_helper.h>
27#include <drm/drm_module.h>
28#include <drm/drm_probe_helper.h>
29#include <drm/drm_vblank.h>
30
31#include "atmel_hlcdc_dc.h"
32
33#define ATMEL_HLCDC_LAYER_IRQS_OFFSET 8
34
35static const struct atmel_hlcdc_layer_desc atmel_hlcdc_at91sam9n12_layers[] = {
36 {
37 .name = "base",
38 .formats = &atmel_hlcdc_plane_rgb_formats,
39 .regs_offset = 0x40,
40 .id = 0,
41 .type = ATMEL_HLCDC_BASE_LAYER,
42 .cfgs_offset = 0x2c,
43 .layout = {
44 .xstride = { 2 },
45 .default_color = 3,
46 .general_config = 4,
47 },
48 .clut_offset = 0x400,
49 },
50};
51
52static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_at91sam9n12 = {
53 .min_width = 0,
54 .min_height = 0,
55 .max_width = 1280,
56 .max_height = 860,
57 .max_spw = 0x3f,
58 .max_vpw = 0x3f,
59 .max_hpw = 0xff,
60 .conflicting_output_formats = true,
61 .nlayers = ARRAY_SIZE(atmel_hlcdc_at91sam9n12_layers),
62 .layers = atmel_hlcdc_at91sam9n12_layers,
63 .ops = &atmel_hlcdc_ops,
64};
65
66static const struct atmel_hlcdc_layer_desc atmel_hlcdc_at91sam9x5_layers[] = {
67 {
68 .name = "base",
69 .formats = &atmel_hlcdc_plane_rgb_formats,
70 .regs_offset = 0x40,
71 .id = 0,
72 .type = ATMEL_HLCDC_BASE_LAYER,
73 .cfgs_offset = 0x2c,
74 .layout = {
75 .xstride = { 2 },
76 .default_color = 3,
77 .general_config = 4,
78 .disc_pos = 5,
79 .disc_size = 6,
80 },
81 .clut_offset = 0x400,
82 },
83 {
84 .name = "overlay1",
85 .formats = &atmel_hlcdc_plane_rgb_formats,
86 .regs_offset = 0x100,
87 .id = 1,
88 .type = ATMEL_HLCDC_OVERLAY_LAYER,
89 .cfgs_offset = 0x2c,
90 .layout = {
91 .pos = 2,
92 .size = 3,
93 .xstride = { 4 },
94 .pstride = { 5 },
95 .default_color = 6,
96 .chroma_key = 7,
97 .chroma_key_mask = 8,
98 .general_config = 9,
99 },
100 .clut_offset = 0x800,
101 },
102 {
103 .name = "high-end-overlay",
104 .formats = &atmel_hlcdc_plane_rgb_and_yuv_formats,
105 .regs_offset = 0x280,
106 .id = 2,
107 .type = ATMEL_HLCDC_OVERLAY_LAYER,
108 .cfgs_offset = 0x4c,
109 .layout = {
110 .pos = 2,
111 .size = 3,
112 .memsize = 4,
113 .xstride = { 5, 7 },
114 .pstride = { 6, 8 },
115 .default_color = 9,
116 .chroma_key = 10,
117 .chroma_key_mask = 11,
118 .general_config = 12,
119 .scaler_config = 13,
120 .csc = 14,
121 },
122 .clut_offset = 0x1000,
123 },
124 {
125 .name = "cursor",
126 .formats = &atmel_hlcdc_plane_rgb_formats,
127 .regs_offset = 0x340,
128 .id = 3,
129 .type = ATMEL_HLCDC_CURSOR_LAYER,
130 .max_width = 128,
131 .max_height = 128,
132 .cfgs_offset = 0x2c,
133 .layout = {
134 .pos = 2,
135 .size = 3,
136 .xstride = { 4 },
137 .default_color = 6,
138 .chroma_key = 7,
139 .chroma_key_mask = 8,
140 .general_config = 9,
141 },
142 .clut_offset = 0x1400,
143 },
144};
145
146static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_at91sam9x5 = {
147 .min_width = 0,
148 .min_height = 0,
149 .max_width = 800,
150 .max_height = 600,
151 .max_spw = 0x3f,
152 .max_vpw = 0x3f,
153 .max_hpw = 0xff,
154 .conflicting_output_formats = true,
155 .nlayers = ARRAY_SIZE(atmel_hlcdc_at91sam9x5_layers),
156 .layers = atmel_hlcdc_at91sam9x5_layers,
157 .ops = &atmel_hlcdc_ops,
158};
159
160static const struct atmel_hlcdc_layer_desc atmel_hlcdc_sama5d3_layers[] = {
161 {
162 .name = "base",
163 .formats = &atmel_hlcdc_plane_rgb_formats,
164 .regs_offset = 0x40,
165 .id = 0,
166 .type = ATMEL_HLCDC_BASE_LAYER,
167 .cfgs_offset = 0x2c,
168 .layout = {
169 .xstride = { 2 },
170 .default_color = 3,
171 .general_config = 4,
172 .disc_pos = 5,
173 .disc_size = 6,
174 },
175 .clut_offset = 0x600,
176 },
177 {
178 .name = "overlay1",
179 .formats = &atmel_hlcdc_plane_rgb_formats,
180 .regs_offset = 0x140,
181 .id = 1,
182 .type = ATMEL_HLCDC_OVERLAY_LAYER,
183 .cfgs_offset = 0x2c,
184 .layout = {
185 .pos = 2,
186 .size = 3,
187 .xstride = { 4 },
188 .pstride = { 5 },
189 .default_color = 6,
190 .chroma_key = 7,
191 .chroma_key_mask = 8,
192 .general_config = 9,
193 },
194 .clut_offset = 0xa00,
195 },
196 {
197 .name = "overlay2",
198 .formats = &atmel_hlcdc_plane_rgb_formats,
199 .regs_offset = 0x240,
200 .id = 2,
201 .type = ATMEL_HLCDC_OVERLAY_LAYER,
202 .cfgs_offset = 0x2c,
203 .layout = {
204 .pos = 2,
205 .size = 3,
206 .xstride = { 4 },
207 .pstride = { 5 },
208 .default_color = 6,
209 .chroma_key = 7,
210 .chroma_key_mask = 8,
211 .general_config = 9,
212 },
213 .clut_offset = 0xe00,
214 },
215 {
216 .name = "high-end-overlay",
217 .formats = &atmel_hlcdc_plane_rgb_and_yuv_formats,
218 .regs_offset = 0x340,
219 .id = 3,
220 .type = ATMEL_HLCDC_OVERLAY_LAYER,
221 .cfgs_offset = 0x4c,
222 .layout = {
223 .pos = 2,
224 .size = 3,
225 .memsize = 4,
226 .xstride = { 5, 7 },
227 .pstride = { 6, 8 },
228 .default_color = 9,
229 .chroma_key = 10,
230 .chroma_key_mask = 11,
231 .general_config = 12,
232 .scaler_config = 13,
233 .phicoeffs = {
234 .x = 17,
235 .y = 33,
236 },
237 .csc = 14,
238 },
239 .clut_offset = 0x1200,
240 },
241 {
242 .name = "cursor",
243 .formats = &atmel_hlcdc_plane_rgb_formats,
244 .regs_offset = 0x440,
245 .id = 4,
246 .type = ATMEL_HLCDC_CURSOR_LAYER,
247 .max_width = 128,
248 .max_height = 128,
249 .cfgs_offset = 0x2c,
250 .layout = {
251 .pos = 2,
252 .size = 3,
253 .xstride = { 4 },
254 .pstride = { 5 },
255 .default_color = 6,
256 .chroma_key = 7,
257 .chroma_key_mask = 8,
258 .general_config = 9,
259 .scaler_config = 13,
260 },
261 .clut_offset = 0x1600,
262 },
263};
264
265static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_sama5d3 = {
266 .min_width = 0,
267 .min_height = 0,
268 .max_width = 2048,
269 .max_height = 2048,
270 .max_spw = 0x3f,
271 .max_vpw = 0x3f,
272 .max_hpw = 0x1ff,
273 .conflicting_output_formats = true,
274 .nlayers = ARRAY_SIZE(atmel_hlcdc_sama5d3_layers),
275 .layers = atmel_hlcdc_sama5d3_layers,
276 .ops = &atmel_hlcdc_ops,
277};
278
279static const struct atmel_hlcdc_layer_desc atmel_hlcdc_sama5d4_layers[] = {
280 {
281 .name = "base",
282 .formats = &atmel_hlcdc_plane_rgb_formats,
283 .regs_offset = 0x40,
284 .id = 0,
285 .type = ATMEL_HLCDC_BASE_LAYER,
286 .cfgs_offset = 0x2c,
287 .layout = {
288 .xstride = { 2 },
289 .default_color = 3,
290 .general_config = 4,
291 .disc_pos = 5,
292 .disc_size = 6,
293 },
294 .clut_offset = 0x600,
295 },
296 {
297 .name = "overlay1",
298 .formats = &atmel_hlcdc_plane_rgb_formats,
299 .regs_offset = 0x140,
300 .id = 1,
301 .type = ATMEL_HLCDC_OVERLAY_LAYER,
302 .cfgs_offset = 0x2c,
303 .layout = {
304 .pos = 2,
305 .size = 3,
306 .xstride = { 4 },
307 .pstride = { 5 },
308 .default_color = 6,
309 .chroma_key = 7,
310 .chroma_key_mask = 8,
311 .general_config = 9,
312 },
313 .clut_offset = 0xa00,
314 },
315 {
316 .name = "overlay2",
317 .formats = &atmel_hlcdc_plane_rgb_formats,
318 .regs_offset = 0x240,
319 .id = 2,
320 .type = ATMEL_HLCDC_OVERLAY_LAYER,
321 .cfgs_offset = 0x2c,
322 .layout = {
323 .pos = 2,
324 .size = 3,
325 .xstride = { 4 },
326 .pstride = { 5 },
327 .default_color = 6,
328 .chroma_key = 7,
329 .chroma_key_mask = 8,
330 .general_config = 9,
331 },
332 .clut_offset = 0xe00,
333 },
334 {
335 .name = "high-end-overlay",
336 .formats = &atmel_hlcdc_plane_rgb_and_yuv_formats,
337 .regs_offset = 0x340,
338 .id = 3,
339 .type = ATMEL_HLCDC_OVERLAY_LAYER,
340 .cfgs_offset = 0x4c,
341 .layout = {
342 .pos = 2,
343 .size = 3,
344 .memsize = 4,
345 .xstride = { 5, 7 },
346 .pstride = { 6, 8 },
347 .default_color = 9,
348 .chroma_key = 10,
349 .chroma_key_mask = 11,
350 .general_config = 12,
351 .scaler_config = 13,
352 .phicoeffs = {
353 .x = 17,
354 .y = 33,
355 },
356 .csc = 14,
357 },
358 .clut_offset = 0x1200,
359 },
360};
361
362static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_sama5d4 = {
363 .min_width = 0,
364 .min_height = 0,
365 .max_width = 2048,
366 .max_height = 2048,
367 .max_spw = 0xff,
368 .max_vpw = 0xff,
369 .max_hpw = 0x3ff,
370 .nlayers = ARRAY_SIZE(atmel_hlcdc_sama5d4_layers),
371 .layers = atmel_hlcdc_sama5d4_layers,
372 .ops = &atmel_hlcdc_ops,
373};
374
375static const struct atmel_hlcdc_layer_desc atmel_hlcdc_sam9x60_layers[] = {
376 {
377 .name = "base",
378 .formats = &atmel_hlcdc_plane_rgb_formats,
379 .regs_offset = 0x60,
380 .id = 0,
381 .type = ATMEL_HLCDC_BASE_LAYER,
382 .cfgs_offset = 0x2c,
383 .layout = {
384 .xstride = { 2 },
385 .default_color = 3,
386 .general_config = 4,
387 .disc_pos = 5,
388 .disc_size = 6,
389 },
390 .clut_offset = 0x600,
391 },
392 {
393 .name = "overlay1",
394 .formats = &atmel_hlcdc_plane_rgb_formats,
395 .regs_offset = 0x160,
396 .id = 1,
397 .type = ATMEL_HLCDC_OVERLAY_LAYER,
398 .cfgs_offset = 0x2c,
399 .layout = {
400 .pos = 2,
401 .size = 3,
402 .xstride = { 4 },
403 .pstride = { 5 },
404 .default_color = 6,
405 .chroma_key = 7,
406 .chroma_key_mask = 8,
407 .general_config = 9,
408 },
409 .clut_offset = 0xa00,
410 },
411 {
412 .name = "overlay2",
413 .formats = &atmel_hlcdc_plane_rgb_formats,
414 .regs_offset = 0x260,
415 .id = 2,
416 .type = ATMEL_HLCDC_OVERLAY_LAYER,
417 .cfgs_offset = 0x2c,
418 .layout = {
419 .pos = 2,
420 .size = 3,
421 .xstride = { 4 },
422 .pstride = { 5 },
423 .default_color = 6,
424 .chroma_key = 7,
425 .chroma_key_mask = 8,
426 .general_config = 9,
427 },
428 .clut_offset = 0xe00,
429 },
430 {
431 .name = "high-end-overlay",
432 .formats = &atmel_hlcdc_plane_rgb_and_yuv_formats,
433 .regs_offset = 0x360,
434 .id = 3,
435 .type = ATMEL_HLCDC_OVERLAY_LAYER,
436 .cfgs_offset = 0x4c,
437 .layout = {
438 .pos = 2,
439 .size = 3,
440 .memsize = 4,
441 .xstride = { 5, 7 },
442 .pstride = { 6, 8 },
443 .default_color = 9,
444 .chroma_key = 10,
445 .chroma_key_mask = 11,
446 .general_config = 12,
447 .scaler_config = 13,
448 .phicoeffs = {
449 .x = 17,
450 .y = 33,
451 },
452 .csc = 14,
453 },
454 .clut_offset = 0x1200,
455 },
456};
457
458static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_sam9x60 = {
459 .min_width = 0,
460 .min_height = 0,
461 .max_width = 2048,
462 .max_height = 2048,
463 .max_spw = 0xff,
464 .max_vpw = 0xff,
465 .max_hpw = 0x3ff,
466 .fixed_clksrc = true,
467 .nlayers = ARRAY_SIZE(atmel_hlcdc_sam9x60_layers),
468 .layers = atmel_hlcdc_sam9x60_layers,
469 .ops = &atmel_hlcdc_ops,
470};
471
472static const struct atmel_hlcdc_layer_desc atmel_xlcdc_sam9x75_layers[] = {
473 {
474 .name = "base",
475 .formats = &atmel_hlcdc_plane_rgb_formats,
476 .regs_offset = 0x60,
477 .id = 0,
478 .type = ATMEL_HLCDC_BASE_LAYER,
479 .cfgs_offset = 0x1c,
480 .layout = {
481 .xstride = { 2 },
482 .default_color = 3,
483 .general_config = 4,
484 .disc_pos = 5,
485 .disc_size = 6,
486 },
487 .clut_offset = 0x700,
488 },
489 {
490 .name = "overlay1",
491 .formats = &atmel_hlcdc_plane_rgb_formats,
492 .regs_offset = 0x160,
493 .id = 1,
494 .type = ATMEL_HLCDC_OVERLAY_LAYER,
495 .cfgs_offset = 0x1c,
496 .layout = {
497 .pos = 2,
498 .size = 3,
499 .xstride = { 4 },
500 .pstride = { 5 },
501 .default_color = 6,
502 .chroma_key = 7,
503 .chroma_key_mask = 8,
504 .general_config = 9,
505 },
506 .clut_offset = 0xb00,
507 },
508 {
509 .name = "overlay2",
510 .formats = &atmel_hlcdc_plane_rgb_formats,
511 .regs_offset = 0x260,
512 .id = 2,
513 .type = ATMEL_HLCDC_OVERLAY_LAYER,
514 .cfgs_offset = 0x1c,
515 .layout = {
516 .pos = 2,
517 .size = 3,
518 .xstride = { 4 },
519 .pstride = { 5 },
520 .default_color = 6,
521 .chroma_key = 7,
522 .chroma_key_mask = 8,
523 .general_config = 9,
524 },
525 .clut_offset = 0xf00,
526 },
527 {
528 .name = "high-end-overlay",
529 .formats = &atmel_hlcdc_plane_rgb_and_yuv_formats,
530 .regs_offset = 0x360,
531 .id = 3,
532 .type = ATMEL_HLCDC_OVERLAY_LAYER,
533 .cfgs_offset = 0x30,
534 .layout = {
535 .pos = 2,
536 .size = 3,
537 .memsize = 4,
538 .xstride = { 5, 7 },
539 .pstride = { 6, 8 },
540 .default_color = 9,
541 .chroma_key = 10,
542 .chroma_key_mask = 11,
543 .general_config = 12,
544 .csc = 16,
545 .scaler_config = 23,
546 .vxs_config = 30,
547 .hxs_config = 31,
548 },
549 .clut_offset = 0x1300,
550 },
551};
552
553static const struct atmel_hlcdc_dc_desc atmel_xlcdc_dc_sam9x75 = {
554 .min_width = 0,
555 .min_height = 0,
556 .max_width = 2048,
557 .max_height = 2048,
558 .max_spw = 0x3ff,
559 .max_vpw = 0x3ff,
560 .max_hpw = 0x3ff,
561 .fixed_clksrc = true,
562 .is_xlcdc = true,
563 .nlayers = ARRAY_SIZE(atmel_xlcdc_sam9x75_layers),
564 .layers = atmel_xlcdc_sam9x75_layers,
565 .ops = &atmel_xlcdc_ops,
566};
567
568static const struct of_device_id atmel_hlcdc_of_match[] = {
569 {
570 .compatible = "atmel,at91sam9n12-hlcdc",
571 .data = &atmel_hlcdc_dc_at91sam9n12,
572 },
573 {
574 .compatible = "atmel,at91sam9x5-hlcdc",
575 .data = &atmel_hlcdc_dc_at91sam9x5,
576 },
577 {
578 .compatible = "atmel,sama5d2-hlcdc",
579 .data = &atmel_hlcdc_dc_sama5d4,
580 },
581 {
582 .compatible = "atmel,sama5d3-hlcdc",
583 .data = &atmel_hlcdc_dc_sama5d3,
584 },
585 {
586 .compatible = "atmel,sama5d4-hlcdc",
587 .data = &atmel_hlcdc_dc_sama5d4,
588 },
589 {
590 .compatible = "microchip,sam9x60-hlcdc",
591 .data = &atmel_hlcdc_dc_sam9x60,
592 },
593 {
594 .compatible = "microchip,sam9x75-xlcdc",
595 .data = &atmel_xlcdc_dc_sam9x75,
596 },
597 { /* sentinel */ },
598};
599MODULE_DEVICE_TABLE(of, atmel_hlcdc_of_match);
600
601enum drm_mode_status
602atmel_hlcdc_dc_mode_valid(struct atmel_hlcdc_dc *dc,
603 const struct drm_display_mode *mode)
604{
605 int vfront_porch = mode->vsync_start - mode->vdisplay;
606 int vback_porch = mode->vtotal - mode->vsync_end;
607 int vsync_len = mode->vsync_end - mode->vsync_start;
608 int hfront_porch = mode->hsync_start - mode->hdisplay;
609 int hback_porch = mode->htotal - mode->hsync_end;
610 int hsync_len = mode->hsync_end - mode->hsync_start;
611
612 if (hsync_len > dc->desc->max_spw + 1 || hsync_len < 1)
613 return MODE_HSYNC;
614
615 if (vsync_len > dc->desc->max_spw + 1 || vsync_len < 1)
616 return MODE_VSYNC;
617
618 if (hfront_porch > dc->desc->max_hpw + 1 || hfront_porch < 1 ||
619 hback_porch > dc->desc->max_hpw + 1 || hback_porch < 1 ||
620 mode->hdisplay < 1)
621 return MODE_H_ILLEGAL;
622
623 if (vfront_porch > dc->desc->max_vpw + 1 || vfront_porch < 1 ||
624 vback_porch > dc->desc->max_vpw || vback_porch < 0 ||
625 mode->vdisplay < 1)
626 return MODE_V_ILLEGAL;
627
628 return MODE_OK;
629}
630
631static void atmel_hlcdc_layer_irq(struct atmel_hlcdc_layer *layer)
632{
633 if (!layer)
634 return;
635
636 if (layer->desc->type == ATMEL_HLCDC_BASE_LAYER ||
637 layer->desc->type == ATMEL_HLCDC_OVERLAY_LAYER ||
638 layer->desc->type == ATMEL_HLCDC_CURSOR_LAYER)
639 atmel_hlcdc_plane_irq(atmel_hlcdc_layer_to_plane(layer));
640}
641
642static irqreturn_t atmel_hlcdc_dc_irq_handler(int irq, void *data)
643{
644 struct drm_device *dev = data;
645 struct atmel_hlcdc_dc *dc = dev->dev_private;
646 unsigned long status;
647 unsigned int imr, isr;
648 int i;
649
650 regmap_read(dc->hlcdc->regmap, ATMEL_HLCDC_IMR, &imr);
651 regmap_read(dc->hlcdc->regmap, ATMEL_HLCDC_ISR, &isr);
652 status = imr & isr;
653 if (!status)
654 return IRQ_NONE;
655
656 if (status & ATMEL_HLCDC_SOF)
657 atmel_hlcdc_crtc_irq(dc->crtc);
658
659 for (i = 0; i < ATMEL_HLCDC_MAX_LAYERS; i++) {
660 if (ATMEL_HLCDC_LAYER_STATUS(i) & status)
661 atmel_hlcdc_layer_irq(dc->layers[i]);
662 }
663
664 return IRQ_HANDLED;
665}
666
667static void atmel_hlcdc_dc_irq_postinstall(struct drm_device *dev)
668{
669 struct atmel_hlcdc_dc *dc = dev->dev_private;
670 unsigned int cfg = 0;
671 int i;
672
673 /* Enable interrupts on activated layers */
674 for (i = 0; i < ATMEL_HLCDC_MAX_LAYERS; i++) {
675 if (dc->layers[i])
676 cfg |= ATMEL_HLCDC_LAYER_STATUS(i);
677 }
678
679 regmap_write(dc->hlcdc->regmap, ATMEL_HLCDC_IER, cfg);
680}
681
682static void atmel_hlcdc_dc_irq_disable(struct drm_device *dev)
683{
684 struct atmel_hlcdc_dc *dc = dev->dev_private;
685 unsigned int isr;
686
687 regmap_write(dc->hlcdc->regmap, ATMEL_HLCDC_IDR, 0xffffffff);
688 regmap_read(dc->hlcdc->regmap, ATMEL_HLCDC_ISR, &isr);
689}
690
691static int atmel_hlcdc_dc_irq_install(struct drm_device *dev, unsigned int irq)
692{
693 int ret;
694
695 atmel_hlcdc_dc_irq_disable(dev);
696
697 ret = devm_request_irq(dev->dev, irq, atmel_hlcdc_dc_irq_handler, 0,
698 dev->driver->name, dev);
699 if (ret)
700 return ret;
701
702 atmel_hlcdc_dc_irq_postinstall(dev);
703
704 return 0;
705}
706
707static void atmel_hlcdc_dc_irq_uninstall(struct drm_device *dev)
708{
709 atmel_hlcdc_dc_irq_disable(dev);
710}
711
712static const struct drm_mode_config_funcs mode_config_funcs = {
713 .fb_create = drm_gem_fb_create,
714 .atomic_check = drm_atomic_helper_check,
715 .atomic_commit = drm_atomic_helper_commit,
716};
717
718static int atmel_hlcdc_dc_modeset_init(struct drm_device *dev)
719{
720 struct atmel_hlcdc_dc *dc = dev->dev_private;
721 int ret;
722
723 drm_mode_config_init(dev);
724
725 ret = atmel_hlcdc_create_outputs(dev);
726 if (ret) {
727 dev_err(dev->dev, "failed to create HLCDC outputs: %d\n", ret);
728 return ret;
729 }
730
731 ret = atmel_hlcdc_create_planes(dev);
732 if (ret) {
733 dev_err(dev->dev, "failed to create planes: %d\n", ret);
734 return ret;
735 }
736
737 ret = atmel_hlcdc_crtc_create(dev);
738 if (ret) {
739 dev_err(dev->dev, "failed to create crtc\n");
740 return ret;
741 }
742
743 dev->mode_config.min_width = dc->desc->min_width;
744 dev->mode_config.min_height = dc->desc->min_height;
745 dev->mode_config.max_width = dc->desc->max_width;
746 dev->mode_config.max_height = dc->desc->max_height;
747 dev->mode_config.funcs = &mode_config_funcs;
748 dev->mode_config.async_page_flip = true;
749
750 return 0;
751}
752
753static int atmel_hlcdc_dc_load(struct drm_device *dev)
754{
755 struct platform_device *pdev = to_platform_device(dev->dev);
756 const struct of_device_id *match;
757 struct atmel_hlcdc_dc *dc;
758 int ret;
759
760 match = of_match_node(atmel_hlcdc_of_match, dev->dev->parent->of_node);
761 if (!match) {
762 dev_err(&pdev->dev, "invalid compatible string\n");
763 return -ENODEV;
764 }
765
766 if (!match->data) {
767 dev_err(&pdev->dev, "invalid hlcdc description\n");
768 return -EINVAL;
769 }
770
771 dc = devm_kzalloc(dev->dev, sizeof(*dc), GFP_KERNEL);
772 if (!dc)
773 return -ENOMEM;
774
775 dc->desc = match->data;
776 dc->hlcdc = dev_get_drvdata(dev->dev->parent);
777 dev->dev_private = dc;
778
779 ret = clk_prepare_enable(dc->hlcdc->periph_clk);
780 if (ret) {
781 dev_err(dev->dev, "failed to enable periph_clk\n");
782 return ret;
783 }
784
785 pm_runtime_enable(dev->dev);
786
787 ret = drm_vblank_init(dev, 1);
788 if (ret < 0) {
789 dev_err(dev->dev, "failed to initialize vblank\n");
790 goto err_periph_clk_disable;
791 }
792
793 ret = atmel_hlcdc_dc_modeset_init(dev);
794 if (ret < 0) {
795 dev_err(dev->dev, "failed to initialize mode setting\n");
796 goto err_periph_clk_disable;
797 }
798
799 drm_mode_config_reset(dev);
800
801 pm_runtime_get_sync(dev->dev);
802 ret = atmel_hlcdc_dc_irq_install(dev, dc->hlcdc->irq);
803 pm_runtime_put_sync(dev->dev);
804 if (ret < 0) {
805 dev_err(dev->dev, "failed to install IRQ handler\n");
806 goto err_periph_clk_disable;
807 }
808
809 platform_set_drvdata(pdev, dev);
810
811 drm_kms_helper_poll_init(dev);
812
813 return 0;
814
815err_periph_clk_disable:
816 pm_runtime_disable(dev->dev);
817 clk_disable_unprepare(dc->hlcdc->periph_clk);
818
819 return ret;
820}
821
822static void atmel_hlcdc_dc_unload(struct drm_device *dev)
823{
824 struct atmel_hlcdc_dc *dc = dev->dev_private;
825
826 drm_kms_helper_poll_fini(dev);
827 drm_atomic_helper_shutdown(dev);
828 drm_mode_config_cleanup(dev);
829
830 pm_runtime_get_sync(dev->dev);
831 atmel_hlcdc_dc_irq_uninstall(dev);
832 pm_runtime_put_sync(dev->dev);
833
834 dev->dev_private = NULL;
835
836 pm_runtime_disable(dev->dev);
837 clk_disable_unprepare(dc->hlcdc->periph_clk);
838}
839
840DEFINE_DRM_GEM_DMA_FOPS(fops);
841
842static const struct drm_driver atmel_hlcdc_dc_driver = {
843 .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
844 DRM_GEM_DMA_DRIVER_OPS,
845 DRM_FBDEV_DMA_DRIVER_OPS,
846 .fops = &fops,
847 .name = "atmel-hlcdc",
848 .desc = "Atmel HLCD Controller DRM",
849 .date = "20141504",
850 .major = 1,
851 .minor = 0,
852};
853
854static int atmel_hlcdc_dc_drm_probe(struct platform_device *pdev)
855{
856 struct drm_device *ddev;
857 int ret;
858
859 ddev = drm_dev_alloc(&atmel_hlcdc_dc_driver, &pdev->dev);
860 if (IS_ERR(ddev))
861 return PTR_ERR(ddev);
862
863 ret = atmel_hlcdc_dc_load(ddev);
864 if (ret)
865 goto err_put;
866
867 ret = drm_dev_register(ddev, 0);
868 if (ret)
869 goto err_unload;
870
871 drm_client_setup_with_fourcc(ddev, DRM_FORMAT_RGB888);
872
873 return 0;
874
875err_unload:
876 atmel_hlcdc_dc_unload(ddev);
877
878err_put:
879 drm_dev_put(ddev);
880
881 return ret;
882}
883
884static void atmel_hlcdc_dc_drm_remove(struct platform_device *pdev)
885{
886 struct drm_device *ddev = platform_get_drvdata(pdev);
887
888 drm_dev_unregister(ddev);
889 atmel_hlcdc_dc_unload(ddev);
890 drm_dev_put(ddev);
891}
892
893static void atmel_hlcdc_dc_drm_shutdown(struct platform_device *pdev)
894{
895 drm_atomic_helper_shutdown(platform_get_drvdata(pdev));
896}
897
898static int atmel_hlcdc_dc_drm_suspend(struct device *dev)
899{
900 struct drm_device *drm_dev = dev_get_drvdata(dev);
901 struct atmel_hlcdc_dc *dc = drm_dev->dev_private;
902 struct regmap *regmap = dc->hlcdc->regmap;
903 struct drm_atomic_state *state;
904
905 state = drm_atomic_helper_suspend(drm_dev);
906 if (IS_ERR(state))
907 return PTR_ERR(state);
908
909 dc->suspend.state = state;
910
911 regmap_read(regmap, ATMEL_HLCDC_IMR, &dc->suspend.imr);
912 regmap_write(regmap, ATMEL_HLCDC_IDR, dc->suspend.imr);
913 clk_disable_unprepare(dc->hlcdc->periph_clk);
914
915 return 0;
916}
917
918static int atmel_hlcdc_dc_drm_resume(struct device *dev)
919{
920 struct drm_device *drm_dev = dev_get_drvdata(dev);
921 struct atmel_hlcdc_dc *dc = drm_dev->dev_private;
922
923 clk_prepare_enable(dc->hlcdc->periph_clk);
924 regmap_write(dc->hlcdc->regmap, ATMEL_HLCDC_IER, dc->suspend.imr);
925
926 return drm_atomic_helper_resume(drm_dev, dc->suspend.state);
927}
928
929static DEFINE_SIMPLE_DEV_PM_OPS(atmel_hlcdc_dc_drm_pm_ops,
930 atmel_hlcdc_dc_drm_suspend,
931 atmel_hlcdc_dc_drm_resume);
932
933static const struct of_device_id atmel_hlcdc_dc_of_match[] = {
934 { .compatible = "atmel,hlcdc-display-controller" },
935 { },
936};
937
938static struct platform_driver atmel_hlcdc_dc_platform_driver = {
939 .probe = atmel_hlcdc_dc_drm_probe,
940 .remove = atmel_hlcdc_dc_drm_remove,
941 .shutdown = atmel_hlcdc_dc_drm_shutdown,
942 .driver = {
943 .name = "atmel-hlcdc-display-controller",
944 .pm = pm_sleep_ptr(&atmel_hlcdc_dc_drm_pm_ops),
945 .of_match_table = atmel_hlcdc_dc_of_match,
946 },
947};
948drm_module_platform_driver(atmel_hlcdc_dc_platform_driver);
949
950MODULE_AUTHOR("Jean-Jacques Hiblot <jjhiblot@traphandler.com>");
951MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com>");
952MODULE_DESCRIPTION("Atmel HLCDC Display Controller DRM Driver");
953MODULE_LICENSE("GPL");
954MODULE_ALIAS("platform:atmel-hlcdc-dc");
1/*
2 * Copyright (C) 2014 Traphandler
3 * Copyright (C) 2014 Free Electrons
4 * Copyright (C) 2014 Atmel
5 *
6 * Author: Jean-Jacques Hiblot <jjhiblot@traphandler.com>
7 * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22#include <linux/clk.h>
23#include <linux/irq.h>
24#include <linux/irqchip.h>
25#include <linux/module.h>
26#include <linux/pm_runtime.h>
27
28#include "atmel_hlcdc_dc.h"
29
30#define ATMEL_HLCDC_LAYER_IRQS_OFFSET 8
31
32static const struct atmel_hlcdc_layer_desc atmel_hlcdc_at91sam9n12_layers[] = {
33 {
34 .name = "base",
35 .formats = &atmel_hlcdc_plane_rgb_formats,
36 .regs_offset = 0x40,
37 .id = 0,
38 .type = ATMEL_HLCDC_BASE_LAYER,
39 .nconfigs = 5,
40 .layout = {
41 .xstride = { 2 },
42 .default_color = 3,
43 .general_config = 4,
44 },
45 },
46};
47
48static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_at91sam9n12 = {
49 .min_width = 0,
50 .min_height = 0,
51 .max_width = 1280,
52 .max_height = 860,
53 .max_spw = 0x3f,
54 .max_vpw = 0x3f,
55 .max_hpw = 0xff,
56 .conflicting_output_formats = true,
57 .nlayers = ARRAY_SIZE(atmel_hlcdc_at91sam9n12_layers),
58 .layers = atmel_hlcdc_at91sam9n12_layers,
59};
60
61static const struct atmel_hlcdc_layer_desc atmel_hlcdc_at91sam9x5_layers[] = {
62 {
63 .name = "base",
64 .formats = &atmel_hlcdc_plane_rgb_formats,
65 .regs_offset = 0x40,
66 .id = 0,
67 .type = ATMEL_HLCDC_BASE_LAYER,
68 .nconfigs = 5,
69 .layout = {
70 .xstride = { 2 },
71 .default_color = 3,
72 .general_config = 4,
73 .disc_pos = 5,
74 .disc_size = 6,
75 },
76 },
77 {
78 .name = "overlay1",
79 .formats = &atmel_hlcdc_plane_rgb_formats,
80 .regs_offset = 0x100,
81 .id = 1,
82 .type = ATMEL_HLCDC_OVERLAY_LAYER,
83 .nconfigs = 10,
84 .layout = {
85 .pos = 2,
86 .size = 3,
87 .xstride = { 4 },
88 .pstride = { 5 },
89 .default_color = 6,
90 .chroma_key = 7,
91 .chroma_key_mask = 8,
92 .general_config = 9,
93 },
94 },
95 {
96 .name = "high-end-overlay",
97 .formats = &atmel_hlcdc_plane_rgb_and_yuv_formats,
98 .regs_offset = 0x280,
99 .id = 2,
100 .type = ATMEL_HLCDC_OVERLAY_LAYER,
101 .nconfigs = 17,
102 .layout = {
103 .pos = 2,
104 .size = 3,
105 .memsize = 4,
106 .xstride = { 5, 7 },
107 .pstride = { 6, 8 },
108 .default_color = 9,
109 .chroma_key = 10,
110 .chroma_key_mask = 11,
111 .general_config = 12,
112 .csc = 14,
113 },
114 },
115 {
116 .name = "cursor",
117 .formats = &atmel_hlcdc_plane_rgb_formats,
118 .regs_offset = 0x340,
119 .id = 3,
120 .type = ATMEL_HLCDC_CURSOR_LAYER,
121 .nconfigs = 10,
122 .max_width = 128,
123 .max_height = 128,
124 .layout = {
125 .pos = 2,
126 .size = 3,
127 .xstride = { 4 },
128 .default_color = 6,
129 .chroma_key = 7,
130 .chroma_key_mask = 8,
131 .general_config = 9,
132 },
133 },
134};
135
136static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_at91sam9x5 = {
137 .min_width = 0,
138 .min_height = 0,
139 .max_width = 800,
140 .max_height = 600,
141 .max_spw = 0x3f,
142 .max_vpw = 0x3f,
143 .max_hpw = 0xff,
144 .conflicting_output_formats = true,
145 .nlayers = ARRAY_SIZE(atmel_hlcdc_at91sam9x5_layers),
146 .layers = atmel_hlcdc_at91sam9x5_layers,
147};
148
149static const struct atmel_hlcdc_layer_desc atmel_hlcdc_sama5d3_layers[] = {
150 {
151 .name = "base",
152 .formats = &atmel_hlcdc_plane_rgb_formats,
153 .regs_offset = 0x40,
154 .id = 0,
155 .type = ATMEL_HLCDC_BASE_LAYER,
156 .nconfigs = 7,
157 .layout = {
158 .xstride = { 2 },
159 .default_color = 3,
160 .general_config = 4,
161 .disc_pos = 5,
162 .disc_size = 6,
163 },
164 },
165 {
166 .name = "overlay1",
167 .formats = &atmel_hlcdc_plane_rgb_formats,
168 .regs_offset = 0x140,
169 .id = 1,
170 .type = ATMEL_HLCDC_OVERLAY_LAYER,
171 .nconfigs = 10,
172 .layout = {
173 .pos = 2,
174 .size = 3,
175 .xstride = { 4 },
176 .pstride = { 5 },
177 .default_color = 6,
178 .chroma_key = 7,
179 .chroma_key_mask = 8,
180 .general_config = 9,
181 },
182 },
183 {
184 .name = "overlay2",
185 .formats = &atmel_hlcdc_plane_rgb_formats,
186 .regs_offset = 0x240,
187 .id = 2,
188 .type = ATMEL_HLCDC_OVERLAY_LAYER,
189 .nconfigs = 10,
190 .layout = {
191 .pos = 2,
192 .size = 3,
193 .xstride = { 4 },
194 .pstride = { 5 },
195 .default_color = 6,
196 .chroma_key = 7,
197 .chroma_key_mask = 8,
198 .general_config = 9,
199 },
200 },
201 {
202 .name = "high-end-overlay",
203 .formats = &atmel_hlcdc_plane_rgb_and_yuv_formats,
204 .regs_offset = 0x340,
205 .id = 3,
206 .type = ATMEL_HLCDC_OVERLAY_LAYER,
207 .nconfigs = 42,
208 .layout = {
209 .pos = 2,
210 .size = 3,
211 .memsize = 4,
212 .xstride = { 5, 7 },
213 .pstride = { 6, 8 },
214 .default_color = 9,
215 .chroma_key = 10,
216 .chroma_key_mask = 11,
217 .general_config = 12,
218 .csc = 14,
219 },
220 },
221 {
222 .name = "cursor",
223 .formats = &atmel_hlcdc_plane_rgb_formats,
224 .regs_offset = 0x440,
225 .id = 4,
226 .type = ATMEL_HLCDC_CURSOR_LAYER,
227 .nconfigs = 10,
228 .max_width = 128,
229 .max_height = 128,
230 .layout = {
231 .pos = 2,
232 .size = 3,
233 .xstride = { 4 },
234 .pstride = { 5 },
235 .default_color = 6,
236 .chroma_key = 7,
237 .chroma_key_mask = 8,
238 .general_config = 9,
239 },
240 },
241};
242
243static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_sama5d3 = {
244 .min_width = 0,
245 .min_height = 0,
246 .max_width = 2048,
247 .max_height = 2048,
248 .max_spw = 0x3f,
249 .max_vpw = 0x3f,
250 .max_hpw = 0x1ff,
251 .conflicting_output_formats = true,
252 .nlayers = ARRAY_SIZE(atmel_hlcdc_sama5d3_layers),
253 .layers = atmel_hlcdc_sama5d3_layers,
254};
255
256static const struct atmel_hlcdc_layer_desc atmel_hlcdc_sama5d4_layers[] = {
257 {
258 .name = "base",
259 .formats = &atmel_hlcdc_plane_rgb_formats,
260 .regs_offset = 0x40,
261 .id = 0,
262 .type = ATMEL_HLCDC_BASE_LAYER,
263 .nconfigs = 7,
264 .layout = {
265 .xstride = { 2 },
266 .default_color = 3,
267 .general_config = 4,
268 .disc_pos = 5,
269 .disc_size = 6,
270 },
271 },
272 {
273 .name = "overlay1",
274 .formats = &atmel_hlcdc_plane_rgb_formats,
275 .regs_offset = 0x140,
276 .id = 1,
277 .type = ATMEL_HLCDC_OVERLAY_LAYER,
278 .nconfigs = 10,
279 .layout = {
280 .pos = 2,
281 .size = 3,
282 .xstride = { 4 },
283 .pstride = { 5 },
284 .default_color = 6,
285 .chroma_key = 7,
286 .chroma_key_mask = 8,
287 .general_config = 9,
288 },
289 },
290 {
291 .name = "overlay2",
292 .formats = &atmel_hlcdc_plane_rgb_formats,
293 .regs_offset = 0x240,
294 .id = 2,
295 .type = ATMEL_HLCDC_OVERLAY_LAYER,
296 .nconfigs = 10,
297 .layout = {
298 .pos = 2,
299 .size = 3,
300 .xstride = { 4 },
301 .pstride = { 5 },
302 .default_color = 6,
303 .chroma_key = 7,
304 .chroma_key_mask = 8,
305 .general_config = 9,
306 },
307 },
308 {
309 .name = "high-end-overlay",
310 .formats = &atmel_hlcdc_plane_rgb_and_yuv_formats,
311 .regs_offset = 0x340,
312 .id = 3,
313 .type = ATMEL_HLCDC_OVERLAY_LAYER,
314 .nconfigs = 42,
315 .layout = {
316 .pos = 2,
317 .size = 3,
318 .memsize = 4,
319 .xstride = { 5, 7 },
320 .pstride = { 6, 8 },
321 .default_color = 9,
322 .chroma_key = 10,
323 .chroma_key_mask = 11,
324 .general_config = 12,
325 .csc = 14,
326 },
327 },
328};
329
330static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_sama5d4 = {
331 .min_width = 0,
332 .min_height = 0,
333 .max_width = 2048,
334 .max_height = 2048,
335 .max_spw = 0xff,
336 .max_vpw = 0xff,
337 .max_hpw = 0x3ff,
338 .nlayers = ARRAY_SIZE(atmel_hlcdc_sama5d4_layers),
339 .layers = atmel_hlcdc_sama5d4_layers,
340};
341static const struct of_device_id atmel_hlcdc_of_match[] = {
342 {
343 .compatible = "atmel,at91sam9n12-hlcdc",
344 .data = &atmel_hlcdc_dc_at91sam9n12,
345 },
346 {
347 .compatible = "atmel,at91sam9x5-hlcdc",
348 .data = &atmel_hlcdc_dc_at91sam9x5,
349 },
350 {
351 .compatible = "atmel,sama5d2-hlcdc",
352 .data = &atmel_hlcdc_dc_sama5d4,
353 },
354 {
355 .compatible = "atmel,sama5d3-hlcdc",
356 .data = &atmel_hlcdc_dc_sama5d3,
357 },
358 {
359 .compatible = "atmel,sama5d4-hlcdc",
360 .data = &atmel_hlcdc_dc_sama5d4,
361 },
362 { /* sentinel */ },
363};
364MODULE_DEVICE_TABLE(of, atmel_hlcdc_of_match);
365
366int atmel_hlcdc_dc_mode_valid(struct atmel_hlcdc_dc *dc,
367 struct drm_display_mode *mode)
368{
369 int vfront_porch = mode->vsync_start - mode->vdisplay;
370 int vback_porch = mode->vtotal - mode->vsync_end;
371 int vsync_len = mode->vsync_end - mode->vsync_start;
372 int hfront_porch = mode->hsync_start - mode->hdisplay;
373 int hback_porch = mode->htotal - mode->hsync_end;
374 int hsync_len = mode->hsync_end - mode->hsync_start;
375
376 if (hsync_len > dc->desc->max_spw + 1 || hsync_len < 1)
377 return MODE_HSYNC;
378
379 if (vsync_len > dc->desc->max_spw + 1 || vsync_len < 1)
380 return MODE_VSYNC;
381
382 if (hfront_porch > dc->desc->max_hpw + 1 || hfront_porch < 1 ||
383 hback_porch > dc->desc->max_hpw + 1 || hback_porch < 1 ||
384 mode->hdisplay < 1)
385 return MODE_H_ILLEGAL;
386
387 if (vfront_porch > dc->desc->max_vpw + 1 || vfront_porch < 1 ||
388 vback_porch > dc->desc->max_vpw || vback_porch < 0 ||
389 mode->vdisplay < 1)
390 return MODE_V_ILLEGAL;
391
392 return MODE_OK;
393}
394
395static irqreturn_t atmel_hlcdc_dc_irq_handler(int irq, void *data)
396{
397 struct drm_device *dev = data;
398 struct atmel_hlcdc_dc *dc = dev->dev_private;
399 unsigned long status;
400 unsigned int imr, isr;
401 int i;
402
403 regmap_read(dc->hlcdc->regmap, ATMEL_HLCDC_IMR, &imr);
404 regmap_read(dc->hlcdc->regmap, ATMEL_HLCDC_ISR, &isr);
405 status = imr & isr;
406 if (!status)
407 return IRQ_NONE;
408
409 if (status & ATMEL_HLCDC_SOF)
410 atmel_hlcdc_crtc_irq(dc->crtc);
411
412 for (i = 0; i < ATMEL_HLCDC_MAX_LAYERS; i++) {
413 struct atmel_hlcdc_layer *layer = dc->layers[i];
414
415 if (!(ATMEL_HLCDC_LAYER_STATUS(i) & status) || !layer)
416 continue;
417
418 atmel_hlcdc_layer_irq(layer);
419 }
420
421 return IRQ_HANDLED;
422}
423
424static struct drm_framebuffer *atmel_hlcdc_fb_create(struct drm_device *dev,
425 struct drm_file *file_priv, const struct drm_mode_fb_cmd2 *mode_cmd)
426{
427 return drm_fb_cma_create(dev, file_priv, mode_cmd);
428}
429
430static void atmel_hlcdc_fb_output_poll_changed(struct drm_device *dev)
431{
432 struct atmel_hlcdc_dc *dc = dev->dev_private;
433
434 if (dc->fbdev) {
435 drm_fbdev_cma_hotplug_event(dc->fbdev);
436 } else {
437 dc->fbdev = drm_fbdev_cma_init(dev, 24,
438 dev->mode_config.num_crtc,
439 dev->mode_config.num_connector);
440 if (IS_ERR(dc->fbdev))
441 dc->fbdev = NULL;
442 }
443}
444
445struct atmel_hlcdc_dc_commit {
446 struct work_struct work;
447 struct drm_device *dev;
448 struct drm_atomic_state *state;
449};
450
451static void
452atmel_hlcdc_dc_atomic_complete(struct atmel_hlcdc_dc_commit *commit)
453{
454 struct drm_device *dev = commit->dev;
455 struct atmel_hlcdc_dc *dc = dev->dev_private;
456 struct drm_atomic_state *old_state = commit->state;
457
458 /* Apply the atomic update. */
459 drm_atomic_helper_commit_modeset_disables(dev, old_state);
460 drm_atomic_helper_commit_planes(dev, old_state, 0);
461 drm_atomic_helper_commit_modeset_enables(dev, old_state);
462
463 drm_atomic_helper_wait_for_vblanks(dev, old_state);
464
465 drm_atomic_helper_cleanup_planes(dev, old_state);
466
467 drm_atomic_state_put(old_state);
468
469 /* Complete the commit, wake up any waiter. */
470 spin_lock(&dc->commit.wait.lock);
471 dc->commit.pending = false;
472 wake_up_all_locked(&dc->commit.wait);
473 spin_unlock(&dc->commit.wait.lock);
474
475 kfree(commit);
476}
477
478static void atmel_hlcdc_dc_atomic_work(struct work_struct *work)
479{
480 struct atmel_hlcdc_dc_commit *commit =
481 container_of(work, struct atmel_hlcdc_dc_commit, work);
482
483 atmel_hlcdc_dc_atomic_complete(commit);
484}
485
486static int atmel_hlcdc_dc_atomic_commit(struct drm_device *dev,
487 struct drm_atomic_state *state,
488 bool async)
489{
490 struct atmel_hlcdc_dc *dc = dev->dev_private;
491 struct atmel_hlcdc_dc_commit *commit;
492 int ret;
493
494 ret = drm_atomic_helper_prepare_planes(dev, state);
495 if (ret)
496 return ret;
497
498 /* Allocate the commit object. */
499 commit = kzalloc(sizeof(*commit), GFP_KERNEL);
500 if (!commit) {
501 ret = -ENOMEM;
502 goto error;
503 }
504
505 INIT_WORK(&commit->work, atmel_hlcdc_dc_atomic_work);
506 commit->dev = dev;
507 commit->state = state;
508
509 spin_lock(&dc->commit.wait.lock);
510 ret = wait_event_interruptible_locked(dc->commit.wait,
511 !dc->commit.pending);
512 if (ret == 0)
513 dc->commit.pending = true;
514 spin_unlock(&dc->commit.wait.lock);
515
516 if (ret) {
517 kfree(commit);
518 goto error;
519 }
520
521 /* Swap the state, this is the point of no return. */
522 drm_atomic_helper_swap_state(state, true);
523
524 drm_atomic_state_get(state);
525 if (async)
526 queue_work(dc->wq, &commit->work);
527 else
528 atmel_hlcdc_dc_atomic_complete(commit);
529
530 return 0;
531
532error:
533 drm_atomic_helper_cleanup_planes(dev, state);
534 return ret;
535}
536
537static const struct drm_mode_config_funcs mode_config_funcs = {
538 .fb_create = atmel_hlcdc_fb_create,
539 .output_poll_changed = atmel_hlcdc_fb_output_poll_changed,
540 .atomic_check = drm_atomic_helper_check,
541 .atomic_commit = atmel_hlcdc_dc_atomic_commit,
542};
543
544static int atmel_hlcdc_dc_modeset_init(struct drm_device *dev)
545{
546 struct atmel_hlcdc_dc *dc = dev->dev_private;
547 struct atmel_hlcdc_planes *planes;
548 int ret;
549 int i;
550
551 drm_mode_config_init(dev);
552
553 ret = atmel_hlcdc_create_outputs(dev);
554 if (ret) {
555 dev_err(dev->dev, "failed to create HLCDC outputs: %d\n", ret);
556 return ret;
557 }
558
559 planes = atmel_hlcdc_create_planes(dev);
560 if (IS_ERR(planes)) {
561 dev_err(dev->dev, "failed to create planes\n");
562 return PTR_ERR(planes);
563 }
564
565 dc->planes = planes;
566
567 dc->layers[planes->primary->layer.desc->id] =
568 &planes->primary->layer;
569
570 if (planes->cursor)
571 dc->layers[planes->cursor->layer.desc->id] =
572 &planes->cursor->layer;
573
574 for (i = 0; i < planes->noverlays; i++)
575 dc->layers[planes->overlays[i]->layer.desc->id] =
576 &planes->overlays[i]->layer;
577
578 ret = atmel_hlcdc_crtc_create(dev);
579 if (ret) {
580 dev_err(dev->dev, "failed to create crtc\n");
581 return ret;
582 }
583
584 dev->mode_config.min_width = dc->desc->min_width;
585 dev->mode_config.min_height = dc->desc->min_height;
586 dev->mode_config.max_width = dc->desc->max_width;
587 dev->mode_config.max_height = dc->desc->max_height;
588 dev->mode_config.funcs = &mode_config_funcs;
589
590 return 0;
591}
592
593static int atmel_hlcdc_dc_load(struct drm_device *dev)
594{
595 struct platform_device *pdev = to_platform_device(dev->dev);
596 const struct of_device_id *match;
597 struct atmel_hlcdc_dc *dc;
598 int ret;
599
600 match = of_match_node(atmel_hlcdc_of_match, dev->dev->parent->of_node);
601 if (!match) {
602 dev_err(&pdev->dev, "invalid compatible string\n");
603 return -ENODEV;
604 }
605
606 if (!match->data) {
607 dev_err(&pdev->dev, "invalid hlcdc description\n");
608 return -EINVAL;
609 }
610
611 dc = devm_kzalloc(dev->dev, sizeof(*dc), GFP_KERNEL);
612 if (!dc)
613 return -ENOMEM;
614
615 dc->wq = alloc_ordered_workqueue("atmel-hlcdc-dc", 0);
616 if (!dc->wq)
617 return -ENOMEM;
618
619 init_waitqueue_head(&dc->commit.wait);
620 dc->desc = match->data;
621 dc->hlcdc = dev_get_drvdata(dev->dev->parent);
622 dev->dev_private = dc;
623
624 ret = clk_prepare_enable(dc->hlcdc->periph_clk);
625 if (ret) {
626 dev_err(dev->dev, "failed to enable periph_clk\n");
627 goto err_destroy_wq;
628 }
629
630 pm_runtime_enable(dev->dev);
631
632 ret = drm_vblank_init(dev, 1);
633 if (ret < 0) {
634 dev_err(dev->dev, "failed to initialize vblank\n");
635 goto err_periph_clk_disable;
636 }
637
638 ret = atmel_hlcdc_dc_modeset_init(dev);
639 if (ret < 0) {
640 dev_err(dev->dev, "failed to initialize mode setting\n");
641 goto err_periph_clk_disable;
642 }
643
644 drm_mode_config_reset(dev);
645
646 pm_runtime_get_sync(dev->dev);
647 ret = drm_irq_install(dev, dc->hlcdc->irq);
648 pm_runtime_put_sync(dev->dev);
649 if (ret < 0) {
650 dev_err(dev->dev, "failed to install IRQ handler\n");
651 goto err_periph_clk_disable;
652 }
653
654 platform_set_drvdata(pdev, dev);
655
656 drm_kms_helper_poll_init(dev);
657
658 /* force connectors detection */
659 drm_helper_hpd_irq_event(dev);
660
661 return 0;
662
663err_periph_clk_disable:
664 pm_runtime_disable(dev->dev);
665 clk_disable_unprepare(dc->hlcdc->periph_clk);
666
667err_destroy_wq:
668 destroy_workqueue(dc->wq);
669
670 return ret;
671}
672
673static void atmel_hlcdc_dc_unload(struct drm_device *dev)
674{
675 struct atmel_hlcdc_dc *dc = dev->dev_private;
676
677 if (dc->fbdev)
678 drm_fbdev_cma_fini(dc->fbdev);
679 flush_workqueue(dc->wq);
680 drm_kms_helper_poll_fini(dev);
681 drm_mode_config_cleanup(dev);
682 drm_vblank_cleanup(dev);
683
684 pm_runtime_get_sync(dev->dev);
685 drm_irq_uninstall(dev);
686 pm_runtime_put_sync(dev->dev);
687
688 dev->dev_private = NULL;
689
690 pm_runtime_disable(dev->dev);
691 clk_disable_unprepare(dc->hlcdc->periph_clk);
692 destroy_workqueue(dc->wq);
693}
694
695static void atmel_hlcdc_dc_lastclose(struct drm_device *dev)
696{
697 struct atmel_hlcdc_dc *dc = dev->dev_private;
698
699 drm_fbdev_cma_restore_mode(dc->fbdev);
700}
701
702static int atmel_hlcdc_dc_irq_postinstall(struct drm_device *dev)
703{
704 struct atmel_hlcdc_dc *dc = dev->dev_private;
705 unsigned int cfg = 0;
706 int i;
707
708 /* Enable interrupts on activated layers */
709 for (i = 0; i < ATMEL_HLCDC_MAX_LAYERS; i++) {
710 if (dc->layers[i])
711 cfg |= ATMEL_HLCDC_LAYER_STATUS(i);
712 }
713
714 regmap_write(dc->hlcdc->regmap, ATMEL_HLCDC_IER, cfg);
715
716 return 0;
717}
718
719static void atmel_hlcdc_dc_irq_uninstall(struct drm_device *dev)
720{
721 struct atmel_hlcdc_dc *dc = dev->dev_private;
722 unsigned int isr;
723
724 regmap_write(dc->hlcdc->regmap, ATMEL_HLCDC_IDR, 0xffffffff);
725 regmap_read(dc->hlcdc->regmap, ATMEL_HLCDC_ISR, &isr);
726}
727
728static int atmel_hlcdc_dc_enable_vblank(struct drm_device *dev,
729 unsigned int pipe)
730{
731 struct atmel_hlcdc_dc *dc = dev->dev_private;
732
733 /* Enable SOF (Start Of Frame) interrupt for vblank counting */
734 regmap_write(dc->hlcdc->regmap, ATMEL_HLCDC_IER, ATMEL_HLCDC_SOF);
735
736 return 0;
737}
738
739static void atmel_hlcdc_dc_disable_vblank(struct drm_device *dev,
740 unsigned int pipe)
741{
742 struct atmel_hlcdc_dc *dc = dev->dev_private;
743
744 regmap_write(dc->hlcdc->regmap, ATMEL_HLCDC_IDR, ATMEL_HLCDC_SOF);
745}
746
747static const struct file_operations fops = {
748 .owner = THIS_MODULE,
749 .open = drm_open,
750 .release = drm_release,
751 .unlocked_ioctl = drm_ioctl,
752 .compat_ioctl = drm_compat_ioctl,
753 .poll = drm_poll,
754 .read = drm_read,
755 .llseek = no_llseek,
756 .mmap = drm_gem_cma_mmap,
757};
758
759static struct drm_driver atmel_hlcdc_dc_driver = {
760 .driver_features = DRIVER_HAVE_IRQ | DRIVER_GEM |
761 DRIVER_MODESET | DRIVER_PRIME |
762 DRIVER_ATOMIC,
763 .lastclose = atmel_hlcdc_dc_lastclose,
764 .irq_handler = atmel_hlcdc_dc_irq_handler,
765 .irq_preinstall = atmel_hlcdc_dc_irq_uninstall,
766 .irq_postinstall = atmel_hlcdc_dc_irq_postinstall,
767 .irq_uninstall = atmel_hlcdc_dc_irq_uninstall,
768 .get_vblank_counter = drm_vblank_no_hw_counter,
769 .enable_vblank = atmel_hlcdc_dc_enable_vblank,
770 .disable_vblank = atmel_hlcdc_dc_disable_vblank,
771 .gem_free_object_unlocked = drm_gem_cma_free_object,
772 .gem_vm_ops = &drm_gem_cma_vm_ops,
773 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
774 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
775 .gem_prime_import = drm_gem_prime_import,
776 .gem_prime_export = drm_gem_prime_export,
777 .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
778 .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
779 .gem_prime_vmap = drm_gem_cma_prime_vmap,
780 .gem_prime_vunmap = drm_gem_cma_prime_vunmap,
781 .gem_prime_mmap = drm_gem_cma_prime_mmap,
782 .dumb_create = drm_gem_cma_dumb_create,
783 .dumb_map_offset = drm_gem_cma_dumb_map_offset,
784 .dumb_destroy = drm_gem_dumb_destroy,
785 .fops = &fops,
786 .name = "atmel-hlcdc",
787 .desc = "Atmel HLCD Controller DRM",
788 .date = "20141504",
789 .major = 1,
790 .minor = 0,
791};
792
793static int atmel_hlcdc_dc_drm_probe(struct platform_device *pdev)
794{
795 struct drm_device *ddev;
796 int ret;
797
798 ddev = drm_dev_alloc(&atmel_hlcdc_dc_driver, &pdev->dev);
799 if (IS_ERR(ddev))
800 return PTR_ERR(ddev);
801
802 ret = atmel_hlcdc_dc_load(ddev);
803 if (ret)
804 goto err_unref;
805
806 ret = drm_dev_register(ddev, 0);
807 if (ret)
808 goto err_unload;
809
810 return 0;
811
812err_unload:
813 atmel_hlcdc_dc_unload(ddev);
814
815err_unref:
816 drm_dev_unref(ddev);
817
818 return ret;
819}
820
821static int atmel_hlcdc_dc_drm_remove(struct platform_device *pdev)
822{
823 struct drm_device *ddev = platform_get_drvdata(pdev);
824
825 drm_dev_unregister(ddev);
826 atmel_hlcdc_dc_unload(ddev);
827 drm_dev_unref(ddev);
828
829 return 0;
830}
831
832#ifdef CONFIG_PM_SLEEP
833static int atmel_hlcdc_dc_drm_suspend(struct device *dev)
834{
835 struct drm_device *drm_dev = dev_get_drvdata(dev);
836 struct drm_crtc *crtc;
837
838 if (pm_runtime_suspended(dev))
839 return 0;
840
841 drm_modeset_lock_all(drm_dev);
842 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head)
843 atmel_hlcdc_crtc_suspend(crtc);
844 drm_modeset_unlock_all(drm_dev);
845 return 0;
846}
847
848static int atmel_hlcdc_dc_drm_resume(struct device *dev)
849{
850 struct drm_device *drm_dev = dev_get_drvdata(dev);
851 struct drm_crtc *crtc;
852
853 if (pm_runtime_suspended(dev))
854 return 0;
855
856 drm_modeset_lock_all(drm_dev);
857 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head)
858 atmel_hlcdc_crtc_resume(crtc);
859 drm_modeset_unlock_all(drm_dev);
860 return 0;
861}
862#endif
863
864static SIMPLE_DEV_PM_OPS(atmel_hlcdc_dc_drm_pm_ops,
865 atmel_hlcdc_dc_drm_suspend, atmel_hlcdc_dc_drm_resume);
866
867static const struct of_device_id atmel_hlcdc_dc_of_match[] = {
868 { .compatible = "atmel,hlcdc-display-controller" },
869 { },
870};
871
872static struct platform_driver atmel_hlcdc_dc_platform_driver = {
873 .probe = atmel_hlcdc_dc_drm_probe,
874 .remove = atmel_hlcdc_dc_drm_remove,
875 .driver = {
876 .name = "atmel-hlcdc-display-controller",
877 .pm = &atmel_hlcdc_dc_drm_pm_ops,
878 .of_match_table = atmel_hlcdc_dc_of_match,
879 },
880};
881module_platform_driver(atmel_hlcdc_dc_platform_driver);
882
883MODULE_AUTHOR("Jean-Jacques Hiblot <jjhiblot@traphandler.com>");
884MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com>");
885MODULE_DESCRIPTION("Atmel HLCDC Display Controller DRM Driver");
886MODULE_LICENSE("GPL");
887MODULE_ALIAS("platform:atmel-hlcdc-dc");