1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Altera Passive Serial SPI Driver
  4 *
  5 *  Copyright (c) 2017 United Western Technologies, Corporation
  6 *
  7 *  Joshua Clayton <stillcompiling@gmail.com>
  8 *
  9 * Manage Altera FPGA firmware that is loaded over SPI using the passive
 10 * serial configuration method.
 11 * Firmware must be in binary "rbf" format.
 12 * Works on Arria 10, Cyclone V and Stratix V. Should work on Cyclone series.
 13 * May work on other Altera FPGAs.
 14 */
 15
 16#include <linux/bitrev.h>
 17#include <linux/delay.h>
 18#include <linux/fpga/fpga-mgr.h>
 19#include <linux/gpio/consumer.h>
 20#include <linux/module.h>
 21#include <linux/of.h>
 22#include <linux/spi/spi.h>
 23#include <linux/sizes.h>
 24
 25enum altera_ps_devtype {
 26	CYCLONE5,
 27	ARRIA10,
 28};
 29
 30struct altera_ps_data {
 31	enum altera_ps_devtype devtype;
 32	int status_wait_min_us;
 33	int status_wait_max_us;
 34	int t_cfg_us;
 35	int t_st2ck_us;
 36};
 37
 38struct altera_ps_conf {
 39	struct gpio_desc *config;
 40	struct gpio_desc *confd;
 41	struct gpio_desc *status;
 42	struct spi_device *spi;
 43	const struct altera_ps_data *data;
 44	u32 info_flags;
 45	char mgr_name[64];
 46};
 47
 48/*          |   Arria 10  |   Cyclone5  |   Stratix5  |
 49 * t_CF2ST0 |     [; 600] |     [; 600] |     [; 600] |ns
 50 * t_CFG    |        [2;] |        [2;] |        [2;] |µs
 51 * t_STATUS | [268; 3000] | [268; 1506] | [268; 1506] |µs
 52 * t_CF2ST1 |    [; 3000] |    [; 1506] |    [; 1506] |µs
 53 * t_CF2CK  |     [3010;] |     [1506;] |     [1506;] |µs
 54 * t_ST2CK  |       [10;] |        [2;] |        [2;] |µs
 55 * t_CD2UM  |  [175; 830] |  [175; 437] |  [175; 437] |µs
 56 */
 57static struct altera_ps_data c5_data = {
 58	/* these values for Cyclone5 are compatible with Stratix5 */
 59	.devtype = CYCLONE5,
 60	.status_wait_min_us = 268,
 61	.status_wait_max_us = 1506,
 62	.t_cfg_us = 2,
 63	.t_st2ck_us = 2,
 64};
 65
 66static struct altera_ps_data a10_data = {
 67	.devtype = ARRIA10,
 68	.status_wait_min_us = 268,  /* min(t_STATUS) */
 69	.status_wait_max_us = 3000, /* max(t_CF2ST1) */
 70	.t_cfg_us = 2,    /* max { min(t_CFG), max(tCF2ST0) } */
 71	.t_st2ck_us = 10, /* min(t_ST2CK) */
 72};
 73
 74static const struct of_device_id of_ef_match[] = {
 75	{ .compatible = "altr,fpga-passive-serial", .data = &c5_data },
 76	{ .compatible = "altr,fpga-arria10-passive-serial", .data = &a10_data },
 77	{}
 78};
 79MODULE_DEVICE_TABLE(of, of_ef_match);
 80
 81static enum fpga_mgr_states altera_ps_state(struct fpga_manager *mgr)
 82{
 83	struct altera_ps_conf *conf = mgr->priv;
 84
 85	if (gpiod_get_value_cansleep(conf->status))
 86		return FPGA_MGR_STATE_RESET;
 87
 88	return FPGA_MGR_STATE_UNKNOWN;
 89}
 90
 91static inline void altera_ps_delay(int delay_us)
 92{
 93	if (delay_us > 10)
 94		usleep_range(delay_us, delay_us + 5);
 95	else
 96		udelay(delay_us);
 97}
 98
 99static int altera_ps_write_init(struct fpga_manager *mgr,
100				struct fpga_image_info *info,
101				const char *buf, size_t count)
102{
103	struct altera_ps_conf *conf = mgr->priv;
104	int min, max, waits;
105	int i;
106
107	conf->info_flags = info->flags;
108
109	if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) {
110		dev_err(&mgr->dev, "Partial reconfiguration not supported.\n");
111		return -EINVAL;
112	}
113
114	gpiod_set_value_cansleep(conf->config, 1);
115
116	/* wait min reset pulse time */
117	altera_ps_delay(conf->data->t_cfg_us);
118
119	if (!gpiod_get_value_cansleep(conf->status)) {
120		dev_err(&mgr->dev, "Status pin failed to show a reset\n");
121		return -EIO;
122	}
123
124	gpiod_set_value_cansleep(conf->config, 0);
125
126	min = conf->data->status_wait_min_us;
127	max = conf->data->status_wait_max_us;
128	waits = max / min;
129	if (max % min)
130		waits++;
131
132	/* wait for max { max(t_STATUS), max(t_CF2ST1) } */
133	for (i = 0; i < waits; i++) {
134		usleep_range(min, min + 10);
135		if (!gpiod_get_value_cansleep(conf->status)) {
136			/* wait for min(t_ST2CK)*/
137			altera_ps_delay(conf->data->t_st2ck_us);
138			return 0;
139		}
140	}
141
142	dev_err(&mgr->dev, "Status pin not ready.\n");
143	return -EIO;
144}
145
146static void rev_buf(char *buf, size_t len)
147{
148	u32 *fw32 = (u32 *)buf;
149	size_t extra_bytes = (len & 0x03);
150	const u32 *fw_end = (u32 *)(buf + len - extra_bytes);
151
152	/* set buffer to lsb first */
153	while (fw32 < fw_end) {
154		*fw32 = bitrev8x4(*fw32);
155		fw32++;
156	}
157
158	if (extra_bytes) {
159		buf = (char *)fw_end;
160		while (extra_bytes) {
161			*buf = bitrev8(*buf);
162			buf++;
163			extra_bytes--;
164		}
165	}
166}
167
168static int altera_ps_write(struct fpga_manager *mgr, const char *buf,
169			   size_t count)
170{
171	struct altera_ps_conf *conf = mgr->priv;
172	const char *fw_data = buf;
173	const char *fw_data_end = fw_data + count;
174
175	while (fw_data < fw_data_end) {
176		int ret;
177		size_t stride = min_t(size_t, fw_data_end - fw_data, SZ_4K);
178
179		if (!(conf->info_flags & FPGA_MGR_BITSTREAM_LSB_FIRST))
180			rev_buf((char *)fw_data, stride);
181
182		ret = spi_write(conf->spi, fw_data, stride);
183		if (ret) {
184			dev_err(&mgr->dev, "spi error in firmware write: %d\n",
185				ret);
186			return ret;
187		}
188		fw_data += stride;
189	}
190
191	return 0;
192}
193
194static int altera_ps_write_complete(struct fpga_manager *mgr,
195				    struct fpga_image_info *info)
196{
197	struct altera_ps_conf *conf = mgr->priv;
198	static const char dummy[] = {0};
199	int ret;
200
201	if (gpiod_get_value_cansleep(conf->status)) {
202		dev_err(&mgr->dev, "Error during configuration.\n");
203		return -EIO;
204	}
205
206	if (conf->confd) {
207		if (!gpiod_get_raw_value_cansleep(conf->confd)) {
208			dev_err(&mgr->dev, "CONF_DONE is inactive!\n");
209			return -EIO;
210		}
211	}
212
213	/*
214	 * After CONF_DONE goes high, send two additional falling edges on DCLK
215	 * to begin initialization and enter user mode
216	 */
217	ret = spi_write(conf->spi, dummy, 1);
218	if (ret) {
219		dev_err(&mgr->dev, "spi error during end sequence: %d\n", ret);
220		return ret;
221	}
222
223	return 0;
224}
225
226static const struct fpga_manager_ops altera_ps_ops = {
227	.state = altera_ps_state,
228	.write_init = altera_ps_write_init,
229	.write = altera_ps_write,
230	.write_complete = altera_ps_write_complete,
231};
232
233static int altera_ps_probe(struct spi_device *spi)
234{
235	struct altera_ps_conf *conf;
236	struct fpga_manager *mgr;
237
238	conf = devm_kzalloc(&spi->dev, sizeof(*conf), GFP_KERNEL);
239	if (!conf)
240		return -ENOMEM;
241
242	conf->data = spi_get_device_match_data(spi);
243	conf->spi = spi;
244	conf->config = devm_gpiod_get(&spi->dev, "nconfig", GPIOD_OUT_LOW);
245	if (IS_ERR(conf->config)) {
246		dev_err(&spi->dev, "Failed to get config gpio: %ld\n",
247			PTR_ERR(conf->config));
248		return PTR_ERR(conf->config);
249	}
250
251	conf->status = devm_gpiod_get(&spi->dev, "nstat", GPIOD_IN);
252	if (IS_ERR(conf->status)) {
253		dev_err(&spi->dev, "Failed to get status gpio: %ld\n",
254			PTR_ERR(conf->status));
255		return PTR_ERR(conf->status);
256	}
257
258	conf->confd = devm_gpiod_get_optional(&spi->dev, "confd", GPIOD_IN);
259	if (IS_ERR(conf->confd)) {
260		dev_err(&spi->dev, "Failed to get confd gpio: %ld\n",
261			PTR_ERR(conf->confd));
262		return PTR_ERR(conf->confd);
263	} else if (!conf->confd) {
264		dev_warn(&spi->dev, "Not using confd gpio");
265	}
266
267	/* Register manager with unique name */
268	snprintf(conf->mgr_name, sizeof(conf->mgr_name), "%s %s",
269		 dev_driver_string(&spi->dev), dev_name(&spi->dev));
270
271	mgr = devm_fpga_mgr_register(&spi->dev, conf->mgr_name,
272				     &altera_ps_ops, conf);
273	return PTR_ERR_OR_ZERO(mgr);
274}
275
276static const struct spi_device_id altera_ps_spi_ids[] = {
277	{ "cyclone-ps-spi", (uintptr_t)&c5_data },
278	{ "fpga-passive-serial", (uintptr_t)&c5_data },
279	{ "fpga-arria10-passive-serial", (uintptr_t)&a10_data },
280	{}
281};
282MODULE_DEVICE_TABLE(spi, altera_ps_spi_ids);
283
284static struct spi_driver altera_ps_driver = {
285	.driver = {
286		.name = "altera-ps-spi",
287		.of_match_table = of_ef_match,
288	},
289	.id_table = altera_ps_spi_ids,
290	.probe = altera_ps_probe,
291};
292
293module_spi_driver(altera_ps_driver)
294
295MODULE_LICENSE("GPL v2");
296MODULE_AUTHOR("Joshua Clayton <stillcompiling@gmail.com>");
297MODULE_DESCRIPTION("Module to load Altera FPGA firmware over SPI");