Loading...
1/*
2 * edac_mc kernel module
3 * (C) 2005, 2006 Linux Networx (http://lnxi.com)
4 * This file may be distributed under the terms of the
5 * GNU General Public License.
6 *
7 * Written by Thayne Harbaugh
8 * Based on work by Dan Hollis <goemon at anime dot net> and others.
9 * http://www.anime.net/~goemon/linux-ecc/
10 *
11 * Modified by Dave Peterson and Doug Thompson
12 *
13 */
14
15#include <linux/module.h>
16#include <linux/proc_fs.h>
17#include <linux/kernel.h>
18#include <linux/types.h>
19#include <linux/smp.h>
20#include <linux/init.h>
21#include <linux/sysctl.h>
22#include <linux/highmem.h>
23#include <linux/timer.h>
24#include <linux/slab.h>
25#include <linux/jiffies.h>
26#include <linux/spinlock.h>
27#include <linux/list.h>
28#include <linux/ctype.h>
29#include <linux/edac.h>
30#include <linux/bitops.h>
31#include <linux/uaccess.h>
32#include <asm/page.h>
33#include "edac_mc.h"
34#include "edac_module.h"
35#include <ras/ras_event.h>
36
37#ifdef CONFIG_EDAC_ATOMIC_SCRUB
38#include <asm/edac.h>
39#else
40#define edac_atomic_scrub(va, size) do { } while (0)
41#endif
42
43int edac_op_state = EDAC_OPSTATE_INVAL;
44EXPORT_SYMBOL_GPL(edac_op_state);
45
46/* lock to memory controller's control array */
47static DEFINE_MUTEX(mem_ctls_mutex);
48static LIST_HEAD(mc_devices);
49
50/*
51 * Used to lock EDAC MC to just one module, avoiding two drivers e. g.
52 * apei/ghes and i7core_edac to be used at the same time.
53 */
54static const char *edac_mc_owner;
55
56static struct mem_ctl_info *error_desc_to_mci(struct edac_raw_error_desc *e)
57{
58 return container_of(e, struct mem_ctl_info, error_desc);
59}
60
61unsigned int edac_dimm_info_location(struct dimm_info *dimm, char *buf,
62 unsigned int len)
63{
64 struct mem_ctl_info *mci = dimm->mci;
65 int i, n, count = 0;
66 char *p = buf;
67
68 for (i = 0; i < mci->n_layers; i++) {
69 n = scnprintf(p, len, "%s %d ",
70 edac_layer_name[mci->layers[i].type],
71 dimm->location[i]);
72 p += n;
73 len -= n;
74 count += n;
75 }
76
77 return count;
78}
79
80#ifdef CONFIG_EDAC_DEBUG
81
82static void edac_mc_dump_channel(struct rank_info *chan)
83{
84 edac_dbg(4, " channel->chan_idx = %d\n", chan->chan_idx);
85 edac_dbg(4, " channel = %p\n", chan);
86 edac_dbg(4, " channel->csrow = %p\n", chan->csrow);
87 edac_dbg(4, " channel->dimm = %p\n", chan->dimm);
88}
89
90static void edac_mc_dump_dimm(struct dimm_info *dimm)
91{
92 char location[80];
93
94 if (!dimm->nr_pages)
95 return;
96
97 edac_dimm_info_location(dimm, location, sizeof(location));
98
99 edac_dbg(4, "%s%i: %smapped as virtual row %d, chan %d\n",
100 dimm->mci->csbased ? "rank" : "dimm",
101 dimm->idx, location, dimm->csrow, dimm->cschannel);
102 edac_dbg(4, " dimm = %p\n", dimm);
103 edac_dbg(4, " dimm->label = '%s'\n", dimm->label);
104 edac_dbg(4, " dimm->nr_pages = 0x%x\n", dimm->nr_pages);
105 edac_dbg(4, " dimm->grain = %d\n", dimm->grain);
106}
107
108static void edac_mc_dump_csrow(struct csrow_info *csrow)
109{
110 edac_dbg(4, "csrow->csrow_idx = %d\n", csrow->csrow_idx);
111 edac_dbg(4, " csrow = %p\n", csrow);
112 edac_dbg(4, " csrow->first_page = 0x%lx\n", csrow->first_page);
113 edac_dbg(4, " csrow->last_page = 0x%lx\n", csrow->last_page);
114 edac_dbg(4, " csrow->page_mask = 0x%lx\n", csrow->page_mask);
115 edac_dbg(4, " csrow->nr_channels = %d\n", csrow->nr_channels);
116 edac_dbg(4, " csrow->channels = %p\n", csrow->channels);
117 edac_dbg(4, " csrow->mci = %p\n", csrow->mci);
118}
119
120static void edac_mc_dump_mci(struct mem_ctl_info *mci)
121{
122 edac_dbg(3, "\tmci = %p\n", mci);
123 edac_dbg(3, "\tmci->mtype_cap = %lx\n", mci->mtype_cap);
124 edac_dbg(3, "\tmci->edac_ctl_cap = %lx\n", mci->edac_ctl_cap);
125 edac_dbg(3, "\tmci->edac_cap = %lx\n", mci->edac_cap);
126 edac_dbg(4, "\tmci->edac_check = %p\n", mci->edac_check);
127 edac_dbg(3, "\tmci->nr_csrows = %d, csrows = %p\n",
128 mci->nr_csrows, mci->csrows);
129 edac_dbg(3, "\tmci->nr_dimms = %d, dimms = %p\n",
130 mci->tot_dimms, mci->dimms);
131 edac_dbg(3, "\tdev = %p\n", mci->pdev);
132 edac_dbg(3, "\tmod_name:ctl_name = %s:%s\n",
133 mci->mod_name, mci->ctl_name);
134 edac_dbg(3, "\tpvt_info = %p\n\n", mci->pvt_info);
135}
136
137#endif /* CONFIG_EDAC_DEBUG */
138
139const char * const edac_mem_types[] = {
140 [MEM_EMPTY] = "Empty",
141 [MEM_RESERVED] = "Reserved",
142 [MEM_UNKNOWN] = "Unknown",
143 [MEM_FPM] = "FPM",
144 [MEM_EDO] = "EDO",
145 [MEM_BEDO] = "BEDO",
146 [MEM_SDR] = "Unbuffered-SDR",
147 [MEM_RDR] = "Registered-SDR",
148 [MEM_DDR] = "Unbuffered-DDR",
149 [MEM_RDDR] = "Registered-DDR",
150 [MEM_RMBS] = "RMBS",
151 [MEM_DDR2] = "Unbuffered-DDR2",
152 [MEM_FB_DDR2] = "FullyBuffered-DDR2",
153 [MEM_RDDR2] = "Registered-DDR2",
154 [MEM_XDR] = "XDR",
155 [MEM_DDR3] = "Unbuffered-DDR3",
156 [MEM_RDDR3] = "Registered-DDR3",
157 [MEM_LRDDR3] = "Load-Reduced-DDR3-RAM",
158 [MEM_LPDDR3] = "Low-Power-DDR3-RAM",
159 [MEM_DDR4] = "Unbuffered-DDR4",
160 [MEM_RDDR4] = "Registered-DDR4",
161 [MEM_LPDDR4] = "Low-Power-DDR4-RAM",
162 [MEM_LRDDR4] = "Load-Reduced-DDR4-RAM",
163 [MEM_DDR5] = "Unbuffered-DDR5",
164 [MEM_RDDR5] = "Registered-DDR5",
165 [MEM_LRDDR5] = "Load-Reduced-DDR5-RAM",
166 [MEM_NVDIMM] = "Non-volatile-RAM",
167 [MEM_WIO2] = "Wide-IO-2",
168 [MEM_HBM2] = "High-bandwidth-memory-Gen2",
169 [MEM_HBM3] = "High-bandwidth-memory-Gen3",
170};
171EXPORT_SYMBOL_GPL(edac_mem_types);
172
173static void _edac_mc_free(struct mem_ctl_info *mci)
174{
175 put_device(&mci->dev);
176}
177
178static void mci_release(struct device *dev)
179{
180 struct mem_ctl_info *mci = container_of(dev, struct mem_ctl_info, dev);
181 struct csrow_info *csr;
182 int i, chn, row;
183
184 if (mci->dimms) {
185 for (i = 0; i < mci->tot_dimms; i++)
186 kfree(mci->dimms[i]);
187 kfree(mci->dimms);
188 }
189
190 if (mci->csrows) {
191 for (row = 0; row < mci->nr_csrows; row++) {
192 csr = mci->csrows[row];
193 if (!csr)
194 continue;
195
196 if (csr->channels) {
197 for (chn = 0; chn < mci->num_cschannel; chn++)
198 kfree(csr->channels[chn]);
199 kfree(csr->channels);
200 }
201 kfree(csr);
202 }
203 kfree(mci->csrows);
204 }
205 kfree(mci->pvt_info);
206 kfree(mci->layers);
207 kfree(mci);
208}
209
210static int edac_mc_alloc_csrows(struct mem_ctl_info *mci)
211{
212 unsigned int tot_channels = mci->num_cschannel;
213 unsigned int tot_csrows = mci->nr_csrows;
214 unsigned int row, chn;
215
216 /*
217 * Alocate and fill the csrow/channels structs
218 */
219 mci->csrows = kcalloc(tot_csrows, sizeof(*mci->csrows), GFP_KERNEL);
220 if (!mci->csrows)
221 return -ENOMEM;
222
223 for (row = 0; row < tot_csrows; row++) {
224 struct csrow_info *csr;
225
226 csr = kzalloc(sizeof(**mci->csrows), GFP_KERNEL);
227 if (!csr)
228 return -ENOMEM;
229
230 mci->csrows[row] = csr;
231 csr->csrow_idx = row;
232 csr->mci = mci;
233 csr->nr_channels = tot_channels;
234 csr->channels = kcalloc(tot_channels, sizeof(*csr->channels),
235 GFP_KERNEL);
236 if (!csr->channels)
237 return -ENOMEM;
238
239 for (chn = 0; chn < tot_channels; chn++) {
240 struct rank_info *chan;
241
242 chan = kzalloc(sizeof(**csr->channels), GFP_KERNEL);
243 if (!chan)
244 return -ENOMEM;
245
246 csr->channels[chn] = chan;
247 chan->chan_idx = chn;
248 chan->csrow = csr;
249 }
250 }
251
252 return 0;
253}
254
255static int edac_mc_alloc_dimms(struct mem_ctl_info *mci)
256{
257 unsigned int pos[EDAC_MAX_LAYERS];
258 unsigned int row, chn, idx;
259 int layer;
260 void *p;
261
262 /*
263 * Allocate and fill the dimm structs
264 */
265 mci->dimms = kcalloc(mci->tot_dimms, sizeof(*mci->dimms), GFP_KERNEL);
266 if (!mci->dimms)
267 return -ENOMEM;
268
269 memset(&pos, 0, sizeof(pos));
270 row = 0;
271 chn = 0;
272 for (idx = 0; idx < mci->tot_dimms; idx++) {
273 struct dimm_info *dimm;
274 struct rank_info *chan;
275 int n, len;
276
277 chan = mci->csrows[row]->channels[chn];
278
279 dimm = kzalloc(sizeof(**mci->dimms), GFP_KERNEL);
280 if (!dimm)
281 return -ENOMEM;
282 mci->dimms[idx] = dimm;
283 dimm->mci = mci;
284 dimm->idx = idx;
285
286 /*
287 * Copy DIMM location and initialize it.
288 */
289 len = sizeof(dimm->label);
290 p = dimm->label;
291 n = scnprintf(p, len, "mc#%u", mci->mc_idx);
292 p += n;
293 len -= n;
294 for (layer = 0; layer < mci->n_layers; layer++) {
295 n = scnprintf(p, len, "%s#%u",
296 edac_layer_name[mci->layers[layer].type],
297 pos[layer]);
298 p += n;
299 len -= n;
300 dimm->location[layer] = pos[layer];
301 }
302
303 /* Link it to the csrows old API data */
304 chan->dimm = dimm;
305 dimm->csrow = row;
306 dimm->cschannel = chn;
307
308 /* Increment csrow location */
309 if (mci->layers[0].is_virt_csrow) {
310 chn++;
311 if (chn == mci->num_cschannel) {
312 chn = 0;
313 row++;
314 }
315 } else {
316 row++;
317 if (row == mci->nr_csrows) {
318 row = 0;
319 chn++;
320 }
321 }
322
323 /* Increment dimm location */
324 for (layer = mci->n_layers - 1; layer >= 0; layer--) {
325 pos[layer]++;
326 if (pos[layer] < mci->layers[layer].size)
327 break;
328 pos[layer] = 0;
329 }
330 }
331
332 return 0;
333}
334
335struct mem_ctl_info *edac_mc_alloc(unsigned int mc_num,
336 unsigned int n_layers,
337 struct edac_mc_layer *layers,
338 unsigned int sz_pvt)
339{
340 struct mem_ctl_info *mci;
341 struct edac_mc_layer *layer;
342 unsigned int idx, tot_dimms = 1;
343 unsigned int tot_csrows = 1, tot_channels = 1;
344 bool per_rank = false;
345
346 if (WARN_ON(n_layers > EDAC_MAX_LAYERS || n_layers == 0))
347 return NULL;
348
349 /*
350 * Calculate the total amount of dimms and csrows/cschannels while
351 * in the old API emulation mode
352 */
353 for (idx = 0; idx < n_layers; idx++) {
354 tot_dimms *= layers[idx].size;
355
356 if (layers[idx].is_virt_csrow)
357 tot_csrows *= layers[idx].size;
358 else
359 tot_channels *= layers[idx].size;
360
361 if (layers[idx].type == EDAC_MC_LAYER_CHIP_SELECT)
362 per_rank = true;
363 }
364
365 mci = kzalloc(sizeof(struct mem_ctl_info), GFP_KERNEL);
366 if (!mci)
367 return NULL;
368
369 mci->layers = kcalloc(n_layers, sizeof(struct edac_mc_layer), GFP_KERNEL);
370 if (!mci->layers)
371 goto error;
372
373 mci->pvt_info = kzalloc(sz_pvt, GFP_KERNEL);
374 if (!mci->pvt_info)
375 goto error;
376
377 mci->dev.release = mci_release;
378 device_initialize(&mci->dev);
379
380 /* setup index and various internal pointers */
381 mci->mc_idx = mc_num;
382 mci->tot_dimms = tot_dimms;
383 mci->n_layers = n_layers;
384 memcpy(mci->layers, layers, sizeof(*layer) * n_layers);
385 mci->nr_csrows = tot_csrows;
386 mci->num_cschannel = tot_channels;
387 mci->csbased = per_rank;
388
389 if (edac_mc_alloc_csrows(mci))
390 goto error;
391
392 if (edac_mc_alloc_dimms(mci))
393 goto error;
394
395 mci->op_state = OP_ALLOC;
396
397 return mci;
398
399error:
400 _edac_mc_free(mci);
401
402 return NULL;
403}
404EXPORT_SYMBOL_GPL(edac_mc_alloc);
405
406void edac_mc_free(struct mem_ctl_info *mci)
407{
408 edac_dbg(1, "\n");
409
410 _edac_mc_free(mci);
411}
412EXPORT_SYMBOL_GPL(edac_mc_free);
413
414bool edac_has_mcs(void)
415{
416 bool ret;
417
418 mutex_lock(&mem_ctls_mutex);
419
420 ret = list_empty(&mc_devices);
421
422 mutex_unlock(&mem_ctls_mutex);
423
424 return !ret;
425}
426EXPORT_SYMBOL_GPL(edac_has_mcs);
427
428/* Caller must hold mem_ctls_mutex */
429static struct mem_ctl_info *__find_mci_by_dev(struct device *dev)
430{
431 struct mem_ctl_info *mci;
432 struct list_head *item;
433
434 edac_dbg(3, "\n");
435
436 list_for_each(item, &mc_devices) {
437 mci = list_entry(item, struct mem_ctl_info, link);
438
439 if (mci->pdev == dev)
440 return mci;
441 }
442
443 return NULL;
444}
445
446/**
447 * find_mci_by_dev
448 *
449 * scan list of controllers looking for the one that manages
450 * the 'dev' device
451 * @dev: pointer to a struct device related with the MCI
452 */
453struct mem_ctl_info *find_mci_by_dev(struct device *dev)
454{
455 struct mem_ctl_info *ret;
456
457 mutex_lock(&mem_ctls_mutex);
458 ret = __find_mci_by_dev(dev);
459 mutex_unlock(&mem_ctls_mutex);
460
461 return ret;
462}
463EXPORT_SYMBOL_GPL(find_mci_by_dev);
464
465/*
466 * edac_mc_workq_function
467 * performs the operation scheduled by a workq request
468 */
469static void edac_mc_workq_function(struct work_struct *work_req)
470{
471 struct delayed_work *d_work = to_delayed_work(work_req);
472 struct mem_ctl_info *mci = to_edac_mem_ctl_work(d_work);
473
474 mutex_lock(&mem_ctls_mutex);
475
476 if (mci->op_state != OP_RUNNING_POLL) {
477 mutex_unlock(&mem_ctls_mutex);
478 return;
479 }
480
481 if (edac_op_state == EDAC_OPSTATE_POLL)
482 mci->edac_check(mci);
483
484 mutex_unlock(&mem_ctls_mutex);
485
486 /* Queue ourselves again. */
487 edac_queue_work(&mci->work, msecs_to_jiffies(edac_mc_get_poll_msec()));
488}
489
490/*
491 * edac_mc_reset_delay_period(unsigned long value)
492 *
493 * user space has updated our poll period value, need to
494 * reset our workq delays
495 */
496void edac_mc_reset_delay_period(unsigned long value)
497{
498 struct mem_ctl_info *mci;
499 struct list_head *item;
500
501 mutex_lock(&mem_ctls_mutex);
502
503 list_for_each(item, &mc_devices) {
504 mci = list_entry(item, struct mem_ctl_info, link);
505
506 if (mci->op_state == OP_RUNNING_POLL)
507 edac_mod_work(&mci->work, value);
508 }
509 mutex_unlock(&mem_ctls_mutex);
510}
511
512
513
514/* Return 0 on success, 1 on failure.
515 * Before calling this function, caller must
516 * assign a unique value to mci->mc_idx.
517 *
518 * locking model:
519 *
520 * called with the mem_ctls_mutex lock held
521 */
522static int add_mc_to_global_list(struct mem_ctl_info *mci)
523{
524 struct list_head *item, *insert_before;
525 struct mem_ctl_info *p;
526
527 insert_before = &mc_devices;
528
529 p = __find_mci_by_dev(mci->pdev);
530 if (unlikely(p != NULL))
531 goto fail0;
532
533 list_for_each(item, &mc_devices) {
534 p = list_entry(item, struct mem_ctl_info, link);
535
536 if (p->mc_idx >= mci->mc_idx) {
537 if (unlikely(p->mc_idx == mci->mc_idx))
538 goto fail1;
539
540 insert_before = item;
541 break;
542 }
543 }
544
545 list_add_tail_rcu(&mci->link, insert_before);
546 return 0;
547
548fail0:
549 edac_printk(KERN_WARNING, EDAC_MC,
550 "%s (%s) %s %s already assigned %d\n", dev_name(p->pdev),
551 edac_dev_name(mci), p->mod_name, p->ctl_name, p->mc_idx);
552 return 1;
553
554fail1:
555 edac_printk(KERN_WARNING, EDAC_MC,
556 "bug in low-level driver: attempt to assign\n"
557 " duplicate mc_idx %d in %s()\n", p->mc_idx, __func__);
558 return 1;
559}
560
561static int del_mc_from_global_list(struct mem_ctl_info *mci)
562{
563 list_del_rcu(&mci->link);
564
565 /* these are for safe removal of devices from global list while
566 * NMI handlers may be traversing list
567 */
568 synchronize_rcu();
569 INIT_LIST_HEAD(&mci->link);
570
571 return list_empty(&mc_devices);
572}
573
574struct mem_ctl_info *edac_mc_find(int idx)
575{
576 struct mem_ctl_info *mci;
577 struct list_head *item;
578
579 mutex_lock(&mem_ctls_mutex);
580
581 list_for_each(item, &mc_devices) {
582 mci = list_entry(item, struct mem_ctl_info, link);
583 if (mci->mc_idx == idx)
584 goto unlock;
585 }
586
587 mci = NULL;
588unlock:
589 mutex_unlock(&mem_ctls_mutex);
590 return mci;
591}
592EXPORT_SYMBOL(edac_mc_find);
593
594const char *edac_get_owner(void)
595{
596 return edac_mc_owner;
597}
598EXPORT_SYMBOL_GPL(edac_get_owner);
599
600/* FIXME - should a warning be printed if no error detection? correction? */
601int edac_mc_add_mc_with_groups(struct mem_ctl_info *mci,
602 const struct attribute_group **groups)
603{
604 int ret = -EINVAL;
605 edac_dbg(0, "\n");
606
607#ifdef CONFIG_EDAC_DEBUG
608 if (edac_debug_level >= 3)
609 edac_mc_dump_mci(mci);
610
611 if (edac_debug_level >= 4) {
612 struct dimm_info *dimm;
613 int i;
614
615 for (i = 0; i < mci->nr_csrows; i++) {
616 struct csrow_info *csrow = mci->csrows[i];
617 u32 nr_pages = 0;
618 int j;
619
620 for (j = 0; j < csrow->nr_channels; j++)
621 nr_pages += csrow->channels[j]->dimm->nr_pages;
622 if (!nr_pages)
623 continue;
624 edac_mc_dump_csrow(csrow);
625 for (j = 0; j < csrow->nr_channels; j++)
626 if (csrow->channels[j]->dimm->nr_pages)
627 edac_mc_dump_channel(csrow->channels[j]);
628 }
629
630 mci_for_each_dimm(mci, dimm)
631 edac_mc_dump_dimm(dimm);
632 }
633#endif
634 mutex_lock(&mem_ctls_mutex);
635
636 if (edac_mc_owner && edac_mc_owner != mci->mod_name) {
637 ret = -EPERM;
638 goto fail0;
639 }
640
641 if (add_mc_to_global_list(mci))
642 goto fail0;
643
644 /* set load time so that error rate can be tracked */
645 mci->start_time = jiffies;
646
647 mci->bus = edac_get_sysfs_subsys();
648
649 if (edac_create_sysfs_mci_device(mci, groups)) {
650 edac_mc_printk(mci, KERN_WARNING,
651 "failed to create sysfs device\n");
652 goto fail1;
653 }
654
655 if (mci->edac_check) {
656 mci->op_state = OP_RUNNING_POLL;
657
658 INIT_DELAYED_WORK(&mci->work, edac_mc_workq_function);
659 edac_queue_work(&mci->work, msecs_to_jiffies(edac_mc_get_poll_msec()));
660
661 } else {
662 mci->op_state = OP_RUNNING_INTERRUPT;
663 }
664
665 /* Report action taken */
666 edac_mc_printk(mci, KERN_INFO,
667 "Giving out device to module %s controller %s: DEV %s (%s)\n",
668 mci->mod_name, mci->ctl_name, mci->dev_name,
669 edac_op_state_to_string(mci->op_state));
670
671 edac_mc_owner = mci->mod_name;
672
673 mutex_unlock(&mem_ctls_mutex);
674 return 0;
675
676fail1:
677 del_mc_from_global_list(mci);
678
679fail0:
680 mutex_unlock(&mem_ctls_mutex);
681 return ret;
682}
683EXPORT_SYMBOL_GPL(edac_mc_add_mc_with_groups);
684
685struct mem_ctl_info *edac_mc_del_mc(struct device *dev)
686{
687 struct mem_ctl_info *mci;
688
689 edac_dbg(0, "\n");
690
691 mutex_lock(&mem_ctls_mutex);
692
693 /* find the requested mci struct in the global list */
694 mci = __find_mci_by_dev(dev);
695 if (mci == NULL) {
696 mutex_unlock(&mem_ctls_mutex);
697 return NULL;
698 }
699
700 /* mark MCI offline: */
701 mci->op_state = OP_OFFLINE;
702
703 if (del_mc_from_global_list(mci))
704 edac_mc_owner = NULL;
705
706 mutex_unlock(&mem_ctls_mutex);
707
708 if (mci->edac_check)
709 edac_stop_work(&mci->work);
710
711 /* remove from sysfs */
712 edac_remove_sysfs_mci_device(mci);
713
714 edac_printk(KERN_INFO, EDAC_MC,
715 "Removed device %d for %s %s: DEV %s\n", mci->mc_idx,
716 mci->mod_name, mci->ctl_name, edac_dev_name(mci));
717
718 return mci;
719}
720EXPORT_SYMBOL_GPL(edac_mc_del_mc);
721
722static void edac_mc_scrub_block(unsigned long page, unsigned long offset,
723 u32 size)
724{
725 struct page *pg;
726 void *virt_addr;
727 unsigned long flags = 0;
728
729 edac_dbg(3, "\n");
730
731 /* ECC error page was not in our memory. Ignore it. */
732 if (!pfn_valid(page))
733 return;
734
735 /* Find the actual page structure then map it and fix */
736 pg = pfn_to_page(page);
737
738 if (PageHighMem(pg))
739 local_irq_save(flags);
740
741 virt_addr = kmap_atomic(pg);
742
743 /* Perform architecture specific atomic scrub operation */
744 edac_atomic_scrub(virt_addr + offset, size);
745
746 /* Unmap and complete */
747 kunmap_atomic(virt_addr);
748
749 if (PageHighMem(pg))
750 local_irq_restore(flags);
751}
752
753/* FIXME - should return -1 */
754int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci, unsigned long page)
755{
756 struct csrow_info **csrows = mci->csrows;
757 int row, i, j, n;
758
759 edac_dbg(1, "MC%d: 0x%lx\n", mci->mc_idx, page);
760 row = -1;
761
762 for (i = 0; i < mci->nr_csrows; i++) {
763 struct csrow_info *csrow = csrows[i];
764 n = 0;
765 for (j = 0; j < csrow->nr_channels; j++) {
766 struct dimm_info *dimm = csrow->channels[j]->dimm;
767 n += dimm->nr_pages;
768 }
769 if (n == 0)
770 continue;
771
772 edac_dbg(3, "MC%d: first(0x%lx) page(0x%lx) last(0x%lx) mask(0x%lx)\n",
773 mci->mc_idx,
774 csrow->first_page, page, csrow->last_page,
775 csrow->page_mask);
776
777 if ((page >= csrow->first_page) &&
778 (page <= csrow->last_page) &&
779 ((page & csrow->page_mask) ==
780 (csrow->first_page & csrow->page_mask))) {
781 row = i;
782 break;
783 }
784 }
785
786 if (row == -1)
787 edac_mc_printk(mci, KERN_ERR,
788 "could not look up page error address %lx\n",
789 (unsigned long)page);
790
791 return row;
792}
793EXPORT_SYMBOL_GPL(edac_mc_find_csrow_by_page);
794
795const char *edac_layer_name[] = {
796 [EDAC_MC_LAYER_BRANCH] = "branch",
797 [EDAC_MC_LAYER_CHANNEL] = "channel",
798 [EDAC_MC_LAYER_SLOT] = "slot",
799 [EDAC_MC_LAYER_CHIP_SELECT] = "csrow",
800 [EDAC_MC_LAYER_ALL_MEM] = "memory",
801};
802EXPORT_SYMBOL_GPL(edac_layer_name);
803
804static void edac_inc_ce_error(struct edac_raw_error_desc *e)
805{
806 int pos[EDAC_MAX_LAYERS] = { e->top_layer, e->mid_layer, e->low_layer };
807 struct mem_ctl_info *mci = error_desc_to_mci(e);
808 struct dimm_info *dimm = edac_get_dimm(mci, pos[0], pos[1], pos[2]);
809
810 mci->ce_mc += e->error_count;
811
812 if (dimm)
813 dimm->ce_count += e->error_count;
814 else
815 mci->ce_noinfo_count += e->error_count;
816}
817
818static void edac_inc_ue_error(struct edac_raw_error_desc *e)
819{
820 int pos[EDAC_MAX_LAYERS] = { e->top_layer, e->mid_layer, e->low_layer };
821 struct mem_ctl_info *mci = error_desc_to_mci(e);
822 struct dimm_info *dimm = edac_get_dimm(mci, pos[0], pos[1], pos[2]);
823
824 mci->ue_mc += e->error_count;
825
826 if (dimm)
827 dimm->ue_count += e->error_count;
828 else
829 mci->ue_noinfo_count += e->error_count;
830}
831
832static void edac_ce_error(struct edac_raw_error_desc *e)
833{
834 struct mem_ctl_info *mci = error_desc_to_mci(e);
835 unsigned long remapped_page;
836
837 if (edac_mc_get_log_ce()) {
838 edac_mc_printk(mci, KERN_WARNING,
839 "%d CE %s%son %s (%s page:0x%lx offset:0x%lx grain:%ld syndrome:0x%lx%s%s)\n",
840 e->error_count, e->msg,
841 *e->msg ? " " : "",
842 e->label, e->location, e->page_frame_number, e->offset_in_page,
843 e->grain, e->syndrome,
844 *e->other_detail ? " - " : "",
845 e->other_detail);
846 }
847
848 edac_inc_ce_error(e);
849
850 if (mci->scrub_mode == SCRUB_SW_SRC) {
851 /*
852 * Some memory controllers (called MCs below) can remap
853 * memory so that it is still available at a different
854 * address when PCI devices map into memory.
855 * MC's that can't do this, lose the memory where PCI
856 * devices are mapped. This mapping is MC-dependent
857 * and so we call back into the MC driver for it to
858 * map the MC page to a physical (CPU) page which can
859 * then be mapped to a virtual page - which can then
860 * be scrubbed.
861 */
862 remapped_page = mci->ctl_page_to_phys ?
863 mci->ctl_page_to_phys(mci, e->page_frame_number) :
864 e->page_frame_number;
865
866 edac_mc_scrub_block(remapped_page, e->offset_in_page, e->grain);
867 }
868}
869
870static void edac_ue_error(struct edac_raw_error_desc *e)
871{
872 struct mem_ctl_info *mci = error_desc_to_mci(e);
873
874 if (edac_mc_get_log_ue()) {
875 edac_mc_printk(mci, KERN_WARNING,
876 "%d UE %s%son %s (%s page:0x%lx offset:0x%lx grain:%ld%s%s)\n",
877 e->error_count, e->msg,
878 *e->msg ? " " : "",
879 e->label, e->location, e->page_frame_number, e->offset_in_page,
880 e->grain,
881 *e->other_detail ? " - " : "",
882 e->other_detail);
883 }
884
885 edac_inc_ue_error(e);
886
887 if (edac_mc_get_panic_on_ue()) {
888 panic("UE %s%son %s (%s page:0x%lx offset:0x%lx grain:%ld%s%s)\n",
889 e->msg,
890 *e->msg ? " " : "",
891 e->label, e->location, e->page_frame_number, e->offset_in_page,
892 e->grain,
893 *e->other_detail ? " - " : "",
894 e->other_detail);
895 }
896}
897
898static void edac_inc_csrow(struct edac_raw_error_desc *e, int row, int chan)
899{
900 struct mem_ctl_info *mci = error_desc_to_mci(e);
901 enum hw_event_mc_err_type type = e->type;
902 u16 count = e->error_count;
903
904 if (row < 0)
905 return;
906
907 edac_dbg(4, "csrow/channel to increment: (%d,%d)\n", row, chan);
908
909 if (type == HW_EVENT_ERR_CORRECTED) {
910 mci->csrows[row]->ce_count += count;
911 if (chan >= 0)
912 mci->csrows[row]->channels[chan]->ce_count += count;
913 } else {
914 mci->csrows[row]->ue_count += count;
915 }
916}
917
918void edac_raw_mc_handle_error(struct edac_raw_error_desc *e)
919{
920 struct mem_ctl_info *mci = error_desc_to_mci(e);
921 u8 grain_bits;
922
923 /* Sanity-check driver-supplied grain value. */
924 if (WARN_ON_ONCE(!e->grain))
925 e->grain = 1;
926
927 grain_bits = fls_long(e->grain - 1);
928
929 /* Report the error via the trace interface */
930 if (IS_ENABLED(CONFIG_RAS))
931 trace_mc_event(e->type, e->msg, e->label, e->error_count,
932 mci->mc_idx, e->top_layer, e->mid_layer,
933 e->low_layer,
934 (e->page_frame_number << PAGE_SHIFT) | e->offset_in_page,
935 grain_bits, e->syndrome, e->other_detail);
936
937 if (e->type == HW_EVENT_ERR_CORRECTED)
938 edac_ce_error(e);
939 else
940 edac_ue_error(e);
941}
942EXPORT_SYMBOL_GPL(edac_raw_mc_handle_error);
943
944void edac_mc_handle_error(const enum hw_event_mc_err_type type,
945 struct mem_ctl_info *mci,
946 const u16 error_count,
947 const unsigned long page_frame_number,
948 const unsigned long offset_in_page,
949 const unsigned long syndrome,
950 const int top_layer,
951 const int mid_layer,
952 const int low_layer,
953 const char *msg,
954 const char *other_detail)
955{
956 struct dimm_info *dimm;
957 char *p, *end;
958 int row = -1, chan = -1;
959 int pos[EDAC_MAX_LAYERS] = { top_layer, mid_layer, low_layer };
960 int i, n_labels = 0;
961 struct edac_raw_error_desc *e = &mci->error_desc;
962 bool any_memory = true;
963 const char *prefix;
964
965 edac_dbg(3, "MC%d\n", mci->mc_idx);
966
967 /* Fills the error report buffer */
968 memset(e, 0, sizeof (*e));
969 e->error_count = error_count;
970 e->type = type;
971 e->top_layer = top_layer;
972 e->mid_layer = mid_layer;
973 e->low_layer = low_layer;
974 e->page_frame_number = page_frame_number;
975 e->offset_in_page = offset_in_page;
976 e->syndrome = syndrome;
977 /* need valid strings here for both: */
978 e->msg = msg ?: "";
979 e->other_detail = other_detail ?: "";
980
981 /*
982 * Check if the event report is consistent and if the memory location is
983 * known. If it is, the DIMM(s) label info will be filled and the DIMM's
984 * error counters will be incremented.
985 */
986 for (i = 0; i < mci->n_layers; i++) {
987 if (pos[i] >= (int)mci->layers[i].size) {
988
989 edac_mc_printk(mci, KERN_ERR,
990 "INTERNAL ERROR: %s value is out of range (%d >= %d)\n",
991 edac_layer_name[mci->layers[i].type],
992 pos[i], mci->layers[i].size);
993 /*
994 * Instead of just returning it, let's use what's
995 * known about the error. The increment routines and
996 * the DIMM filter logic will do the right thing by
997 * pointing the likely damaged DIMMs.
998 */
999 pos[i] = -1;
1000 }
1001 if (pos[i] >= 0)
1002 any_memory = false;
1003 }
1004
1005 /*
1006 * Get the dimm label/grain that applies to the match criteria.
1007 * As the error algorithm may not be able to point to just one memory
1008 * stick, the logic here will get all possible labels that could
1009 * pottentially be affected by the error.
1010 * On FB-DIMM memory controllers, for uncorrected errors, it is common
1011 * to have only the MC channel and the MC dimm (also called "branch")
1012 * but the channel is not known, as the memory is arranged in pairs,
1013 * where each memory belongs to a separate channel within the same
1014 * branch.
1015 */
1016 p = e->label;
1017 *p = '\0';
1018 end = p + sizeof(e->label);
1019 prefix = "";
1020
1021 mci_for_each_dimm(mci, dimm) {
1022 if (top_layer >= 0 && top_layer != dimm->location[0])
1023 continue;
1024 if (mid_layer >= 0 && mid_layer != dimm->location[1])
1025 continue;
1026 if (low_layer >= 0 && low_layer != dimm->location[2])
1027 continue;
1028
1029 /* get the max grain, over the error match range */
1030 if (dimm->grain > e->grain)
1031 e->grain = dimm->grain;
1032
1033 /*
1034 * If the error is memory-controller wide, there's no need to
1035 * seek for the affected DIMMs because the whole channel/memory
1036 * controller/... may be affected. Also, don't show errors for
1037 * empty DIMM slots.
1038 */
1039 if (!dimm->nr_pages)
1040 continue;
1041
1042 n_labels++;
1043 if (n_labels > EDAC_MAX_LABELS) {
1044 p = e->label;
1045 *p = '\0';
1046 } else {
1047 p += scnprintf(p, end - p, "%s%s", prefix, dimm->label);
1048 prefix = OTHER_LABEL;
1049 }
1050
1051 /*
1052 * get csrow/channel of the DIMM, in order to allow
1053 * incrementing the compat API counters
1054 */
1055 edac_dbg(4, "%s csrows map: (%d,%d)\n",
1056 mci->csbased ? "rank" : "dimm",
1057 dimm->csrow, dimm->cschannel);
1058 if (row == -1)
1059 row = dimm->csrow;
1060 else if (row >= 0 && row != dimm->csrow)
1061 row = -2;
1062
1063 if (chan == -1)
1064 chan = dimm->cschannel;
1065 else if (chan >= 0 && chan != dimm->cschannel)
1066 chan = -2;
1067 }
1068
1069 if (any_memory)
1070 strscpy(e->label, "any memory", sizeof(e->label));
1071 else if (!*e->label)
1072 strscpy(e->label, "unknown memory", sizeof(e->label));
1073
1074 edac_inc_csrow(e, row, chan);
1075
1076 /* Fill the RAM location data */
1077 p = e->location;
1078 end = p + sizeof(e->location);
1079 prefix = "";
1080
1081 for (i = 0; i < mci->n_layers; i++) {
1082 if (pos[i] < 0)
1083 continue;
1084
1085 p += scnprintf(p, end - p, "%s%s:%d", prefix,
1086 edac_layer_name[mci->layers[i].type], pos[i]);
1087 prefix = " ";
1088 }
1089
1090 edac_raw_mc_handle_error(e);
1091}
1092EXPORT_SYMBOL_GPL(edac_mc_handle_error);
1/*
2 * edac_mc kernel module
3 * (C) 2005, 2006 Linux Networx (http://lnxi.com)
4 * This file may be distributed under the terms of the
5 * GNU General Public License.
6 *
7 * Written by Thayne Harbaugh
8 * Based on work by Dan Hollis <goemon at anime dot net> and others.
9 * http://www.anime.net/~goemon/linux-ecc/
10 *
11 * Modified by Dave Peterson and Doug Thompson
12 *
13 */
14
15#include <linux/module.h>
16#include <linux/proc_fs.h>
17#include <linux/kernel.h>
18#include <linux/types.h>
19#include <linux/smp.h>
20#include <linux/init.h>
21#include <linux/sysctl.h>
22#include <linux/highmem.h>
23#include <linux/timer.h>
24#include <linux/slab.h>
25#include <linux/jiffies.h>
26#include <linux/spinlock.h>
27#include <linux/list.h>
28#include <linux/ctype.h>
29#include <linux/edac.h>
30#include <linux/bitops.h>
31#include <linux/uaccess.h>
32#include <asm/page.h>
33#include "edac_mc.h"
34#include "edac_module.h"
35#include <ras/ras_event.h>
36
37#ifdef CONFIG_EDAC_ATOMIC_SCRUB
38#include <asm/edac.h>
39#else
40#define edac_atomic_scrub(va, size) do { } while (0)
41#endif
42
43/* lock to memory controller's control array */
44static DEFINE_MUTEX(mem_ctls_mutex);
45static LIST_HEAD(mc_devices);
46
47/*
48 * Used to lock EDAC MC to just one module, avoiding two drivers e. g.
49 * apei/ghes and i7core_edac to be used at the same time.
50 */
51static void const *edac_mc_owner;
52
53static struct bus_type mc_bus[EDAC_MAX_MCS];
54
55unsigned edac_dimm_info_location(struct dimm_info *dimm, char *buf,
56 unsigned len)
57{
58 struct mem_ctl_info *mci = dimm->mci;
59 int i, n, count = 0;
60 char *p = buf;
61
62 for (i = 0; i < mci->n_layers; i++) {
63 n = snprintf(p, len, "%s %d ",
64 edac_layer_name[mci->layers[i].type],
65 dimm->location[i]);
66 p += n;
67 len -= n;
68 count += n;
69 if (!len)
70 break;
71 }
72
73 return count;
74}
75
76#ifdef CONFIG_EDAC_DEBUG
77
78static void edac_mc_dump_channel(struct rank_info *chan)
79{
80 edac_dbg(4, " channel->chan_idx = %d\n", chan->chan_idx);
81 edac_dbg(4, " channel = %p\n", chan);
82 edac_dbg(4, " channel->csrow = %p\n", chan->csrow);
83 edac_dbg(4, " channel->dimm = %p\n", chan->dimm);
84}
85
86static void edac_mc_dump_dimm(struct dimm_info *dimm, int number)
87{
88 char location[80];
89
90 edac_dimm_info_location(dimm, location, sizeof(location));
91
92 edac_dbg(4, "%s%i: %smapped as virtual row %d, chan %d\n",
93 dimm->mci->csbased ? "rank" : "dimm",
94 number, location, dimm->csrow, dimm->cschannel);
95 edac_dbg(4, " dimm = %p\n", dimm);
96 edac_dbg(4, " dimm->label = '%s'\n", dimm->label);
97 edac_dbg(4, " dimm->nr_pages = 0x%x\n", dimm->nr_pages);
98 edac_dbg(4, " dimm->grain = %d\n", dimm->grain);
99 edac_dbg(4, " dimm->nr_pages = 0x%x\n", dimm->nr_pages);
100}
101
102static void edac_mc_dump_csrow(struct csrow_info *csrow)
103{
104 edac_dbg(4, "csrow->csrow_idx = %d\n", csrow->csrow_idx);
105 edac_dbg(4, " csrow = %p\n", csrow);
106 edac_dbg(4, " csrow->first_page = 0x%lx\n", csrow->first_page);
107 edac_dbg(4, " csrow->last_page = 0x%lx\n", csrow->last_page);
108 edac_dbg(4, " csrow->page_mask = 0x%lx\n", csrow->page_mask);
109 edac_dbg(4, " csrow->nr_channels = %d\n", csrow->nr_channels);
110 edac_dbg(4, " csrow->channels = %p\n", csrow->channels);
111 edac_dbg(4, " csrow->mci = %p\n", csrow->mci);
112}
113
114static void edac_mc_dump_mci(struct mem_ctl_info *mci)
115{
116 edac_dbg(3, "\tmci = %p\n", mci);
117 edac_dbg(3, "\tmci->mtype_cap = %lx\n", mci->mtype_cap);
118 edac_dbg(3, "\tmci->edac_ctl_cap = %lx\n", mci->edac_ctl_cap);
119 edac_dbg(3, "\tmci->edac_cap = %lx\n", mci->edac_cap);
120 edac_dbg(4, "\tmci->edac_check = %p\n", mci->edac_check);
121 edac_dbg(3, "\tmci->nr_csrows = %d, csrows = %p\n",
122 mci->nr_csrows, mci->csrows);
123 edac_dbg(3, "\tmci->nr_dimms = %d, dimms = %p\n",
124 mci->tot_dimms, mci->dimms);
125 edac_dbg(3, "\tdev = %p\n", mci->pdev);
126 edac_dbg(3, "\tmod_name:ctl_name = %s:%s\n",
127 mci->mod_name, mci->ctl_name);
128 edac_dbg(3, "\tpvt_info = %p\n\n", mci->pvt_info);
129}
130
131#endif /* CONFIG_EDAC_DEBUG */
132
133const char * const edac_mem_types[] = {
134 [MEM_EMPTY] = "Empty csrow",
135 [MEM_RESERVED] = "Reserved csrow type",
136 [MEM_UNKNOWN] = "Unknown csrow type",
137 [MEM_FPM] = "Fast page mode RAM",
138 [MEM_EDO] = "Extended data out RAM",
139 [MEM_BEDO] = "Burst Extended data out RAM",
140 [MEM_SDR] = "Single data rate SDRAM",
141 [MEM_RDR] = "Registered single data rate SDRAM",
142 [MEM_DDR] = "Double data rate SDRAM",
143 [MEM_RDDR] = "Registered Double data rate SDRAM",
144 [MEM_RMBS] = "Rambus DRAM",
145 [MEM_DDR2] = "Unbuffered DDR2 RAM",
146 [MEM_FB_DDR2] = "Fully buffered DDR2",
147 [MEM_RDDR2] = "Registered DDR2 RAM",
148 [MEM_XDR] = "Rambus XDR",
149 [MEM_DDR3] = "Unbuffered DDR3 RAM",
150 [MEM_RDDR3] = "Registered DDR3 RAM",
151 [MEM_LRDDR3] = "Load-Reduced DDR3 RAM",
152 [MEM_DDR4] = "Unbuffered DDR4 RAM",
153 [MEM_RDDR4] = "Registered DDR4 RAM",
154};
155EXPORT_SYMBOL_GPL(edac_mem_types);
156
157/**
158 * edac_align_ptr - Prepares the pointer offsets for a single-shot allocation
159 * @p: pointer to a pointer with the memory offset to be used. At
160 * return, this will be incremented to point to the next offset
161 * @size: Size of the data structure to be reserved
162 * @n_elems: Number of elements that should be reserved
163 *
164 * If 'size' is a constant, the compiler will optimize this whole function
165 * down to either a no-op or the addition of a constant to the value of '*p'.
166 *
167 * The 'p' pointer is absolutely needed to keep the proper advancing
168 * further in memory to the proper offsets when allocating the struct along
169 * with its embedded structs, as edac_device_alloc_ctl_info() does it
170 * above, for example.
171 *
172 * At return, the pointer 'p' will be incremented to be used on a next call
173 * to this function.
174 */
175void *edac_align_ptr(void **p, unsigned size, int n_elems)
176{
177 unsigned align, r;
178 void *ptr = *p;
179
180 *p += size * n_elems;
181
182 /*
183 * 'p' can possibly be an unaligned item X such that sizeof(X) is
184 * 'size'. Adjust 'p' so that its alignment is at least as
185 * stringent as what the compiler would provide for X and return
186 * the aligned result.
187 * Here we assume that the alignment of a "long long" is the most
188 * stringent alignment that the compiler will ever provide by default.
189 * As far as I know, this is a reasonable assumption.
190 */
191 if (size > sizeof(long))
192 align = sizeof(long long);
193 else if (size > sizeof(int))
194 align = sizeof(long);
195 else if (size > sizeof(short))
196 align = sizeof(int);
197 else if (size > sizeof(char))
198 align = sizeof(short);
199 else
200 return (char *)ptr;
201
202 r = (unsigned long)p % align;
203
204 if (r == 0)
205 return (char *)ptr;
206
207 *p += align - r;
208
209 return (void *)(((unsigned long)ptr) + align - r);
210}
211
212static void _edac_mc_free(struct mem_ctl_info *mci)
213{
214 int i, chn, row;
215 struct csrow_info *csr;
216 const unsigned int tot_dimms = mci->tot_dimms;
217 const unsigned int tot_channels = mci->num_cschannel;
218 const unsigned int tot_csrows = mci->nr_csrows;
219
220 if (mci->dimms) {
221 for (i = 0; i < tot_dimms; i++)
222 kfree(mci->dimms[i]);
223 kfree(mci->dimms);
224 }
225 if (mci->csrows) {
226 for (row = 0; row < tot_csrows; row++) {
227 csr = mci->csrows[row];
228 if (csr) {
229 if (csr->channels) {
230 for (chn = 0; chn < tot_channels; chn++)
231 kfree(csr->channels[chn]);
232 kfree(csr->channels);
233 }
234 kfree(csr);
235 }
236 }
237 kfree(mci->csrows);
238 }
239 kfree(mci);
240}
241
242struct mem_ctl_info *edac_mc_alloc(unsigned mc_num,
243 unsigned n_layers,
244 struct edac_mc_layer *layers,
245 unsigned sz_pvt)
246{
247 struct mem_ctl_info *mci;
248 struct edac_mc_layer *layer;
249 struct csrow_info *csr;
250 struct rank_info *chan;
251 struct dimm_info *dimm;
252 u32 *ce_per_layer[EDAC_MAX_LAYERS], *ue_per_layer[EDAC_MAX_LAYERS];
253 unsigned pos[EDAC_MAX_LAYERS];
254 unsigned size, tot_dimms = 1, count = 1;
255 unsigned tot_csrows = 1, tot_channels = 1, tot_errcount = 0;
256 void *pvt, *p, *ptr = NULL;
257 int i, j, row, chn, n, len, off;
258 bool per_rank = false;
259
260 BUG_ON(n_layers > EDAC_MAX_LAYERS || n_layers == 0);
261 /*
262 * Calculate the total amount of dimms and csrows/cschannels while
263 * in the old API emulation mode
264 */
265 for (i = 0; i < n_layers; i++) {
266 tot_dimms *= layers[i].size;
267 if (layers[i].is_virt_csrow)
268 tot_csrows *= layers[i].size;
269 else
270 tot_channels *= layers[i].size;
271
272 if (layers[i].type == EDAC_MC_LAYER_CHIP_SELECT)
273 per_rank = true;
274 }
275
276 /* Figure out the offsets of the various items from the start of an mc
277 * structure. We want the alignment of each item to be at least as
278 * stringent as what the compiler would provide if we could simply
279 * hardcode everything into a single struct.
280 */
281 mci = edac_align_ptr(&ptr, sizeof(*mci), 1);
282 layer = edac_align_ptr(&ptr, sizeof(*layer), n_layers);
283 for (i = 0; i < n_layers; i++) {
284 count *= layers[i].size;
285 edac_dbg(4, "errcount layer %d size %d\n", i, count);
286 ce_per_layer[i] = edac_align_ptr(&ptr, sizeof(u32), count);
287 ue_per_layer[i] = edac_align_ptr(&ptr, sizeof(u32), count);
288 tot_errcount += 2 * count;
289 }
290
291 edac_dbg(4, "allocating %d error counters\n", tot_errcount);
292 pvt = edac_align_ptr(&ptr, sz_pvt, 1);
293 size = ((unsigned long)pvt) + sz_pvt;
294
295 edac_dbg(1, "allocating %u bytes for mci data (%d %s, %d csrows/channels)\n",
296 size,
297 tot_dimms,
298 per_rank ? "ranks" : "dimms",
299 tot_csrows * tot_channels);
300
301 mci = kzalloc(size, GFP_KERNEL);
302 if (mci == NULL)
303 return NULL;
304
305 /* Adjust pointers so they point within the memory we just allocated
306 * rather than an imaginary chunk of memory located at address 0.
307 */
308 layer = (struct edac_mc_layer *)(((char *)mci) + ((unsigned long)layer));
309 for (i = 0; i < n_layers; i++) {
310 mci->ce_per_layer[i] = (u32 *)((char *)mci + ((unsigned long)ce_per_layer[i]));
311 mci->ue_per_layer[i] = (u32 *)((char *)mci + ((unsigned long)ue_per_layer[i]));
312 }
313 pvt = sz_pvt ? (((char *)mci) + ((unsigned long)pvt)) : NULL;
314
315 /* setup index and various internal pointers */
316 mci->mc_idx = mc_num;
317 mci->tot_dimms = tot_dimms;
318 mci->pvt_info = pvt;
319 mci->n_layers = n_layers;
320 mci->layers = layer;
321 memcpy(mci->layers, layers, sizeof(*layer) * n_layers);
322 mci->nr_csrows = tot_csrows;
323 mci->num_cschannel = tot_channels;
324 mci->csbased = per_rank;
325
326 /*
327 * Alocate and fill the csrow/channels structs
328 */
329 mci->csrows = kcalloc(tot_csrows, sizeof(*mci->csrows), GFP_KERNEL);
330 if (!mci->csrows)
331 goto error;
332 for (row = 0; row < tot_csrows; row++) {
333 csr = kzalloc(sizeof(**mci->csrows), GFP_KERNEL);
334 if (!csr)
335 goto error;
336 mci->csrows[row] = csr;
337 csr->csrow_idx = row;
338 csr->mci = mci;
339 csr->nr_channels = tot_channels;
340 csr->channels = kcalloc(tot_channels, sizeof(*csr->channels),
341 GFP_KERNEL);
342 if (!csr->channels)
343 goto error;
344
345 for (chn = 0; chn < tot_channels; chn++) {
346 chan = kzalloc(sizeof(**csr->channels), GFP_KERNEL);
347 if (!chan)
348 goto error;
349 csr->channels[chn] = chan;
350 chan->chan_idx = chn;
351 chan->csrow = csr;
352 }
353 }
354
355 /*
356 * Allocate and fill the dimm structs
357 */
358 mci->dimms = kcalloc(tot_dimms, sizeof(*mci->dimms), GFP_KERNEL);
359 if (!mci->dimms)
360 goto error;
361
362 memset(&pos, 0, sizeof(pos));
363 row = 0;
364 chn = 0;
365 for (i = 0; i < tot_dimms; i++) {
366 chan = mci->csrows[row]->channels[chn];
367 off = EDAC_DIMM_OFF(layer, n_layers, pos[0], pos[1], pos[2]);
368 if (off < 0 || off >= tot_dimms) {
369 edac_mc_printk(mci, KERN_ERR, "EDAC core bug: EDAC_DIMM_OFF is trying to do an illegal data access\n");
370 goto error;
371 }
372
373 dimm = kzalloc(sizeof(**mci->dimms), GFP_KERNEL);
374 if (!dimm)
375 goto error;
376 mci->dimms[off] = dimm;
377 dimm->mci = mci;
378
379 /*
380 * Copy DIMM location and initialize it.
381 */
382 len = sizeof(dimm->label);
383 p = dimm->label;
384 n = snprintf(p, len, "mc#%u", mc_num);
385 p += n;
386 len -= n;
387 for (j = 0; j < n_layers; j++) {
388 n = snprintf(p, len, "%s#%u",
389 edac_layer_name[layers[j].type],
390 pos[j]);
391 p += n;
392 len -= n;
393 dimm->location[j] = pos[j];
394
395 if (len <= 0)
396 break;
397 }
398
399 /* Link it to the csrows old API data */
400 chan->dimm = dimm;
401 dimm->csrow = row;
402 dimm->cschannel = chn;
403
404 /* Increment csrow location */
405 if (layers[0].is_virt_csrow) {
406 chn++;
407 if (chn == tot_channels) {
408 chn = 0;
409 row++;
410 }
411 } else {
412 row++;
413 if (row == tot_csrows) {
414 row = 0;
415 chn++;
416 }
417 }
418
419 /* Increment dimm location */
420 for (j = n_layers - 1; j >= 0; j--) {
421 pos[j]++;
422 if (pos[j] < layers[j].size)
423 break;
424 pos[j] = 0;
425 }
426 }
427
428 mci->op_state = OP_ALLOC;
429
430 return mci;
431
432error:
433 _edac_mc_free(mci);
434
435 return NULL;
436}
437EXPORT_SYMBOL_GPL(edac_mc_alloc);
438
439void edac_mc_free(struct mem_ctl_info *mci)
440{
441 edac_dbg(1, "\n");
442
443 /* If we're not yet registered with sysfs free only what was allocated
444 * in edac_mc_alloc().
445 */
446 if (!device_is_registered(&mci->dev)) {
447 _edac_mc_free(mci);
448 return;
449 }
450
451 /* the mci instance is freed here, when the sysfs object is dropped */
452 edac_unregister_sysfs(mci);
453}
454EXPORT_SYMBOL_GPL(edac_mc_free);
455
456/* Caller must hold mem_ctls_mutex */
457static struct mem_ctl_info *__find_mci_by_dev(struct device *dev)
458{
459 struct mem_ctl_info *mci;
460 struct list_head *item;
461
462 edac_dbg(3, "\n");
463
464 list_for_each(item, &mc_devices) {
465 mci = list_entry(item, struct mem_ctl_info, link);
466
467 if (mci->pdev == dev)
468 return mci;
469 }
470
471 return NULL;
472}
473
474/**
475 * find_mci_by_dev
476 *
477 * scan list of controllers looking for the one that manages
478 * the 'dev' device
479 * @dev: pointer to a struct device related with the MCI
480 */
481struct mem_ctl_info *find_mci_by_dev(struct device *dev)
482{
483 struct mem_ctl_info *ret;
484
485 mutex_lock(&mem_ctls_mutex);
486 ret = __find_mci_by_dev(dev);
487 mutex_unlock(&mem_ctls_mutex);
488
489 return ret;
490}
491EXPORT_SYMBOL_GPL(find_mci_by_dev);
492
493/*
494 * handler for EDAC to check if NMI type handler has asserted interrupt
495 */
496static int edac_mc_assert_error_check_and_clear(void)
497{
498 int old_state;
499
500 if (edac_op_state == EDAC_OPSTATE_POLL)
501 return 1;
502
503 old_state = edac_err_assert;
504 edac_err_assert = 0;
505
506 return old_state;
507}
508
509/*
510 * edac_mc_workq_function
511 * performs the operation scheduled by a workq request
512 */
513static void edac_mc_workq_function(struct work_struct *work_req)
514{
515 struct delayed_work *d_work = to_delayed_work(work_req);
516 struct mem_ctl_info *mci = to_edac_mem_ctl_work(d_work);
517
518 mutex_lock(&mem_ctls_mutex);
519
520 if (mci->op_state != OP_RUNNING_POLL) {
521 mutex_unlock(&mem_ctls_mutex);
522 return;
523 }
524
525 if (edac_mc_assert_error_check_and_clear())
526 mci->edac_check(mci);
527
528 mutex_unlock(&mem_ctls_mutex);
529
530 /* Queue ourselves again. */
531 edac_queue_work(&mci->work, msecs_to_jiffies(edac_mc_get_poll_msec()));
532}
533
534/*
535 * edac_mc_reset_delay_period(unsigned long value)
536 *
537 * user space has updated our poll period value, need to
538 * reset our workq delays
539 */
540void edac_mc_reset_delay_period(unsigned long value)
541{
542 struct mem_ctl_info *mci;
543 struct list_head *item;
544
545 mutex_lock(&mem_ctls_mutex);
546
547 list_for_each(item, &mc_devices) {
548 mci = list_entry(item, struct mem_ctl_info, link);
549
550 if (mci->op_state == OP_RUNNING_POLL)
551 edac_mod_work(&mci->work, value);
552 }
553 mutex_unlock(&mem_ctls_mutex);
554}
555
556
557
558/* Return 0 on success, 1 on failure.
559 * Before calling this function, caller must
560 * assign a unique value to mci->mc_idx.
561 *
562 * locking model:
563 *
564 * called with the mem_ctls_mutex lock held
565 */
566static int add_mc_to_global_list(struct mem_ctl_info *mci)
567{
568 struct list_head *item, *insert_before;
569 struct mem_ctl_info *p;
570
571 insert_before = &mc_devices;
572
573 p = __find_mci_by_dev(mci->pdev);
574 if (unlikely(p != NULL))
575 goto fail0;
576
577 list_for_each(item, &mc_devices) {
578 p = list_entry(item, struct mem_ctl_info, link);
579
580 if (p->mc_idx >= mci->mc_idx) {
581 if (unlikely(p->mc_idx == mci->mc_idx))
582 goto fail1;
583
584 insert_before = item;
585 break;
586 }
587 }
588
589 list_add_tail_rcu(&mci->link, insert_before);
590 atomic_inc(&edac_handlers);
591 return 0;
592
593fail0:
594 edac_printk(KERN_WARNING, EDAC_MC,
595 "%s (%s) %s %s already assigned %d\n", dev_name(p->pdev),
596 edac_dev_name(mci), p->mod_name, p->ctl_name, p->mc_idx);
597 return 1;
598
599fail1:
600 edac_printk(KERN_WARNING, EDAC_MC,
601 "bug in low-level driver: attempt to assign\n"
602 " duplicate mc_idx %d in %s()\n", p->mc_idx, __func__);
603 return 1;
604}
605
606static int del_mc_from_global_list(struct mem_ctl_info *mci)
607{
608 int handlers = atomic_dec_return(&edac_handlers);
609 list_del_rcu(&mci->link);
610
611 /* these are for safe removal of devices from global list while
612 * NMI handlers may be traversing list
613 */
614 synchronize_rcu();
615 INIT_LIST_HEAD(&mci->link);
616
617 return handlers;
618}
619
620struct mem_ctl_info *edac_mc_find(int idx)
621{
622 struct mem_ctl_info *mci = NULL;
623 struct list_head *item;
624
625 mutex_lock(&mem_ctls_mutex);
626
627 list_for_each(item, &mc_devices) {
628 mci = list_entry(item, struct mem_ctl_info, link);
629
630 if (mci->mc_idx >= idx) {
631 if (mci->mc_idx == idx) {
632 goto unlock;
633 }
634 break;
635 }
636 }
637
638unlock:
639 mutex_unlock(&mem_ctls_mutex);
640 return mci;
641}
642EXPORT_SYMBOL(edac_mc_find);
643
644
645/* FIXME - should a warning be printed if no error detection? correction? */
646int edac_mc_add_mc_with_groups(struct mem_ctl_info *mci,
647 const struct attribute_group **groups)
648{
649 int ret = -EINVAL;
650 edac_dbg(0, "\n");
651
652 if (mci->mc_idx >= EDAC_MAX_MCS) {
653 pr_warn_once("Too many memory controllers: %d\n", mci->mc_idx);
654 return -ENODEV;
655 }
656
657#ifdef CONFIG_EDAC_DEBUG
658 if (edac_debug_level >= 3)
659 edac_mc_dump_mci(mci);
660
661 if (edac_debug_level >= 4) {
662 int i;
663
664 for (i = 0; i < mci->nr_csrows; i++) {
665 struct csrow_info *csrow = mci->csrows[i];
666 u32 nr_pages = 0;
667 int j;
668
669 for (j = 0; j < csrow->nr_channels; j++)
670 nr_pages += csrow->channels[j]->dimm->nr_pages;
671 if (!nr_pages)
672 continue;
673 edac_mc_dump_csrow(csrow);
674 for (j = 0; j < csrow->nr_channels; j++)
675 if (csrow->channels[j]->dimm->nr_pages)
676 edac_mc_dump_channel(csrow->channels[j]);
677 }
678 for (i = 0; i < mci->tot_dimms; i++)
679 if (mci->dimms[i]->nr_pages)
680 edac_mc_dump_dimm(mci->dimms[i], i);
681 }
682#endif
683 mutex_lock(&mem_ctls_mutex);
684
685 if (edac_mc_owner && edac_mc_owner != mci->mod_name) {
686 ret = -EPERM;
687 goto fail0;
688 }
689
690 if (add_mc_to_global_list(mci))
691 goto fail0;
692
693 /* set load time so that error rate can be tracked */
694 mci->start_time = jiffies;
695
696 mci->bus = &mc_bus[mci->mc_idx];
697
698 if (edac_create_sysfs_mci_device(mci, groups)) {
699 edac_mc_printk(mci, KERN_WARNING,
700 "failed to create sysfs device\n");
701 goto fail1;
702 }
703
704 if (mci->edac_check) {
705 mci->op_state = OP_RUNNING_POLL;
706
707 INIT_DELAYED_WORK(&mci->work, edac_mc_workq_function);
708 edac_queue_work(&mci->work, msecs_to_jiffies(edac_mc_get_poll_msec()));
709
710 } else {
711 mci->op_state = OP_RUNNING_INTERRUPT;
712 }
713
714 /* Report action taken */
715 edac_mc_printk(mci, KERN_INFO,
716 "Giving out device to module %s controller %s: DEV %s (%s)\n",
717 mci->mod_name, mci->ctl_name, mci->dev_name,
718 edac_op_state_to_string(mci->op_state));
719
720 edac_mc_owner = mci->mod_name;
721
722 mutex_unlock(&mem_ctls_mutex);
723 return 0;
724
725fail1:
726 del_mc_from_global_list(mci);
727
728fail0:
729 mutex_unlock(&mem_ctls_mutex);
730 return ret;
731}
732EXPORT_SYMBOL_GPL(edac_mc_add_mc_with_groups);
733
734struct mem_ctl_info *edac_mc_del_mc(struct device *dev)
735{
736 struct mem_ctl_info *mci;
737
738 edac_dbg(0, "\n");
739
740 mutex_lock(&mem_ctls_mutex);
741
742 /* find the requested mci struct in the global list */
743 mci = __find_mci_by_dev(dev);
744 if (mci == NULL) {
745 mutex_unlock(&mem_ctls_mutex);
746 return NULL;
747 }
748
749 /* mark MCI offline: */
750 mci->op_state = OP_OFFLINE;
751
752 if (!del_mc_from_global_list(mci))
753 edac_mc_owner = NULL;
754
755 mutex_unlock(&mem_ctls_mutex);
756
757 if (mci->edac_check)
758 edac_stop_work(&mci->work);
759
760 /* remove from sysfs */
761 edac_remove_sysfs_mci_device(mci);
762
763 edac_printk(KERN_INFO, EDAC_MC,
764 "Removed device %d for %s %s: DEV %s\n", mci->mc_idx,
765 mci->mod_name, mci->ctl_name, edac_dev_name(mci));
766
767 return mci;
768}
769EXPORT_SYMBOL_GPL(edac_mc_del_mc);
770
771static void edac_mc_scrub_block(unsigned long page, unsigned long offset,
772 u32 size)
773{
774 struct page *pg;
775 void *virt_addr;
776 unsigned long flags = 0;
777
778 edac_dbg(3, "\n");
779
780 /* ECC error page was not in our memory. Ignore it. */
781 if (!pfn_valid(page))
782 return;
783
784 /* Find the actual page structure then map it and fix */
785 pg = pfn_to_page(page);
786
787 if (PageHighMem(pg))
788 local_irq_save(flags);
789
790 virt_addr = kmap_atomic(pg);
791
792 /* Perform architecture specific atomic scrub operation */
793 edac_atomic_scrub(virt_addr + offset, size);
794
795 /* Unmap and complete */
796 kunmap_atomic(virt_addr);
797
798 if (PageHighMem(pg))
799 local_irq_restore(flags);
800}
801
802/* FIXME - should return -1 */
803int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci, unsigned long page)
804{
805 struct csrow_info **csrows = mci->csrows;
806 int row, i, j, n;
807
808 edac_dbg(1, "MC%d: 0x%lx\n", mci->mc_idx, page);
809 row = -1;
810
811 for (i = 0; i < mci->nr_csrows; i++) {
812 struct csrow_info *csrow = csrows[i];
813 n = 0;
814 for (j = 0; j < csrow->nr_channels; j++) {
815 struct dimm_info *dimm = csrow->channels[j]->dimm;
816 n += dimm->nr_pages;
817 }
818 if (n == 0)
819 continue;
820
821 edac_dbg(3, "MC%d: first(0x%lx) page(0x%lx) last(0x%lx) mask(0x%lx)\n",
822 mci->mc_idx,
823 csrow->first_page, page, csrow->last_page,
824 csrow->page_mask);
825
826 if ((page >= csrow->first_page) &&
827 (page <= csrow->last_page) &&
828 ((page & csrow->page_mask) ==
829 (csrow->first_page & csrow->page_mask))) {
830 row = i;
831 break;
832 }
833 }
834
835 if (row == -1)
836 edac_mc_printk(mci, KERN_ERR,
837 "could not look up page error address %lx\n",
838 (unsigned long)page);
839
840 return row;
841}
842EXPORT_SYMBOL_GPL(edac_mc_find_csrow_by_page);
843
844const char *edac_layer_name[] = {
845 [EDAC_MC_LAYER_BRANCH] = "branch",
846 [EDAC_MC_LAYER_CHANNEL] = "channel",
847 [EDAC_MC_LAYER_SLOT] = "slot",
848 [EDAC_MC_LAYER_CHIP_SELECT] = "csrow",
849 [EDAC_MC_LAYER_ALL_MEM] = "memory",
850};
851EXPORT_SYMBOL_GPL(edac_layer_name);
852
853static void edac_inc_ce_error(struct mem_ctl_info *mci,
854 bool enable_per_layer_report,
855 const int pos[EDAC_MAX_LAYERS],
856 const u16 count)
857{
858 int i, index = 0;
859
860 mci->ce_mc += count;
861
862 if (!enable_per_layer_report) {
863 mci->ce_noinfo_count += count;
864 return;
865 }
866
867 for (i = 0; i < mci->n_layers; i++) {
868 if (pos[i] < 0)
869 break;
870 index += pos[i];
871 mci->ce_per_layer[i][index] += count;
872
873 if (i < mci->n_layers - 1)
874 index *= mci->layers[i + 1].size;
875 }
876}
877
878static void edac_inc_ue_error(struct mem_ctl_info *mci,
879 bool enable_per_layer_report,
880 const int pos[EDAC_MAX_LAYERS],
881 const u16 count)
882{
883 int i, index = 0;
884
885 mci->ue_mc += count;
886
887 if (!enable_per_layer_report) {
888 mci->ue_noinfo_count += count;
889 return;
890 }
891
892 for (i = 0; i < mci->n_layers; i++) {
893 if (pos[i] < 0)
894 break;
895 index += pos[i];
896 mci->ue_per_layer[i][index] += count;
897
898 if (i < mci->n_layers - 1)
899 index *= mci->layers[i + 1].size;
900 }
901}
902
903static void edac_ce_error(struct mem_ctl_info *mci,
904 const u16 error_count,
905 const int pos[EDAC_MAX_LAYERS],
906 const char *msg,
907 const char *location,
908 const char *label,
909 const char *detail,
910 const char *other_detail,
911 const bool enable_per_layer_report,
912 const unsigned long page_frame_number,
913 const unsigned long offset_in_page,
914 long grain)
915{
916 unsigned long remapped_page;
917 char *msg_aux = "";
918
919 if (*msg)
920 msg_aux = " ";
921
922 if (edac_mc_get_log_ce()) {
923 if (other_detail && *other_detail)
924 edac_mc_printk(mci, KERN_WARNING,
925 "%d CE %s%son %s (%s %s - %s)\n",
926 error_count, msg, msg_aux, label,
927 location, detail, other_detail);
928 else
929 edac_mc_printk(mci, KERN_WARNING,
930 "%d CE %s%son %s (%s %s)\n",
931 error_count, msg, msg_aux, label,
932 location, detail);
933 }
934 edac_inc_ce_error(mci, enable_per_layer_report, pos, error_count);
935
936 if (mci->scrub_mode == SCRUB_SW_SRC) {
937 /*
938 * Some memory controllers (called MCs below) can remap
939 * memory so that it is still available at a different
940 * address when PCI devices map into memory.
941 * MC's that can't do this, lose the memory where PCI
942 * devices are mapped. This mapping is MC-dependent
943 * and so we call back into the MC driver for it to
944 * map the MC page to a physical (CPU) page which can
945 * then be mapped to a virtual page - which can then
946 * be scrubbed.
947 */
948 remapped_page = mci->ctl_page_to_phys ?
949 mci->ctl_page_to_phys(mci, page_frame_number) :
950 page_frame_number;
951
952 edac_mc_scrub_block(remapped_page,
953 offset_in_page, grain);
954 }
955}
956
957static void edac_ue_error(struct mem_ctl_info *mci,
958 const u16 error_count,
959 const int pos[EDAC_MAX_LAYERS],
960 const char *msg,
961 const char *location,
962 const char *label,
963 const char *detail,
964 const char *other_detail,
965 const bool enable_per_layer_report)
966{
967 char *msg_aux = "";
968
969 if (*msg)
970 msg_aux = " ";
971
972 if (edac_mc_get_log_ue()) {
973 if (other_detail && *other_detail)
974 edac_mc_printk(mci, KERN_WARNING,
975 "%d UE %s%son %s (%s %s - %s)\n",
976 error_count, msg, msg_aux, label,
977 location, detail, other_detail);
978 else
979 edac_mc_printk(mci, KERN_WARNING,
980 "%d UE %s%son %s (%s %s)\n",
981 error_count, msg, msg_aux, label,
982 location, detail);
983 }
984
985 if (edac_mc_get_panic_on_ue()) {
986 if (other_detail && *other_detail)
987 panic("UE %s%son %s (%s%s - %s)\n",
988 msg, msg_aux, label, location, detail, other_detail);
989 else
990 panic("UE %s%son %s (%s%s)\n",
991 msg, msg_aux, label, location, detail);
992 }
993
994 edac_inc_ue_error(mci, enable_per_layer_report, pos, error_count);
995}
996
997void edac_raw_mc_handle_error(const enum hw_event_mc_err_type type,
998 struct mem_ctl_info *mci,
999 struct edac_raw_error_desc *e)
1000{
1001 char detail[80];
1002 int pos[EDAC_MAX_LAYERS] = { e->top_layer, e->mid_layer, e->low_layer };
1003
1004 /* Memory type dependent details about the error */
1005 if (type == HW_EVENT_ERR_CORRECTED) {
1006 snprintf(detail, sizeof(detail),
1007 "page:0x%lx offset:0x%lx grain:%ld syndrome:0x%lx",
1008 e->page_frame_number, e->offset_in_page,
1009 e->grain, e->syndrome);
1010 edac_ce_error(mci, e->error_count, pos, e->msg, e->location, e->label,
1011 detail, e->other_detail, e->enable_per_layer_report,
1012 e->page_frame_number, e->offset_in_page, e->grain);
1013 } else {
1014 snprintf(detail, sizeof(detail),
1015 "page:0x%lx offset:0x%lx grain:%ld",
1016 e->page_frame_number, e->offset_in_page, e->grain);
1017
1018 edac_ue_error(mci, e->error_count, pos, e->msg, e->location, e->label,
1019 detail, e->other_detail, e->enable_per_layer_report);
1020 }
1021
1022
1023}
1024EXPORT_SYMBOL_GPL(edac_raw_mc_handle_error);
1025
1026void edac_mc_handle_error(const enum hw_event_mc_err_type type,
1027 struct mem_ctl_info *mci,
1028 const u16 error_count,
1029 const unsigned long page_frame_number,
1030 const unsigned long offset_in_page,
1031 const unsigned long syndrome,
1032 const int top_layer,
1033 const int mid_layer,
1034 const int low_layer,
1035 const char *msg,
1036 const char *other_detail)
1037{
1038 char *p;
1039 int row = -1, chan = -1;
1040 int pos[EDAC_MAX_LAYERS] = { top_layer, mid_layer, low_layer };
1041 int i, n_labels = 0;
1042 u8 grain_bits;
1043 struct edac_raw_error_desc *e = &mci->error_desc;
1044
1045 edac_dbg(3, "MC%d\n", mci->mc_idx);
1046
1047 /* Fills the error report buffer */
1048 memset(e, 0, sizeof (*e));
1049 e->error_count = error_count;
1050 e->top_layer = top_layer;
1051 e->mid_layer = mid_layer;
1052 e->low_layer = low_layer;
1053 e->page_frame_number = page_frame_number;
1054 e->offset_in_page = offset_in_page;
1055 e->syndrome = syndrome;
1056 e->msg = msg;
1057 e->other_detail = other_detail;
1058
1059 /*
1060 * Check if the event report is consistent and if the memory
1061 * location is known. If it is known, enable_per_layer_report will be
1062 * true, the DIMM(s) label info will be filled and the per-layer
1063 * error counters will be incremented.
1064 */
1065 for (i = 0; i < mci->n_layers; i++) {
1066 if (pos[i] >= (int)mci->layers[i].size) {
1067
1068 edac_mc_printk(mci, KERN_ERR,
1069 "INTERNAL ERROR: %s value is out of range (%d >= %d)\n",
1070 edac_layer_name[mci->layers[i].type],
1071 pos[i], mci->layers[i].size);
1072 /*
1073 * Instead of just returning it, let's use what's
1074 * known about the error. The increment routines and
1075 * the DIMM filter logic will do the right thing by
1076 * pointing the likely damaged DIMMs.
1077 */
1078 pos[i] = -1;
1079 }
1080 if (pos[i] >= 0)
1081 e->enable_per_layer_report = true;
1082 }
1083
1084 /*
1085 * Get the dimm label/grain that applies to the match criteria.
1086 * As the error algorithm may not be able to point to just one memory
1087 * stick, the logic here will get all possible labels that could
1088 * pottentially be affected by the error.
1089 * On FB-DIMM memory controllers, for uncorrected errors, it is common
1090 * to have only the MC channel and the MC dimm (also called "branch")
1091 * but the channel is not known, as the memory is arranged in pairs,
1092 * where each memory belongs to a separate channel within the same
1093 * branch.
1094 */
1095 p = e->label;
1096 *p = '\0';
1097
1098 for (i = 0; i < mci->tot_dimms; i++) {
1099 struct dimm_info *dimm = mci->dimms[i];
1100
1101 if (top_layer >= 0 && top_layer != dimm->location[0])
1102 continue;
1103 if (mid_layer >= 0 && mid_layer != dimm->location[1])
1104 continue;
1105 if (low_layer >= 0 && low_layer != dimm->location[2])
1106 continue;
1107
1108 /* get the max grain, over the error match range */
1109 if (dimm->grain > e->grain)
1110 e->grain = dimm->grain;
1111
1112 /*
1113 * If the error is memory-controller wide, there's no need to
1114 * seek for the affected DIMMs because the whole
1115 * channel/memory controller/... may be affected.
1116 * Also, don't show errors for empty DIMM slots.
1117 */
1118 if (e->enable_per_layer_report && dimm->nr_pages) {
1119 if (n_labels >= EDAC_MAX_LABELS) {
1120 e->enable_per_layer_report = false;
1121 break;
1122 }
1123 n_labels++;
1124 if (p != e->label) {
1125 strcpy(p, OTHER_LABEL);
1126 p += strlen(OTHER_LABEL);
1127 }
1128 strcpy(p, dimm->label);
1129 p += strlen(p);
1130 *p = '\0';
1131
1132 /*
1133 * get csrow/channel of the DIMM, in order to allow
1134 * incrementing the compat API counters
1135 */
1136 edac_dbg(4, "%s csrows map: (%d,%d)\n",
1137 mci->csbased ? "rank" : "dimm",
1138 dimm->csrow, dimm->cschannel);
1139 if (row == -1)
1140 row = dimm->csrow;
1141 else if (row >= 0 && row != dimm->csrow)
1142 row = -2;
1143
1144 if (chan == -1)
1145 chan = dimm->cschannel;
1146 else if (chan >= 0 && chan != dimm->cschannel)
1147 chan = -2;
1148 }
1149 }
1150
1151 if (!e->enable_per_layer_report) {
1152 strcpy(e->label, "any memory");
1153 } else {
1154 edac_dbg(4, "csrow/channel to increment: (%d,%d)\n", row, chan);
1155 if (p == e->label)
1156 strcpy(e->label, "unknown memory");
1157 if (type == HW_EVENT_ERR_CORRECTED) {
1158 if (row >= 0) {
1159 mci->csrows[row]->ce_count += error_count;
1160 if (chan >= 0)
1161 mci->csrows[row]->channels[chan]->ce_count += error_count;
1162 }
1163 } else
1164 if (row >= 0)
1165 mci->csrows[row]->ue_count += error_count;
1166 }
1167
1168 /* Fill the RAM location data */
1169 p = e->location;
1170
1171 for (i = 0; i < mci->n_layers; i++) {
1172 if (pos[i] < 0)
1173 continue;
1174
1175 p += sprintf(p, "%s:%d ",
1176 edac_layer_name[mci->layers[i].type],
1177 pos[i]);
1178 }
1179 if (p > e->location)
1180 *(p - 1) = '\0';
1181
1182 /* Report the error via the trace interface */
1183 grain_bits = fls_long(e->grain) + 1;
1184 trace_mc_event(type, e->msg, e->label, e->error_count,
1185 mci->mc_idx, e->top_layer, e->mid_layer, e->low_layer,
1186 (e->page_frame_number << PAGE_SHIFT) | e->offset_in_page,
1187 grain_bits, e->syndrome, e->other_detail);
1188
1189 edac_raw_mc_handle_error(type, mci, e);
1190}
1191EXPORT_SYMBOL_GPL(edac_mc_handle_error);