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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (C) 2012-2015 Altera Corporation
4 */
5#include <linux/irqchip.h>
6#include <linux/of.h>
7#include <linux/of_address.h>
8#include <linux/reboot.h>
9#include <linux/reset/socfpga.h>
10
11#include <asm/mach/arch.h>
12#include <asm/mach/map.h>
13#include <asm/cacheflush.h>
14
15#include "core.h"
16
17void __iomem *sys_manager_base_addr;
18void __iomem *rst_manager_base_addr;
19void __iomem *sdr_ctl_base_addr;
20unsigned long socfpga_cpu1start_addr;
21
22static void __init socfpga_sysmgr_init(void)
23{
24 struct device_node *np;
25
26 np = of_find_compatible_node(NULL, NULL, "altr,sys-mgr");
27
28 if (of_property_read_u32(np, "cpu1-start-addr",
29 (u32 *) &socfpga_cpu1start_addr))
30 pr_err("SMP: Need cpu1-start-addr in device tree.\n");
31
32 /* Ensure that socfpga_cpu1start_addr is visible to other CPUs */
33 smp_wmb();
34 sync_cache_w(&socfpga_cpu1start_addr);
35
36 sys_manager_base_addr = of_iomap(np, 0);
37
38 np = of_find_compatible_node(NULL, NULL, "altr,rst-mgr");
39 rst_manager_base_addr = of_iomap(np, 0);
40
41 np = of_find_compatible_node(NULL, NULL, "altr,sdr-ctl");
42 sdr_ctl_base_addr = of_iomap(np, 0);
43}
44
45static void __init socfpga_init_irq(void)
46{
47 irqchip_init();
48 socfpga_sysmgr_init();
49 if (IS_ENABLED(CONFIG_EDAC_ALTERA_L2C))
50 socfpga_init_l2_ecc();
51
52 if (IS_ENABLED(CONFIG_EDAC_ALTERA_OCRAM))
53 socfpga_init_ocram_ecc();
54 socfpga_reset_init();
55}
56
57static void __init socfpga_arria10_init_irq(void)
58{
59 irqchip_init();
60 socfpga_sysmgr_init();
61 if (IS_ENABLED(CONFIG_EDAC_ALTERA_L2C))
62 socfpga_init_arria10_l2_ecc();
63 if (IS_ENABLED(CONFIG_EDAC_ALTERA_OCRAM))
64 socfpga_init_arria10_ocram_ecc();
65 socfpga_reset_init();
66}
67
68static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd)
69{
70 u32 temp;
71
72 temp = readl(rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL);
73
74 if (mode == REBOOT_WARM)
75 temp |= RSTMGR_CTRL_SWWARMRSTREQ;
76 else
77 temp |= RSTMGR_CTRL_SWCOLDRSTREQ;
78 writel(temp, rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL);
79}
80
81static void socfpga_arria10_restart(enum reboot_mode mode, const char *cmd)
82{
83 u32 temp;
84
85 temp = readl(rst_manager_base_addr + SOCFPGA_A10_RSTMGR_CTRL);
86
87 if (mode == REBOOT_WARM)
88 temp |= RSTMGR_CTRL_SWWARMRSTREQ;
89 else
90 temp |= RSTMGR_CTRL_SWCOLDRSTREQ;
91 writel(temp, rst_manager_base_addr + SOCFPGA_A10_RSTMGR_CTRL);
92}
93
94static const char *altera_dt_match[] = {
95 "altr,socfpga",
96 NULL
97};
98
99DT_MACHINE_START(SOCFPGA, "Altera SOCFPGA")
100 .l2c_aux_val = 0,
101 .l2c_aux_mask = ~0,
102 .init_irq = socfpga_init_irq,
103 .restart = socfpga_cyclone5_restart,
104 .dt_compat = altera_dt_match,
105MACHINE_END
106
107static const char *altera_a10_dt_match[] = {
108 "altr,socfpga-arria10",
109 NULL
110};
111
112DT_MACHINE_START(SOCFPGA_A10, "Altera SOCFPGA Arria10")
113 .l2c_aux_val = 0,
114 .l2c_aux_mask = ~0,
115 .init_irq = socfpga_arria10_init_irq,
116 .restart = socfpga_arria10_restart,
117 .dt_compat = altera_a10_dt_match,
118MACHINE_END
1/*
2 * Copyright (C) 2012-2015 Altera Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17#include <linux/irqchip.h>
18#include <linux/of_address.h>
19#include <linux/of_irq.h>
20#include <linux/of_platform.h>
21#include <linux/reboot.h>
22
23#include <asm/hardware/cache-l2x0.h>
24#include <asm/mach/arch.h>
25#include <asm/mach/map.h>
26#include <asm/cacheflush.h>
27
28#include "core.h"
29
30void __iomem *sys_manager_base_addr;
31void __iomem *rst_manager_base_addr;
32void __iomem *sdr_ctl_base_addr;
33unsigned long socfpga_cpu1start_addr;
34
35void __init socfpga_sysmgr_init(void)
36{
37 struct device_node *np;
38
39 np = of_find_compatible_node(NULL, NULL, "altr,sys-mgr");
40
41 if (of_property_read_u32(np, "cpu1-start-addr",
42 (u32 *) &socfpga_cpu1start_addr))
43 pr_err("SMP: Need cpu1-start-addr in device tree.\n");
44
45 /* Ensure that socfpga_cpu1start_addr is visible to other CPUs */
46 smp_wmb();
47 sync_cache_w(&socfpga_cpu1start_addr);
48
49 sys_manager_base_addr = of_iomap(np, 0);
50
51 np = of_find_compatible_node(NULL, NULL, "altr,rst-mgr");
52 rst_manager_base_addr = of_iomap(np, 0);
53
54 np = of_find_compatible_node(NULL, NULL, "altr,sdr-ctl");
55 sdr_ctl_base_addr = of_iomap(np, 0);
56}
57
58static void __init socfpga_init_irq(void)
59{
60 irqchip_init();
61 socfpga_sysmgr_init();
62 if (IS_ENABLED(CONFIG_EDAC_ALTERA_L2C))
63 socfpga_init_l2_ecc();
64
65 if (IS_ENABLED(CONFIG_EDAC_ALTERA_OCRAM))
66 socfpga_init_ocram_ecc();
67}
68
69static void __init socfpga_arria10_init_irq(void)
70{
71 irqchip_init();
72 socfpga_sysmgr_init();
73 if (IS_ENABLED(CONFIG_EDAC_ALTERA_L2C))
74 socfpga_init_arria10_l2_ecc();
75 if (IS_ENABLED(CONFIG_EDAC_ALTERA_OCRAM))
76 socfpga_init_arria10_ocram_ecc();
77}
78
79static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd)
80{
81 u32 temp;
82
83 temp = readl(rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL);
84
85 if (mode == REBOOT_HARD)
86 temp |= RSTMGR_CTRL_SWCOLDRSTREQ;
87 else
88 temp |= RSTMGR_CTRL_SWWARMRSTREQ;
89 writel(temp, rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL);
90}
91
92static void socfpga_arria10_restart(enum reboot_mode mode, const char *cmd)
93{
94 u32 temp;
95
96 temp = readl(rst_manager_base_addr + SOCFPGA_A10_RSTMGR_CTRL);
97
98 if (mode == REBOOT_HARD)
99 temp |= RSTMGR_CTRL_SWCOLDRSTREQ;
100 else
101 temp |= RSTMGR_CTRL_SWWARMRSTREQ;
102 writel(temp, rst_manager_base_addr + SOCFPGA_A10_RSTMGR_CTRL);
103}
104
105static const char *altera_dt_match[] = {
106 "altr,socfpga",
107 NULL
108};
109
110DT_MACHINE_START(SOCFPGA, "Altera SOCFPGA")
111 .l2c_aux_val = 0,
112 .l2c_aux_mask = ~0,
113 .init_irq = socfpga_init_irq,
114 .restart = socfpga_cyclone5_restart,
115 .dt_compat = altera_dt_match,
116MACHINE_END
117
118static const char *altera_a10_dt_match[] = {
119 "altr,socfpga-arria10",
120 NULL
121};
122
123DT_MACHINE_START(SOCFPGA_A10, "Altera SOCFPGA Arria10")
124 .l2c_aux_val = 0,
125 .l2c_aux_mask = ~0,
126 .init_irq = socfpga_arria10_init_irq,
127 .restart = socfpga_arria10_restart,
128 .dt_compat = altera_a10_dt_match,
129MACHINE_END