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1/*
2 * Copyright (C) 2014 STMicroelectronics R&D Limited
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8#include <dt-bindings/clock/stih410-clks.h>
9/ {
10 clocks {
11 #address-cells = <1>;
12 #size-cells = <1>;
13 ranges;
14
15 compatible = "st,stih410-clk", "simple-bus";
16
17 /*
18 * Fixed 30MHz oscillator inputs to SoC
19 */
20 clk_sysin: clk-sysin {
21 #clock-cells = <0>;
22 compatible = "fixed-clock";
23 clock-frequency = <30000000>;
24 clock-output-names = "CLK_SYSIN";
25 };
26
27 /*
28 * ARM Peripheral clock for timers
29 */
30 arm_periph_clk: clk-m-a9-periphs {
31 #clock-cells = <0>;
32 compatible = "fixed-factor-clock";
33 clocks = <&clk_m_a9>;
34 clock-div = <2>;
35 clock-mult = <1>;
36 };
37
38 /*
39 * A9 PLL.
40 */
41 clockgen-a9@92b0000 {
42 compatible = "st,clkgen-c32";
43 reg = <0x92b0000 0xffff>;
44
45 clockgen_a9_pll: clockgen-a9-pll {
46 #clock-cells = <1>;
47 compatible = "st,stih407-clkgen-plla9";
48
49 clocks = <&clk_sysin>;
50
51 clock-output-names = "clockgen-a9-pll-odf";
52 };
53 };
54
55 /*
56 * ARM CPU related clocks.
57 */
58 clk_m_a9: clk-m-a9@92b0000 {
59 #clock-cells = <0>;
60 compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux";
61 reg = <0x92b0000 0x10000>;
62
63 clocks = <&clockgen_a9_pll 0>,
64 <&clockgen_a9_pll 0>,
65 <&clk_s_c0_flexgen 13>,
66 <&clk_m_a9_ext2f_div2>;
67 };
68
69 /*
70 * ARM Peripheral clock for timers
71 */
72 clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
73 #clock-cells = <0>;
74 compatible = "fixed-factor-clock";
75
76 clocks = <&clk_s_c0_flexgen 13>;
77
78 clock-output-names = "clk-m-a9-ext2f-div2";
79
80 clock-div = <2>;
81 clock-mult = <1>;
82 };
83
84 /*
85 * Bootloader initialized system infrastructure clock for
86 * serial devices.
87 */
88 clk_ext2f_a9: clockgen-c0@13 {
89 #clock-cells = <0>;
90 compatible = "fixed-clock";
91 clock-frequency = <200000000>;
92 clock-output-names = "clk-s-icn-reg-0";
93 };
94
95 clockgen-a@090ff000 {
96 compatible = "st,clkgen-c32";
97 reg = <0x90ff000 0x1000>;
98
99 clk_s_a0_pll: clk-s-a0-pll {
100 #clock-cells = <1>;
101 compatible = "st,clkgen-pll0";
102
103 clocks = <&clk_sysin>;
104
105 clock-output-names = "clk-s-a0-pll-ofd-0";
106 clock-critical = <0>; /* clk-s-a0-pll-ofd-0 */
107 };
108
109 clk_s_a0_flexgen: clk-s-a0-flexgen {
110 compatible = "st,flexgen";
111
112 #clock-cells = <1>;
113
114 clocks = <&clk_s_a0_pll 0>,
115 <&clk_sysin>;
116
117 clock-output-names = "clk-ic-lmi0",
118 "clk-ic-lmi1";
119 clock-critical = <CLK_IC_LMI0>;
120 };
121 };
122
123 clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
124 #clock-cells = <1>;
125 compatible = "st,quadfs-pll";
126 reg = <0x9103000 0x1000>;
127
128 clocks = <&clk_sysin>;
129
130 clock-output-names = "clk-s-c0-fs0-ch0",
131 "clk-s-c0-fs0-ch1",
132 "clk-s-c0-fs0-ch2",
133 "clk-s-c0-fs0-ch3";
134 clock-critical = <0>; /* clk-s-c0-fs0-ch0 */
135 };
136
137 clk_s_c0: clockgen-c@09103000 {
138 compatible = "st,clkgen-c32";
139 reg = <0x9103000 0x1000>;
140
141 clk_s_c0_pll0: clk-s-c0-pll0 {
142 #clock-cells = <1>;
143 compatible = "st,clkgen-pll0";
144
145 clocks = <&clk_sysin>;
146
147 clock-output-names = "clk-s-c0-pll0-odf-0";
148 clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */
149 };
150
151 clk_s_c0_pll1: clk-s-c0-pll1 {
152 #clock-cells = <1>;
153 compatible = "st,clkgen-pll1";
154
155 clocks = <&clk_sysin>;
156
157 clock-output-names = "clk-s-c0-pll1-odf-0";
158 };
159
160 clk_s_c0_flexgen: clk-s-c0-flexgen {
161 #clock-cells = <1>;
162 compatible = "st,flexgen";
163
164 clocks = <&clk_s_c0_pll0 0>,
165 <&clk_s_c0_pll1 0>,
166 <&clk_s_c0_quadfs 0>,
167 <&clk_s_c0_quadfs 1>,
168 <&clk_s_c0_quadfs 2>,
169 <&clk_s_c0_quadfs 3>,
170 <&clk_sysin>;
171
172 clock-output-names = "clk-icn-gpu",
173 "clk-fdma",
174 "clk-nand",
175 "clk-hva",
176 "clk-proc-stfe",
177 "clk-proc-tp",
178 "clk-rx-icn-dmu",
179 "clk-rx-icn-hva",
180 "clk-icn-cpu",
181 "clk-tx-icn-dmu",
182 "clk-mmc-0",
183 "clk-mmc-1",
184 "clk-jpegdec",
185 "clk-ext2fa9",
186 "clk-ic-bdisp-0",
187 "clk-ic-bdisp-1",
188 "clk-pp-dmu",
189 "clk-vid-dmu",
190 "clk-dss-lpc",
191 "clk-st231-aud-0",
192 "clk-st231-gp-1",
193 "clk-st231-dmu",
194 "clk-icn-lmi",
195 "clk-tx-icn-disp-1",
196 "clk-icn-sbc",
197 "clk-stfe-frc2",
198 "clk-eth-phy",
199 "clk-eth-ref-phyclk",
200 "clk-flash-promip",
201 "clk-main-disp",
202 "clk-aux-disp",
203 "clk-compo-dvp",
204 "clk-tx-icn-hades",
205 "clk-rx-icn-hades",
206 "clk-icn-reg-16",
207 "clk-pp-hades",
208 "clk-clust-hades",
209 "clk-hwpe-hades",
210 "clk-fc-hades";
211 clock-critical = <CLK_PROC_STFE>,
212 <CLK_ICN_CPU>,
213 <CLK_TX_ICN_DMU>,
214 <CLK_EXT2F_A9>,
215 <CLK_ICN_LMI>,
216 <CLK_ICN_SBC>;
217 };
218 };
219
220 clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
221 #clock-cells = <1>;
222 compatible = "st,quadfs";
223 reg = <0x9104000 0x1000>;
224
225 clocks = <&clk_sysin>;
226
227 clock-output-names = "clk-s-d0-fs0-ch0",
228 "clk-s-d0-fs0-ch1",
229 "clk-s-d0-fs0-ch2",
230 "clk-s-d0-fs0-ch3";
231 };
232
233 clockgen-d0@09104000 {
234 compatible = "st,clkgen-c32";
235 reg = <0x9104000 0x1000>;
236
237 clk_s_d0_flexgen: clk-s-d0-flexgen {
238 #clock-cells = <1>;
239 compatible = "st,flexgen-audio", "st,flexgen";
240
241 clocks = <&clk_s_d0_quadfs 0>,
242 <&clk_s_d0_quadfs 1>,
243 <&clk_s_d0_quadfs 2>,
244 <&clk_s_d0_quadfs 3>,
245 <&clk_sysin>;
246
247 clock-output-names = "clk-pcm-0",
248 "clk-pcm-1",
249 "clk-pcm-2",
250 "clk-spdiff",
251 "clk-pcmr10-master",
252 "clk-usb2-phy";
253 };
254 };
255
256 clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
257 #clock-cells = <1>;
258 compatible = "st,quadfs";
259 reg = <0x9106000 0x1000>;
260
261 clocks = <&clk_sysin>;
262
263 clock-output-names = "clk-s-d2-fs0-ch0",
264 "clk-s-d2-fs0-ch1",
265 "clk-s-d2-fs0-ch2",
266 "clk-s-d2-fs0-ch3";
267 };
268
269 clk_tmdsout_hdmi: clk-tmdsout-hdmi {
270 #clock-cells = <0>;
271 compatible = "fixed-clock";
272 clock-frequency = <0>;
273 };
274
275 clockgen-d2@x9106000 {
276 compatible = "st,clkgen-c32";
277 reg = <0x9106000 0x1000>;
278
279 clk_s_d2_flexgen: clk-s-d2-flexgen {
280 #clock-cells = <1>;
281 compatible = "st,flexgen-video", "st,flexgen";
282
283 clocks = <&clk_s_d2_quadfs 0>,
284 <&clk_s_d2_quadfs 1>,
285 <&clk_s_d2_quadfs 2>,
286 <&clk_s_d2_quadfs 3>,
287 <&clk_sysin>,
288 <&clk_sysin>,
289 <&clk_tmdsout_hdmi>;
290
291 clock-output-names = "clk-pix-main-disp",
292 "clk-pix-pip",
293 "clk-pix-gdp1",
294 "clk-pix-gdp2",
295 "clk-pix-gdp3",
296 "clk-pix-gdp4",
297 "clk-pix-aux-disp",
298 "clk-denc",
299 "clk-pix-hddac",
300 "clk-hddac",
301 "clk-sddac",
302 "clk-pix-dvo",
303 "clk-dvo",
304 "clk-pix-hdmi",
305 "clk-tmds-hdmi",
306 "clk-ref-hdmiphy";
307 };
308 };
309
310 clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
311 #clock-cells = <1>;
312 compatible = "st,quadfs";
313 reg = <0x9107000 0x1000>;
314
315 clocks = <&clk_sysin>;
316
317 clock-output-names = "clk-s-d3-fs0-ch0",
318 "clk-s-d3-fs0-ch1",
319 "clk-s-d3-fs0-ch2",
320 "clk-s-d3-fs0-ch3";
321 };
322
323 clockgen-d3@9107000 {
324 compatible = "st,clkgen-c32";
325 reg = <0x9107000 0x1000>;
326
327 clk_s_d3_flexgen: clk-s-d3-flexgen {
328 #clock-cells = <1>;
329 compatible = "st,flexgen";
330
331 clocks = <&clk_s_d3_quadfs 0>,
332 <&clk_s_d3_quadfs 1>,
333 <&clk_s_d3_quadfs 2>,
334 <&clk_s_d3_quadfs 3>,
335 <&clk_sysin>;
336
337 clock-output-names = "clk-stfe-frc1",
338 "clk-tsout-0",
339 "clk-tsout-1",
340 "clk-mchi",
341 "clk-vsens-compo",
342 "clk-frc1-remote",
343 "clk-lpc-0",
344 "clk-lpc-1";
345 };
346 };
347 };
348};