Loading...
Note: File does not exist in v6.13.7.
1/*
2 * Copyright Altera Corporation (C) 2014. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include "skeleton.dtsi"
18#include <dt-bindings/interrupt-controller/arm-gic.h>
19#include <dt-bindings/reset/altr,rst-mgr-a10.h>
20
21/ {
22 #address-cells = <1>;
23 #size-cells = <1>;
24
25 cpus {
26 #address-cells = <1>;
27 #size-cells = <0>;
28 enable-method = "altr,socfpga-a10-smp";
29
30 cpu@0 {
31 compatible = "arm,cortex-a9";
32 device_type = "cpu";
33 reg = <0>;
34 next-level-cache = <&L2>;
35 };
36 cpu@1 {
37 compatible = "arm,cortex-a9";
38 device_type = "cpu";
39 reg = <1>;
40 next-level-cache = <&L2>;
41 };
42 };
43
44 intc: intc@ffffd000 {
45 compatible = "arm,cortex-a9-gic";
46 #interrupt-cells = <3>;
47 interrupt-controller;
48 reg = <0xffffd000 0x1000>,
49 <0xffffc100 0x100>;
50 };
51
52 soc {
53 #address-cells = <1>;
54 #size-cells = <1>;
55 compatible = "simple-bus";
56 device_type = "soc";
57 interrupt-parent = <&intc>;
58 ranges;
59
60 amba {
61 compatible = "simple-bus";
62 #address-cells = <1>;
63 #size-cells = <1>;
64 ranges;
65
66 pdma: pdma@ffda1000 {
67 compatible = "arm,pl330", "arm,primecell";
68 reg = <0xffda1000 0x1000>;
69 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>,
70 <0 84 IRQ_TYPE_LEVEL_HIGH>,
71 <0 85 IRQ_TYPE_LEVEL_HIGH>,
72 <0 86 IRQ_TYPE_LEVEL_HIGH>,
73 <0 87 IRQ_TYPE_LEVEL_HIGH>,
74 <0 88 IRQ_TYPE_LEVEL_HIGH>,
75 <0 89 IRQ_TYPE_LEVEL_HIGH>,
76 <0 90 IRQ_TYPE_LEVEL_HIGH>,
77 <0 91 IRQ_TYPE_LEVEL_HIGH>;
78 #dma-cells = <1>;
79 #dma-channels = <8>;
80 #dma-requests = <32>;
81 clocks = <&l4_main_clk>;
82 clock-names = "apb_pclk";
83 };
84 };
85
86 clkmgr@ffd04000 {
87 compatible = "altr,clk-mgr";
88 reg = <0xffd04000 0x1000>;
89
90 clocks {
91 #address-cells = <1>;
92 #size-cells = <0>;
93
94 cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk {
95 #clock-cells = <0>;
96 compatible = "fixed-clock";
97 };
98
99 cb_intosc_ls_clk: cb_intosc_ls_clk {
100 #clock-cells = <0>;
101 compatible = "fixed-clock";
102 };
103
104 f2s_free_clk: f2s_free_clk {
105 #clock-cells = <0>;
106 compatible = "fixed-clock";
107 };
108
109 osc1: osc1 {
110 #clock-cells = <0>;
111 compatible = "fixed-clock";
112 };
113
114 main_pll: main_pll {
115 #address-cells = <1>;
116 #size-cells = <0>;
117 #clock-cells = <0>;
118 compatible = "altr,socfpga-a10-pll-clock";
119 clocks = <&osc1>, <&cb_intosc_ls_clk>,
120 <&f2s_free_clk>;
121 reg = <0x40>;
122
123 main_mpu_base_clk: main_mpu_base_clk {
124 #clock-cells = <0>;
125 compatible = "altr,socfpga-a10-perip-clk";
126 clocks = <&main_pll>;
127 div-reg = <0x140 0 11>;
128 };
129
130 main_noc_base_clk: main_noc_base_clk {
131 #clock-cells = <0>;
132 compatible = "altr,socfpga-a10-perip-clk";
133 clocks = <&main_pll>;
134 div-reg = <0x144 0 11>;
135 };
136
137 main_emaca_clk: main_emaca_clk {
138 #clock-cells = <0>;
139 compatible = "altr,socfpga-a10-perip-clk";
140 clocks = <&main_pll>;
141 reg = <0x68>;
142 };
143
144 main_emacb_clk: main_emacb_clk {
145 #clock-cells = <0>;
146 compatible = "altr,socfpga-a10-perip-clk";
147 clocks = <&main_pll>;
148 reg = <0x6C>;
149 };
150
151 main_emac_ptp_clk: main_emac_ptp_clk {
152 #clock-cells = <0>;
153 compatible = "altr,socfpga-a10-perip-clk";
154 clocks = <&main_pll>;
155 reg = <0x70>;
156 };
157
158 main_gpio_db_clk: main_gpio_db_clk {
159 #clock-cells = <0>;
160 compatible = "altr,socfpga-a10-perip-clk";
161 clocks = <&main_pll>;
162 reg = <0x74>;
163 };
164
165 main_sdmmc_clk: main_sdmmc_clk {
166 #clock-cells = <0>;
167 compatible = "altr,socfpga-a10-perip-clk"
168;
169 clocks = <&main_pll>;
170 reg = <0x78>;
171 };
172
173 main_s2f_usr0_clk: main_s2f_usr0_clk {
174 #clock-cells = <0>;
175 compatible = "altr,socfpga-a10-perip-clk";
176 clocks = <&main_pll>;
177 reg = <0x7C>;
178 };
179
180 main_s2f_usr1_clk: main_s2f_usr1_clk {
181 #clock-cells = <0>;
182 compatible = "altr,socfpga-a10-perip-clk";
183 clocks = <&main_pll>;
184 reg = <0x80>;
185 };
186
187 main_hmc_pll_ref_clk: main_hmc_pll_ref_clk {
188 #clock-cells = <0>;
189 compatible = "altr,socfpga-a10-perip-clk";
190 clocks = <&main_pll>;
191 reg = <0x84>;
192 };
193
194 main_periph_ref_clk: main_periph_ref_clk {
195 #clock-cells = <0>;
196 compatible = "altr,socfpga-a10-perip-clk";
197 clocks = <&main_pll>;
198 reg = <0x9C>;
199 };
200 };
201
202 periph_pll: periph_pll {
203 #address-cells = <1>;
204 #size-cells = <0>;
205 #clock-cells = <0>;
206 compatible = "altr,socfpga-a10-pll-clock";
207 clocks = <&osc1>, <&cb_intosc_ls_clk>,
208 <&f2s_free_clk>, <&main_periph_ref_clk>;
209 reg = <0xC0>;
210
211 peri_mpu_base_clk: peri_mpu_base_clk {
212 #clock-cells = <0>;
213 compatible = "altr,socfpga-a10-perip-clk";
214 clocks = <&periph_pll>;
215 div-reg = <0x140 16 11>;
216 };
217
218 peri_noc_base_clk: peri_noc_base_clk {
219 #clock-cells = <0>;
220 compatible = "altr,socfpga-a10-perip-clk";
221 clocks = <&periph_pll>;
222 div-reg = <0x144 16 11>;
223 };
224
225 peri_emaca_clk: peri_emaca_clk {
226 #clock-cells = <0>;
227 compatible = "altr,socfpga-a10-perip-clk";
228 clocks = <&periph_pll>;
229 reg = <0xE8>;
230 };
231
232 peri_emacb_clk: peri_emacb_clk {
233 #clock-cells = <0>;
234 compatible = "altr,socfpga-a10-perip-clk";
235 clocks = <&periph_pll>;
236 reg = <0xEC>;
237 };
238
239 peri_emac_ptp_clk: peri_emac_ptp_clk {
240 #clock-cells = <0>;
241 compatible = "altr,socfpga-a10-perip-clk";
242 clocks = <&periph_pll>;
243 reg = <0xF0>;
244 };
245
246 peri_gpio_db_clk: peri_gpio_db_clk {
247 #clock-cells = <0>;
248 compatible = "altr,socfpga-a10-perip-clk";
249 clocks = <&periph_pll>;
250 reg = <0xF4>;
251 };
252
253 peri_sdmmc_clk: peri_sdmmc_clk {
254 #clock-cells = <0>;
255 compatible = "altr,socfpga-a10-perip-clk";
256 clocks = <&periph_pll>;
257 reg = <0xF8>;
258 };
259
260 peri_s2f_usr0_clk: peri_s2f_usr0_clk {
261 #clock-cells = <0>;
262 compatible = "altr,socfpga-a10-perip-clk";
263 clocks = <&periph_pll>;
264 reg = <0xFC>;
265 };
266
267 peri_s2f_usr1_clk: peri_s2f_usr1_clk {
268 #clock-cells = <0>;
269 compatible = "altr,socfpga-a10-perip-clk";
270 clocks = <&periph_pll>;
271 reg = <0x100>;
272 };
273
274 peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk {
275 #clock-cells = <0>;
276 compatible = "altr,socfpga-a10-perip-clk";
277 clocks = <&periph_pll>;
278 reg = <0x104>;
279 };
280 };
281
282 mpu_free_clk: mpu_free_clk {
283 #clock-cells = <0>;
284 compatible = "altr,socfpga-a10-perip-clk";
285 clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>,
286 <&osc1>, <&cb_intosc_hs_div2_clk>,
287 <&f2s_free_clk>;
288 reg = <0x60>;
289 };
290
291 noc_free_clk: noc_free_clk {
292 #clock-cells = <0>;
293 compatible = "altr,socfpga-a10-perip-clk";
294 clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>,
295 <&osc1>, <&cb_intosc_hs_div2_clk>,
296 <&f2s_free_clk>;
297 reg = <0x64>;
298 };
299
300 s2f_user1_free_clk: s2f_user1_free_clk {
301 #clock-cells = <0>;
302 compatible = "altr,socfpga-a10-perip-clk";
303 clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>,
304 <&osc1>, <&cb_intosc_hs_div2_clk>,
305 <&f2s_free_clk>;
306 reg = <0x104>;
307 };
308
309 sdmmc_free_clk: sdmmc_free_clk {
310 #clock-cells = <0>;
311 compatible = "altr,socfpga-a10-perip-clk";
312 clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>,
313 <&osc1>, <&cb_intosc_hs_div2_clk>,
314 <&f2s_free_clk>;
315 fixed-divider = <4>;
316 reg = <0xF8>;
317 };
318
319 l4_sys_free_clk: l4_sys_free_clk {
320 #clock-cells = <0>;
321 compatible = "altr,socfpga-a10-perip-clk";
322 clocks = <&noc_free_clk>;
323 fixed-divider = <4>;
324 };
325
326 l4_main_clk: l4_main_clk {
327 #clock-cells = <0>;
328 compatible = "altr,socfpga-a10-gate-clk";
329 clocks = <&noc_free_clk>;
330 div-reg = <0xA8 0 2>;
331 clk-gate = <0x48 1>;
332 };
333
334 l4_mp_clk: l4_mp_clk {
335 #clock-cells = <0>;
336 compatible = "altr,socfpga-a10-gate-clk";
337 clocks = <&noc_free_clk>;
338 div-reg = <0xA8 8 2>;
339 clk-gate = <0x48 2>;
340 };
341
342 l4_sp_clk: l4_sp_clk {
343 #clock-cells = <0>;
344 compatible = "altr,socfpga-a10-gate-clk";
345 clocks = <&noc_free_clk>;
346 div-reg = <0xA8 16 2>;
347 clk-gate = <0x48 3>;
348 };
349
350 mpu_periph_clk: mpu_periph_clk {
351 #clock-cells = <0>;
352 compatible = "altr,socfpga-a10-gate-clk";
353 clocks = <&mpu_free_clk>;
354 fixed-divider = <4>;
355 clk-gate = <0x48 0>;
356 };
357
358 sdmmc_clk: sdmmc_clk {
359 #clock-cells = <0>;
360 compatible = "altr,socfpga-a10-gate-clk";
361 clocks = <&sdmmc_free_clk>;
362 clk-gate = <0xC8 5>;
363 clk-phase = <0 135>;
364 };
365
366 qspi_clk: qspi_clk {
367 #clock-cells = <0>;
368 compatible = "altr,socfpga-a10-gate-clk";
369 clocks = <&l4_main_clk>;
370 clk-gate = <0xC8 11>;
371 };
372
373 nand_clk: nand_clk {
374 #clock-cells = <0>;
375 compatible = "altr,socfpga-a10-gate-clk";
376 clocks = <&l4_mp_clk>;
377 clk-gate = <0xC8 10>;
378 };
379
380 spi_m_clk: spi_m_clk {
381 #clock-cells = <0>;
382 compatible = "altr,socfpga-a10-gate-clk";
383 clocks = <&l4_main_clk>;
384 clk-gate = <0xC8 9>;
385 };
386
387 usb_clk: usb_clk {
388 #clock-cells = <0>;
389 compatible = "altr,socfpga-a10-gate-clk";
390 clocks = <&l4_mp_clk>;
391 clk-gate = <0xC8 8>;
392 };
393
394 s2f_usr1_clk: s2f_usr1_clk {
395 #clock-cells = <0>;
396 compatible = "altr,socfpga-a10-gate-clk";
397 clocks = <&peri_s2f_usr1_clk>;
398 clk-gate = <0xC8 6>;
399 };
400 };
401 };
402
403 gmac0: ethernet@ff800000 {
404 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
405 altr,sysmgr-syscon = <&sysmgr 0x44 0>;
406 reg = <0xff800000 0x2000>;
407 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
408 interrupt-names = "macirq";
409 /* Filled in by bootloader */
410 mac-address = [00 00 00 00 00 00];
411 snps,multicast-filter-bins = <256>;
412 snps,perfect-filter-entries = <128>;
413 tx-fifo-depth = <4096>;
414 rx-fifo-depth = <16384>;
415 clocks = <&l4_mp_clk>;
416 clock-names = "stmmaceth";
417 resets = <&rst EMAC0_RESET>;
418 reset-names = "stmmaceth";
419 status = "disabled";
420 };
421
422 gmac1: ethernet@ff802000 {
423 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
424 altr,sysmgr-syscon = <&sysmgr 0x48 0>;
425 reg = <0xff802000 0x2000>;
426 interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
427 interrupt-names = "macirq";
428 /* Filled in by bootloader */
429 mac-address = [00 00 00 00 00 00];
430 snps,multicast-filter-bins = <256>;
431 snps,perfect-filter-entries = <128>;
432 tx-fifo-depth = <4096>;
433 rx-fifo-depth = <16384>;
434 clocks = <&l4_mp_clk>;
435 clock-names = "stmmaceth";
436 resets = <&rst EMAC1_RESET>;
437 reset-names = "stmmaceth";
438 status = "disabled";
439 };
440
441 gmac2: ethernet@ff804000 {
442 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
443 altr,sysmgr-syscon = <&sysmgr 0x4C 0>;
444 reg = <0xff804000 0x2000>;
445 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
446 interrupt-names = "macirq";
447 /* Filled in by bootloader */
448 mac-address = [00 00 00 00 00 00];
449 snps,multicast-filter-bins = <256>;
450 snps,perfect-filter-entries = <128>;
451 tx-fifo-depth = <4096>;
452 rx-fifo-depth = <16384>;
453 clocks = <&l4_mp_clk>;
454 clock-names = "stmmaceth";
455 status = "disabled";
456 };
457
458 gpio0: gpio@ffc02900 {
459 #address-cells = <1>;
460 #size-cells = <0>;
461 compatible = "snps,dw-apb-gpio";
462 reg = <0xffc02900 0x100>;
463 status = "disabled";
464
465 porta: gpio-controller@0 {
466 compatible = "snps,dw-apb-gpio-port";
467 gpio-controller;
468 #gpio-cells = <2>;
469 snps,nr-gpios = <29>;
470 reg = <0>;
471 interrupt-controller;
472 #interrupt-cells = <2>;
473 interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
474 };
475 };
476
477 gpio1: gpio@ffc02a00 {
478 #address-cells = <1>;
479 #size-cells = <0>;
480 compatible = "snps,dw-apb-gpio";
481 reg = <0xffc02a00 0x100>;
482 status = "disabled";
483
484 portb: gpio-controller@0 {
485 compatible = "snps,dw-apb-gpio-port";
486 gpio-controller;
487 #gpio-cells = <2>;
488 snps,nr-gpios = <29>;
489 reg = <0>;
490 interrupt-controller;
491 #interrupt-cells = <2>;
492 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
493 };
494 };
495
496 gpio2: gpio@ffc02b00 {
497 #address-cells = <1>;
498 #size-cells = <0>;
499 compatible = "snps,dw-apb-gpio";
500 reg = <0xffc02b00 0x100>;
501 status = "disabled";
502
503 portc: gpio-controller@0 {
504 compatible = "snps,dw-apb-gpio-port";
505 gpio-controller;
506 #gpio-cells = <2>;
507 snps,nr-gpios = <27>;
508 reg = <0>;
509 interrupt-controller;
510 #interrupt-cells = <2>;
511 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
512 };
513 };
514
515 i2c0: i2c@ffc02200 {
516 #address-cells = <1>;
517 #size-cells = <0>;
518 compatible = "snps,designware-i2c";
519 reg = <0xffc02200 0x100>;
520 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
521 clocks = <&l4_sp_clk>;
522 status = "disabled";
523 };
524
525 i2c1: i2c@ffc02300 {
526 #address-cells = <1>;
527 #size-cells = <0>;
528 compatible = "snps,designware-i2c";
529 reg = <0xffc02300 0x100>;
530 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
531 clocks = <&l4_sp_clk>;
532 status = "disabled";
533 };
534
535 i2c2: i2c@ffc02400 {
536 #address-cells = <1>;
537 #size-cells = <0>;
538 compatible = "snps,designware-i2c";
539 reg = <0xffc02400 0x100>;
540 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
541 clocks = <&l4_sp_clk>;
542 status = "disabled";
543 };
544
545 i2c3: i2c@ffc02500 {
546 #address-cells = <1>;
547 #size-cells = <0>;
548 compatible = "snps,designware-i2c";
549 reg = <0xffc02500 0x100>;
550 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
551 clocks = <&l4_sp_clk>;
552 status = "disabled";
553 };
554
555 i2c4: i2c@ffc02600 {
556 #address-cells = <1>;
557 #size-cells = <0>;
558 compatible = "snps,designware-i2c";
559 reg = <0xffc02600 0x100>;
560 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
561 clocks = <&l4_sp_clk>;
562 status = "disabled";
563 };
564
565 spi1: spi@ffda5000 {
566 compatible = "snps,dw-apb-ssi";
567 #address-cells = <1>;
568 #size-cells = <0>;
569 reg = <0xffda5000 0x100>;
570 interrupts = <0 102 4>;
571 num-chipselect = <4>;
572 bus-num = <0>;
573 /*32bit_access;*/
574 tx-dma-channel = <&pdma 16>;
575 rx-dma-channel = <&pdma 17>;
576 clocks = <&spi_m_clk>;
577 status = "disabled";
578 };
579
580 sdr: sdr@ffc25000 {
581 compatible = "syscon";
582 reg = <0xffcfb100 0x80>;
583 };
584
585 L2: l2-cache@fffff000 {
586 compatible = "arm,pl310-cache";
587 reg = <0xfffff000 0x1000>;
588 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
589 cache-unified;
590 cache-level = <2>;
591 prefetch-data = <1>;
592 prefetch-instr = <1>;
593 arm,shared-override;
594 };
595
596 mmc: dwmmc0@ff808000 {
597 #address-cells = <1>;
598 #size-cells = <0>;
599 compatible = "altr,socfpga-dw-mshc";
600 reg = <0xff808000 0x1000>;
601 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
602 fifo-depth = <0x400>;
603 clocks = <&l4_mp_clk>, <&sdmmc_clk>;
604 clock-names = "biu", "ciu";
605 status = "disabled";
606 };
607
608 ocram: sram@ffe00000 {
609 compatible = "mmio-sram";
610 reg = <0xffe00000 0x40000>;
611 };
612
613 eccmgr: eccmgr@ffd06000 {
614 compatible = "altr,socfpga-a10-ecc-manager";
615 altr,sysmgr-syscon = <&sysmgr>;
616 #address-cells = <1>;
617 #size-cells = <1>;
618 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
619 <0 0 IRQ_TYPE_LEVEL_HIGH>;
620 interrupt-controller;
621 #interrupt-cells = <2>;
622 ranges;
623
624 sdramedac {
625 compatible = "altr,sdram-edac-a10";
626 altr,sdr-syscon = <&sdr>;
627 interrupts = <17 IRQ_TYPE_LEVEL_HIGH>,
628 <49 IRQ_TYPE_LEVEL_HIGH>;
629 };
630
631 l2-ecc@ffd06010 {
632 compatible = "altr,socfpga-a10-l2-ecc";
633 reg = <0xffd06010 0x4>;
634 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>,
635 <32 IRQ_TYPE_LEVEL_HIGH>;
636 };
637
638 ocram-ecc@ff8c3000 {
639 compatible = "altr,socfpga-a10-ocram-ecc";
640 reg = <0xff8c3000 0x400>;
641 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>,
642 <33 IRQ_TYPE_LEVEL_HIGH>;
643 };
644
645 emac0-rx-ecc@ff8c0800 {
646 compatible = "altr,socfpga-eth-mac-ecc";
647 reg = <0xff8c0800 0x400>;
648 altr,ecc-parent = <&gmac0>;
649 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>,
650 <36 IRQ_TYPE_LEVEL_HIGH>;
651 };
652
653 emac0-tx-ecc@ff8c0c00 {
654 compatible = "altr,socfpga-eth-mac-ecc";
655 reg = <0xff8c0c00 0x400>;
656 altr,ecc-parent = <&gmac0>;
657 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>,
658 <37 IRQ_TYPE_LEVEL_HIGH>;
659 };
660
661 dma-ecc@ff8c8000 {
662 compatible = "altr,socfpga-dma-ecc";
663 reg = <0xff8c8000 0x400>;
664 altr,ecc-parent = <&pdma>;
665 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
666 <42 IRQ_TYPE_LEVEL_HIGH>;
667 };
668
669 usb0-ecc@ff8c8800 {
670 compatible = "altr,socfpga-usb-ecc";
671 reg = <0xff8c8800 0x400>;
672 altr,ecc-parent = <&usb0>;
673 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
674 <34 IRQ_TYPE_LEVEL_HIGH>;
675 };
676 };
677
678 qspi: spi@ff809000 {
679 compatible = "cdns,qspi-nor";
680 #address-cells = <1>;
681 #size-cells = <0>;
682 reg = <0xff809000 0x100>,
683 <0xffa00000 0x100000>;
684 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
685 cdns,fifo-depth = <128>;
686 cdns,fifo-width = <4>;
687 cdns,trigger-address = <0x00000000>;
688 clocks = <&qspi_clk>;
689 status = "disabled";
690 };
691
692 rst: rstmgr@ffd05000 {
693 #reset-cells = <1>;
694 compatible = "altr,rst-mgr";
695 reg = <0xffd05000 0x100>;
696 altr,modrst-offset = <0x20>;
697 };
698
699 scu: snoop-control-unit@ffffc000 {
700 compatible = "arm,cortex-a9-scu";
701 reg = <0xffffc000 0x100>;
702 };
703
704 sysmgr: sysmgr@ffd06000 {
705 compatible = "altr,sys-mgr", "syscon";
706 reg = <0xffd06000 0x300>;
707 cpu1-start-addr = <0xffd06230>;
708 };
709
710 /* Local timer */
711 timer@ffffc600 {
712 compatible = "arm,cortex-a9-twd-timer";
713 reg = <0xffffc600 0x100>;
714 interrupts = <1 13 0xf04>;
715 clocks = <&mpu_periph_clk>;
716 };
717
718 timer0: timer0@ffc02700 {
719 compatible = "snps,dw-apb-timer";
720 interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
721 reg = <0xffc02700 0x100>;
722 clocks = <&l4_sp_clk>;
723 clock-names = "timer";
724 };
725
726 timer1: timer1@ffc02800 {
727 compatible = "snps,dw-apb-timer";
728 interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>;
729 reg = <0xffc02800 0x100>;
730 clocks = <&l4_sp_clk>;
731 clock-names = "timer";
732 };
733
734 timer2: timer2@ffd00000 {
735 compatible = "snps,dw-apb-timer";
736 interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>;
737 reg = <0xffd00000 0x100>;
738 clocks = <&l4_sys_free_clk>;
739 clock-names = "timer";
740 };
741
742 timer3: timer3@ffd00100 {
743 compatible = "snps,dw-apb-timer";
744 interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>;
745 reg = <0xffd01000 0x100>;
746 clocks = <&l4_sys_free_clk>;
747 clock-names = "timer";
748 };
749
750 uart0: serial0@ffc02000 {
751 compatible = "snps,dw-apb-uart";
752 reg = <0xffc02000 0x100>;
753 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
754 reg-shift = <2>;
755 reg-io-width = <4>;
756 clocks = <&l4_sp_clk>;
757 status = "disabled";
758 };
759
760 uart1: serial1@ffc02100 {
761 compatible = "snps,dw-apb-uart";
762 reg = <0xffc02100 0x100>;
763 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
764 reg-shift = <2>;
765 reg-io-width = <4>;
766 clocks = <&l4_sp_clk>;
767 status = "disabled";
768 };
769
770 usbphy0: usbphy@0 {
771 #phy-cells = <0>;
772 compatible = "usb-nop-xceiv";
773 status = "okay";
774 };
775
776 usb0: usb@ffb00000 {
777 compatible = "snps,dwc2";
778 reg = <0xffb00000 0xffff>;
779 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
780 clocks = <&usb_clk>;
781 clock-names = "otg";
782 resets = <&rst USB0_RESET>;
783 reset-names = "dwc2";
784 phys = <&usbphy0>;
785 phy-names = "usb2-phy";
786 status = "disabled";
787 };
788
789 usb1: usb@ffb40000 {
790 compatible = "snps,dwc2";
791 reg = <0xffb40000 0xffff>;
792 interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
793 clocks = <&usb_clk>;
794 clock-names = "otg";
795 resets = <&rst USB1_RESET>;
796 reset-names = "dwc2";
797 phys = <&usbphy0>;
798 phy-names = "usb2-phy";
799 status = "disabled";
800 };
801
802 watchdog0: watchdog@ffd00200 {
803 compatible = "snps,dw-wdt";
804 reg = <0xffd00200 0x100>;
805 interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
806 clocks = <&l4_sys_free_clk>;
807 status = "disabled";
808 };
809
810 watchdog1: watchdog@ffd00300 {
811 compatible = "snps,dw-wdt";
812 reg = <0xffd00300 0x100>;
813 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
814 clocks = <&l4_sys_free_clk>;
815 status = "disabled";
816 };
817 };
818};