Loading...
Note: File does not exist in v6.13.7.
1/*
2 * Device Tree Source for the r8a7793 SoC
3 *
4 * Copyright (C) 2014-2015 Renesas Electronics Corporation
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11#include <dt-bindings/clock/r8a7793-clock.h>
12#include <dt-bindings/interrupt-controller/arm-gic.h>
13#include <dt-bindings/interrupt-controller/irq.h>
14#include <dt-bindings/power/r8a7793-sysc.h>
15
16/ {
17 compatible = "renesas,r8a7793";
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
21
22 aliases {
23 i2c0 = &i2c0;
24 i2c1 = &i2c1;
25 i2c2 = &i2c2;
26 i2c3 = &i2c3;
27 i2c4 = &i2c4;
28 i2c5 = &i2c5;
29 i2c6 = &i2c6;
30 i2c7 = &i2c7;
31 i2c8 = &i2c8;
32 spi0 = &qspi;
33 };
34
35 cpus {
36 #address-cells = <1>;
37 #size-cells = <0>;
38 enable-method = "renesas,apmu";
39
40 cpu0: cpu@0 {
41 device_type = "cpu";
42 compatible = "arm,cortex-a15";
43 reg = <0>;
44 clock-frequency = <1500000000>;
45 voltage-tolerance = <1>; /* 1% */
46 clocks = <&cpg_clocks R8A7793_CLK_Z>;
47 clock-latency = <300000>; /* 300 us */
48 power-domains = <&sysc R8A7793_PD_CA15_CPU0>;
49
50 /* kHz - uV - OPPs unknown yet */
51 operating-points = <1500000 1000000>,
52 <1312500 1000000>,
53 <1125000 1000000>,
54 < 937500 1000000>,
55 < 750000 1000000>,
56 < 375000 1000000>;
57 next-level-cache = <&L2_CA15>;
58 };
59
60 cpu1: cpu@1 {
61 device_type = "cpu";
62 compatible = "arm,cortex-a15";
63 reg = <1>;
64 clock-frequency = <1500000000>;
65 power-domains = <&sysc R8A7793_PD_CA15_CPU1>;
66 };
67
68 L2_CA15: cache-controller@0 {
69 compatible = "cache";
70 reg = <0>;
71 power-domains = <&sysc R8A7793_PD_CA15_SCU>;
72 cache-unified;
73 cache-level = <2>;
74 };
75 };
76
77 apmu@e6152000 {
78 compatible = "renesas,r8a7793-apmu", "renesas,apmu";
79 reg = <0 0xe6152000 0 0x188>;
80 cpus = <&cpu0 &cpu1>;
81 };
82
83 thermal-zones {
84 cpu_thermal: cpu-thermal {
85 polling-delay-passive = <0>;
86 polling-delay = <0>;
87
88 thermal-sensors = <&thermal>;
89
90 trips {
91 cpu-crit {
92 temperature = <115000>;
93 hysteresis = <0>;
94 type = "critical";
95 };
96 };
97 cooling-maps {
98 };
99 };
100 };
101
102 gic: interrupt-controller@f1001000 {
103 compatible = "arm,gic-400";
104 #interrupt-cells = <3>;
105 #address-cells = <0>;
106 interrupt-controller;
107 reg = <0 0xf1001000 0 0x1000>,
108 <0 0xf1002000 0 0x1000>,
109 <0 0xf1004000 0 0x2000>,
110 <0 0xf1006000 0 0x2000>;
111 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
112 };
113
114 gpio0: gpio@e6050000 {
115 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
116 reg = <0 0xe6050000 0 0x50>;
117 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
118 #gpio-cells = <2>;
119 gpio-controller;
120 gpio-ranges = <&pfc 0 0 32>;
121 #interrupt-cells = <2>;
122 interrupt-controller;
123 clocks = <&mstp9_clks R8A7793_CLK_GPIO0>;
124 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
125 };
126
127 gpio1: gpio@e6051000 {
128 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
129 reg = <0 0xe6051000 0 0x50>;
130 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
131 #gpio-cells = <2>;
132 gpio-controller;
133 gpio-ranges = <&pfc 0 32 26>;
134 #interrupt-cells = <2>;
135 interrupt-controller;
136 clocks = <&mstp9_clks R8A7793_CLK_GPIO1>;
137 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
138 };
139
140 gpio2: gpio@e6052000 {
141 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
142 reg = <0 0xe6052000 0 0x50>;
143 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
144 #gpio-cells = <2>;
145 gpio-controller;
146 gpio-ranges = <&pfc 0 64 32>;
147 #interrupt-cells = <2>;
148 interrupt-controller;
149 clocks = <&mstp9_clks R8A7793_CLK_GPIO2>;
150 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
151 };
152
153 gpio3: gpio@e6053000 {
154 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
155 reg = <0 0xe6053000 0 0x50>;
156 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
157 #gpio-cells = <2>;
158 gpio-controller;
159 gpio-ranges = <&pfc 0 96 32>;
160 #interrupt-cells = <2>;
161 interrupt-controller;
162 clocks = <&mstp9_clks R8A7793_CLK_GPIO3>;
163 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
164 };
165
166 gpio4: gpio@e6054000 {
167 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
168 reg = <0 0xe6054000 0 0x50>;
169 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
170 #gpio-cells = <2>;
171 gpio-controller;
172 gpio-ranges = <&pfc 0 128 32>;
173 #interrupt-cells = <2>;
174 interrupt-controller;
175 clocks = <&mstp9_clks R8A7793_CLK_GPIO4>;
176 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
177 };
178
179 gpio5: gpio@e6055000 {
180 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
181 reg = <0 0xe6055000 0 0x50>;
182 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
183 #gpio-cells = <2>;
184 gpio-controller;
185 gpio-ranges = <&pfc 0 160 32>;
186 #interrupt-cells = <2>;
187 interrupt-controller;
188 clocks = <&mstp9_clks R8A7793_CLK_GPIO5>;
189 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
190 };
191
192 gpio6: gpio@e6055400 {
193 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
194 reg = <0 0xe6055400 0 0x50>;
195 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
196 #gpio-cells = <2>;
197 gpio-controller;
198 gpio-ranges = <&pfc 0 192 32>;
199 #interrupt-cells = <2>;
200 interrupt-controller;
201 clocks = <&mstp9_clks R8A7793_CLK_GPIO6>;
202 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
203 };
204
205 gpio7: gpio@e6055800 {
206 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
207 reg = <0 0xe6055800 0 0x50>;
208 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
209 #gpio-cells = <2>;
210 gpio-controller;
211 gpio-ranges = <&pfc 0 224 26>;
212 #interrupt-cells = <2>;
213 interrupt-controller;
214 clocks = <&mstp9_clks R8A7793_CLK_GPIO7>;
215 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
216 };
217
218 thermal: thermal@e61f0000 {
219 compatible = "renesas,thermal-r8a7793",
220 "renesas,rcar-gen2-thermal",
221 "renesas,rcar-thermal";
222 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
223 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
224 clocks = <&mstp5_clks R8A7793_CLK_THERMAL>;
225 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
226 #thermal-sensor-cells = <0>;
227 };
228
229 timer {
230 compatible = "arm,armv7-timer";
231 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
232 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
233 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
234 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
235 };
236
237 cmt0: timer@ffca0000 {
238 compatible = "renesas,cmt-48-r8a7793", "renesas,cmt-48-gen2";
239 reg = <0 0xffca0000 0 0x1004>;
240 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
241 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
242 clocks = <&mstp1_clks R8A7793_CLK_CMT0>;
243 clock-names = "fck";
244 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
245
246 renesas,channels-mask = <0x60>;
247
248 status = "disabled";
249 };
250
251 cmt1: timer@e6130000 {
252 compatible = "renesas,cmt-48-r8a7793", "renesas,cmt-48-gen2";
253 reg = <0 0xe6130000 0 0x1004>;
254 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
255 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
256 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
257 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
258 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
259 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
260 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
261 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
262 clocks = <&mstp3_clks R8A7793_CLK_CMT1>;
263 clock-names = "fck";
264 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
265
266 renesas,channels-mask = <0xff>;
267
268 status = "disabled";
269 };
270
271 irqc0: interrupt-controller@e61c0000 {
272 compatible = "renesas,irqc-r8a7793", "renesas,irqc";
273 #interrupt-cells = <2>;
274 interrupt-controller;
275 reg = <0 0xe61c0000 0 0x200>;
276 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
277 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
278 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
279 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
280 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
281 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
282 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
283 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
284 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
285 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
286 clocks = <&mstp4_clks R8A7793_CLK_IRQC>;
287 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
288 };
289
290 dmac0: dma-controller@e6700000 {
291 compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
292 reg = <0 0xe6700000 0 0x20000>;
293 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
294 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
295 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
296 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
297 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
298 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
299 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
300 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
301 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
302 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
303 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
304 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
305 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
306 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
307 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
308 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
309 interrupt-names = "error",
310 "ch0", "ch1", "ch2", "ch3",
311 "ch4", "ch5", "ch6", "ch7",
312 "ch8", "ch9", "ch10", "ch11",
313 "ch12", "ch13", "ch14";
314 clocks = <&mstp2_clks R8A7793_CLK_SYS_DMAC0>;
315 clock-names = "fck";
316 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
317 #dma-cells = <1>;
318 dma-channels = <15>;
319 };
320
321 dmac1: dma-controller@e6720000 {
322 compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
323 reg = <0 0xe6720000 0 0x20000>;
324 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
325 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
326 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
327 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
328 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
329 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
330 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
331 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
332 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
333 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
334 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
335 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
336 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
337 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
338 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
339 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
340 interrupt-names = "error",
341 "ch0", "ch1", "ch2", "ch3",
342 "ch4", "ch5", "ch6", "ch7",
343 "ch8", "ch9", "ch10", "ch11",
344 "ch12", "ch13", "ch14";
345 clocks = <&mstp2_clks R8A7793_CLK_SYS_DMAC1>;
346 clock-names = "fck";
347 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
348 #dma-cells = <1>;
349 dma-channels = <15>;
350 };
351
352 audma0: dma-controller@ec700000 {
353 compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
354 reg = <0 0xec700000 0 0x10000>;
355 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
356 GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
357 GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
358 GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
359 GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
360 GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
361 GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
362 GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
363 GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
364 GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
365 GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
366 GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
367 GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
368 GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
369 interrupt-names = "error",
370 "ch0", "ch1", "ch2", "ch3",
371 "ch4", "ch5", "ch6", "ch7",
372 "ch8", "ch9", "ch10", "ch11",
373 "ch12";
374 clocks = <&mstp5_clks R8A7793_CLK_AUDIO_DMAC0>;
375 clock-names = "fck";
376 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
377 #dma-cells = <1>;
378 dma-channels = <13>;
379 };
380
381 audma1: dma-controller@ec720000 {
382 compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
383 reg = <0 0xec720000 0 0x10000>;
384 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
385 GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
386 GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
387 GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
388 GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
389 GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
390 GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
391 GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
392 GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
393 GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
394 GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
395 GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
396 GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
397 GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
398 interrupt-names = "error",
399 "ch0", "ch1", "ch2", "ch3",
400 "ch4", "ch5", "ch6", "ch7",
401 "ch8", "ch9", "ch10", "ch11",
402 "ch12";
403 clocks = <&mstp5_clks R8A7793_CLK_AUDIO_DMAC1>;
404 clock-names = "fck";
405 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
406 #dma-cells = <1>;
407 dma-channels = <13>;
408 };
409
410 /* The memory map in the User's Manual maps the cores to bus numbers */
411 i2c0: i2c@e6508000 {
412 #address-cells = <1>;
413 #size-cells = <0>;
414 compatible = "renesas,i2c-r8a7793";
415 reg = <0 0xe6508000 0 0x40>;
416 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
417 clocks = <&mstp9_clks R8A7793_CLK_I2C0>;
418 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
419 i2c-scl-internal-delay-ns = <6>;
420 status = "disabled";
421 };
422
423 i2c1: i2c@e6518000 {
424 #address-cells = <1>;
425 #size-cells = <0>;
426 compatible = "renesas,i2c-r8a7793";
427 reg = <0 0xe6518000 0 0x40>;
428 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
429 clocks = <&mstp9_clks R8A7793_CLK_I2C1>;
430 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
431 i2c-scl-internal-delay-ns = <6>;
432 status = "disabled";
433 };
434
435 i2c2: i2c@e6530000 {
436 #address-cells = <1>;
437 #size-cells = <0>;
438 compatible = "renesas,i2c-r8a7793";
439 reg = <0 0xe6530000 0 0x40>;
440 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
441 clocks = <&mstp9_clks R8A7793_CLK_I2C2>;
442 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
443 i2c-scl-internal-delay-ns = <6>;
444 status = "disabled";
445 };
446
447 i2c3: i2c@e6540000 {
448 #address-cells = <1>;
449 #size-cells = <0>;
450 compatible = "renesas,i2c-r8a7793";
451 reg = <0 0xe6540000 0 0x40>;
452 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
453 clocks = <&mstp9_clks R8A7793_CLK_I2C3>;
454 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
455 i2c-scl-internal-delay-ns = <6>;
456 status = "disabled";
457 };
458
459 i2c4: i2c@e6520000 {
460 #address-cells = <1>;
461 #size-cells = <0>;
462 compatible = "renesas,i2c-r8a7793";
463 reg = <0 0xe6520000 0 0x40>;
464 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
465 clocks = <&mstp9_clks R8A7793_CLK_I2C4>;
466 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
467 i2c-scl-internal-delay-ns = <6>;
468 status = "disabled";
469 };
470
471 i2c5: i2c@e6528000 {
472 /* doesn't need pinmux */
473 #address-cells = <1>;
474 #size-cells = <0>;
475 compatible = "renesas,i2c-r8a7793";
476 reg = <0 0xe6528000 0 0x40>;
477 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
478 clocks = <&mstp9_clks R8A7793_CLK_I2C5>;
479 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
480 i2c-scl-internal-delay-ns = <110>;
481 status = "disabled";
482 };
483
484 i2c6: i2c@e60b0000 {
485 /* doesn't need pinmux */
486 #address-cells = <1>;
487 #size-cells = <0>;
488 compatible = "renesas,iic-r8a7793", "renesas,rmobile-iic";
489 reg = <0 0xe60b0000 0 0x425>;
490 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
491 clocks = <&mstp9_clks R8A7793_CLK_IICDVFS>;
492 dmas = <&dmac0 0x77>, <&dmac0 0x78>,
493 <&dmac1 0x77>, <&dmac1 0x78>;
494 dma-names = "tx", "rx", "tx", "rx";
495 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
496 status = "disabled";
497 };
498
499 i2c7: i2c@e6500000 {
500 #address-cells = <1>;
501 #size-cells = <0>;
502 compatible = "renesas,iic-r8a7793", "renesas,rmobile-iic";
503 reg = <0 0xe6500000 0 0x425>;
504 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
505 clocks = <&mstp3_clks R8A7793_CLK_IIC0>;
506 dmas = <&dmac0 0x61>, <&dmac0 0x62>,
507 <&dmac1 0x61>, <&dmac1 0x62>;
508 dma-names = "tx", "rx", "tx", "rx";
509 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
510 status = "disabled";
511 };
512
513 i2c8: i2c@e6510000 {
514 #address-cells = <1>;
515 #size-cells = <0>;
516 compatible = "renesas,iic-r8a7793", "renesas,rmobile-iic";
517 reg = <0 0xe6510000 0 0x425>;
518 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
519 clocks = <&mstp3_clks R8A7793_CLK_IIC1>;
520 dmas = <&dmac0 0x65>, <&dmac0 0x66>,
521 <&dmac1 0x65>, <&dmac1 0x66>;
522 dma-names = "tx", "rx", "tx", "rx";
523 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
524 status = "disabled";
525 };
526
527 pfc: pfc@e6060000 {
528 compatible = "renesas,pfc-r8a7793";
529 reg = <0 0xe6060000 0 0x250>;
530 };
531
532 sdhi0: sd@ee100000 {
533 compatible = "renesas,sdhi-r8a7793";
534 reg = <0 0xee100000 0 0x328>;
535 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
536 clocks = <&mstp3_clks R8A7793_CLK_SDHI0>;
537 dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
538 <&dmac1 0xcd>, <&dmac1 0xce>;
539 dma-names = "tx", "rx", "tx", "rx";
540 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
541 status = "disabled";
542 };
543
544 sdhi1: sd@ee140000 {
545 compatible = "renesas,sdhi-r8a7793";
546 reg = <0 0xee140000 0 0x100>;
547 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
548 clocks = <&mstp3_clks R8A7793_CLK_SDHI1>;
549 dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
550 <&dmac1 0xc1>, <&dmac1 0xc2>;
551 dma-names = "tx", "rx", "tx", "rx";
552 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
553 status = "disabled";
554 };
555
556 sdhi2: sd@ee160000 {
557 compatible = "renesas,sdhi-r8a7793";
558 reg = <0 0xee160000 0 0x100>;
559 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
560 clocks = <&mstp3_clks R8A7793_CLK_SDHI2>;
561 dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
562 <&dmac1 0xd3>, <&dmac1 0xd4>;
563 dma-names = "tx", "rx", "tx", "rx";
564 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
565 status = "disabled";
566 };
567
568 mmcif0: mmc@ee200000 {
569 compatible = "renesas,mmcif-r8a7793", "renesas,sh-mmcif";
570 reg = <0 0xee200000 0 0x80>;
571 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
572 clocks = <&mstp3_clks R8A7793_CLK_MMCIF0>;
573 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
574 <&dmac1 0xd1>, <&dmac1 0xd2>;
575 dma-names = "tx", "rx", "tx", "rx";
576 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
577 reg-io-width = <4>;
578 status = "disabled";
579 max-frequency = <97500000>;
580 };
581
582 scifa0: serial@e6c40000 {
583 compatible = "renesas,scifa-r8a7793",
584 "renesas,rcar-gen2-scifa", "renesas,scifa";
585 reg = <0 0xe6c40000 0 64>;
586 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
587 clocks = <&mstp2_clks R8A7793_CLK_SCIFA0>;
588 clock-names = "fck";
589 dmas = <&dmac0 0x21>, <&dmac0 0x22>,
590 <&dmac1 0x21>, <&dmac1 0x22>;
591 dma-names = "tx", "rx", "tx", "rx";
592 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
593 status = "disabled";
594 };
595
596 scifa1: serial@e6c50000 {
597 compatible = "renesas,scifa-r8a7793",
598 "renesas,rcar-gen2-scifa", "renesas,scifa";
599 reg = <0 0xe6c50000 0 64>;
600 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
601 clocks = <&mstp2_clks R8A7793_CLK_SCIFA1>;
602 clock-names = "fck";
603 dmas = <&dmac0 0x25>, <&dmac0 0x26>,
604 <&dmac1 0x25>, <&dmac1 0x26>;
605 dma-names = "tx", "rx", "tx", "rx";
606 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
607 status = "disabled";
608 };
609
610 scifa2: serial@e6c60000 {
611 compatible = "renesas,scifa-r8a7793",
612 "renesas,rcar-gen2-scifa", "renesas,scifa";
613 reg = <0 0xe6c60000 0 64>;
614 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
615 clocks = <&mstp2_clks R8A7793_CLK_SCIFA2>;
616 clock-names = "fck";
617 dmas = <&dmac0 0x27>, <&dmac0 0x28>,
618 <&dmac1 0x27>, <&dmac1 0x28>;
619 dma-names = "tx", "rx", "tx", "rx";
620 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
621 status = "disabled";
622 };
623
624 scifa3: serial@e6c70000 {
625 compatible = "renesas,scifa-r8a7793",
626 "renesas,rcar-gen2-scifa", "renesas,scifa";
627 reg = <0 0xe6c70000 0 64>;
628 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
629 clocks = <&mstp11_clks R8A7793_CLK_SCIFA3>;
630 clock-names = "fck";
631 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
632 <&dmac1 0x1b>, <&dmac1 0x1c>;
633 dma-names = "tx", "rx", "tx", "rx";
634 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
635 status = "disabled";
636 };
637
638 scifa4: serial@e6c78000 {
639 compatible = "renesas,scifa-r8a7793",
640 "renesas,rcar-gen2-scifa", "renesas,scifa";
641 reg = <0 0xe6c78000 0 64>;
642 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
643 clocks = <&mstp11_clks R8A7793_CLK_SCIFA4>;
644 clock-names = "fck";
645 dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
646 <&dmac1 0x1f>, <&dmac1 0x20>;
647 dma-names = "tx", "rx", "tx", "rx";
648 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
649 status = "disabled";
650 };
651
652 scifa5: serial@e6c80000 {
653 compatible = "renesas,scifa-r8a7793",
654 "renesas,rcar-gen2-scifa", "renesas,scifa";
655 reg = <0 0xe6c80000 0 64>;
656 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
657 clocks = <&mstp11_clks R8A7793_CLK_SCIFA5>;
658 clock-names = "fck";
659 dmas = <&dmac0 0x23>, <&dmac0 0x24>,
660 <&dmac1 0x23>, <&dmac1 0x24>;
661 dma-names = "tx", "rx", "tx", "rx";
662 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
663 status = "disabled";
664 };
665
666 scifb0: serial@e6c20000 {
667 compatible = "renesas,scifb-r8a7793",
668 "renesas,rcar-gen2-scifb", "renesas,scifb";
669 reg = <0 0xe6c20000 0 0x100>;
670 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
671 clocks = <&mstp2_clks R8A7793_CLK_SCIFB0>;
672 clock-names = "fck";
673 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
674 <&dmac1 0x3d>, <&dmac1 0x3e>;
675 dma-names = "tx", "rx", "tx", "rx";
676 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
677 status = "disabled";
678 };
679
680 scifb1: serial@e6c30000 {
681 compatible = "renesas,scifb-r8a7793",
682 "renesas,rcar-gen2-scifb", "renesas,scifb";
683 reg = <0 0xe6c30000 0 0x100>;
684 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
685 clocks = <&mstp2_clks R8A7793_CLK_SCIFB1>;
686 clock-names = "fck";
687 dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
688 <&dmac1 0x19>, <&dmac1 0x1a>;
689 dma-names = "tx", "rx", "tx", "rx";
690 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
691 status = "disabled";
692 };
693
694 scifb2: serial@e6ce0000 {
695 compatible = "renesas,scifb-r8a7793",
696 "renesas,rcar-gen2-scifb", "renesas,scifb";
697 reg = <0 0xe6ce0000 0 0x100>;
698 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
699 clocks = <&mstp2_clks R8A7793_CLK_SCIFB2>;
700 clock-names = "fck";
701 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
702 <&dmac1 0x1d>, <&dmac1 0x1e>;
703 dma-names = "tx", "rx", "tx", "rx";
704 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
705 status = "disabled";
706 };
707
708 scif0: serial@e6e60000 {
709 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
710 "renesas,scif";
711 reg = <0 0xe6e60000 0 64>;
712 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
713 clocks = <&mstp7_clks R8A7793_CLK_SCIF0>, <&zs_clk>,
714 <&scif_clk>;
715 clock-names = "fck", "brg_int", "scif_clk";
716 dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
717 <&dmac1 0x29>, <&dmac1 0x2a>;
718 dma-names = "tx", "rx", "tx", "rx";
719 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
720 status = "disabled";
721 };
722
723 scif1: serial@e6e68000 {
724 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
725 "renesas,scif";
726 reg = <0 0xe6e68000 0 64>;
727 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
728 clocks = <&mstp7_clks R8A7793_CLK_SCIF1>, <&zs_clk>,
729 <&scif_clk>;
730 clock-names = "fck", "brg_int", "scif_clk";
731 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
732 <&dmac1 0x2d>, <&dmac1 0x2e>;
733 dma-names = "tx", "rx", "tx", "rx";
734 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
735 status = "disabled";
736 };
737
738 scif2: serial@e6e58000 {
739 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
740 "renesas,scif";
741 reg = <0 0xe6e58000 0 64>;
742 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
743 clocks = <&mstp7_clks R8A7793_CLK_SCIF2>, <&zs_clk>,
744 <&scif_clk>;
745 clock-names = "fck", "brg_int", "scif_clk";
746 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
747 <&dmac1 0x2b>, <&dmac1 0x2c>;
748 dma-names = "tx", "rx", "tx", "rx";
749 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
750 status = "disabled";
751 };
752
753 scif3: serial@e6ea8000 {
754 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
755 "renesas,scif";
756 reg = <0 0xe6ea8000 0 64>;
757 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
758 clocks = <&mstp7_clks R8A7793_CLK_SCIF3>, <&zs_clk>,
759 <&scif_clk>;
760 clock-names = "fck", "brg_int", "scif_clk";
761 dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
762 <&dmac1 0x2f>, <&dmac1 0x30>;
763 dma-names = "tx", "rx", "tx", "rx";
764 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
765 status = "disabled";
766 };
767
768 scif4: serial@e6ee0000 {
769 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
770 "renesas,scif";
771 reg = <0 0xe6ee0000 0 64>;
772 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
773 clocks = <&mstp7_clks R8A7793_CLK_SCIF4>, <&zs_clk>,
774 <&scif_clk>;
775 clock-names = "fck", "brg_int", "scif_clk";
776 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
777 <&dmac1 0xfb>, <&dmac1 0xfc>;
778 dma-names = "tx", "rx", "tx", "rx";
779 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
780 status = "disabled";
781 };
782
783 scif5: serial@e6ee8000 {
784 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
785 "renesas,scif";
786 reg = <0 0xe6ee8000 0 64>;
787 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
788 clocks = <&mstp7_clks R8A7793_CLK_SCIF5>, <&zs_clk>,
789 <&scif_clk>;
790 clock-names = "fck", "brg_int", "scif_clk";
791 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
792 <&dmac1 0xfd>, <&dmac1 0xfe>;
793 dma-names = "tx", "rx", "tx", "rx";
794 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
795 status = "disabled";
796 };
797
798 hscif0: serial@e62c0000 {
799 compatible = "renesas,hscif-r8a7793",
800 "renesas,rcar-gen2-hscif", "renesas,hscif";
801 reg = <0 0xe62c0000 0 96>;
802 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
803 clocks = <&mstp7_clks R8A7793_CLK_HSCIF0>, <&zs_clk>,
804 <&scif_clk>;
805 clock-names = "fck", "brg_int", "scif_clk";
806 dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
807 <&dmac1 0x39>, <&dmac1 0x3a>;
808 dma-names = "tx", "rx", "tx", "rx";
809 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
810 status = "disabled";
811 };
812
813 hscif1: serial@e62c8000 {
814 compatible = "renesas,hscif-r8a7793",
815 "renesas,rcar-gen2-hscif", "renesas,hscif";
816 reg = <0 0xe62c8000 0 96>;
817 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
818 clocks = <&mstp7_clks R8A7793_CLK_HSCIF1>, <&zs_clk>,
819 <&scif_clk>;
820 clock-names = "fck", "brg_int", "scif_clk";
821 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
822 <&dmac1 0x4d>, <&dmac1 0x4e>;
823 dma-names = "tx", "rx", "tx", "rx";
824 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
825 status = "disabled";
826 };
827
828 hscif2: serial@e62d0000 {
829 compatible = "renesas,hscif-r8a7793",
830 "renesas,rcar-gen2-hscif", "renesas,hscif";
831 reg = <0 0xe62d0000 0 96>;
832 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
833 clocks = <&mstp7_clks R8A7793_CLK_HSCIF2>, <&zs_clk>,
834 <&scif_clk>;
835 clock-names = "fck", "brg_int", "scif_clk";
836 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
837 <&dmac1 0x3b>, <&dmac1 0x3c>;
838 dma-names = "tx", "rx", "tx", "rx";
839 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
840 status = "disabled";
841 };
842
843 ether: ethernet@ee700000 {
844 compatible = "renesas,ether-r8a7793";
845 reg = <0 0xee700000 0 0x400>;
846 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
847 clocks = <&mstp8_clks R8A7793_CLK_ETHER>;
848 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
849 phy-mode = "rmii";
850 #address-cells = <1>;
851 #size-cells = <0>;
852 status = "disabled";
853 };
854
855 vin0: video@e6ef0000 {
856 compatible = "renesas,vin-r8a7793", "renesas,rcar-gen2-vin";
857 reg = <0 0xe6ef0000 0 0x1000>;
858 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
859 clocks = <&mstp8_clks R8A7793_CLK_VIN0>;
860 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
861 status = "disabled";
862 };
863
864 vin1: video@e6ef1000 {
865 compatible = "renesas,vin-r8a7793", "renesas,rcar-gen2-vin";
866 reg = <0 0xe6ef1000 0 0x1000>;
867 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
868 clocks = <&mstp8_clks R8A7793_CLK_VIN1>;
869 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
870 status = "disabled";
871 };
872
873 vin2: video@e6ef2000 {
874 compatible = "renesas,vin-r8a7793", "renesas,rcar-gen2-vin";
875 reg = <0 0xe6ef2000 0 0x1000>;
876 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
877 clocks = <&mstp8_clks R8A7793_CLK_VIN2>;
878 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
879 status = "disabled";
880 };
881
882 qspi: spi@e6b10000 {
883 compatible = "renesas,qspi-r8a7793", "renesas,qspi";
884 reg = <0 0xe6b10000 0 0x2c>;
885 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
886 clocks = <&mstp9_clks R8A7793_CLK_QSPI_MOD>;
887 dmas = <&dmac0 0x17>, <&dmac0 0x18>,
888 <&dmac1 0x17>, <&dmac1 0x18>;
889 dma-names = "tx", "rx", "tx", "rx";
890 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
891 num-cs = <1>;
892 #address-cells = <1>;
893 #size-cells = <0>;
894 status = "disabled";
895 };
896
897 du: display@feb00000 {
898 compatible = "renesas,du-r8a7793";
899 reg = <0 0xfeb00000 0 0x40000>,
900 <0 0xfeb90000 0 0x1c>;
901 reg-names = "du", "lvds.0";
902 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
903 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
904 clocks = <&mstp7_clks R8A7793_CLK_DU0>,
905 <&mstp7_clks R8A7793_CLK_DU1>,
906 <&mstp7_clks R8A7793_CLK_LVDS0>;
907 clock-names = "du.0", "du.1", "lvds.0";
908 status = "disabled";
909
910 ports {
911 #address-cells = <1>;
912 #size-cells = <0>;
913
914 port@0 {
915 reg = <0>;
916 du_out_rgb: endpoint {
917 };
918 };
919 port@1 {
920 reg = <1>;
921 du_out_lvds0: endpoint {
922 };
923 };
924 };
925 };
926
927 can0: can@e6e80000 {
928 compatible = "renesas,can-r8a7793", "renesas,rcar-gen2-can";
929 reg = <0 0xe6e80000 0 0x1000>;
930 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
931 clocks = <&mstp9_clks R8A7793_CLK_RCAN0>,
932 <&cpg_clocks R8A7793_CLK_RCAN>, <&can_clk>;
933 clock-names = "clkp1", "clkp2", "can_clk";
934 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
935 status = "disabled";
936 };
937
938 can1: can@e6e88000 {
939 compatible = "renesas,can-r8a7793", "renesas,rcar-gen2-can";
940 reg = <0 0xe6e88000 0 0x1000>;
941 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
942 clocks = <&mstp9_clks R8A7793_CLK_RCAN1>,
943 <&cpg_clocks R8A7793_CLK_RCAN>, <&can_clk>;
944 clock-names = "clkp1", "clkp2", "can_clk";
945 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
946 status = "disabled";
947 };
948
949 clocks {
950 #address-cells = <2>;
951 #size-cells = <2>;
952 ranges;
953
954 /* External root clock */
955 extal_clk: extal {
956 compatible = "fixed-clock";
957 #clock-cells = <0>;
958 /* This value must be overridden by the board. */
959 clock-frequency = <0>;
960 };
961
962 /*
963 * The external audio clocks are configured as 0 Hz fixed frequency clocks by
964 * default. Boards that provide audio clocks should override them.
965 */
966 audio_clk_a: audio_clk_a {
967 compatible = "fixed-clock";
968 #clock-cells = <0>;
969 clock-frequency = <0>;
970 };
971 audio_clk_b: audio_clk_b {
972 compatible = "fixed-clock";
973 #clock-cells = <0>;
974 clock-frequency = <0>;
975 };
976 audio_clk_c: audio_clk_c {
977 compatible = "fixed-clock";
978 #clock-cells = <0>;
979 clock-frequency = <0>;
980 };
981
982 /* External USB clock - can be overridden by the board */
983 usb_extal_clk: usb_extal {
984 compatible = "fixed-clock";
985 #clock-cells = <0>;
986 clock-frequency = <48000000>;
987 };
988
989 /* External CAN clock */
990 can_clk: can {
991 compatible = "fixed-clock";
992 #clock-cells = <0>;
993 /* This value must be overridden by the board. */
994 clock-frequency = <0>;
995 };
996
997 /* External SCIF clock */
998 scif_clk: scif {
999 compatible = "fixed-clock";
1000 #clock-cells = <0>;
1001 /* This value must be overridden by the board. */
1002 clock-frequency = <0>;
1003 };
1004
1005 /* Special CPG clocks */
1006 cpg_clocks: cpg_clocks@e6150000 {
1007 compatible = "renesas,r8a7793-cpg-clocks",
1008 "renesas,rcar-gen2-cpg-clocks";
1009 reg = <0 0xe6150000 0 0x1000>;
1010 clocks = <&extal_clk &usb_extal_clk>;
1011 #clock-cells = <1>;
1012 clock-output-names = "main", "pll0", "pll1", "pll3",
1013 "lb", "qspi", "sdh", "sd0", "z",
1014 "rcan", "adsp";
1015 #power-domain-cells = <0>;
1016 };
1017
1018 /* Variable factor clocks */
1019 sd2_clk: sd2@e6150078 {
1020 compatible = "renesas,r8a7793-div6-clock",
1021 "renesas,cpg-div6-clock";
1022 reg = <0 0xe6150078 0 4>;
1023 clocks = <&pll1_div2_clk>;
1024 #clock-cells = <0>;
1025 };
1026 sd3_clk: sd3@e615026c {
1027 compatible = "renesas,r8a7793-div6-clock",
1028 "renesas,cpg-div6-clock";
1029 reg = <0 0xe615026c 0 4>;
1030 clocks = <&pll1_div2_clk>;
1031 #clock-cells = <0>;
1032 };
1033 mmc0_clk: mmc0@e6150240 {
1034 compatible = "renesas,r8a7793-div6-clock",
1035 "renesas,cpg-div6-clock";
1036 reg = <0 0xe6150240 0 4>;
1037 clocks = <&pll1_div2_clk>;
1038 #clock-cells = <0>;
1039 };
1040
1041 /* Fixed factor clocks */
1042 pll1_div2_clk: pll1_div2 {
1043 compatible = "fixed-factor-clock";
1044 clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
1045 #clock-cells = <0>;
1046 clock-div = <2>;
1047 clock-mult = <1>;
1048 };
1049 zg_clk: zg {
1050 compatible = "fixed-factor-clock";
1051 clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
1052 #clock-cells = <0>;
1053 clock-div = <5>;
1054 clock-mult = <1>;
1055 };
1056 zx_clk: zx {
1057 compatible = "fixed-factor-clock";
1058 clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
1059 #clock-cells = <0>;
1060 clock-div = <3>;
1061 clock-mult = <1>;
1062 };
1063 zs_clk: zs {
1064 compatible = "fixed-factor-clock";
1065 clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
1066 #clock-cells = <0>;
1067 clock-div = <6>;
1068 clock-mult = <1>;
1069 };
1070 hp_clk: hp {
1071 compatible = "fixed-factor-clock";
1072 clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
1073 #clock-cells = <0>;
1074 clock-div = <12>;
1075 clock-mult = <1>;
1076 };
1077 p_clk: p {
1078 compatible = "fixed-factor-clock";
1079 clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
1080 #clock-cells = <0>;
1081 clock-div = <24>;
1082 clock-mult = <1>;
1083 };
1084 m2_clk: m2 {
1085 compatible = "fixed-factor-clock";
1086 clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
1087 #clock-cells = <0>;
1088 clock-div = <8>;
1089 clock-mult = <1>;
1090 };
1091 rclk_clk: rclk {
1092 compatible = "fixed-factor-clock";
1093 clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
1094 #clock-cells = <0>;
1095 clock-div = <(48 * 1024)>;
1096 clock-mult = <1>;
1097 };
1098 mp_clk: mp {
1099 compatible = "fixed-factor-clock";
1100 clocks = <&pll1_div2_clk>;
1101 #clock-cells = <0>;
1102 clock-div = <15>;
1103 clock-mult = <1>;
1104 };
1105 cp_clk: cp {
1106 compatible = "fixed-factor-clock";
1107 clocks = <&extal_clk>;
1108 #clock-cells = <0>;
1109 clock-div = <2>;
1110 clock-mult = <1>;
1111 };
1112
1113 /* Gate clocks */
1114 mstp1_clks: mstp1_clks@e6150134 {
1115 compatible = "renesas,r8a7793-mstp-clocks",
1116 "renesas,cpg-mstp-clocks";
1117 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
1118 clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
1119 <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>,
1120 <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>,
1121 <&zs_clk>, <&zs_clk>, <&zs_clk>;
1122 #clock-cells = <1>;
1123 clock-indices = <
1124 R8A7793_CLK_VCP0 R8A7793_CLK_VPC0
1125 R8A7793_CLK_SSP1 R8A7793_CLK_TMU1
1126 R8A7793_CLK_3DG R8A7793_CLK_2DDMAC
1127 R8A7793_CLK_FDP1_1 R8A7793_CLK_FDP1_0
1128 R8A7793_CLK_TMU3 R8A7793_CLK_TMU2
1129 R8A7793_CLK_CMT0 R8A7793_CLK_TMU0
1130 R8A7793_CLK_VSP1_DU1 R8A7793_CLK_VSP1_DU0
1131 R8A7793_CLK_VSP1_S
1132 >;
1133 clock-output-names =
1134 "vcp0", "vpc0", "ssp_dev", "tmu1",
1135 "pvrsrvkm", "tddmac", "fdp1", "fdp0",
1136 "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
1137 "vsp1-du0", "vsps";
1138 };
1139 mstp2_clks: mstp2_clks@e6150138 {
1140 compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
1141 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
1142 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
1143 <&mp_clk>, <&mp_clk>, <&zs_clk>, <&zs_clk>;
1144 #clock-cells = <1>;
1145 clock-indices = <
1146 R8A7793_CLK_SCIFA2 R8A7793_CLK_SCIFA1 R8A7793_CLK_SCIFA0
1147 R8A7793_CLK_SCIFB0 R8A7793_CLK_SCIFB1 R8A7793_CLK_SCIFB2
1148 R8A7793_CLK_SYS_DMAC1 R8A7793_CLK_SYS_DMAC0
1149 >;
1150 clock-output-names =
1151 "scifa2", "scifa1", "scifa0", "scifb0",
1152 "scifb1", "scifb2", "sys-dmac1", "sys-dmac0";
1153 };
1154 mstp3_clks: mstp3_clks@e615013c {
1155 compatible = "renesas,r8a7793-mstp-clocks",
1156 "renesas,cpg-mstp-clocks";
1157 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
1158 clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>,
1159 <&cpg_clocks R8A7793_CLK_SD0>, <&mmc0_clk>,
1160 <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>,
1161 <&rclk_clk>, <&hp_clk>, <&hp_clk>;
1162 #clock-cells = <1>;
1163 clock-indices = <
1164 R8A7793_CLK_TPU0 R8A7793_CLK_SDHI2
1165 R8A7793_CLK_SDHI1 R8A7793_CLK_SDHI0
1166 R8A7793_CLK_MMCIF0 R8A7793_CLK_IIC0
1167 R8A7793_CLK_PCIEC R8A7793_CLK_IIC1
1168 R8A7793_CLK_SSUSB R8A7793_CLK_CMT1
1169 R8A7793_CLK_USBDMAC0 R8A7793_CLK_USBDMAC1
1170 >;
1171 clock-output-names =
1172 "tpu0", "sdhi2", "sdhi1", "sdhi0", "mmcif0",
1173 "i2c7", "pciec", "i2c8", "ssusb", "cmt1",
1174 "usbdmac0", "usbdmac1";
1175 };
1176 mstp4_clks: mstp4_clks@e6150140 {
1177 compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
1178 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
1179 clocks = <&cp_clk>;
1180 #clock-cells = <1>;
1181 clock-indices = <R8A7793_CLK_IRQC>;
1182 clock-output-names = "irqc";
1183 };
1184 mstp5_clks: mstp5_clks@e6150144 {
1185 compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
1186 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
1187 clocks = <&hp_clk>, <&hp_clk>, <&extal_clk>;
1188 #clock-cells = <1>;
1189 clock-indices = <R8A7793_CLK_AUDIO_DMAC0 R8A7793_CLK_AUDIO_DMAC1
1190 R8A7793_CLK_THERMAL>;
1191 clock-output-names = "audmac0", "audmac1", "thermal";
1192 };
1193 mstp7_clks: mstp7_clks@e615014c {
1194 compatible = "renesas,r8a7793-mstp-clocks",
1195 "renesas,cpg-mstp-clocks";
1196 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
1197 clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&p_clk>,
1198 <&p_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
1199 <&p_clk>, <&p_clk>, <&p_clk>, <&zx_clk>,
1200 <&zx_clk>, <&zx_clk>;
1201 #clock-cells = <1>;
1202 clock-indices = <
1203 R8A7793_CLK_EHCI R8A7793_CLK_HSUSB
1204 R8A7793_CLK_HSCIF2 R8A7793_CLK_SCIF5
1205 R8A7793_CLK_SCIF4 R8A7793_CLK_HSCIF1
1206 R8A7793_CLK_HSCIF0 R8A7793_CLK_SCIF3
1207 R8A7793_CLK_SCIF2 R8A7793_CLK_SCIF1
1208 R8A7793_CLK_SCIF0 R8A7793_CLK_DU1
1209 R8A7793_CLK_DU0 R8A7793_CLK_LVDS0
1210 >;
1211 clock-output-names =
1212 "ehci", "hsusb", "hscif2", "scif5", "scif4",
1213 "hscif1", "hscif0", "scif3", "scif2",
1214 "scif1", "scif0", "du1", "du0", "lvds0";
1215 };
1216 mstp8_clks: mstp8_clks@e6150990 {
1217 compatible = "renesas,r8a7793-mstp-clocks",
1218 "renesas,cpg-mstp-clocks";
1219 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
1220 clocks = <&zx_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
1221 <&p_clk>, <&zs_clk>, <&zs_clk>;
1222 #clock-cells = <1>;
1223 clock-indices = <
1224 R8A7793_CLK_IPMMU_SGX R8A7793_CLK_VIN2
1225 R8A7793_CLK_VIN1 R8A7793_CLK_VIN0
1226 R8A7793_CLK_ETHER R8A7793_CLK_SATA1
1227 R8A7793_CLK_SATA0
1228 >;
1229 clock-output-names =
1230 "ipmmu_sgx", "vin2", "vin1", "vin0", "ether",
1231 "sata1", "sata0";
1232 };
1233 mstp9_clks: mstp9_clks@e6150994 {
1234 compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
1235 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
1236 clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1237 <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1238 <&p_clk>, <&p_clk>,
1239 <&cpg_clocks R8A7793_CLK_QSPI>, <&hp_clk>,
1240 <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
1241 <&hp_clk>, <&hp_clk>;
1242 #clock-cells = <1>;
1243 clock-indices = <
1244 R8A7793_CLK_GPIO7 R8A7793_CLK_GPIO6
1245 R8A7793_CLK_GPIO5 R8A7793_CLK_GPIO4
1246 R8A7793_CLK_GPIO3 R8A7793_CLK_GPIO2
1247 R8A7793_CLK_GPIO1 R8A7793_CLK_GPIO0
1248 R8A7793_CLK_QSPI_MOD R8A7793_CLK_RCAN1
1249 R8A7793_CLK_RCAN0 R8A7793_CLK_I2C5
1250 R8A7793_CLK_IICDVFS R8A7793_CLK_I2C4
1251 R8A7793_CLK_I2C3 R8A7793_CLK_I2C2
1252 R8A7793_CLK_I2C1 R8A7793_CLK_I2C0
1253 >;
1254 clock-output-names =
1255 "gpio7", "gpio6", "gpio5", "gpio4",
1256 "gpio3", "gpio2", "gpio1", "gpio0",
1257 "rcan1", "rcan0", "qspi_mod", "i2c5",
1258 "i2c6", "i2c4", "i2c3", "i2c2", "i2c1",
1259 "i2c0";
1260 };
1261 mstp10_clks: mstp10_clks@e6150998 {
1262 compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
1263 reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
1264 clocks = <&p_clk>,
1265 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1266 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1267 <&p_clk>,
1268 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
1269 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
1270 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
1271 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
1272 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
1273 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
1274 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>;
1275
1276 #clock-cells = <1>;
1277 clock-indices = <
1278 R8A7793_CLK_SSI_ALL
1279 R8A7793_CLK_SSI9 R8A7793_CLK_SSI8 R8A7793_CLK_SSI7 R8A7793_CLK_SSI6 R8A7793_CLK_SSI5
1280 R8A7793_CLK_SSI4 R8A7793_CLK_SSI3 R8A7793_CLK_SSI2 R8A7793_CLK_SSI1 R8A7793_CLK_SSI0
1281 R8A7793_CLK_SCU_ALL
1282 R8A7793_CLK_SCU_DVC1 R8A7793_CLK_SCU_DVC0
1283 R8A7793_CLK_SCU_CTU1_MIX1 R8A7793_CLK_SCU_CTU0_MIX0
1284 R8A7793_CLK_SCU_SRC9 R8A7793_CLK_SCU_SRC8 R8A7793_CLK_SCU_SRC7 R8A7793_CLK_SCU_SRC6 R8A7793_CLK_SCU_SRC5
1285 R8A7793_CLK_SCU_SRC4 R8A7793_CLK_SCU_SRC3 R8A7793_CLK_SCU_SRC2 R8A7793_CLK_SCU_SRC1 R8A7793_CLK_SCU_SRC0
1286 >;
1287 clock-output-names =
1288 "ssi-all",
1289 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
1290 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
1291 "scu-all",
1292 "scu-dvc1", "scu-dvc0",
1293 "scu-ctu1-mix1", "scu-ctu0-mix0",
1294 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
1295 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
1296 };
1297 mstp11_clks: mstp11_clks@e615099c {
1298 compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
1299 reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
1300 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
1301 #clock-cells = <1>;
1302 clock-indices = <
1303 R8A7793_CLK_SCIFA3 R8A7793_CLK_SCIFA4 R8A7793_CLK_SCIFA5
1304 >;
1305 clock-output-names = "scifa3", "scifa4", "scifa5";
1306 };
1307 };
1308
1309 rst: reset-controller@e6160000 {
1310 compatible = "renesas,r8a7793-rst";
1311 reg = <0 0xe6160000 0 0x0100>;
1312 };
1313
1314 prr: chipid@ff000044 {
1315 compatible = "renesas,prr";
1316 reg = <0 0xff000044 0 4>;
1317 };
1318
1319 sysc: system-controller@e6180000 {
1320 compatible = "renesas,r8a7793-sysc";
1321 reg = <0 0xe6180000 0 0x0200>;
1322 #power-domain-cells = <1>;
1323 };
1324
1325 ipmmu_sy0: mmu@e6280000 {
1326 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1327 reg = <0 0xe6280000 0 0x1000>;
1328 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
1329 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
1330 #iommu-cells = <1>;
1331 status = "disabled";
1332 };
1333
1334 ipmmu_sy1: mmu@e6290000 {
1335 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1336 reg = <0 0xe6290000 0 0x1000>;
1337 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1338 #iommu-cells = <1>;
1339 status = "disabled";
1340 };
1341
1342 ipmmu_ds: mmu@e6740000 {
1343 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1344 reg = <0 0xe6740000 0 0x1000>;
1345 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1346 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
1347 #iommu-cells = <1>;
1348 status = "disabled";
1349 };
1350
1351 ipmmu_mp: mmu@ec680000 {
1352 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1353 reg = <0 0xec680000 0 0x1000>;
1354 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1355 #iommu-cells = <1>;
1356 status = "disabled";
1357 };
1358
1359 ipmmu_mx: mmu@fe951000 {
1360 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1361 reg = <0 0xfe951000 0 0x1000>;
1362 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
1363 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1364 #iommu-cells = <1>;
1365 status = "disabled";
1366 };
1367
1368 ipmmu_rt: mmu@ffc80000 {
1369 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1370 reg = <0 0xffc80000 0 0x1000>;
1371 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
1372 #iommu-cells = <1>;
1373 status = "disabled";
1374 };
1375
1376 ipmmu_gp: mmu@e62a0000 {
1377 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1378 reg = <0 0xe62a0000 0 0x1000>;
1379 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
1380 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
1381 #iommu-cells = <1>;
1382 status = "disabled";
1383 };
1384
1385 rcar_sound: sound@ec500000 {
1386 /*
1387 * #sound-dai-cells is required
1388 *
1389 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1390 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1391 */
1392 compatible = "renesas,rcar_sound-r8a7793", "renesas,rcar_sound-gen2";
1393 reg = <0 0xec500000 0 0x1000>, /* SCU */
1394 <0 0xec5a0000 0 0x100>, /* ADG */
1395 <0 0xec540000 0 0x1000>, /* SSIU */
1396 <0 0xec541000 0 0x280>, /* SSI */
1397 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
1398 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1399
1400 clocks = <&mstp10_clks R8A7793_CLK_SSI_ALL>,
1401 <&mstp10_clks R8A7793_CLK_SSI9>, <&mstp10_clks R8A7793_CLK_SSI8>,
1402 <&mstp10_clks R8A7793_CLK_SSI7>, <&mstp10_clks R8A7793_CLK_SSI6>,
1403 <&mstp10_clks R8A7793_CLK_SSI5>, <&mstp10_clks R8A7793_CLK_SSI4>,
1404 <&mstp10_clks R8A7793_CLK_SSI3>, <&mstp10_clks R8A7793_CLK_SSI2>,
1405 <&mstp10_clks R8A7793_CLK_SSI1>, <&mstp10_clks R8A7793_CLK_SSI0>,
1406 <&mstp10_clks R8A7793_CLK_SCU_SRC9>, <&mstp10_clks R8A7793_CLK_SCU_SRC8>,
1407 <&mstp10_clks R8A7793_CLK_SCU_SRC7>, <&mstp10_clks R8A7793_CLK_SCU_SRC6>,
1408 <&mstp10_clks R8A7793_CLK_SCU_SRC5>, <&mstp10_clks R8A7793_CLK_SCU_SRC4>,
1409 <&mstp10_clks R8A7793_CLK_SCU_SRC3>, <&mstp10_clks R8A7793_CLK_SCU_SRC2>,
1410 <&mstp10_clks R8A7793_CLK_SCU_SRC1>, <&mstp10_clks R8A7793_CLK_SCU_SRC0>,
1411 <&mstp10_clks R8A7793_CLK_SCU_DVC0>, <&mstp10_clks R8A7793_CLK_SCU_DVC1>,
1412 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
1413 clock-names = "ssi-all",
1414 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1415 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1416 "src.9", "src.8", "src.7", "src.6", "src.5",
1417 "src.4", "src.3", "src.2", "src.1", "src.0",
1418 "dvc.0", "dvc.1",
1419 "clk_a", "clk_b", "clk_c", "clk_i";
1420 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
1421
1422 status = "disabled";
1423
1424 rcar_sound,dvc {
1425 dvc0: dvc-0 {
1426 dmas = <&audma0 0xbc>;
1427 dma-names = "tx";
1428 };
1429 dvc1: dvc-1 {
1430 dmas = <&audma0 0xbe>;
1431 dma-names = "tx";
1432 };
1433 };
1434
1435 rcar_sound,src {
1436 src0: src-0 {
1437 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1438 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1439 dma-names = "rx", "tx";
1440 };
1441 src1: src-1 {
1442 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1443 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1444 dma-names = "rx", "tx";
1445 };
1446 src2: src-2 {
1447 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1448 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1449 dma-names = "rx", "tx";
1450 };
1451 src3: src-3 {
1452 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1453 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1454 dma-names = "rx", "tx";
1455 };
1456 src4: src-4 {
1457 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1458 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1459 dma-names = "rx", "tx";
1460 };
1461 src5: src-5 {
1462 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1463 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1464 dma-names = "rx", "tx";
1465 };
1466 src6: src-6 {
1467 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1468 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1469 dma-names = "rx", "tx";
1470 };
1471 src7: src-7 {
1472 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1473 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1474 dma-names = "rx", "tx";
1475 };
1476 src8: src-8 {
1477 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1478 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1479 dma-names = "rx", "tx";
1480 };
1481 src9: src-9 {
1482 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1483 dmas = <&audma0 0x97>, <&audma1 0xba>;
1484 dma-names = "rx", "tx";
1485 };
1486 };
1487
1488 rcar_sound,ssi {
1489 ssi0: ssi-0 {
1490 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1491 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
1492 dma-names = "rx", "tx", "rxu", "txu";
1493 };
1494 ssi1: ssi-1 {
1495 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1496 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
1497 dma-names = "rx", "tx", "rxu", "txu";
1498 };
1499 ssi2: ssi-2 {
1500 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1501 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
1502 dma-names = "rx", "tx", "rxu", "txu";
1503 };
1504 ssi3: ssi-3 {
1505 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1506 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
1507 dma-names = "rx", "tx", "rxu", "txu";
1508 };
1509 ssi4: ssi-4 {
1510 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1511 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
1512 dma-names = "rx", "tx", "rxu", "txu";
1513 };
1514 ssi5: ssi-5 {
1515 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1516 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
1517 dma-names = "rx", "tx", "rxu", "txu";
1518 };
1519 ssi6: ssi-6 {
1520 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1521 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
1522 dma-names = "rx", "tx", "rxu", "txu";
1523 };
1524 ssi7: ssi-7 {
1525 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1526 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
1527 dma-names = "rx", "tx", "rxu", "txu";
1528 };
1529 ssi8: ssi-8 {
1530 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1531 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
1532 dma-names = "rx", "tx", "rxu", "txu";
1533 };
1534 ssi9: ssi-9 {
1535 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1536 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
1537 dma-names = "rx", "tx", "rxu", "txu";
1538 };
1539 };
1540 };
1541};