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1/*
2 * Device Tree file for the Turris Omnia
3 *
4 * Copyright (C) 2016 Uwe Kleine-König <uwe@kleine-koenig.org>
5 * Copyright (C) 2016 Tomas Hlavacek <tmshlvkc@gmail.com>
6 *
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
10 * whole.
11 *
12 * a) This file is licensed under the terms of the GNU General Public
13 * License version 2. This program is licensed "as is" without
14 * any warranty of any kind, whether express or implied.
15 *
16 * Or, alternatively,
17 *
18 * b) Permission is hereby granted, free of charge, to any person
19 * obtaining a copy of this software and associated documentation
20 * files (the "Software"), to deal in the Software without
21 * restriction, including without limitation the rights to use,
22 * copy, modify, merge, publish, distribute, sublicense, and/or
23 * sell copies of the Software, and to permit persons to whom the
24 * Software is furnished to do so, subject to the following
25 * conditions:
26 *
27 * The above copyright notice and this permission notice shall be
28 * included in all copies or substantial portions of the Software.
29 *
30 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
31 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
32 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
33 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
34 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
35 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
36 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
37 * OTHER DEALINGS IN THE SOFTWARE.
38 */
39
40/*
41 * Schematic available at https://www.turris.cz/doc/_media/rtrom01-schema.pdf
42 */
43
44/dts-v1/;
45
46#include <dt-bindings/gpio/gpio.h>
47#include <dt-bindings/input/input.h>
48#include "armada-385.dtsi"
49
50/ {
51 model = "Turris Omnia";
52 compatible = "cznic,turris-omnia", "marvell,armada385", "marvell,armada380";
53
54 chosen {
55 stdout-path = &uart0;
56 };
57
58 memory {
59 device_type = "memory";
60 reg = <0x00000000 0x40000000>; /* 1024 MB */
61 };
62
63 soc {
64 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
65 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
66 MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
67 MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
68
69 internal-regs {
70
71 /* USB part of the PCIe2/USB 2.0 port */
72 usb@58000 {
73 status = "okay";
74 };
75
76 sata@a8000 {
77 status = "okay";
78 };
79
80 sdhci@d8000 {
81 pinctrl-names = "default";
82 pinctrl-0 = <&sdhci_pins>;
83 status = "okay";
84
85 bus-width = <8>;
86 no-1-8-v;
87 non-removable;
88 };
89
90 usb3@f0000 {
91 status = "okay";
92 };
93
94 usb3@f8000 {
95 status = "okay";
96 };
97 };
98
99 pcie-controller {
100 status = "okay";
101
102 pcie@1,0 {
103 /* Port 0, Lane 0 */
104 status = "okay";
105 };
106
107 pcie@2,0 {
108 /* Port 1, Lane 0 */
109 status = "okay";
110 };
111
112 pcie@3,0 {
113 /* Port 2, Lane 0 */
114 status = "okay";
115 };
116 };
117 };
118};
119
120/* Connected to 88E6176 switch, port 6 */
121ð0 {
122 pinctrl-names = "default";
123 pinctrl-0 = <&ge0_rgmii_pins>;
124 status = "okay";
125 phy-mode = "rgmii-id";
126
127 fixed-link {
128 speed = <1000>;
129 full-duplex;
130 };
131};
132
133/* Connected to 88E6176 switch, port 5 */
134ð1 {
135 pinctrl-names = "default";
136 pinctrl-0 = <&ge1_rgmii_pins>;
137 status = "okay";
138 phy-mode = "rgmii-id";
139
140 fixed-link {
141 speed = <1000>;
142 full-duplex;
143 };
144};
145
146/* WAN port */
147ð2 {
148 status = "okay";
149 phy-mode = "sgmii";
150 phy = <&phy1>;
151};
152
153&i2c0 {
154 pinctrl-names = "default";
155 pinctrl-0 = <&i2c0_pins>;
156 status = "okay";
157
158 i2cmux@70 {
159 compatible = "nxp,pca9547";
160 #address-cells = <1>;
161 #size-cells = <0>;
162 reg = <0x70>;
163 status = "okay";
164
165 i2c@0 {
166 #address-cells = <1>;
167 #size-cells = <0>;
168 reg = <0>;
169
170 /* STM32F0 command interface at address 0x2a */
171 /* leds device (in STM32F0) at address 0x2b */
172
173 eeprom@54 {
174 compatible = "at,24c64";
175 reg = <0x54>;
176
177 /* The EEPROM contains data for bootloader.
178 * Contents:
179 * struct omnia_eeprom {
180 * u32 magic; (=0x0341a034 in LE)
181 * u32 ramsize; (in GiB)
182 * char regdomain[4];
183 * u32 crc32;
184 * };
185 */
186 };
187 };
188
189 i2c@1 {
190 #address-cells = <1>;
191 #size-cells = <0>;
192 reg = <1>;
193
194 /* routed to PCIe0/mSATA connector (CN7A) */
195 };
196
197 i2c@2 {
198 #address-cells = <1>;
199 #size-cells = <0>;
200 reg = <2>;
201
202 /* routed to PCIe1/USB2 connector (CN61A) */
203 };
204
205 i2c@3 {
206 #address-cells = <1>;
207 #size-cells = <0>;
208 reg = <3>;
209
210 /* routed to PCIe2 connector (CN62A) */
211 };
212
213 i2c@4 {
214 #address-cells = <1>;
215 #size-cells = <0>;
216 reg = <4>;
217
218 /* routed to SFP+ */
219 };
220
221 i2c@5 {
222 #address-cells = <1>;
223 #size-cells = <0>;
224 reg = <5>;
225
226 /* ATSHA204A at address 0x64 */
227 };
228
229 i2c@6 {
230 #address-cells = <1>;
231 #size-cells = <0>;
232 reg = <6>;
233
234 /* exposed on pin header */
235 };
236
237 i2c@7 {
238 #address-cells = <1>;
239 #size-cells = <0>;
240 reg = <7>;
241
242 pcawan: gpio@71 {
243 /*
244 * GPIO expander for SFP+ signals and
245 * and phy irq
246 */
247 compatible = "nxp,pca9538";
248 reg = <0x71>;
249
250 pinctrl-names = "default";
251 pinctrl-0 = <&pcawan_pins>;
252
253 interrupt-parent = <&gpio1>;
254 interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
255
256 gpio-controller;
257 #gpio-cells = <2>;
258 };
259 };
260 };
261};
262
263&mdio {
264 pinctrl-names = "default";
265 pinctrl-0 = <&mdio_pins>;
266 status = "okay";
267
268 phy1: phy@1 {
269 status = "okay";
270 compatible = "ethernet-phy-id0141.0DD1", "ethernet-phy-ieee802.3-c22";
271 reg = <1>;
272
273 /* irq is connected to &pcawan pin 7 */
274 };
275
276 /* Switch MV88E7176 at address 0x10 */
277};
278
279&pinctrl {
280 pcawan_pins: pcawan-pins {
281 marvell,pins = "mpp46";
282 marvell,function = "gpio";
283 };
284
285 spi0cs0_pins: spi0cs0-pins {
286 marvell,pins = "mpp25";
287 marvell,function = "spi0";
288 };
289
290 spi0cs1_pins: spi0cs1-pins {
291 marvell,pins = "mpp26";
292 marvell,function = "spi0";
293 };
294};
295
296&spi0 {
297 pinctrl-names = "default";
298 pinctrl-0 = <&spi0_pins &spi0cs0_pins>;
299 status = "okay";
300
301 spi-nor@0 {
302 compatible = "spansion,s25fl164k", "jedec,spi-nor";
303 #address-cells = <1>;
304 #size-cells = <1>;
305 reg = <0>;
306 spi-max-frequency = <40000000>;
307
308 partitions {
309 compatible = "fixed-partitions";
310 #address-cells = <1>;
311 #size-cells = <1>;
312
313 partition@0 {
314 reg = <0x0 0x00100000>;
315 label = "U-Boot";
316 };
317
318 partition@100000 {
319 reg = <0x00100000 0x00700000>;
320 label = "Rescue system";
321 };
322 };
323 };
324
325 /* MISO, MOSI, SCLK and CS1 are routed to pin header CN11 */
326};
327
328&uart0 {
329 /* Pin header CN10 */
330 pinctrl-names = "default";
331 pinctrl-0 = <&uart0_pins>;
332 status = "okay";
333};
334
335&uart1 {
336 /* Pin header CN11 */
337 pinctrl-names = "default";
338 pinctrl-0 = <&uart1_pins>;
339 status = "okay";
340};