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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * wm8962.c -- WM8962 ALSA SoC Audio driver
4 *
5 * Copyright 2010-2 Wolfson Microelectronics plc
6 *
7 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 */
9
10#include <linux/module.h>
11#include <linux/moduleparam.h>
12#include <linux/init.h>
13#include <linux/clk.h>
14#include <linux/delay.h>
15#include <linux/pm.h>
16#include <linux/gcd.h>
17#include <linux/gpio/driver.h>
18#include <linux/i2c.h>
19#include <linux/input.h>
20#include <linux/pm_runtime.h>
21#include <linux/regmap.h>
22#include <linux/regulator/consumer.h>
23#include <linux/slab.h>
24#include <linux/workqueue.h>
25#include <linux/mutex.h>
26#include <sound/core.h>
27#include <sound/jack.h>
28#include <sound/pcm.h>
29#include <sound/pcm_params.h>
30#include <sound/soc.h>
31#include <sound/initval.h>
32#include <sound/tlv.h>
33#include <sound/wm8962.h>
34#include <trace/events/asoc.h>
35
36#include "wm8962.h"
37
38#define WM8962_NUM_SUPPLIES 8
39static const char *wm8962_supply_names[WM8962_NUM_SUPPLIES] = {
40 "DCVDD",
41 "DBVDD",
42 "AVDD",
43 "CPVDD",
44 "MICVDD",
45 "PLLVDD",
46 "SPKVDD1",
47 "SPKVDD2",
48};
49
50/* codec private data */
51struct wm8962_priv {
52 struct wm8962_pdata pdata;
53 struct regmap *regmap;
54 struct snd_soc_component *component;
55
56 int sysclk;
57 int sysclk_rate;
58
59 int bclk; /* Desired BCLK */
60 int lrclk;
61
62 struct completion fll_lock;
63 int fll_src;
64 int fll_fref;
65 int fll_fout;
66
67 struct mutex dsp2_ena_lock;
68 u16 dsp2_ena;
69
70 struct delayed_work mic_work;
71 struct snd_soc_jack *jack;
72
73 struct regulator_bulk_data supplies[WM8962_NUM_SUPPLIES];
74 struct notifier_block disable_nb[WM8962_NUM_SUPPLIES];
75
76 struct input_dev *beep;
77 struct work_struct beep_work;
78 int beep_rate;
79
80#ifdef CONFIG_GPIOLIB
81 struct gpio_chip gpio_chip;
82#endif
83
84 int irq;
85};
86
87/* We can't use the same notifier block for more than one supply and
88 * there's no way I can see to get from a callback to the caller
89 * except container_of().
90 */
91#define WM8962_REGULATOR_EVENT(n) \
92static int wm8962_regulator_event_##n(struct notifier_block *nb, \
93 unsigned long event, void *data) \
94{ \
95 struct wm8962_priv *wm8962 = container_of(nb, struct wm8962_priv, \
96 disable_nb[n]); \
97 if (event & REGULATOR_EVENT_DISABLE) { \
98 regcache_mark_dirty(wm8962->regmap); \
99 } \
100 return 0; \
101}
102
103WM8962_REGULATOR_EVENT(0)
104WM8962_REGULATOR_EVENT(1)
105WM8962_REGULATOR_EVENT(2)
106WM8962_REGULATOR_EVENT(3)
107WM8962_REGULATOR_EVENT(4)
108WM8962_REGULATOR_EVENT(5)
109WM8962_REGULATOR_EVENT(6)
110WM8962_REGULATOR_EVENT(7)
111
112static const struct reg_default wm8962_reg[] = {
113 { 0, 0x009F }, /* R0 - Left Input volume */
114 { 1, 0x049F }, /* R1 - Right Input volume */
115 { 2, 0x0000 }, /* R2 - HPOUTL volume */
116 { 3, 0x0000 }, /* R3 - HPOUTR volume */
117
118 { 5, 0x0018 }, /* R5 - ADC & DAC Control 1 */
119 { 6, 0x2008 }, /* R6 - ADC & DAC Control 2 */
120 { 7, 0x000A }, /* R7 - Audio Interface 0 */
121 { 8, 0x01E4 }, /* R8 - Clocking2 */
122 { 9, 0x0300 }, /* R9 - Audio Interface 1 */
123 { 10, 0x00C0 }, /* R10 - Left DAC volume */
124 { 11, 0x00C0 }, /* R11 - Right DAC volume */
125
126 { 14, 0x0040 }, /* R14 - Audio Interface 2 */
127 { 15, 0x6243 }, /* R15 - Software Reset */
128
129 { 17, 0x007B }, /* R17 - ALC1 */
130 { 18, 0x0000 }, /* R18 - ALC2 */
131 { 19, 0x1C32 }, /* R19 - ALC3 */
132 { 20, 0x3200 }, /* R20 - Noise Gate */
133 { 21, 0x00C0 }, /* R21 - Left ADC volume */
134 { 22, 0x00C0 }, /* R22 - Right ADC volume */
135 { 23, 0x0160 }, /* R23 - Additional control(1) */
136 { 24, 0x0000 }, /* R24 - Additional control(2) */
137 { 25, 0x0000 }, /* R25 - Pwr Mgmt (1) */
138 { 26, 0x0000 }, /* R26 - Pwr Mgmt (2) */
139 { 27, 0x0010 }, /* R27 - Additional Control (3) */
140 { 28, 0x0000 }, /* R28 - Anti-pop */
141
142 { 30, 0x005E }, /* R30 - Clocking 3 */
143 { 31, 0x0000 }, /* R31 - Input mixer control (1) */
144 { 32, 0x0145 }, /* R32 - Left input mixer volume */
145 { 33, 0x0145 }, /* R33 - Right input mixer volume */
146 { 34, 0x0009 }, /* R34 - Input mixer control (2) */
147 { 35, 0x0003 }, /* R35 - Input bias control */
148 { 37, 0x0008 }, /* R37 - Left input PGA control */
149 { 38, 0x0008 }, /* R38 - Right input PGA control */
150
151 { 40, 0x0000 }, /* R40 - SPKOUTL volume */
152 { 41, 0x0000 }, /* R41 - SPKOUTR volume */
153
154 { 49, 0x0010 }, /* R49 - Class D Control 1 */
155 { 51, 0x0003 }, /* R51 - Class D Control 2 */
156
157 { 56, 0x0506 }, /* R56 - Clocking 4 */
158 { 57, 0x0000 }, /* R57 - DAC DSP Mixing (1) */
159 { 58, 0x0000 }, /* R58 - DAC DSP Mixing (2) */
160
161 { 60, 0x0300 }, /* R60 - DC Servo 0 */
162 { 61, 0x0300 }, /* R61 - DC Servo 1 */
163
164 { 64, 0x0810 }, /* R64 - DC Servo 4 */
165
166 { 68, 0x001B }, /* R68 - Analogue PGA Bias */
167 { 69, 0x0000 }, /* R69 - Analogue HP 0 */
168
169 { 71, 0x01FB }, /* R71 - Analogue HP 2 */
170 { 72, 0x0000 }, /* R72 - Charge Pump 1 */
171
172 { 82, 0x0004 }, /* R82 - Charge Pump B */
173
174 { 87, 0x0000 }, /* R87 - Write Sequencer Control 1 */
175
176 { 90, 0x0000 }, /* R90 - Write Sequencer Control 2 */
177
178 { 93, 0x0000 }, /* R93 - Write Sequencer Control 3 */
179 { 94, 0x0000 }, /* R94 - Control Interface */
180
181 { 99, 0x0000 }, /* R99 - Mixer Enables */
182 { 100, 0x0000 }, /* R100 - Headphone Mixer (1) */
183 { 101, 0x0000 }, /* R101 - Headphone Mixer (2) */
184 { 102, 0x013F }, /* R102 - Headphone Mixer (3) */
185 { 103, 0x013F }, /* R103 - Headphone Mixer (4) */
186
187 { 105, 0x0000 }, /* R105 - Speaker Mixer (1) */
188 { 106, 0x0000 }, /* R106 - Speaker Mixer (2) */
189 { 107, 0x013F }, /* R107 - Speaker Mixer (3) */
190 { 108, 0x013F }, /* R108 - Speaker Mixer (4) */
191 { 109, 0x0003 }, /* R109 - Speaker Mixer (5) */
192 { 110, 0x0002 }, /* R110 - Beep Generator (1) */
193
194 { 115, 0x0006 }, /* R115 - Oscillator Trim (3) */
195 { 116, 0x0026 }, /* R116 - Oscillator Trim (4) */
196
197 { 119, 0x0000 }, /* R119 - Oscillator Trim (7) */
198
199 { 124, 0x0011 }, /* R124 - Analogue Clocking1 */
200 { 125, 0x004B }, /* R125 - Analogue Clocking2 */
201 { 126, 0x000D }, /* R126 - Analogue Clocking3 */
202 { 127, 0x0000 }, /* R127 - PLL Software Reset */
203
204 { 131, 0x0000 }, /* R131 - PLL 4 */
205
206 { 136, 0x0067 }, /* R136 - PLL 9 */
207 { 137, 0x001C }, /* R137 - PLL 10 */
208 { 138, 0x0071 }, /* R138 - PLL 11 */
209 { 139, 0x00C7 }, /* R139 - PLL 12 */
210 { 140, 0x0067 }, /* R140 - PLL 13 */
211 { 141, 0x0048 }, /* R141 - PLL 14 */
212 { 142, 0x0022 }, /* R142 - PLL 15 */
213 { 143, 0x0097 }, /* R143 - PLL 16 */
214
215 { 155, 0x000C }, /* R155 - FLL Control (1) */
216 { 156, 0x0039 }, /* R156 - FLL Control (2) */
217 { 157, 0x0180 }, /* R157 - FLL Control (3) */
218
219 { 159, 0x0032 }, /* R159 - FLL Control (5) */
220 { 160, 0x0018 }, /* R160 - FLL Control (6) */
221 { 161, 0x007D }, /* R161 - FLL Control (7) */
222 { 162, 0x0008 }, /* R162 - FLL Control (8) */
223
224 { 252, 0x0005 }, /* R252 - General test 1 */
225
226 { 256, 0x0000 }, /* R256 - DF1 */
227 { 257, 0x0000 }, /* R257 - DF2 */
228 { 258, 0x0000 }, /* R258 - DF3 */
229 { 259, 0x0000 }, /* R259 - DF4 */
230 { 260, 0x0000 }, /* R260 - DF5 */
231 { 261, 0x0000 }, /* R261 - DF6 */
232 { 262, 0x0000 }, /* R262 - DF7 */
233
234 { 264, 0x0000 }, /* R264 - LHPF1 */
235 { 265, 0x0000 }, /* R265 - LHPF2 */
236
237 { 268, 0x0000 }, /* R268 - THREED1 */
238 { 269, 0x0000 }, /* R269 - THREED2 */
239 { 270, 0x0000 }, /* R270 - THREED3 */
240 { 271, 0x0000 }, /* R271 - THREED4 */
241
242 { 276, 0x000C }, /* R276 - DRC 1 */
243 { 277, 0x0925 }, /* R277 - DRC 2 */
244 { 278, 0x0000 }, /* R278 - DRC 3 */
245 { 279, 0x0000 }, /* R279 - DRC 4 */
246 { 280, 0x0000 }, /* R280 - DRC 5 */
247
248 { 285, 0x0000 }, /* R285 - Tloopback */
249
250 { 335, 0x0004 }, /* R335 - EQ1 */
251 { 336, 0x6318 }, /* R336 - EQ2 */
252 { 337, 0x6300 }, /* R337 - EQ3 */
253 { 338, 0x0FCA }, /* R338 - EQ4 */
254 { 339, 0x0400 }, /* R339 - EQ5 */
255 { 340, 0x00D8 }, /* R340 - EQ6 */
256 { 341, 0x1EB5 }, /* R341 - EQ7 */
257 { 342, 0xF145 }, /* R342 - EQ8 */
258 { 343, 0x0B75 }, /* R343 - EQ9 */
259 { 344, 0x01C5 }, /* R344 - EQ10 */
260 { 345, 0x1C58 }, /* R345 - EQ11 */
261 { 346, 0xF373 }, /* R346 - EQ12 */
262 { 347, 0x0A54 }, /* R347 - EQ13 */
263 { 348, 0x0558 }, /* R348 - EQ14 */
264 { 349, 0x168E }, /* R349 - EQ15 */
265 { 350, 0xF829 }, /* R350 - EQ16 */
266 { 351, 0x07AD }, /* R351 - EQ17 */
267 { 352, 0x1103 }, /* R352 - EQ18 */
268 { 353, 0x0564 }, /* R353 - EQ19 */
269 { 354, 0x0559 }, /* R354 - EQ20 */
270 { 355, 0x4000 }, /* R355 - EQ21 */
271 { 356, 0x6318 }, /* R356 - EQ22 */
272 { 357, 0x6300 }, /* R357 - EQ23 */
273 { 358, 0x0FCA }, /* R358 - EQ24 */
274 { 359, 0x0400 }, /* R359 - EQ25 */
275 { 360, 0x00D8 }, /* R360 - EQ26 */
276 { 361, 0x1EB5 }, /* R361 - EQ27 */
277 { 362, 0xF145 }, /* R362 - EQ28 */
278 { 363, 0x0B75 }, /* R363 - EQ29 */
279 { 364, 0x01C5 }, /* R364 - EQ30 */
280 { 365, 0x1C58 }, /* R365 - EQ31 */
281 { 366, 0xF373 }, /* R366 - EQ32 */
282 { 367, 0x0A54 }, /* R367 - EQ33 */
283 { 368, 0x0558 }, /* R368 - EQ34 */
284 { 369, 0x168E }, /* R369 - EQ35 */
285 { 370, 0xF829 }, /* R370 - EQ36 */
286 { 371, 0x07AD }, /* R371 - EQ37 */
287 { 372, 0x1103 }, /* R372 - EQ38 */
288 { 373, 0x0564 }, /* R373 - EQ39 */
289 { 374, 0x0559 }, /* R374 - EQ40 */
290 { 375, 0x4000 }, /* R375 - EQ41 */
291
292 { 513, 0x0000 }, /* R513 - GPIO 2 */
293 { 514, 0x0000 }, /* R514 - GPIO 3 */
294
295 { 516, 0x8100 }, /* R516 - GPIO 5 */
296 { 517, 0x8100 }, /* R517 - GPIO 6 */
297
298 { 568, 0x0030 }, /* R568 - Interrupt Status 1 Mask */
299 { 569, 0xFFED }, /* R569 - Interrupt Status 2 Mask */
300
301 { 576, 0x0000 }, /* R576 - Interrupt Control */
302
303 { 584, 0x002D }, /* R584 - IRQ Debounce */
304
305 { 586, 0x0000 }, /* R586 - MICINT Source Pol */
306
307 { 768, 0x1C00 }, /* R768 - DSP2 Power Management */
308
309 { 8192, 0x0000 }, /* R8192 - DSP2 Instruction RAM 0 */
310
311 { 9216, 0x0030 }, /* R9216 - DSP2 Address RAM 2 */
312 { 9217, 0x0000 }, /* R9217 - DSP2 Address RAM 1 */
313 { 9218, 0x0000 }, /* R9218 - DSP2 Address RAM 0 */
314
315 { 12288, 0x0000 }, /* R12288 - DSP2 Data1 RAM 1 */
316 { 12289, 0x0000 }, /* R12289 - DSP2 Data1 RAM 0 */
317
318 { 13312, 0x0000 }, /* R13312 - DSP2 Data2 RAM 1 */
319 { 13313, 0x0000 }, /* R13313 - DSP2 Data2 RAM 0 */
320
321 { 14336, 0x0000 }, /* R14336 - DSP2 Data3 RAM 1 */
322 { 14337, 0x0000 }, /* R14337 - DSP2 Data3 RAM 0 */
323
324 { 15360, 0x000A }, /* R15360 - DSP2 Coeff RAM 0 */
325
326 { 16384, 0x0000 }, /* R16384 - RETUNEADC_SHARED_COEFF_1 */
327 { 16385, 0x0000 }, /* R16385 - RETUNEADC_SHARED_COEFF_0 */
328 { 16386, 0x0000 }, /* R16386 - RETUNEDAC_SHARED_COEFF_1 */
329 { 16387, 0x0000 }, /* R16387 - RETUNEDAC_SHARED_COEFF_0 */
330 { 16388, 0x0000 }, /* R16388 - SOUNDSTAGE_ENABLES_1 */
331 { 16389, 0x0000 }, /* R16389 - SOUNDSTAGE_ENABLES_0 */
332
333 { 16896, 0x0002 }, /* R16896 - HDBASS_AI_1 */
334 { 16897, 0xBD12 }, /* R16897 - HDBASS_AI_0 */
335 { 16898, 0x007C }, /* R16898 - HDBASS_AR_1 */
336 { 16899, 0x586C }, /* R16899 - HDBASS_AR_0 */
337 { 16900, 0x0053 }, /* R16900 - HDBASS_B_1 */
338 { 16901, 0x8121 }, /* R16901 - HDBASS_B_0 */
339 { 16902, 0x003F }, /* R16902 - HDBASS_K_1 */
340 { 16903, 0x8BD8 }, /* R16903 - HDBASS_K_0 */
341 { 16904, 0x0032 }, /* R16904 - HDBASS_N1_1 */
342 { 16905, 0xF52D }, /* R16905 - HDBASS_N1_0 */
343 { 16906, 0x0065 }, /* R16906 - HDBASS_N2_1 */
344 { 16907, 0xAC8C }, /* R16907 - HDBASS_N2_0 */
345 { 16908, 0x006B }, /* R16908 - HDBASS_N3_1 */
346 { 16909, 0xE087 }, /* R16909 - HDBASS_N3_0 */
347 { 16910, 0x0072 }, /* R16910 - HDBASS_N4_1 */
348 { 16911, 0x1483 }, /* R16911 - HDBASS_N4_0 */
349 { 16912, 0x0072 }, /* R16912 - HDBASS_N5_1 */
350 { 16913, 0x1483 }, /* R16913 - HDBASS_N5_0 */
351 { 16914, 0x0043 }, /* R16914 - HDBASS_X1_1 */
352 { 16915, 0x3525 }, /* R16915 - HDBASS_X1_0 */
353 { 16916, 0x0006 }, /* R16916 - HDBASS_X2_1 */
354 { 16917, 0x6A4A }, /* R16917 - HDBASS_X2_0 */
355 { 16918, 0x0043 }, /* R16918 - HDBASS_X3_1 */
356 { 16919, 0x6079 }, /* R16919 - HDBASS_X3_0 */
357 { 16920, 0x0008 }, /* R16920 - HDBASS_ATK_1 */
358 { 16921, 0x0000 }, /* R16921 - HDBASS_ATK_0 */
359 { 16922, 0x0001 }, /* R16922 - HDBASS_DCY_1 */
360 { 16923, 0x0000 }, /* R16923 - HDBASS_DCY_0 */
361 { 16924, 0x0059 }, /* R16924 - HDBASS_PG_1 */
362 { 16925, 0x999A }, /* R16925 - HDBASS_PG_0 */
363
364 { 17408, 0x0083 }, /* R17408 - HPF_C_1 */
365 { 17409, 0x98AD }, /* R17409 - HPF_C_0 */
366
367 { 17920, 0x007F }, /* R17920 - ADCL_RETUNE_C1_1 */
368 { 17921, 0xFFFF }, /* R17921 - ADCL_RETUNE_C1_0 */
369 { 17922, 0x0000 }, /* R17922 - ADCL_RETUNE_C2_1 */
370 { 17923, 0x0000 }, /* R17923 - ADCL_RETUNE_C2_0 */
371 { 17924, 0x0000 }, /* R17924 - ADCL_RETUNE_C3_1 */
372 { 17925, 0x0000 }, /* R17925 - ADCL_RETUNE_C3_0 */
373 { 17926, 0x0000 }, /* R17926 - ADCL_RETUNE_C4_1 */
374 { 17927, 0x0000 }, /* R17927 - ADCL_RETUNE_C4_0 */
375 { 17928, 0x0000 }, /* R17928 - ADCL_RETUNE_C5_1 */
376 { 17929, 0x0000 }, /* R17929 - ADCL_RETUNE_C5_0 */
377 { 17930, 0x0000 }, /* R17930 - ADCL_RETUNE_C6_1 */
378 { 17931, 0x0000 }, /* R17931 - ADCL_RETUNE_C6_0 */
379 { 17932, 0x0000 }, /* R17932 - ADCL_RETUNE_C7_1 */
380 { 17933, 0x0000 }, /* R17933 - ADCL_RETUNE_C7_0 */
381 { 17934, 0x0000 }, /* R17934 - ADCL_RETUNE_C8_1 */
382 { 17935, 0x0000 }, /* R17935 - ADCL_RETUNE_C8_0 */
383 { 17936, 0x0000 }, /* R17936 - ADCL_RETUNE_C9_1 */
384 { 17937, 0x0000 }, /* R17937 - ADCL_RETUNE_C9_0 */
385 { 17938, 0x0000 }, /* R17938 - ADCL_RETUNE_C10_1 */
386 { 17939, 0x0000 }, /* R17939 - ADCL_RETUNE_C10_0 */
387 { 17940, 0x0000 }, /* R17940 - ADCL_RETUNE_C11_1 */
388 { 17941, 0x0000 }, /* R17941 - ADCL_RETUNE_C11_0 */
389 { 17942, 0x0000 }, /* R17942 - ADCL_RETUNE_C12_1 */
390 { 17943, 0x0000 }, /* R17943 - ADCL_RETUNE_C12_0 */
391 { 17944, 0x0000 }, /* R17944 - ADCL_RETUNE_C13_1 */
392 { 17945, 0x0000 }, /* R17945 - ADCL_RETUNE_C13_0 */
393 { 17946, 0x0000 }, /* R17946 - ADCL_RETUNE_C14_1 */
394 { 17947, 0x0000 }, /* R17947 - ADCL_RETUNE_C14_0 */
395 { 17948, 0x0000 }, /* R17948 - ADCL_RETUNE_C15_1 */
396 { 17949, 0x0000 }, /* R17949 - ADCL_RETUNE_C15_0 */
397 { 17950, 0x0000 }, /* R17950 - ADCL_RETUNE_C16_1 */
398 { 17951, 0x0000 }, /* R17951 - ADCL_RETUNE_C16_0 */
399 { 17952, 0x0000 }, /* R17952 - ADCL_RETUNE_C17_1 */
400 { 17953, 0x0000 }, /* R17953 - ADCL_RETUNE_C17_0 */
401 { 17954, 0x0000 }, /* R17954 - ADCL_RETUNE_C18_1 */
402 { 17955, 0x0000 }, /* R17955 - ADCL_RETUNE_C18_0 */
403 { 17956, 0x0000 }, /* R17956 - ADCL_RETUNE_C19_1 */
404 { 17957, 0x0000 }, /* R17957 - ADCL_RETUNE_C19_0 */
405 { 17958, 0x0000 }, /* R17958 - ADCL_RETUNE_C20_1 */
406 { 17959, 0x0000 }, /* R17959 - ADCL_RETUNE_C20_0 */
407 { 17960, 0x0000 }, /* R17960 - ADCL_RETUNE_C21_1 */
408 { 17961, 0x0000 }, /* R17961 - ADCL_RETUNE_C21_0 */
409 { 17962, 0x0000 }, /* R17962 - ADCL_RETUNE_C22_1 */
410 { 17963, 0x0000 }, /* R17963 - ADCL_RETUNE_C22_0 */
411 { 17964, 0x0000 }, /* R17964 - ADCL_RETUNE_C23_1 */
412 { 17965, 0x0000 }, /* R17965 - ADCL_RETUNE_C23_0 */
413 { 17966, 0x0000 }, /* R17966 - ADCL_RETUNE_C24_1 */
414 { 17967, 0x0000 }, /* R17967 - ADCL_RETUNE_C24_0 */
415 { 17968, 0x0000 }, /* R17968 - ADCL_RETUNE_C25_1 */
416 { 17969, 0x0000 }, /* R17969 - ADCL_RETUNE_C25_0 */
417 { 17970, 0x0000 }, /* R17970 - ADCL_RETUNE_C26_1 */
418 { 17971, 0x0000 }, /* R17971 - ADCL_RETUNE_C26_0 */
419 { 17972, 0x0000 }, /* R17972 - ADCL_RETUNE_C27_1 */
420 { 17973, 0x0000 }, /* R17973 - ADCL_RETUNE_C27_0 */
421 { 17974, 0x0000 }, /* R17974 - ADCL_RETUNE_C28_1 */
422 { 17975, 0x0000 }, /* R17975 - ADCL_RETUNE_C28_0 */
423 { 17976, 0x0000 }, /* R17976 - ADCL_RETUNE_C29_1 */
424 { 17977, 0x0000 }, /* R17977 - ADCL_RETUNE_C29_0 */
425 { 17978, 0x0000 }, /* R17978 - ADCL_RETUNE_C30_1 */
426 { 17979, 0x0000 }, /* R17979 - ADCL_RETUNE_C30_0 */
427 { 17980, 0x0000 }, /* R17980 - ADCL_RETUNE_C31_1 */
428 { 17981, 0x0000 }, /* R17981 - ADCL_RETUNE_C31_0 */
429 { 17982, 0x0000 }, /* R17982 - ADCL_RETUNE_C32_1 */
430 { 17983, 0x0000 }, /* R17983 - ADCL_RETUNE_C32_0 */
431
432 { 18432, 0x0020 }, /* R18432 - RETUNEADC_PG2_1 */
433 { 18433, 0x0000 }, /* R18433 - RETUNEADC_PG2_0 */
434 { 18434, 0x0040 }, /* R18434 - RETUNEADC_PG_1 */
435 { 18435, 0x0000 }, /* R18435 - RETUNEADC_PG_0 */
436
437 { 18944, 0x007F }, /* R18944 - ADCR_RETUNE_C1_1 */
438 { 18945, 0xFFFF }, /* R18945 - ADCR_RETUNE_C1_0 */
439 { 18946, 0x0000 }, /* R18946 - ADCR_RETUNE_C2_1 */
440 { 18947, 0x0000 }, /* R18947 - ADCR_RETUNE_C2_0 */
441 { 18948, 0x0000 }, /* R18948 - ADCR_RETUNE_C3_1 */
442 { 18949, 0x0000 }, /* R18949 - ADCR_RETUNE_C3_0 */
443 { 18950, 0x0000 }, /* R18950 - ADCR_RETUNE_C4_1 */
444 { 18951, 0x0000 }, /* R18951 - ADCR_RETUNE_C4_0 */
445 { 18952, 0x0000 }, /* R18952 - ADCR_RETUNE_C5_1 */
446 { 18953, 0x0000 }, /* R18953 - ADCR_RETUNE_C5_0 */
447 { 18954, 0x0000 }, /* R18954 - ADCR_RETUNE_C6_1 */
448 { 18955, 0x0000 }, /* R18955 - ADCR_RETUNE_C6_0 */
449 { 18956, 0x0000 }, /* R18956 - ADCR_RETUNE_C7_1 */
450 { 18957, 0x0000 }, /* R18957 - ADCR_RETUNE_C7_0 */
451 { 18958, 0x0000 }, /* R18958 - ADCR_RETUNE_C8_1 */
452 { 18959, 0x0000 }, /* R18959 - ADCR_RETUNE_C8_0 */
453 { 18960, 0x0000 }, /* R18960 - ADCR_RETUNE_C9_1 */
454 { 18961, 0x0000 }, /* R18961 - ADCR_RETUNE_C9_0 */
455 { 18962, 0x0000 }, /* R18962 - ADCR_RETUNE_C10_1 */
456 { 18963, 0x0000 }, /* R18963 - ADCR_RETUNE_C10_0 */
457 { 18964, 0x0000 }, /* R18964 - ADCR_RETUNE_C11_1 */
458 { 18965, 0x0000 }, /* R18965 - ADCR_RETUNE_C11_0 */
459 { 18966, 0x0000 }, /* R18966 - ADCR_RETUNE_C12_1 */
460 { 18967, 0x0000 }, /* R18967 - ADCR_RETUNE_C12_0 */
461 { 18968, 0x0000 }, /* R18968 - ADCR_RETUNE_C13_1 */
462 { 18969, 0x0000 }, /* R18969 - ADCR_RETUNE_C13_0 */
463 { 18970, 0x0000 }, /* R18970 - ADCR_RETUNE_C14_1 */
464 { 18971, 0x0000 }, /* R18971 - ADCR_RETUNE_C14_0 */
465 { 18972, 0x0000 }, /* R18972 - ADCR_RETUNE_C15_1 */
466 { 18973, 0x0000 }, /* R18973 - ADCR_RETUNE_C15_0 */
467 { 18974, 0x0000 }, /* R18974 - ADCR_RETUNE_C16_1 */
468 { 18975, 0x0000 }, /* R18975 - ADCR_RETUNE_C16_0 */
469 { 18976, 0x0000 }, /* R18976 - ADCR_RETUNE_C17_1 */
470 { 18977, 0x0000 }, /* R18977 - ADCR_RETUNE_C17_0 */
471 { 18978, 0x0000 }, /* R18978 - ADCR_RETUNE_C18_1 */
472 { 18979, 0x0000 }, /* R18979 - ADCR_RETUNE_C18_0 */
473 { 18980, 0x0000 }, /* R18980 - ADCR_RETUNE_C19_1 */
474 { 18981, 0x0000 }, /* R18981 - ADCR_RETUNE_C19_0 */
475 { 18982, 0x0000 }, /* R18982 - ADCR_RETUNE_C20_1 */
476 { 18983, 0x0000 }, /* R18983 - ADCR_RETUNE_C20_0 */
477 { 18984, 0x0000 }, /* R18984 - ADCR_RETUNE_C21_1 */
478 { 18985, 0x0000 }, /* R18985 - ADCR_RETUNE_C21_0 */
479 { 18986, 0x0000 }, /* R18986 - ADCR_RETUNE_C22_1 */
480 { 18987, 0x0000 }, /* R18987 - ADCR_RETUNE_C22_0 */
481 { 18988, 0x0000 }, /* R18988 - ADCR_RETUNE_C23_1 */
482 { 18989, 0x0000 }, /* R18989 - ADCR_RETUNE_C23_0 */
483 { 18990, 0x0000 }, /* R18990 - ADCR_RETUNE_C24_1 */
484 { 18991, 0x0000 }, /* R18991 - ADCR_RETUNE_C24_0 */
485 { 18992, 0x0000 }, /* R18992 - ADCR_RETUNE_C25_1 */
486 { 18993, 0x0000 }, /* R18993 - ADCR_RETUNE_C25_0 */
487 { 18994, 0x0000 }, /* R18994 - ADCR_RETUNE_C26_1 */
488 { 18995, 0x0000 }, /* R18995 - ADCR_RETUNE_C26_0 */
489 { 18996, 0x0000 }, /* R18996 - ADCR_RETUNE_C27_1 */
490 { 18997, 0x0000 }, /* R18997 - ADCR_RETUNE_C27_0 */
491 { 18998, 0x0000 }, /* R18998 - ADCR_RETUNE_C28_1 */
492 { 18999, 0x0000 }, /* R18999 - ADCR_RETUNE_C28_0 */
493 { 19000, 0x0000 }, /* R19000 - ADCR_RETUNE_C29_1 */
494 { 19001, 0x0000 }, /* R19001 - ADCR_RETUNE_C29_0 */
495 { 19002, 0x0000 }, /* R19002 - ADCR_RETUNE_C30_1 */
496 { 19003, 0x0000 }, /* R19003 - ADCR_RETUNE_C30_0 */
497 { 19004, 0x0000 }, /* R19004 - ADCR_RETUNE_C31_1 */
498 { 19005, 0x0000 }, /* R19005 - ADCR_RETUNE_C31_0 */
499 { 19006, 0x0000 }, /* R19006 - ADCR_RETUNE_C32_1 */
500 { 19007, 0x0000 }, /* R19007 - ADCR_RETUNE_C32_0 */
501
502 { 19456, 0x007F }, /* R19456 - DACL_RETUNE_C1_1 */
503 { 19457, 0xFFFF }, /* R19457 - DACL_RETUNE_C1_0 */
504 { 19458, 0x0000 }, /* R19458 - DACL_RETUNE_C2_1 */
505 { 19459, 0x0000 }, /* R19459 - DACL_RETUNE_C2_0 */
506 { 19460, 0x0000 }, /* R19460 - DACL_RETUNE_C3_1 */
507 { 19461, 0x0000 }, /* R19461 - DACL_RETUNE_C3_0 */
508 { 19462, 0x0000 }, /* R19462 - DACL_RETUNE_C4_1 */
509 { 19463, 0x0000 }, /* R19463 - DACL_RETUNE_C4_0 */
510 { 19464, 0x0000 }, /* R19464 - DACL_RETUNE_C5_1 */
511 { 19465, 0x0000 }, /* R19465 - DACL_RETUNE_C5_0 */
512 { 19466, 0x0000 }, /* R19466 - DACL_RETUNE_C6_1 */
513 { 19467, 0x0000 }, /* R19467 - DACL_RETUNE_C6_0 */
514 { 19468, 0x0000 }, /* R19468 - DACL_RETUNE_C7_1 */
515 { 19469, 0x0000 }, /* R19469 - DACL_RETUNE_C7_0 */
516 { 19470, 0x0000 }, /* R19470 - DACL_RETUNE_C8_1 */
517 { 19471, 0x0000 }, /* R19471 - DACL_RETUNE_C8_0 */
518 { 19472, 0x0000 }, /* R19472 - DACL_RETUNE_C9_1 */
519 { 19473, 0x0000 }, /* R19473 - DACL_RETUNE_C9_0 */
520 { 19474, 0x0000 }, /* R19474 - DACL_RETUNE_C10_1 */
521 { 19475, 0x0000 }, /* R19475 - DACL_RETUNE_C10_0 */
522 { 19476, 0x0000 }, /* R19476 - DACL_RETUNE_C11_1 */
523 { 19477, 0x0000 }, /* R19477 - DACL_RETUNE_C11_0 */
524 { 19478, 0x0000 }, /* R19478 - DACL_RETUNE_C12_1 */
525 { 19479, 0x0000 }, /* R19479 - DACL_RETUNE_C12_0 */
526 { 19480, 0x0000 }, /* R19480 - DACL_RETUNE_C13_1 */
527 { 19481, 0x0000 }, /* R19481 - DACL_RETUNE_C13_0 */
528 { 19482, 0x0000 }, /* R19482 - DACL_RETUNE_C14_1 */
529 { 19483, 0x0000 }, /* R19483 - DACL_RETUNE_C14_0 */
530 { 19484, 0x0000 }, /* R19484 - DACL_RETUNE_C15_1 */
531 { 19485, 0x0000 }, /* R19485 - DACL_RETUNE_C15_0 */
532 { 19486, 0x0000 }, /* R19486 - DACL_RETUNE_C16_1 */
533 { 19487, 0x0000 }, /* R19487 - DACL_RETUNE_C16_0 */
534 { 19488, 0x0000 }, /* R19488 - DACL_RETUNE_C17_1 */
535 { 19489, 0x0000 }, /* R19489 - DACL_RETUNE_C17_0 */
536 { 19490, 0x0000 }, /* R19490 - DACL_RETUNE_C18_1 */
537 { 19491, 0x0000 }, /* R19491 - DACL_RETUNE_C18_0 */
538 { 19492, 0x0000 }, /* R19492 - DACL_RETUNE_C19_1 */
539 { 19493, 0x0000 }, /* R19493 - DACL_RETUNE_C19_0 */
540 { 19494, 0x0000 }, /* R19494 - DACL_RETUNE_C20_1 */
541 { 19495, 0x0000 }, /* R19495 - DACL_RETUNE_C20_0 */
542 { 19496, 0x0000 }, /* R19496 - DACL_RETUNE_C21_1 */
543 { 19497, 0x0000 }, /* R19497 - DACL_RETUNE_C21_0 */
544 { 19498, 0x0000 }, /* R19498 - DACL_RETUNE_C22_1 */
545 { 19499, 0x0000 }, /* R19499 - DACL_RETUNE_C22_0 */
546 { 19500, 0x0000 }, /* R19500 - DACL_RETUNE_C23_1 */
547 { 19501, 0x0000 }, /* R19501 - DACL_RETUNE_C23_0 */
548 { 19502, 0x0000 }, /* R19502 - DACL_RETUNE_C24_1 */
549 { 19503, 0x0000 }, /* R19503 - DACL_RETUNE_C24_0 */
550 { 19504, 0x0000 }, /* R19504 - DACL_RETUNE_C25_1 */
551 { 19505, 0x0000 }, /* R19505 - DACL_RETUNE_C25_0 */
552 { 19506, 0x0000 }, /* R19506 - DACL_RETUNE_C26_1 */
553 { 19507, 0x0000 }, /* R19507 - DACL_RETUNE_C26_0 */
554 { 19508, 0x0000 }, /* R19508 - DACL_RETUNE_C27_1 */
555 { 19509, 0x0000 }, /* R19509 - DACL_RETUNE_C27_0 */
556 { 19510, 0x0000 }, /* R19510 - DACL_RETUNE_C28_1 */
557 { 19511, 0x0000 }, /* R19511 - DACL_RETUNE_C28_0 */
558 { 19512, 0x0000 }, /* R19512 - DACL_RETUNE_C29_1 */
559 { 19513, 0x0000 }, /* R19513 - DACL_RETUNE_C29_0 */
560 { 19514, 0x0000 }, /* R19514 - DACL_RETUNE_C30_1 */
561 { 19515, 0x0000 }, /* R19515 - DACL_RETUNE_C30_0 */
562 { 19516, 0x0000 }, /* R19516 - DACL_RETUNE_C31_1 */
563 { 19517, 0x0000 }, /* R19517 - DACL_RETUNE_C31_0 */
564 { 19518, 0x0000 }, /* R19518 - DACL_RETUNE_C32_1 */
565 { 19519, 0x0000 }, /* R19519 - DACL_RETUNE_C32_0 */
566
567 { 19968, 0x0020 }, /* R19968 - RETUNEDAC_PG2_1 */
568 { 19969, 0x0000 }, /* R19969 - RETUNEDAC_PG2_0 */
569 { 19970, 0x0040 }, /* R19970 - RETUNEDAC_PG_1 */
570 { 19971, 0x0000 }, /* R19971 - RETUNEDAC_PG_0 */
571
572 { 20480, 0x007F }, /* R20480 - DACR_RETUNE_C1_1 */
573 { 20481, 0xFFFF }, /* R20481 - DACR_RETUNE_C1_0 */
574 { 20482, 0x0000 }, /* R20482 - DACR_RETUNE_C2_1 */
575 { 20483, 0x0000 }, /* R20483 - DACR_RETUNE_C2_0 */
576 { 20484, 0x0000 }, /* R20484 - DACR_RETUNE_C3_1 */
577 { 20485, 0x0000 }, /* R20485 - DACR_RETUNE_C3_0 */
578 { 20486, 0x0000 }, /* R20486 - DACR_RETUNE_C4_1 */
579 { 20487, 0x0000 }, /* R20487 - DACR_RETUNE_C4_0 */
580 { 20488, 0x0000 }, /* R20488 - DACR_RETUNE_C5_1 */
581 { 20489, 0x0000 }, /* R20489 - DACR_RETUNE_C5_0 */
582 { 20490, 0x0000 }, /* R20490 - DACR_RETUNE_C6_1 */
583 { 20491, 0x0000 }, /* R20491 - DACR_RETUNE_C6_0 */
584 { 20492, 0x0000 }, /* R20492 - DACR_RETUNE_C7_1 */
585 { 20493, 0x0000 }, /* R20493 - DACR_RETUNE_C7_0 */
586 { 20494, 0x0000 }, /* R20494 - DACR_RETUNE_C8_1 */
587 { 20495, 0x0000 }, /* R20495 - DACR_RETUNE_C8_0 */
588 { 20496, 0x0000 }, /* R20496 - DACR_RETUNE_C9_1 */
589 { 20497, 0x0000 }, /* R20497 - DACR_RETUNE_C9_0 */
590 { 20498, 0x0000 }, /* R20498 - DACR_RETUNE_C10_1 */
591 { 20499, 0x0000 }, /* R20499 - DACR_RETUNE_C10_0 */
592 { 20500, 0x0000 }, /* R20500 - DACR_RETUNE_C11_1 */
593 { 20501, 0x0000 }, /* R20501 - DACR_RETUNE_C11_0 */
594 { 20502, 0x0000 }, /* R20502 - DACR_RETUNE_C12_1 */
595 { 20503, 0x0000 }, /* R20503 - DACR_RETUNE_C12_0 */
596 { 20504, 0x0000 }, /* R20504 - DACR_RETUNE_C13_1 */
597 { 20505, 0x0000 }, /* R20505 - DACR_RETUNE_C13_0 */
598 { 20506, 0x0000 }, /* R20506 - DACR_RETUNE_C14_1 */
599 { 20507, 0x0000 }, /* R20507 - DACR_RETUNE_C14_0 */
600 { 20508, 0x0000 }, /* R20508 - DACR_RETUNE_C15_1 */
601 { 20509, 0x0000 }, /* R20509 - DACR_RETUNE_C15_0 */
602 { 20510, 0x0000 }, /* R20510 - DACR_RETUNE_C16_1 */
603 { 20511, 0x0000 }, /* R20511 - DACR_RETUNE_C16_0 */
604 { 20512, 0x0000 }, /* R20512 - DACR_RETUNE_C17_1 */
605 { 20513, 0x0000 }, /* R20513 - DACR_RETUNE_C17_0 */
606 { 20514, 0x0000 }, /* R20514 - DACR_RETUNE_C18_1 */
607 { 20515, 0x0000 }, /* R20515 - DACR_RETUNE_C18_0 */
608 { 20516, 0x0000 }, /* R20516 - DACR_RETUNE_C19_1 */
609 { 20517, 0x0000 }, /* R20517 - DACR_RETUNE_C19_0 */
610 { 20518, 0x0000 }, /* R20518 - DACR_RETUNE_C20_1 */
611 { 20519, 0x0000 }, /* R20519 - DACR_RETUNE_C20_0 */
612 { 20520, 0x0000 }, /* R20520 - DACR_RETUNE_C21_1 */
613 { 20521, 0x0000 }, /* R20521 - DACR_RETUNE_C21_0 */
614 { 20522, 0x0000 }, /* R20522 - DACR_RETUNE_C22_1 */
615 { 20523, 0x0000 }, /* R20523 - DACR_RETUNE_C22_0 */
616 { 20524, 0x0000 }, /* R20524 - DACR_RETUNE_C23_1 */
617 { 20525, 0x0000 }, /* R20525 - DACR_RETUNE_C23_0 */
618 { 20526, 0x0000 }, /* R20526 - DACR_RETUNE_C24_1 */
619 { 20527, 0x0000 }, /* R20527 - DACR_RETUNE_C24_0 */
620 { 20528, 0x0000 }, /* R20528 - DACR_RETUNE_C25_1 */
621 { 20529, 0x0000 }, /* R20529 - DACR_RETUNE_C25_0 */
622 { 20530, 0x0000 }, /* R20530 - DACR_RETUNE_C26_1 */
623 { 20531, 0x0000 }, /* R20531 - DACR_RETUNE_C26_0 */
624 { 20532, 0x0000 }, /* R20532 - DACR_RETUNE_C27_1 */
625 { 20533, 0x0000 }, /* R20533 - DACR_RETUNE_C27_0 */
626 { 20534, 0x0000 }, /* R20534 - DACR_RETUNE_C28_1 */
627 { 20535, 0x0000 }, /* R20535 - DACR_RETUNE_C28_0 */
628 { 20536, 0x0000 }, /* R20536 - DACR_RETUNE_C29_1 */
629 { 20537, 0x0000 }, /* R20537 - DACR_RETUNE_C29_0 */
630 { 20538, 0x0000 }, /* R20538 - DACR_RETUNE_C30_1 */
631 { 20539, 0x0000 }, /* R20539 - DACR_RETUNE_C30_0 */
632 { 20540, 0x0000 }, /* R20540 - DACR_RETUNE_C31_1 */
633 { 20541, 0x0000 }, /* R20541 - DACR_RETUNE_C31_0 */
634 { 20542, 0x0000 }, /* R20542 - DACR_RETUNE_C32_1 */
635 { 20543, 0x0000 }, /* R20543 - DACR_RETUNE_C32_0 */
636
637 { 20992, 0x008C }, /* R20992 - VSS_XHD2_1 */
638 { 20993, 0x0200 }, /* R20993 - VSS_XHD2_0 */
639 { 20994, 0x0035 }, /* R20994 - VSS_XHD3_1 */
640 { 20995, 0x0700 }, /* R20995 - VSS_XHD3_0 */
641 { 20996, 0x003A }, /* R20996 - VSS_XHN1_1 */
642 { 20997, 0x4100 }, /* R20997 - VSS_XHN1_0 */
643 { 20998, 0x008B }, /* R20998 - VSS_XHN2_1 */
644 { 20999, 0x7D00 }, /* R20999 - VSS_XHN2_0 */
645 { 21000, 0x003A }, /* R21000 - VSS_XHN3_1 */
646 { 21001, 0x4100 }, /* R21001 - VSS_XHN3_0 */
647 { 21002, 0x008C }, /* R21002 - VSS_XLA_1 */
648 { 21003, 0xFEE8 }, /* R21003 - VSS_XLA_0 */
649 { 21004, 0x0078 }, /* R21004 - VSS_XLB_1 */
650 { 21005, 0x0000 }, /* R21005 - VSS_XLB_0 */
651 { 21006, 0x003F }, /* R21006 - VSS_XLG_1 */
652 { 21007, 0xB260 }, /* R21007 - VSS_XLG_0 */
653 { 21008, 0x002D }, /* R21008 - VSS_PG2_1 */
654 { 21009, 0x1818 }, /* R21009 - VSS_PG2_0 */
655 { 21010, 0x0020 }, /* R21010 - VSS_PG_1 */
656 { 21011, 0x0000 }, /* R21011 - VSS_PG_0 */
657 { 21012, 0x00F1 }, /* R21012 - VSS_XTD1_1 */
658 { 21013, 0x8340 }, /* R21013 - VSS_XTD1_0 */
659 { 21014, 0x00FB }, /* R21014 - VSS_XTD2_1 */
660 { 21015, 0x8300 }, /* R21015 - VSS_XTD2_0 */
661 { 21016, 0x00EE }, /* R21016 - VSS_XTD3_1 */
662 { 21017, 0xAEC0 }, /* R21017 - VSS_XTD3_0 */
663 { 21018, 0x00FB }, /* R21018 - VSS_XTD4_1 */
664 { 21019, 0xAC40 }, /* R21019 - VSS_XTD4_0 */
665 { 21020, 0x00F1 }, /* R21020 - VSS_XTD5_1 */
666 { 21021, 0x7F80 }, /* R21021 - VSS_XTD5_0 */
667 { 21022, 0x00F4 }, /* R21022 - VSS_XTD6_1 */
668 { 21023, 0x3B40 }, /* R21023 - VSS_XTD6_0 */
669 { 21024, 0x00F5 }, /* R21024 - VSS_XTD7_1 */
670 { 21025, 0xFB00 }, /* R21025 - VSS_XTD7_0 */
671 { 21026, 0x00EA }, /* R21026 - VSS_XTD8_1 */
672 { 21027, 0x10C0 }, /* R21027 - VSS_XTD8_0 */
673 { 21028, 0x00FC }, /* R21028 - VSS_XTD9_1 */
674 { 21029, 0xC580 }, /* R21029 - VSS_XTD9_0 */
675 { 21030, 0x00E2 }, /* R21030 - VSS_XTD10_1 */
676 { 21031, 0x75C0 }, /* R21031 - VSS_XTD10_0 */
677 { 21032, 0x0004 }, /* R21032 - VSS_XTD11_1 */
678 { 21033, 0xB480 }, /* R21033 - VSS_XTD11_0 */
679 { 21034, 0x00D4 }, /* R21034 - VSS_XTD12_1 */
680 { 21035, 0xF980 }, /* R21035 - VSS_XTD12_0 */
681 { 21036, 0x0004 }, /* R21036 - VSS_XTD13_1 */
682 { 21037, 0x9140 }, /* R21037 - VSS_XTD13_0 */
683 { 21038, 0x00D8 }, /* R21038 - VSS_XTD14_1 */
684 { 21039, 0xA480 }, /* R21039 - VSS_XTD14_0 */
685 { 21040, 0x0002 }, /* R21040 - VSS_XTD15_1 */
686 { 21041, 0x3DC0 }, /* R21041 - VSS_XTD15_0 */
687 { 21042, 0x00CF }, /* R21042 - VSS_XTD16_1 */
688 { 21043, 0x7A80 }, /* R21043 - VSS_XTD16_0 */
689 { 21044, 0x00DC }, /* R21044 - VSS_XTD17_1 */
690 { 21045, 0x0600 }, /* R21045 - VSS_XTD17_0 */
691 { 21046, 0x00F2 }, /* R21046 - VSS_XTD18_1 */
692 { 21047, 0xDAC0 }, /* R21047 - VSS_XTD18_0 */
693 { 21048, 0x00BA }, /* R21048 - VSS_XTD19_1 */
694 { 21049, 0xF340 }, /* R21049 - VSS_XTD19_0 */
695 { 21050, 0x000A }, /* R21050 - VSS_XTD20_1 */
696 { 21051, 0x7940 }, /* R21051 - VSS_XTD20_0 */
697 { 21052, 0x001C }, /* R21052 - VSS_XTD21_1 */
698 { 21053, 0x0680 }, /* R21053 - VSS_XTD21_0 */
699 { 21054, 0x00FD }, /* R21054 - VSS_XTD22_1 */
700 { 21055, 0x2D00 }, /* R21055 - VSS_XTD22_0 */
701 { 21056, 0x001C }, /* R21056 - VSS_XTD23_1 */
702 { 21057, 0xE840 }, /* R21057 - VSS_XTD23_0 */
703 { 21058, 0x000D }, /* R21058 - VSS_XTD24_1 */
704 { 21059, 0xDC40 }, /* R21059 - VSS_XTD24_0 */
705 { 21060, 0x00FC }, /* R21060 - VSS_XTD25_1 */
706 { 21061, 0x9D00 }, /* R21061 - VSS_XTD25_0 */
707 { 21062, 0x0009 }, /* R21062 - VSS_XTD26_1 */
708 { 21063, 0x5580 }, /* R21063 - VSS_XTD26_0 */
709 { 21064, 0x00FE }, /* R21064 - VSS_XTD27_1 */
710 { 21065, 0x7E80 }, /* R21065 - VSS_XTD27_0 */
711 { 21066, 0x000E }, /* R21066 - VSS_XTD28_1 */
712 { 21067, 0xAB40 }, /* R21067 - VSS_XTD28_0 */
713 { 21068, 0x00F9 }, /* R21068 - VSS_XTD29_1 */
714 { 21069, 0x9880 }, /* R21069 - VSS_XTD29_0 */
715 { 21070, 0x0009 }, /* R21070 - VSS_XTD30_1 */
716 { 21071, 0x87C0 }, /* R21071 - VSS_XTD30_0 */
717 { 21072, 0x00FD }, /* R21072 - VSS_XTD31_1 */
718 { 21073, 0x2C40 }, /* R21073 - VSS_XTD31_0 */
719 { 21074, 0x0009 }, /* R21074 - VSS_XTD32_1 */
720 { 21075, 0x4800 }, /* R21075 - VSS_XTD32_0 */
721 { 21076, 0x0003 }, /* R21076 - VSS_XTS1_1 */
722 { 21077, 0x5F40 }, /* R21077 - VSS_XTS1_0 */
723 { 21078, 0x0000 }, /* R21078 - VSS_XTS2_1 */
724 { 21079, 0x8700 }, /* R21079 - VSS_XTS2_0 */
725 { 21080, 0x00FA }, /* R21080 - VSS_XTS3_1 */
726 { 21081, 0xE4C0 }, /* R21081 - VSS_XTS3_0 */
727 { 21082, 0x0000 }, /* R21082 - VSS_XTS4_1 */
728 { 21083, 0x0B40 }, /* R21083 - VSS_XTS4_0 */
729 { 21084, 0x0004 }, /* R21084 - VSS_XTS5_1 */
730 { 21085, 0xE180 }, /* R21085 - VSS_XTS5_0 */
731 { 21086, 0x0001 }, /* R21086 - VSS_XTS6_1 */
732 { 21087, 0x1F40 }, /* R21087 - VSS_XTS6_0 */
733 { 21088, 0x00F8 }, /* R21088 - VSS_XTS7_1 */
734 { 21089, 0xB000 }, /* R21089 - VSS_XTS7_0 */
735 { 21090, 0x00FB }, /* R21090 - VSS_XTS8_1 */
736 { 21091, 0xCBC0 }, /* R21091 - VSS_XTS8_0 */
737 { 21092, 0x0004 }, /* R21092 - VSS_XTS9_1 */
738 { 21093, 0xF380 }, /* R21093 - VSS_XTS9_0 */
739 { 21094, 0x0007 }, /* R21094 - VSS_XTS10_1 */
740 { 21095, 0xDF40 }, /* R21095 - VSS_XTS10_0 */
741 { 21096, 0x00FF }, /* R21096 - VSS_XTS11_1 */
742 { 21097, 0x0700 }, /* R21097 - VSS_XTS11_0 */
743 { 21098, 0x00EF }, /* R21098 - VSS_XTS12_1 */
744 { 21099, 0xD700 }, /* R21099 - VSS_XTS12_0 */
745 { 21100, 0x00FB }, /* R21100 - VSS_XTS13_1 */
746 { 21101, 0xAF40 }, /* R21101 - VSS_XTS13_0 */
747 { 21102, 0x0010 }, /* R21102 - VSS_XTS14_1 */
748 { 21103, 0x8A80 }, /* R21103 - VSS_XTS14_0 */
749 { 21104, 0x0011 }, /* R21104 - VSS_XTS15_1 */
750 { 21105, 0x07C0 }, /* R21105 - VSS_XTS15_0 */
751 { 21106, 0x00E0 }, /* R21106 - VSS_XTS16_1 */
752 { 21107, 0x0800 }, /* R21107 - VSS_XTS16_0 */
753 { 21108, 0x00D2 }, /* R21108 - VSS_XTS17_1 */
754 { 21109, 0x7600 }, /* R21109 - VSS_XTS17_0 */
755 { 21110, 0x0020 }, /* R21110 - VSS_XTS18_1 */
756 { 21111, 0xCF40 }, /* R21111 - VSS_XTS18_0 */
757 { 21112, 0x0030 }, /* R21112 - VSS_XTS19_1 */
758 { 21113, 0x2340 }, /* R21113 - VSS_XTS19_0 */
759 { 21114, 0x00FD }, /* R21114 - VSS_XTS20_1 */
760 { 21115, 0x69C0 }, /* R21115 - VSS_XTS20_0 */
761 { 21116, 0x0028 }, /* R21116 - VSS_XTS21_1 */
762 { 21117, 0x3500 }, /* R21117 - VSS_XTS21_0 */
763 { 21118, 0x0006 }, /* R21118 - VSS_XTS22_1 */
764 { 21119, 0x3300 }, /* R21119 - VSS_XTS22_0 */
765 { 21120, 0x00D9 }, /* R21120 - VSS_XTS23_1 */
766 { 21121, 0xF6C0 }, /* R21121 - VSS_XTS23_0 */
767 { 21122, 0x00F3 }, /* R21122 - VSS_XTS24_1 */
768 { 21123, 0x3340 }, /* R21123 - VSS_XTS24_0 */
769 { 21124, 0x000F }, /* R21124 - VSS_XTS25_1 */
770 { 21125, 0x4200 }, /* R21125 - VSS_XTS25_0 */
771 { 21126, 0x0004 }, /* R21126 - VSS_XTS26_1 */
772 { 21127, 0x0C80 }, /* R21127 - VSS_XTS26_0 */
773 { 21128, 0x00FB }, /* R21128 - VSS_XTS27_1 */
774 { 21129, 0x3F80 }, /* R21129 - VSS_XTS27_0 */
775 { 21130, 0x00F7 }, /* R21130 - VSS_XTS28_1 */
776 { 21131, 0x57C0 }, /* R21131 - VSS_XTS28_0 */
777 { 21132, 0x0003 }, /* R21132 - VSS_XTS29_1 */
778 { 21133, 0x5400 }, /* R21133 - VSS_XTS29_0 */
779 { 21134, 0x0000 }, /* R21134 - VSS_XTS30_1 */
780 { 21135, 0xC6C0 }, /* R21135 - VSS_XTS30_0 */
781 { 21136, 0x0003 }, /* R21136 - VSS_XTS31_1 */
782 { 21137, 0x12C0 }, /* R21137 - VSS_XTS31_0 */
783 { 21138, 0x00FD }, /* R21138 - VSS_XTS32_1 */
784 { 21139, 0x8580 }, /* R21139 - VSS_XTS32_0 */
785};
786
787static bool wm8962_volatile_register(struct device *dev, unsigned int reg)
788{
789 switch (reg) {
790 case WM8962_CLOCKING1:
791 case WM8962_SOFTWARE_RESET:
792 case WM8962_THERMAL_SHUTDOWN_STATUS:
793 case WM8962_ADDITIONAL_CONTROL_4:
794 case WM8962_DC_SERVO_6:
795 case WM8962_INTERRUPT_STATUS_1:
796 case WM8962_INTERRUPT_STATUS_2:
797 case WM8962_DSP2_EXECCONTROL:
798 return true;
799 default:
800 return false;
801 }
802}
803
804static bool wm8962_readable_register(struct device *dev, unsigned int reg)
805{
806 switch (reg) {
807 case WM8962_LEFT_INPUT_VOLUME:
808 case WM8962_RIGHT_INPUT_VOLUME:
809 case WM8962_HPOUTL_VOLUME:
810 case WM8962_HPOUTR_VOLUME:
811 case WM8962_CLOCKING1:
812 case WM8962_ADC_DAC_CONTROL_1:
813 case WM8962_ADC_DAC_CONTROL_2:
814 case WM8962_AUDIO_INTERFACE_0:
815 case WM8962_CLOCKING2:
816 case WM8962_AUDIO_INTERFACE_1:
817 case WM8962_LEFT_DAC_VOLUME:
818 case WM8962_RIGHT_DAC_VOLUME:
819 case WM8962_AUDIO_INTERFACE_2:
820 case WM8962_SOFTWARE_RESET:
821 case WM8962_ALC1:
822 case WM8962_ALC2:
823 case WM8962_ALC3:
824 case WM8962_NOISE_GATE:
825 case WM8962_LEFT_ADC_VOLUME:
826 case WM8962_RIGHT_ADC_VOLUME:
827 case WM8962_ADDITIONAL_CONTROL_1:
828 case WM8962_ADDITIONAL_CONTROL_2:
829 case WM8962_PWR_MGMT_1:
830 case WM8962_PWR_MGMT_2:
831 case WM8962_ADDITIONAL_CONTROL_3:
832 case WM8962_ANTI_POP:
833 case WM8962_CLOCKING_3:
834 case WM8962_INPUT_MIXER_CONTROL_1:
835 case WM8962_LEFT_INPUT_MIXER_VOLUME:
836 case WM8962_RIGHT_INPUT_MIXER_VOLUME:
837 case WM8962_INPUT_MIXER_CONTROL_2:
838 case WM8962_INPUT_BIAS_CONTROL:
839 case WM8962_LEFT_INPUT_PGA_CONTROL:
840 case WM8962_RIGHT_INPUT_PGA_CONTROL:
841 case WM8962_SPKOUTL_VOLUME:
842 case WM8962_SPKOUTR_VOLUME:
843 case WM8962_THERMAL_SHUTDOWN_STATUS:
844 case WM8962_ADDITIONAL_CONTROL_4:
845 case WM8962_CLASS_D_CONTROL_1:
846 case WM8962_CLASS_D_CONTROL_2:
847 case WM8962_CLOCKING_4:
848 case WM8962_DAC_DSP_MIXING_1:
849 case WM8962_DAC_DSP_MIXING_2:
850 case WM8962_DC_SERVO_0:
851 case WM8962_DC_SERVO_1:
852 case WM8962_DC_SERVO_4:
853 case WM8962_DC_SERVO_6:
854 case WM8962_ANALOGUE_PGA_BIAS:
855 case WM8962_ANALOGUE_HP_0:
856 case WM8962_ANALOGUE_HP_2:
857 case WM8962_CHARGE_PUMP_1:
858 case WM8962_CHARGE_PUMP_B:
859 case WM8962_WRITE_SEQUENCER_CONTROL_1:
860 case WM8962_WRITE_SEQUENCER_CONTROL_2:
861 case WM8962_WRITE_SEQUENCER_CONTROL_3:
862 case WM8962_CONTROL_INTERFACE:
863 case WM8962_MIXER_ENABLES:
864 case WM8962_HEADPHONE_MIXER_1:
865 case WM8962_HEADPHONE_MIXER_2:
866 case WM8962_HEADPHONE_MIXER_3:
867 case WM8962_HEADPHONE_MIXER_4:
868 case WM8962_SPEAKER_MIXER_1:
869 case WM8962_SPEAKER_MIXER_2:
870 case WM8962_SPEAKER_MIXER_3:
871 case WM8962_SPEAKER_MIXER_4:
872 case WM8962_SPEAKER_MIXER_5:
873 case WM8962_BEEP_GENERATOR_1:
874 case WM8962_OSCILLATOR_TRIM_3:
875 case WM8962_OSCILLATOR_TRIM_4:
876 case WM8962_OSCILLATOR_TRIM_7:
877 case WM8962_ANALOGUE_CLOCKING1:
878 case WM8962_ANALOGUE_CLOCKING2:
879 case WM8962_ANALOGUE_CLOCKING3:
880 case WM8962_PLL_SOFTWARE_RESET:
881 case WM8962_PLL2:
882 case WM8962_PLL_4:
883 case WM8962_PLL_9:
884 case WM8962_PLL_10:
885 case WM8962_PLL_11:
886 case WM8962_PLL_12:
887 case WM8962_PLL_13:
888 case WM8962_PLL_14:
889 case WM8962_PLL_15:
890 case WM8962_PLL_16:
891 case WM8962_FLL_CONTROL_1:
892 case WM8962_FLL_CONTROL_2:
893 case WM8962_FLL_CONTROL_3:
894 case WM8962_FLL_CONTROL_5:
895 case WM8962_FLL_CONTROL_6:
896 case WM8962_FLL_CONTROL_7:
897 case WM8962_FLL_CONTROL_8:
898 case WM8962_GENERAL_TEST_1:
899 case WM8962_DF1:
900 case WM8962_DF2:
901 case WM8962_DF3:
902 case WM8962_DF4:
903 case WM8962_DF5:
904 case WM8962_DF6:
905 case WM8962_DF7:
906 case WM8962_LHPF1:
907 case WM8962_LHPF2:
908 case WM8962_THREED1:
909 case WM8962_THREED2:
910 case WM8962_THREED3:
911 case WM8962_THREED4:
912 case WM8962_DRC_1:
913 case WM8962_DRC_2:
914 case WM8962_DRC_3:
915 case WM8962_DRC_4:
916 case WM8962_DRC_5:
917 case WM8962_TLOOPBACK:
918 case WM8962_EQ1:
919 case WM8962_EQ2:
920 case WM8962_EQ3:
921 case WM8962_EQ4:
922 case WM8962_EQ5:
923 case WM8962_EQ6:
924 case WM8962_EQ7:
925 case WM8962_EQ8:
926 case WM8962_EQ9:
927 case WM8962_EQ10:
928 case WM8962_EQ11:
929 case WM8962_EQ12:
930 case WM8962_EQ13:
931 case WM8962_EQ14:
932 case WM8962_EQ15:
933 case WM8962_EQ16:
934 case WM8962_EQ17:
935 case WM8962_EQ18:
936 case WM8962_EQ19:
937 case WM8962_EQ20:
938 case WM8962_EQ21:
939 case WM8962_EQ22:
940 case WM8962_EQ23:
941 case WM8962_EQ24:
942 case WM8962_EQ25:
943 case WM8962_EQ26:
944 case WM8962_EQ27:
945 case WM8962_EQ28:
946 case WM8962_EQ29:
947 case WM8962_EQ30:
948 case WM8962_EQ31:
949 case WM8962_EQ32:
950 case WM8962_EQ33:
951 case WM8962_EQ34:
952 case WM8962_EQ35:
953 case WM8962_EQ36:
954 case WM8962_EQ37:
955 case WM8962_EQ38:
956 case WM8962_EQ39:
957 case WM8962_EQ40:
958 case WM8962_EQ41:
959 case WM8962_GPIO_2:
960 case WM8962_GPIO_3:
961 case WM8962_GPIO_5:
962 case WM8962_GPIO_6:
963 case WM8962_INTERRUPT_STATUS_1:
964 case WM8962_INTERRUPT_STATUS_2:
965 case WM8962_INTERRUPT_STATUS_1_MASK:
966 case WM8962_INTERRUPT_STATUS_2_MASK:
967 case WM8962_INTERRUPT_CONTROL:
968 case WM8962_IRQ_DEBOUNCE:
969 case WM8962_MICINT_SOURCE_POL:
970 case WM8962_DSP2_POWER_MANAGEMENT:
971 case WM8962_DSP2_EXECCONTROL:
972 case WM8962_DSP2_INSTRUCTION_RAM_0:
973 case WM8962_DSP2_ADDRESS_RAM_2:
974 case WM8962_DSP2_ADDRESS_RAM_1:
975 case WM8962_DSP2_ADDRESS_RAM_0:
976 case WM8962_DSP2_DATA1_RAM_1:
977 case WM8962_DSP2_DATA1_RAM_0:
978 case WM8962_DSP2_DATA2_RAM_1:
979 case WM8962_DSP2_DATA2_RAM_0:
980 case WM8962_DSP2_DATA3_RAM_1:
981 case WM8962_DSP2_DATA3_RAM_0:
982 case WM8962_DSP2_COEFF_RAM_0:
983 case WM8962_RETUNEADC_SHARED_COEFF_1:
984 case WM8962_RETUNEADC_SHARED_COEFF_0:
985 case WM8962_RETUNEDAC_SHARED_COEFF_1:
986 case WM8962_RETUNEDAC_SHARED_COEFF_0:
987 case WM8962_SOUNDSTAGE_ENABLES_1:
988 case WM8962_SOUNDSTAGE_ENABLES_0:
989 case WM8962_HDBASS_AI_1:
990 case WM8962_HDBASS_AI_0:
991 case WM8962_HDBASS_AR_1:
992 case WM8962_HDBASS_AR_0:
993 case WM8962_HDBASS_B_1:
994 case WM8962_HDBASS_B_0:
995 case WM8962_HDBASS_K_1:
996 case WM8962_HDBASS_K_0:
997 case WM8962_HDBASS_N1_1:
998 case WM8962_HDBASS_N1_0:
999 case WM8962_HDBASS_N2_1:
1000 case WM8962_HDBASS_N2_0:
1001 case WM8962_HDBASS_N3_1:
1002 case WM8962_HDBASS_N3_0:
1003 case WM8962_HDBASS_N4_1:
1004 case WM8962_HDBASS_N4_0:
1005 case WM8962_HDBASS_N5_1:
1006 case WM8962_HDBASS_N5_0:
1007 case WM8962_HDBASS_X1_1:
1008 case WM8962_HDBASS_X1_0:
1009 case WM8962_HDBASS_X2_1:
1010 case WM8962_HDBASS_X2_0:
1011 case WM8962_HDBASS_X3_1:
1012 case WM8962_HDBASS_X3_0:
1013 case WM8962_HDBASS_ATK_1:
1014 case WM8962_HDBASS_ATK_0:
1015 case WM8962_HDBASS_DCY_1:
1016 case WM8962_HDBASS_DCY_0:
1017 case WM8962_HDBASS_PG_1:
1018 case WM8962_HDBASS_PG_0:
1019 case WM8962_HPF_C_1:
1020 case WM8962_HPF_C_0:
1021 case WM8962_ADCL_RETUNE_C1_1:
1022 case WM8962_ADCL_RETUNE_C1_0:
1023 case WM8962_ADCL_RETUNE_C2_1:
1024 case WM8962_ADCL_RETUNE_C2_0:
1025 case WM8962_ADCL_RETUNE_C3_1:
1026 case WM8962_ADCL_RETUNE_C3_0:
1027 case WM8962_ADCL_RETUNE_C4_1:
1028 case WM8962_ADCL_RETUNE_C4_0:
1029 case WM8962_ADCL_RETUNE_C5_1:
1030 case WM8962_ADCL_RETUNE_C5_0:
1031 case WM8962_ADCL_RETUNE_C6_1:
1032 case WM8962_ADCL_RETUNE_C6_0:
1033 case WM8962_ADCL_RETUNE_C7_1:
1034 case WM8962_ADCL_RETUNE_C7_0:
1035 case WM8962_ADCL_RETUNE_C8_1:
1036 case WM8962_ADCL_RETUNE_C8_0:
1037 case WM8962_ADCL_RETUNE_C9_1:
1038 case WM8962_ADCL_RETUNE_C9_0:
1039 case WM8962_ADCL_RETUNE_C10_1:
1040 case WM8962_ADCL_RETUNE_C10_0:
1041 case WM8962_ADCL_RETUNE_C11_1:
1042 case WM8962_ADCL_RETUNE_C11_0:
1043 case WM8962_ADCL_RETUNE_C12_1:
1044 case WM8962_ADCL_RETUNE_C12_0:
1045 case WM8962_ADCL_RETUNE_C13_1:
1046 case WM8962_ADCL_RETUNE_C13_0:
1047 case WM8962_ADCL_RETUNE_C14_1:
1048 case WM8962_ADCL_RETUNE_C14_0:
1049 case WM8962_ADCL_RETUNE_C15_1:
1050 case WM8962_ADCL_RETUNE_C15_0:
1051 case WM8962_ADCL_RETUNE_C16_1:
1052 case WM8962_ADCL_RETUNE_C16_0:
1053 case WM8962_ADCL_RETUNE_C17_1:
1054 case WM8962_ADCL_RETUNE_C17_0:
1055 case WM8962_ADCL_RETUNE_C18_1:
1056 case WM8962_ADCL_RETUNE_C18_0:
1057 case WM8962_ADCL_RETUNE_C19_1:
1058 case WM8962_ADCL_RETUNE_C19_0:
1059 case WM8962_ADCL_RETUNE_C20_1:
1060 case WM8962_ADCL_RETUNE_C20_0:
1061 case WM8962_ADCL_RETUNE_C21_1:
1062 case WM8962_ADCL_RETUNE_C21_0:
1063 case WM8962_ADCL_RETUNE_C22_1:
1064 case WM8962_ADCL_RETUNE_C22_0:
1065 case WM8962_ADCL_RETUNE_C23_1:
1066 case WM8962_ADCL_RETUNE_C23_0:
1067 case WM8962_ADCL_RETUNE_C24_1:
1068 case WM8962_ADCL_RETUNE_C24_0:
1069 case WM8962_ADCL_RETUNE_C25_1:
1070 case WM8962_ADCL_RETUNE_C25_0:
1071 case WM8962_ADCL_RETUNE_C26_1:
1072 case WM8962_ADCL_RETUNE_C26_0:
1073 case WM8962_ADCL_RETUNE_C27_1:
1074 case WM8962_ADCL_RETUNE_C27_0:
1075 case WM8962_ADCL_RETUNE_C28_1:
1076 case WM8962_ADCL_RETUNE_C28_0:
1077 case WM8962_ADCL_RETUNE_C29_1:
1078 case WM8962_ADCL_RETUNE_C29_0:
1079 case WM8962_ADCL_RETUNE_C30_1:
1080 case WM8962_ADCL_RETUNE_C30_0:
1081 case WM8962_ADCL_RETUNE_C31_1:
1082 case WM8962_ADCL_RETUNE_C31_0:
1083 case WM8962_ADCL_RETUNE_C32_1:
1084 case WM8962_ADCL_RETUNE_C32_0:
1085 case WM8962_RETUNEADC_PG2_1:
1086 case WM8962_RETUNEADC_PG2_0:
1087 case WM8962_RETUNEADC_PG_1:
1088 case WM8962_RETUNEADC_PG_0:
1089 case WM8962_ADCR_RETUNE_C1_1:
1090 case WM8962_ADCR_RETUNE_C1_0:
1091 case WM8962_ADCR_RETUNE_C2_1:
1092 case WM8962_ADCR_RETUNE_C2_0:
1093 case WM8962_ADCR_RETUNE_C3_1:
1094 case WM8962_ADCR_RETUNE_C3_0:
1095 case WM8962_ADCR_RETUNE_C4_1:
1096 case WM8962_ADCR_RETUNE_C4_0:
1097 case WM8962_ADCR_RETUNE_C5_1:
1098 case WM8962_ADCR_RETUNE_C5_0:
1099 case WM8962_ADCR_RETUNE_C6_1:
1100 case WM8962_ADCR_RETUNE_C6_0:
1101 case WM8962_ADCR_RETUNE_C7_1:
1102 case WM8962_ADCR_RETUNE_C7_0:
1103 case WM8962_ADCR_RETUNE_C8_1:
1104 case WM8962_ADCR_RETUNE_C8_0:
1105 case WM8962_ADCR_RETUNE_C9_1:
1106 case WM8962_ADCR_RETUNE_C9_0:
1107 case WM8962_ADCR_RETUNE_C10_1:
1108 case WM8962_ADCR_RETUNE_C10_0:
1109 case WM8962_ADCR_RETUNE_C11_1:
1110 case WM8962_ADCR_RETUNE_C11_0:
1111 case WM8962_ADCR_RETUNE_C12_1:
1112 case WM8962_ADCR_RETUNE_C12_0:
1113 case WM8962_ADCR_RETUNE_C13_1:
1114 case WM8962_ADCR_RETUNE_C13_0:
1115 case WM8962_ADCR_RETUNE_C14_1:
1116 case WM8962_ADCR_RETUNE_C14_0:
1117 case WM8962_ADCR_RETUNE_C15_1:
1118 case WM8962_ADCR_RETUNE_C15_0:
1119 case WM8962_ADCR_RETUNE_C16_1:
1120 case WM8962_ADCR_RETUNE_C16_0:
1121 case WM8962_ADCR_RETUNE_C17_1:
1122 case WM8962_ADCR_RETUNE_C17_0:
1123 case WM8962_ADCR_RETUNE_C18_1:
1124 case WM8962_ADCR_RETUNE_C18_0:
1125 case WM8962_ADCR_RETUNE_C19_1:
1126 case WM8962_ADCR_RETUNE_C19_0:
1127 case WM8962_ADCR_RETUNE_C20_1:
1128 case WM8962_ADCR_RETUNE_C20_0:
1129 case WM8962_ADCR_RETUNE_C21_1:
1130 case WM8962_ADCR_RETUNE_C21_0:
1131 case WM8962_ADCR_RETUNE_C22_1:
1132 case WM8962_ADCR_RETUNE_C22_0:
1133 case WM8962_ADCR_RETUNE_C23_1:
1134 case WM8962_ADCR_RETUNE_C23_0:
1135 case WM8962_ADCR_RETUNE_C24_1:
1136 case WM8962_ADCR_RETUNE_C24_0:
1137 case WM8962_ADCR_RETUNE_C25_1:
1138 case WM8962_ADCR_RETUNE_C25_0:
1139 case WM8962_ADCR_RETUNE_C26_1:
1140 case WM8962_ADCR_RETUNE_C26_0:
1141 case WM8962_ADCR_RETUNE_C27_1:
1142 case WM8962_ADCR_RETUNE_C27_0:
1143 case WM8962_ADCR_RETUNE_C28_1:
1144 case WM8962_ADCR_RETUNE_C28_0:
1145 case WM8962_ADCR_RETUNE_C29_1:
1146 case WM8962_ADCR_RETUNE_C29_0:
1147 case WM8962_ADCR_RETUNE_C30_1:
1148 case WM8962_ADCR_RETUNE_C30_0:
1149 case WM8962_ADCR_RETUNE_C31_1:
1150 case WM8962_ADCR_RETUNE_C31_0:
1151 case WM8962_ADCR_RETUNE_C32_1:
1152 case WM8962_ADCR_RETUNE_C32_0:
1153 case WM8962_DACL_RETUNE_C1_1:
1154 case WM8962_DACL_RETUNE_C1_0:
1155 case WM8962_DACL_RETUNE_C2_1:
1156 case WM8962_DACL_RETUNE_C2_0:
1157 case WM8962_DACL_RETUNE_C3_1:
1158 case WM8962_DACL_RETUNE_C3_0:
1159 case WM8962_DACL_RETUNE_C4_1:
1160 case WM8962_DACL_RETUNE_C4_0:
1161 case WM8962_DACL_RETUNE_C5_1:
1162 case WM8962_DACL_RETUNE_C5_0:
1163 case WM8962_DACL_RETUNE_C6_1:
1164 case WM8962_DACL_RETUNE_C6_0:
1165 case WM8962_DACL_RETUNE_C7_1:
1166 case WM8962_DACL_RETUNE_C7_0:
1167 case WM8962_DACL_RETUNE_C8_1:
1168 case WM8962_DACL_RETUNE_C8_0:
1169 case WM8962_DACL_RETUNE_C9_1:
1170 case WM8962_DACL_RETUNE_C9_0:
1171 case WM8962_DACL_RETUNE_C10_1:
1172 case WM8962_DACL_RETUNE_C10_0:
1173 case WM8962_DACL_RETUNE_C11_1:
1174 case WM8962_DACL_RETUNE_C11_0:
1175 case WM8962_DACL_RETUNE_C12_1:
1176 case WM8962_DACL_RETUNE_C12_0:
1177 case WM8962_DACL_RETUNE_C13_1:
1178 case WM8962_DACL_RETUNE_C13_0:
1179 case WM8962_DACL_RETUNE_C14_1:
1180 case WM8962_DACL_RETUNE_C14_0:
1181 case WM8962_DACL_RETUNE_C15_1:
1182 case WM8962_DACL_RETUNE_C15_0:
1183 case WM8962_DACL_RETUNE_C16_1:
1184 case WM8962_DACL_RETUNE_C16_0:
1185 case WM8962_DACL_RETUNE_C17_1:
1186 case WM8962_DACL_RETUNE_C17_0:
1187 case WM8962_DACL_RETUNE_C18_1:
1188 case WM8962_DACL_RETUNE_C18_0:
1189 case WM8962_DACL_RETUNE_C19_1:
1190 case WM8962_DACL_RETUNE_C19_0:
1191 case WM8962_DACL_RETUNE_C20_1:
1192 case WM8962_DACL_RETUNE_C20_0:
1193 case WM8962_DACL_RETUNE_C21_1:
1194 case WM8962_DACL_RETUNE_C21_0:
1195 case WM8962_DACL_RETUNE_C22_1:
1196 case WM8962_DACL_RETUNE_C22_0:
1197 case WM8962_DACL_RETUNE_C23_1:
1198 case WM8962_DACL_RETUNE_C23_0:
1199 case WM8962_DACL_RETUNE_C24_1:
1200 case WM8962_DACL_RETUNE_C24_0:
1201 case WM8962_DACL_RETUNE_C25_1:
1202 case WM8962_DACL_RETUNE_C25_0:
1203 case WM8962_DACL_RETUNE_C26_1:
1204 case WM8962_DACL_RETUNE_C26_0:
1205 case WM8962_DACL_RETUNE_C27_1:
1206 case WM8962_DACL_RETUNE_C27_0:
1207 case WM8962_DACL_RETUNE_C28_1:
1208 case WM8962_DACL_RETUNE_C28_0:
1209 case WM8962_DACL_RETUNE_C29_1:
1210 case WM8962_DACL_RETUNE_C29_0:
1211 case WM8962_DACL_RETUNE_C30_1:
1212 case WM8962_DACL_RETUNE_C30_0:
1213 case WM8962_DACL_RETUNE_C31_1:
1214 case WM8962_DACL_RETUNE_C31_0:
1215 case WM8962_DACL_RETUNE_C32_1:
1216 case WM8962_DACL_RETUNE_C32_0:
1217 case WM8962_RETUNEDAC_PG2_1:
1218 case WM8962_RETUNEDAC_PG2_0:
1219 case WM8962_RETUNEDAC_PG_1:
1220 case WM8962_RETUNEDAC_PG_0:
1221 case WM8962_DACR_RETUNE_C1_1:
1222 case WM8962_DACR_RETUNE_C1_0:
1223 case WM8962_DACR_RETUNE_C2_1:
1224 case WM8962_DACR_RETUNE_C2_0:
1225 case WM8962_DACR_RETUNE_C3_1:
1226 case WM8962_DACR_RETUNE_C3_0:
1227 case WM8962_DACR_RETUNE_C4_1:
1228 case WM8962_DACR_RETUNE_C4_0:
1229 case WM8962_DACR_RETUNE_C5_1:
1230 case WM8962_DACR_RETUNE_C5_0:
1231 case WM8962_DACR_RETUNE_C6_1:
1232 case WM8962_DACR_RETUNE_C6_0:
1233 case WM8962_DACR_RETUNE_C7_1:
1234 case WM8962_DACR_RETUNE_C7_0:
1235 case WM8962_DACR_RETUNE_C8_1:
1236 case WM8962_DACR_RETUNE_C8_0:
1237 case WM8962_DACR_RETUNE_C9_1:
1238 case WM8962_DACR_RETUNE_C9_0:
1239 case WM8962_DACR_RETUNE_C10_1:
1240 case WM8962_DACR_RETUNE_C10_0:
1241 case WM8962_DACR_RETUNE_C11_1:
1242 case WM8962_DACR_RETUNE_C11_0:
1243 case WM8962_DACR_RETUNE_C12_1:
1244 case WM8962_DACR_RETUNE_C12_0:
1245 case WM8962_DACR_RETUNE_C13_1:
1246 case WM8962_DACR_RETUNE_C13_0:
1247 case WM8962_DACR_RETUNE_C14_1:
1248 case WM8962_DACR_RETUNE_C14_0:
1249 case WM8962_DACR_RETUNE_C15_1:
1250 case WM8962_DACR_RETUNE_C15_0:
1251 case WM8962_DACR_RETUNE_C16_1:
1252 case WM8962_DACR_RETUNE_C16_0:
1253 case WM8962_DACR_RETUNE_C17_1:
1254 case WM8962_DACR_RETUNE_C17_0:
1255 case WM8962_DACR_RETUNE_C18_1:
1256 case WM8962_DACR_RETUNE_C18_0:
1257 case WM8962_DACR_RETUNE_C19_1:
1258 case WM8962_DACR_RETUNE_C19_0:
1259 case WM8962_DACR_RETUNE_C20_1:
1260 case WM8962_DACR_RETUNE_C20_0:
1261 case WM8962_DACR_RETUNE_C21_1:
1262 case WM8962_DACR_RETUNE_C21_0:
1263 case WM8962_DACR_RETUNE_C22_1:
1264 case WM8962_DACR_RETUNE_C22_0:
1265 case WM8962_DACR_RETUNE_C23_1:
1266 case WM8962_DACR_RETUNE_C23_0:
1267 case WM8962_DACR_RETUNE_C24_1:
1268 case WM8962_DACR_RETUNE_C24_0:
1269 case WM8962_DACR_RETUNE_C25_1:
1270 case WM8962_DACR_RETUNE_C25_0:
1271 case WM8962_DACR_RETUNE_C26_1:
1272 case WM8962_DACR_RETUNE_C26_0:
1273 case WM8962_DACR_RETUNE_C27_1:
1274 case WM8962_DACR_RETUNE_C27_0:
1275 case WM8962_DACR_RETUNE_C28_1:
1276 case WM8962_DACR_RETUNE_C28_0:
1277 case WM8962_DACR_RETUNE_C29_1:
1278 case WM8962_DACR_RETUNE_C29_0:
1279 case WM8962_DACR_RETUNE_C30_1:
1280 case WM8962_DACR_RETUNE_C30_0:
1281 case WM8962_DACR_RETUNE_C31_1:
1282 case WM8962_DACR_RETUNE_C31_0:
1283 case WM8962_DACR_RETUNE_C32_1:
1284 case WM8962_DACR_RETUNE_C32_0:
1285 case WM8962_VSS_XHD2_1:
1286 case WM8962_VSS_XHD2_0:
1287 case WM8962_VSS_XHD3_1:
1288 case WM8962_VSS_XHD3_0:
1289 case WM8962_VSS_XHN1_1:
1290 case WM8962_VSS_XHN1_0:
1291 case WM8962_VSS_XHN2_1:
1292 case WM8962_VSS_XHN2_0:
1293 case WM8962_VSS_XHN3_1:
1294 case WM8962_VSS_XHN3_0:
1295 case WM8962_VSS_XLA_1:
1296 case WM8962_VSS_XLA_0:
1297 case WM8962_VSS_XLB_1:
1298 case WM8962_VSS_XLB_0:
1299 case WM8962_VSS_XLG_1:
1300 case WM8962_VSS_XLG_0:
1301 case WM8962_VSS_PG2_1:
1302 case WM8962_VSS_PG2_0:
1303 case WM8962_VSS_PG_1:
1304 case WM8962_VSS_PG_0:
1305 case WM8962_VSS_XTD1_1:
1306 case WM8962_VSS_XTD1_0:
1307 case WM8962_VSS_XTD2_1:
1308 case WM8962_VSS_XTD2_0:
1309 case WM8962_VSS_XTD3_1:
1310 case WM8962_VSS_XTD3_0:
1311 case WM8962_VSS_XTD4_1:
1312 case WM8962_VSS_XTD4_0:
1313 case WM8962_VSS_XTD5_1:
1314 case WM8962_VSS_XTD5_0:
1315 case WM8962_VSS_XTD6_1:
1316 case WM8962_VSS_XTD6_0:
1317 case WM8962_VSS_XTD7_1:
1318 case WM8962_VSS_XTD7_0:
1319 case WM8962_VSS_XTD8_1:
1320 case WM8962_VSS_XTD8_0:
1321 case WM8962_VSS_XTD9_1:
1322 case WM8962_VSS_XTD9_0:
1323 case WM8962_VSS_XTD10_1:
1324 case WM8962_VSS_XTD10_0:
1325 case WM8962_VSS_XTD11_1:
1326 case WM8962_VSS_XTD11_0:
1327 case WM8962_VSS_XTD12_1:
1328 case WM8962_VSS_XTD12_0:
1329 case WM8962_VSS_XTD13_1:
1330 case WM8962_VSS_XTD13_0:
1331 case WM8962_VSS_XTD14_1:
1332 case WM8962_VSS_XTD14_0:
1333 case WM8962_VSS_XTD15_1:
1334 case WM8962_VSS_XTD15_0:
1335 case WM8962_VSS_XTD16_1:
1336 case WM8962_VSS_XTD16_0:
1337 case WM8962_VSS_XTD17_1:
1338 case WM8962_VSS_XTD17_0:
1339 case WM8962_VSS_XTD18_1:
1340 case WM8962_VSS_XTD18_0:
1341 case WM8962_VSS_XTD19_1:
1342 case WM8962_VSS_XTD19_0:
1343 case WM8962_VSS_XTD20_1:
1344 case WM8962_VSS_XTD20_0:
1345 case WM8962_VSS_XTD21_1:
1346 case WM8962_VSS_XTD21_0:
1347 case WM8962_VSS_XTD22_1:
1348 case WM8962_VSS_XTD22_0:
1349 case WM8962_VSS_XTD23_1:
1350 case WM8962_VSS_XTD23_0:
1351 case WM8962_VSS_XTD24_1:
1352 case WM8962_VSS_XTD24_0:
1353 case WM8962_VSS_XTD25_1:
1354 case WM8962_VSS_XTD25_0:
1355 case WM8962_VSS_XTD26_1:
1356 case WM8962_VSS_XTD26_0:
1357 case WM8962_VSS_XTD27_1:
1358 case WM8962_VSS_XTD27_0:
1359 case WM8962_VSS_XTD28_1:
1360 case WM8962_VSS_XTD28_0:
1361 case WM8962_VSS_XTD29_1:
1362 case WM8962_VSS_XTD29_0:
1363 case WM8962_VSS_XTD30_1:
1364 case WM8962_VSS_XTD30_0:
1365 case WM8962_VSS_XTD31_1:
1366 case WM8962_VSS_XTD31_0:
1367 case WM8962_VSS_XTD32_1:
1368 case WM8962_VSS_XTD32_0:
1369 case WM8962_VSS_XTS1_1:
1370 case WM8962_VSS_XTS1_0:
1371 case WM8962_VSS_XTS2_1:
1372 case WM8962_VSS_XTS2_0:
1373 case WM8962_VSS_XTS3_1:
1374 case WM8962_VSS_XTS3_0:
1375 case WM8962_VSS_XTS4_1:
1376 case WM8962_VSS_XTS4_0:
1377 case WM8962_VSS_XTS5_1:
1378 case WM8962_VSS_XTS5_0:
1379 case WM8962_VSS_XTS6_1:
1380 case WM8962_VSS_XTS6_0:
1381 case WM8962_VSS_XTS7_1:
1382 case WM8962_VSS_XTS7_0:
1383 case WM8962_VSS_XTS8_1:
1384 case WM8962_VSS_XTS8_0:
1385 case WM8962_VSS_XTS9_1:
1386 case WM8962_VSS_XTS9_0:
1387 case WM8962_VSS_XTS10_1:
1388 case WM8962_VSS_XTS10_0:
1389 case WM8962_VSS_XTS11_1:
1390 case WM8962_VSS_XTS11_0:
1391 case WM8962_VSS_XTS12_1:
1392 case WM8962_VSS_XTS12_0:
1393 case WM8962_VSS_XTS13_1:
1394 case WM8962_VSS_XTS13_0:
1395 case WM8962_VSS_XTS14_1:
1396 case WM8962_VSS_XTS14_0:
1397 case WM8962_VSS_XTS15_1:
1398 case WM8962_VSS_XTS15_0:
1399 case WM8962_VSS_XTS16_1:
1400 case WM8962_VSS_XTS16_0:
1401 case WM8962_VSS_XTS17_1:
1402 case WM8962_VSS_XTS17_0:
1403 case WM8962_VSS_XTS18_1:
1404 case WM8962_VSS_XTS18_0:
1405 case WM8962_VSS_XTS19_1:
1406 case WM8962_VSS_XTS19_0:
1407 case WM8962_VSS_XTS20_1:
1408 case WM8962_VSS_XTS20_0:
1409 case WM8962_VSS_XTS21_1:
1410 case WM8962_VSS_XTS21_0:
1411 case WM8962_VSS_XTS22_1:
1412 case WM8962_VSS_XTS22_0:
1413 case WM8962_VSS_XTS23_1:
1414 case WM8962_VSS_XTS23_0:
1415 case WM8962_VSS_XTS24_1:
1416 case WM8962_VSS_XTS24_0:
1417 case WM8962_VSS_XTS25_1:
1418 case WM8962_VSS_XTS25_0:
1419 case WM8962_VSS_XTS26_1:
1420 case WM8962_VSS_XTS26_0:
1421 case WM8962_VSS_XTS27_1:
1422 case WM8962_VSS_XTS27_0:
1423 case WM8962_VSS_XTS28_1:
1424 case WM8962_VSS_XTS28_0:
1425 case WM8962_VSS_XTS29_1:
1426 case WM8962_VSS_XTS29_0:
1427 case WM8962_VSS_XTS30_1:
1428 case WM8962_VSS_XTS30_0:
1429 case WM8962_VSS_XTS31_1:
1430 case WM8962_VSS_XTS31_0:
1431 case WM8962_VSS_XTS32_1:
1432 case WM8962_VSS_XTS32_0:
1433 return true;
1434 default:
1435 return false;
1436 }
1437}
1438
1439static int wm8962_reset(struct wm8962_priv *wm8962)
1440{
1441 int ret;
1442
1443 ret = regmap_write(wm8962->regmap, WM8962_SOFTWARE_RESET, 0x6243);
1444 if (ret != 0)
1445 return ret;
1446
1447 return regmap_write(wm8962->regmap, WM8962_PLL_SOFTWARE_RESET, 0);
1448}
1449
1450static const DECLARE_TLV_DB_SCALE(inpga_tlv, -2325, 75, 0);
1451static const DECLARE_TLV_DB_SCALE(mixin_tlv, -1500, 300, 0);
1452static const DECLARE_TLV_DB_RANGE(mixinpga_tlv,
1453 0, 1, TLV_DB_SCALE_ITEM(0, 600, 0),
1454 2, 2, TLV_DB_SCALE_ITEM(1300, 1300, 0),
1455 3, 4, TLV_DB_SCALE_ITEM(1800, 200, 0),
1456 5, 5, TLV_DB_SCALE_ITEM(2400, 0, 0),
1457 6, 7, TLV_DB_SCALE_ITEM(2700, 300, 0)
1458);
1459static const DECLARE_TLV_DB_SCALE(beep_tlv, -9600, 600, 1);
1460static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
1461static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
1462static const DECLARE_TLV_DB_SCALE(inmix_tlv, -600, 600, 0);
1463static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
1464static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
1465static const DECLARE_TLV_DB_SCALE(hp_tlv, -700, 100, 0);
1466static const DECLARE_TLV_DB_RANGE(classd_tlv,
1467 0, 6, TLV_DB_SCALE_ITEM(0, 150, 0),
1468 7, 7, TLV_DB_SCALE_ITEM(1200, 0, 0)
1469);
1470static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
1471
1472static int wm8962_dsp2_write_config(struct snd_soc_component *component)
1473{
1474 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
1475
1476 return regcache_sync_region(wm8962->regmap,
1477 WM8962_HDBASS_AI_1, WM8962_MAX_REGISTER);
1478}
1479
1480static int wm8962_dsp2_set_enable(struct snd_soc_component *component, u16 val)
1481{
1482 u16 adcl = snd_soc_component_read(component, WM8962_LEFT_ADC_VOLUME);
1483 u16 adcr = snd_soc_component_read(component, WM8962_RIGHT_ADC_VOLUME);
1484 u16 dac = snd_soc_component_read(component, WM8962_ADC_DAC_CONTROL_1);
1485
1486 /* Mute the ADCs and DACs */
1487 snd_soc_component_write(component, WM8962_LEFT_ADC_VOLUME, 0);
1488 snd_soc_component_write(component, WM8962_RIGHT_ADC_VOLUME, WM8962_ADC_VU);
1489 snd_soc_component_update_bits(component, WM8962_ADC_DAC_CONTROL_1,
1490 WM8962_DAC_MUTE, WM8962_DAC_MUTE);
1491
1492 snd_soc_component_write(component, WM8962_SOUNDSTAGE_ENABLES_0, val);
1493
1494 /* Restore the ADCs and DACs */
1495 snd_soc_component_write(component, WM8962_LEFT_ADC_VOLUME, adcl);
1496 snd_soc_component_write(component, WM8962_RIGHT_ADC_VOLUME, adcr);
1497 snd_soc_component_update_bits(component, WM8962_ADC_DAC_CONTROL_1,
1498 WM8962_DAC_MUTE, dac);
1499
1500 return 0;
1501}
1502
1503static int wm8962_dsp2_start(struct snd_soc_component *component)
1504{
1505 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
1506
1507 wm8962_dsp2_write_config(component);
1508
1509 snd_soc_component_write(component, WM8962_DSP2_EXECCONTROL, WM8962_DSP2_RUNR);
1510
1511 wm8962_dsp2_set_enable(component, wm8962->dsp2_ena);
1512
1513 return 0;
1514}
1515
1516static int wm8962_dsp2_stop(struct snd_soc_component *component)
1517{
1518 wm8962_dsp2_set_enable(component, 0);
1519
1520 snd_soc_component_write(component, WM8962_DSP2_EXECCONTROL, WM8962_DSP2_STOP);
1521
1522 return 0;
1523}
1524
1525#define WM8962_DSP2_ENABLE(xname, xshift) \
1526{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1527 .info = wm8962_dsp2_ena_info, \
1528 .get = wm8962_dsp2_ena_get, .put = wm8962_dsp2_ena_put, \
1529 .private_value = xshift }
1530
1531static int wm8962_dsp2_ena_info(struct snd_kcontrol *kcontrol,
1532 struct snd_ctl_elem_info *uinfo)
1533{
1534 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1535
1536 uinfo->count = 1;
1537 uinfo->value.integer.min = 0;
1538 uinfo->value.integer.max = 1;
1539
1540 return 0;
1541}
1542
1543static int wm8962_dsp2_ena_get(struct snd_kcontrol *kcontrol,
1544 struct snd_ctl_elem_value *ucontrol)
1545{
1546 int shift = kcontrol->private_value;
1547 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1548 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
1549
1550 ucontrol->value.integer.value[0] = !!(wm8962->dsp2_ena & 1 << shift);
1551
1552 return 0;
1553}
1554
1555static int wm8962_dsp2_ena_put(struct snd_kcontrol *kcontrol,
1556 struct snd_ctl_elem_value *ucontrol)
1557{
1558 int shift = kcontrol->private_value;
1559 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1560 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
1561 int old = wm8962->dsp2_ena;
1562 int ret = 0;
1563 int dsp2_running = snd_soc_component_read(component, WM8962_DSP2_POWER_MANAGEMENT) &
1564 WM8962_DSP2_ENA;
1565
1566 mutex_lock(&wm8962->dsp2_ena_lock);
1567
1568 if (ucontrol->value.integer.value[0])
1569 wm8962->dsp2_ena |= 1 << shift;
1570 else
1571 wm8962->dsp2_ena &= ~(1 << shift);
1572
1573 if (wm8962->dsp2_ena == old)
1574 goto out;
1575
1576 ret = 1;
1577
1578 if (dsp2_running) {
1579 if (wm8962->dsp2_ena)
1580 wm8962_dsp2_set_enable(component, wm8962->dsp2_ena);
1581 else
1582 wm8962_dsp2_stop(component);
1583 }
1584
1585out:
1586 mutex_unlock(&wm8962->dsp2_ena_lock);
1587
1588 return ret;
1589}
1590
1591/* The VU bits for the headphones are in a different register to the mute
1592 * bits and only take effect on the PGA if it is actually powered.
1593 */
1594static int wm8962_put_hp_sw(struct snd_kcontrol *kcontrol,
1595 struct snd_ctl_elem_value *ucontrol)
1596{
1597 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1598 int ret;
1599
1600 /* Apply the update (if any) */
1601 ret = snd_soc_put_volsw(kcontrol, ucontrol);
1602 if (ret == 0)
1603 return 0;
1604
1605 /* If the left PGA is enabled hit that VU bit... */
1606 ret = snd_soc_component_read(component, WM8962_PWR_MGMT_2);
1607 if (ret & WM8962_HPOUTL_PGA_ENA) {
1608 snd_soc_component_write(component, WM8962_HPOUTL_VOLUME,
1609 snd_soc_component_read(component, WM8962_HPOUTL_VOLUME));
1610 return 1;
1611 }
1612
1613 /* ...otherwise the right. The VU is stereo. */
1614 if (ret & WM8962_HPOUTR_PGA_ENA)
1615 snd_soc_component_write(component, WM8962_HPOUTR_VOLUME,
1616 snd_soc_component_read(component, WM8962_HPOUTR_VOLUME));
1617
1618 return 1;
1619}
1620
1621/* The VU bits for the speakers are in a different register to the mute
1622 * bits and only take effect on the PGA if it is actually powered.
1623 */
1624static int wm8962_put_spk_sw(struct snd_kcontrol *kcontrol,
1625 struct snd_ctl_elem_value *ucontrol)
1626{
1627 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1628 int ret;
1629
1630 /* Apply the update (if any) */
1631 ret = snd_soc_put_volsw(kcontrol, ucontrol);
1632 if (ret == 0)
1633 return 0;
1634
1635 /* If the left PGA is enabled hit that VU bit... */
1636 ret = snd_soc_component_read(component, WM8962_PWR_MGMT_2);
1637 if (ret & WM8962_SPKOUTL_PGA_ENA) {
1638 snd_soc_component_write(component, WM8962_SPKOUTL_VOLUME,
1639 snd_soc_component_read(component, WM8962_SPKOUTL_VOLUME));
1640 return 1;
1641 }
1642
1643 /* ...otherwise the right. The VU is stereo. */
1644 if (ret & WM8962_SPKOUTR_PGA_ENA)
1645 snd_soc_component_write(component, WM8962_SPKOUTR_VOLUME,
1646 snd_soc_component_read(component, WM8962_SPKOUTR_VOLUME));
1647
1648 return 1;
1649}
1650
1651static const char *cap_hpf_mode_text[] = {
1652 "Hi-fi", "Application"
1653};
1654
1655static SOC_ENUM_SINGLE_DECL(cap_hpf_mode,
1656 WM8962_ADC_DAC_CONTROL_2, 10, cap_hpf_mode_text);
1657
1658
1659static const char *cap_lhpf_mode_text[] = {
1660 "LPF", "HPF"
1661};
1662
1663static SOC_ENUM_SINGLE_DECL(cap_lhpf_mode,
1664 WM8962_LHPF1, 1, cap_lhpf_mode_text);
1665
1666static const struct snd_kcontrol_new wm8962_snd_controls[] = {
1667SOC_DOUBLE("Input Mixer Switch", WM8962_INPUT_MIXER_CONTROL_1, 3, 2, 1, 1),
1668
1669SOC_SINGLE_TLV("MIXINL IN2L Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 6, 7, 0,
1670 mixin_tlv),
1671SOC_SINGLE_TLV("MIXINL PGA Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 3, 7, 0,
1672 mixinpga_tlv),
1673SOC_SINGLE_TLV("MIXINL IN3L Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 0, 7, 0,
1674 mixin_tlv),
1675
1676SOC_SINGLE_TLV("MIXINR IN2R Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 6, 7, 0,
1677 mixin_tlv),
1678SOC_SINGLE_TLV("MIXINR PGA Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 3, 7, 0,
1679 mixinpga_tlv),
1680SOC_SINGLE_TLV("MIXINR IN3R Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 0, 7, 0,
1681 mixin_tlv),
1682
1683SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8962_LEFT_ADC_VOLUME,
1684 WM8962_RIGHT_ADC_VOLUME, 1, 127, 0, digital_tlv),
1685SOC_DOUBLE_R_TLV("Capture Volume", WM8962_LEFT_INPUT_VOLUME,
1686 WM8962_RIGHT_INPUT_VOLUME, 0, 63, 0, inpga_tlv),
1687SOC_DOUBLE_R("Capture Switch", WM8962_LEFT_INPUT_VOLUME,
1688 WM8962_RIGHT_INPUT_VOLUME, 7, 1, 1),
1689SOC_DOUBLE_R("Capture ZC Switch", WM8962_LEFT_INPUT_VOLUME,
1690 WM8962_RIGHT_INPUT_VOLUME, 6, 1, 1),
1691SOC_SINGLE("Capture HPF Switch", WM8962_ADC_DAC_CONTROL_1, 0, 1, 1),
1692SOC_ENUM("Capture HPF Mode", cap_hpf_mode),
1693SOC_SINGLE("Capture HPF Cutoff", WM8962_ADC_DAC_CONTROL_2, 7, 7, 0),
1694SOC_SINGLE("Capture LHPF Switch", WM8962_LHPF1, 0, 1, 0),
1695SOC_ENUM("Capture LHPF Mode", cap_lhpf_mode),
1696
1697SOC_DOUBLE_R_TLV("Sidetone Volume", WM8962_DAC_DSP_MIXING_1,
1698 WM8962_DAC_DSP_MIXING_2, 4, 12, 0, st_tlv),
1699
1700SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8962_LEFT_DAC_VOLUME,
1701 WM8962_RIGHT_DAC_VOLUME, 1, 127, 0, digital_tlv),
1702SOC_SINGLE("DAC High Performance Switch", WM8962_ADC_DAC_CONTROL_2, 0, 1, 0),
1703SOC_SINGLE("DAC L/R Swap Switch", WM8962_AUDIO_INTERFACE_0, 5, 1, 0),
1704SOC_SINGLE("ADC L/R Swap Switch", WM8962_AUDIO_INTERFACE_0, 8, 1, 0),
1705SOC_SINGLE("DAC Monomix Switch", WM8962_DAC_DSP_MIXING_1, WM8962_DAC_MONOMIX_SHIFT, 1, 0),
1706SOC_SINGLE("ADC Monomix Switch", WM8962_THREED1, WM8962_ADC_MONOMIX_SHIFT, 1, 0),
1707
1708SOC_SINGLE("ADC High Performance Switch", WM8962_ADDITIONAL_CONTROL_1,
1709 5, 1, 0),
1710
1711SOC_SINGLE_TLV("Beep Volume", WM8962_BEEP_GENERATOR_1, 4, 15, 0, beep_tlv),
1712
1713SOC_DOUBLE_R_TLV("Headphone Volume", WM8962_HPOUTL_VOLUME,
1714 WM8962_HPOUTR_VOLUME, 0, 127, 0, out_tlv),
1715SOC_DOUBLE_EXT("Headphone Switch", WM8962_PWR_MGMT_2, 1, 0, 1, 1,
1716 snd_soc_get_volsw, wm8962_put_hp_sw),
1717SOC_DOUBLE_R("Headphone ZC Switch", WM8962_HPOUTL_VOLUME, WM8962_HPOUTR_VOLUME,
1718 7, 1, 0),
1719SOC_DOUBLE_TLV("Headphone Aux Volume", WM8962_ANALOGUE_HP_2, 3, 6, 7, 0,
1720 hp_tlv),
1721
1722SOC_DOUBLE_R("Headphone Mixer Switch", WM8962_HEADPHONE_MIXER_3,
1723 WM8962_HEADPHONE_MIXER_4, 8, 1, 1),
1724
1725SOC_SINGLE_TLV("HPMIXL IN4L Volume", WM8962_HEADPHONE_MIXER_3,
1726 3, 7, 0, bypass_tlv),
1727SOC_SINGLE_TLV("HPMIXL IN4R Volume", WM8962_HEADPHONE_MIXER_3,
1728 0, 7, 0, bypass_tlv),
1729SOC_SINGLE_TLV("HPMIXL MIXINL Volume", WM8962_HEADPHONE_MIXER_3,
1730 7, 1, 1, inmix_tlv),
1731SOC_SINGLE_TLV("HPMIXL MIXINR Volume", WM8962_HEADPHONE_MIXER_3,
1732 6, 1, 1, inmix_tlv),
1733
1734SOC_SINGLE_TLV("HPMIXR IN4L Volume", WM8962_HEADPHONE_MIXER_4,
1735 3, 7, 0, bypass_tlv),
1736SOC_SINGLE_TLV("HPMIXR IN4R Volume", WM8962_HEADPHONE_MIXER_4,
1737 0, 7, 0, bypass_tlv),
1738SOC_SINGLE_TLV("HPMIXR MIXINL Volume", WM8962_HEADPHONE_MIXER_4,
1739 7, 1, 1, inmix_tlv),
1740SOC_SINGLE_TLV("HPMIXR MIXINR Volume", WM8962_HEADPHONE_MIXER_4,
1741 6, 1, 1, inmix_tlv),
1742
1743SOC_SINGLE_TLV("Speaker Boost Volume", WM8962_CLASS_D_CONTROL_2, 0, 7, 0,
1744 classd_tlv),
1745
1746SOC_SINGLE("EQ Switch", WM8962_EQ1, WM8962_EQ_ENA_SHIFT, 1, 0),
1747SOC_DOUBLE_R_TLV("EQ1 Volume", WM8962_EQ2, WM8962_EQ22,
1748 WM8962_EQL_B1_GAIN_SHIFT, 31, 0, eq_tlv),
1749SOC_DOUBLE_R_TLV("EQ2 Volume", WM8962_EQ2, WM8962_EQ22,
1750 WM8962_EQL_B2_GAIN_SHIFT, 31, 0, eq_tlv),
1751SOC_DOUBLE_R_TLV("EQ3 Volume", WM8962_EQ2, WM8962_EQ22,
1752 WM8962_EQL_B3_GAIN_SHIFT, 31, 0, eq_tlv),
1753SOC_DOUBLE_R_TLV("EQ4 Volume", WM8962_EQ3, WM8962_EQ23,
1754 WM8962_EQL_B4_GAIN_SHIFT, 31, 0, eq_tlv),
1755SOC_DOUBLE_R_TLV("EQ5 Volume", WM8962_EQ3, WM8962_EQ23,
1756 WM8962_EQL_B5_GAIN_SHIFT, 31, 0, eq_tlv),
1757SND_SOC_BYTES("EQL Coefficients", WM8962_EQ4, 18),
1758SND_SOC_BYTES("EQR Coefficients", WM8962_EQ24, 18),
1759
1760
1761SOC_SINGLE("3D Switch", WM8962_THREED1, 0, 1, 0),
1762SND_SOC_BYTES_MASK("3D Coefficients", WM8962_THREED1, 4, WM8962_THREED_ENA),
1763
1764SOC_SINGLE("DF1 Switch", WM8962_DF1, 0, 1, 0),
1765SND_SOC_BYTES_MASK("DF1 Coefficients", WM8962_DF1, 7, WM8962_DF1_ENA),
1766
1767SOC_SINGLE("DRC Switch", WM8962_DRC_1, 0, 1, 0),
1768SND_SOC_BYTES_MASK("DRC Coefficients", WM8962_DRC_1, 5, WM8962_DRC_ENA),
1769
1770WM8962_DSP2_ENABLE("VSS Switch", WM8962_VSS_ENA_SHIFT),
1771SND_SOC_BYTES("VSS Coefficients", WM8962_VSS_XHD2_1, 148),
1772WM8962_DSP2_ENABLE("HPF1 Switch", WM8962_HPF1_ENA_SHIFT),
1773WM8962_DSP2_ENABLE("HPF2 Switch", WM8962_HPF2_ENA_SHIFT),
1774SND_SOC_BYTES("HPF Coefficients", WM8962_LHPF2, 1),
1775WM8962_DSP2_ENABLE("HD Bass Switch", WM8962_HDBASS_ENA_SHIFT),
1776SND_SOC_BYTES("HD Bass Coefficients", WM8962_HDBASS_AI_1, 30),
1777
1778SOC_DOUBLE("ALC Switch", WM8962_ALC1, WM8962_ALCL_ENA_SHIFT,
1779 WM8962_ALCR_ENA_SHIFT, 1, 0),
1780SND_SOC_BYTES_MASK("ALC Coefficients", WM8962_ALC1, 4,
1781 WM8962_ALCL_ENA_MASK | WM8962_ALCR_ENA_MASK),
1782};
1783
1784static const struct snd_kcontrol_new wm8962_spk_mono_controls[] = {
1785SOC_SINGLE_TLV("Speaker Volume", WM8962_SPKOUTL_VOLUME, 0, 127, 0, out_tlv),
1786SOC_SINGLE_EXT("Speaker Switch", WM8962_CLASS_D_CONTROL_1, 1, 1, 1,
1787 snd_soc_get_volsw, wm8962_put_spk_sw),
1788SOC_SINGLE("Speaker ZC Switch", WM8962_SPKOUTL_VOLUME, 7, 1, 0),
1789
1790SOC_SINGLE("Speaker Mixer Switch", WM8962_SPEAKER_MIXER_3, 8, 1, 1),
1791SOC_SINGLE_TLV("Speaker Mixer IN4L Volume", WM8962_SPEAKER_MIXER_3,
1792 3, 7, 0, bypass_tlv),
1793SOC_SINGLE_TLV("Speaker Mixer IN4R Volume", WM8962_SPEAKER_MIXER_3,
1794 0, 7, 0, bypass_tlv),
1795SOC_SINGLE_TLV("Speaker Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_3,
1796 7, 1, 1, inmix_tlv),
1797SOC_SINGLE_TLV("Speaker Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_3,
1798 6, 1, 1, inmix_tlv),
1799SOC_SINGLE_TLV("Speaker Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
1800 7, 1, 0, inmix_tlv),
1801SOC_SINGLE_TLV("Speaker Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
1802 6, 1, 0, inmix_tlv),
1803};
1804
1805static const struct snd_kcontrol_new wm8962_spk_stereo_controls[] = {
1806SOC_DOUBLE_R_TLV("Speaker Volume", WM8962_SPKOUTL_VOLUME,
1807 WM8962_SPKOUTR_VOLUME, 0, 127, 0, out_tlv),
1808SOC_DOUBLE_EXT("Speaker Switch", WM8962_CLASS_D_CONTROL_1, 1, 0, 1, 1,
1809 snd_soc_get_volsw, wm8962_put_spk_sw),
1810SOC_DOUBLE_R("Speaker ZC Switch", WM8962_SPKOUTL_VOLUME, WM8962_SPKOUTR_VOLUME,
1811 7, 1, 0),
1812
1813SOC_DOUBLE_R("Speaker Mixer Switch", WM8962_SPEAKER_MIXER_3,
1814 WM8962_SPEAKER_MIXER_4, 8, 1, 1),
1815
1816SOC_SINGLE_TLV("SPKOUTL Mixer IN4L Volume", WM8962_SPEAKER_MIXER_3,
1817 3, 7, 0, bypass_tlv),
1818SOC_SINGLE_TLV("SPKOUTL Mixer IN4R Volume", WM8962_SPEAKER_MIXER_3,
1819 0, 7, 0, bypass_tlv),
1820SOC_SINGLE_TLV("SPKOUTL Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_3,
1821 7, 1, 1, inmix_tlv),
1822SOC_SINGLE_TLV("SPKOUTL Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_3,
1823 6, 1, 1, inmix_tlv),
1824SOC_SINGLE_TLV("SPKOUTL Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
1825 7, 1, 0, inmix_tlv),
1826SOC_SINGLE_TLV("SPKOUTL Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
1827 6, 1, 0, inmix_tlv),
1828
1829SOC_SINGLE_TLV("SPKOUTR Mixer IN4L Volume", WM8962_SPEAKER_MIXER_4,
1830 3, 7, 0, bypass_tlv),
1831SOC_SINGLE_TLV("SPKOUTR Mixer IN4R Volume", WM8962_SPEAKER_MIXER_4,
1832 0, 7, 0, bypass_tlv),
1833SOC_SINGLE_TLV("SPKOUTR Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_4,
1834 7, 1, 1, inmix_tlv),
1835SOC_SINGLE_TLV("SPKOUTR Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_4,
1836 6, 1, 1, inmix_tlv),
1837SOC_SINGLE_TLV("SPKOUTR Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
1838 5, 1, 0, inmix_tlv),
1839SOC_SINGLE_TLV("SPKOUTR Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
1840 4, 1, 0, inmix_tlv),
1841};
1842
1843static int tp_event(struct snd_soc_dapm_widget *w,
1844 struct snd_kcontrol *kcontrol, int event)
1845{
1846 int ret, reg, val, mask;
1847 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1848
1849 ret = pm_runtime_resume_and_get(component->dev);
1850 if (ret < 0) {
1851 dev_err(component->dev, "Failed to resume device: %d\n", ret);
1852 return ret;
1853 }
1854
1855 reg = WM8962_ADDITIONAL_CONTROL_4;
1856
1857 if (!snd_soc_dapm_widget_name_cmp(w, "TEMP_HP")) {
1858 mask = WM8962_TEMP_ENA_HP_MASK;
1859 val = WM8962_TEMP_ENA_HP;
1860 } else if (!snd_soc_dapm_widget_name_cmp(w, "TEMP_SPK")) {
1861 mask = WM8962_TEMP_ENA_SPK_MASK;
1862 val = WM8962_TEMP_ENA_SPK;
1863 } else {
1864 pm_runtime_put(component->dev);
1865 return -EINVAL;
1866 }
1867
1868 switch (event) {
1869 case SND_SOC_DAPM_POST_PMD:
1870 val = 0;
1871 fallthrough;
1872 case SND_SOC_DAPM_POST_PMU:
1873 ret = snd_soc_component_update_bits(component, reg, mask, val);
1874 break;
1875 default:
1876 WARN(1, "Invalid event %d\n", event);
1877 pm_runtime_put(component->dev);
1878 return -EINVAL;
1879 }
1880
1881 pm_runtime_put(component->dev);
1882
1883 return 0;
1884}
1885
1886static int cp_event(struct snd_soc_dapm_widget *w,
1887 struct snd_kcontrol *kcontrol, int event)
1888{
1889 switch (event) {
1890 case SND_SOC_DAPM_POST_PMU:
1891 msleep(5);
1892 break;
1893
1894 default:
1895 WARN(1, "Invalid event %d\n", event);
1896 return -EINVAL;
1897 }
1898
1899 return 0;
1900}
1901
1902static int hp_event(struct snd_soc_dapm_widget *w,
1903 struct snd_kcontrol *kcontrol, int event)
1904{
1905 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1906 int timeout;
1907 int reg;
1908 int expected = (WM8962_DCS_STARTUP_DONE_HP1L |
1909 WM8962_DCS_STARTUP_DONE_HP1R);
1910
1911 switch (event) {
1912 case SND_SOC_DAPM_POST_PMU:
1913 snd_soc_component_update_bits(component, WM8962_ANALOGUE_HP_0,
1914 WM8962_HP1L_ENA | WM8962_HP1R_ENA,
1915 WM8962_HP1L_ENA | WM8962_HP1R_ENA);
1916 udelay(20);
1917
1918 snd_soc_component_update_bits(component, WM8962_ANALOGUE_HP_0,
1919 WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY,
1920 WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY);
1921
1922 /* Start the DC servo */
1923 snd_soc_component_update_bits(component, WM8962_DC_SERVO_1,
1924 WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
1925 WM8962_HP1L_DCS_STARTUP |
1926 WM8962_HP1R_DCS_STARTUP,
1927 WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
1928 WM8962_HP1L_DCS_STARTUP |
1929 WM8962_HP1R_DCS_STARTUP);
1930
1931 /* Wait for it to complete, should be well under 100ms */
1932 timeout = 0;
1933 do {
1934 msleep(1);
1935 reg = snd_soc_component_read(component, WM8962_DC_SERVO_6);
1936 if (reg < 0) {
1937 dev_err(component->dev,
1938 "Failed to read DCS status: %d\n",
1939 reg);
1940 continue;
1941 }
1942 dev_dbg(component->dev, "DCS status: %x\n", reg);
1943 } while (++timeout < 200 && (reg & expected) != expected);
1944
1945 if ((reg & expected) != expected)
1946 dev_err(component->dev, "DC servo timed out\n");
1947 else
1948 dev_dbg(component->dev, "DC servo complete after %dms\n",
1949 timeout);
1950
1951 snd_soc_component_update_bits(component, WM8962_ANALOGUE_HP_0,
1952 WM8962_HP1L_ENA_OUTP |
1953 WM8962_HP1R_ENA_OUTP,
1954 WM8962_HP1L_ENA_OUTP |
1955 WM8962_HP1R_ENA_OUTP);
1956 udelay(20);
1957
1958 snd_soc_component_update_bits(component, WM8962_ANALOGUE_HP_0,
1959 WM8962_HP1L_RMV_SHORT |
1960 WM8962_HP1R_RMV_SHORT,
1961 WM8962_HP1L_RMV_SHORT |
1962 WM8962_HP1R_RMV_SHORT);
1963 break;
1964
1965 case SND_SOC_DAPM_PRE_PMD:
1966 snd_soc_component_update_bits(component, WM8962_ANALOGUE_HP_0,
1967 WM8962_HP1L_RMV_SHORT |
1968 WM8962_HP1R_RMV_SHORT, 0);
1969
1970 udelay(20);
1971
1972 snd_soc_component_update_bits(component, WM8962_DC_SERVO_1,
1973 WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
1974 WM8962_HP1L_DCS_STARTUP |
1975 WM8962_HP1R_DCS_STARTUP,
1976 0);
1977
1978 snd_soc_component_update_bits(component, WM8962_ANALOGUE_HP_0,
1979 WM8962_HP1L_ENA | WM8962_HP1R_ENA |
1980 WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY |
1981 WM8962_HP1L_ENA_OUTP |
1982 WM8962_HP1R_ENA_OUTP, 0);
1983
1984 break;
1985
1986 default:
1987 WARN(1, "Invalid event %d\n", event);
1988 return -EINVAL;
1989
1990 }
1991
1992 return 0;
1993}
1994
1995/* VU bits for the output PGAs only take effect while the PGA is powered */
1996static int out_pga_event(struct snd_soc_dapm_widget *w,
1997 struct snd_kcontrol *kcontrol, int event)
1998{
1999 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2000 int reg;
2001
2002 switch (w->shift) {
2003 case WM8962_HPOUTR_PGA_ENA_SHIFT:
2004 reg = WM8962_HPOUTR_VOLUME;
2005 break;
2006 case WM8962_HPOUTL_PGA_ENA_SHIFT:
2007 reg = WM8962_HPOUTL_VOLUME;
2008 break;
2009 case WM8962_SPKOUTR_PGA_ENA_SHIFT:
2010 reg = WM8962_SPKOUTR_VOLUME;
2011 break;
2012 case WM8962_SPKOUTL_PGA_ENA_SHIFT:
2013 reg = WM8962_SPKOUTL_VOLUME;
2014 break;
2015 default:
2016 WARN(1, "Invalid shift %d\n", w->shift);
2017 return -EINVAL;
2018 }
2019
2020 switch (event) {
2021 case SND_SOC_DAPM_POST_PMU:
2022 return snd_soc_component_write(component, reg,
2023 snd_soc_component_read(component, reg));
2024 default:
2025 WARN(1, "Invalid event %d\n", event);
2026 return -EINVAL;
2027 }
2028}
2029
2030static int dsp2_event(struct snd_soc_dapm_widget *w,
2031 struct snd_kcontrol *kcontrol, int event)
2032{
2033 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2034 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
2035
2036 switch (event) {
2037 case SND_SOC_DAPM_POST_PMU:
2038 if (wm8962->dsp2_ena)
2039 wm8962_dsp2_start(component);
2040 break;
2041
2042 case SND_SOC_DAPM_PRE_PMD:
2043 if (wm8962->dsp2_ena)
2044 wm8962_dsp2_stop(component);
2045 break;
2046
2047 default:
2048 WARN(1, "Invalid event %d\n", event);
2049 return -EINVAL;
2050 }
2051
2052 return 0;
2053}
2054
2055static const char *st_text[] = { "None", "Left", "Right" };
2056
2057static SOC_ENUM_SINGLE_DECL(str_enum,
2058 WM8962_DAC_DSP_MIXING_1, 2, st_text);
2059
2060static const struct snd_kcontrol_new str_mux =
2061 SOC_DAPM_ENUM("Right Sidetone", str_enum);
2062
2063static SOC_ENUM_SINGLE_DECL(stl_enum,
2064 WM8962_DAC_DSP_MIXING_2, 2, st_text);
2065
2066static const struct snd_kcontrol_new stl_mux =
2067 SOC_DAPM_ENUM("Left Sidetone", stl_enum);
2068
2069static const char *outmux_text[] = { "DAC", "Mixer" };
2070
2071static SOC_ENUM_SINGLE_DECL(spkoutr_enum,
2072 WM8962_SPEAKER_MIXER_2, 7, outmux_text);
2073
2074static const struct snd_kcontrol_new spkoutr_mux =
2075 SOC_DAPM_ENUM("SPKOUTR Mux", spkoutr_enum);
2076
2077static SOC_ENUM_SINGLE_DECL(spkoutl_enum,
2078 WM8962_SPEAKER_MIXER_1, 7, outmux_text);
2079
2080static const struct snd_kcontrol_new spkoutl_mux =
2081 SOC_DAPM_ENUM("SPKOUTL Mux", spkoutl_enum);
2082
2083static SOC_ENUM_SINGLE_DECL(hpoutr_enum,
2084 WM8962_HEADPHONE_MIXER_2, 7, outmux_text);
2085
2086static const struct snd_kcontrol_new hpoutr_mux =
2087 SOC_DAPM_ENUM("HPOUTR Mux", hpoutr_enum);
2088
2089static SOC_ENUM_SINGLE_DECL(hpoutl_enum,
2090 WM8962_HEADPHONE_MIXER_1, 7, outmux_text);
2091
2092static const struct snd_kcontrol_new hpoutl_mux =
2093 SOC_DAPM_ENUM("HPOUTL Mux", hpoutl_enum);
2094
2095static const char * const input_mode_text[] = { "Analog", "Digital" };
2096
2097static SOC_ENUM_SINGLE_VIRT_DECL(input_mode_enum, input_mode_text);
2098
2099static const struct snd_kcontrol_new input_mode_mux =
2100 SOC_DAPM_ENUM("Input Mode", input_mode_enum);
2101
2102static const struct snd_kcontrol_new inpgal[] = {
2103SOC_DAPM_SINGLE("IN1L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 3, 1, 0),
2104SOC_DAPM_SINGLE("IN2L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 2, 1, 0),
2105SOC_DAPM_SINGLE("IN3L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 1, 1, 0),
2106SOC_DAPM_SINGLE("IN4L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 0, 1, 0),
2107};
2108
2109static const struct snd_kcontrol_new inpgar[] = {
2110SOC_DAPM_SINGLE("IN1R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 3, 1, 0),
2111SOC_DAPM_SINGLE("IN2R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 2, 1, 0),
2112SOC_DAPM_SINGLE("IN3R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 1, 1, 0),
2113SOC_DAPM_SINGLE("IN4R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 0, 1, 0),
2114};
2115
2116static const struct snd_kcontrol_new mixinl[] = {
2117SOC_DAPM_SINGLE("IN2L Switch", WM8962_INPUT_MIXER_CONTROL_2, 5, 1, 0),
2118SOC_DAPM_SINGLE("IN3L Switch", WM8962_INPUT_MIXER_CONTROL_2, 4, 1, 0),
2119SOC_DAPM_SINGLE("PGA Switch", WM8962_INPUT_MIXER_CONTROL_2, 3, 1, 0),
2120};
2121
2122static const struct snd_kcontrol_new mixinr[] = {
2123SOC_DAPM_SINGLE("IN2R Switch", WM8962_INPUT_MIXER_CONTROL_2, 2, 1, 0),
2124SOC_DAPM_SINGLE("IN3R Switch", WM8962_INPUT_MIXER_CONTROL_2, 1, 1, 0),
2125SOC_DAPM_SINGLE("PGA Switch", WM8962_INPUT_MIXER_CONTROL_2, 0, 1, 0),
2126};
2127
2128static const struct snd_kcontrol_new hpmixl[] = {
2129SOC_DAPM_SINGLE("DACL Switch", WM8962_HEADPHONE_MIXER_1, 5, 1, 0),
2130SOC_DAPM_SINGLE("DACR Switch", WM8962_HEADPHONE_MIXER_1, 4, 1, 0),
2131SOC_DAPM_SINGLE("MIXINL Switch", WM8962_HEADPHONE_MIXER_1, 3, 1, 0),
2132SOC_DAPM_SINGLE("MIXINR Switch", WM8962_HEADPHONE_MIXER_1, 2, 1, 0),
2133SOC_DAPM_SINGLE("IN4L Switch", WM8962_HEADPHONE_MIXER_1, 1, 1, 0),
2134SOC_DAPM_SINGLE("IN4R Switch", WM8962_HEADPHONE_MIXER_1, 0, 1, 0),
2135};
2136
2137static const struct snd_kcontrol_new hpmixr[] = {
2138SOC_DAPM_SINGLE("DACL Switch", WM8962_HEADPHONE_MIXER_2, 5, 1, 0),
2139SOC_DAPM_SINGLE("DACR Switch", WM8962_HEADPHONE_MIXER_2, 4, 1, 0),
2140SOC_DAPM_SINGLE("MIXINL Switch", WM8962_HEADPHONE_MIXER_2, 3, 1, 0),
2141SOC_DAPM_SINGLE("MIXINR Switch", WM8962_HEADPHONE_MIXER_2, 2, 1, 0),
2142SOC_DAPM_SINGLE("IN4L Switch", WM8962_HEADPHONE_MIXER_2, 1, 1, 0),
2143SOC_DAPM_SINGLE("IN4R Switch", WM8962_HEADPHONE_MIXER_2, 0, 1, 0),
2144};
2145
2146static const struct snd_kcontrol_new spkmixl[] = {
2147SOC_DAPM_SINGLE("DACL Switch", WM8962_SPEAKER_MIXER_1, 5, 1, 0),
2148SOC_DAPM_SINGLE("DACR Switch", WM8962_SPEAKER_MIXER_1, 4, 1, 0),
2149SOC_DAPM_SINGLE("MIXINL Switch", WM8962_SPEAKER_MIXER_1, 3, 1, 0),
2150SOC_DAPM_SINGLE("MIXINR Switch", WM8962_SPEAKER_MIXER_1, 2, 1, 0),
2151SOC_DAPM_SINGLE("IN4L Switch", WM8962_SPEAKER_MIXER_1, 1, 1, 0),
2152SOC_DAPM_SINGLE("IN4R Switch", WM8962_SPEAKER_MIXER_1, 0, 1, 0),
2153};
2154
2155static const struct snd_kcontrol_new spkmixr[] = {
2156SOC_DAPM_SINGLE("DACL Switch", WM8962_SPEAKER_MIXER_2, 5, 1, 0),
2157SOC_DAPM_SINGLE("DACR Switch", WM8962_SPEAKER_MIXER_2, 4, 1, 0),
2158SOC_DAPM_SINGLE("MIXINL Switch", WM8962_SPEAKER_MIXER_2, 3, 1, 0),
2159SOC_DAPM_SINGLE("MIXINR Switch", WM8962_SPEAKER_MIXER_2, 2, 1, 0),
2160SOC_DAPM_SINGLE("IN4L Switch", WM8962_SPEAKER_MIXER_2, 1, 1, 0),
2161SOC_DAPM_SINGLE("IN4R Switch", WM8962_SPEAKER_MIXER_2, 0, 1, 0),
2162};
2163
2164static const struct snd_soc_dapm_widget wm8962_dapm_widgets[] = {
2165SND_SOC_DAPM_INPUT("IN1L"),
2166SND_SOC_DAPM_INPUT("IN1R"),
2167SND_SOC_DAPM_INPUT("IN2L"),
2168SND_SOC_DAPM_INPUT("IN2R"),
2169SND_SOC_DAPM_INPUT("IN3L"),
2170SND_SOC_DAPM_INPUT("IN3R"),
2171SND_SOC_DAPM_INPUT("IN4L"),
2172SND_SOC_DAPM_INPUT("IN4R"),
2173SND_SOC_DAPM_SIGGEN("Beep"),
2174SND_SOC_DAPM_INPUT("DMICDAT"),
2175
2176SND_SOC_DAPM_SUPPLY("MICBIAS", WM8962_PWR_MGMT_1, 1, 0, NULL, 0),
2177
2178SND_SOC_DAPM_SUPPLY("Class G", WM8962_CHARGE_PUMP_B, 0, 1, NULL, 0),
2179SND_SOC_DAPM_SUPPLY("SYSCLK", WM8962_CLOCKING2, 5, 0, NULL, 0),
2180SND_SOC_DAPM_SUPPLY("Charge Pump", WM8962_CHARGE_PUMP_1, 0, 0, cp_event,
2181 SND_SOC_DAPM_POST_PMU),
2182SND_SOC_DAPM_SUPPLY("TOCLK", WM8962_ADDITIONAL_CONTROL_1, 0, 0, NULL, 0),
2183SND_SOC_DAPM_SUPPLY_S("DSP2", 1, WM8962_DSP2_POWER_MANAGEMENT,
2184 WM8962_DSP2_ENA_SHIFT, 0, dsp2_event,
2185 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2186SND_SOC_DAPM_SUPPLY("TEMP_HP", SND_SOC_NOPM, 0, 0, tp_event,
2187 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
2188SND_SOC_DAPM_SUPPLY("TEMP_SPK", SND_SOC_NOPM, 0, 0, tp_event,
2189 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
2190
2191SND_SOC_DAPM_MIXER("INPGAL", WM8962_LEFT_INPUT_PGA_CONTROL, 4, 0,
2192 inpgal, ARRAY_SIZE(inpgal)),
2193SND_SOC_DAPM_MIXER("INPGAR", WM8962_RIGHT_INPUT_PGA_CONTROL, 4, 0,
2194 inpgar, ARRAY_SIZE(inpgar)),
2195SND_SOC_DAPM_MIXER("MIXINL", WM8962_PWR_MGMT_1, 5, 0,
2196 mixinl, ARRAY_SIZE(mixinl)),
2197SND_SOC_DAPM_MIXER("MIXINR", WM8962_PWR_MGMT_1, 4, 0,
2198 mixinr, ARRAY_SIZE(mixinr)),
2199
2200SND_SOC_DAPM_AIF_IN("DMIC_ENA", NULL, 0, WM8962_PWR_MGMT_1, 10, 0),
2201
2202SND_SOC_DAPM_MUX("Input Mode L", SND_SOC_NOPM, 0, 0, &input_mode_mux),
2203SND_SOC_DAPM_MUX("Input Mode R", SND_SOC_NOPM, 0, 0, &input_mode_mux),
2204
2205SND_SOC_DAPM_ADC("ADCL", "Capture", WM8962_PWR_MGMT_1, 3, 0),
2206SND_SOC_DAPM_ADC("ADCR", "Capture", WM8962_PWR_MGMT_1, 2, 0),
2207
2208SND_SOC_DAPM_MUX("STL", SND_SOC_NOPM, 0, 0, &stl_mux),
2209SND_SOC_DAPM_MUX("STR", SND_SOC_NOPM, 0, 0, &str_mux),
2210
2211SND_SOC_DAPM_DAC("DACL", "Playback", WM8962_PWR_MGMT_2, 8, 0),
2212SND_SOC_DAPM_DAC("DACR", "Playback", WM8962_PWR_MGMT_2, 7, 0),
2213
2214SND_SOC_DAPM_PGA("Left Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
2215SND_SOC_DAPM_PGA("Right Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
2216
2217SND_SOC_DAPM_MIXER("HPMIXL", WM8962_MIXER_ENABLES, 3, 0,
2218 hpmixl, ARRAY_SIZE(hpmixl)),
2219SND_SOC_DAPM_MIXER("HPMIXR", WM8962_MIXER_ENABLES, 2, 0,
2220 hpmixr, ARRAY_SIZE(hpmixr)),
2221
2222SND_SOC_DAPM_MUX_E("HPOUTL PGA", WM8962_PWR_MGMT_2, 6, 0, &hpoutl_mux,
2223 out_pga_event, SND_SOC_DAPM_POST_PMU),
2224SND_SOC_DAPM_MUX_E("HPOUTR PGA", WM8962_PWR_MGMT_2, 5, 0, &hpoutr_mux,
2225 out_pga_event, SND_SOC_DAPM_POST_PMU),
2226
2227SND_SOC_DAPM_PGA_E("HPOUT", SND_SOC_NOPM, 0, 0, NULL, 0, hp_event,
2228 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2229
2230SND_SOC_DAPM_OUTPUT("HPOUTL"),
2231SND_SOC_DAPM_OUTPUT("HPOUTR"),
2232
2233SND_SOC_DAPM_PGA("SPKOUTL Output", WM8962_CLASS_D_CONTROL_1, 6, 0, NULL, 0),
2234SND_SOC_DAPM_PGA("SPKOUTR Output", WM8962_CLASS_D_CONTROL_1, 7, 0, NULL, 0),
2235};
2236
2237static const struct snd_soc_dapm_widget wm8962_dapm_spk_mono_widgets[] = {
2238SND_SOC_DAPM_MIXER("Speaker Mixer", WM8962_MIXER_ENABLES, 1, 0,
2239 spkmixl, ARRAY_SIZE(spkmixl)),
2240SND_SOC_DAPM_MUX_E("Speaker PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux,
2241 out_pga_event, SND_SOC_DAPM_POST_PMU),
2242SND_SOC_DAPM_OUTPUT("SPKOUT"),
2243};
2244
2245static const struct snd_soc_dapm_widget wm8962_dapm_spk_stereo_widgets[] = {
2246SND_SOC_DAPM_MIXER("SPKOUTL Mixer", WM8962_MIXER_ENABLES, 1, 0,
2247 spkmixl, ARRAY_SIZE(spkmixl)),
2248SND_SOC_DAPM_MIXER("SPKOUTR Mixer", WM8962_MIXER_ENABLES, 0, 0,
2249 spkmixr, ARRAY_SIZE(spkmixr)),
2250
2251SND_SOC_DAPM_MUX_E("SPKOUTL PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux,
2252 out_pga_event, SND_SOC_DAPM_POST_PMU),
2253SND_SOC_DAPM_MUX_E("SPKOUTR PGA", WM8962_PWR_MGMT_2, 3, 0, &spkoutr_mux,
2254 out_pga_event, SND_SOC_DAPM_POST_PMU),
2255
2256SND_SOC_DAPM_OUTPUT("SPKOUTL"),
2257SND_SOC_DAPM_OUTPUT("SPKOUTR"),
2258};
2259
2260static const struct snd_soc_dapm_route wm8962_intercon[] = {
2261 { "INPGAL", "IN1L Switch", "IN1L" },
2262 { "INPGAL", "IN2L Switch", "IN2L" },
2263 { "INPGAL", "IN3L Switch", "IN3L" },
2264 { "INPGAL", "IN4L Switch", "IN4L" },
2265
2266 { "INPGAR", "IN1R Switch", "IN1R" },
2267 { "INPGAR", "IN2R Switch", "IN2R" },
2268 { "INPGAR", "IN3R Switch", "IN3R" },
2269 { "INPGAR", "IN4R Switch", "IN4R" },
2270
2271 { "MIXINL", "IN2L Switch", "IN2L" },
2272 { "MIXINL", "IN3L Switch", "IN3L" },
2273 { "MIXINL", "PGA Switch", "INPGAL" },
2274
2275 { "MIXINR", "IN2R Switch", "IN2R" },
2276 { "MIXINR", "IN3R Switch", "IN3R" },
2277 { "MIXINR", "PGA Switch", "INPGAR" },
2278
2279 { "MICBIAS", NULL, "SYSCLK" },
2280
2281 { "DMIC_ENA", NULL, "DMICDAT" },
2282
2283 { "Input Mode L", "Analog", "MIXINL" },
2284 { "Input Mode L", "Digital", "DMIC_ENA" },
2285 { "Input Mode R", "Analog", "MIXINR" },
2286 { "Input Mode R", "Digital", "DMIC_ENA" },
2287
2288 { "ADCL", NULL, "SYSCLK" },
2289 { "ADCL", NULL, "TOCLK" },
2290 { "ADCL", NULL, "Input Mode L" },
2291 { "ADCL", NULL, "DSP2" },
2292
2293 { "ADCR", NULL, "SYSCLK" },
2294 { "ADCR", NULL, "TOCLK" },
2295 { "ADCR", NULL, "Input Mode R" },
2296 { "ADCR", NULL, "DSP2" },
2297
2298 { "STL", "Left", "ADCL" },
2299 { "STL", "Right", "ADCR" },
2300 { "STL", NULL, "Class G" },
2301
2302 { "STR", "Left", "ADCL" },
2303 { "STR", "Right", "ADCR" },
2304 { "STR", NULL, "Class G" },
2305
2306 { "DACL", NULL, "SYSCLK" },
2307 { "DACL", NULL, "TOCLK" },
2308 { "DACL", NULL, "Beep" },
2309 { "DACL", NULL, "STL" },
2310 { "DACL", NULL, "DSP2" },
2311
2312 { "DACR", NULL, "SYSCLK" },
2313 { "DACR", NULL, "TOCLK" },
2314 { "DACR", NULL, "Beep" },
2315 { "DACR", NULL, "STR" },
2316 { "DACR", NULL, "DSP2" },
2317
2318 { "HPMIXL", "IN4L Switch", "IN4L" },
2319 { "HPMIXL", "IN4R Switch", "IN4R" },
2320 { "HPMIXL", "DACL Switch", "DACL" },
2321 { "HPMIXL", "DACR Switch", "DACR" },
2322 { "HPMIXL", "MIXINL Switch", "MIXINL" },
2323 { "HPMIXL", "MIXINR Switch", "MIXINR" },
2324
2325 { "HPMIXR", "IN4L Switch", "IN4L" },
2326 { "HPMIXR", "IN4R Switch", "IN4R" },
2327 { "HPMIXR", "DACL Switch", "DACL" },
2328 { "HPMIXR", "DACR Switch", "DACR" },
2329 { "HPMIXR", "MIXINL Switch", "MIXINL" },
2330 { "HPMIXR", "MIXINR Switch", "MIXINR" },
2331
2332 { "Left Bypass", NULL, "HPMIXL" },
2333 { "Left Bypass", NULL, "Class G" },
2334
2335 { "Right Bypass", NULL, "HPMIXR" },
2336 { "Right Bypass", NULL, "Class G" },
2337
2338 { "HPOUTL PGA", "Mixer", "Left Bypass" },
2339 { "HPOUTL PGA", "DAC", "DACL" },
2340
2341 { "HPOUTR PGA", "Mixer", "Right Bypass" },
2342 { "HPOUTR PGA", "DAC", "DACR" },
2343
2344 { "HPOUT", NULL, "HPOUTL PGA" },
2345 { "HPOUT", NULL, "HPOUTR PGA" },
2346 { "HPOUT", NULL, "Charge Pump" },
2347 { "HPOUT", NULL, "SYSCLK" },
2348 { "HPOUT", NULL, "TOCLK" },
2349
2350 { "HPOUTL", NULL, "HPOUT" },
2351 { "HPOUTR", NULL, "HPOUT" },
2352
2353 { "HPOUTL", NULL, "TEMP_HP" },
2354 { "HPOUTR", NULL, "TEMP_HP" },
2355};
2356
2357static const struct snd_soc_dapm_route wm8962_spk_mono_intercon[] = {
2358 { "Speaker Mixer", "IN4L Switch", "IN4L" },
2359 { "Speaker Mixer", "IN4R Switch", "IN4R" },
2360 { "Speaker Mixer", "DACL Switch", "DACL" },
2361 { "Speaker Mixer", "DACR Switch", "DACR" },
2362 { "Speaker Mixer", "MIXINL Switch", "MIXINL" },
2363 { "Speaker Mixer", "MIXINR Switch", "MIXINR" },
2364
2365 { "Speaker PGA", "Mixer", "Speaker Mixer" },
2366 { "Speaker PGA", "DAC", "DACL" },
2367
2368 { "SPKOUTL Output", NULL, "Speaker PGA" },
2369 { "SPKOUTL Output", NULL, "SYSCLK" },
2370 { "SPKOUTL Output", NULL, "TOCLK" },
2371 { "SPKOUTL Output", NULL, "TEMP_SPK" },
2372
2373 { "SPKOUTR Output", NULL, "Speaker PGA" },
2374 { "SPKOUTR Output", NULL, "SYSCLK" },
2375 { "SPKOUTR Output", NULL, "TOCLK" },
2376 { "SPKOUTR Output", NULL, "TEMP_SPK" },
2377
2378 { "SPKOUT", NULL, "SPKOUTL Output" },
2379 { "SPKOUT", NULL, "SPKOUTR Output" },
2380};
2381
2382static const struct snd_soc_dapm_route wm8962_spk_stereo_intercon[] = {
2383 { "SPKOUTL Mixer", "IN4L Switch", "IN4L" },
2384 { "SPKOUTL Mixer", "IN4R Switch", "IN4R" },
2385 { "SPKOUTL Mixer", "DACL Switch", "DACL" },
2386 { "SPKOUTL Mixer", "DACR Switch", "DACR" },
2387 { "SPKOUTL Mixer", "MIXINL Switch", "MIXINL" },
2388 { "SPKOUTL Mixer", "MIXINR Switch", "MIXINR" },
2389
2390 { "SPKOUTR Mixer", "IN4L Switch", "IN4L" },
2391 { "SPKOUTR Mixer", "IN4R Switch", "IN4R" },
2392 { "SPKOUTR Mixer", "DACL Switch", "DACL" },
2393 { "SPKOUTR Mixer", "DACR Switch", "DACR" },
2394 { "SPKOUTR Mixer", "MIXINL Switch", "MIXINL" },
2395 { "SPKOUTR Mixer", "MIXINR Switch", "MIXINR" },
2396
2397 { "SPKOUTL PGA", "Mixer", "SPKOUTL Mixer" },
2398 { "SPKOUTL PGA", "DAC", "DACL" },
2399
2400 { "SPKOUTR PGA", "Mixer", "SPKOUTR Mixer" },
2401 { "SPKOUTR PGA", "DAC", "DACR" },
2402
2403 { "SPKOUTL Output", NULL, "SPKOUTL PGA" },
2404 { "SPKOUTL Output", NULL, "SYSCLK" },
2405 { "SPKOUTL Output", NULL, "TOCLK" },
2406 { "SPKOUTL Output", NULL, "TEMP_SPK" },
2407
2408 { "SPKOUTR Output", NULL, "SPKOUTR PGA" },
2409 { "SPKOUTR Output", NULL, "SYSCLK" },
2410 { "SPKOUTR Output", NULL, "TOCLK" },
2411 { "SPKOUTR Output", NULL, "TEMP_SPK" },
2412
2413 { "SPKOUTL", NULL, "SPKOUTL Output" },
2414 { "SPKOUTR", NULL, "SPKOUTR Output" },
2415};
2416
2417static int wm8962_add_widgets(struct snd_soc_component *component)
2418{
2419 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
2420 struct wm8962_pdata *pdata = &wm8962->pdata;
2421 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
2422
2423 snd_soc_add_component_controls(component, wm8962_snd_controls,
2424 ARRAY_SIZE(wm8962_snd_controls));
2425 if (pdata->spk_mono)
2426 snd_soc_add_component_controls(component, wm8962_spk_mono_controls,
2427 ARRAY_SIZE(wm8962_spk_mono_controls));
2428 else
2429 snd_soc_add_component_controls(component, wm8962_spk_stereo_controls,
2430 ARRAY_SIZE(wm8962_spk_stereo_controls));
2431
2432
2433 snd_soc_dapm_new_controls(dapm, wm8962_dapm_widgets,
2434 ARRAY_SIZE(wm8962_dapm_widgets));
2435 if (pdata->spk_mono)
2436 snd_soc_dapm_new_controls(dapm, wm8962_dapm_spk_mono_widgets,
2437 ARRAY_SIZE(wm8962_dapm_spk_mono_widgets));
2438 else
2439 snd_soc_dapm_new_controls(dapm, wm8962_dapm_spk_stereo_widgets,
2440 ARRAY_SIZE(wm8962_dapm_spk_stereo_widgets));
2441
2442 snd_soc_dapm_add_routes(dapm, wm8962_intercon,
2443 ARRAY_SIZE(wm8962_intercon));
2444 if (pdata->spk_mono)
2445 snd_soc_dapm_add_routes(dapm, wm8962_spk_mono_intercon,
2446 ARRAY_SIZE(wm8962_spk_mono_intercon));
2447 else
2448 snd_soc_dapm_add_routes(dapm, wm8962_spk_stereo_intercon,
2449 ARRAY_SIZE(wm8962_spk_stereo_intercon));
2450
2451
2452 snd_soc_dapm_disable_pin(dapm, "Beep");
2453
2454 return 0;
2455}
2456
2457/* -1 for reserved values */
2458static const int bclk_divs[] = {
2459 1, -1, 2, 3, 4, -1, 6, 8, -1, 12, 16, 24, -1, 32, 32, 32
2460};
2461
2462static const int sysclk_rates[] = {
2463 64, 128, 192, 256, 384, 512, 768, 1024, 1408, 1536, 3072, 6144
2464};
2465
2466static void wm8962_configure_bclk(struct snd_soc_component *component)
2467{
2468 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
2469 int best, min_diff, diff;
2470 int dspclk, i;
2471 int clocking2 = 0;
2472 int clocking4 = 0;
2473 int aif2 = 0;
2474
2475 if (!wm8962->sysclk_rate) {
2476 dev_dbg(component->dev, "No SYSCLK configured\n");
2477 return;
2478 }
2479
2480 if (!wm8962->bclk || !wm8962->lrclk) {
2481 dev_dbg(component->dev, "No audio clocks configured\n");
2482 return;
2483 }
2484
2485 for (i = 0; i < ARRAY_SIZE(sysclk_rates); i++) {
2486 if (sysclk_rates[i] == wm8962->sysclk_rate / wm8962->lrclk) {
2487 clocking4 |= i << WM8962_SYSCLK_RATE_SHIFT;
2488 break;
2489 }
2490 }
2491
2492 if (i == ARRAY_SIZE(sysclk_rates)) {
2493 dev_err(component->dev, "Unsupported sysclk ratio %d\n",
2494 wm8962->sysclk_rate / wm8962->lrclk);
2495 return;
2496 }
2497
2498 dev_dbg(component->dev, "Selected sysclk ratio %d\n", sysclk_rates[i]);
2499
2500 snd_soc_component_update_bits(component, WM8962_CLOCKING_4,
2501 WM8962_SYSCLK_RATE_MASK, clocking4);
2502
2503 /* DSPCLK_DIV can be only generated correctly after enabling SYSCLK.
2504 * So we here provisionally enable it and then disable it afterward
2505 * if current bias_level hasn't reached SND_SOC_BIAS_ON.
2506 */
2507 if (snd_soc_component_get_bias_level(component) != SND_SOC_BIAS_ON)
2508 snd_soc_component_update_bits(component, WM8962_CLOCKING2,
2509 WM8962_SYSCLK_ENA_MASK, WM8962_SYSCLK_ENA);
2510
2511 /* DSPCLK_DIV field in WM8962_CLOCKING1 register is used to generate
2512 * correct frequency of LRCLK and BCLK. Sometimes the read-only value
2513 * can't be updated timely after enabling SYSCLK. This results in wrong
2514 * calculation values. Delay is introduced here to wait for newest
2515 * value from register. The time of the delay should be at least
2516 * 500~1000us according to test.
2517 */
2518 usleep_range(500, 1000);
2519 dspclk = snd_soc_component_read(component, WM8962_CLOCKING1);
2520
2521 if (snd_soc_component_get_bias_level(component) != SND_SOC_BIAS_ON)
2522 snd_soc_component_update_bits(component, WM8962_CLOCKING2,
2523 WM8962_SYSCLK_ENA_MASK, 0);
2524
2525 if (dspclk < 0) {
2526 dev_err(component->dev, "Failed to read DSPCLK: %d\n", dspclk);
2527 return;
2528 }
2529
2530 dspclk = (dspclk & WM8962_DSPCLK_DIV_MASK) >> WM8962_DSPCLK_DIV_SHIFT;
2531 switch (dspclk) {
2532 case 0:
2533 dspclk = wm8962->sysclk_rate;
2534 break;
2535 case 1:
2536 dspclk = wm8962->sysclk_rate / 2;
2537 break;
2538 case 2:
2539 dspclk = wm8962->sysclk_rate / 4;
2540 break;
2541 default:
2542 dev_warn(component->dev, "Unknown DSPCLK divisor read back\n");
2543 dspclk = wm8962->sysclk_rate;
2544 }
2545
2546 dev_dbg(component->dev, "DSPCLK is %dHz, BCLK %d\n", dspclk, wm8962->bclk);
2547
2548 /* Search a proper bclk, not exact match. */
2549 best = 0;
2550 min_diff = INT_MAX;
2551 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2552 if (bclk_divs[i] < 0)
2553 continue;
2554
2555 diff = (dspclk / bclk_divs[i]) - wm8962->bclk;
2556 if (diff < 0) /* Table is sorted */
2557 break;
2558 if (diff < min_diff) {
2559 best = i;
2560 min_diff = diff;
2561 }
2562 }
2563 wm8962->bclk = dspclk / bclk_divs[best];
2564 clocking2 |= best;
2565 dev_dbg(component->dev, "Selected BCLK_DIV %d for %dHz\n",
2566 bclk_divs[best], wm8962->bclk);
2567
2568 aif2 |= wm8962->bclk / wm8962->lrclk;
2569 dev_dbg(component->dev, "Selected LRCLK divisor %d for %dHz\n",
2570 wm8962->bclk / wm8962->lrclk, wm8962->lrclk);
2571
2572 snd_soc_component_update_bits(component, WM8962_CLOCKING2,
2573 WM8962_BCLK_DIV_MASK, clocking2);
2574 snd_soc_component_update_bits(component, WM8962_AUDIO_INTERFACE_2,
2575 WM8962_AIF_RATE_MASK, aif2);
2576}
2577
2578static int wm8962_set_bias_level(struct snd_soc_component *component,
2579 enum snd_soc_bias_level level)
2580{
2581 switch (level) {
2582 case SND_SOC_BIAS_ON:
2583 break;
2584
2585 case SND_SOC_BIAS_PREPARE:
2586 /* VMID 2*50k */
2587 snd_soc_component_update_bits(component, WM8962_PWR_MGMT_1,
2588 WM8962_VMID_SEL_MASK, 0x80);
2589
2590 wm8962_configure_bclk(component);
2591 break;
2592
2593 case SND_SOC_BIAS_STANDBY:
2594 /* VMID 2*250k */
2595 snd_soc_component_update_bits(component, WM8962_PWR_MGMT_1,
2596 WM8962_VMID_SEL_MASK, 0x100);
2597
2598 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
2599 msleep(100);
2600 break;
2601
2602 case SND_SOC_BIAS_OFF:
2603 break;
2604 }
2605
2606 return 0;
2607}
2608
2609static const struct {
2610 int rate;
2611 int reg;
2612} sr_vals[] = {
2613 { 48000, 0 },
2614 { 44100, 0 },
2615 { 32000, 1 },
2616 { 22050, 2 },
2617 { 24000, 2 },
2618 { 16000, 3 },
2619 { 11025, 4 },
2620 { 12000, 4 },
2621 { 8000, 5 },
2622 { 88200, 6 },
2623 { 96000, 6 },
2624};
2625
2626static int wm8962_hw_params(struct snd_pcm_substream *substream,
2627 struct snd_pcm_hw_params *params,
2628 struct snd_soc_dai *dai)
2629{
2630 struct snd_soc_component *component = dai->component;
2631 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
2632 int i;
2633 int aif0 = 0;
2634 int adctl3 = 0;
2635
2636 wm8962->bclk = snd_soc_params_to_bclk(params);
2637 if (params_channels(params) == 1)
2638 wm8962->bclk *= 2;
2639
2640 wm8962->lrclk = params_rate(params);
2641
2642 for (i = 0; i < ARRAY_SIZE(sr_vals); i++) {
2643 if (sr_vals[i].rate == wm8962->lrclk) {
2644 adctl3 |= sr_vals[i].reg;
2645 break;
2646 }
2647 }
2648 if (i == ARRAY_SIZE(sr_vals)) {
2649 dev_err(component->dev, "Unsupported rate %dHz\n", wm8962->lrclk);
2650 return -EINVAL;
2651 }
2652
2653 if (wm8962->lrclk % 8000 == 0)
2654 adctl3 |= WM8962_SAMPLE_RATE_INT_MODE;
2655
2656 switch (params_width(params)) {
2657 case 16:
2658 break;
2659 case 20:
2660 aif0 |= 0x4;
2661 break;
2662 case 24:
2663 aif0 |= 0x8;
2664 break;
2665 case 32:
2666 aif0 |= 0xc;
2667 break;
2668 default:
2669 return -EINVAL;
2670 }
2671
2672 snd_soc_component_update_bits(component, WM8962_AUDIO_INTERFACE_0,
2673 WM8962_WL_MASK, aif0);
2674 snd_soc_component_update_bits(component, WM8962_ADDITIONAL_CONTROL_3,
2675 WM8962_SAMPLE_RATE_INT_MODE |
2676 WM8962_SAMPLE_RATE_MASK, adctl3);
2677
2678 dev_dbg(component->dev, "hw_params set BCLK %dHz LRCLK %dHz\n",
2679 wm8962->bclk, wm8962->lrclk);
2680
2681 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_ON)
2682 wm8962_configure_bclk(component);
2683
2684 return 0;
2685}
2686
2687static int wm8962_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
2688 unsigned int freq, int dir)
2689{
2690 struct snd_soc_component *component = dai->component;
2691 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
2692 int src;
2693
2694 switch (clk_id) {
2695 case WM8962_SYSCLK_MCLK:
2696 wm8962->sysclk = WM8962_SYSCLK_MCLK;
2697 src = 0;
2698 break;
2699 case WM8962_SYSCLK_FLL:
2700 wm8962->sysclk = WM8962_SYSCLK_FLL;
2701 src = 1 << WM8962_SYSCLK_SRC_SHIFT;
2702 break;
2703 default:
2704 return -EINVAL;
2705 }
2706
2707 snd_soc_component_update_bits(component, WM8962_CLOCKING2, WM8962_SYSCLK_SRC_MASK,
2708 src);
2709
2710 wm8962->sysclk_rate = freq;
2711
2712 return 0;
2713}
2714
2715static int wm8962_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2716{
2717 struct snd_soc_component *component = dai->component;
2718 int aif0 = 0;
2719
2720 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2721 case SND_SOC_DAIFMT_DSP_B:
2722 aif0 |= WM8962_LRCLK_INV | 3;
2723 fallthrough;
2724 case SND_SOC_DAIFMT_DSP_A:
2725 aif0 |= 3;
2726
2727 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2728 case SND_SOC_DAIFMT_NB_NF:
2729 case SND_SOC_DAIFMT_IB_NF:
2730 break;
2731 default:
2732 return -EINVAL;
2733 }
2734 break;
2735
2736 case SND_SOC_DAIFMT_RIGHT_J:
2737 break;
2738 case SND_SOC_DAIFMT_LEFT_J:
2739 aif0 |= 1;
2740 break;
2741 case SND_SOC_DAIFMT_I2S:
2742 aif0 |= 2;
2743 break;
2744 default:
2745 return -EINVAL;
2746 }
2747
2748 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2749 case SND_SOC_DAIFMT_NB_NF:
2750 break;
2751 case SND_SOC_DAIFMT_IB_NF:
2752 aif0 |= WM8962_BCLK_INV;
2753 break;
2754 case SND_SOC_DAIFMT_NB_IF:
2755 aif0 |= WM8962_LRCLK_INV;
2756 break;
2757 case SND_SOC_DAIFMT_IB_IF:
2758 aif0 |= WM8962_BCLK_INV | WM8962_LRCLK_INV;
2759 break;
2760 default:
2761 return -EINVAL;
2762 }
2763
2764 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2765 case SND_SOC_DAIFMT_CBM_CFM:
2766 aif0 |= WM8962_MSTR;
2767 break;
2768 case SND_SOC_DAIFMT_CBS_CFS:
2769 break;
2770 default:
2771 return -EINVAL;
2772 }
2773
2774 snd_soc_component_update_bits(component, WM8962_AUDIO_INTERFACE_0,
2775 WM8962_FMT_MASK | WM8962_BCLK_INV | WM8962_MSTR |
2776 WM8962_LRCLK_INV, aif0);
2777
2778 return 0;
2779}
2780
2781struct _fll_div {
2782 u16 fll_fratio;
2783 u16 fll_outdiv;
2784 u16 fll_refclk_div;
2785 u16 n;
2786 u16 theta;
2787 u16 lambda;
2788};
2789
2790/* The size in bits of the FLL divide multiplied by 10
2791 * to allow rounding later */
2792#define FIXED_FLL_SIZE ((1 << 16) * 10)
2793
2794static struct {
2795 unsigned int min;
2796 unsigned int max;
2797 u16 fll_fratio;
2798 int ratio;
2799} fll_fratios[] = {
2800 { 0, 64000, 4, 16 },
2801 { 64000, 128000, 3, 8 },
2802 { 128000, 256000, 2, 4 },
2803 { 256000, 1000000, 1, 2 },
2804 { 1000000, 13500000, 0, 1 },
2805};
2806
2807static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
2808 unsigned int Fout)
2809{
2810 unsigned int target;
2811 unsigned int div;
2812 unsigned int fratio, gcd_fll;
2813 int i;
2814
2815 /* Fref must be <=13.5MHz */
2816 div = 1;
2817 fll_div->fll_refclk_div = 0;
2818 while ((Fref / div) > 13500000) {
2819 div *= 2;
2820 fll_div->fll_refclk_div++;
2821
2822 if (div > 4) {
2823 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
2824 Fref);
2825 return -EINVAL;
2826 }
2827 }
2828
2829 pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout);
2830
2831 /* Apply the division for our remaining calculations */
2832 Fref /= div;
2833
2834 /* Fvco should be 90-100MHz; don't check the upper bound */
2835 div = 2;
2836 while (Fout * div < 90000000) {
2837 div++;
2838 if (div > 64) {
2839 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
2840 Fout);
2841 return -EINVAL;
2842 }
2843 }
2844 target = Fout * div;
2845 fll_div->fll_outdiv = div - 1;
2846
2847 pr_debug("FLL Fvco=%dHz\n", target);
2848
2849 /* Find an appropriate FLL_FRATIO and factor it out of the target */
2850 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
2851 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
2852 fll_div->fll_fratio = fll_fratios[i].fll_fratio;
2853 fratio = fll_fratios[i].ratio;
2854 break;
2855 }
2856 }
2857 if (i == ARRAY_SIZE(fll_fratios)) {
2858 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
2859 return -EINVAL;
2860 }
2861
2862 fll_div->n = target / (fratio * Fref);
2863
2864 if (target % Fref == 0) {
2865 fll_div->theta = 0;
2866 fll_div->lambda = 1;
2867 } else {
2868 gcd_fll = gcd(target, fratio * Fref);
2869
2870 fll_div->theta = (target - (fll_div->n * fratio * Fref))
2871 / gcd_fll;
2872 fll_div->lambda = (fratio * Fref) / gcd_fll;
2873 }
2874
2875 pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
2876 fll_div->n, fll_div->theta, fll_div->lambda);
2877 pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
2878 fll_div->fll_fratio, fll_div->fll_outdiv,
2879 fll_div->fll_refclk_div);
2880
2881 return 0;
2882}
2883
2884static int wm8962_set_fll(struct snd_soc_component *component, int fll_id, int source,
2885 unsigned int Fref, unsigned int Fout)
2886{
2887 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
2888 struct _fll_div fll_div;
2889 unsigned long time_left;
2890 int ret;
2891 int fll1 = 0;
2892
2893 /* Any change? */
2894 if (source == wm8962->fll_src && Fref == wm8962->fll_fref &&
2895 Fout == wm8962->fll_fout)
2896 return 0;
2897
2898 if (Fout == 0) {
2899 dev_dbg(component->dev, "FLL disabled\n");
2900
2901 wm8962->fll_fref = 0;
2902 wm8962->fll_fout = 0;
2903
2904 snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_1,
2905 WM8962_FLL_ENA, 0);
2906
2907 pm_runtime_put(component->dev);
2908
2909 return 0;
2910 }
2911
2912 ret = fll_factors(&fll_div, Fref, Fout);
2913 if (ret != 0)
2914 return ret;
2915
2916 /* Parameters good, disable so we can reprogram */
2917 snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_1, WM8962_FLL_ENA, 0);
2918
2919 switch (fll_id) {
2920 case WM8962_FLL_MCLK:
2921 case WM8962_FLL_BCLK:
2922 fll1 |= (fll_id - 1) << WM8962_FLL_REFCLK_SRC_SHIFT;
2923 break;
2924 case WM8962_FLL_OSC:
2925 fll1 |= (fll_id - 1) << WM8962_FLL_REFCLK_SRC_SHIFT;
2926 snd_soc_component_update_bits(component, WM8962_PLL2,
2927 WM8962_OSC_ENA, WM8962_OSC_ENA);
2928 break;
2929 case WM8962_FLL_INT:
2930 snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_1,
2931 WM8962_FLL_OSC_ENA, WM8962_FLL_OSC_ENA);
2932 snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_5,
2933 WM8962_FLL_FRC_NCO, WM8962_FLL_FRC_NCO);
2934 break;
2935 default:
2936 dev_err(component->dev, "Unknown FLL source %d\n", source);
2937 return -EINVAL;
2938 }
2939
2940 if (fll_div.theta)
2941 fll1 |= WM8962_FLL_FRAC;
2942
2943 /* Stop the FLL while we reconfigure */
2944 snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_1, WM8962_FLL_ENA, 0);
2945
2946 snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_2,
2947 WM8962_FLL_OUTDIV_MASK |
2948 WM8962_FLL_REFCLK_DIV_MASK,
2949 (fll_div.fll_outdiv << WM8962_FLL_OUTDIV_SHIFT) |
2950 (fll_div.fll_refclk_div));
2951
2952 snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_3,
2953 WM8962_FLL_FRATIO_MASK, fll_div.fll_fratio);
2954
2955 snd_soc_component_write(component, WM8962_FLL_CONTROL_6, fll_div.theta);
2956 snd_soc_component_write(component, WM8962_FLL_CONTROL_7, fll_div.lambda);
2957 snd_soc_component_write(component, WM8962_FLL_CONTROL_8, fll_div.n);
2958
2959 reinit_completion(&wm8962->fll_lock);
2960
2961 ret = pm_runtime_resume_and_get(component->dev);
2962 if (ret < 0) {
2963 dev_err(component->dev, "Failed to resume device: %d\n", ret);
2964 return ret;
2965 }
2966
2967 snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_1,
2968 WM8962_FLL_FRAC | WM8962_FLL_REFCLK_SRC_MASK |
2969 WM8962_FLL_ENA, fll1 | WM8962_FLL_ENA);
2970
2971 dev_dbg(component->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
2972
2973 /* This should be a massive overestimate but go even
2974 * higher if we'll error out
2975 */
2976 if (wm8962->irq)
2977 time_left = msecs_to_jiffies(5);
2978 else
2979 time_left = msecs_to_jiffies(1);
2980
2981 time_left = wait_for_completion_timeout(&wm8962->fll_lock,
2982 time_left);
2983
2984 if (time_left == 0 && wm8962->irq) {
2985 dev_err(component->dev, "FLL lock timed out");
2986 snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_1,
2987 WM8962_FLL_ENA, 0);
2988 pm_runtime_put(component->dev);
2989 return -ETIMEDOUT;
2990 }
2991
2992 wm8962->fll_fref = Fref;
2993 wm8962->fll_fout = Fout;
2994 wm8962->fll_src = source;
2995
2996 return 0;
2997}
2998
2999static int wm8962_mute(struct snd_soc_dai *dai, int mute, int direction)
3000{
3001 struct snd_soc_component *component = dai->component;
3002 int val, ret;
3003
3004 if (mute)
3005 val = WM8962_DAC_MUTE | WM8962_DAC_MUTE_ALT;
3006 else
3007 val = 0;
3008
3009 /**
3010 * The DAC mute bit is mirrored in two registers, update both to keep
3011 * the register cache consistent.
3012 */
3013 ret = snd_soc_component_update_bits(component, WM8962_CLASS_D_CONTROL_1,
3014 WM8962_DAC_MUTE_ALT, val);
3015 if (ret < 0)
3016 return ret;
3017
3018 return snd_soc_component_update_bits(component, WM8962_ADC_DAC_CONTROL_1,
3019 WM8962_DAC_MUTE, val);
3020}
3021
3022#define WM8962_RATES (SNDRV_PCM_RATE_8000_48000 |\
3023 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
3024
3025#define WM8962_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
3026 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
3027
3028static const struct snd_soc_dai_ops wm8962_dai_ops = {
3029 .hw_params = wm8962_hw_params,
3030 .set_sysclk = wm8962_set_dai_sysclk,
3031 .set_fmt = wm8962_set_dai_fmt,
3032 .mute_stream = wm8962_mute,
3033 .no_capture_mute = 1,
3034};
3035
3036static struct snd_soc_dai_driver wm8962_dai = {
3037 .name = "wm8962",
3038 .playback = {
3039 .stream_name = "Playback",
3040 .channels_min = 1,
3041 .channels_max = 2,
3042 .rates = WM8962_RATES,
3043 .formats = WM8962_FORMATS,
3044 },
3045 .capture = {
3046 .stream_name = "Capture",
3047 .channels_min = 1,
3048 .channels_max = 2,
3049 .rates = WM8962_RATES,
3050 .formats = WM8962_FORMATS,
3051 },
3052 .ops = &wm8962_dai_ops,
3053 .symmetric_rate = 1,
3054};
3055
3056static void wm8962_mic_work(struct work_struct *work)
3057{
3058 struct wm8962_priv *wm8962 = container_of(work,
3059 struct wm8962_priv,
3060 mic_work.work);
3061 struct snd_soc_component *component = wm8962->component;
3062 int status = 0;
3063 int irq_pol = 0;
3064 int reg;
3065
3066 reg = snd_soc_component_read(component, WM8962_ADDITIONAL_CONTROL_4);
3067
3068 if (reg & WM8962_MICDET_STS) {
3069 status |= SND_JACK_MICROPHONE;
3070 irq_pol |= WM8962_MICD_IRQ_POL;
3071 }
3072
3073 if (reg & WM8962_MICSHORT_STS) {
3074 status |= SND_JACK_BTN_0;
3075 irq_pol |= WM8962_MICSCD_IRQ_POL;
3076 }
3077
3078 snd_soc_jack_report(wm8962->jack, status,
3079 SND_JACK_MICROPHONE | SND_JACK_BTN_0);
3080
3081 snd_soc_component_update_bits(component, WM8962_MICINT_SOURCE_POL,
3082 WM8962_MICSCD_IRQ_POL |
3083 WM8962_MICD_IRQ_POL, irq_pol);
3084}
3085
3086static irqreturn_t wm8962_irq(int irq, void *data)
3087{
3088 struct device *dev = data;
3089 struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
3090 unsigned int mask;
3091 unsigned int active;
3092 int reg, ret;
3093
3094 ret = pm_runtime_resume_and_get(dev);
3095 if (ret < 0) {
3096 dev_err(dev, "Failed to resume: %d\n", ret);
3097 return IRQ_NONE;
3098 }
3099
3100 ret = regmap_read(wm8962->regmap, WM8962_INTERRUPT_STATUS_2_MASK,
3101 &mask);
3102 if (ret != 0) {
3103 pm_runtime_put(dev);
3104 dev_err(dev, "Failed to read interrupt mask: %d\n",
3105 ret);
3106 return IRQ_NONE;
3107 }
3108
3109 ret = regmap_read(wm8962->regmap, WM8962_INTERRUPT_STATUS_2, &active);
3110 if (ret != 0) {
3111 pm_runtime_put(dev);
3112 dev_err(dev, "Failed to read interrupt: %d\n", ret);
3113 return IRQ_NONE;
3114 }
3115
3116 active &= ~mask;
3117
3118 if (!active) {
3119 pm_runtime_put(dev);
3120 return IRQ_NONE;
3121 }
3122
3123 /* Acknowledge the interrupts */
3124 ret = regmap_write(wm8962->regmap, WM8962_INTERRUPT_STATUS_2, active);
3125 if (ret != 0)
3126 dev_warn(dev, "Failed to ack interrupt: %d\n", ret);
3127
3128 if (active & WM8962_FLL_LOCK_EINT) {
3129 dev_dbg(dev, "FLL locked\n");
3130 complete(&wm8962->fll_lock);
3131 }
3132
3133 if (active & WM8962_FIFOS_ERR_EINT)
3134 dev_err(dev, "FIFO error\n");
3135
3136 if (active & WM8962_TEMP_SHUT_EINT) {
3137 dev_crit(dev, "Thermal shutdown\n");
3138
3139 ret = regmap_read(wm8962->regmap,
3140 WM8962_THERMAL_SHUTDOWN_STATUS, ®);
3141 if (ret != 0) {
3142 dev_warn(dev, "Failed to read thermal status: %d\n",
3143 ret);
3144 reg = 0;
3145 }
3146
3147 if (reg & WM8962_TEMP_ERR_HP)
3148 dev_crit(dev, "Headphone thermal error\n");
3149 if (reg & WM8962_TEMP_WARN_HP)
3150 dev_crit(dev, "Headphone thermal warning\n");
3151 if (reg & WM8962_TEMP_ERR_SPK)
3152 dev_crit(dev, "Speaker thermal error\n");
3153 if (reg & WM8962_TEMP_WARN_SPK)
3154 dev_crit(dev, "Speaker thermal warning\n");
3155 }
3156
3157 if (active & (WM8962_MICSCD_EINT | WM8962_MICD_EINT)) {
3158 dev_dbg(dev, "Microphone event detected\n");
3159
3160#ifndef CONFIG_SND_SOC_WM8962_MODULE
3161 trace_snd_soc_jack_irq(dev_name(dev));
3162#endif
3163
3164 pm_wakeup_event(dev, 300);
3165
3166 queue_delayed_work(system_power_efficient_wq,
3167 &wm8962->mic_work,
3168 msecs_to_jiffies(250));
3169 }
3170
3171 pm_runtime_put(dev);
3172
3173 return IRQ_HANDLED;
3174}
3175
3176/**
3177 * wm8962_mic_detect - Enable microphone detection via the WM8962 IRQ
3178 *
3179 * @component: WM8962 component
3180 * @jack: jack to report detection events on
3181 *
3182 * Enable microphone detection via IRQ on the WM8962. If GPIOs are
3183 * being used to bring out signals to the processor then only platform
3184 * data configuration is needed for WM8962 and processor GPIOs should
3185 * be configured using snd_soc_jack_add_gpios() instead.
3186 *
3187 * If no jack is supplied detection will be disabled.
3188 */
3189int wm8962_mic_detect(struct snd_soc_component *component, struct snd_soc_jack *jack)
3190{
3191 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
3192 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
3193 int irq_mask, enable;
3194
3195 wm8962->jack = jack;
3196 if (jack) {
3197 irq_mask = 0;
3198 enable = WM8962_MICDET_ENA;
3199 } else {
3200 irq_mask = WM8962_MICD_EINT | WM8962_MICSCD_EINT;
3201 enable = 0;
3202 }
3203
3204 snd_soc_component_update_bits(component, WM8962_INTERRUPT_STATUS_2_MASK,
3205 WM8962_MICD_EINT | WM8962_MICSCD_EINT, irq_mask);
3206 snd_soc_component_update_bits(component, WM8962_ADDITIONAL_CONTROL_4,
3207 WM8962_MICDET_ENA, enable);
3208
3209 /* Send an initial empty report */
3210 snd_soc_jack_report(wm8962->jack, 0,
3211 SND_JACK_MICROPHONE | SND_JACK_BTN_0);
3212
3213 snd_soc_dapm_mutex_lock(dapm);
3214
3215 if (jack) {
3216 snd_soc_dapm_force_enable_pin_unlocked(dapm, "SYSCLK");
3217 snd_soc_dapm_force_enable_pin_unlocked(dapm, "MICBIAS");
3218 } else {
3219 snd_soc_dapm_disable_pin_unlocked(dapm, "SYSCLK");
3220 snd_soc_dapm_disable_pin_unlocked(dapm, "MICBIAS");
3221 }
3222
3223 snd_soc_dapm_mutex_unlock(dapm);
3224
3225 return 0;
3226}
3227EXPORT_SYMBOL_GPL(wm8962_mic_detect);
3228
3229static int beep_rates[] = {
3230 500, 1000, 2000, 4000,
3231};
3232
3233static void wm8962_beep_work(struct work_struct *work)
3234{
3235 struct wm8962_priv *wm8962 =
3236 container_of(work, struct wm8962_priv, beep_work);
3237 struct snd_soc_component *component = wm8962->component;
3238 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
3239 int i;
3240 int reg = 0;
3241 int best = 0;
3242
3243 if (wm8962->beep_rate) {
3244 for (i = 0; i < ARRAY_SIZE(beep_rates); i++) {
3245 if (abs(wm8962->beep_rate - beep_rates[i]) <
3246 abs(wm8962->beep_rate - beep_rates[best]))
3247 best = i;
3248 }
3249
3250 dev_dbg(component->dev, "Set beep rate %dHz for requested %dHz\n",
3251 beep_rates[best], wm8962->beep_rate);
3252
3253 reg = WM8962_BEEP_ENA | (best << WM8962_BEEP_RATE_SHIFT);
3254
3255 snd_soc_dapm_enable_pin(dapm, "Beep");
3256 } else {
3257 dev_dbg(component->dev, "Disabling beep\n");
3258 snd_soc_dapm_disable_pin(dapm, "Beep");
3259 }
3260
3261 snd_soc_component_update_bits(component, WM8962_BEEP_GENERATOR_1,
3262 WM8962_BEEP_ENA | WM8962_BEEP_RATE_MASK, reg);
3263
3264 snd_soc_dapm_sync(dapm);
3265}
3266
3267/* For usability define a way of injecting beep events for the device -
3268 * many systems will not have a keyboard.
3269 */
3270static int wm8962_beep_event(struct input_dev *dev, unsigned int type,
3271 unsigned int code, int hz)
3272{
3273 struct snd_soc_component *component = input_get_drvdata(dev);
3274 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
3275
3276 dev_dbg(component->dev, "Beep event %x %x\n", code, hz);
3277
3278 switch (code) {
3279 case SND_BELL:
3280 if (hz)
3281 hz = 1000;
3282 fallthrough;
3283 case SND_TONE:
3284 break;
3285 default:
3286 return -1;
3287 }
3288
3289 /* Kick the beep from a workqueue */
3290 wm8962->beep_rate = hz;
3291 schedule_work(&wm8962->beep_work);
3292 return 0;
3293}
3294
3295static ssize_t beep_store(struct device *dev, struct device_attribute *attr,
3296 const char *buf, size_t count)
3297{
3298 struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
3299 long int time;
3300 int ret;
3301
3302 ret = kstrtol(buf, 10, &time);
3303 if (ret != 0)
3304 return ret;
3305
3306 input_event(wm8962->beep, EV_SND, SND_TONE, time);
3307
3308 return count;
3309}
3310
3311static DEVICE_ATTR_WO(beep);
3312
3313static void wm8962_init_beep(struct snd_soc_component *component)
3314{
3315 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
3316 int ret;
3317
3318 wm8962->beep = devm_input_allocate_device(component->dev);
3319 if (!wm8962->beep) {
3320 dev_err(component->dev, "Failed to allocate beep device\n");
3321 return;
3322 }
3323
3324 INIT_WORK(&wm8962->beep_work, wm8962_beep_work);
3325 wm8962->beep_rate = 0;
3326
3327 wm8962->beep->name = "WM8962 Beep Generator";
3328 wm8962->beep->phys = dev_name(component->dev);
3329 wm8962->beep->id.bustype = BUS_I2C;
3330
3331 wm8962->beep->evbit[0] = BIT_MASK(EV_SND);
3332 wm8962->beep->sndbit[0] = BIT_MASK(SND_BELL) | BIT_MASK(SND_TONE);
3333 wm8962->beep->event = wm8962_beep_event;
3334 wm8962->beep->dev.parent = component->dev;
3335 input_set_drvdata(wm8962->beep, component);
3336
3337 ret = input_register_device(wm8962->beep);
3338 if (ret != 0) {
3339 wm8962->beep = NULL;
3340 dev_err(component->dev, "Failed to register beep device\n");
3341 }
3342
3343 ret = device_create_file(component->dev, &dev_attr_beep);
3344 if (ret != 0) {
3345 dev_err(component->dev, "Failed to create keyclick file: %d\n",
3346 ret);
3347 }
3348}
3349
3350static void wm8962_free_beep(struct snd_soc_component *component)
3351{
3352 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
3353
3354 device_remove_file(component->dev, &dev_attr_beep);
3355 cancel_work_sync(&wm8962->beep_work);
3356 wm8962->beep = NULL;
3357
3358 snd_soc_component_update_bits(component, WM8962_BEEP_GENERATOR_1, WM8962_BEEP_ENA,0);
3359}
3360
3361static void wm8962_set_gpio_mode(struct wm8962_priv *wm8962, int gpio)
3362{
3363 int mask = 0;
3364 int val = 0;
3365
3366 /* Some of the GPIOs are behind MFP configuration and need to
3367 * be put into GPIO mode. */
3368 switch (gpio) {
3369 case 2:
3370 mask = WM8962_CLKOUT2_SEL_MASK;
3371 val = 1 << WM8962_CLKOUT2_SEL_SHIFT;
3372 break;
3373 case 3:
3374 mask = WM8962_CLKOUT3_SEL_MASK;
3375 val = 1 << WM8962_CLKOUT3_SEL_SHIFT;
3376 break;
3377 default:
3378 break;
3379 }
3380
3381 if (mask)
3382 regmap_update_bits(wm8962->regmap, WM8962_ANALOGUE_CLOCKING1,
3383 mask, val);
3384}
3385
3386#ifdef CONFIG_GPIOLIB
3387static int wm8962_gpio_request(struct gpio_chip *chip, unsigned offset)
3388{
3389 struct wm8962_priv *wm8962 = gpiochip_get_data(chip);
3390
3391 /* The WM8962 GPIOs aren't linearly numbered. For simplicity
3392 * we export linear numbers and error out if the unsupported
3393 * ones are requsted.
3394 */
3395 switch (offset + 1) {
3396 case 2:
3397 case 3:
3398 case 5:
3399 case 6:
3400 break;
3401 default:
3402 return -EINVAL;
3403 }
3404
3405 wm8962_set_gpio_mode(wm8962, offset + 1);
3406
3407 return 0;
3408}
3409
3410static void wm8962_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
3411{
3412 struct wm8962_priv *wm8962 = gpiochip_get_data(chip);
3413 struct snd_soc_component *component = wm8962->component;
3414
3415 snd_soc_component_update_bits(component, WM8962_GPIO_BASE + offset,
3416 WM8962_GP2_LVL, !!value << WM8962_GP2_LVL_SHIFT);
3417}
3418
3419static int wm8962_gpio_direction_out(struct gpio_chip *chip,
3420 unsigned offset, int value)
3421{
3422 struct wm8962_priv *wm8962 = gpiochip_get_data(chip);
3423 struct snd_soc_component *component = wm8962->component;
3424 int ret, val;
3425
3426 /* Force function 1 (logic output) */
3427 val = (1 << WM8962_GP2_FN_SHIFT) | (value << WM8962_GP2_LVL_SHIFT);
3428
3429 ret = snd_soc_component_update_bits(component, WM8962_GPIO_BASE + offset,
3430 WM8962_GP2_FN_MASK | WM8962_GP2_LVL, val);
3431 if (ret < 0)
3432 return ret;
3433
3434 return 0;
3435}
3436
3437static const struct gpio_chip wm8962_template_chip = {
3438 .label = "wm8962",
3439 .owner = THIS_MODULE,
3440 .request = wm8962_gpio_request,
3441 .direction_output = wm8962_gpio_direction_out,
3442 .set = wm8962_gpio_set,
3443 .can_sleep = 1,
3444};
3445
3446static void wm8962_init_gpio(struct snd_soc_component *component)
3447{
3448 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
3449 struct wm8962_pdata *pdata = &wm8962->pdata;
3450 int ret;
3451
3452 wm8962->gpio_chip = wm8962_template_chip;
3453 wm8962->gpio_chip.ngpio = WM8962_MAX_GPIO;
3454 wm8962->gpio_chip.parent = component->dev;
3455
3456 if (pdata->gpio_base)
3457 wm8962->gpio_chip.base = pdata->gpio_base;
3458 else
3459 wm8962->gpio_chip.base = -1;
3460
3461 ret = gpiochip_add_data(&wm8962->gpio_chip, wm8962);
3462 if (ret != 0)
3463 dev_err(component->dev, "Failed to add GPIOs: %d\n", ret);
3464}
3465
3466static void wm8962_free_gpio(struct snd_soc_component *component)
3467{
3468 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
3469
3470 gpiochip_remove(&wm8962->gpio_chip);
3471}
3472#else
3473static void wm8962_init_gpio(struct snd_soc_component *component)
3474{
3475}
3476
3477static void wm8962_free_gpio(struct snd_soc_component *component)
3478{
3479}
3480#endif
3481
3482static int wm8962_probe(struct snd_soc_component *component)
3483{
3484 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
3485 int ret;
3486 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
3487 int i;
3488 bool dmicclk, dmicdat;
3489
3490 wm8962->component = component;
3491
3492 wm8962->disable_nb[0].notifier_call = wm8962_regulator_event_0;
3493 wm8962->disable_nb[1].notifier_call = wm8962_regulator_event_1;
3494 wm8962->disable_nb[2].notifier_call = wm8962_regulator_event_2;
3495 wm8962->disable_nb[3].notifier_call = wm8962_regulator_event_3;
3496 wm8962->disable_nb[4].notifier_call = wm8962_regulator_event_4;
3497 wm8962->disable_nb[5].notifier_call = wm8962_regulator_event_5;
3498 wm8962->disable_nb[6].notifier_call = wm8962_regulator_event_6;
3499 wm8962->disable_nb[7].notifier_call = wm8962_regulator_event_7;
3500
3501 /* This should really be moved into the regulator core */
3502 for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++) {
3503 ret = devm_regulator_register_notifier(
3504 wm8962->supplies[i].consumer,
3505 &wm8962->disable_nb[i]);
3506 if (ret != 0) {
3507 dev_err(component->dev,
3508 "Failed to register regulator notifier: %d\n",
3509 ret);
3510 }
3511 }
3512
3513 wm8962_add_widgets(component);
3514
3515 /* Save boards having to disable DMIC when not in use */
3516 dmicclk = false;
3517 dmicdat = false;
3518 for (i = 1; i < WM8962_MAX_GPIO; i++) {
3519 /*
3520 * Register 515 (WM8962_GPIO_BASE + 3) does not exist,
3521 * so skip its access
3522 */
3523 if (i == 3)
3524 continue;
3525 switch (snd_soc_component_read(component, WM8962_GPIO_BASE + i)
3526 & WM8962_GP2_FN_MASK) {
3527 case WM8962_GPIO_FN_DMICCLK:
3528 dmicclk = true;
3529 break;
3530 case WM8962_GPIO_FN_DMICDAT:
3531 dmicdat = true;
3532 break;
3533 default:
3534 break;
3535 }
3536 }
3537 if (!dmicclk || !dmicdat) {
3538 dev_dbg(component->dev, "DMIC not in use, disabling\n");
3539 snd_soc_dapm_nc_pin(dapm, "DMICDAT");
3540 }
3541 if (dmicclk != dmicdat)
3542 dev_warn(component->dev, "DMIC GPIOs partially configured\n");
3543
3544 wm8962_init_beep(component);
3545 wm8962_init_gpio(component);
3546
3547 return 0;
3548}
3549
3550static void wm8962_remove(struct snd_soc_component *component)
3551{
3552 struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
3553
3554 cancel_delayed_work_sync(&wm8962->mic_work);
3555
3556 wm8962_free_gpio(component);
3557 wm8962_free_beep(component);
3558}
3559
3560static const struct snd_soc_component_driver soc_component_dev_wm8962 = {
3561 .probe = wm8962_probe,
3562 .remove = wm8962_remove,
3563 .set_bias_level = wm8962_set_bias_level,
3564 .set_pll = wm8962_set_fll,
3565 .use_pmdown_time = 1,
3566 .endianness = 1,
3567};
3568
3569/* Improve power consumption for IN4 DC measurement mode */
3570static const struct reg_sequence wm8962_dc_measure[] = {
3571 { 0xfd, 0x1 },
3572 { 0xcc, 0x40 },
3573 { 0xfd, 0 },
3574};
3575
3576static const struct regmap_config wm8962_regmap = {
3577 .reg_bits = 16,
3578 .val_bits = 16,
3579
3580 .max_register = WM8962_MAX_REGISTER,
3581 .reg_defaults = wm8962_reg,
3582 .num_reg_defaults = ARRAY_SIZE(wm8962_reg),
3583 .volatile_reg = wm8962_volatile_register,
3584 .readable_reg = wm8962_readable_register,
3585 .cache_type = REGCACHE_MAPLE,
3586};
3587
3588static int wm8962_set_pdata_from_of(struct i2c_client *i2c,
3589 struct wm8962_pdata *pdata)
3590{
3591 const struct device_node *np = i2c->dev.of_node;
3592 u32 val32;
3593 int i;
3594
3595 if (of_property_read_bool(np, "spk-mono"))
3596 pdata->spk_mono = true;
3597
3598 if (of_property_read_u32(np, "mic-cfg", &val32) >= 0)
3599 pdata->mic_cfg = val32;
3600
3601 if (of_property_read_u32_array(np, "gpio-cfg", pdata->gpio_init,
3602 ARRAY_SIZE(pdata->gpio_init)) >= 0)
3603 for (i = 0; i < ARRAY_SIZE(pdata->gpio_init); i++) {
3604 /*
3605 * The range of GPIO register value is [0x0, 0xffff]
3606 * While the default value of each register is 0x0
3607 * Any other value will be regarded as default value
3608 */
3609 if (pdata->gpio_init[i] > 0xffff)
3610 pdata->gpio_init[i] = 0x0;
3611 }
3612
3613 pdata->mclk = devm_clk_get_optional(&i2c->dev, NULL);
3614 return PTR_ERR_OR_ZERO(pdata->mclk);
3615}
3616
3617static int wm8962_i2c_probe(struct i2c_client *i2c)
3618{
3619 struct wm8962_pdata *pdata = dev_get_platdata(&i2c->dev);
3620 struct wm8962_priv *wm8962;
3621 unsigned int reg;
3622 int ret, i, irq_pol, trigger;
3623
3624 wm8962 = devm_kzalloc(&i2c->dev, sizeof(*wm8962), GFP_KERNEL);
3625 if (wm8962 == NULL)
3626 return -ENOMEM;
3627
3628 mutex_init(&wm8962->dsp2_ena_lock);
3629
3630 i2c_set_clientdata(i2c, wm8962);
3631
3632 INIT_DELAYED_WORK(&wm8962->mic_work, wm8962_mic_work);
3633 init_completion(&wm8962->fll_lock);
3634 wm8962->irq = i2c->irq;
3635
3636 /* If platform data was supplied, update the default data in priv */
3637 if (pdata) {
3638 memcpy(&wm8962->pdata, pdata, sizeof(struct wm8962_pdata));
3639 } else if (i2c->dev.of_node) {
3640 ret = wm8962_set_pdata_from_of(i2c, &wm8962->pdata);
3641 if (ret != 0)
3642 return ret;
3643 }
3644
3645 for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++)
3646 wm8962->supplies[i].supply = wm8962_supply_names[i];
3647
3648 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8962->supplies),
3649 wm8962->supplies);
3650 if (ret != 0) {
3651 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
3652 goto err;
3653 }
3654
3655 ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies),
3656 wm8962->supplies);
3657 if (ret != 0) {
3658 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
3659 return ret;
3660 }
3661
3662 wm8962->regmap = devm_regmap_init_i2c(i2c, &wm8962_regmap);
3663 if (IS_ERR(wm8962->regmap)) {
3664 ret = PTR_ERR(wm8962->regmap);
3665 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
3666 goto err_enable;
3667 }
3668
3669 /*
3670 * We haven't marked the chip revision as volatile due to
3671 * sharing a register with the right input volume; explicitly
3672 * bypass the cache to read it.
3673 */
3674 regcache_cache_bypass(wm8962->regmap, true);
3675
3676 ret = regmap_read(wm8962->regmap, WM8962_SOFTWARE_RESET, ®);
3677 if (ret < 0) {
3678 dev_err(&i2c->dev, "Failed to read ID register\n");
3679 goto err_enable;
3680 }
3681 if (reg != 0x6243) {
3682 dev_err(&i2c->dev,
3683 "Device is not a WM8962, ID %x != 0x6243\n", reg);
3684 ret = -EINVAL;
3685 goto err_enable;
3686 }
3687
3688 ret = regmap_read(wm8962->regmap, WM8962_RIGHT_INPUT_VOLUME, ®);
3689 if (ret < 0) {
3690 dev_err(&i2c->dev, "Failed to read device revision: %d\n",
3691 ret);
3692 goto err_enable;
3693 }
3694
3695 dev_info(&i2c->dev, "customer id %x revision %c\n",
3696 (reg & WM8962_CUST_ID_MASK) >> WM8962_CUST_ID_SHIFT,
3697 ((reg & WM8962_CHIP_REV_MASK) >> WM8962_CHIP_REV_SHIFT)
3698 + 'A');
3699
3700 regcache_cache_bypass(wm8962->regmap, false);
3701
3702 ret = wm8962_reset(wm8962);
3703 if (ret < 0) {
3704 dev_err(&i2c->dev, "Failed to issue reset\n");
3705 goto err_enable;
3706 }
3707
3708 /* SYSCLK defaults to on; make sure it is off so we can safely
3709 * write to registers if the device is declocked.
3710 */
3711 regmap_update_bits(wm8962->regmap, WM8962_CLOCKING2,
3712 WM8962_SYSCLK_ENA, 0);
3713
3714 /* Ensure we have soft control over all registers */
3715 regmap_update_bits(wm8962->regmap, WM8962_CLOCKING2,
3716 WM8962_CLKREG_OVD, WM8962_CLKREG_OVD);
3717
3718 /* Ensure that the oscillator and PLLs are disabled */
3719 regmap_update_bits(wm8962->regmap, WM8962_PLL2,
3720 WM8962_OSC_ENA | WM8962_PLL2_ENA | WM8962_PLL3_ENA,
3721 0);
3722
3723 /* Apply static configuration for GPIOs */
3724 for (i = 0; i < ARRAY_SIZE(wm8962->pdata.gpio_init); i++)
3725 if (wm8962->pdata.gpio_init[i]) {
3726 wm8962_set_gpio_mode(wm8962, i + 1);
3727 regmap_write(wm8962->regmap, 0x200 + i,
3728 wm8962->pdata.gpio_init[i] & 0xffff);
3729 }
3730
3731
3732 /* Put the speakers into mono mode? */
3733 if (wm8962->pdata.spk_mono)
3734 regmap_update_bits(wm8962->regmap, WM8962_CLASS_D_CONTROL_2,
3735 WM8962_SPK_MONO_MASK, WM8962_SPK_MONO);
3736
3737 /* Micbias setup, detection enable and detection
3738 * threasholds. */
3739 if (wm8962->pdata.mic_cfg)
3740 regmap_update_bits(wm8962->regmap, WM8962_ADDITIONAL_CONTROL_4,
3741 WM8962_MICDET_ENA |
3742 WM8962_MICDET_THR_MASK |
3743 WM8962_MICSHORT_THR_MASK |
3744 WM8962_MICBIAS_LVL,
3745 wm8962->pdata.mic_cfg);
3746
3747 /* Latch volume update bits */
3748 regmap_update_bits(wm8962->regmap, WM8962_LEFT_INPUT_VOLUME,
3749 WM8962_IN_VU, WM8962_IN_VU);
3750 regmap_update_bits(wm8962->regmap, WM8962_RIGHT_INPUT_VOLUME,
3751 WM8962_IN_VU, WM8962_IN_VU);
3752 regmap_update_bits(wm8962->regmap, WM8962_LEFT_ADC_VOLUME,
3753 WM8962_ADC_VU, WM8962_ADC_VU);
3754 regmap_update_bits(wm8962->regmap, WM8962_RIGHT_ADC_VOLUME,
3755 WM8962_ADC_VU, WM8962_ADC_VU);
3756 regmap_update_bits(wm8962->regmap, WM8962_LEFT_DAC_VOLUME,
3757 WM8962_DAC_VU, WM8962_DAC_VU);
3758 regmap_update_bits(wm8962->regmap, WM8962_RIGHT_DAC_VOLUME,
3759 WM8962_DAC_VU, WM8962_DAC_VU);
3760 regmap_update_bits(wm8962->regmap, WM8962_SPKOUTL_VOLUME,
3761 WM8962_SPKOUT_VU, WM8962_SPKOUT_VU);
3762 regmap_update_bits(wm8962->regmap, WM8962_SPKOUTR_VOLUME,
3763 WM8962_SPKOUT_VU, WM8962_SPKOUT_VU);
3764 regmap_update_bits(wm8962->regmap, WM8962_HPOUTL_VOLUME,
3765 WM8962_HPOUT_VU, WM8962_HPOUT_VU);
3766 regmap_update_bits(wm8962->regmap, WM8962_HPOUTR_VOLUME,
3767 WM8962_HPOUT_VU, WM8962_HPOUT_VU);
3768
3769 /* Stereo control for EQ */
3770 regmap_update_bits(wm8962->regmap, WM8962_EQ1,
3771 WM8962_EQ_SHARED_COEFF, 0);
3772
3773 /* Don't debouce interrupts so we don't need SYSCLK */
3774 regmap_update_bits(wm8962->regmap, WM8962_IRQ_DEBOUNCE,
3775 WM8962_FLL_LOCK_DB | WM8962_PLL3_LOCK_DB |
3776 WM8962_PLL2_LOCK_DB | WM8962_TEMP_SHUT_DB,
3777 0);
3778
3779 if (wm8962->pdata.in4_dc_measure) {
3780 ret = regmap_register_patch(wm8962->regmap,
3781 wm8962_dc_measure,
3782 ARRAY_SIZE(wm8962_dc_measure));
3783 if (ret != 0)
3784 dev_err(&i2c->dev,
3785 "Failed to configure for DC measurement: %d\n",
3786 ret);
3787 }
3788
3789 if (wm8962->irq) {
3790 if (wm8962->pdata.irq_active_low) {
3791 trigger = IRQF_TRIGGER_LOW;
3792 irq_pol = WM8962_IRQ_POL;
3793 } else {
3794 trigger = IRQF_TRIGGER_HIGH;
3795 irq_pol = 0;
3796 }
3797
3798 regmap_update_bits(wm8962->regmap, WM8962_INTERRUPT_CONTROL,
3799 WM8962_IRQ_POL, irq_pol);
3800
3801 ret = devm_request_threaded_irq(&i2c->dev, wm8962->irq, NULL,
3802 wm8962_irq,
3803 trigger | IRQF_ONESHOT,
3804 "wm8962", &i2c->dev);
3805 if (ret != 0) {
3806 dev_err(&i2c->dev, "Failed to request IRQ %d: %d\n",
3807 wm8962->irq, ret);
3808 wm8962->irq = 0;
3809 /* Non-fatal */
3810 } else {
3811 /* Enable some IRQs by default */
3812 regmap_update_bits(wm8962->regmap,
3813 WM8962_INTERRUPT_STATUS_2_MASK,
3814 WM8962_FLL_LOCK_EINT |
3815 WM8962_TEMP_SHUT_EINT |
3816 WM8962_FIFOS_ERR_EINT, 0);
3817 }
3818 }
3819
3820 pm_runtime_enable(&i2c->dev);
3821 pm_request_idle(&i2c->dev);
3822
3823 ret = devm_snd_soc_register_component(&i2c->dev,
3824 &soc_component_dev_wm8962, &wm8962_dai, 1);
3825 if (ret < 0)
3826 goto err_pm_runtime;
3827
3828 regmap_update_bits(wm8962->regmap, WM8962_ADDITIONAL_CONTROL_4,
3829 WM8962_TEMP_ENA_HP_MASK, 0);
3830 regmap_update_bits(wm8962->regmap, WM8962_ADDITIONAL_CONTROL_4,
3831 WM8962_TEMP_ENA_SPK_MASK, 0);
3832
3833 regcache_cache_only(wm8962->regmap, true);
3834
3835 /* The drivers should power up as needed */
3836 regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
3837
3838 return 0;
3839
3840err_pm_runtime:
3841 pm_runtime_disable(&i2c->dev);
3842err_enable:
3843 regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
3844err:
3845 return ret;
3846}
3847
3848static void wm8962_i2c_remove(struct i2c_client *client)
3849{
3850 pm_runtime_disable(&client->dev);
3851}
3852
3853#ifdef CONFIG_PM
3854static int wm8962_runtime_resume(struct device *dev)
3855{
3856 struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
3857 int ret;
3858
3859 ret = clk_prepare_enable(wm8962->pdata.mclk);
3860 if (ret) {
3861 dev_err(dev, "Failed to enable MCLK: %d\n", ret);
3862 return ret;
3863 }
3864
3865 ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies),
3866 wm8962->supplies);
3867 if (ret != 0) {
3868 dev_err(dev, "Failed to enable supplies: %d\n", ret);
3869 goto disable_clock;
3870 }
3871
3872 regcache_cache_only(wm8962->regmap, false);
3873
3874 wm8962_reset(wm8962);
3875
3876 regcache_mark_dirty(wm8962->regmap);
3877
3878 /* SYSCLK defaults to on; make sure it is off so we can safely
3879 * write to registers if the device is declocked.
3880 */
3881 regmap_write_bits(wm8962->regmap, WM8962_CLOCKING2,
3882 WM8962_SYSCLK_ENA, 0);
3883
3884 /* Ensure we have soft control over all registers */
3885 regmap_update_bits(wm8962->regmap, WM8962_CLOCKING2,
3886 WM8962_CLKREG_OVD, WM8962_CLKREG_OVD);
3887
3888 /* Ensure that the oscillator and PLLs are disabled */
3889 regmap_update_bits(wm8962->regmap, WM8962_PLL2,
3890 WM8962_OSC_ENA | WM8962_PLL2_ENA | WM8962_PLL3_ENA,
3891 0);
3892
3893 regcache_sync(wm8962->regmap);
3894
3895 regmap_update_bits(wm8962->regmap, WM8962_ANTI_POP,
3896 WM8962_STARTUP_BIAS_ENA | WM8962_VMID_BUF_ENA,
3897 WM8962_STARTUP_BIAS_ENA | WM8962_VMID_BUF_ENA);
3898
3899 /* Bias enable at 2*5k (fast start-up) */
3900 regmap_update_bits(wm8962->regmap, WM8962_PWR_MGMT_1,
3901 WM8962_BIAS_ENA | WM8962_VMID_SEL_MASK,
3902 WM8962_BIAS_ENA | 0x180);
3903
3904 msleep(5);
3905
3906 return 0;
3907
3908disable_clock:
3909 clk_disable_unprepare(wm8962->pdata.mclk);
3910 return ret;
3911}
3912
3913static int wm8962_runtime_suspend(struct device *dev)
3914{
3915 struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
3916
3917 regmap_update_bits(wm8962->regmap, WM8962_PWR_MGMT_1,
3918 WM8962_VMID_SEL_MASK | WM8962_BIAS_ENA, 0);
3919
3920 regmap_update_bits(wm8962->regmap, WM8962_ANTI_POP,
3921 WM8962_STARTUP_BIAS_ENA |
3922 WM8962_VMID_BUF_ENA, 0);
3923
3924 regcache_cache_only(wm8962->regmap, true);
3925
3926 regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies),
3927 wm8962->supplies);
3928
3929 clk_disable_unprepare(wm8962->pdata.mclk);
3930
3931 return 0;
3932}
3933#endif
3934
3935static const struct dev_pm_ops wm8962_pm = {
3936 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
3937 SET_RUNTIME_PM_OPS(wm8962_runtime_suspend, wm8962_runtime_resume, NULL)
3938};
3939
3940static const struct i2c_device_id wm8962_i2c_id[] = {
3941 { "wm8962" },
3942 { }
3943};
3944MODULE_DEVICE_TABLE(i2c, wm8962_i2c_id);
3945
3946static const struct of_device_id wm8962_of_match[] = {
3947 { .compatible = "wlf,wm8962", },
3948 { }
3949};
3950MODULE_DEVICE_TABLE(of, wm8962_of_match);
3951
3952static struct i2c_driver wm8962_i2c_driver = {
3953 .driver = {
3954 .name = "wm8962",
3955 .of_match_table = wm8962_of_match,
3956 .pm = &wm8962_pm,
3957 },
3958 .probe = wm8962_i2c_probe,
3959 .remove = wm8962_i2c_remove,
3960 .id_table = wm8962_i2c_id,
3961};
3962
3963module_i2c_driver(wm8962_i2c_driver);
3964
3965MODULE_DESCRIPTION("ASoC WM8962 driver");
3966MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3967MODULE_LICENSE("GPL");
1/*
2 * wm8962.c -- WM8962 ALSA SoC Audio driver
3 *
4 * Copyright 2010 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/gcd.h>
20#include <linux/gpio.h>
21#include <linux/i2c.h>
22#include <linux/input.h>
23#include <linux/pm_runtime.h>
24#include <linux/regmap.h>
25#include <linux/regulator/consumer.h>
26#include <linux/slab.h>
27#include <linux/workqueue.h>
28#include <sound/core.h>
29#include <sound/jack.h>
30#include <sound/pcm.h>
31#include <sound/pcm_params.h>
32#include <sound/soc.h>
33#include <sound/initval.h>
34#include <sound/tlv.h>
35#include <sound/wm8962.h>
36#include <trace/events/asoc.h>
37
38#include "wm8962.h"
39
40#define WM8962_NUM_SUPPLIES 8
41static const char *wm8962_supply_names[WM8962_NUM_SUPPLIES] = {
42 "DCVDD",
43 "DBVDD",
44 "AVDD",
45 "CPVDD",
46 "MICVDD",
47 "PLLVDD",
48 "SPKVDD1",
49 "SPKVDD2",
50};
51
52/* codec private data */
53struct wm8962_priv {
54 struct regmap *regmap;
55 struct snd_soc_codec *codec;
56
57 int sysclk;
58 int sysclk_rate;
59
60 int bclk; /* Desired BCLK */
61 int lrclk;
62
63 struct completion fll_lock;
64 int fll_src;
65 int fll_fref;
66 int fll_fout;
67
68 u16 dsp2_ena;
69
70 struct delayed_work mic_work;
71 struct snd_soc_jack *jack;
72
73 struct regulator_bulk_data supplies[WM8962_NUM_SUPPLIES];
74 struct notifier_block disable_nb[WM8962_NUM_SUPPLIES];
75
76#if defined(CONFIG_INPUT) || defined(CONFIG_INPUT_MODULE)
77 struct input_dev *beep;
78 struct work_struct beep_work;
79 int beep_rate;
80#endif
81
82#ifdef CONFIG_GPIOLIB
83 struct gpio_chip gpio_chip;
84#endif
85
86 int irq;
87};
88
89/* We can't use the same notifier block for more than one supply and
90 * there's no way I can see to get from a callback to the caller
91 * except container_of().
92 */
93#define WM8962_REGULATOR_EVENT(n) \
94static int wm8962_regulator_event_##n(struct notifier_block *nb, \
95 unsigned long event, void *data) \
96{ \
97 struct wm8962_priv *wm8962 = container_of(nb, struct wm8962_priv, \
98 disable_nb[n]); \
99 if (event & REGULATOR_EVENT_DISABLE) { \
100 regcache_mark_dirty(wm8962->regmap); \
101 } \
102 return 0; \
103}
104
105WM8962_REGULATOR_EVENT(0)
106WM8962_REGULATOR_EVENT(1)
107WM8962_REGULATOR_EVENT(2)
108WM8962_REGULATOR_EVENT(3)
109WM8962_REGULATOR_EVENT(4)
110WM8962_REGULATOR_EVENT(5)
111WM8962_REGULATOR_EVENT(6)
112WM8962_REGULATOR_EVENT(7)
113
114static struct reg_default wm8962_reg[] = {
115 { 0, 0x009F }, /* R0 - Left Input volume */
116 { 1, 0x049F }, /* R1 - Right Input volume */
117 { 2, 0x0000 }, /* R2 - HPOUTL volume */
118 { 3, 0x0000 }, /* R3 - HPOUTR volume */
119
120 { 5, 0x0018 }, /* R5 - ADC & DAC Control 1 */
121 { 6, 0x2008 }, /* R6 - ADC & DAC Control 2 */
122 { 7, 0x000A }, /* R7 - Audio Interface 0 */
123
124 { 9, 0x0300 }, /* R9 - Audio Interface 1 */
125 { 10, 0x00C0 }, /* R10 - Left DAC volume */
126 { 11, 0x00C0 }, /* R11 - Right DAC volume */
127
128 { 14, 0x0040 }, /* R14 - Audio Interface 2 */
129 { 15, 0x6243 }, /* R15 - Software Reset */
130
131 { 17, 0x007B }, /* R17 - ALC1 */
132
133 { 19, 0x1C32 }, /* R19 - ALC3 */
134 { 20, 0x3200 }, /* R20 - Noise Gate */
135 { 21, 0x00C0 }, /* R21 - Left ADC volume */
136 { 22, 0x00C0 }, /* R22 - Right ADC volume */
137 { 23, 0x0160 }, /* R23 - Additional control(1) */
138 { 24, 0x0000 }, /* R24 - Additional control(2) */
139 { 25, 0x0000 }, /* R25 - Pwr Mgmt (1) */
140 { 26, 0x0000 }, /* R26 - Pwr Mgmt (2) */
141 { 27, 0x0010 }, /* R27 - Additional Control (3) */
142 { 28, 0x0000 }, /* R28 - Anti-pop */
143
144 { 30, 0x005E }, /* R30 - Clocking 3 */
145 { 31, 0x0000 }, /* R31 - Input mixer control (1) */
146 { 32, 0x0145 }, /* R32 - Left input mixer volume */
147 { 33, 0x0145 }, /* R33 - Right input mixer volume */
148 { 34, 0x0009 }, /* R34 - Input mixer control (2) */
149 { 35, 0x0003 }, /* R35 - Input bias control */
150 { 37, 0x0008 }, /* R37 - Left input PGA control */
151 { 38, 0x0008 }, /* R38 - Right input PGA control */
152
153 { 40, 0x0000 }, /* R40 - SPKOUTL volume */
154 { 41, 0x0000 }, /* R41 - SPKOUTR volume */
155
156 { 51, 0x0003 }, /* R51 - Class D Control 2 */
157
158 { 56, 0x0506 }, /* R56 - Clocking 4 */
159 { 57, 0x0000 }, /* R57 - DAC DSP Mixing (1) */
160 { 58, 0x0000 }, /* R58 - DAC DSP Mixing (2) */
161
162 { 60, 0x0300 }, /* R60 - DC Servo 0 */
163 { 61, 0x0300 }, /* R61 - DC Servo 1 */
164
165 { 64, 0x0810 }, /* R64 - DC Servo 4 */
166
167 { 68, 0x001B }, /* R68 - Analogue PGA Bias */
168 { 69, 0x0000 }, /* R69 - Analogue HP 0 */
169
170 { 71, 0x01FB }, /* R71 - Analogue HP 2 */
171 { 72, 0x0000 }, /* R72 - Charge Pump 1 */
172
173 { 82, 0x0004 }, /* R82 - Charge Pump B */
174
175 { 87, 0x0000 }, /* R87 - Write Sequencer Control 1 */
176
177 { 90, 0x0000 }, /* R90 - Write Sequencer Control 2 */
178
179 { 93, 0x0000 }, /* R93 - Write Sequencer Control 3 */
180 { 94, 0x0000 }, /* R94 - Control Interface */
181
182 { 99, 0x0000 }, /* R99 - Mixer Enables */
183 { 100, 0x0000 }, /* R100 - Headphone Mixer (1) */
184 { 101, 0x0000 }, /* R101 - Headphone Mixer (2) */
185 { 102, 0x013F }, /* R102 - Headphone Mixer (3) */
186 { 103, 0x013F }, /* R103 - Headphone Mixer (4) */
187
188 { 105, 0x0000 }, /* R105 - Speaker Mixer (1) */
189 { 106, 0x0000 }, /* R106 - Speaker Mixer (2) */
190 { 107, 0x013F }, /* R107 - Speaker Mixer (3) */
191 { 108, 0x013F }, /* R108 - Speaker Mixer (4) */
192 { 109, 0x0003 }, /* R109 - Speaker Mixer (5) */
193 { 110, 0x0002 }, /* R110 - Beep Generator (1) */
194
195 { 115, 0x0006 }, /* R115 - Oscillator Trim (3) */
196 { 116, 0x0026 }, /* R116 - Oscillator Trim (4) */
197
198 { 119, 0x0000 }, /* R119 - Oscillator Trim (7) */
199
200 { 124, 0x0011 }, /* R124 - Analogue Clocking1 */
201 { 125, 0x004B }, /* R125 - Analogue Clocking2 */
202 { 126, 0x000D }, /* R126 - Analogue Clocking3 */
203 { 127, 0x0000 }, /* R127 - PLL Software Reset */
204
205 { 131, 0x0000 }, /* R131 - PLL 4 */
206
207 { 136, 0x0067 }, /* R136 - PLL 9 */
208 { 137, 0x001C }, /* R137 - PLL 10 */
209 { 138, 0x0071 }, /* R138 - PLL 11 */
210 { 139, 0x00C7 }, /* R139 - PLL 12 */
211 { 140, 0x0067 }, /* R140 - PLL 13 */
212 { 141, 0x0048 }, /* R141 - PLL 14 */
213 { 142, 0x0022 }, /* R142 - PLL 15 */
214 { 143, 0x0097 }, /* R143 - PLL 16 */
215
216 { 155, 0x000C }, /* R155 - FLL Control (1) */
217 { 156, 0x0039 }, /* R156 - FLL Control (2) */
218 { 157, 0x0180 }, /* R157 - FLL Control (3) */
219
220 { 159, 0x0032 }, /* R159 - FLL Control (5) */
221 { 160, 0x0018 }, /* R160 - FLL Control (6) */
222 { 161, 0x007D }, /* R161 - FLL Control (7) */
223 { 162, 0x0008 }, /* R162 - FLL Control (8) */
224
225 { 252, 0x0005 }, /* R252 - General test 1 */
226
227 { 256, 0x0000 }, /* R256 - DF1 */
228 { 257, 0x0000 }, /* R257 - DF2 */
229 { 258, 0x0000 }, /* R258 - DF3 */
230 { 259, 0x0000 }, /* R259 - DF4 */
231 { 260, 0x0000 }, /* R260 - DF5 */
232 { 261, 0x0000 }, /* R261 - DF6 */
233 { 262, 0x0000 }, /* R262 - DF7 */
234
235 { 264, 0x0000 }, /* R264 - LHPF1 */
236 { 265, 0x0000 }, /* R265 - LHPF2 */
237
238 { 268, 0x0000 }, /* R268 - THREED1 */
239 { 269, 0x0000 }, /* R269 - THREED2 */
240 { 270, 0x0000 }, /* R270 - THREED3 */
241 { 271, 0x0000 }, /* R271 - THREED4 */
242
243 { 276, 0x000C }, /* R276 - DRC 1 */
244 { 277, 0x0925 }, /* R277 - DRC 2 */
245 { 278, 0x0000 }, /* R278 - DRC 3 */
246 { 279, 0x0000 }, /* R279 - DRC 4 */
247 { 280, 0x0000 }, /* R280 - DRC 5 */
248
249 { 285, 0x0000 }, /* R285 - Tloopback */
250
251 { 335, 0x0004 }, /* R335 - EQ1 */
252 { 336, 0x6318 }, /* R336 - EQ2 */
253 { 337, 0x6300 }, /* R337 - EQ3 */
254 { 338, 0x0FCA }, /* R338 - EQ4 */
255 { 339, 0x0400 }, /* R339 - EQ5 */
256 { 340, 0x00D8 }, /* R340 - EQ6 */
257 { 341, 0x1EB5 }, /* R341 - EQ7 */
258 { 342, 0xF145 }, /* R342 - EQ8 */
259 { 343, 0x0B75 }, /* R343 - EQ9 */
260 { 344, 0x01C5 }, /* R344 - EQ10 */
261 { 345, 0x1C58 }, /* R345 - EQ11 */
262 { 346, 0xF373 }, /* R346 - EQ12 */
263 { 347, 0x0A54 }, /* R347 - EQ13 */
264 { 348, 0x0558 }, /* R348 - EQ14 */
265 { 349, 0x168E }, /* R349 - EQ15 */
266 { 350, 0xF829 }, /* R350 - EQ16 */
267 { 351, 0x07AD }, /* R351 - EQ17 */
268 { 352, 0x1103 }, /* R352 - EQ18 */
269 { 353, 0x0564 }, /* R353 - EQ19 */
270 { 354, 0x0559 }, /* R354 - EQ20 */
271 { 355, 0x4000 }, /* R355 - EQ21 */
272 { 356, 0x6318 }, /* R356 - EQ22 */
273 { 357, 0x6300 }, /* R357 - EQ23 */
274 { 358, 0x0FCA }, /* R358 - EQ24 */
275 { 359, 0x0400 }, /* R359 - EQ25 */
276 { 360, 0x00D8 }, /* R360 - EQ26 */
277 { 361, 0x1EB5 }, /* R361 - EQ27 */
278 { 362, 0xF145 }, /* R362 - EQ28 */
279 { 363, 0x0B75 }, /* R363 - EQ29 */
280 { 364, 0x01C5 }, /* R364 - EQ30 */
281 { 365, 0x1C58 }, /* R365 - EQ31 */
282 { 366, 0xF373 }, /* R366 - EQ32 */
283 { 367, 0x0A54 }, /* R367 - EQ33 */
284 { 368, 0x0558 }, /* R368 - EQ34 */
285 { 369, 0x168E }, /* R369 - EQ35 */
286 { 370, 0xF829 }, /* R370 - EQ36 */
287 { 371, 0x07AD }, /* R371 - EQ37 */
288 { 372, 0x1103 }, /* R372 - EQ38 */
289 { 373, 0x0564 }, /* R373 - EQ39 */
290 { 374, 0x0559 }, /* R374 - EQ40 */
291 { 375, 0x4000 }, /* R375 - EQ41 */
292
293 { 513, 0x0000 }, /* R513 - GPIO 2 */
294 { 514, 0x0000 }, /* R514 - GPIO 3 */
295
296 { 516, 0x8100 }, /* R516 - GPIO 5 */
297 { 517, 0x8100 }, /* R517 - GPIO 6 */
298
299 { 568, 0x0030 }, /* R568 - Interrupt Status 1 Mask */
300 { 569, 0xFFED }, /* R569 - Interrupt Status 2 Mask */
301
302 { 576, 0x0000 }, /* R576 - Interrupt Control */
303
304 { 584, 0x002D }, /* R584 - IRQ Debounce */
305
306 { 586, 0x0000 }, /* R586 - MICINT Source Pol */
307
308 { 768, 0x1C00 }, /* R768 - DSP2 Power Management */
309
310 { 8192, 0x0000 }, /* R8192 - DSP2 Instruction RAM 0 */
311
312 { 9216, 0x0030 }, /* R9216 - DSP2 Address RAM 2 */
313 { 9217, 0x0000 }, /* R9217 - DSP2 Address RAM 1 */
314 { 9218, 0x0000 }, /* R9218 - DSP2 Address RAM 0 */
315
316 { 12288, 0x0000 }, /* R12288 - DSP2 Data1 RAM 1 */
317 { 12289, 0x0000 }, /* R12289 - DSP2 Data1 RAM 0 */
318
319 { 13312, 0x0000 }, /* R13312 - DSP2 Data2 RAM 1 */
320 { 13313, 0x0000 }, /* R13313 - DSP2 Data2 RAM 0 */
321
322 { 14336, 0x0000 }, /* R14336 - DSP2 Data3 RAM 1 */
323 { 14337, 0x0000 }, /* R14337 - DSP2 Data3 RAM 0 */
324
325 { 15360, 0x000A }, /* R15360 - DSP2 Coeff RAM 0 */
326
327 { 16384, 0x0000 }, /* R16384 - RETUNEADC_SHARED_COEFF_1 */
328 { 16385, 0x0000 }, /* R16385 - RETUNEADC_SHARED_COEFF_0 */
329 { 16386, 0x0000 }, /* R16386 - RETUNEDAC_SHARED_COEFF_1 */
330 { 16387, 0x0000 }, /* R16387 - RETUNEDAC_SHARED_COEFF_0 */
331 { 16388, 0x0000 }, /* R16388 - SOUNDSTAGE_ENABLES_1 */
332 { 16389, 0x0000 }, /* R16389 - SOUNDSTAGE_ENABLES_0 */
333
334 { 16896, 0x0002 }, /* R16896 - HDBASS_AI_1 */
335 { 16897, 0xBD12 }, /* R16897 - HDBASS_AI_0 */
336 { 16898, 0x007C }, /* R16898 - HDBASS_AR_1 */
337 { 16899, 0x586C }, /* R16899 - HDBASS_AR_0 */
338 { 16900, 0x0053 }, /* R16900 - HDBASS_B_1 */
339 { 16901, 0x8121 }, /* R16901 - HDBASS_B_0 */
340 { 16902, 0x003F }, /* R16902 - HDBASS_K_1 */
341 { 16903, 0x8BD8 }, /* R16903 - HDBASS_K_0 */
342 { 16904, 0x0032 }, /* R16904 - HDBASS_N1_1 */
343 { 16905, 0xF52D }, /* R16905 - HDBASS_N1_0 */
344 { 16906, 0x0065 }, /* R16906 - HDBASS_N2_1 */
345 { 16907, 0xAC8C }, /* R16907 - HDBASS_N2_0 */
346 { 16908, 0x006B }, /* R16908 - HDBASS_N3_1 */
347 { 16909, 0xE087 }, /* R16909 - HDBASS_N3_0 */
348 { 16910, 0x0072 }, /* R16910 - HDBASS_N4_1 */
349 { 16911, 0x1483 }, /* R16911 - HDBASS_N4_0 */
350 { 16912, 0x0072 }, /* R16912 - HDBASS_N5_1 */
351 { 16913, 0x1483 }, /* R16913 - HDBASS_N5_0 */
352 { 16914, 0x0043 }, /* R16914 - HDBASS_X1_1 */
353 { 16915, 0x3525 }, /* R16915 - HDBASS_X1_0 */
354 { 16916, 0x0006 }, /* R16916 - HDBASS_X2_1 */
355 { 16917, 0x6A4A }, /* R16917 - HDBASS_X2_0 */
356 { 16918, 0x0043 }, /* R16918 - HDBASS_X3_1 */
357 { 16919, 0x6079 }, /* R16919 - HDBASS_X3_0 */
358 { 16920, 0x0008 }, /* R16920 - HDBASS_ATK_1 */
359 { 16921, 0x0000 }, /* R16921 - HDBASS_ATK_0 */
360 { 16922, 0x0001 }, /* R16922 - HDBASS_DCY_1 */
361 { 16923, 0x0000 }, /* R16923 - HDBASS_DCY_0 */
362 { 16924, 0x0059 }, /* R16924 - HDBASS_PG_1 */
363 { 16925, 0x999A }, /* R16925 - HDBASS_PG_0 */
364
365 { 17048, 0x0083 }, /* R17408 - HPF_C_1 */
366 { 17049, 0x98AD }, /* R17409 - HPF_C_0 */
367
368 { 17920, 0x007F }, /* R17920 - ADCL_RETUNE_C1_1 */
369 { 17921, 0xFFFF }, /* R17921 - ADCL_RETUNE_C1_0 */
370 { 17922, 0x0000 }, /* R17922 - ADCL_RETUNE_C2_1 */
371 { 17923, 0x0000 }, /* R17923 - ADCL_RETUNE_C2_0 */
372 { 17924, 0x0000 }, /* R17924 - ADCL_RETUNE_C3_1 */
373 { 17925, 0x0000 }, /* R17925 - ADCL_RETUNE_C3_0 */
374 { 17926, 0x0000 }, /* R17926 - ADCL_RETUNE_C4_1 */
375 { 17927, 0x0000 }, /* R17927 - ADCL_RETUNE_C4_0 */
376 { 17928, 0x0000 }, /* R17928 - ADCL_RETUNE_C5_1 */
377 { 17929, 0x0000 }, /* R17929 - ADCL_RETUNE_C5_0 */
378 { 17930, 0x0000 }, /* R17930 - ADCL_RETUNE_C6_1 */
379 { 17931, 0x0000 }, /* R17931 - ADCL_RETUNE_C6_0 */
380 { 17932, 0x0000 }, /* R17932 - ADCL_RETUNE_C7_1 */
381 { 17933, 0x0000 }, /* R17933 - ADCL_RETUNE_C7_0 */
382 { 17934, 0x0000 }, /* R17934 - ADCL_RETUNE_C8_1 */
383 { 17935, 0x0000 }, /* R17935 - ADCL_RETUNE_C8_0 */
384 { 17936, 0x0000 }, /* R17936 - ADCL_RETUNE_C9_1 */
385 { 17937, 0x0000 }, /* R17937 - ADCL_RETUNE_C9_0 */
386 { 17938, 0x0000 }, /* R17938 - ADCL_RETUNE_C10_1 */
387 { 17939, 0x0000 }, /* R17939 - ADCL_RETUNE_C10_0 */
388 { 17940, 0x0000 }, /* R17940 - ADCL_RETUNE_C11_1 */
389 { 17941, 0x0000 }, /* R17941 - ADCL_RETUNE_C11_0 */
390 { 17942, 0x0000 }, /* R17942 - ADCL_RETUNE_C12_1 */
391 { 17943, 0x0000 }, /* R17943 - ADCL_RETUNE_C12_0 */
392 { 17944, 0x0000 }, /* R17944 - ADCL_RETUNE_C13_1 */
393 { 17945, 0x0000 }, /* R17945 - ADCL_RETUNE_C13_0 */
394 { 17946, 0x0000 }, /* R17946 - ADCL_RETUNE_C14_1 */
395 { 17947, 0x0000 }, /* R17947 - ADCL_RETUNE_C14_0 */
396 { 17948, 0x0000 }, /* R17948 - ADCL_RETUNE_C15_1 */
397 { 17949, 0x0000 }, /* R17949 - ADCL_RETUNE_C15_0 */
398 { 17950, 0x0000 }, /* R17950 - ADCL_RETUNE_C16_1 */
399 { 17951, 0x0000 }, /* R17951 - ADCL_RETUNE_C16_0 */
400 { 17952, 0x0000 }, /* R17952 - ADCL_RETUNE_C17_1 */
401 { 17953, 0x0000 }, /* R17953 - ADCL_RETUNE_C17_0 */
402 { 17954, 0x0000 }, /* R17954 - ADCL_RETUNE_C18_1 */
403 { 17955, 0x0000 }, /* R17955 - ADCL_RETUNE_C18_0 */
404 { 17956, 0x0000 }, /* R17956 - ADCL_RETUNE_C19_1 */
405 { 17957, 0x0000 }, /* R17957 - ADCL_RETUNE_C19_0 */
406 { 17958, 0x0000 }, /* R17958 - ADCL_RETUNE_C20_1 */
407 { 17959, 0x0000 }, /* R17959 - ADCL_RETUNE_C20_0 */
408 { 17960, 0x0000 }, /* R17960 - ADCL_RETUNE_C21_1 */
409 { 17961, 0x0000 }, /* R17961 - ADCL_RETUNE_C21_0 */
410 { 17962, 0x0000 }, /* R17962 - ADCL_RETUNE_C22_1 */
411 { 17963, 0x0000 }, /* R17963 - ADCL_RETUNE_C22_0 */
412 { 17964, 0x0000 }, /* R17964 - ADCL_RETUNE_C23_1 */
413 { 17965, 0x0000 }, /* R17965 - ADCL_RETUNE_C23_0 */
414 { 17966, 0x0000 }, /* R17966 - ADCL_RETUNE_C24_1 */
415 { 17967, 0x0000 }, /* R17967 - ADCL_RETUNE_C24_0 */
416 { 17968, 0x0000 }, /* R17968 - ADCL_RETUNE_C25_1 */
417 { 17969, 0x0000 }, /* R17969 - ADCL_RETUNE_C25_0 */
418 { 17970, 0x0000 }, /* R17970 - ADCL_RETUNE_C26_1 */
419 { 17971, 0x0000 }, /* R17971 - ADCL_RETUNE_C26_0 */
420 { 17972, 0x0000 }, /* R17972 - ADCL_RETUNE_C27_1 */
421 { 17973, 0x0000 }, /* R17973 - ADCL_RETUNE_C27_0 */
422 { 17974, 0x0000 }, /* R17974 - ADCL_RETUNE_C28_1 */
423 { 17975, 0x0000 }, /* R17975 - ADCL_RETUNE_C28_0 */
424 { 17976, 0x0000 }, /* R17976 - ADCL_RETUNE_C29_1 */
425 { 17977, 0x0000 }, /* R17977 - ADCL_RETUNE_C29_0 */
426 { 17978, 0x0000 }, /* R17978 - ADCL_RETUNE_C30_1 */
427 { 17979, 0x0000 }, /* R17979 - ADCL_RETUNE_C30_0 */
428 { 17980, 0x0000 }, /* R17980 - ADCL_RETUNE_C31_1 */
429 { 17981, 0x0000 }, /* R17981 - ADCL_RETUNE_C31_0 */
430 { 17982, 0x0000 }, /* R17982 - ADCL_RETUNE_C32_1 */
431 { 17983, 0x0000 }, /* R17983 - ADCL_RETUNE_C32_0 */
432
433 { 18432, 0x0020 }, /* R18432 - RETUNEADC_PG2_1 */
434 { 18433, 0x0000 }, /* R18433 - RETUNEADC_PG2_0 */
435 { 18434, 0x0040 }, /* R18434 - RETUNEADC_PG_1 */
436 { 18435, 0x0000 }, /* R18435 - RETUNEADC_PG_0 */
437
438 { 18944, 0x007F }, /* R18944 - ADCR_RETUNE_C1_1 */
439 { 18945, 0xFFFF }, /* R18945 - ADCR_RETUNE_C1_0 */
440 { 18946, 0x0000 }, /* R18946 - ADCR_RETUNE_C2_1 */
441 { 18947, 0x0000 }, /* R18947 - ADCR_RETUNE_C2_0 */
442 { 18948, 0x0000 }, /* R18948 - ADCR_RETUNE_C3_1 */
443 { 18949, 0x0000 }, /* R18949 - ADCR_RETUNE_C3_0 */
444 { 18950, 0x0000 }, /* R18950 - ADCR_RETUNE_C4_1 */
445 { 18951, 0x0000 }, /* R18951 - ADCR_RETUNE_C4_0 */
446 { 18952, 0x0000 }, /* R18952 - ADCR_RETUNE_C5_1 */
447 { 18953, 0x0000 }, /* R18953 - ADCR_RETUNE_C5_0 */
448 { 18954, 0x0000 }, /* R18954 - ADCR_RETUNE_C6_1 */
449 { 18955, 0x0000 }, /* R18955 - ADCR_RETUNE_C6_0 */
450 { 18956, 0x0000 }, /* R18956 - ADCR_RETUNE_C7_1 */
451 { 18957, 0x0000 }, /* R18957 - ADCR_RETUNE_C7_0 */
452 { 18958, 0x0000 }, /* R18958 - ADCR_RETUNE_C8_1 */
453 { 18959, 0x0000 }, /* R18959 - ADCR_RETUNE_C8_0 */
454 { 18960, 0x0000 }, /* R18960 - ADCR_RETUNE_C9_1 */
455 { 18961, 0x0000 }, /* R18961 - ADCR_RETUNE_C9_0 */
456 { 18962, 0x0000 }, /* R18962 - ADCR_RETUNE_C10_1 */
457 { 18963, 0x0000 }, /* R18963 - ADCR_RETUNE_C10_0 */
458 { 18964, 0x0000 }, /* R18964 - ADCR_RETUNE_C11_1 */
459 { 18965, 0x0000 }, /* R18965 - ADCR_RETUNE_C11_0 */
460 { 18966, 0x0000 }, /* R18966 - ADCR_RETUNE_C12_1 */
461 { 18967, 0x0000 }, /* R18967 - ADCR_RETUNE_C12_0 */
462 { 18968, 0x0000 }, /* R18968 - ADCR_RETUNE_C13_1 */
463 { 18969, 0x0000 }, /* R18969 - ADCR_RETUNE_C13_0 */
464 { 18970, 0x0000 }, /* R18970 - ADCR_RETUNE_C14_1 */
465 { 18971, 0x0000 }, /* R18971 - ADCR_RETUNE_C14_0 */
466 { 18972, 0x0000 }, /* R18972 - ADCR_RETUNE_C15_1 */
467 { 18973, 0x0000 }, /* R18973 - ADCR_RETUNE_C15_0 */
468 { 18974, 0x0000 }, /* R18974 - ADCR_RETUNE_C16_1 */
469 { 18975, 0x0000 }, /* R18975 - ADCR_RETUNE_C16_0 */
470 { 18976, 0x0000 }, /* R18976 - ADCR_RETUNE_C17_1 */
471 { 18977, 0x0000 }, /* R18977 - ADCR_RETUNE_C17_0 */
472 { 18978, 0x0000 }, /* R18978 - ADCR_RETUNE_C18_1 */
473 { 18979, 0x0000 }, /* R18979 - ADCR_RETUNE_C18_0 */
474 { 18980, 0x0000 }, /* R18980 - ADCR_RETUNE_C19_1 */
475 { 18981, 0x0000 }, /* R18981 - ADCR_RETUNE_C19_0 */
476 { 18982, 0x0000 }, /* R18982 - ADCR_RETUNE_C20_1 */
477 { 18983, 0x0000 }, /* R18983 - ADCR_RETUNE_C20_0 */
478 { 18984, 0x0000 }, /* R18984 - ADCR_RETUNE_C21_1 */
479 { 18985, 0x0000 }, /* R18985 - ADCR_RETUNE_C21_0 */
480 { 18986, 0x0000 }, /* R18986 - ADCR_RETUNE_C22_1 */
481 { 18987, 0x0000 }, /* R18987 - ADCR_RETUNE_C22_0 */
482 { 18988, 0x0000 }, /* R18988 - ADCR_RETUNE_C23_1 */
483 { 18989, 0x0000 }, /* R18989 - ADCR_RETUNE_C23_0 */
484 { 18990, 0x0000 }, /* R18990 - ADCR_RETUNE_C24_1 */
485 { 18991, 0x0000 }, /* R18991 - ADCR_RETUNE_C24_0 */
486 { 18992, 0x0000 }, /* R18992 - ADCR_RETUNE_C25_1 */
487 { 18993, 0x0000 }, /* R18993 - ADCR_RETUNE_C25_0 */
488 { 18994, 0x0000 }, /* R18994 - ADCR_RETUNE_C26_1 */
489 { 18995, 0x0000 }, /* R18995 - ADCR_RETUNE_C26_0 */
490 { 18996, 0x0000 }, /* R18996 - ADCR_RETUNE_C27_1 */
491 { 18997, 0x0000 }, /* R18997 - ADCR_RETUNE_C27_0 */
492 { 18998, 0x0000 }, /* R18998 - ADCR_RETUNE_C28_1 */
493 { 18999, 0x0000 }, /* R18999 - ADCR_RETUNE_C28_0 */
494 { 19000, 0x0000 }, /* R19000 - ADCR_RETUNE_C29_1 */
495 { 19001, 0x0000 }, /* R19001 - ADCR_RETUNE_C29_0 */
496 { 19002, 0x0000 }, /* R19002 - ADCR_RETUNE_C30_1 */
497 { 19003, 0x0000 }, /* R19003 - ADCR_RETUNE_C30_0 */
498 { 19004, 0x0000 }, /* R19004 - ADCR_RETUNE_C31_1 */
499 { 19005, 0x0000 }, /* R19005 - ADCR_RETUNE_C31_0 */
500 { 19006, 0x0000 }, /* R19006 - ADCR_RETUNE_C32_1 */
501 { 19007, 0x0000 }, /* R19007 - ADCR_RETUNE_C32_0 */
502
503 { 19456, 0x007F }, /* R19456 - DACL_RETUNE_C1_1 */
504 { 19457, 0xFFFF }, /* R19457 - DACL_RETUNE_C1_0 */
505 { 19458, 0x0000 }, /* R19458 - DACL_RETUNE_C2_1 */
506 { 19459, 0x0000 }, /* R19459 - DACL_RETUNE_C2_0 */
507 { 19460, 0x0000 }, /* R19460 - DACL_RETUNE_C3_1 */
508 { 19461, 0x0000 }, /* R19461 - DACL_RETUNE_C3_0 */
509 { 19462, 0x0000 }, /* R19462 - DACL_RETUNE_C4_1 */
510 { 19463, 0x0000 }, /* R19463 - DACL_RETUNE_C4_0 */
511 { 19464, 0x0000 }, /* R19464 - DACL_RETUNE_C5_1 */
512 { 19465, 0x0000 }, /* R19465 - DACL_RETUNE_C5_0 */
513 { 19466, 0x0000 }, /* R19466 - DACL_RETUNE_C6_1 */
514 { 19467, 0x0000 }, /* R19467 - DACL_RETUNE_C6_0 */
515 { 19468, 0x0000 }, /* R19468 - DACL_RETUNE_C7_1 */
516 { 19469, 0x0000 }, /* R19469 - DACL_RETUNE_C7_0 */
517 { 19470, 0x0000 }, /* R19470 - DACL_RETUNE_C8_1 */
518 { 19471, 0x0000 }, /* R19471 - DACL_RETUNE_C8_0 */
519 { 19472, 0x0000 }, /* R19472 - DACL_RETUNE_C9_1 */
520 { 19473, 0x0000 }, /* R19473 - DACL_RETUNE_C9_0 */
521 { 19474, 0x0000 }, /* R19474 - DACL_RETUNE_C10_1 */
522 { 19475, 0x0000 }, /* R19475 - DACL_RETUNE_C10_0 */
523 { 19476, 0x0000 }, /* R19476 - DACL_RETUNE_C11_1 */
524 { 19477, 0x0000 }, /* R19477 - DACL_RETUNE_C11_0 */
525 { 19478, 0x0000 }, /* R19478 - DACL_RETUNE_C12_1 */
526 { 19479, 0x0000 }, /* R19479 - DACL_RETUNE_C12_0 */
527 { 19480, 0x0000 }, /* R19480 - DACL_RETUNE_C13_1 */
528 { 19481, 0x0000 }, /* R19481 - DACL_RETUNE_C13_0 */
529 { 19482, 0x0000 }, /* R19482 - DACL_RETUNE_C14_1 */
530 { 19483, 0x0000 }, /* R19483 - DACL_RETUNE_C14_0 */
531 { 19484, 0x0000 }, /* R19484 - DACL_RETUNE_C15_1 */
532 { 19485, 0x0000 }, /* R19485 - DACL_RETUNE_C15_0 */
533 { 19486, 0x0000 }, /* R19486 - DACL_RETUNE_C16_1 */
534 { 19487, 0x0000 }, /* R19487 - DACL_RETUNE_C16_0 */
535 { 19488, 0x0000 }, /* R19488 - DACL_RETUNE_C17_1 */
536 { 19489, 0x0000 }, /* R19489 - DACL_RETUNE_C17_0 */
537 { 19490, 0x0000 }, /* R19490 - DACL_RETUNE_C18_1 */
538 { 19491, 0x0000 }, /* R19491 - DACL_RETUNE_C18_0 */
539 { 19492, 0x0000 }, /* R19492 - DACL_RETUNE_C19_1 */
540 { 19493, 0x0000 }, /* R19493 - DACL_RETUNE_C19_0 */
541 { 19494, 0x0000 }, /* R19494 - DACL_RETUNE_C20_1 */
542 { 19495, 0x0000 }, /* R19495 - DACL_RETUNE_C20_0 */
543 { 19496, 0x0000 }, /* R19496 - DACL_RETUNE_C21_1 */
544 { 19497, 0x0000 }, /* R19497 - DACL_RETUNE_C21_0 */
545 { 19498, 0x0000 }, /* R19498 - DACL_RETUNE_C22_1 */
546 { 19499, 0x0000 }, /* R19499 - DACL_RETUNE_C22_0 */
547 { 19500, 0x0000 }, /* R19500 - DACL_RETUNE_C23_1 */
548 { 19501, 0x0000 }, /* R19501 - DACL_RETUNE_C23_0 */
549 { 19502, 0x0000 }, /* R19502 - DACL_RETUNE_C24_1 */
550 { 19503, 0x0000 }, /* R19503 - DACL_RETUNE_C24_0 */
551 { 19504, 0x0000 }, /* R19504 - DACL_RETUNE_C25_1 */
552 { 19505, 0x0000 }, /* R19505 - DACL_RETUNE_C25_0 */
553 { 19506, 0x0000 }, /* R19506 - DACL_RETUNE_C26_1 */
554 { 19507, 0x0000 }, /* R19507 - DACL_RETUNE_C26_0 */
555 { 19508, 0x0000 }, /* R19508 - DACL_RETUNE_C27_1 */
556 { 19509, 0x0000 }, /* R19509 - DACL_RETUNE_C27_0 */
557 { 19510, 0x0000 }, /* R19510 - DACL_RETUNE_C28_1 */
558 { 19511, 0x0000 }, /* R19511 - DACL_RETUNE_C28_0 */
559 { 19512, 0x0000 }, /* R19512 - DACL_RETUNE_C29_1 */
560 { 19513, 0x0000 }, /* R19513 - DACL_RETUNE_C29_0 */
561 { 19514, 0x0000 }, /* R19514 - DACL_RETUNE_C30_1 */
562 { 19515, 0x0000 }, /* R19515 - DACL_RETUNE_C30_0 */
563 { 19516, 0x0000 }, /* R19516 - DACL_RETUNE_C31_1 */
564 { 19517, 0x0000 }, /* R19517 - DACL_RETUNE_C31_0 */
565 { 19518, 0x0000 }, /* R19518 - DACL_RETUNE_C32_1 */
566 { 19519, 0x0000 }, /* R19519 - DACL_RETUNE_C32_0 */
567
568 { 19968, 0x0020 }, /* R19968 - RETUNEDAC_PG2_1 */
569 { 19969, 0x0000 }, /* R19969 - RETUNEDAC_PG2_0 */
570 { 19970, 0x0040 }, /* R19970 - RETUNEDAC_PG_1 */
571 { 19971, 0x0000 }, /* R19971 - RETUNEDAC_PG_0 */
572
573 { 20480, 0x007F }, /* R20480 - DACR_RETUNE_C1_1 */
574 { 20481, 0xFFFF }, /* R20481 - DACR_RETUNE_C1_0 */
575 { 20482, 0x0000 }, /* R20482 - DACR_RETUNE_C2_1 */
576 { 20483, 0x0000 }, /* R20483 - DACR_RETUNE_C2_0 */
577 { 20484, 0x0000 }, /* R20484 - DACR_RETUNE_C3_1 */
578 { 20485, 0x0000 }, /* R20485 - DACR_RETUNE_C3_0 */
579 { 20486, 0x0000 }, /* R20486 - DACR_RETUNE_C4_1 */
580 { 20487, 0x0000 }, /* R20487 - DACR_RETUNE_C4_0 */
581 { 20488, 0x0000 }, /* R20488 - DACR_RETUNE_C5_1 */
582 { 20489, 0x0000 }, /* R20489 - DACR_RETUNE_C5_0 */
583 { 20490, 0x0000 }, /* R20490 - DACR_RETUNE_C6_1 */
584 { 20491, 0x0000 }, /* R20491 - DACR_RETUNE_C6_0 */
585 { 20492, 0x0000 }, /* R20492 - DACR_RETUNE_C7_1 */
586 { 20493, 0x0000 }, /* R20493 - DACR_RETUNE_C7_0 */
587 { 20494, 0x0000 }, /* R20494 - DACR_RETUNE_C8_1 */
588 { 20495, 0x0000 }, /* R20495 - DACR_RETUNE_C8_0 */
589 { 20496, 0x0000 }, /* R20496 - DACR_RETUNE_C9_1 */
590 { 20497, 0x0000 }, /* R20497 - DACR_RETUNE_C9_0 */
591 { 20498, 0x0000 }, /* R20498 - DACR_RETUNE_C10_1 */
592 { 20499, 0x0000 }, /* R20499 - DACR_RETUNE_C10_0 */
593 { 20500, 0x0000 }, /* R20500 - DACR_RETUNE_C11_1 */
594 { 20501, 0x0000 }, /* R20501 - DACR_RETUNE_C11_0 */
595 { 20502, 0x0000 }, /* R20502 - DACR_RETUNE_C12_1 */
596 { 20503, 0x0000 }, /* R20503 - DACR_RETUNE_C12_0 */
597 { 20504, 0x0000 }, /* R20504 - DACR_RETUNE_C13_1 */
598 { 20505, 0x0000 }, /* R20505 - DACR_RETUNE_C13_0 */
599 { 20506, 0x0000 }, /* R20506 - DACR_RETUNE_C14_1 */
600 { 20507, 0x0000 }, /* R20507 - DACR_RETUNE_C14_0 */
601 { 20508, 0x0000 }, /* R20508 - DACR_RETUNE_C15_1 */
602 { 20509, 0x0000 }, /* R20509 - DACR_RETUNE_C15_0 */
603 { 20510, 0x0000 }, /* R20510 - DACR_RETUNE_C16_1 */
604 { 20511, 0x0000 }, /* R20511 - DACR_RETUNE_C16_0 */
605 { 20512, 0x0000 }, /* R20512 - DACR_RETUNE_C17_1 */
606 { 20513, 0x0000 }, /* R20513 - DACR_RETUNE_C17_0 */
607 { 20514, 0x0000 }, /* R20514 - DACR_RETUNE_C18_1 */
608 { 20515, 0x0000 }, /* R20515 - DACR_RETUNE_C18_0 */
609 { 20516, 0x0000 }, /* R20516 - DACR_RETUNE_C19_1 */
610 { 20517, 0x0000 }, /* R20517 - DACR_RETUNE_C19_0 */
611 { 20518, 0x0000 }, /* R20518 - DACR_RETUNE_C20_1 */
612 { 20519, 0x0000 }, /* R20519 - DACR_RETUNE_C20_0 */
613 { 20520, 0x0000 }, /* R20520 - DACR_RETUNE_C21_1 */
614 { 20521, 0x0000 }, /* R20521 - DACR_RETUNE_C21_0 */
615 { 20522, 0x0000 }, /* R20522 - DACR_RETUNE_C22_1 */
616 { 20523, 0x0000 }, /* R20523 - DACR_RETUNE_C22_0 */
617 { 20524, 0x0000 }, /* R20524 - DACR_RETUNE_C23_1 */
618 { 20525, 0x0000 }, /* R20525 - DACR_RETUNE_C23_0 */
619 { 20526, 0x0000 }, /* R20526 - DACR_RETUNE_C24_1 */
620 { 20527, 0x0000 }, /* R20527 - DACR_RETUNE_C24_0 */
621 { 20528, 0x0000 }, /* R20528 - DACR_RETUNE_C25_1 */
622 { 20529, 0x0000 }, /* R20529 - DACR_RETUNE_C25_0 */
623 { 20530, 0x0000 }, /* R20530 - DACR_RETUNE_C26_1 */
624 { 20531, 0x0000 }, /* R20531 - DACR_RETUNE_C26_0 */
625 { 20532, 0x0000 }, /* R20532 - DACR_RETUNE_C27_1 */
626 { 20533, 0x0000 }, /* R20533 - DACR_RETUNE_C27_0 */
627 { 20534, 0x0000 }, /* R20534 - DACR_RETUNE_C28_1 */
628 { 20535, 0x0000 }, /* R20535 - DACR_RETUNE_C28_0 */
629 { 20536, 0x0000 }, /* R20536 - DACR_RETUNE_C29_1 */
630 { 20537, 0x0000 }, /* R20537 - DACR_RETUNE_C29_0 */
631 { 20538, 0x0000 }, /* R20538 - DACR_RETUNE_C30_1 */
632 { 20539, 0x0000 }, /* R20539 - DACR_RETUNE_C30_0 */
633 { 20540, 0x0000 }, /* R20540 - DACR_RETUNE_C31_1 */
634 { 20541, 0x0000 }, /* R20541 - DACR_RETUNE_C31_0 */
635 { 20542, 0x0000 }, /* R20542 - DACR_RETUNE_C32_1 */
636 { 20543, 0x0000 }, /* R20543 - DACR_RETUNE_C32_0 */
637
638 { 20992, 0x008C }, /* R20992 - VSS_XHD2_1 */
639 { 20993, 0x0200 }, /* R20993 - VSS_XHD2_0 */
640 { 20994, 0x0035 }, /* R20994 - VSS_XHD3_1 */
641 { 20995, 0x0700 }, /* R20995 - VSS_XHD3_0 */
642 { 20996, 0x003A }, /* R20996 - VSS_XHN1_1 */
643 { 20997, 0x4100 }, /* R20997 - VSS_XHN1_0 */
644 { 20998, 0x008B }, /* R20998 - VSS_XHN2_1 */
645 { 20999, 0x7D00 }, /* R20999 - VSS_XHN2_0 */
646 { 21000, 0x003A }, /* R21000 - VSS_XHN3_1 */
647 { 21001, 0x4100 }, /* R21001 - VSS_XHN3_0 */
648 { 21002, 0x008C }, /* R21002 - VSS_XLA_1 */
649 { 21003, 0xFEE8 }, /* R21003 - VSS_XLA_0 */
650 { 21004, 0x0078 }, /* R21004 - VSS_XLB_1 */
651 { 21005, 0x0000 }, /* R21005 - VSS_XLB_0 */
652 { 21006, 0x003F }, /* R21006 - VSS_XLG_1 */
653 { 21007, 0xB260 }, /* R21007 - VSS_XLG_0 */
654 { 21008, 0x002D }, /* R21008 - VSS_PG2_1 */
655 { 21009, 0x1818 }, /* R21009 - VSS_PG2_0 */
656 { 21010, 0x0020 }, /* R21010 - VSS_PG_1 */
657 { 21011, 0x0000 }, /* R21011 - VSS_PG_0 */
658 { 21012, 0x00F1 }, /* R21012 - VSS_XTD1_1 */
659 { 21013, 0x8340 }, /* R21013 - VSS_XTD1_0 */
660 { 21014, 0x00FB }, /* R21014 - VSS_XTD2_1 */
661 { 21015, 0x8300 }, /* R21015 - VSS_XTD2_0 */
662 { 21016, 0x00EE }, /* R21016 - VSS_XTD3_1 */
663 { 21017, 0xAEC0 }, /* R21017 - VSS_XTD3_0 */
664 { 21018, 0x00FB }, /* R21018 - VSS_XTD4_1 */
665 { 21019, 0xAC40 }, /* R21019 - VSS_XTD4_0 */
666 { 21020, 0x00F1 }, /* R21020 - VSS_XTD5_1 */
667 { 21021, 0x7F80 }, /* R21021 - VSS_XTD5_0 */
668 { 21022, 0x00F4 }, /* R21022 - VSS_XTD6_1 */
669 { 21023, 0x3B40 }, /* R21023 - VSS_XTD6_0 */
670 { 21024, 0x00F5 }, /* R21024 - VSS_XTD7_1 */
671 { 21025, 0xFB00 }, /* R21025 - VSS_XTD7_0 */
672 { 21026, 0x00EA }, /* R21026 - VSS_XTD8_1 */
673 { 21027, 0x10C0 }, /* R21027 - VSS_XTD8_0 */
674 { 21028, 0x00FC }, /* R21028 - VSS_XTD9_1 */
675 { 21029, 0xC580 }, /* R21029 - VSS_XTD9_0 */
676 { 21030, 0x00E2 }, /* R21030 - VSS_XTD10_1 */
677 { 21031, 0x75C0 }, /* R21031 - VSS_XTD10_0 */
678 { 21032, 0x0004 }, /* R21032 - VSS_XTD11_1 */
679 { 21033, 0xB480 }, /* R21033 - VSS_XTD11_0 */
680 { 21034, 0x00D4 }, /* R21034 - VSS_XTD12_1 */
681 { 21035, 0xF980 }, /* R21035 - VSS_XTD12_0 */
682 { 21036, 0x0004 }, /* R21036 - VSS_XTD13_1 */
683 { 21037, 0x9140 }, /* R21037 - VSS_XTD13_0 */
684 { 21038, 0x00D8 }, /* R21038 - VSS_XTD14_1 */
685 { 21039, 0xA480 }, /* R21039 - VSS_XTD14_0 */
686 { 21040, 0x0002 }, /* R21040 - VSS_XTD15_1 */
687 { 21041, 0x3DC0 }, /* R21041 - VSS_XTD15_0 */
688 { 21042, 0x00CF }, /* R21042 - VSS_XTD16_1 */
689 { 21043, 0x7A80 }, /* R21043 - VSS_XTD16_0 */
690 { 21044, 0x00DC }, /* R21044 - VSS_XTD17_1 */
691 { 21045, 0x0600 }, /* R21045 - VSS_XTD17_0 */
692 { 21046, 0x00F2 }, /* R21046 - VSS_XTD18_1 */
693 { 21047, 0xDAC0 }, /* R21047 - VSS_XTD18_0 */
694 { 21048, 0x00BA }, /* R21048 - VSS_XTD19_1 */
695 { 21049, 0xF340 }, /* R21049 - VSS_XTD19_0 */
696 { 21050, 0x000A }, /* R21050 - VSS_XTD20_1 */
697 { 21051, 0x7940 }, /* R21051 - VSS_XTD20_0 */
698 { 21052, 0x001C }, /* R21052 - VSS_XTD21_1 */
699 { 21053, 0x0680 }, /* R21053 - VSS_XTD21_0 */
700 { 21054, 0x00FD }, /* R21054 - VSS_XTD22_1 */
701 { 21055, 0x2D00 }, /* R21055 - VSS_XTD22_0 */
702 { 21056, 0x001C }, /* R21056 - VSS_XTD23_1 */
703 { 21057, 0xE840 }, /* R21057 - VSS_XTD23_0 */
704 { 21058, 0x000D }, /* R21058 - VSS_XTD24_1 */
705 { 21059, 0xDC40 }, /* R21059 - VSS_XTD24_0 */
706 { 21060, 0x00FC }, /* R21060 - VSS_XTD25_1 */
707 { 21061, 0x9D00 }, /* R21061 - VSS_XTD25_0 */
708 { 21062, 0x0009 }, /* R21062 - VSS_XTD26_1 */
709 { 21063, 0x5580 }, /* R21063 - VSS_XTD26_0 */
710 { 21064, 0x00FE }, /* R21064 - VSS_XTD27_1 */
711 { 21065, 0x7E80 }, /* R21065 - VSS_XTD27_0 */
712 { 21066, 0x000E }, /* R21066 - VSS_XTD28_1 */
713 { 21067, 0xAB40 }, /* R21067 - VSS_XTD28_0 */
714 { 21068, 0x00F9 }, /* R21068 - VSS_XTD29_1 */
715 { 21069, 0x9880 }, /* R21069 - VSS_XTD29_0 */
716 { 21070, 0x0009 }, /* R21070 - VSS_XTD30_1 */
717 { 21071, 0x87C0 }, /* R21071 - VSS_XTD30_0 */
718 { 21072, 0x00FD }, /* R21072 - VSS_XTD31_1 */
719 { 21073, 0x2C40 }, /* R21073 - VSS_XTD31_0 */
720 { 21074, 0x0009 }, /* R21074 - VSS_XTD32_1 */
721 { 21075, 0x4800 }, /* R21075 - VSS_XTD32_0 */
722 { 21076, 0x0003 }, /* R21076 - VSS_XTS1_1 */
723 { 21077, 0x5F40 }, /* R21077 - VSS_XTS1_0 */
724 { 21078, 0x0000 }, /* R21078 - VSS_XTS2_1 */
725 { 21079, 0x8700 }, /* R21079 - VSS_XTS2_0 */
726 { 21080, 0x00FA }, /* R21080 - VSS_XTS3_1 */
727 { 21081, 0xE4C0 }, /* R21081 - VSS_XTS3_0 */
728 { 21082, 0x0000 }, /* R21082 - VSS_XTS4_1 */
729 { 21083, 0x0B40 }, /* R21083 - VSS_XTS4_0 */
730 { 21084, 0x0004 }, /* R21084 - VSS_XTS5_1 */
731 { 21085, 0xE180 }, /* R21085 - VSS_XTS5_0 */
732 { 21086, 0x0001 }, /* R21086 - VSS_XTS6_1 */
733 { 21087, 0x1F40 }, /* R21087 - VSS_XTS6_0 */
734 { 21088, 0x00F8 }, /* R21088 - VSS_XTS7_1 */
735 { 21089, 0xB000 }, /* R21089 - VSS_XTS7_0 */
736 { 21090, 0x00FB }, /* R21090 - VSS_XTS8_1 */
737 { 21091, 0xCBC0 }, /* R21091 - VSS_XTS8_0 */
738 { 21092, 0x0004 }, /* R21092 - VSS_XTS9_1 */
739 { 21093, 0xF380 }, /* R21093 - VSS_XTS9_0 */
740 { 21094, 0x0007 }, /* R21094 - VSS_XTS10_1 */
741 { 21095, 0xDF40 }, /* R21095 - VSS_XTS10_0 */
742 { 21096, 0x00FF }, /* R21096 - VSS_XTS11_1 */
743 { 21097, 0x0700 }, /* R21097 - VSS_XTS11_0 */
744 { 21098, 0x00EF }, /* R21098 - VSS_XTS12_1 */
745 { 21099, 0xD700 }, /* R21099 - VSS_XTS12_0 */
746 { 21100, 0x00FB }, /* R21100 - VSS_XTS13_1 */
747 { 21101, 0xAF40 }, /* R21101 - VSS_XTS13_0 */
748 { 21102, 0x0010 }, /* R21102 - VSS_XTS14_1 */
749 { 21103, 0x8A80 }, /* R21103 - VSS_XTS14_0 */
750 { 21104, 0x0011 }, /* R21104 - VSS_XTS15_1 */
751 { 21105, 0x07C0 }, /* R21105 - VSS_XTS15_0 */
752 { 21106, 0x00E0 }, /* R21106 - VSS_XTS16_1 */
753 { 21107, 0x0800 }, /* R21107 - VSS_XTS16_0 */
754 { 21108, 0x00D2 }, /* R21108 - VSS_XTS17_1 */
755 { 21109, 0x7600 }, /* R21109 - VSS_XTS17_0 */
756 { 21110, 0x0020 }, /* R21110 - VSS_XTS18_1 */
757 { 21111, 0xCF40 }, /* R21111 - VSS_XTS18_0 */
758 { 21112, 0x0030 }, /* R21112 - VSS_XTS19_1 */
759 { 21113, 0x2340 }, /* R21113 - VSS_XTS19_0 */
760 { 21114, 0x00FD }, /* R21114 - VSS_XTS20_1 */
761 { 21115, 0x69C0 }, /* R21115 - VSS_XTS20_0 */
762 { 21116, 0x0028 }, /* R21116 - VSS_XTS21_1 */
763 { 21117, 0x3500 }, /* R21117 - VSS_XTS21_0 */
764 { 21118, 0x0006 }, /* R21118 - VSS_XTS22_1 */
765 { 21119, 0x3300 }, /* R21119 - VSS_XTS22_0 */
766 { 21120, 0x00D9 }, /* R21120 - VSS_XTS23_1 */
767 { 21121, 0xF6C0 }, /* R21121 - VSS_XTS23_0 */
768 { 21122, 0x00F3 }, /* R21122 - VSS_XTS24_1 */
769 { 21123, 0x3340 }, /* R21123 - VSS_XTS24_0 */
770 { 21124, 0x000F }, /* R21124 - VSS_XTS25_1 */
771 { 21125, 0x4200 }, /* R21125 - VSS_XTS25_0 */
772 { 21126, 0x0004 }, /* R21126 - VSS_XTS26_1 */
773 { 21127, 0x0C80 }, /* R21127 - VSS_XTS26_0 */
774 { 21128, 0x00FB }, /* R21128 - VSS_XTS27_1 */
775 { 21129, 0x3F80 }, /* R21129 - VSS_XTS27_0 */
776 { 21130, 0x00F7 }, /* R21130 - VSS_XTS28_1 */
777 { 21131, 0x57C0 }, /* R21131 - VSS_XTS28_0 */
778 { 21132, 0x0003 }, /* R21132 - VSS_XTS29_1 */
779 { 21133, 0x5400 }, /* R21133 - VSS_XTS29_0 */
780 { 21134, 0x0000 }, /* R21134 - VSS_XTS30_1 */
781 { 21135, 0xC6C0 }, /* R21135 - VSS_XTS30_0 */
782 { 21136, 0x0003 }, /* R21136 - VSS_XTS31_1 */
783 { 21137, 0x12C0 }, /* R21137 - VSS_XTS31_0 */
784 { 21138, 0x00FD }, /* R21138 - VSS_XTS32_1 */
785 { 21139, 0x8580 }, /* R21139 - VSS_XTS32_0 */
786};
787
788static bool wm8962_volatile_register(struct device *dev, unsigned int reg)
789{
790 switch (reg) {
791 case WM8962_CLOCKING1:
792 case WM8962_CLOCKING2:
793 case WM8962_SOFTWARE_RESET:
794 case WM8962_ALC2:
795 case WM8962_THERMAL_SHUTDOWN_STATUS:
796 case WM8962_ADDITIONAL_CONTROL_4:
797 case WM8962_CLASS_D_CONTROL_1:
798 case WM8962_DC_SERVO_6:
799 case WM8962_INTERRUPT_STATUS_1:
800 case WM8962_INTERRUPT_STATUS_2:
801 case WM8962_DSP2_EXECCONTROL:
802 return true;
803 default:
804 return false;
805 }
806}
807
808static bool wm8962_readable_register(struct device *dev, unsigned int reg)
809{
810 switch (reg) {
811 case WM8962_LEFT_INPUT_VOLUME:
812 case WM8962_RIGHT_INPUT_VOLUME:
813 case WM8962_HPOUTL_VOLUME:
814 case WM8962_HPOUTR_VOLUME:
815 case WM8962_CLOCKING1:
816 case WM8962_ADC_DAC_CONTROL_1:
817 case WM8962_ADC_DAC_CONTROL_2:
818 case WM8962_AUDIO_INTERFACE_0:
819 case WM8962_CLOCKING2:
820 case WM8962_AUDIO_INTERFACE_1:
821 case WM8962_LEFT_DAC_VOLUME:
822 case WM8962_RIGHT_DAC_VOLUME:
823 case WM8962_AUDIO_INTERFACE_2:
824 case WM8962_SOFTWARE_RESET:
825 case WM8962_ALC1:
826 case WM8962_ALC2:
827 case WM8962_ALC3:
828 case WM8962_NOISE_GATE:
829 case WM8962_LEFT_ADC_VOLUME:
830 case WM8962_RIGHT_ADC_VOLUME:
831 case WM8962_ADDITIONAL_CONTROL_1:
832 case WM8962_ADDITIONAL_CONTROL_2:
833 case WM8962_PWR_MGMT_1:
834 case WM8962_PWR_MGMT_2:
835 case WM8962_ADDITIONAL_CONTROL_3:
836 case WM8962_ANTI_POP:
837 case WM8962_CLOCKING_3:
838 case WM8962_INPUT_MIXER_CONTROL_1:
839 case WM8962_LEFT_INPUT_MIXER_VOLUME:
840 case WM8962_RIGHT_INPUT_MIXER_VOLUME:
841 case WM8962_INPUT_MIXER_CONTROL_2:
842 case WM8962_INPUT_BIAS_CONTROL:
843 case WM8962_LEFT_INPUT_PGA_CONTROL:
844 case WM8962_RIGHT_INPUT_PGA_CONTROL:
845 case WM8962_SPKOUTL_VOLUME:
846 case WM8962_SPKOUTR_VOLUME:
847 case WM8962_THERMAL_SHUTDOWN_STATUS:
848 case WM8962_ADDITIONAL_CONTROL_4:
849 case WM8962_CLASS_D_CONTROL_1:
850 case WM8962_CLASS_D_CONTROL_2:
851 case WM8962_CLOCKING_4:
852 case WM8962_DAC_DSP_MIXING_1:
853 case WM8962_DAC_DSP_MIXING_2:
854 case WM8962_DC_SERVO_0:
855 case WM8962_DC_SERVO_1:
856 case WM8962_DC_SERVO_4:
857 case WM8962_DC_SERVO_6:
858 case WM8962_ANALOGUE_PGA_BIAS:
859 case WM8962_ANALOGUE_HP_0:
860 case WM8962_ANALOGUE_HP_2:
861 case WM8962_CHARGE_PUMP_1:
862 case WM8962_CHARGE_PUMP_B:
863 case WM8962_WRITE_SEQUENCER_CONTROL_1:
864 case WM8962_WRITE_SEQUENCER_CONTROL_2:
865 case WM8962_WRITE_SEQUENCER_CONTROL_3:
866 case WM8962_CONTROL_INTERFACE:
867 case WM8962_MIXER_ENABLES:
868 case WM8962_HEADPHONE_MIXER_1:
869 case WM8962_HEADPHONE_MIXER_2:
870 case WM8962_HEADPHONE_MIXER_3:
871 case WM8962_HEADPHONE_MIXER_4:
872 case WM8962_SPEAKER_MIXER_1:
873 case WM8962_SPEAKER_MIXER_2:
874 case WM8962_SPEAKER_MIXER_3:
875 case WM8962_SPEAKER_MIXER_4:
876 case WM8962_SPEAKER_MIXER_5:
877 case WM8962_BEEP_GENERATOR_1:
878 case WM8962_OSCILLATOR_TRIM_3:
879 case WM8962_OSCILLATOR_TRIM_4:
880 case WM8962_OSCILLATOR_TRIM_7:
881 case WM8962_ANALOGUE_CLOCKING1:
882 case WM8962_ANALOGUE_CLOCKING2:
883 case WM8962_ANALOGUE_CLOCKING3:
884 case WM8962_PLL_SOFTWARE_RESET:
885 case WM8962_PLL2:
886 case WM8962_PLL_4:
887 case WM8962_PLL_9:
888 case WM8962_PLL_10:
889 case WM8962_PLL_11:
890 case WM8962_PLL_12:
891 case WM8962_PLL_13:
892 case WM8962_PLL_14:
893 case WM8962_PLL_15:
894 case WM8962_PLL_16:
895 case WM8962_FLL_CONTROL_1:
896 case WM8962_FLL_CONTROL_2:
897 case WM8962_FLL_CONTROL_3:
898 case WM8962_FLL_CONTROL_5:
899 case WM8962_FLL_CONTROL_6:
900 case WM8962_FLL_CONTROL_7:
901 case WM8962_FLL_CONTROL_8:
902 case WM8962_GENERAL_TEST_1:
903 case WM8962_DF1:
904 case WM8962_DF2:
905 case WM8962_DF3:
906 case WM8962_DF4:
907 case WM8962_DF5:
908 case WM8962_DF6:
909 case WM8962_DF7:
910 case WM8962_LHPF1:
911 case WM8962_LHPF2:
912 case WM8962_THREED1:
913 case WM8962_THREED2:
914 case WM8962_THREED3:
915 case WM8962_THREED4:
916 case WM8962_DRC_1:
917 case WM8962_DRC_2:
918 case WM8962_DRC_3:
919 case WM8962_DRC_4:
920 case WM8962_DRC_5:
921 case WM8962_TLOOPBACK:
922 case WM8962_EQ1:
923 case WM8962_EQ2:
924 case WM8962_EQ3:
925 case WM8962_EQ4:
926 case WM8962_EQ5:
927 case WM8962_EQ6:
928 case WM8962_EQ7:
929 case WM8962_EQ8:
930 case WM8962_EQ9:
931 case WM8962_EQ10:
932 case WM8962_EQ11:
933 case WM8962_EQ12:
934 case WM8962_EQ13:
935 case WM8962_EQ14:
936 case WM8962_EQ15:
937 case WM8962_EQ16:
938 case WM8962_EQ17:
939 case WM8962_EQ18:
940 case WM8962_EQ19:
941 case WM8962_EQ20:
942 case WM8962_EQ21:
943 case WM8962_EQ22:
944 case WM8962_EQ23:
945 case WM8962_EQ24:
946 case WM8962_EQ25:
947 case WM8962_EQ26:
948 case WM8962_EQ27:
949 case WM8962_EQ28:
950 case WM8962_EQ29:
951 case WM8962_EQ30:
952 case WM8962_EQ31:
953 case WM8962_EQ32:
954 case WM8962_EQ33:
955 case WM8962_EQ34:
956 case WM8962_EQ35:
957 case WM8962_EQ36:
958 case WM8962_EQ37:
959 case WM8962_EQ38:
960 case WM8962_EQ39:
961 case WM8962_EQ40:
962 case WM8962_EQ41:
963 case WM8962_GPIO_BASE:
964 case WM8962_GPIO_2:
965 case WM8962_GPIO_3:
966 case WM8962_GPIO_5:
967 case WM8962_GPIO_6:
968 case WM8962_INTERRUPT_STATUS_1:
969 case WM8962_INTERRUPT_STATUS_2:
970 case WM8962_INTERRUPT_STATUS_1_MASK:
971 case WM8962_INTERRUPT_STATUS_2_MASK:
972 case WM8962_INTERRUPT_CONTROL:
973 case WM8962_IRQ_DEBOUNCE:
974 case WM8962_MICINT_SOURCE_POL:
975 case WM8962_DSP2_POWER_MANAGEMENT:
976 case WM8962_DSP2_EXECCONTROL:
977 case WM8962_DSP2_INSTRUCTION_RAM_0:
978 case WM8962_DSP2_ADDRESS_RAM_2:
979 case WM8962_DSP2_ADDRESS_RAM_1:
980 case WM8962_DSP2_ADDRESS_RAM_0:
981 case WM8962_DSP2_DATA1_RAM_1:
982 case WM8962_DSP2_DATA1_RAM_0:
983 case WM8962_DSP2_DATA2_RAM_1:
984 case WM8962_DSP2_DATA2_RAM_0:
985 case WM8962_DSP2_DATA3_RAM_1:
986 case WM8962_DSP2_DATA3_RAM_0:
987 case WM8962_DSP2_COEFF_RAM_0:
988 case WM8962_RETUNEADC_SHARED_COEFF_1:
989 case WM8962_RETUNEADC_SHARED_COEFF_0:
990 case WM8962_RETUNEDAC_SHARED_COEFF_1:
991 case WM8962_RETUNEDAC_SHARED_COEFF_0:
992 case WM8962_SOUNDSTAGE_ENABLES_1:
993 case WM8962_SOUNDSTAGE_ENABLES_0:
994 case WM8962_HDBASS_AI_1:
995 case WM8962_HDBASS_AI_0:
996 case WM8962_HDBASS_AR_1:
997 case WM8962_HDBASS_AR_0:
998 case WM8962_HDBASS_B_1:
999 case WM8962_HDBASS_B_0:
1000 case WM8962_HDBASS_K_1:
1001 case WM8962_HDBASS_K_0:
1002 case WM8962_HDBASS_N1_1:
1003 case WM8962_HDBASS_N1_0:
1004 case WM8962_HDBASS_N2_1:
1005 case WM8962_HDBASS_N2_0:
1006 case WM8962_HDBASS_N3_1:
1007 case WM8962_HDBASS_N3_0:
1008 case WM8962_HDBASS_N4_1:
1009 case WM8962_HDBASS_N4_0:
1010 case WM8962_HDBASS_N5_1:
1011 case WM8962_HDBASS_N5_0:
1012 case WM8962_HDBASS_X1_1:
1013 case WM8962_HDBASS_X1_0:
1014 case WM8962_HDBASS_X2_1:
1015 case WM8962_HDBASS_X2_0:
1016 case WM8962_HDBASS_X3_1:
1017 case WM8962_HDBASS_X3_0:
1018 case WM8962_HDBASS_ATK_1:
1019 case WM8962_HDBASS_ATK_0:
1020 case WM8962_HDBASS_DCY_1:
1021 case WM8962_HDBASS_DCY_0:
1022 case WM8962_HDBASS_PG_1:
1023 case WM8962_HDBASS_PG_0:
1024 case WM8962_HPF_C_1:
1025 case WM8962_HPF_C_0:
1026 case WM8962_ADCL_RETUNE_C1_1:
1027 case WM8962_ADCL_RETUNE_C1_0:
1028 case WM8962_ADCL_RETUNE_C2_1:
1029 case WM8962_ADCL_RETUNE_C2_0:
1030 case WM8962_ADCL_RETUNE_C3_1:
1031 case WM8962_ADCL_RETUNE_C3_0:
1032 case WM8962_ADCL_RETUNE_C4_1:
1033 case WM8962_ADCL_RETUNE_C4_0:
1034 case WM8962_ADCL_RETUNE_C5_1:
1035 case WM8962_ADCL_RETUNE_C5_0:
1036 case WM8962_ADCL_RETUNE_C6_1:
1037 case WM8962_ADCL_RETUNE_C6_0:
1038 case WM8962_ADCL_RETUNE_C7_1:
1039 case WM8962_ADCL_RETUNE_C7_0:
1040 case WM8962_ADCL_RETUNE_C8_1:
1041 case WM8962_ADCL_RETUNE_C8_0:
1042 case WM8962_ADCL_RETUNE_C9_1:
1043 case WM8962_ADCL_RETUNE_C9_0:
1044 case WM8962_ADCL_RETUNE_C10_1:
1045 case WM8962_ADCL_RETUNE_C10_0:
1046 case WM8962_ADCL_RETUNE_C11_1:
1047 case WM8962_ADCL_RETUNE_C11_0:
1048 case WM8962_ADCL_RETUNE_C12_1:
1049 case WM8962_ADCL_RETUNE_C12_0:
1050 case WM8962_ADCL_RETUNE_C13_1:
1051 case WM8962_ADCL_RETUNE_C13_0:
1052 case WM8962_ADCL_RETUNE_C14_1:
1053 case WM8962_ADCL_RETUNE_C14_0:
1054 case WM8962_ADCL_RETUNE_C15_1:
1055 case WM8962_ADCL_RETUNE_C15_0:
1056 case WM8962_ADCL_RETUNE_C16_1:
1057 case WM8962_ADCL_RETUNE_C16_0:
1058 case WM8962_ADCL_RETUNE_C17_1:
1059 case WM8962_ADCL_RETUNE_C17_0:
1060 case WM8962_ADCL_RETUNE_C18_1:
1061 case WM8962_ADCL_RETUNE_C18_0:
1062 case WM8962_ADCL_RETUNE_C19_1:
1063 case WM8962_ADCL_RETUNE_C19_0:
1064 case WM8962_ADCL_RETUNE_C20_1:
1065 case WM8962_ADCL_RETUNE_C20_0:
1066 case WM8962_ADCL_RETUNE_C21_1:
1067 case WM8962_ADCL_RETUNE_C21_0:
1068 case WM8962_ADCL_RETUNE_C22_1:
1069 case WM8962_ADCL_RETUNE_C22_0:
1070 case WM8962_ADCL_RETUNE_C23_1:
1071 case WM8962_ADCL_RETUNE_C23_0:
1072 case WM8962_ADCL_RETUNE_C24_1:
1073 case WM8962_ADCL_RETUNE_C24_0:
1074 case WM8962_ADCL_RETUNE_C25_1:
1075 case WM8962_ADCL_RETUNE_C25_0:
1076 case WM8962_ADCL_RETUNE_C26_1:
1077 case WM8962_ADCL_RETUNE_C26_0:
1078 case WM8962_ADCL_RETUNE_C27_1:
1079 case WM8962_ADCL_RETUNE_C27_0:
1080 case WM8962_ADCL_RETUNE_C28_1:
1081 case WM8962_ADCL_RETUNE_C28_0:
1082 case WM8962_ADCL_RETUNE_C29_1:
1083 case WM8962_ADCL_RETUNE_C29_0:
1084 case WM8962_ADCL_RETUNE_C30_1:
1085 case WM8962_ADCL_RETUNE_C30_0:
1086 case WM8962_ADCL_RETUNE_C31_1:
1087 case WM8962_ADCL_RETUNE_C31_0:
1088 case WM8962_ADCL_RETUNE_C32_1:
1089 case WM8962_ADCL_RETUNE_C32_0:
1090 case WM8962_RETUNEADC_PG2_1:
1091 case WM8962_RETUNEADC_PG2_0:
1092 case WM8962_RETUNEADC_PG_1:
1093 case WM8962_RETUNEADC_PG_0:
1094 case WM8962_ADCR_RETUNE_C1_1:
1095 case WM8962_ADCR_RETUNE_C1_0:
1096 case WM8962_ADCR_RETUNE_C2_1:
1097 case WM8962_ADCR_RETUNE_C2_0:
1098 case WM8962_ADCR_RETUNE_C3_1:
1099 case WM8962_ADCR_RETUNE_C3_0:
1100 case WM8962_ADCR_RETUNE_C4_1:
1101 case WM8962_ADCR_RETUNE_C4_0:
1102 case WM8962_ADCR_RETUNE_C5_1:
1103 case WM8962_ADCR_RETUNE_C5_0:
1104 case WM8962_ADCR_RETUNE_C6_1:
1105 case WM8962_ADCR_RETUNE_C6_0:
1106 case WM8962_ADCR_RETUNE_C7_1:
1107 case WM8962_ADCR_RETUNE_C7_0:
1108 case WM8962_ADCR_RETUNE_C8_1:
1109 case WM8962_ADCR_RETUNE_C8_0:
1110 case WM8962_ADCR_RETUNE_C9_1:
1111 case WM8962_ADCR_RETUNE_C9_0:
1112 case WM8962_ADCR_RETUNE_C10_1:
1113 case WM8962_ADCR_RETUNE_C10_0:
1114 case WM8962_ADCR_RETUNE_C11_1:
1115 case WM8962_ADCR_RETUNE_C11_0:
1116 case WM8962_ADCR_RETUNE_C12_1:
1117 case WM8962_ADCR_RETUNE_C12_0:
1118 case WM8962_ADCR_RETUNE_C13_1:
1119 case WM8962_ADCR_RETUNE_C13_0:
1120 case WM8962_ADCR_RETUNE_C14_1:
1121 case WM8962_ADCR_RETUNE_C14_0:
1122 case WM8962_ADCR_RETUNE_C15_1:
1123 case WM8962_ADCR_RETUNE_C15_0:
1124 case WM8962_ADCR_RETUNE_C16_1:
1125 case WM8962_ADCR_RETUNE_C16_0:
1126 case WM8962_ADCR_RETUNE_C17_1:
1127 case WM8962_ADCR_RETUNE_C17_0:
1128 case WM8962_ADCR_RETUNE_C18_1:
1129 case WM8962_ADCR_RETUNE_C18_0:
1130 case WM8962_ADCR_RETUNE_C19_1:
1131 case WM8962_ADCR_RETUNE_C19_0:
1132 case WM8962_ADCR_RETUNE_C20_1:
1133 case WM8962_ADCR_RETUNE_C20_0:
1134 case WM8962_ADCR_RETUNE_C21_1:
1135 case WM8962_ADCR_RETUNE_C21_0:
1136 case WM8962_ADCR_RETUNE_C22_1:
1137 case WM8962_ADCR_RETUNE_C22_0:
1138 case WM8962_ADCR_RETUNE_C23_1:
1139 case WM8962_ADCR_RETUNE_C23_0:
1140 case WM8962_ADCR_RETUNE_C24_1:
1141 case WM8962_ADCR_RETUNE_C24_0:
1142 case WM8962_ADCR_RETUNE_C25_1:
1143 case WM8962_ADCR_RETUNE_C25_0:
1144 case WM8962_ADCR_RETUNE_C26_1:
1145 case WM8962_ADCR_RETUNE_C26_0:
1146 case WM8962_ADCR_RETUNE_C27_1:
1147 case WM8962_ADCR_RETUNE_C27_0:
1148 case WM8962_ADCR_RETUNE_C28_1:
1149 case WM8962_ADCR_RETUNE_C28_0:
1150 case WM8962_ADCR_RETUNE_C29_1:
1151 case WM8962_ADCR_RETUNE_C29_0:
1152 case WM8962_ADCR_RETUNE_C30_1:
1153 case WM8962_ADCR_RETUNE_C30_0:
1154 case WM8962_ADCR_RETUNE_C31_1:
1155 case WM8962_ADCR_RETUNE_C31_0:
1156 case WM8962_ADCR_RETUNE_C32_1:
1157 case WM8962_ADCR_RETUNE_C32_0:
1158 case WM8962_DACL_RETUNE_C1_1:
1159 case WM8962_DACL_RETUNE_C1_0:
1160 case WM8962_DACL_RETUNE_C2_1:
1161 case WM8962_DACL_RETUNE_C2_0:
1162 case WM8962_DACL_RETUNE_C3_1:
1163 case WM8962_DACL_RETUNE_C3_0:
1164 case WM8962_DACL_RETUNE_C4_1:
1165 case WM8962_DACL_RETUNE_C4_0:
1166 case WM8962_DACL_RETUNE_C5_1:
1167 case WM8962_DACL_RETUNE_C5_0:
1168 case WM8962_DACL_RETUNE_C6_1:
1169 case WM8962_DACL_RETUNE_C6_0:
1170 case WM8962_DACL_RETUNE_C7_1:
1171 case WM8962_DACL_RETUNE_C7_0:
1172 case WM8962_DACL_RETUNE_C8_1:
1173 case WM8962_DACL_RETUNE_C8_0:
1174 case WM8962_DACL_RETUNE_C9_1:
1175 case WM8962_DACL_RETUNE_C9_0:
1176 case WM8962_DACL_RETUNE_C10_1:
1177 case WM8962_DACL_RETUNE_C10_0:
1178 case WM8962_DACL_RETUNE_C11_1:
1179 case WM8962_DACL_RETUNE_C11_0:
1180 case WM8962_DACL_RETUNE_C12_1:
1181 case WM8962_DACL_RETUNE_C12_0:
1182 case WM8962_DACL_RETUNE_C13_1:
1183 case WM8962_DACL_RETUNE_C13_0:
1184 case WM8962_DACL_RETUNE_C14_1:
1185 case WM8962_DACL_RETUNE_C14_0:
1186 case WM8962_DACL_RETUNE_C15_1:
1187 case WM8962_DACL_RETUNE_C15_0:
1188 case WM8962_DACL_RETUNE_C16_1:
1189 case WM8962_DACL_RETUNE_C16_0:
1190 case WM8962_DACL_RETUNE_C17_1:
1191 case WM8962_DACL_RETUNE_C17_0:
1192 case WM8962_DACL_RETUNE_C18_1:
1193 case WM8962_DACL_RETUNE_C18_0:
1194 case WM8962_DACL_RETUNE_C19_1:
1195 case WM8962_DACL_RETUNE_C19_0:
1196 case WM8962_DACL_RETUNE_C20_1:
1197 case WM8962_DACL_RETUNE_C20_0:
1198 case WM8962_DACL_RETUNE_C21_1:
1199 case WM8962_DACL_RETUNE_C21_0:
1200 case WM8962_DACL_RETUNE_C22_1:
1201 case WM8962_DACL_RETUNE_C22_0:
1202 case WM8962_DACL_RETUNE_C23_1:
1203 case WM8962_DACL_RETUNE_C23_0:
1204 case WM8962_DACL_RETUNE_C24_1:
1205 case WM8962_DACL_RETUNE_C24_0:
1206 case WM8962_DACL_RETUNE_C25_1:
1207 case WM8962_DACL_RETUNE_C25_0:
1208 case WM8962_DACL_RETUNE_C26_1:
1209 case WM8962_DACL_RETUNE_C26_0:
1210 case WM8962_DACL_RETUNE_C27_1:
1211 case WM8962_DACL_RETUNE_C27_0:
1212 case WM8962_DACL_RETUNE_C28_1:
1213 case WM8962_DACL_RETUNE_C28_0:
1214 case WM8962_DACL_RETUNE_C29_1:
1215 case WM8962_DACL_RETUNE_C29_0:
1216 case WM8962_DACL_RETUNE_C30_1:
1217 case WM8962_DACL_RETUNE_C30_0:
1218 case WM8962_DACL_RETUNE_C31_1:
1219 case WM8962_DACL_RETUNE_C31_0:
1220 case WM8962_DACL_RETUNE_C32_1:
1221 case WM8962_DACL_RETUNE_C32_0:
1222 case WM8962_RETUNEDAC_PG2_1:
1223 case WM8962_RETUNEDAC_PG2_0:
1224 case WM8962_RETUNEDAC_PG_1:
1225 case WM8962_RETUNEDAC_PG_0:
1226 case WM8962_DACR_RETUNE_C1_1:
1227 case WM8962_DACR_RETUNE_C1_0:
1228 case WM8962_DACR_RETUNE_C2_1:
1229 case WM8962_DACR_RETUNE_C2_0:
1230 case WM8962_DACR_RETUNE_C3_1:
1231 case WM8962_DACR_RETUNE_C3_0:
1232 case WM8962_DACR_RETUNE_C4_1:
1233 case WM8962_DACR_RETUNE_C4_0:
1234 case WM8962_DACR_RETUNE_C5_1:
1235 case WM8962_DACR_RETUNE_C5_0:
1236 case WM8962_DACR_RETUNE_C6_1:
1237 case WM8962_DACR_RETUNE_C6_0:
1238 case WM8962_DACR_RETUNE_C7_1:
1239 case WM8962_DACR_RETUNE_C7_0:
1240 case WM8962_DACR_RETUNE_C8_1:
1241 case WM8962_DACR_RETUNE_C8_0:
1242 case WM8962_DACR_RETUNE_C9_1:
1243 case WM8962_DACR_RETUNE_C9_0:
1244 case WM8962_DACR_RETUNE_C10_1:
1245 case WM8962_DACR_RETUNE_C10_0:
1246 case WM8962_DACR_RETUNE_C11_1:
1247 case WM8962_DACR_RETUNE_C11_0:
1248 case WM8962_DACR_RETUNE_C12_1:
1249 case WM8962_DACR_RETUNE_C12_0:
1250 case WM8962_DACR_RETUNE_C13_1:
1251 case WM8962_DACR_RETUNE_C13_0:
1252 case WM8962_DACR_RETUNE_C14_1:
1253 case WM8962_DACR_RETUNE_C14_0:
1254 case WM8962_DACR_RETUNE_C15_1:
1255 case WM8962_DACR_RETUNE_C15_0:
1256 case WM8962_DACR_RETUNE_C16_1:
1257 case WM8962_DACR_RETUNE_C16_0:
1258 case WM8962_DACR_RETUNE_C17_1:
1259 case WM8962_DACR_RETUNE_C17_0:
1260 case WM8962_DACR_RETUNE_C18_1:
1261 case WM8962_DACR_RETUNE_C18_0:
1262 case WM8962_DACR_RETUNE_C19_1:
1263 case WM8962_DACR_RETUNE_C19_0:
1264 case WM8962_DACR_RETUNE_C20_1:
1265 case WM8962_DACR_RETUNE_C20_0:
1266 case WM8962_DACR_RETUNE_C21_1:
1267 case WM8962_DACR_RETUNE_C21_0:
1268 case WM8962_DACR_RETUNE_C22_1:
1269 case WM8962_DACR_RETUNE_C22_0:
1270 case WM8962_DACR_RETUNE_C23_1:
1271 case WM8962_DACR_RETUNE_C23_0:
1272 case WM8962_DACR_RETUNE_C24_1:
1273 case WM8962_DACR_RETUNE_C24_0:
1274 case WM8962_DACR_RETUNE_C25_1:
1275 case WM8962_DACR_RETUNE_C25_0:
1276 case WM8962_DACR_RETUNE_C26_1:
1277 case WM8962_DACR_RETUNE_C26_0:
1278 case WM8962_DACR_RETUNE_C27_1:
1279 case WM8962_DACR_RETUNE_C27_0:
1280 case WM8962_DACR_RETUNE_C28_1:
1281 case WM8962_DACR_RETUNE_C28_0:
1282 case WM8962_DACR_RETUNE_C29_1:
1283 case WM8962_DACR_RETUNE_C29_0:
1284 case WM8962_DACR_RETUNE_C30_1:
1285 case WM8962_DACR_RETUNE_C30_0:
1286 case WM8962_DACR_RETUNE_C31_1:
1287 case WM8962_DACR_RETUNE_C31_0:
1288 case WM8962_DACR_RETUNE_C32_1:
1289 case WM8962_DACR_RETUNE_C32_0:
1290 case WM8962_VSS_XHD2_1:
1291 case WM8962_VSS_XHD2_0:
1292 case WM8962_VSS_XHD3_1:
1293 case WM8962_VSS_XHD3_0:
1294 case WM8962_VSS_XHN1_1:
1295 case WM8962_VSS_XHN1_0:
1296 case WM8962_VSS_XHN2_1:
1297 case WM8962_VSS_XHN2_0:
1298 case WM8962_VSS_XHN3_1:
1299 case WM8962_VSS_XHN3_0:
1300 case WM8962_VSS_XLA_1:
1301 case WM8962_VSS_XLA_0:
1302 case WM8962_VSS_XLB_1:
1303 case WM8962_VSS_XLB_0:
1304 case WM8962_VSS_XLG_1:
1305 case WM8962_VSS_XLG_0:
1306 case WM8962_VSS_PG2_1:
1307 case WM8962_VSS_PG2_0:
1308 case WM8962_VSS_PG_1:
1309 case WM8962_VSS_PG_0:
1310 case WM8962_VSS_XTD1_1:
1311 case WM8962_VSS_XTD1_0:
1312 case WM8962_VSS_XTD2_1:
1313 case WM8962_VSS_XTD2_0:
1314 case WM8962_VSS_XTD3_1:
1315 case WM8962_VSS_XTD3_0:
1316 case WM8962_VSS_XTD4_1:
1317 case WM8962_VSS_XTD4_0:
1318 case WM8962_VSS_XTD5_1:
1319 case WM8962_VSS_XTD5_0:
1320 case WM8962_VSS_XTD6_1:
1321 case WM8962_VSS_XTD6_0:
1322 case WM8962_VSS_XTD7_1:
1323 case WM8962_VSS_XTD7_0:
1324 case WM8962_VSS_XTD8_1:
1325 case WM8962_VSS_XTD8_0:
1326 case WM8962_VSS_XTD9_1:
1327 case WM8962_VSS_XTD9_0:
1328 case WM8962_VSS_XTD10_1:
1329 case WM8962_VSS_XTD10_0:
1330 case WM8962_VSS_XTD11_1:
1331 case WM8962_VSS_XTD11_0:
1332 case WM8962_VSS_XTD12_1:
1333 case WM8962_VSS_XTD12_0:
1334 case WM8962_VSS_XTD13_1:
1335 case WM8962_VSS_XTD13_0:
1336 case WM8962_VSS_XTD14_1:
1337 case WM8962_VSS_XTD14_0:
1338 case WM8962_VSS_XTD15_1:
1339 case WM8962_VSS_XTD15_0:
1340 case WM8962_VSS_XTD16_1:
1341 case WM8962_VSS_XTD16_0:
1342 case WM8962_VSS_XTD17_1:
1343 case WM8962_VSS_XTD17_0:
1344 case WM8962_VSS_XTD18_1:
1345 case WM8962_VSS_XTD18_0:
1346 case WM8962_VSS_XTD19_1:
1347 case WM8962_VSS_XTD19_0:
1348 case WM8962_VSS_XTD20_1:
1349 case WM8962_VSS_XTD20_0:
1350 case WM8962_VSS_XTD21_1:
1351 case WM8962_VSS_XTD21_0:
1352 case WM8962_VSS_XTD22_1:
1353 case WM8962_VSS_XTD22_0:
1354 case WM8962_VSS_XTD23_1:
1355 case WM8962_VSS_XTD23_0:
1356 case WM8962_VSS_XTD24_1:
1357 case WM8962_VSS_XTD24_0:
1358 case WM8962_VSS_XTD25_1:
1359 case WM8962_VSS_XTD25_0:
1360 case WM8962_VSS_XTD26_1:
1361 case WM8962_VSS_XTD26_0:
1362 case WM8962_VSS_XTD27_1:
1363 case WM8962_VSS_XTD27_0:
1364 case WM8962_VSS_XTD28_1:
1365 case WM8962_VSS_XTD28_0:
1366 case WM8962_VSS_XTD29_1:
1367 case WM8962_VSS_XTD29_0:
1368 case WM8962_VSS_XTD30_1:
1369 case WM8962_VSS_XTD30_0:
1370 case WM8962_VSS_XTD31_1:
1371 case WM8962_VSS_XTD31_0:
1372 case WM8962_VSS_XTD32_1:
1373 case WM8962_VSS_XTD32_0:
1374 case WM8962_VSS_XTS1_1:
1375 case WM8962_VSS_XTS1_0:
1376 case WM8962_VSS_XTS2_1:
1377 case WM8962_VSS_XTS2_0:
1378 case WM8962_VSS_XTS3_1:
1379 case WM8962_VSS_XTS3_0:
1380 case WM8962_VSS_XTS4_1:
1381 case WM8962_VSS_XTS4_0:
1382 case WM8962_VSS_XTS5_1:
1383 case WM8962_VSS_XTS5_0:
1384 case WM8962_VSS_XTS6_1:
1385 case WM8962_VSS_XTS6_0:
1386 case WM8962_VSS_XTS7_1:
1387 case WM8962_VSS_XTS7_0:
1388 case WM8962_VSS_XTS8_1:
1389 case WM8962_VSS_XTS8_0:
1390 case WM8962_VSS_XTS9_1:
1391 case WM8962_VSS_XTS9_0:
1392 case WM8962_VSS_XTS10_1:
1393 case WM8962_VSS_XTS10_0:
1394 case WM8962_VSS_XTS11_1:
1395 case WM8962_VSS_XTS11_0:
1396 case WM8962_VSS_XTS12_1:
1397 case WM8962_VSS_XTS12_0:
1398 case WM8962_VSS_XTS13_1:
1399 case WM8962_VSS_XTS13_0:
1400 case WM8962_VSS_XTS14_1:
1401 case WM8962_VSS_XTS14_0:
1402 case WM8962_VSS_XTS15_1:
1403 case WM8962_VSS_XTS15_0:
1404 case WM8962_VSS_XTS16_1:
1405 case WM8962_VSS_XTS16_0:
1406 case WM8962_VSS_XTS17_1:
1407 case WM8962_VSS_XTS17_0:
1408 case WM8962_VSS_XTS18_1:
1409 case WM8962_VSS_XTS18_0:
1410 case WM8962_VSS_XTS19_1:
1411 case WM8962_VSS_XTS19_0:
1412 case WM8962_VSS_XTS20_1:
1413 case WM8962_VSS_XTS20_0:
1414 case WM8962_VSS_XTS21_1:
1415 case WM8962_VSS_XTS21_0:
1416 case WM8962_VSS_XTS22_1:
1417 case WM8962_VSS_XTS22_0:
1418 case WM8962_VSS_XTS23_1:
1419 case WM8962_VSS_XTS23_0:
1420 case WM8962_VSS_XTS24_1:
1421 case WM8962_VSS_XTS24_0:
1422 case WM8962_VSS_XTS25_1:
1423 case WM8962_VSS_XTS25_0:
1424 case WM8962_VSS_XTS26_1:
1425 case WM8962_VSS_XTS26_0:
1426 case WM8962_VSS_XTS27_1:
1427 case WM8962_VSS_XTS27_0:
1428 case WM8962_VSS_XTS28_1:
1429 case WM8962_VSS_XTS28_0:
1430 case WM8962_VSS_XTS29_1:
1431 case WM8962_VSS_XTS29_0:
1432 case WM8962_VSS_XTS30_1:
1433 case WM8962_VSS_XTS30_0:
1434 case WM8962_VSS_XTS31_1:
1435 case WM8962_VSS_XTS31_0:
1436 case WM8962_VSS_XTS32_1:
1437 case WM8962_VSS_XTS32_0:
1438 return true;
1439 default:
1440 return false;
1441 }
1442}
1443
1444static int wm8962_reset(struct wm8962_priv *wm8962)
1445{
1446 int ret;
1447
1448 ret = regmap_write(wm8962->regmap, WM8962_SOFTWARE_RESET, 0x6243);
1449 if (ret != 0)
1450 return ret;
1451
1452 return regmap_write(wm8962->regmap, WM8962_PLL_SOFTWARE_RESET, 0);
1453}
1454
1455static const DECLARE_TLV_DB_SCALE(inpga_tlv, -2325, 75, 0);
1456static const DECLARE_TLV_DB_SCALE(mixin_tlv, -1500, 300, 0);
1457static const unsigned int mixinpga_tlv[] = {
1458 TLV_DB_RANGE_HEAD(5),
1459 0, 1, TLV_DB_SCALE_ITEM(0, 600, 0),
1460 2, 2, TLV_DB_SCALE_ITEM(1300, 1300, 0),
1461 3, 4, TLV_DB_SCALE_ITEM(1800, 200, 0),
1462 5, 5, TLV_DB_SCALE_ITEM(2400, 0, 0),
1463 6, 7, TLV_DB_SCALE_ITEM(2700, 300, 0),
1464};
1465static const DECLARE_TLV_DB_SCALE(beep_tlv, -9600, 600, 1);
1466static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
1467static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
1468static const DECLARE_TLV_DB_SCALE(inmix_tlv, -600, 600, 0);
1469static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
1470static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
1471static const DECLARE_TLV_DB_SCALE(hp_tlv, -700, 100, 0);
1472static const unsigned int classd_tlv[] = {
1473 TLV_DB_RANGE_HEAD(2),
1474 0, 6, TLV_DB_SCALE_ITEM(0, 150, 0),
1475 7, 7, TLV_DB_SCALE_ITEM(1200, 0, 0),
1476};
1477static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
1478
1479static int wm8962_dsp2_write_config(struct snd_soc_codec *codec)
1480{
1481 return regcache_sync_region(codec->control_data,
1482 WM8962_HDBASS_AI_1, WM8962_MAX_REGISTER);
1483}
1484
1485static int wm8962_dsp2_set_enable(struct snd_soc_codec *codec, u16 val)
1486{
1487 u16 adcl = snd_soc_read(codec, WM8962_LEFT_ADC_VOLUME);
1488 u16 adcr = snd_soc_read(codec, WM8962_RIGHT_ADC_VOLUME);
1489 u16 dac = snd_soc_read(codec, WM8962_ADC_DAC_CONTROL_1);
1490
1491 /* Mute the ADCs and DACs */
1492 snd_soc_write(codec, WM8962_LEFT_ADC_VOLUME, 0);
1493 snd_soc_write(codec, WM8962_RIGHT_ADC_VOLUME, WM8962_ADC_VU);
1494 snd_soc_update_bits(codec, WM8962_ADC_DAC_CONTROL_1,
1495 WM8962_DAC_MUTE, WM8962_DAC_MUTE);
1496
1497 snd_soc_write(codec, WM8962_SOUNDSTAGE_ENABLES_0, val);
1498
1499 /* Restore the ADCs and DACs */
1500 snd_soc_write(codec, WM8962_LEFT_ADC_VOLUME, adcl);
1501 snd_soc_write(codec, WM8962_RIGHT_ADC_VOLUME, adcr);
1502 snd_soc_update_bits(codec, WM8962_ADC_DAC_CONTROL_1,
1503 WM8962_DAC_MUTE, dac);
1504
1505 return 0;
1506}
1507
1508static int wm8962_dsp2_start(struct snd_soc_codec *codec)
1509{
1510 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1511
1512 wm8962_dsp2_write_config(codec);
1513
1514 snd_soc_write(codec, WM8962_DSP2_EXECCONTROL, WM8962_DSP2_RUNR);
1515
1516 wm8962_dsp2_set_enable(codec, wm8962->dsp2_ena);
1517
1518 return 0;
1519}
1520
1521static int wm8962_dsp2_stop(struct snd_soc_codec *codec)
1522{
1523 wm8962_dsp2_set_enable(codec, 0);
1524
1525 snd_soc_write(codec, WM8962_DSP2_EXECCONTROL, WM8962_DSP2_STOP);
1526
1527 return 0;
1528}
1529
1530#define WM8962_DSP2_ENABLE(xname, xshift) \
1531{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1532 .info = wm8962_dsp2_ena_info, \
1533 .get = wm8962_dsp2_ena_get, .put = wm8962_dsp2_ena_put, \
1534 .private_value = xshift }
1535
1536static int wm8962_dsp2_ena_info(struct snd_kcontrol *kcontrol,
1537 struct snd_ctl_elem_info *uinfo)
1538{
1539 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1540
1541 uinfo->count = 1;
1542 uinfo->value.integer.min = 0;
1543 uinfo->value.integer.max = 1;
1544
1545 return 0;
1546}
1547
1548static int wm8962_dsp2_ena_get(struct snd_kcontrol *kcontrol,
1549 struct snd_ctl_elem_value *ucontrol)
1550{
1551 int shift = kcontrol->private_value;
1552 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1553 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1554
1555 ucontrol->value.integer.value[0] = !!(wm8962->dsp2_ena & 1 << shift);
1556
1557 return 0;
1558}
1559
1560static int wm8962_dsp2_ena_put(struct snd_kcontrol *kcontrol,
1561 struct snd_ctl_elem_value *ucontrol)
1562{
1563 int shift = kcontrol->private_value;
1564 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1565 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1566 int old = wm8962->dsp2_ena;
1567 int ret = 0;
1568 int dsp2_running = snd_soc_read(codec, WM8962_DSP2_POWER_MANAGEMENT) &
1569 WM8962_DSP2_ENA;
1570
1571 mutex_lock(&codec->mutex);
1572
1573 if (ucontrol->value.integer.value[0])
1574 wm8962->dsp2_ena |= 1 << shift;
1575 else
1576 wm8962->dsp2_ena &= ~(1 << shift);
1577
1578 if (wm8962->dsp2_ena == old)
1579 goto out;
1580
1581 ret = 1;
1582
1583 if (dsp2_running) {
1584 if (wm8962->dsp2_ena)
1585 wm8962_dsp2_set_enable(codec, wm8962->dsp2_ena);
1586 else
1587 wm8962_dsp2_stop(codec);
1588 }
1589
1590out:
1591 mutex_unlock(&codec->mutex);
1592
1593 return ret;
1594}
1595
1596/* The VU bits for the headphones are in a different register to the mute
1597 * bits and only take effect on the PGA if it is actually powered.
1598 */
1599static int wm8962_put_hp_sw(struct snd_kcontrol *kcontrol,
1600 struct snd_ctl_elem_value *ucontrol)
1601{
1602 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1603 u16 *reg_cache = codec->reg_cache;
1604 int ret;
1605
1606 /* Apply the update (if any) */
1607 ret = snd_soc_put_volsw(kcontrol, ucontrol);
1608 if (ret == 0)
1609 return 0;
1610
1611 /* If the left PGA is enabled hit that VU bit... */
1612 if (snd_soc_read(codec, WM8962_PWR_MGMT_2) & WM8962_HPOUTL_PGA_ENA)
1613 return snd_soc_write(codec, WM8962_HPOUTL_VOLUME,
1614 reg_cache[WM8962_HPOUTL_VOLUME]);
1615
1616 /* ...otherwise the right. The VU is stereo. */
1617 if (snd_soc_read(codec, WM8962_PWR_MGMT_2) & WM8962_HPOUTR_PGA_ENA)
1618 return snd_soc_write(codec, WM8962_HPOUTR_VOLUME,
1619 reg_cache[WM8962_HPOUTR_VOLUME]);
1620
1621 return 0;
1622}
1623
1624/* The VU bits for the speakers are in a different register to the mute
1625 * bits and only take effect on the PGA if it is actually powered.
1626 */
1627static int wm8962_put_spk_sw(struct snd_kcontrol *kcontrol,
1628 struct snd_ctl_elem_value *ucontrol)
1629{
1630 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1631 int ret;
1632
1633 /* Apply the update (if any) */
1634 ret = snd_soc_put_volsw(kcontrol, ucontrol);
1635 if (ret == 0)
1636 return 0;
1637
1638 /* If the left PGA is enabled hit that VU bit... */
1639 ret = snd_soc_read(codec, WM8962_PWR_MGMT_2);
1640 if (ret & WM8962_SPKOUTL_PGA_ENA) {
1641 snd_soc_write(codec, WM8962_SPKOUTL_VOLUME,
1642 snd_soc_read(codec, WM8962_SPKOUTL_VOLUME));
1643 return 1;
1644 }
1645
1646 /* ...otherwise the right. The VU is stereo. */
1647 if (ret & WM8962_SPKOUTR_PGA_ENA)
1648 snd_soc_write(codec, WM8962_SPKOUTR_VOLUME,
1649 snd_soc_read(codec, WM8962_SPKOUTR_VOLUME));
1650
1651 return 1;
1652}
1653
1654static const char *cap_hpf_mode_text[] = {
1655 "Hi-fi", "Application"
1656};
1657
1658static const struct soc_enum cap_hpf_mode =
1659 SOC_ENUM_SINGLE(WM8962_ADC_DAC_CONTROL_2, 10, 2, cap_hpf_mode_text);
1660
1661
1662static const char *cap_lhpf_mode_text[] = {
1663 "LPF", "HPF"
1664};
1665
1666static const struct soc_enum cap_lhpf_mode =
1667 SOC_ENUM_SINGLE(WM8962_LHPF1, 1, 2, cap_lhpf_mode_text);
1668
1669static const struct snd_kcontrol_new wm8962_snd_controls[] = {
1670SOC_DOUBLE("Input Mixer Switch", WM8962_INPUT_MIXER_CONTROL_1, 3, 2, 1, 1),
1671
1672SOC_SINGLE_TLV("MIXINL IN2L Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 6, 7, 0,
1673 mixin_tlv),
1674SOC_SINGLE_TLV("MIXINL PGA Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 3, 7, 0,
1675 mixinpga_tlv),
1676SOC_SINGLE_TLV("MIXINL IN3L Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 0, 7, 0,
1677 mixin_tlv),
1678
1679SOC_SINGLE_TLV("MIXINR IN2R Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 6, 7, 0,
1680 mixin_tlv),
1681SOC_SINGLE_TLV("MIXINR PGA Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 3, 7, 0,
1682 mixinpga_tlv),
1683SOC_SINGLE_TLV("MIXINR IN3R Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 0, 7, 0,
1684 mixin_tlv),
1685
1686SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8962_LEFT_ADC_VOLUME,
1687 WM8962_RIGHT_ADC_VOLUME, 1, 127, 0, digital_tlv),
1688SOC_DOUBLE_R_TLV("Capture Volume", WM8962_LEFT_INPUT_VOLUME,
1689 WM8962_RIGHT_INPUT_VOLUME, 0, 63, 0, inpga_tlv),
1690SOC_DOUBLE_R("Capture Switch", WM8962_LEFT_INPUT_VOLUME,
1691 WM8962_RIGHT_INPUT_VOLUME, 7, 1, 1),
1692SOC_DOUBLE_R("Capture ZC Switch", WM8962_LEFT_INPUT_VOLUME,
1693 WM8962_RIGHT_INPUT_VOLUME, 6, 1, 1),
1694SOC_SINGLE("Capture HPF Switch", WM8962_ADC_DAC_CONTROL_1, 0, 1, 1),
1695SOC_ENUM("Capture HPF Mode", cap_hpf_mode),
1696SOC_SINGLE("Capture HPF Cutoff", WM8962_ADC_DAC_CONTROL_2, 7, 7, 0),
1697SOC_SINGLE("Capture LHPF Switch", WM8962_LHPF1, 0, 1, 0),
1698SOC_ENUM("Capture LHPF Mode", cap_lhpf_mode),
1699
1700SOC_DOUBLE_R_TLV("Sidetone Volume", WM8962_DAC_DSP_MIXING_1,
1701 WM8962_DAC_DSP_MIXING_2, 4, 12, 0, st_tlv),
1702
1703SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8962_LEFT_DAC_VOLUME,
1704 WM8962_RIGHT_DAC_VOLUME, 1, 127, 0, digital_tlv),
1705SOC_SINGLE("DAC High Performance Switch", WM8962_ADC_DAC_CONTROL_2, 0, 1, 0),
1706SOC_SINGLE("DAC L/R Swap Switch", WM8962_AUDIO_INTERFACE_0, 5, 1, 0),
1707SOC_SINGLE("ADC L/R Swap Switch", WM8962_AUDIO_INTERFACE_0, 8, 1, 0),
1708
1709SOC_SINGLE("ADC High Performance Switch", WM8962_ADDITIONAL_CONTROL_1,
1710 5, 1, 0),
1711
1712SOC_SINGLE_TLV("Beep Volume", WM8962_BEEP_GENERATOR_1, 4, 15, 0, beep_tlv),
1713
1714SOC_DOUBLE_R_TLV("Headphone Volume", WM8962_HPOUTL_VOLUME,
1715 WM8962_HPOUTR_VOLUME, 0, 127, 0, out_tlv),
1716SOC_DOUBLE_EXT("Headphone Switch", WM8962_PWR_MGMT_2, 1, 0, 1, 1,
1717 snd_soc_get_volsw, wm8962_put_hp_sw),
1718SOC_DOUBLE_R("Headphone ZC Switch", WM8962_HPOUTL_VOLUME, WM8962_HPOUTR_VOLUME,
1719 7, 1, 0),
1720SOC_DOUBLE_TLV("Headphone Aux Volume", WM8962_ANALOGUE_HP_2, 3, 6, 7, 0,
1721 hp_tlv),
1722
1723SOC_DOUBLE_R("Headphone Mixer Switch", WM8962_HEADPHONE_MIXER_3,
1724 WM8962_HEADPHONE_MIXER_4, 8, 1, 1),
1725
1726SOC_SINGLE_TLV("HPMIXL IN4L Volume", WM8962_HEADPHONE_MIXER_3,
1727 3, 7, 0, bypass_tlv),
1728SOC_SINGLE_TLV("HPMIXL IN4R Volume", WM8962_HEADPHONE_MIXER_3,
1729 0, 7, 0, bypass_tlv),
1730SOC_SINGLE_TLV("HPMIXL MIXINL Volume", WM8962_HEADPHONE_MIXER_3,
1731 7, 1, 1, inmix_tlv),
1732SOC_SINGLE_TLV("HPMIXL MIXINR Volume", WM8962_HEADPHONE_MIXER_3,
1733 6, 1, 1, inmix_tlv),
1734
1735SOC_SINGLE_TLV("HPMIXR IN4L Volume", WM8962_HEADPHONE_MIXER_4,
1736 3, 7, 0, bypass_tlv),
1737SOC_SINGLE_TLV("HPMIXR IN4R Volume", WM8962_HEADPHONE_MIXER_4,
1738 0, 7, 0, bypass_tlv),
1739SOC_SINGLE_TLV("HPMIXR MIXINL Volume", WM8962_HEADPHONE_MIXER_4,
1740 7, 1, 1, inmix_tlv),
1741SOC_SINGLE_TLV("HPMIXR MIXINR Volume", WM8962_HEADPHONE_MIXER_4,
1742 6, 1, 1, inmix_tlv),
1743
1744SOC_SINGLE_TLV("Speaker Boost Volume", WM8962_CLASS_D_CONTROL_2, 0, 7, 0,
1745 classd_tlv),
1746
1747SOC_SINGLE("EQ Switch", WM8962_EQ1, WM8962_EQ_ENA_SHIFT, 1, 0),
1748SOC_DOUBLE_R_TLV("EQ1 Volume", WM8962_EQ2, WM8962_EQ22,
1749 WM8962_EQL_B1_GAIN_SHIFT, 31, 0, eq_tlv),
1750SOC_DOUBLE_R_TLV("EQ2 Volume", WM8962_EQ2, WM8962_EQ22,
1751 WM8962_EQL_B2_GAIN_SHIFT, 31, 0, eq_tlv),
1752SOC_DOUBLE_R_TLV("EQ3 Volume", WM8962_EQ2, WM8962_EQ22,
1753 WM8962_EQL_B3_GAIN_SHIFT, 31, 0, eq_tlv),
1754SOC_DOUBLE_R_TLV("EQ4 Volume", WM8962_EQ3, WM8962_EQ23,
1755 WM8962_EQL_B4_GAIN_SHIFT, 31, 0, eq_tlv),
1756SOC_DOUBLE_R_TLV("EQ5 Volume", WM8962_EQ3, WM8962_EQ23,
1757 WM8962_EQL_B5_GAIN_SHIFT, 31, 0, eq_tlv),
1758
1759SOC_SINGLE("3D Switch", WM8962_THREED1, 0, 1, 0),
1760SND_SOC_BYTES_MASK("3D Coefficients", WM8962_THREED1, 4, WM8962_THREED_ENA),
1761
1762SOC_SINGLE("DF1 Switch", WM8962_DF1, 0, 1, 0),
1763SND_SOC_BYTES_MASK("DF1 Coefficients", WM8962_DF1, 7, WM8962_DF1_ENA),
1764
1765SOC_SINGLE("DRC Switch", WM8962_DRC_1, 0, 1, 0),
1766SND_SOC_BYTES_MASK("DRC Coefficients", WM8962_DRC_1, 5, WM8962_DRC_ENA),
1767
1768WM8962_DSP2_ENABLE("VSS Switch", WM8962_VSS_ENA_SHIFT),
1769SND_SOC_BYTES("VSS Coefficients", WM8962_VSS_XHD2_1, 148),
1770WM8962_DSP2_ENABLE("HPF1 Switch", WM8962_HPF1_ENA_SHIFT),
1771WM8962_DSP2_ENABLE("HPF2 Switch", WM8962_HPF2_ENA_SHIFT),
1772SND_SOC_BYTES("HPF Coefficients", WM8962_LHPF2, 1),
1773WM8962_DSP2_ENABLE("HD Bass Switch", WM8962_HDBASS_ENA_SHIFT),
1774SND_SOC_BYTES("HD Bass Coefficients", WM8962_HDBASS_AI_1, 30),
1775};
1776
1777static const struct snd_kcontrol_new wm8962_spk_mono_controls[] = {
1778SOC_SINGLE_TLV("Speaker Volume", WM8962_SPKOUTL_VOLUME, 0, 127, 0, out_tlv),
1779SOC_SINGLE_EXT("Speaker Switch", WM8962_CLASS_D_CONTROL_1, 1, 1, 1,
1780 snd_soc_get_volsw, wm8962_put_spk_sw),
1781SOC_SINGLE("Speaker ZC Switch", WM8962_SPKOUTL_VOLUME, 7, 1, 0),
1782
1783SOC_SINGLE("Speaker Mixer Switch", WM8962_SPEAKER_MIXER_3, 8, 1, 1),
1784SOC_SINGLE_TLV("Speaker Mixer IN4L Volume", WM8962_SPEAKER_MIXER_3,
1785 3, 7, 0, bypass_tlv),
1786SOC_SINGLE_TLV("Speaker Mixer IN4R Volume", WM8962_SPEAKER_MIXER_3,
1787 0, 7, 0, bypass_tlv),
1788SOC_SINGLE_TLV("Speaker Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_3,
1789 7, 1, 1, inmix_tlv),
1790SOC_SINGLE_TLV("Speaker Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_3,
1791 6, 1, 1, inmix_tlv),
1792SOC_SINGLE_TLV("Speaker Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
1793 7, 1, 0, inmix_tlv),
1794SOC_SINGLE_TLV("Speaker Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
1795 6, 1, 0, inmix_tlv),
1796};
1797
1798static const struct snd_kcontrol_new wm8962_spk_stereo_controls[] = {
1799SOC_DOUBLE_R_TLV("Speaker Volume", WM8962_SPKOUTL_VOLUME,
1800 WM8962_SPKOUTR_VOLUME, 0, 127, 0, out_tlv),
1801SOC_DOUBLE_EXT("Speaker Switch", WM8962_CLASS_D_CONTROL_1, 1, 0, 1, 1,
1802 snd_soc_get_volsw, wm8962_put_spk_sw),
1803SOC_DOUBLE_R("Speaker ZC Switch", WM8962_SPKOUTL_VOLUME, WM8962_SPKOUTR_VOLUME,
1804 7, 1, 0),
1805
1806SOC_DOUBLE_R("Speaker Mixer Switch", WM8962_SPEAKER_MIXER_3,
1807 WM8962_SPEAKER_MIXER_4, 8, 1, 1),
1808
1809SOC_SINGLE_TLV("SPKOUTL Mixer IN4L Volume", WM8962_SPEAKER_MIXER_3,
1810 3, 7, 0, bypass_tlv),
1811SOC_SINGLE_TLV("SPKOUTL Mixer IN4R Volume", WM8962_SPEAKER_MIXER_3,
1812 0, 7, 0, bypass_tlv),
1813SOC_SINGLE_TLV("SPKOUTL Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_3,
1814 7, 1, 1, inmix_tlv),
1815SOC_SINGLE_TLV("SPKOUTL Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_3,
1816 6, 1, 1, inmix_tlv),
1817SOC_SINGLE_TLV("SPKOUTL Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
1818 7, 1, 0, inmix_tlv),
1819SOC_SINGLE_TLV("SPKOUTL Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
1820 6, 1, 0, inmix_tlv),
1821
1822SOC_SINGLE_TLV("SPKOUTR Mixer IN4L Volume", WM8962_SPEAKER_MIXER_4,
1823 3, 7, 0, bypass_tlv),
1824SOC_SINGLE_TLV("SPKOUTR Mixer IN4R Volume", WM8962_SPEAKER_MIXER_4,
1825 0, 7, 0, bypass_tlv),
1826SOC_SINGLE_TLV("SPKOUTR Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_4,
1827 7, 1, 1, inmix_tlv),
1828SOC_SINGLE_TLV("SPKOUTR Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_4,
1829 6, 1, 1, inmix_tlv),
1830SOC_SINGLE_TLV("SPKOUTR Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
1831 5, 1, 0, inmix_tlv),
1832SOC_SINGLE_TLV("SPKOUTR Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
1833 4, 1, 0, inmix_tlv),
1834};
1835
1836static int cp_event(struct snd_soc_dapm_widget *w,
1837 struct snd_kcontrol *kcontrol, int event)
1838{
1839 switch (event) {
1840 case SND_SOC_DAPM_POST_PMU:
1841 msleep(5);
1842 break;
1843
1844 default:
1845 BUG();
1846 return -EINVAL;
1847 }
1848
1849 return 0;
1850}
1851
1852static int hp_event(struct snd_soc_dapm_widget *w,
1853 struct snd_kcontrol *kcontrol, int event)
1854{
1855 struct snd_soc_codec *codec = w->codec;
1856 int timeout;
1857 int reg;
1858 int expected = (WM8962_DCS_STARTUP_DONE_HP1L |
1859 WM8962_DCS_STARTUP_DONE_HP1R);
1860
1861 switch (event) {
1862 case SND_SOC_DAPM_POST_PMU:
1863 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
1864 WM8962_HP1L_ENA | WM8962_HP1R_ENA,
1865 WM8962_HP1L_ENA | WM8962_HP1R_ENA);
1866 udelay(20);
1867
1868 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
1869 WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY,
1870 WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY);
1871
1872 /* Start the DC servo */
1873 snd_soc_update_bits(codec, WM8962_DC_SERVO_1,
1874 WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
1875 WM8962_HP1L_DCS_STARTUP |
1876 WM8962_HP1R_DCS_STARTUP,
1877 WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
1878 WM8962_HP1L_DCS_STARTUP |
1879 WM8962_HP1R_DCS_STARTUP);
1880
1881 /* Wait for it to complete, should be well under 100ms */
1882 timeout = 0;
1883 do {
1884 msleep(1);
1885 reg = snd_soc_read(codec, WM8962_DC_SERVO_6);
1886 if (reg < 0) {
1887 dev_err(codec->dev,
1888 "Failed to read DCS status: %d\n",
1889 reg);
1890 continue;
1891 }
1892 dev_dbg(codec->dev, "DCS status: %x\n", reg);
1893 } while (++timeout < 200 && (reg & expected) != expected);
1894
1895 if ((reg & expected) != expected)
1896 dev_err(codec->dev, "DC servo timed out\n");
1897 else
1898 dev_dbg(codec->dev, "DC servo complete after %dms\n",
1899 timeout);
1900
1901 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
1902 WM8962_HP1L_ENA_OUTP |
1903 WM8962_HP1R_ENA_OUTP,
1904 WM8962_HP1L_ENA_OUTP |
1905 WM8962_HP1R_ENA_OUTP);
1906 udelay(20);
1907
1908 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
1909 WM8962_HP1L_RMV_SHORT |
1910 WM8962_HP1R_RMV_SHORT,
1911 WM8962_HP1L_RMV_SHORT |
1912 WM8962_HP1R_RMV_SHORT);
1913 break;
1914
1915 case SND_SOC_DAPM_PRE_PMD:
1916 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
1917 WM8962_HP1L_RMV_SHORT |
1918 WM8962_HP1R_RMV_SHORT, 0);
1919
1920 udelay(20);
1921
1922 snd_soc_update_bits(codec, WM8962_DC_SERVO_1,
1923 WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
1924 WM8962_HP1L_DCS_STARTUP |
1925 WM8962_HP1R_DCS_STARTUP,
1926 0);
1927
1928 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
1929 WM8962_HP1L_ENA | WM8962_HP1R_ENA |
1930 WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY |
1931 WM8962_HP1L_ENA_OUTP |
1932 WM8962_HP1R_ENA_OUTP, 0);
1933
1934 break;
1935
1936 default:
1937 BUG();
1938 return -EINVAL;
1939
1940 }
1941
1942 return 0;
1943}
1944
1945/* VU bits for the output PGAs only take effect while the PGA is powered */
1946static int out_pga_event(struct snd_soc_dapm_widget *w,
1947 struct snd_kcontrol *kcontrol, int event)
1948{
1949 struct snd_soc_codec *codec = w->codec;
1950 int reg;
1951
1952 switch (w->shift) {
1953 case WM8962_HPOUTR_PGA_ENA_SHIFT:
1954 reg = WM8962_HPOUTR_VOLUME;
1955 break;
1956 case WM8962_HPOUTL_PGA_ENA_SHIFT:
1957 reg = WM8962_HPOUTL_VOLUME;
1958 break;
1959 case WM8962_SPKOUTR_PGA_ENA_SHIFT:
1960 reg = WM8962_SPKOUTR_VOLUME;
1961 break;
1962 case WM8962_SPKOUTL_PGA_ENA_SHIFT:
1963 reg = WM8962_SPKOUTL_VOLUME;
1964 break;
1965 default:
1966 BUG();
1967 return -EINVAL;
1968 }
1969
1970 switch (event) {
1971 case SND_SOC_DAPM_POST_PMU:
1972 return snd_soc_write(codec, reg, snd_soc_read(codec, reg));
1973 default:
1974 BUG();
1975 return -EINVAL;
1976 }
1977}
1978
1979static int dsp2_event(struct snd_soc_dapm_widget *w,
1980 struct snd_kcontrol *kcontrol, int event)
1981{
1982 struct snd_soc_codec *codec = w->codec;
1983 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1984
1985 switch (event) {
1986 case SND_SOC_DAPM_POST_PMU:
1987 if (wm8962->dsp2_ena)
1988 wm8962_dsp2_start(codec);
1989 break;
1990
1991 case SND_SOC_DAPM_PRE_PMD:
1992 if (wm8962->dsp2_ena)
1993 wm8962_dsp2_stop(codec);
1994 break;
1995
1996 default:
1997 BUG();
1998 return -EINVAL;
1999 }
2000
2001 return 0;
2002}
2003
2004static const char *st_text[] = { "None", "Left", "Right" };
2005
2006static const struct soc_enum str_enum =
2007 SOC_ENUM_SINGLE(WM8962_DAC_DSP_MIXING_1, 2, 3, st_text);
2008
2009static const struct snd_kcontrol_new str_mux =
2010 SOC_DAPM_ENUM("Right Sidetone", str_enum);
2011
2012static const struct soc_enum stl_enum =
2013 SOC_ENUM_SINGLE(WM8962_DAC_DSP_MIXING_2, 2, 3, st_text);
2014
2015static const struct snd_kcontrol_new stl_mux =
2016 SOC_DAPM_ENUM("Left Sidetone", stl_enum);
2017
2018static const char *outmux_text[] = { "DAC", "Mixer" };
2019
2020static const struct soc_enum spkoutr_enum =
2021 SOC_ENUM_SINGLE(WM8962_SPEAKER_MIXER_2, 7, 2, outmux_text);
2022
2023static const struct snd_kcontrol_new spkoutr_mux =
2024 SOC_DAPM_ENUM("SPKOUTR Mux", spkoutr_enum);
2025
2026static const struct soc_enum spkoutl_enum =
2027 SOC_ENUM_SINGLE(WM8962_SPEAKER_MIXER_1, 7, 2, outmux_text);
2028
2029static const struct snd_kcontrol_new spkoutl_mux =
2030 SOC_DAPM_ENUM("SPKOUTL Mux", spkoutl_enum);
2031
2032static const struct soc_enum hpoutr_enum =
2033 SOC_ENUM_SINGLE(WM8962_HEADPHONE_MIXER_2, 7, 2, outmux_text);
2034
2035static const struct snd_kcontrol_new hpoutr_mux =
2036 SOC_DAPM_ENUM("HPOUTR Mux", hpoutr_enum);
2037
2038static const struct soc_enum hpoutl_enum =
2039 SOC_ENUM_SINGLE(WM8962_HEADPHONE_MIXER_1, 7, 2, outmux_text);
2040
2041static const struct snd_kcontrol_new hpoutl_mux =
2042 SOC_DAPM_ENUM("HPOUTL Mux", hpoutl_enum);
2043
2044static const struct snd_kcontrol_new inpgal[] = {
2045SOC_DAPM_SINGLE("IN1L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 3, 1, 0),
2046SOC_DAPM_SINGLE("IN2L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 2, 1, 0),
2047SOC_DAPM_SINGLE("IN3L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 1, 1, 0),
2048SOC_DAPM_SINGLE("IN4L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 0, 1, 0),
2049};
2050
2051static const struct snd_kcontrol_new inpgar[] = {
2052SOC_DAPM_SINGLE("IN1R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 3, 1, 0),
2053SOC_DAPM_SINGLE("IN2R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 2, 1, 0),
2054SOC_DAPM_SINGLE("IN3R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 1, 1, 0),
2055SOC_DAPM_SINGLE("IN4R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 0, 1, 0),
2056};
2057
2058static const struct snd_kcontrol_new mixinl[] = {
2059SOC_DAPM_SINGLE("IN2L Switch", WM8962_INPUT_MIXER_CONTROL_2, 5, 1, 0),
2060SOC_DAPM_SINGLE("IN3L Switch", WM8962_INPUT_MIXER_CONTROL_2, 4, 1, 0),
2061SOC_DAPM_SINGLE("PGA Switch", WM8962_INPUT_MIXER_CONTROL_2, 3, 1, 0),
2062};
2063
2064static const struct snd_kcontrol_new mixinr[] = {
2065SOC_DAPM_SINGLE("IN2R Switch", WM8962_INPUT_MIXER_CONTROL_2, 2, 1, 0),
2066SOC_DAPM_SINGLE("IN3R Switch", WM8962_INPUT_MIXER_CONTROL_2, 1, 1, 0),
2067SOC_DAPM_SINGLE("PGA Switch", WM8962_INPUT_MIXER_CONTROL_2, 0, 1, 0),
2068};
2069
2070static const struct snd_kcontrol_new hpmixl[] = {
2071SOC_DAPM_SINGLE("DACL Switch", WM8962_HEADPHONE_MIXER_1, 5, 1, 0),
2072SOC_DAPM_SINGLE("DACR Switch", WM8962_HEADPHONE_MIXER_1, 4, 1, 0),
2073SOC_DAPM_SINGLE("MIXINL Switch", WM8962_HEADPHONE_MIXER_1, 3, 1, 0),
2074SOC_DAPM_SINGLE("MIXINR Switch", WM8962_HEADPHONE_MIXER_1, 2, 1, 0),
2075SOC_DAPM_SINGLE("IN4L Switch", WM8962_HEADPHONE_MIXER_1, 1, 1, 0),
2076SOC_DAPM_SINGLE("IN4R Switch", WM8962_HEADPHONE_MIXER_1, 0, 1, 0),
2077};
2078
2079static const struct snd_kcontrol_new hpmixr[] = {
2080SOC_DAPM_SINGLE("DACL Switch", WM8962_HEADPHONE_MIXER_2, 5, 1, 0),
2081SOC_DAPM_SINGLE("DACR Switch", WM8962_HEADPHONE_MIXER_2, 4, 1, 0),
2082SOC_DAPM_SINGLE("MIXINL Switch", WM8962_HEADPHONE_MIXER_2, 3, 1, 0),
2083SOC_DAPM_SINGLE("MIXINR Switch", WM8962_HEADPHONE_MIXER_2, 2, 1, 0),
2084SOC_DAPM_SINGLE("IN4L Switch", WM8962_HEADPHONE_MIXER_2, 1, 1, 0),
2085SOC_DAPM_SINGLE("IN4R Switch", WM8962_HEADPHONE_MIXER_2, 0, 1, 0),
2086};
2087
2088static const struct snd_kcontrol_new spkmixl[] = {
2089SOC_DAPM_SINGLE("DACL Switch", WM8962_SPEAKER_MIXER_1, 5, 1, 0),
2090SOC_DAPM_SINGLE("DACR Switch", WM8962_SPEAKER_MIXER_1, 4, 1, 0),
2091SOC_DAPM_SINGLE("MIXINL Switch", WM8962_SPEAKER_MIXER_1, 3, 1, 0),
2092SOC_DAPM_SINGLE("MIXINR Switch", WM8962_SPEAKER_MIXER_1, 2, 1, 0),
2093SOC_DAPM_SINGLE("IN4L Switch", WM8962_SPEAKER_MIXER_1, 1, 1, 0),
2094SOC_DAPM_SINGLE("IN4R Switch", WM8962_SPEAKER_MIXER_1, 0, 1, 0),
2095};
2096
2097static const struct snd_kcontrol_new spkmixr[] = {
2098SOC_DAPM_SINGLE("DACL Switch", WM8962_SPEAKER_MIXER_2, 5, 1, 0),
2099SOC_DAPM_SINGLE("DACR Switch", WM8962_SPEAKER_MIXER_2, 4, 1, 0),
2100SOC_DAPM_SINGLE("MIXINL Switch", WM8962_SPEAKER_MIXER_2, 3, 1, 0),
2101SOC_DAPM_SINGLE("MIXINR Switch", WM8962_SPEAKER_MIXER_2, 2, 1, 0),
2102SOC_DAPM_SINGLE("IN4L Switch", WM8962_SPEAKER_MIXER_2, 1, 1, 0),
2103SOC_DAPM_SINGLE("IN4R Switch", WM8962_SPEAKER_MIXER_2, 0, 1, 0),
2104};
2105
2106static const struct snd_soc_dapm_widget wm8962_dapm_widgets[] = {
2107SND_SOC_DAPM_INPUT("IN1L"),
2108SND_SOC_DAPM_INPUT("IN1R"),
2109SND_SOC_DAPM_INPUT("IN2L"),
2110SND_SOC_DAPM_INPUT("IN2R"),
2111SND_SOC_DAPM_INPUT("IN3L"),
2112SND_SOC_DAPM_INPUT("IN3R"),
2113SND_SOC_DAPM_INPUT("IN4L"),
2114SND_SOC_DAPM_INPUT("IN4R"),
2115SND_SOC_DAPM_SIGGEN("Beep"),
2116SND_SOC_DAPM_INPUT("DMICDAT"),
2117
2118SND_SOC_DAPM_SUPPLY("MICBIAS", WM8962_PWR_MGMT_1, 1, 0, NULL, 0),
2119
2120SND_SOC_DAPM_SUPPLY("Class G", WM8962_CHARGE_PUMP_B, 0, 1, NULL, 0),
2121SND_SOC_DAPM_SUPPLY("SYSCLK", WM8962_CLOCKING2, 5, 0, NULL, 0),
2122SND_SOC_DAPM_SUPPLY("Charge Pump", WM8962_CHARGE_PUMP_1, 0, 0, cp_event,
2123 SND_SOC_DAPM_POST_PMU),
2124SND_SOC_DAPM_SUPPLY("TOCLK", WM8962_ADDITIONAL_CONTROL_1, 0, 0, NULL, 0),
2125SND_SOC_DAPM_SUPPLY_S("DSP2", 1, WM8962_DSP2_POWER_MANAGEMENT,
2126 WM8962_DSP2_ENA_SHIFT, 0, dsp2_event,
2127 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2128SND_SOC_DAPM_SUPPLY("TEMP_HP", WM8962_ADDITIONAL_CONTROL_4, 2, 0, NULL, 0),
2129SND_SOC_DAPM_SUPPLY("TEMP_SPK", WM8962_ADDITIONAL_CONTROL_4, 1, 0, NULL, 0),
2130
2131SND_SOC_DAPM_MIXER("INPGAL", WM8962_LEFT_INPUT_PGA_CONTROL, 4, 0,
2132 inpgal, ARRAY_SIZE(inpgal)),
2133SND_SOC_DAPM_MIXER("INPGAR", WM8962_RIGHT_INPUT_PGA_CONTROL, 4, 0,
2134 inpgar, ARRAY_SIZE(inpgar)),
2135SND_SOC_DAPM_MIXER("MIXINL", WM8962_PWR_MGMT_1, 5, 0,
2136 mixinl, ARRAY_SIZE(mixinl)),
2137SND_SOC_DAPM_MIXER("MIXINR", WM8962_PWR_MGMT_1, 4, 0,
2138 mixinr, ARRAY_SIZE(mixinr)),
2139
2140SND_SOC_DAPM_AIF_IN("DMIC_ENA", NULL, 0, WM8962_PWR_MGMT_1, 10, 0),
2141
2142SND_SOC_DAPM_ADC("ADCL", "Capture", WM8962_PWR_MGMT_1, 3, 0),
2143SND_SOC_DAPM_ADC("ADCR", "Capture", WM8962_PWR_MGMT_1, 2, 0),
2144
2145SND_SOC_DAPM_MUX("STL", SND_SOC_NOPM, 0, 0, &stl_mux),
2146SND_SOC_DAPM_MUX("STR", SND_SOC_NOPM, 0, 0, &str_mux),
2147
2148SND_SOC_DAPM_DAC("DACL", "Playback", WM8962_PWR_MGMT_2, 8, 0),
2149SND_SOC_DAPM_DAC("DACR", "Playback", WM8962_PWR_MGMT_2, 7, 0),
2150
2151SND_SOC_DAPM_PGA("Left Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
2152SND_SOC_DAPM_PGA("Right Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
2153
2154SND_SOC_DAPM_MIXER("HPMIXL", WM8962_MIXER_ENABLES, 3, 0,
2155 hpmixl, ARRAY_SIZE(hpmixl)),
2156SND_SOC_DAPM_MIXER("HPMIXR", WM8962_MIXER_ENABLES, 2, 0,
2157 hpmixr, ARRAY_SIZE(hpmixr)),
2158
2159SND_SOC_DAPM_MUX_E("HPOUTL PGA", WM8962_PWR_MGMT_2, 6, 0, &hpoutl_mux,
2160 out_pga_event, SND_SOC_DAPM_POST_PMU),
2161SND_SOC_DAPM_MUX_E("HPOUTR PGA", WM8962_PWR_MGMT_2, 5, 0, &hpoutr_mux,
2162 out_pga_event, SND_SOC_DAPM_POST_PMU),
2163
2164SND_SOC_DAPM_PGA_E("HPOUT", SND_SOC_NOPM, 0, 0, NULL, 0, hp_event,
2165 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2166
2167SND_SOC_DAPM_OUTPUT("HPOUTL"),
2168SND_SOC_DAPM_OUTPUT("HPOUTR"),
2169};
2170
2171static const struct snd_soc_dapm_widget wm8962_dapm_spk_mono_widgets[] = {
2172SND_SOC_DAPM_MIXER("Speaker Mixer", WM8962_MIXER_ENABLES, 1, 0,
2173 spkmixl, ARRAY_SIZE(spkmixl)),
2174SND_SOC_DAPM_MUX_E("Speaker PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux,
2175 out_pga_event, SND_SOC_DAPM_POST_PMU),
2176SND_SOC_DAPM_PGA("Speaker Output", WM8962_CLASS_D_CONTROL_1, 7, 0, NULL, 0),
2177SND_SOC_DAPM_OUTPUT("SPKOUT"),
2178};
2179
2180static const struct snd_soc_dapm_widget wm8962_dapm_spk_stereo_widgets[] = {
2181SND_SOC_DAPM_MIXER("SPKOUTL Mixer", WM8962_MIXER_ENABLES, 1, 0,
2182 spkmixl, ARRAY_SIZE(spkmixl)),
2183SND_SOC_DAPM_MIXER("SPKOUTR Mixer", WM8962_MIXER_ENABLES, 0, 0,
2184 spkmixr, ARRAY_SIZE(spkmixr)),
2185
2186SND_SOC_DAPM_MUX_E("SPKOUTL PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux,
2187 out_pga_event, SND_SOC_DAPM_POST_PMU),
2188SND_SOC_DAPM_MUX_E("SPKOUTR PGA", WM8962_PWR_MGMT_2, 3, 0, &spkoutr_mux,
2189 out_pga_event, SND_SOC_DAPM_POST_PMU),
2190
2191SND_SOC_DAPM_PGA("SPKOUTR Output", WM8962_CLASS_D_CONTROL_1, 7, 0, NULL, 0),
2192SND_SOC_DAPM_PGA("SPKOUTL Output", WM8962_CLASS_D_CONTROL_1, 6, 0, NULL, 0),
2193
2194SND_SOC_DAPM_OUTPUT("SPKOUTL"),
2195SND_SOC_DAPM_OUTPUT("SPKOUTR"),
2196};
2197
2198static const struct snd_soc_dapm_route wm8962_intercon[] = {
2199 { "INPGAL", "IN1L Switch", "IN1L" },
2200 { "INPGAL", "IN2L Switch", "IN2L" },
2201 { "INPGAL", "IN3L Switch", "IN3L" },
2202 { "INPGAL", "IN4L Switch", "IN4L" },
2203
2204 { "INPGAR", "IN1R Switch", "IN1R" },
2205 { "INPGAR", "IN2R Switch", "IN2R" },
2206 { "INPGAR", "IN3R Switch", "IN3R" },
2207 { "INPGAR", "IN4R Switch", "IN4R" },
2208
2209 { "MIXINL", "IN2L Switch", "IN2L" },
2210 { "MIXINL", "IN3L Switch", "IN3L" },
2211 { "MIXINL", "PGA Switch", "INPGAL" },
2212
2213 { "MIXINR", "IN2R Switch", "IN2R" },
2214 { "MIXINR", "IN3R Switch", "IN3R" },
2215 { "MIXINR", "PGA Switch", "INPGAR" },
2216
2217 { "MICBIAS", NULL, "SYSCLK" },
2218
2219 { "DMIC_ENA", NULL, "DMICDAT" },
2220
2221 { "ADCL", NULL, "SYSCLK" },
2222 { "ADCL", NULL, "TOCLK" },
2223 { "ADCL", NULL, "MIXINL" },
2224 { "ADCL", NULL, "DMIC_ENA" },
2225 { "ADCL", NULL, "DSP2" },
2226
2227 { "ADCR", NULL, "SYSCLK" },
2228 { "ADCR", NULL, "TOCLK" },
2229 { "ADCR", NULL, "MIXINR" },
2230 { "ADCR", NULL, "DMIC_ENA" },
2231 { "ADCR", NULL, "DSP2" },
2232
2233 { "STL", "Left", "ADCL" },
2234 { "STL", "Right", "ADCR" },
2235 { "STL", NULL, "Class G" },
2236
2237 { "STR", "Left", "ADCL" },
2238 { "STR", "Right", "ADCR" },
2239 { "STR", NULL, "Class G" },
2240
2241 { "DACL", NULL, "SYSCLK" },
2242 { "DACL", NULL, "TOCLK" },
2243 { "DACL", NULL, "Beep" },
2244 { "DACL", NULL, "STL" },
2245 { "DACL", NULL, "DSP2" },
2246
2247 { "DACR", NULL, "SYSCLK" },
2248 { "DACR", NULL, "TOCLK" },
2249 { "DACR", NULL, "Beep" },
2250 { "DACR", NULL, "STR" },
2251 { "DACR", NULL, "DSP2" },
2252
2253 { "HPMIXL", "IN4L Switch", "IN4L" },
2254 { "HPMIXL", "IN4R Switch", "IN4R" },
2255 { "HPMIXL", "DACL Switch", "DACL" },
2256 { "HPMIXL", "DACR Switch", "DACR" },
2257 { "HPMIXL", "MIXINL Switch", "MIXINL" },
2258 { "HPMIXL", "MIXINR Switch", "MIXINR" },
2259
2260 { "HPMIXR", "IN4L Switch", "IN4L" },
2261 { "HPMIXR", "IN4R Switch", "IN4R" },
2262 { "HPMIXR", "DACL Switch", "DACL" },
2263 { "HPMIXR", "DACR Switch", "DACR" },
2264 { "HPMIXR", "MIXINL Switch", "MIXINL" },
2265 { "HPMIXR", "MIXINR Switch", "MIXINR" },
2266
2267 { "Left Bypass", NULL, "HPMIXL" },
2268 { "Left Bypass", NULL, "Class G" },
2269
2270 { "Right Bypass", NULL, "HPMIXR" },
2271 { "Right Bypass", NULL, "Class G" },
2272
2273 { "HPOUTL PGA", "Mixer", "Left Bypass" },
2274 { "HPOUTL PGA", "DAC", "DACL" },
2275
2276 { "HPOUTR PGA", "Mixer", "Right Bypass" },
2277 { "HPOUTR PGA", "DAC", "DACR" },
2278
2279 { "HPOUT", NULL, "HPOUTL PGA" },
2280 { "HPOUT", NULL, "HPOUTR PGA" },
2281 { "HPOUT", NULL, "Charge Pump" },
2282 { "HPOUT", NULL, "SYSCLK" },
2283 { "HPOUT", NULL, "TOCLK" },
2284
2285 { "HPOUTL", NULL, "HPOUT" },
2286 { "HPOUTR", NULL, "HPOUT" },
2287
2288 { "HPOUTL", NULL, "TEMP_HP" },
2289 { "HPOUTR", NULL, "TEMP_HP" },
2290};
2291
2292static const struct snd_soc_dapm_route wm8962_spk_mono_intercon[] = {
2293 { "Speaker Mixer", "IN4L Switch", "IN4L" },
2294 { "Speaker Mixer", "IN4R Switch", "IN4R" },
2295 { "Speaker Mixer", "DACL Switch", "DACL" },
2296 { "Speaker Mixer", "DACR Switch", "DACR" },
2297 { "Speaker Mixer", "MIXINL Switch", "MIXINL" },
2298 { "Speaker Mixer", "MIXINR Switch", "MIXINR" },
2299
2300 { "Speaker PGA", "Mixer", "Speaker Mixer" },
2301 { "Speaker PGA", "DAC", "DACL" },
2302
2303 { "Speaker Output", NULL, "Speaker PGA" },
2304 { "Speaker Output", NULL, "SYSCLK" },
2305 { "Speaker Output", NULL, "TOCLK" },
2306 { "Speaker Output", NULL, "TEMP_SPK" },
2307
2308 { "SPKOUT", NULL, "Speaker Output" },
2309};
2310
2311static const struct snd_soc_dapm_route wm8962_spk_stereo_intercon[] = {
2312 { "SPKOUTL Mixer", "IN4L Switch", "IN4L" },
2313 { "SPKOUTL Mixer", "IN4R Switch", "IN4R" },
2314 { "SPKOUTL Mixer", "DACL Switch", "DACL" },
2315 { "SPKOUTL Mixer", "DACR Switch", "DACR" },
2316 { "SPKOUTL Mixer", "MIXINL Switch", "MIXINL" },
2317 { "SPKOUTL Mixer", "MIXINR Switch", "MIXINR" },
2318
2319 { "SPKOUTR Mixer", "IN4L Switch", "IN4L" },
2320 { "SPKOUTR Mixer", "IN4R Switch", "IN4R" },
2321 { "SPKOUTR Mixer", "DACL Switch", "DACL" },
2322 { "SPKOUTR Mixer", "DACR Switch", "DACR" },
2323 { "SPKOUTR Mixer", "MIXINL Switch", "MIXINL" },
2324 { "SPKOUTR Mixer", "MIXINR Switch", "MIXINR" },
2325
2326 { "SPKOUTL PGA", "Mixer", "SPKOUTL Mixer" },
2327 { "SPKOUTL PGA", "DAC", "DACL" },
2328
2329 { "SPKOUTR PGA", "Mixer", "SPKOUTR Mixer" },
2330 { "SPKOUTR PGA", "DAC", "DACR" },
2331
2332 { "SPKOUTL Output", NULL, "SPKOUTL PGA" },
2333 { "SPKOUTL Output", NULL, "SYSCLK" },
2334 { "SPKOUTL Output", NULL, "TOCLK" },
2335 { "SPKOUTL Output", NULL, "TEMP_SPK" },
2336
2337 { "SPKOUTR Output", NULL, "SPKOUTR PGA" },
2338 { "SPKOUTR Output", NULL, "SYSCLK" },
2339 { "SPKOUTR Output", NULL, "TOCLK" },
2340 { "SPKOUTR Output", NULL, "TEMP_SPK" },
2341
2342 { "SPKOUTL", NULL, "SPKOUTL Output" },
2343 { "SPKOUTR", NULL, "SPKOUTR Output" },
2344};
2345
2346static int wm8962_add_widgets(struct snd_soc_codec *codec)
2347{
2348 struct wm8962_pdata *pdata = dev_get_platdata(codec->dev);
2349 struct snd_soc_dapm_context *dapm = &codec->dapm;
2350
2351 snd_soc_add_codec_controls(codec, wm8962_snd_controls,
2352 ARRAY_SIZE(wm8962_snd_controls));
2353 if (pdata && pdata->spk_mono)
2354 snd_soc_add_codec_controls(codec, wm8962_spk_mono_controls,
2355 ARRAY_SIZE(wm8962_spk_mono_controls));
2356 else
2357 snd_soc_add_codec_controls(codec, wm8962_spk_stereo_controls,
2358 ARRAY_SIZE(wm8962_spk_stereo_controls));
2359
2360
2361 snd_soc_dapm_new_controls(dapm, wm8962_dapm_widgets,
2362 ARRAY_SIZE(wm8962_dapm_widgets));
2363 if (pdata && pdata->spk_mono)
2364 snd_soc_dapm_new_controls(dapm, wm8962_dapm_spk_mono_widgets,
2365 ARRAY_SIZE(wm8962_dapm_spk_mono_widgets));
2366 else
2367 snd_soc_dapm_new_controls(dapm, wm8962_dapm_spk_stereo_widgets,
2368 ARRAY_SIZE(wm8962_dapm_spk_stereo_widgets));
2369
2370 snd_soc_dapm_add_routes(dapm, wm8962_intercon,
2371 ARRAY_SIZE(wm8962_intercon));
2372 if (pdata && pdata->spk_mono)
2373 snd_soc_dapm_add_routes(dapm, wm8962_spk_mono_intercon,
2374 ARRAY_SIZE(wm8962_spk_mono_intercon));
2375 else
2376 snd_soc_dapm_add_routes(dapm, wm8962_spk_stereo_intercon,
2377 ARRAY_SIZE(wm8962_spk_stereo_intercon));
2378
2379
2380 snd_soc_dapm_disable_pin(dapm, "Beep");
2381
2382 return 0;
2383}
2384
2385/* -1 for reserved values */
2386static const int bclk_divs[] = {
2387 1, -1, 2, 3, 4, -1, 6, 8, -1, 12, 16, 24, -1, 32, 32, 32
2388};
2389
2390static const int sysclk_rates[] = {
2391 64, 128, 192, 256, 384, 512, 768, 1024, 1408, 1536, 3072, 6144
2392};
2393
2394static void wm8962_configure_bclk(struct snd_soc_codec *codec)
2395{
2396 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
2397 int dspclk, i;
2398 int clocking2 = 0;
2399 int clocking4 = 0;
2400 int aif2 = 0;
2401
2402 if (!wm8962->sysclk_rate) {
2403 dev_dbg(codec->dev, "No SYSCLK configured\n");
2404 return;
2405 }
2406
2407 if (!wm8962->bclk || !wm8962->lrclk) {
2408 dev_dbg(codec->dev, "No audio clocks configured\n");
2409 return;
2410 }
2411
2412 for (i = 0; i < ARRAY_SIZE(sysclk_rates); i++) {
2413 if (sysclk_rates[i] == wm8962->sysclk_rate / wm8962->lrclk) {
2414 clocking4 |= i << WM8962_SYSCLK_RATE_SHIFT;
2415 break;
2416 }
2417 }
2418
2419 if (i == ARRAY_SIZE(sysclk_rates)) {
2420 dev_err(codec->dev, "Unsupported sysclk ratio %d\n",
2421 wm8962->sysclk_rate / wm8962->lrclk);
2422 return;
2423 }
2424
2425 dev_dbg(codec->dev, "Selected sysclk ratio %d\n", sysclk_rates[i]);
2426
2427 snd_soc_update_bits(codec, WM8962_CLOCKING_4,
2428 WM8962_SYSCLK_RATE_MASK, clocking4);
2429
2430 dspclk = snd_soc_read(codec, WM8962_CLOCKING1);
2431 if (dspclk < 0) {
2432 dev_err(codec->dev, "Failed to read DSPCLK: %d\n", dspclk);
2433 return;
2434 }
2435
2436 dspclk = (dspclk & WM8962_DSPCLK_DIV_MASK) >> WM8962_DSPCLK_DIV_SHIFT;
2437 switch (dspclk) {
2438 case 0:
2439 dspclk = wm8962->sysclk_rate;
2440 break;
2441 case 1:
2442 dspclk = wm8962->sysclk_rate / 2;
2443 break;
2444 case 2:
2445 dspclk = wm8962->sysclk_rate / 4;
2446 break;
2447 default:
2448 dev_warn(codec->dev, "Unknown DSPCLK divisor read back\n");
2449 dspclk = wm8962->sysclk;
2450 }
2451
2452 dev_dbg(codec->dev, "DSPCLK is %dHz, BCLK %d\n", dspclk, wm8962->bclk);
2453
2454 /* We're expecting an exact match */
2455 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2456 if (bclk_divs[i] < 0)
2457 continue;
2458
2459 if (dspclk / bclk_divs[i] == wm8962->bclk) {
2460 dev_dbg(codec->dev, "Selected BCLK_DIV %d for %dHz\n",
2461 bclk_divs[i], wm8962->bclk);
2462 clocking2 |= i;
2463 break;
2464 }
2465 }
2466 if (i == ARRAY_SIZE(bclk_divs)) {
2467 dev_err(codec->dev, "Unsupported BCLK ratio %d\n",
2468 dspclk / wm8962->bclk);
2469 return;
2470 }
2471
2472 aif2 |= wm8962->bclk / wm8962->lrclk;
2473 dev_dbg(codec->dev, "Selected LRCLK divisor %d for %dHz\n",
2474 wm8962->bclk / wm8962->lrclk, wm8962->lrclk);
2475
2476 snd_soc_update_bits(codec, WM8962_CLOCKING2,
2477 WM8962_BCLK_DIV_MASK, clocking2);
2478 snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_2,
2479 WM8962_AIF_RATE_MASK, aif2);
2480}
2481
2482static int wm8962_set_bias_level(struct snd_soc_codec *codec,
2483 enum snd_soc_bias_level level)
2484{
2485 if (level == codec->dapm.bias_level)
2486 return 0;
2487
2488 switch (level) {
2489 case SND_SOC_BIAS_ON:
2490 break;
2491
2492 case SND_SOC_BIAS_PREPARE:
2493 /* VMID 2*50k */
2494 snd_soc_update_bits(codec, WM8962_PWR_MGMT_1,
2495 WM8962_VMID_SEL_MASK, 0x80);
2496
2497 wm8962_configure_bclk(codec);
2498 break;
2499
2500 case SND_SOC_BIAS_STANDBY:
2501 /* VMID 2*250k */
2502 snd_soc_update_bits(codec, WM8962_PWR_MGMT_1,
2503 WM8962_VMID_SEL_MASK, 0x100);
2504
2505 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
2506 msleep(100);
2507 break;
2508
2509 case SND_SOC_BIAS_OFF:
2510 break;
2511 }
2512
2513 codec->dapm.bias_level = level;
2514 return 0;
2515}
2516
2517static const struct {
2518 int rate;
2519 int reg;
2520} sr_vals[] = {
2521 { 48000, 0 },
2522 { 44100, 0 },
2523 { 32000, 1 },
2524 { 22050, 2 },
2525 { 24000, 2 },
2526 { 16000, 3 },
2527 { 11025, 4 },
2528 { 12000, 4 },
2529 { 8000, 5 },
2530 { 88200, 6 },
2531 { 96000, 6 },
2532};
2533
2534static int wm8962_hw_params(struct snd_pcm_substream *substream,
2535 struct snd_pcm_hw_params *params,
2536 struct snd_soc_dai *dai)
2537{
2538 struct snd_soc_codec *codec = dai->codec;
2539 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
2540 int i;
2541 int aif0 = 0;
2542 int adctl3 = 0;
2543
2544 wm8962->bclk = snd_soc_params_to_bclk(params);
2545 if (params_channels(params) == 1)
2546 wm8962->bclk *= 2;
2547
2548 wm8962->lrclk = params_rate(params);
2549
2550 for (i = 0; i < ARRAY_SIZE(sr_vals); i++) {
2551 if (sr_vals[i].rate == wm8962->lrclk) {
2552 adctl3 |= sr_vals[i].reg;
2553 break;
2554 }
2555 }
2556 if (i == ARRAY_SIZE(sr_vals)) {
2557 dev_err(codec->dev, "Unsupported rate %dHz\n", wm8962->lrclk);
2558 return -EINVAL;
2559 }
2560
2561 if (wm8962->lrclk % 8000 == 0)
2562 adctl3 |= WM8962_SAMPLE_RATE_INT_MODE;
2563
2564 switch (params_format(params)) {
2565 case SNDRV_PCM_FORMAT_S16_LE:
2566 break;
2567 case SNDRV_PCM_FORMAT_S20_3LE:
2568 aif0 |= 0x4;
2569 break;
2570 case SNDRV_PCM_FORMAT_S24_LE:
2571 aif0 |= 0x8;
2572 break;
2573 case SNDRV_PCM_FORMAT_S32_LE:
2574 aif0 |= 0xc;
2575 break;
2576 default:
2577 return -EINVAL;
2578 }
2579
2580 snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_0,
2581 WM8962_WL_MASK, aif0);
2582 snd_soc_update_bits(codec, WM8962_ADDITIONAL_CONTROL_3,
2583 WM8962_SAMPLE_RATE_INT_MODE |
2584 WM8962_SAMPLE_RATE_MASK, adctl3);
2585
2586 if (codec->dapm.bias_level == SND_SOC_BIAS_ON)
2587 wm8962_configure_bclk(codec);
2588
2589 return 0;
2590}
2591
2592static int wm8962_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
2593 unsigned int freq, int dir)
2594{
2595 struct snd_soc_codec *codec = dai->codec;
2596 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
2597 int src;
2598
2599 switch (clk_id) {
2600 case WM8962_SYSCLK_MCLK:
2601 wm8962->sysclk = WM8962_SYSCLK_MCLK;
2602 src = 0;
2603 break;
2604 case WM8962_SYSCLK_FLL:
2605 wm8962->sysclk = WM8962_SYSCLK_FLL;
2606 src = 1 << WM8962_SYSCLK_SRC_SHIFT;
2607 break;
2608 default:
2609 return -EINVAL;
2610 }
2611
2612 snd_soc_update_bits(codec, WM8962_CLOCKING2, WM8962_SYSCLK_SRC_MASK,
2613 src);
2614
2615 wm8962->sysclk_rate = freq;
2616
2617 wm8962_configure_bclk(codec);
2618
2619 return 0;
2620}
2621
2622static int wm8962_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2623{
2624 struct snd_soc_codec *codec = dai->codec;
2625 int aif0 = 0;
2626
2627 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2628 case SND_SOC_DAIFMT_DSP_B:
2629 aif0 |= WM8962_LRCLK_INV | 3;
2630 case SND_SOC_DAIFMT_DSP_A:
2631 aif0 |= 3;
2632
2633 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2634 case SND_SOC_DAIFMT_NB_NF:
2635 case SND_SOC_DAIFMT_IB_NF:
2636 break;
2637 default:
2638 return -EINVAL;
2639 }
2640 break;
2641
2642 case SND_SOC_DAIFMT_RIGHT_J:
2643 break;
2644 case SND_SOC_DAIFMT_LEFT_J:
2645 aif0 |= 1;
2646 break;
2647 case SND_SOC_DAIFMT_I2S:
2648 aif0 |= 2;
2649 break;
2650 default:
2651 return -EINVAL;
2652 }
2653
2654 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2655 case SND_SOC_DAIFMT_NB_NF:
2656 break;
2657 case SND_SOC_DAIFMT_IB_NF:
2658 aif0 |= WM8962_BCLK_INV;
2659 break;
2660 case SND_SOC_DAIFMT_NB_IF:
2661 aif0 |= WM8962_LRCLK_INV;
2662 break;
2663 case SND_SOC_DAIFMT_IB_IF:
2664 aif0 |= WM8962_BCLK_INV | WM8962_LRCLK_INV;
2665 break;
2666 default:
2667 return -EINVAL;
2668 }
2669
2670 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2671 case SND_SOC_DAIFMT_CBM_CFM:
2672 aif0 |= WM8962_MSTR;
2673 break;
2674 case SND_SOC_DAIFMT_CBS_CFS:
2675 break;
2676 default:
2677 return -EINVAL;
2678 }
2679
2680 snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_0,
2681 WM8962_FMT_MASK | WM8962_BCLK_INV | WM8962_MSTR |
2682 WM8962_LRCLK_INV, aif0);
2683
2684 return 0;
2685}
2686
2687struct _fll_div {
2688 u16 fll_fratio;
2689 u16 fll_outdiv;
2690 u16 fll_refclk_div;
2691 u16 n;
2692 u16 theta;
2693 u16 lambda;
2694};
2695
2696/* The size in bits of the FLL divide multiplied by 10
2697 * to allow rounding later */
2698#define FIXED_FLL_SIZE ((1 << 16) * 10)
2699
2700static struct {
2701 unsigned int min;
2702 unsigned int max;
2703 u16 fll_fratio;
2704 int ratio;
2705} fll_fratios[] = {
2706 { 0, 64000, 4, 16 },
2707 { 64000, 128000, 3, 8 },
2708 { 128000, 256000, 2, 4 },
2709 { 256000, 1000000, 1, 2 },
2710 { 1000000, 13500000, 0, 1 },
2711};
2712
2713static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
2714 unsigned int Fout)
2715{
2716 unsigned int target;
2717 unsigned int div;
2718 unsigned int fratio, gcd_fll;
2719 int i;
2720
2721 /* Fref must be <=13.5MHz */
2722 div = 1;
2723 fll_div->fll_refclk_div = 0;
2724 while ((Fref / div) > 13500000) {
2725 div *= 2;
2726 fll_div->fll_refclk_div++;
2727
2728 if (div > 4) {
2729 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
2730 Fref);
2731 return -EINVAL;
2732 }
2733 }
2734
2735 pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout);
2736
2737 /* Apply the division for our remaining calculations */
2738 Fref /= div;
2739
2740 /* Fvco should be 90-100MHz; don't check the upper bound */
2741 div = 2;
2742 while (Fout * div < 90000000) {
2743 div++;
2744 if (div > 64) {
2745 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
2746 Fout);
2747 return -EINVAL;
2748 }
2749 }
2750 target = Fout * div;
2751 fll_div->fll_outdiv = div - 1;
2752
2753 pr_debug("FLL Fvco=%dHz\n", target);
2754
2755 /* Find an appropriate FLL_FRATIO and factor it out of the target */
2756 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
2757 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
2758 fll_div->fll_fratio = fll_fratios[i].fll_fratio;
2759 fratio = fll_fratios[i].ratio;
2760 break;
2761 }
2762 }
2763 if (i == ARRAY_SIZE(fll_fratios)) {
2764 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
2765 return -EINVAL;
2766 }
2767
2768 fll_div->n = target / (fratio * Fref);
2769
2770 if (target % Fref == 0) {
2771 fll_div->theta = 0;
2772 fll_div->lambda = 0;
2773 } else {
2774 gcd_fll = gcd(target, fratio * Fref);
2775
2776 fll_div->theta = (target - (fll_div->n * fratio * Fref))
2777 / gcd_fll;
2778 fll_div->lambda = (fratio * Fref) / gcd_fll;
2779 }
2780
2781 pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
2782 fll_div->n, fll_div->theta, fll_div->lambda);
2783 pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
2784 fll_div->fll_fratio, fll_div->fll_outdiv,
2785 fll_div->fll_refclk_div);
2786
2787 return 0;
2788}
2789
2790static int wm8962_set_fll(struct snd_soc_codec *codec, int fll_id, int source,
2791 unsigned int Fref, unsigned int Fout)
2792{
2793 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
2794 struct _fll_div fll_div;
2795 unsigned long timeout;
2796 int ret;
2797 int fll1 = 0;
2798
2799 /* Any change? */
2800 if (source == wm8962->fll_src && Fref == wm8962->fll_fref &&
2801 Fout == wm8962->fll_fout)
2802 return 0;
2803
2804 if (Fout == 0) {
2805 dev_dbg(codec->dev, "FLL disabled\n");
2806
2807 wm8962->fll_fref = 0;
2808 wm8962->fll_fout = 0;
2809
2810 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
2811 WM8962_FLL_ENA, 0);
2812
2813 pm_runtime_put(codec->dev);
2814
2815 return 0;
2816 }
2817
2818 ret = fll_factors(&fll_div, Fref, Fout);
2819 if (ret != 0)
2820 return ret;
2821
2822 /* Parameters good, disable so we can reprogram */
2823 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1, WM8962_FLL_ENA, 0);
2824
2825 switch (fll_id) {
2826 case WM8962_FLL_MCLK:
2827 case WM8962_FLL_BCLK:
2828 case WM8962_FLL_OSC:
2829 fll1 |= (fll_id - 1) << WM8962_FLL_REFCLK_SRC_SHIFT;
2830 break;
2831 case WM8962_FLL_INT:
2832 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
2833 WM8962_FLL_OSC_ENA, WM8962_FLL_OSC_ENA);
2834 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_5,
2835 WM8962_FLL_FRC_NCO, WM8962_FLL_FRC_NCO);
2836 break;
2837 default:
2838 dev_err(codec->dev, "Unknown FLL source %d\n", ret);
2839 return -EINVAL;
2840 }
2841
2842 if (fll_div.theta || fll_div.lambda)
2843 fll1 |= WM8962_FLL_FRAC;
2844
2845 /* Stop the FLL while we reconfigure */
2846 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1, WM8962_FLL_ENA, 0);
2847
2848 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_2,
2849 WM8962_FLL_OUTDIV_MASK |
2850 WM8962_FLL_REFCLK_DIV_MASK,
2851 (fll_div.fll_outdiv << WM8962_FLL_OUTDIV_SHIFT) |
2852 (fll_div.fll_refclk_div));
2853
2854 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_3,
2855 WM8962_FLL_FRATIO_MASK, fll_div.fll_fratio);
2856
2857 snd_soc_write(codec, WM8962_FLL_CONTROL_6, fll_div.theta);
2858 snd_soc_write(codec, WM8962_FLL_CONTROL_7, fll_div.lambda);
2859 snd_soc_write(codec, WM8962_FLL_CONTROL_8, fll_div.n);
2860
2861 try_wait_for_completion(&wm8962->fll_lock);
2862
2863 pm_runtime_get_sync(codec->dev);
2864
2865 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
2866 WM8962_FLL_FRAC | WM8962_FLL_REFCLK_SRC_MASK |
2867 WM8962_FLL_ENA, fll1 | WM8962_FLL_ENA);
2868
2869 dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
2870
2871 ret = 0;
2872
2873 if (fll1 & WM8962_FLL_ENA) {
2874 /* This should be a massive overestimate but go even
2875 * higher if we'll error out
2876 */
2877 if (wm8962->irq)
2878 timeout = msecs_to_jiffies(5);
2879 else
2880 timeout = msecs_to_jiffies(1);
2881
2882 timeout = wait_for_completion_timeout(&wm8962->fll_lock,
2883 timeout);
2884
2885 if (timeout == 0 && wm8962->irq) {
2886 dev_err(codec->dev, "FLL lock timed out");
2887 ret = -ETIMEDOUT;
2888 }
2889 }
2890
2891 wm8962->fll_fref = Fref;
2892 wm8962->fll_fout = Fout;
2893 wm8962->fll_src = source;
2894
2895 return ret;
2896}
2897
2898static int wm8962_mute(struct snd_soc_dai *dai, int mute)
2899{
2900 struct snd_soc_codec *codec = dai->codec;
2901 int val;
2902
2903 if (mute)
2904 val = WM8962_DAC_MUTE;
2905 else
2906 val = 0;
2907
2908 return snd_soc_update_bits(codec, WM8962_ADC_DAC_CONTROL_1,
2909 WM8962_DAC_MUTE, val);
2910}
2911
2912#define WM8962_RATES SNDRV_PCM_RATE_8000_96000
2913
2914#define WM8962_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2915 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2916
2917static const struct snd_soc_dai_ops wm8962_dai_ops = {
2918 .hw_params = wm8962_hw_params,
2919 .set_sysclk = wm8962_set_dai_sysclk,
2920 .set_fmt = wm8962_set_dai_fmt,
2921 .digital_mute = wm8962_mute,
2922};
2923
2924static struct snd_soc_dai_driver wm8962_dai = {
2925 .name = "wm8962",
2926 .playback = {
2927 .stream_name = "Playback",
2928 .channels_min = 1,
2929 .channels_max = 2,
2930 .rates = WM8962_RATES,
2931 .formats = WM8962_FORMATS,
2932 },
2933 .capture = {
2934 .stream_name = "Capture",
2935 .channels_min = 1,
2936 .channels_max = 2,
2937 .rates = WM8962_RATES,
2938 .formats = WM8962_FORMATS,
2939 },
2940 .ops = &wm8962_dai_ops,
2941 .symmetric_rates = 1,
2942};
2943
2944static void wm8962_mic_work(struct work_struct *work)
2945{
2946 struct wm8962_priv *wm8962 = container_of(work,
2947 struct wm8962_priv,
2948 mic_work.work);
2949 struct snd_soc_codec *codec = wm8962->codec;
2950 int status = 0;
2951 int irq_pol = 0;
2952 int reg;
2953
2954 reg = snd_soc_read(codec, WM8962_ADDITIONAL_CONTROL_4);
2955
2956 if (reg & WM8962_MICDET_STS) {
2957 status |= SND_JACK_MICROPHONE;
2958 irq_pol |= WM8962_MICD_IRQ_POL;
2959 }
2960
2961 if (reg & WM8962_MICSHORT_STS) {
2962 status |= SND_JACK_BTN_0;
2963 irq_pol |= WM8962_MICSCD_IRQ_POL;
2964 }
2965
2966 snd_soc_jack_report(wm8962->jack, status,
2967 SND_JACK_MICROPHONE | SND_JACK_BTN_0);
2968
2969 snd_soc_update_bits(codec, WM8962_MICINT_SOURCE_POL,
2970 WM8962_MICSCD_IRQ_POL |
2971 WM8962_MICD_IRQ_POL, irq_pol);
2972}
2973
2974static irqreturn_t wm8962_irq(int irq, void *data)
2975{
2976 struct device *dev = data;
2977 struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
2978 unsigned int mask;
2979 unsigned int active;
2980 int reg, ret;
2981
2982 ret = regmap_read(wm8962->regmap, WM8962_INTERRUPT_STATUS_2_MASK,
2983 &mask);
2984 if (ret != 0) {
2985 dev_err(dev, "Failed to read interrupt mask: %d\n",
2986 ret);
2987 return IRQ_NONE;
2988 }
2989
2990 ret = regmap_read(wm8962->regmap, WM8962_INTERRUPT_STATUS_2, &active);
2991 if (ret != 0) {
2992 dev_err(dev, "Failed to read interrupt: %d\n", ret);
2993 return IRQ_NONE;
2994 }
2995
2996 active &= ~mask;
2997
2998 if (!active)
2999 return IRQ_NONE;
3000
3001 /* Acknowledge the interrupts */
3002 ret = regmap_write(wm8962->regmap, WM8962_INTERRUPT_STATUS_2, active);
3003 if (ret != 0)
3004 dev_warn(dev, "Failed to ack interrupt: %d\n", ret);
3005
3006 if (active & WM8962_FLL_LOCK_EINT) {
3007 dev_dbg(dev, "FLL locked\n");
3008 complete(&wm8962->fll_lock);
3009 }
3010
3011 if (active & WM8962_FIFOS_ERR_EINT)
3012 dev_err(dev, "FIFO error\n");
3013
3014 if (active & WM8962_TEMP_SHUT_EINT) {
3015 dev_crit(dev, "Thermal shutdown\n");
3016
3017 ret = regmap_read(wm8962->regmap,
3018 WM8962_THERMAL_SHUTDOWN_STATUS, ®);
3019 if (ret != 0) {
3020 dev_warn(dev, "Failed to read thermal status: %d\n",
3021 ret);
3022 reg = 0;
3023 }
3024
3025 if (reg & WM8962_TEMP_ERR_HP)
3026 dev_crit(dev, "Headphone thermal error\n");
3027 if (reg & WM8962_TEMP_WARN_HP)
3028 dev_crit(dev, "Headphone thermal warning\n");
3029 if (reg & WM8962_TEMP_ERR_SPK)
3030 dev_crit(dev, "Speaker thermal error\n");
3031 if (reg & WM8962_TEMP_WARN_SPK)
3032 dev_crit(dev, "Speaker thermal warning\n");
3033 }
3034
3035 if (active & (WM8962_MICSCD_EINT | WM8962_MICD_EINT)) {
3036 dev_dbg(dev, "Microphone event detected\n");
3037
3038#ifndef CONFIG_SND_SOC_WM8962_MODULE
3039 trace_snd_soc_jack_irq(dev_name(dev));
3040#endif
3041
3042 pm_wakeup_event(dev, 300);
3043
3044 schedule_delayed_work(&wm8962->mic_work,
3045 msecs_to_jiffies(250));
3046 }
3047
3048 return IRQ_HANDLED;
3049}
3050
3051/**
3052 * wm8962_mic_detect - Enable microphone detection via the WM8962 IRQ
3053 *
3054 * @codec: WM8962 codec
3055 * @jack: jack to report detection events on
3056 *
3057 * Enable microphone detection via IRQ on the WM8962. If GPIOs are
3058 * being used to bring out signals to the processor then only platform
3059 * data configuration is needed for WM8962 and processor GPIOs should
3060 * be configured using snd_soc_jack_add_gpios() instead.
3061 *
3062 * If no jack is supplied detection will be disabled.
3063 */
3064int wm8962_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack)
3065{
3066 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3067 int irq_mask, enable;
3068
3069 wm8962->jack = jack;
3070 if (jack) {
3071 irq_mask = 0;
3072 enable = WM8962_MICDET_ENA;
3073 } else {
3074 irq_mask = WM8962_MICD_EINT | WM8962_MICSCD_EINT;
3075 enable = 0;
3076 }
3077
3078 snd_soc_update_bits(codec, WM8962_INTERRUPT_STATUS_2_MASK,
3079 WM8962_MICD_EINT | WM8962_MICSCD_EINT, irq_mask);
3080 snd_soc_update_bits(codec, WM8962_ADDITIONAL_CONTROL_4,
3081 WM8962_MICDET_ENA, enable);
3082
3083 /* Send an initial empty report */
3084 snd_soc_jack_report(wm8962->jack, 0,
3085 SND_JACK_MICROPHONE | SND_JACK_BTN_0);
3086
3087 if (jack) {
3088 snd_soc_dapm_force_enable_pin(&codec->dapm, "SYSCLK");
3089 snd_soc_dapm_force_enable_pin(&codec->dapm, "MICBIAS");
3090 } else {
3091 snd_soc_dapm_disable_pin(&codec->dapm, "SYSCLK");
3092 snd_soc_dapm_disable_pin(&codec->dapm, "MICBIAS");
3093 }
3094
3095 return 0;
3096}
3097EXPORT_SYMBOL_GPL(wm8962_mic_detect);
3098
3099#if defined(CONFIG_INPUT) || defined(CONFIG_INPUT_MODULE)
3100static int beep_rates[] = {
3101 500, 1000, 2000, 4000,
3102};
3103
3104static void wm8962_beep_work(struct work_struct *work)
3105{
3106 struct wm8962_priv *wm8962 =
3107 container_of(work, struct wm8962_priv, beep_work);
3108 struct snd_soc_codec *codec = wm8962->codec;
3109 struct snd_soc_dapm_context *dapm = &codec->dapm;
3110 int i;
3111 int reg = 0;
3112 int best = 0;
3113
3114 if (wm8962->beep_rate) {
3115 for (i = 0; i < ARRAY_SIZE(beep_rates); i++) {
3116 if (abs(wm8962->beep_rate - beep_rates[i]) <
3117 abs(wm8962->beep_rate - beep_rates[best]))
3118 best = i;
3119 }
3120
3121 dev_dbg(codec->dev, "Set beep rate %dHz for requested %dHz\n",
3122 beep_rates[best], wm8962->beep_rate);
3123
3124 reg = WM8962_BEEP_ENA | (best << WM8962_BEEP_RATE_SHIFT);
3125
3126 snd_soc_dapm_enable_pin(dapm, "Beep");
3127 } else {
3128 dev_dbg(codec->dev, "Disabling beep\n");
3129 snd_soc_dapm_disable_pin(dapm, "Beep");
3130 }
3131
3132 snd_soc_update_bits(codec, WM8962_BEEP_GENERATOR_1,
3133 WM8962_BEEP_ENA | WM8962_BEEP_RATE_MASK, reg);
3134
3135 snd_soc_dapm_sync(dapm);
3136}
3137
3138/* For usability define a way of injecting beep events for the device -
3139 * many systems will not have a keyboard.
3140 */
3141static int wm8962_beep_event(struct input_dev *dev, unsigned int type,
3142 unsigned int code, int hz)
3143{
3144 struct snd_soc_codec *codec = input_get_drvdata(dev);
3145 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3146
3147 dev_dbg(codec->dev, "Beep event %x %x\n", code, hz);
3148
3149 switch (code) {
3150 case SND_BELL:
3151 if (hz)
3152 hz = 1000;
3153 case SND_TONE:
3154 break;
3155 default:
3156 return -1;
3157 }
3158
3159 /* Kick the beep from a workqueue */
3160 wm8962->beep_rate = hz;
3161 schedule_work(&wm8962->beep_work);
3162 return 0;
3163}
3164
3165static ssize_t wm8962_beep_set(struct device *dev,
3166 struct device_attribute *attr,
3167 const char *buf, size_t count)
3168{
3169 struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
3170 long int time;
3171 int ret;
3172
3173 ret = strict_strtol(buf, 10, &time);
3174 if (ret != 0)
3175 return ret;
3176
3177 input_event(wm8962->beep, EV_SND, SND_TONE, time);
3178
3179 return count;
3180}
3181
3182static DEVICE_ATTR(beep, 0200, NULL, wm8962_beep_set);
3183
3184static void wm8962_init_beep(struct snd_soc_codec *codec)
3185{
3186 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3187 int ret;
3188
3189 wm8962->beep = input_allocate_device();
3190 if (!wm8962->beep) {
3191 dev_err(codec->dev, "Failed to allocate beep device\n");
3192 return;
3193 }
3194
3195 INIT_WORK(&wm8962->beep_work, wm8962_beep_work);
3196 wm8962->beep_rate = 0;
3197
3198 wm8962->beep->name = "WM8962 Beep Generator";
3199 wm8962->beep->phys = dev_name(codec->dev);
3200 wm8962->beep->id.bustype = BUS_I2C;
3201
3202 wm8962->beep->evbit[0] = BIT_MASK(EV_SND);
3203 wm8962->beep->sndbit[0] = BIT_MASK(SND_BELL) | BIT_MASK(SND_TONE);
3204 wm8962->beep->event = wm8962_beep_event;
3205 wm8962->beep->dev.parent = codec->dev;
3206 input_set_drvdata(wm8962->beep, codec);
3207
3208 ret = input_register_device(wm8962->beep);
3209 if (ret != 0) {
3210 input_free_device(wm8962->beep);
3211 wm8962->beep = NULL;
3212 dev_err(codec->dev, "Failed to register beep device\n");
3213 }
3214
3215 ret = device_create_file(codec->dev, &dev_attr_beep);
3216 if (ret != 0) {
3217 dev_err(codec->dev, "Failed to create keyclick file: %d\n",
3218 ret);
3219 }
3220}
3221
3222static void wm8962_free_beep(struct snd_soc_codec *codec)
3223{
3224 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3225
3226 device_remove_file(codec->dev, &dev_attr_beep);
3227 input_unregister_device(wm8962->beep);
3228 cancel_work_sync(&wm8962->beep_work);
3229 wm8962->beep = NULL;
3230
3231 snd_soc_update_bits(codec, WM8962_BEEP_GENERATOR_1, WM8962_BEEP_ENA,0);
3232}
3233#else
3234static void wm8962_init_beep(struct snd_soc_codec *codec)
3235{
3236}
3237
3238static void wm8962_free_beep(struct snd_soc_codec *codec)
3239{
3240}
3241#endif
3242
3243static void wm8962_set_gpio_mode(struct snd_soc_codec *codec, int gpio)
3244{
3245 int mask = 0;
3246 int val = 0;
3247
3248 /* Some of the GPIOs are behind MFP configuration and need to
3249 * be put into GPIO mode. */
3250 switch (gpio) {
3251 case 2:
3252 mask = WM8962_CLKOUT2_SEL_MASK;
3253 val = 1 << WM8962_CLKOUT2_SEL_SHIFT;
3254 break;
3255 case 3:
3256 mask = WM8962_CLKOUT3_SEL_MASK;
3257 val = 1 << WM8962_CLKOUT3_SEL_SHIFT;
3258 break;
3259 default:
3260 break;
3261 }
3262
3263 if (mask)
3264 snd_soc_update_bits(codec, WM8962_ANALOGUE_CLOCKING1,
3265 mask, val);
3266}
3267
3268#ifdef CONFIG_GPIOLIB
3269static inline struct wm8962_priv *gpio_to_wm8962(struct gpio_chip *chip)
3270{
3271 return container_of(chip, struct wm8962_priv, gpio_chip);
3272}
3273
3274static int wm8962_gpio_request(struct gpio_chip *chip, unsigned offset)
3275{
3276 struct wm8962_priv *wm8962 = gpio_to_wm8962(chip);
3277 struct snd_soc_codec *codec = wm8962->codec;
3278
3279 /* The WM8962 GPIOs aren't linearly numbered. For simplicity
3280 * we export linear numbers and error out if the unsupported
3281 * ones are requsted.
3282 */
3283 switch (offset + 1) {
3284 case 2:
3285 case 3:
3286 case 5:
3287 case 6:
3288 break;
3289 default:
3290 return -EINVAL;
3291 }
3292
3293 wm8962_set_gpio_mode(codec, offset + 1);
3294
3295 return 0;
3296}
3297
3298static void wm8962_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
3299{
3300 struct wm8962_priv *wm8962 = gpio_to_wm8962(chip);
3301 struct snd_soc_codec *codec = wm8962->codec;
3302
3303 snd_soc_update_bits(codec, WM8962_GPIO_BASE + offset,
3304 WM8962_GP2_LVL, !!value << WM8962_GP2_LVL_SHIFT);
3305}
3306
3307static int wm8962_gpio_direction_out(struct gpio_chip *chip,
3308 unsigned offset, int value)
3309{
3310 struct wm8962_priv *wm8962 = gpio_to_wm8962(chip);
3311 struct snd_soc_codec *codec = wm8962->codec;
3312 int ret, val;
3313
3314 /* Force function 1 (logic output) */
3315 val = (1 << WM8962_GP2_FN_SHIFT) | (value << WM8962_GP2_LVL_SHIFT);
3316
3317 ret = snd_soc_update_bits(codec, WM8962_GPIO_BASE + offset,
3318 WM8962_GP2_FN_MASK | WM8962_GP2_LVL, val);
3319 if (ret < 0)
3320 return ret;
3321
3322 return 0;
3323}
3324
3325static struct gpio_chip wm8962_template_chip = {
3326 .label = "wm8962",
3327 .owner = THIS_MODULE,
3328 .request = wm8962_gpio_request,
3329 .direction_output = wm8962_gpio_direction_out,
3330 .set = wm8962_gpio_set,
3331 .can_sleep = 1,
3332};
3333
3334static void wm8962_init_gpio(struct snd_soc_codec *codec)
3335{
3336 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3337 struct wm8962_pdata *pdata = dev_get_platdata(codec->dev);
3338 int ret;
3339
3340 wm8962->gpio_chip = wm8962_template_chip;
3341 wm8962->gpio_chip.ngpio = WM8962_MAX_GPIO;
3342 wm8962->gpio_chip.dev = codec->dev;
3343
3344 if (pdata && pdata->gpio_base)
3345 wm8962->gpio_chip.base = pdata->gpio_base;
3346 else
3347 wm8962->gpio_chip.base = -1;
3348
3349 ret = gpiochip_add(&wm8962->gpio_chip);
3350 if (ret != 0)
3351 dev_err(codec->dev, "Failed to add GPIOs: %d\n", ret);
3352}
3353
3354static void wm8962_free_gpio(struct snd_soc_codec *codec)
3355{
3356 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3357 int ret;
3358
3359 ret = gpiochip_remove(&wm8962->gpio_chip);
3360 if (ret != 0)
3361 dev_err(codec->dev, "Failed to remove GPIOs: %d\n", ret);
3362}
3363#else
3364static void wm8962_init_gpio(struct snd_soc_codec *codec)
3365{
3366}
3367
3368static void wm8962_free_gpio(struct snd_soc_codec *codec)
3369{
3370}
3371#endif
3372
3373static int wm8962_probe(struct snd_soc_codec *codec)
3374{
3375 int ret;
3376 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3377 struct wm8962_pdata *pdata = dev_get_platdata(codec->dev);
3378 u16 *reg_cache = codec->reg_cache;
3379 int i, trigger, irq_pol;
3380 bool dmicclk, dmicdat;
3381
3382 wm8962->codec = codec;
3383 codec->control_data = wm8962->regmap;
3384
3385 ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
3386 if (ret != 0) {
3387 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
3388 return ret;
3389 }
3390
3391 wm8962->disable_nb[0].notifier_call = wm8962_regulator_event_0;
3392 wm8962->disable_nb[1].notifier_call = wm8962_regulator_event_1;
3393 wm8962->disable_nb[2].notifier_call = wm8962_regulator_event_2;
3394 wm8962->disable_nb[3].notifier_call = wm8962_regulator_event_3;
3395 wm8962->disable_nb[4].notifier_call = wm8962_regulator_event_4;
3396 wm8962->disable_nb[5].notifier_call = wm8962_regulator_event_5;
3397 wm8962->disable_nb[6].notifier_call = wm8962_regulator_event_6;
3398 wm8962->disable_nb[7].notifier_call = wm8962_regulator_event_7;
3399
3400 /* This should really be moved into the regulator core */
3401 for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++) {
3402 ret = regulator_register_notifier(wm8962->supplies[i].consumer,
3403 &wm8962->disable_nb[i]);
3404 if (ret != 0) {
3405 dev_err(codec->dev,
3406 "Failed to register regulator notifier: %d\n",
3407 ret);
3408 }
3409 }
3410
3411 /* SYSCLK defaults to on; make sure it is off so we can safely
3412 * write to registers if the device is declocked.
3413 */
3414 snd_soc_update_bits(codec, WM8962_CLOCKING2, WM8962_SYSCLK_ENA, 0);
3415
3416 /* Ensure we have soft control over all registers */
3417 snd_soc_update_bits(codec, WM8962_CLOCKING2,
3418 WM8962_CLKREG_OVD, WM8962_CLKREG_OVD);
3419
3420 /* Ensure that the oscillator and PLLs are disabled */
3421 snd_soc_update_bits(codec, WM8962_PLL2,
3422 WM8962_OSC_ENA | WM8962_PLL2_ENA | WM8962_PLL3_ENA,
3423 0);
3424
3425 if (pdata) {
3426 /* Apply static configuration for GPIOs */
3427 for (i = 0; i < ARRAY_SIZE(pdata->gpio_init); i++)
3428 if (pdata->gpio_init[i]) {
3429 wm8962_set_gpio_mode(codec, i + 1);
3430 snd_soc_write(codec, 0x200 + i,
3431 pdata->gpio_init[i] & 0xffff);
3432 }
3433
3434 /* Put the speakers into mono mode? */
3435 if (pdata->spk_mono)
3436 reg_cache[WM8962_CLASS_D_CONTROL_2]
3437 |= WM8962_SPK_MONO;
3438
3439 /* Micbias setup, detection enable and detection
3440 * threasholds. */
3441 if (pdata->mic_cfg)
3442 snd_soc_update_bits(codec, WM8962_ADDITIONAL_CONTROL_4,
3443 WM8962_MICDET_ENA |
3444 WM8962_MICDET_THR_MASK |
3445 WM8962_MICSHORT_THR_MASK |
3446 WM8962_MICBIAS_LVL,
3447 pdata->mic_cfg);
3448 }
3449
3450 /* Latch volume update bits */
3451 snd_soc_update_bits(codec, WM8962_LEFT_INPUT_VOLUME,
3452 WM8962_IN_VU, WM8962_IN_VU);
3453 snd_soc_update_bits(codec, WM8962_RIGHT_INPUT_VOLUME,
3454 WM8962_IN_VU, WM8962_IN_VU);
3455 snd_soc_update_bits(codec, WM8962_LEFT_ADC_VOLUME,
3456 WM8962_ADC_VU, WM8962_ADC_VU);
3457 snd_soc_update_bits(codec, WM8962_RIGHT_ADC_VOLUME,
3458 WM8962_ADC_VU, WM8962_ADC_VU);
3459 snd_soc_update_bits(codec, WM8962_LEFT_DAC_VOLUME,
3460 WM8962_DAC_VU, WM8962_DAC_VU);
3461 snd_soc_update_bits(codec, WM8962_RIGHT_DAC_VOLUME,
3462 WM8962_DAC_VU, WM8962_DAC_VU);
3463 snd_soc_update_bits(codec, WM8962_SPKOUTL_VOLUME,
3464 WM8962_SPKOUT_VU, WM8962_SPKOUT_VU);
3465 snd_soc_update_bits(codec, WM8962_SPKOUTR_VOLUME,
3466 WM8962_SPKOUT_VU, WM8962_SPKOUT_VU);
3467 snd_soc_update_bits(codec, WM8962_HPOUTL_VOLUME,
3468 WM8962_HPOUT_VU, WM8962_HPOUT_VU);
3469 snd_soc_update_bits(codec, WM8962_HPOUTR_VOLUME,
3470 WM8962_HPOUT_VU, WM8962_HPOUT_VU);
3471
3472 /* Stereo control for EQ */
3473 snd_soc_update_bits(codec, WM8962_EQ1, WM8962_EQ_SHARED_COEFF, 0);
3474
3475 /* Don't debouce interrupts so we don't need SYSCLK */
3476 snd_soc_update_bits(codec, WM8962_IRQ_DEBOUNCE,
3477 WM8962_FLL_LOCK_DB | WM8962_PLL3_LOCK_DB |
3478 WM8962_PLL2_LOCK_DB | WM8962_TEMP_SHUT_DB,
3479 0);
3480
3481 wm8962_add_widgets(codec);
3482
3483 /* Save boards having to disable DMIC when not in use */
3484 dmicclk = false;
3485 dmicdat = false;
3486 for (i = 0; i < WM8962_MAX_GPIO; i++) {
3487 switch (snd_soc_read(codec, WM8962_GPIO_BASE + i)
3488 & WM8962_GP2_FN_MASK) {
3489 case WM8962_GPIO_FN_DMICCLK:
3490 dmicclk = true;
3491 break;
3492 case WM8962_GPIO_FN_DMICDAT:
3493 dmicdat = true;
3494 break;
3495 default:
3496 break;
3497 }
3498 }
3499 if (!dmicclk || !dmicdat) {
3500 dev_dbg(codec->dev, "DMIC not in use, disabling\n");
3501 snd_soc_dapm_nc_pin(&codec->dapm, "DMICDAT");
3502 }
3503 if (dmicclk != dmicdat)
3504 dev_warn(codec->dev, "DMIC GPIOs partially configured\n");
3505
3506 wm8962_init_beep(codec);
3507 wm8962_init_gpio(codec);
3508
3509 if (wm8962->irq) {
3510 if (pdata && pdata->irq_active_low) {
3511 trigger = IRQF_TRIGGER_LOW;
3512 irq_pol = WM8962_IRQ_POL;
3513 } else {
3514 trigger = IRQF_TRIGGER_HIGH;
3515 irq_pol = 0;
3516 }
3517
3518 snd_soc_update_bits(codec, WM8962_INTERRUPT_CONTROL,
3519 WM8962_IRQ_POL, irq_pol);
3520
3521 ret = request_threaded_irq(wm8962->irq, NULL, wm8962_irq,
3522 trigger | IRQF_ONESHOT,
3523 "wm8962", codec->dev);
3524 if (ret != 0) {
3525 dev_err(codec->dev, "Failed to request IRQ %d: %d\n",
3526 wm8962->irq, ret);
3527 wm8962->irq = 0;
3528 /* Non-fatal */
3529 } else {
3530 /* Enable some IRQs by default */
3531 snd_soc_update_bits(codec,
3532 WM8962_INTERRUPT_STATUS_2_MASK,
3533 WM8962_FLL_LOCK_EINT |
3534 WM8962_TEMP_SHUT_EINT |
3535 WM8962_FIFOS_ERR_EINT, 0);
3536 }
3537 }
3538
3539 return 0;
3540}
3541
3542static int wm8962_remove(struct snd_soc_codec *codec)
3543{
3544 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3545 int i;
3546
3547 if (wm8962->irq)
3548 free_irq(wm8962->irq, codec);
3549
3550 cancel_delayed_work_sync(&wm8962->mic_work);
3551
3552 wm8962_free_gpio(codec);
3553 wm8962_free_beep(codec);
3554 for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++)
3555 regulator_unregister_notifier(wm8962->supplies[i].consumer,
3556 &wm8962->disable_nb[i]);
3557
3558 return 0;
3559}
3560
3561static struct snd_soc_codec_driver soc_codec_dev_wm8962 = {
3562 .probe = wm8962_probe,
3563 .remove = wm8962_remove,
3564 .set_bias_level = wm8962_set_bias_level,
3565 .set_pll = wm8962_set_fll,
3566 .idle_bias_off = true,
3567};
3568
3569/* Improve power consumption for IN4 DC measurement mode */
3570static const struct reg_default wm8962_dc_measure[] = {
3571 { 0xfd, 0x1 },
3572 { 0xcc, 0x40 },
3573 { 0xfd, 0 },
3574};
3575
3576static const struct regmap_config wm8962_regmap = {
3577 .reg_bits = 16,
3578 .val_bits = 16,
3579
3580 .max_register = WM8962_MAX_REGISTER,
3581 .reg_defaults = wm8962_reg,
3582 .num_reg_defaults = ARRAY_SIZE(wm8962_reg),
3583 .volatile_reg = wm8962_volatile_register,
3584 .readable_reg = wm8962_readable_register,
3585 .cache_type = REGCACHE_RBTREE,
3586};
3587
3588static __devinit int wm8962_i2c_probe(struct i2c_client *i2c,
3589 const struct i2c_device_id *id)
3590{
3591 struct wm8962_pdata *pdata = dev_get_platdata(&i2c->dev);
3592 struct wm8962_priv *wm8962;
3593 unsigned int reg;
3594 int ret, i;
3595
3596 wm8962 = devm_kzalloc(&i2c->dev, sizeof(struct wm8962_priv),
3597 GFP_KERNEL);
3598 if (wm8962 == NULL)
3599 return -ENOMEM;
3600
3601 i2c_set_clientdata(i2c, wm8962);
3602
3603 INIT_DELAYED_WORK(&wm8962->mic_work, wm8962_mic_work);
3604 init_completion(&wm8962->fll_lock);
3605 wm8962->irq = i2c->irq;
3606
3607 for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++)
3608 wm8962->supplies[i].supply = wm8962_supply_names[i];
3609
3610 ret = regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8962->supplies),
3611 wm8962->supplies);
3612 if (ret != 0) {
3613 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
3614 goto err;
3615 }
3616
3617 ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies),
3618 wm8962->supplies);
3619 if (ret != 0) {
3620 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
3621 goto err_get;
3622 }
3623
3624 wm8962->regmap = regmap_init_i2c(i2c, &wm8962_regmap);
3625 if (IS_ERR(wm8962->regmap)) {
3626 ret = PTR_ERR(wm8962->regmap);
3627 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
3628 goto err_enable;
3629 }
3630
3631 /*
3632 * We haven't marked the chip revision as volatile due to
3633 * sharing a register with the right input volume; explicitly
3634 * bypass the cache to read it.
3635 */
3636 regcache_cache_bypass(wm8962->regmap, true);
3637
3638 ret = regmap_read(wm8962->regmap, WM8962_SOFTWARE_RESET, ®);
3639 if (ret < 0) {
3640 dev_err(&i2c->dev, "Failed to read ID register\n");
3641 goto err_regmap;
3642 }
3643 if (reg != 0x6243) {
3644 dev_err(&i2c->dev,
3645 "Device is not a WM8962, ID %x != 0x6243\n", reg);
3646 ret = -EINVAL;
3647 goto err_regmap;
3648 }
3649
3650 ret = regmap_read(wm8962->regmap, WM8962_RIGHT_INPUT_VOLUME, ®);
3651 if (ret < 0) {
3652 dev_err(&i2c->dev, "Failed to read device revision: %d\n",
3653 ret);
3654 goto err_regmap;
3655 }
3656
3657 dev_info(&i2c->dev, "customer id %x revision %c\n",
3658 (reg & WM8962_CUST_ID_MASK) >> WM8962_CUST_ID_SHIFT,
3659 ((reg & WM8962_CHIP_REV_MASK) >> WM8962_CHIP_REV_SHIFT)
3660 + 'A');
3661
3662 regcache_cache_bypass(wm8962->regmap, false);
3663
3664 ret = wm8962_reset(wm8962);
3665 if (ret < 0) {
3666 dev_err(&i2c->dev, "Failed to issue reset\n");
3667 goto err_regmap;
3668 }
3669
3670 if (pdata && pdata->in4_dc_measure) {
3671 ret = regmap_register_patch(wm8962->regmap,
3672 wm8962_dc_measure,
3673 ARRAY_SIZE(wm8962_dc_measure));
3674 if (ret != 0)
3675 dev_err(&i2c->dev,
3676 "Failed to configure for DC mesurement: %d\n",
3677 ret);
3678 }
3679
3680 pm_runtime_enable(&i2c->dev);
3681 pm_request_idle(&i2c->dev);
3682
3683 ret = snd_soc_register_codec(&i2c->dev,
3684 &soc_codec_dev_wm8962, &wm8962_dai, 1);
3685 if (ret < 0)
3686 goto err_regmap;
3687
3688 /* The drivers should power up as needed */
3689 regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
3690
3691 return 0;
3692
3693err_regmap:
3694 regmap_exit(wm8962->regmap);
3695err_enable:
3696 regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
3697err_get:
3698 regulator_bulk_free(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
3699err:
3700 return ret;
3701}
3702
3703static __devexit int wm8962_i2c_remove(struct i2c_client *client)
3704{
3705 struct wm8962_priv *wm8962 = dev_get_drvdata(&client->dev);
3706
3707 snd_soc_unregister_codec(&client->dev);
3708 regmap_exit(wm8962->regmap);
3709 regulator_bulk_free(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
3710 return 0;
3711}
3712
3713#ifdef CONFIG_PM_RUNTIME
3714static int wm8962_runtime_resume(struct device *dev)
3715{
3716 struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
3717 int ret;
3718
3719 ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies),
3720 wm8962->supplies);
3721 if (ret != 0) {
3722 dev_err(dev,
3723 "Failed to enable supplies: %d\n", ret);
3724 return ret;
3725 }
3726
3727 regcache_cache_only(wm8962->regmap, false);
3728
3729 wm8962_reset(wm8962);
3730
3731 regcache_sync(wm8962->regmap);
3732
3733 regmap_update_bits(wm8962->regmap, WM8962_ANTI_POP,
3734 WM8962_STARTUP_BIAS_ENA | WM8962_VMID_BUF_ENA,
3735 WM8962_STARTUP_BIAS_ENA | WM8962_VMID_BUF_ENA);
3736
3737 /* Bias enable at 2*50k for ramp */
3738 regmap_update_bits(wm8962->regmap, WM8962_PWR_MGMT_1,
3739 WM8962_VMID_SEL_MASK | WM8962_BIAS_ENA,
3740 WM8962_BIAS_ENA | 0x180);
3741
3742 msleep(5);
3743
3744 /* VMID back to 2x250k for standby */
3745 regmap_update_bits(wm8962->regmap, WM8962_PWR_MGMT_1,
3746 WM8962_VMID_SEL_MASK, 0x100);
3747
3748 return 0;
3749}
3750
3751static int wm8962_runtime_suspend(struct device *dev)
3752{
3753 struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
3754
3755 regmap_update_bits(wm8962->regmap, WM8962_PWR_MGMT_1,
3756 WM8962_VMID_SEL_MASK | WM8962_BIAS_ENA, 0);
3757
3758 regmap_update_bits(wm8962->regmap, WM8962_ANTI_POP,
3759 WM8962_STARTUP_BIAS_ENA |
3760 WM8962_VMID_BUF_ENA, 0);
3761
3762 regcache_cache_only(wm8962->regmap, true);
3763
3764 regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies),
3765 wm8962->supplies);
3766
3767 return 0;
3768}
3769#endif
3770
3771static struct dev_pm_ops wm8962_pm = {
3772 SET_RUNTIME_PM_OPS(wm8962_runtime_suspend, wm8962_runtime_resume, NULL)
3773};
3774
3775static const struct i2c_device_id wm8962_i2c_id[] = {
3776 { "wm8962", 0 },
3777 { }
3778};
3779MODULE_DEVICE_TABLE(i2c, wm8962_i2c_id);
3780
3781static struct i2c_driver wm8962_i2c_driver = {
3782 .driver = {
3783 .name = "wm8962",
3784 .owner = THIS_MODULE,
3785 .pm = &wm8962_pm,
3786 },
3787 .probe = wm8962_i2c_probe,
3788 .remove = __devexit_p(wm8962_i2c_remove),
3789 .id_table = wm8962_i2c_id,
3790};
3791
3792module_i2c_driver(wm8962_i2c_driver);
3793
3794MODULE_DESCRIPTION("ASoC WM8962 driver");
3795MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3796MODULE_LICENSE("GPL");