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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * linux/sound/soc/codecs/tlv320aic32x4.c
4 *
5 * Copyright 2011 Vista Silicon S.L.
6 *
7 * Author: Javier Martin <javier.martin@vista-silicon.com>
8 *
9 * Based on sound/soc/codecs/wm8974 and TI driver for kernel 2.6.27.
10 */
11
12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/init.h>
15#include <linux/delay.h>
16#include <linux/pm.h>
17#include <linux/gpio.h>
18#include <linux/of_gpio.h>
19#include <linux/cdev.h>
20#include <linux/slab.h>
21#include <linux/clk.h>
22#include <linux/of_clk.h>
23#include <linux/regulator/consumer.h>
24
25#include <sound/tlv320aic32x4.h>
26#include <sound/core.h>
27#include <sound/pcm.h>
28#include <sound/pcm_params.h>
29#include <sound/soc.h>
30#include <sound/soc-dapm.h>
31#include <sound/initval.h>
32#include <sound/tlv.h>
33
34#include "tlv320aic32x4.h"
35
36struct aic32x4_priv {
37 struct regmap *regmap;
38 u32 power_cfg;
39 u32 micpga_routing;
40 bool swapdacs;
41 int rstn_gpio;
42 const char *mclk_name;
43
44 struct regulator *supply_ldo;
45 struct regulator *supply_iov;
46 struct regulator *supply_dv;
47 struct regulator *supply_av;
48
49 struct aic32x4_setup_data *setup;
50 struct device *dev;
51 enum aic32x4_type type;
52
53 unsigned int fmt;
54};
55
56static int aic32x4_reset_adc(struct snd_soc_dapm_widget *w,
57 struct snd_kcontrol *kcontrol, int event)
58{
59 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
60 u32 adc_reg;
61
62 /*
63 * Workaround: the datasheet does not mention a required programming
64 * sequence but experiments show the ADC needs to be reset after each
65 * capture to avoid audible artifacts.
66 */
67 switch (event) {
68 case SND_SOC_DAPM_POST_PMD:
69 adc_reg = snd_soc_component_read(component, AIC32X4_ADCSETUP);
70 snd_soc_component_write(component, AIC32X4_ADCSETUP, adc_reg |
71 AIC32X4_LADC_EN | AIC32X4_RADC_EN);
72 snd_soc_component_write(component, AIC32X4_ADCSETUP, adc_reg);
73 break;
74 }
75 return 0;
76};
77
78static int mic_bias_event(struct snd_soc_dapm_widget *w,
79 struct snd_kcontrol *kcontrol, int event)
80{
81 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
82
83 switch (event) {
84 case SND_SOC_DAPM_POST_PMU:
85 /* Change Mic Bias Registor */
86 snd_soc_component_update_bits(component, AIC32X4_MICBIAS,
87 AIC32x4_MICBIAS_MASK,
88 AIC32X4_MICBIAS_LDOIN |
89 AIC32X4_MICBIAS_2075V);
90 printk(KERN_DEBUG "%s: Mic Bias will be turned ON\n", __func__);
91 break;
92 case SND_SOC_DAPM_PRE_PMD:
93 snd_soc_component_update_bits(component, AIC32X4_MICBIAS,
94 AIC32x4_MICBIAS_MASK, 0);
95 printk(KERN_DEBUG "%s: Mic Bias will be turned OFF\n",
96 __func__);
97 break;
98 }
99
100 return 0;
101}
102
103
104static int aic32x4_get_mfp1_gpio(struct snd_kcontrol *kcontrol,
105 struct snd_ctl_elem_value *ucontrol)
106{
107 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
108 u8 val;
109
110 val = snd_soc_component_read(component, AIC32X4_DINCTL);
111
112 ucontrol->value.integer.value[0] = (val & 0x01);
113
114 return 0;
115};
116
117static int aic32x4_set_mfp2_gpio(struct snd_kcontrol *kcontrol,
118 struct snd_ctl_elem_value *ucontrol)
119{
120 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
121 u8 val;
122 u8 gpio_check;
123
124 val = snd_soc_component_read(component, AIC32X4_DOUTCTL);
125 gpio_check = (val & AIC32X4_MFP_GPIO_ENABLED);
126 if (gpio_check != AIC32X4_MFP_GPIO_ENABLED) {
127 printk(KERN_ERR "%s: MFP2 is not configure as a GPIO output\n",
128 __func__);
129 return -EINVAL;
130 }
131
132 if (ucontrol->value.integer.value[0] == (val & AIC32X4_MFP2_GPIO_OUT_HIGH))
133 return 0;
134
135 if (ucontrol->value.integer.value[0])
136 val |= ucontrol->value.integer.value[0];
137 else
138 val &= ~AIC32X4_MFP2_GPIO_OUT_HIGH;
139
140 snd_soc_component_write(component, AIC32X4_DOUTCTL, val);
141
142 return 0;
143};
144
145static int aic32x4_get_mfp3_gpio(struct snd_kcontrol *kcontrol,
146 struct snd_ctl_elem_value *ucontrol)
147{
148 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
149 u8 val;
150
151 val = snd_soc_component_read(component, AIC32X4_SCLKCTL);
152
153 ucontrol->value.integer.value[0] = (val & 0x01);
154
155 return 0;
156};
157
158static int aic32x4_set_mfp4_gpio(struct snd_kcontrol *kcontrol,
159 struct snd_ctl_elem_value *ucontrol)
160{
161 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
162 u8 val;
163 u8 gpio_check;
164
165 val = snd_soc_component_read(component, AIC32X4_MISOCTL);
166 gpio_check = (val & AIC32X4_MFP_GPIO_ENABLED);
167 if (gpio_check != AIC32X4_MFP_GPIO_ENABLED) {
168 printk(KERN_ERR "%s: MFP4 is not configure as a GPIO output\n",
169 __func__);
170 return -EINVAL;
171 }
172
173 if (ucontrol->value.integer.value[0] == (val & AIC32X4_MFP5_GPIO_OUT_HIGH))
174 return 0;
175
176 if (ucontrol->value.integer.value[0])
177 val |= ucontrol->value.integer.value[0];
178 else
179 val &= ~AIC32X4_MFP5_GPIO_OUT_HIGH;
180
181 snd_soc_component_write(component, AIC32X4_MISOCTL, val);
182
183 return 0;
184};
185
186static int aic32x4_get_mfp5_gpio(struct snd_kcontrol *kcontrol,
187 struct snd_ctl_elem_value *ucontrol)
188{
189 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
190 u8 val;
191
192 val = snd_soc_component_read(component, AIC32X4_GPIOCTL);
193 ucontrol->value.integer.value[0] = ((val & 0x2) >> 1);
194
195 return 0;
196};
197
198static int aic32x4_set_mfp5_gpio(struct snd_kcontrol *kcontrol,
199 struct snd_ctl_elem_value *ucontrol)
200{
201 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
202 u8 val;
203 u8 gpio_check;
204
205 val = snd_soc_component_read(component, AIC32X4_GPIOCTL);
206 gpio_check = (val & AIC32X4_MFP5_GPIO_OUTPUT);
207 if (gpio_check != AIC32X4_MFP5_GPIO_OUTPUT) {
208 printk(KERN_ERR "%s: MFP5 is not configure as a GPIO output\n",
209 __func__);
210 return -EINVAL;
211 }
212
213 if (ucontrol->value.integer.value[0] == (val & 0x1))
214 return 0;
215
216 if (ucontrol->value.integer.value[0])
217 val |= ucontrol->value.integer.value[0];
218 else
219 val &= 0xfe;
220
221 snd_soc_component_write(component, AIC32X4_GPIOCTL, val);
222
223 return 0;
224};
225
226static const struct snd_kcontrol_new aic32x4_mfp1[] = {
227 SOC_SINGLE_BOOL_EXT("MFP1 GPIO", 0, aic32x4_get_mfp1_gpio, NULL),
228};
229
230static const struct snd_kcontrol_new aic32x4_mfp2[] = {
231 SOC_SINGLE_BOOL_EXT("MFP2 GPIO", 0, NULL, aic32x4_set_mfp2_gpio),
232};
233
234static const struct snd_kcontrol_new aic32x4_mfp3[] = {
235 SOC_SINGLE_BOOL_EXT("MFP3 GPIO", 0, aic32x4_get_mfp3_gpio, NULL),
236};
237
238static const struct snd_kcontrol_new aic32x4_mfp4[] = {
239 SOC_SINGLE_BOOL_EXT("MFP4 GPIO", 0, NULL, aic32x4_set_mfp4_gpio),
240};
241
242static const struct snd_kcontrol_new aic32x4_mfp5[] = {
243 SOC_SINGLE_BOOL_EXT("MFP5 GPIO", 0, aic32x4_get_mfp5_gpio,
244 aic32x4_set_mfp5_gpio),
245};
246
247/* 0dB min, 0.5dB steps */
248static DECLARE_TLV_DB_SCALE(tlv_step_0_5, 0, 50, 0);
249/* -63.5dB min, 0.5dB steps */
250static DECLARE_TLV_DB_SCALE(tlv_pcm, -6350, 50, 0);
251/* -6dB min, 1dB steps */
252static DECLARE_TLV_DB_SCALE(tlv_driver_gain, -600, 100, 0);
253/* -12dB min, 0.5dB steps */
254static DECLARE_TLV_DB_SCALE(tlv_adc_vol, -1200, 50, 0);
255/* -6dB min, 1dB steps */
256static DECLARE_TLV_DB_SCALE(tlv_tas_driver_gain, -5850, 50, 0);
257static DECLARE_TLV_DB_SCALE(tlv_amp_vol, 0, 600, 1);
258
259static const char * const lo_cm_text[] = {
260 "Full Chip", "1.65V",
261};
262
263static SOC_ENUM_SINGLE_DECL(lo_cm_enum, AIC32X4_CMMODE, 3, lo_cm_text);
264
265static const char * const ptm_text[] = {
266 "P3", "P2", "P1",
267};
268
269static SOC_ENUM_SINGLE_DECL(l_ptm_enum, AIC32X4_LPLAYBACK, 2, ptm_text);
270static SOC_ENUM_SINGLE_DECL(r_ptm_enum, AIC32X4_RPLAYBACK, 2, ptm_text);
271
272static const struct snd_kcontrol_new aic32x4_snd_controls[] = {
273 SOC_DOUBLE_R_S_TLV("PCM Playback Volume", AIC32X4_LDACVOL,
274 AIC32X4_RDACVOL, 0, -0x7f, 0x30, 7, 0, tlv_pcm),
275 SOC_ENUM("DAC Left Playback PowerTune Switch", l_ptm_enum),
276 SOC_ENUM("DAC Right Playback PowerTune Switch", r_ptm_enum),
277 SOC_DOUBLE_R_S_TLV("HP Driver Gain Volume", AIC32X4_HPLGAIN,
278 AIC32X4_HPRGAIN, 0, -0x6, 0x1d, 5, 0,
279 tlv_driver_gain),
280 SOC_DOUBLE_R_S_TLV("LO Driver Gain Volume", AIC32X4_LOLGAIN,
281 AIC32X4_LORGAIN, 0, -0x6, 0x1d, 5, 0,
282 tlv_driver_gain),
283 SOC_DOUBLE_R("HP DAC Playback Switch", AIC32X4_HPLGAIN,
284 AIC32X4_HPRGAIN, 6, 0x01, 1),
285 SOC_DOUBLE_R("LO DAC Playback Switch", AIC32X4_LOLGAIN,
286 AIC32X4_LORGAIN, 6, 0x01, 1),
287 SOC_ENUM("LO Playback Common Mode Switch", lo_cm_enum),
288 SOC_DOUBLE_R("Mic PGA Switch", AIC32X4_LMICPGAVOL,
289 AIC32X4_RMICPGAVOL, 7, 0x01, 1),
290
291 SOC_SINGLE("ADCFGA Left Mute Switch", AIC32X4_ADCFGA, 7, 1, 0),
292 SOC_SINGLE("ADCFGA Right Mute Switch", AIC32X4_ADCFGA, 3, 1, 0),
293
294 SOC_DOUBLE_R_S_TLV("ADC Level Volume", AIC32X4_LADCVOL,
295 AIC32X4_RADCVOL, 0, -0x18, 0x28, 6, 0, tlv_adc_vol),
296 SOC_DOUBLE_R_TLV("PGA Level Volume", AIC32X4_LMICPGAVOL,
297 AIC32X4_RMICPGAVOL, 0, 0x5f, 0, tlv_step_0_5),
298
299 SOC_SINGLE("Auto-mute Switch", AIC32X4_DACMUTE, 4, 7, 0),
300
301 SOC_SINGLE("AGC Left Switch", AIC32X4_LAGC1, 7, 1, 0),
302 SOC_SINGLE("AGC Right Switch", AIC32X4_RAGC1, 7, 1, 0),
303 SOC_DOUBLE_R("AGC Target Level", AIC32X4_LAGC1, AIC32X4_RAGC1,
304 4, 0x07, 0),
305 SOC_DOUBLE_R("AGC Gain Hysteresis", AIC32X4_LAGC1, AIC32X4_RAGC1,
306 0, 0x03, 0),
307 SOC_DOUBLE_R("AGC Hysteresis", AIC32X4_LAGC2, AIC32X4_RAGC2,
308 6, 0x03, 0),
309 SOC_DOUBLE_R("AGC Noise Threshold", AIC32X4_LAGC2, AIC32X4_RAGC2,
310 1, 0x1F, 0),
311 SOC_DOUBLE_R("AGC Max PGA", AIC32X4_LAGC3, AIC32X4_RAGC3,
312 0, 0x7F, 0),
313 SOC_DOUBLE_R("AGC Attack Time", AIC32X4_LAGC4, AIC32X4_RAGC4,
314 3, 0x1F, 0),
315 SOC_DOUBLE_R("AGC Decay Time", AIC32X4_LAGC5, AIC32X4_RAGC5,
316 3, 0x1F, 0),
317 SOC_DOUBLE_R("AGC Noise Debounce", AIC32X4_LAGC6, AIC32X4_RAGC6,
318 0, 0x1F, 0),
319 SOC_DOUBLE_R("AGC Signal Debounce", AIC32X4_LAGC7, AIC32X4_RAGC7,
320 0, 0x0F, 0),
321};
322
323static const struct snd_kcontrol_new hpl_output_mixer_controls[] = {
324 SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_HPLROUTE, 3, 1, 0),
325 SOC_DAPM_SINGLE("IN1_L Switch", AIC32X4_HPLROUTE, 2, 1, 0),
326};
327
328static const struct snd_kcontrol_new hpr_output_mixer_controls[] = {
329 SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_HPRROUTE, 3, 1, 0),
330 SOC_DAPM_SINGLE("IN1_R Switch", AIC32X4_HPRROUTE, 2, 1, 0),
331};
332
333static const struct snd_kcontrol_new lol_output_mixer_controls[] = {
334 SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_LOLROUTE, 3, 1, 0),
335};
336
337static const struct snd_kcontrol_new lor_output_mixer_controls[] = {
338 SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_LORROUTE, 3, 1, 0),
339};
340
341static const char * const resistor_text[] = {
342 "Off", "10 kOhm", "20 kOhm", "40 kOhm",
343};
344
345/* Left mixer pins */
346static SOC_ENUM_SINGLE_DECL(in1l_lpga_p_enum, AIC32X4_LMICPGAPIN, 6, resistor_text);
347static SOC_ENUM_SINGLE_DECL(in2l_lpga_p_enum, AIC32X4_LMICPGAPIN, 4, resistor_text);
348static SOC_ENUM_SINGLE_DECL(in3l_lpga_p_enum, AIC32X4_LMICPGAPIN, 2, resistor_text);
349static SOC_ENUM_SINGLE_DECL(in1r_lpga_p_enum, AIC32X4_LMICPGAPIN, 0, resistor_text);
350
351static SOC_ENUM_SINGLE_DECL(cml_lpga_n_enum, AIC32X4_LMICPGANIN, 6, resistor_text);
352static SOC_ENUM_SINGLE_DECL(in2r_lpga_n_enum, AIC32X4_LMICPGANIN, 4, resistor_text);
353static SOC_ENUM_SINGLE_DECL(in3r_lpga_n_enum, AIC32X4_LMICPGANIN, 2, resistor_text);
354
355static const struct snd_kcontrol_new in1l_to_lmixer_controls[] = {
356 SOC_DAPM_ENUM("IN1_L L+ Switch", in1l_lpga_p_enum),
357};
358static const struct snd_kcontrol_new in2l_to_lmixer_controls[] = {
359 SOC_DAPM_ENUM("IN2_L L+ Switch", in2l_lpga_p_enum),
360};
361static const struct snd_kcontrol_new in3l_to_lmixer_controls[] = {
362 SOC_DAPM_ENUM("IN3_L L+ Switch", in3l_lpga_p_enum),
363};
364static const struct snd_kcontrol_new in1r_to_lmixer_controls[] = {
365 SOC_DAPM_ENUM("IN1_R L+ Switch", in1r_lpga_p_enum),
366};
367static const struct snd_kcontrol_new cml_to_lmixer_controls[] = {
368 SOC_DAPM_ENUM("CM_L L- Switch", cml_lpga_n_enum),
369};
370static const struct snd_kcontrol_new in2r_to_lmixer_controls[] = {
371 SOC_DAPM_ENUM("IN2_R L- Switch", in2r_lpga_n_enum),
372};
373static const struct snd_kcontrol_new in3r_to_lmixer_controls[] = {
374 SOC_DAPM_ENUM("IN3_R L- Switch", in3r_lpga_n_enum),
375};
376
377/* Right mixer pins */
378static SOC_ENUM_SINGLE_DECL(in1r_rpga_p_enum, AIC32X4_RMICPGAPIN, 6, resistor_text);
379static SOC_ENUM_SINGLE_DECL(in2r_rpga_p_enum, AIC32X4_RMICPGAPIN, 4, resistor_text);
380static SOC_ENUM_SINGLE_DECL(in3r_rpga_p_enum, AIC32X4_RMICPGAPIN, 2, resistor_text);
381static SOC_ENUM_SINGLE_DECL(in2l_rpga_p_enum, AIC32X4_RMICPGAPIN, 0, resistor_text);
382static SOC_ENUM_SINGLE_DECL(cmr_rpga_n_enum, AIC32X4_RMICPGANIN, 6, resistor_text);
383static SOC_ENUM_SINGLE_DECL(in1l_rpga_n_enum, AIC32X4_RMICPGANIN, 4, resistor_text);
384static SOC_ENUM_SINGLE_DECL(in3l_rpga_n_enum, AIC32X4_RMICPGANIN, 2, resistor_text);
385
386static const struct snd_kcontrol_new in1r_to_rmixer_controls[] = {
387 SOC_DAPM_ENUM("IN1_R R+ Switch", in1r_rpga_p_enum),
388};
389static const struct snd_kcontrol_new in2r_to_rmixer_controls[] = {
390 SOC_DAPM_ENUM("IN2_R R+ Switch", in2r_rpga_p_enum),
391};
392static const struct snd_kcontrol_new in3r_to_rmixer_controls[] = {
393 SOC_DAPM_ENUM("IN3_R R+ Switch", in3r_rpga_p_enum),
394};
395static const struct snd_kcontrol_new in2l_to_rmixer_controls[] = {
396 SOC_DAPM_ENUM("IN2_L R+ Switch", in2l_rpga_p_enum),
397};
398static const struct snd_kcontrol_new cmr_to_rmixer_controls[] = {
399 SOC_DAPM_ENUM("CM_R R- Switch", cmr_rpga_n_enum),
400};
401static const struct snd_kcontrol_new in1l_to_rmixer_controls[] = {
402 SOC_DAPM_ENUM("IN1_L R- Switch", in1l_rpga_n_enum),
403};
404static const struct snd_kcontrol_new in3l_to_rmixer_controls[] = {
405 SOC_DAPM_ENUM("IN3_L R- Switch", in3l_rpga_n_enum),
406};
407
408static const struct snd_soc_dapm_widget aic32x4_dapm_widgets[] = {
409 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", AIC32X4_DACSETUP, 7, 0),
410 SND_SOC_DAPM_MIXER("HPL Output Mixer", SND_SOC_NOPM, 0, 0,
411 &hpl_output_mixer_controls[0],
412 ARRAY_SIZE(hpl_output_mixer_controls)),
413 SND_SOC_DAPM_PGA("HPL Power", AIC32X4_OUTPWRCTL, 5, 0, NULL, 0),
414
415 SND_SOC_DAPM_MIXER("LOL Output Mixer", SND_SOC_NOPM, 0, 0,
416 &lol_output_mixer_controls[0],
417 ARRAY_SIZE(lol_output_mixer_controls)),
418 SND_SOC_DAPM_PGA("LOL Power", AIC32X4_OUTPWRCTL, 3, 0, NULL, 0),
419
420 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", AIC32X4_DACSETUP, 6, 0),
421 SND_SOC_DAPM_MIXER("HPR Output Mixer", SND_SOC_NOPM, 0, 0,
422 &hpr_output_mixer_controls[0],
423 ARRAY_SIZE(hpr_output_mixer_controls)),
424 SND_SOC_DAPM_PGA("HPR Power", AIC32X4_OUTPWRCTL, 4, 0, NULL, 0),
425 SND_SOC_DAPM_MIXER("LOR Output Mixer", SND_SOC_NOPM, 0, 0,
426 &lor_output_mixer_controls[0],
427 ARRAY_SIZE(lor_output_mixer_controls)),
428 SND_SOC_DAPM_PGA("LOR Power", AIC32X4_OUTPWRCTL, 2, 0, NULL, 0),
429
430 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", AIC32X4_ADCSETUP, 6, 0),
431 SND_SOC_DAPM_MUX("IN1_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
432 in1r_to_rmixer_controls),
433 SND_SOC_DAPM_MUX("IN2_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
434 in2r_to_rmixer_controls),
435 SND_SOC_DAPM_MUX("IN3_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
436 in3r_to_rmixer_controls),
437 SND_SOC_DAPM_MUX("IN2_L to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
438 in2l_to_rmixer_controls),
439 SND_SOC_DAPM_MUX("CM_R to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
440 cmr_to_rmixer_controls),
441 SND_SOC_DAPM_MUX("IN1_L to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
442 in1l_to_rmixer_controls),
443 SND_SOC_DAPM_MUX("IN3_L to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
444 in3l_to_rmixer_controls),
445
446 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", AIC32X4_ADCSETUP, 7, 0),
447 SND_SOC_DAPM_MUX("IN1_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
448 in1l_to_lmixer_controls),
449 SND_SOC_DAPM_MUX("IN2_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
450 in2l_to_lmixer_controls),
451 SND_SOC_DAPM_MUX("IN3_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
452 in3l_to_lmixer_controls),
453 SND_SOC_DAPM_MUX("IN1_R to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
454 in1r_to_lmixer_controls),
455 SND_SOC_DAPM_MUX("CM_L to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
456 cml_to_lmixer_controls),
457 SND_SOC_DAPM_MUX("IN2_R to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
458 in2r_to_lmixer_controls),
459 SND_SOC_DAPM_MUX("IN3_R to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
460 in3r_to_lmixer_controls),
461
462 SND_SOC_DAPM_SUPPLY("Mic Bias", AIC32X4_MICBIAS, 6, 0, mic_bias_event,
463 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
464
465 SND_SOC_DAPM_POST("ADC Reset", aic32x4_reset_adc),
466
467 SND_SOC_DAPM_OUTPUT("HPL"),
468 SND_SOC_DAPM_OUTPUT("HPR"),
469 SND_SOC_DAPM_OUTPUT("LOL"),
470 SND_SOC_DAPM_OUTPUT("LOR"),
471 SND_SOC_DAPM_INPUT("IN1_L"),
472 SND_SOC_DAPM_INPUT("IN1_R"),
473 SND_SOC_DAPM_INPUT("IN2_L"),
474 SND_SOC_DAPM_INPUT("IN2_R"),
475 SND_SOC_DAPM_INPUT("IN3_L"),
476 SND_SOC_DAPM_INPUT("IN3_R"),
477 SND_SOC_DAPM_INPUT("CM_L"),
478 SND_SOC_DAPM_INPUT("CM_R"),
479};
480
481static const struct snd_soc_dapm_route aic32x4_dapm_routes[] = {
482 /* Left Output */
483 {"HPL Output Mixer", "L_DAC Switch", "Left DAC"},
484 {"HPL Output Mixer", "IN1_L Switch", "IN1_L"},
485
486 {"HPL Power", NULL, "HPL Output Mixer"},
487 {"HPL", NULL, "HPL Power"},
488
489 {"LOL Output Mixer", "L_DAC Switch", "Left DAC"},
490
491 {"LOL Power", NULL, "LOL Output Mixer"},
492 {"LOL", NULL, "LOL Power"},
493
494 /* Right Output */
495 {"HPR Output Mixer", "R_DAC Switch", "Right DAC"},
496 {"HPR Output Mixer", "IN1_R Switch", "IN1_R"},
497
498 {"HPR Power", NULL, "HPR Output Mixer"},
499 {"HPR", NULL, "HPR Power"},
500
501 {"LOR Output Mixer", "R_DAC Switch", "Right DAC"},
502
503 {"LOR Power", NULL, "LOR Output Mixer"},
504 {"LOR", NULL, "LOR Power"},
505
506 /* Right Input */
507 {"Right ADC", NULL, "IN1_R to Right Mixer Positive Resistor"},
508 {"IN1_R to Right Mixer Positive Resistor", "10 kOhm", "IN1_R"},
509 {"IN1_R to Right Mixer Positive Resistor", "20 kOhm", "IN1_R"},
510 {"IN1_R to Right Mixer Positive Resistor", "40 kOhm", "IN1_R"},
511
512 {"Right ADC", NULL, "IN2_R to Right Mixer Positive Resistor"},
513 {"IN2_R to Right Mixer Positive Resistor", "10 kOhm", "IN2_R"},
514 {"IN2_R to Right Mixer Positive Resistor", "20 kOhm", "IN2_R"},
515 {"IN2_R to Right Mixer Positive Resistor", "40 kOhm", "IN2_R"},
516
517 {"Right ADC", NULL, "IN3_R to Right Mixer Positive Resistor"},
518 {"IN3_R to Right Mixer Positive Resistor", "10 kOhm", "IN3_R"},
519 {"IN3_R to Right Mixer Positive Resistor", "20 kOhm", "IN3_R"},
520 {"IN3_R to Right Mixer Positive Resistor", "40 kOhm", "IN3_R"},
521
522 {"Right ADC", NULL, "IN2_L to Right Mixer Positive Resistor"},
523 {"IN2_L to Right Mixer Positive Resistor", "10 kOhm", "IN2_L"},
524 {"IN2_L to Right Mixer Positive Resistor", "20 kOhm", "IN2_L"},
525 {"IN2_L to Right Mixer Positive Resistor", "40 kOhm", "IN2_L"},
526
527 {"Right ADC", NULL, "CM_R to Right Mixer Negative Resistor"},
528 {"CM_R to Right Mixer Negative Resistor", "10 kOhm", "CM_R"},
529 {"CM_R to Right Mixer Negative Resistor", "20 kOhm", "CM_R"},
530 {"CM_R to Right Mixer Negative Resistor", "40 kOhm", "CM_R"},
531
532 {"Right ADC", NULL, "IN1_L to Right Mixer Negative Resistor"},
533 {"IN1_L to Right Mixer Negative Resistor", "10 kOhm", "IN1_L"},
534 {"IN1_L to Right Mixer Negative Resistor", "20 kOhm", "IN1_L"},
535 {"IN1_L to Right Mixer Negative Resistor", "40 kOhm", "IN1_L"},
536
537 {"Right ADC", NULL, "IN3_L to Right Mixer Negative Resistor"},
538 {"IN3_L to Right Mixer Negative Resistor", "10 kOhm", "IN3_L"},
539 {"IN3_L to Right Mixer Negative Resistor", "20 kOhm", "IN3_L"},
540 {"IN3_L to Right Mixer Negative Resistor", "40 kOhm", "IN3_L"},
541
542 /* Left Input */
543 {"Left ADC", NULL, "IN1_L to Left Mixer Positive Resistor"},
544 {"IN1_L to Left Mixer Positive Resistor", "10 kOhm", "IN1_L"},
545 {"IN1_L to Left Mixer Positive Resistor", "20 kOhm", "IN1_L"},
546 {"IN1_L to Left Mixer Positive Resistor", "40 kOhm", "IN1_L"},
547
548 {"Left ADC", NULL, "IN2_L to Left Mixer Positive Resistor"},
549 {"IN2_L to Left Mixer Positive Resistor", "10 kOhm", "IN2_L"},
550 {"IN2_L to Left Mixer Positive Resistor", "20 kOhm", "IN2_L"},
551 {"IN2_L to Left Mixer Positive Resistor", "40 kOhm", "IN2_L"},
552
553 {"Left ADC", NULL, "IN3_L to Left Mixer Positive Resistor"},
554 {"IN3_L to Left Mixer Positive Resistor", "10 kOhm", "IN3_L"},
555 {"IN3_L to Left Mixer Positive Resistor", "20 kOhm", "IN3_L"},
556 {"IN3_L to Left Mixer Positive Resistor", "40 kOhm", "IN3_L"},
557
558 {"Left ADC", NULL, "IN1_R to Left Mixer Positive Resistor"},
559 {"IN1_R to Left Mixer Positive Resistor", "10 kOhm", "IN1_R"},
560 {"IN1_R to Left Mixer Positive Resistor", "20 kOhm", "IN1_R"},
561 {"IN1_R to Left Mixer Positive Resistor", "40 kOhm", "IN1_R"},
562
563 {"Left ADC", NULL, "CM_L to Left Mixer Negative Resistor"},
564 {"CM_L to Left Mixer Negative Resistor", "10 kOhm", "CM_L"},
565 {"CM_L to Left Mixer Negative Resistor", "20 kOhm", "CM_L"},
566 {"CM_L to Left Mixer Negative Resistor", "40 kOhm", "CM_L"},
567
568 {"Left ADC", NULL, "IN2_R to Left Mixer Negative Resistor"},
569 {"IN2_R to Left Mixer Negative Resistor", "10 kOhm", "IN2_R"},
570 {"IN2_R to Left Mixer Negative Resistor", "20 kOhm", "IN2_R"},
571 {"IN2_R to Left Mixer Negative Resistor", "40 kOhm", "IN2_R"},
572
573 {"Left ADC", NULL, "IN3_R to Left Mixer Negative Resistor"},
574 {"IN3_R to Left Mixer Negative Resistor", "10 kOhm", "IN3_R"},
575 {"IN3_R to Left Mixer Negative Resistor", "20 kOhm", "IN3_R"},
576 {"IN3_R to Left Mixer Negative Resistor", "40 kOhm", "IN3_R"},
577};
578
579static const struct regmap_range_cfg aic32x4_regmap_pages[] = {
580 {
581 .selector_reg = 0,
582 .selector_mask = 0xff,
583 .window_start = 0,
584 .window_len = 128,
585 .range_min = 0,
586 .range_max = AIC32X4_REFPOWERUP,
587 },
588};
589
590const struct regmap_config aic32x4_regmap_config = {
591 .max_register = AIC32X4_REFPOWERUP,
592 .ranges = aic32x4_regmap_pages,
593 .num_ranges = ARRAY_SIZE(aic32x4_regmap_pages),
594};
595EXPORT_SYMBOL(aic32x4_regmap_config);
596
597static int aic32x4_set_dai_sysclk(struct snd_soc_dai *codec_dai,
598 int clk_id, unsigned int freq, int dir)
599{
600 struct snd_soc_component *component = codec_dai->component;
601 struct clk *mclk;
602 struct clk *pll;
603
604 pll = devm_clk_get(component->dev, "pll");
605 if (IS_ERR(pll))
606 return PTR_ERR(pll);
607
608 mclk = clk_get_parent(pll);
609
610 return clk_set_rate(mclk, freq);
611}
612
613static int aic32x4_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
614{
615 struct snd_soc_component *component = codec_dai->component;
616 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
617 u8 iface_reg_1 = 0;
618 u8 iface_reg_2 = 0;
619 u8 iface_reg_3 = 0;
620
621 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
622 case SND_SOC_DAIFMT_CBP_CFP:
623 iface_reg_1 |= AIC32X4_BCLKMASTER | AIC32X4_WCLKMASTER;
624 break;
625 case SND_SOC_DAIFMT_CBC_CFC:
626 break;
627 default:
628 printk(KERN_ERR "aic32x4: invalid clock provider\n");
629 return -EINVAL;
630 }
631
632 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
633 case SND_SOC_DAIFMT_I2S:
634 break;
635 case SND_SOC_DAIFMT_DSP_A:
636 iface_reg_1 |= (AIC32X4_DSP_MODE <<
637 AIC32X4_IFACE1_DATATYPE_SHIFT);
638 iface_reg_3 |= AIC32X4_BCLKINV_MASK; /* invert bit clock */
639 iface_reg_2 = 0x01; /* add offset 1 */
640 break;
641 case SND_SOC_DAIFMT_DSP_B:
642 iface_reg_1 |= (AIC32X4_DSP_MODE <<
643 AIC32X4_IFACE1_DATATYPE_SHIFT);
644 iface_reg_3 |= AIC32X4_BCLKINV_MASK; /* invert bit clock */
645 break;
646 case SND_SOC_DAIFMT_RIGHT_J:
647 iface_reg_1 |= (AIC32X4_RIGHT_JUSTIFIED_MODE <<
648 AIC32X4_IFACE1_DATATYPE_SHIFT);
649 break;
650 case SND_SOC_DAIFMT_LEFT_J:
651 iface_reg_1 |= (AIC32X4_LEFT_JUSTIFIED_MODE <<
652 AIC32X4_IFACE1_DATATYPE_SHIFT);
653 break;
654 default:
655 printk(KERN_ERR "aic32x4: invalid DAI interface format\n");
656 return -EINVAL;
657 }
658
659 aic32x4->fmt = fmt;
660
661 snd_soc_component_update_bits(component, AIC32X4_IFACE1,
662 AIC32X4_IFACE1_DATATYPE_MASK |
663 AIC32X4_IFACE1_MASTER_MASK, iface_reg_1);
664 snd_soc_component_update_bits(component, AIC32X4_IFACE2,
665 AIC32X4_DATA_OFFSET_MASK, iface_reg_2);
666 snd_soc_component_update_bits(component, AIC32X4_IFACE3,
667 AIC32X4_BCLKINV_MASK, iface_reg_3);
668
669 return 0;
670}
671
672static int aic32x4_set_aosr(struct snd_soc_component *component, u8 aosr)
673{
674 return snd_soc_component_write(component, AIC32X4_AOSR, aosr);
675}
676
677static int aic32x4_set_dosr(struct snd_soc_component *component, u16 dosr)
678{
679 snd_soc_component_write(component, AIC32X4_DOSRMSB, dosr >> 8);
680 snd_soc_component_write(component, AIC32X4_DOSRLSB,
681 (dosr & 0xff));
682
683 return 0;
684}
685
686static int aic32x4_set_processing_blocks(struct snd_soc_component *component,
687 u8 r_block, u8 p_block)
688{
689 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
690
691 if (aic32x4->type == AIC32X4_TYPE_TAS2505) {
692 if (r_block || p_block > 3)
693 return -EINVAL;
694
695 snd_soc_component_write(component, AIC32X4_DACSPB, p_block);
696 } else { /* AIC32x4 */
697 if (r_block > 18 || p_block > 25)
698 return -EINVAL;
699
700 snd_soc_component_write(component, AIC32X4_ADCSPB, r_block);
701 snd_soc_component_write(component, AIC32X4_DACSPB, p_block);
702 }
703
704 return 0;
705}
706
707static int aic32x4_setup_clocks(struct snd_soc_component *component,
708 unsigned int sample_rate, unsigned int channels,
709 unsigned int bit_depth)
710{
711 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
712 u8 aosr;
713 u16 dosr;
714 u8 adc_resource_class, dac_resource_class;
715 u8 madc, nadc, mdac, ndac, max_nadc, min_mdac, max_ndac;
716 u8 dosr_increment;
717 u16 max_dosr, min_dosr;
718 unsigned long adc_clock_rate, dac_clock_rate;
719 int ret;
720
721 static struct clk_bulk_data clocks[] = {
722 { .id = "pll" },
723 { .id = "nadc" },
724 { .id = "madc" },
725 { .id = "ndac" },
726 { .id = "mdac" },
727 { .id = "bdiv" },
728 };
729 ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks);
730 if (ret)
731 return ret;
732
733 if (sample_rate <= 48000) {
734 aosr = 128;
735 adc_resource_class = 6;
736 dac_resource_class = 8;
737 dosr_increment = 8;
738 if (aic32x4->type == AIC32X4_TYPE_TAS2505)
739 aic32x4_set_processing_blocks(component, 0, 1);
740 else
741 aic32x4_set_processing_blocks(component, 1, 1);
742 } else if (sample_rate <= 96000) {
743 aosr = 64;
744 adc_resource_class = 6;
745 dac_resource_class = 8;
746 dosr_increment = 4;
747 if (aic32x4->type == AIC32X4_TYPE_TAS2505)
748 aic32x4_set_processing_blocks(component, 0, 1);
749 else
750 aic32x4_set_processing_blocks(component, 1, 9);
751 } else if (sample_rate == 192000) {
752 aosr = 32;
753 adc_resource_class = 3;
754 dac_resource_class = 4;
755 dosr_increment = 2;
756 if (aic32x4->type == AIC32X4_TYPE_TAS2505)
757 aic32x4_set_processing_blocks(component, 0, 1);
758 else
759 aic32x4_set_processing_blocks(component, 13, 19);
760 } else {
761 dev_err(component->dev, "Sampling rate not supported\n");
762 return -EINVAL;
763 }
764
765 /* PCM over I2S is always 2-channel */
766 if ((aic32x4->fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_I2S)
767 channels = 2;
768
769 madc = DIV_ROUND_UP((32 * adc_resource_class), aosr);
770 max_dosr = (AIC32X4_MAX_DOSR_FREQ / sample_rate / dosr_increment) *
771 dosr_increment;
772 min_dosr = (AIC32X4_MIN_DOSR_FREQ / sample_rate / dosr_increment) *
773 dosr_increment;
774 max_nadc = AIC32X4_MAX_CODEC_CLKIN_FREQ / (madc * aosr * sample_rate);
775
776 for (nadc = max_nadc; nadc > 0; --nadc) {
777 adc_clock_rate = nadc * madc * aosr * sample_rate;
778 for (dosr = max_dosr; dosr >= min_dosr;
779 dosr -= dosr_increment) {
780 min_mdac = DIV_ROUND_UP((32 * dac_resource_class), dosr);
781 max_ndac = AIC32X4_MAX_CODEC_CLKIN_FREQ /
782 (min_mdac * dosr * sample_rate);
783 for (mdac = min_mdac; mdac <= 128; ++mdac) {
784 for (ndac = max_ndac; ndac > 0; --ndac) {
785 dac_clock_rate = ndac * mdac * dosr *
786 sample_rate;
787 if (dac_clock_rate == adc_clock_rate) {
788 if (clk_round_rate(clocks[0].clk, dac_clock_rate) == 0)
789 continue;
790
791 clk_set_rate(clocks[0].clk,
792 dac_clock_rate);
793
794 clk_set_rate(clocks[1].clk,
795 sample_rate * aosr *
796 madc);
797 clk_set_rate(clocks[2].clk,
798 sample_rate * aosr);
799 aic32x4_set_aosr(component,
800 aosr);
801
802 clk_set_rate(clocks[3].clk,
803 sample_rate * dosr *
804 mdac);
805 clk_set_rate(clocks[4].clk,
806 sample_rate * dosr);
807 aic32x4_set_dosr(component,
808 dosr);
809
810 clk_set_rate(clocks[5].clk,
811 sample_rate * channels *
812 bit_depth);
813
814 return 0;
815 }
816 }
817 }
818 }
819 }
820
821 dev_err(component->dev,
822 "Could not set clocks to support sample rate.\n");
823 return -EINVAL;
824}
825
826static int aic32x4_hw_params(struct snd_pcm_substream *substream,
827 struct snd_pcm_hw_params *params,
828 struct snd_soc_dai *dai)
829{
830 struct snd_soc_component *component = dai->component;
831 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
832 u8 iface1_reg = 0;
833 u8 dacsetup_reg = 0;
834
835 aic32x4_setup_clocks(component, params_rate(params),
836 params_channels(params),
837 params_physical_width(params));
838
839 switch (params_physical_width(params)) {
840 case 16:
841 iface1_reg |= (AIC32X4_WORD_LEN_16BITS <<
842 AIC32X4_IFACE1_DATALEN_SHIFT);
843 break;
844 case 20:
845 iface1_reg |= (AIC32X4_WORD_LEN_20BITS <<
846 AIC32X4_IFACE1_DATALEN_SHIFT);
847 break;
848 case 24:
849 iface1_reg |= (AIC32X4_WORD_LEN_24BITS <<
850 AIC32X4_IFACE1_DATALEN_SHIFT);
851 break;
852 case 32:
853 iface1_reg |= (AIC32X4_WORD_LEN_32BITS <<
854 AIC32X4_IFACE1_DATALEN_SHIFT);
855 break;
856 }
857 snd_soc_component_update_bits(component, AIC32X4_IFACE1,
858 AIC32X4_IFACE1_DATALEN_MASK, iface1_reg);
859
860 if (params_channels(params) == 1) {
861 dacsetup_reg = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2LCHN;
862 } else {
863 if (aic32x4->swapdacs)
864 dacsetup_reg = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2RCHN;
865 else
866 dacsetup_reg = AIC32X4_LDAC2LCHN | AIC32X4_RDAC2RCHN;
867 }
868 snd_soc_component_update_bits(component, AIC32X4_DACSETUP,
869 AIC32X4_DAC_CHAN_MASK, dacsetup_reg);
870
871 return 0;
872}
873
874static int aic32x4_mute(struct snd_soc_dai *dai, int mute, int direction)
875{
876 struct snd_soc_component *component = dai->component;
877
878 snd_soc_component_update_bits(component, AIC32X4_DACMUTE,
879 AIC32X4_MUTEON, mute ? AIC32X4_MUTEON : 0);
880
881 return 0;
882}
883
884static int aic32x4_set_bias_level(struct snd_soc_component *component,
885 enum snd_soc_bias_level level)
886{
887 int ret;
888
889 static struct clk_bulk_data clocks[] = {
890 { .id = "madc" },
891 { .id = "mdac" },
892 { .id = "bdiv" },
893 };
894
895 ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks);
896 if (ret)
897 return ret;
898
899 switch (level) {
900 case SND_SOC_BIAS_ON:
901 ret = clk_bulk_prepare_enable(ARRAY_SIZE(clocks), clocks);
902 if (ret) {
903 dev_err(component->dev, "Failed to enable clocks\n");
904 return ret;
905 }
906 break;
907 case SND_SOC_BIAS_PREPARE:
908 break;
909 case SND_SOC_BIAS_STANDBY:
910 /* Initial cold start */
911 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
912 break;
913
914 clk_bulk_disable_unprepare(ARRAY_SIZE(clocks), clocks);
915 break;
916 case SND_SOC_BIAS_OFF:
917 break;
918 }
919 return 0;
920}
921
922#define AIC32X4_RATES SNDRV_PCM_RATE_8000_192000
923#define AIC32X4_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
924 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_3LE \
925 | SNDRV_PCM_FMTBIT_S32_LE)
926
927static const struct snd_soc_dai_ops aic32x4_ops = {
928 .hw_params = aic32x4_hw_params,
929 .mute_stream = aic32x4_mute,
930 .set_fmt = aic32x4_set_dai_fmt,
931 .set_sysclk = aic32x4_set_dai_sysclk,
932 .no_capture_mute = 1,
933};
934
935static struct snd_soc_dai_driver aic32x4_dai = {
936 .name = "tlv320aic32x4-hifi",
937 .playback = {
938 .stream_name = "Playback",
939 .channels_min = 1,
940 .channels_max = 2,
941 .rates = AIC32X4_RATES,
942 .formats = AIC32X4_FORMATS,},
943 .capture = {
944 .stream_name = "Capture",
945 .channels_min = 1,
946 .channels_max = 8,
947 .rates = AIC32X4_RATES,
948 .formats = AIC32X4_FORMATS,},
949 .ops = &aic32x4_ops,
950 .symmetric_rate = 1,
951};
952
953static void aic32x4_setup_gpios(struct snd_soc_component *component)
954{
955 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
956
957 /* setup GPIO functions */
958 /* MFP1 */
959 if (aic32x4->setup->gpio_func[0] != AIC32X4_MFPX_DEFAULT_VALUE) {
960 snd_soc_component_write(component, AIC32X4_DINCTL,
961 aic32x4->setup->gpio_func[0]);
962 snd_soc_add_component_controls(component, aic32x4_mfp1,
963 ARRAY_SIZE(aic32x4_mfp1));
964 }
965
966 /* MFP2 */
967 if (aic32x4->setup->gpio_func[1] != AIC32X4_MFPX_DEFAULT_VALUE) {
968 snd_soc_component_write(component, AIC32X4_DOUTCTL,
969 aic32x4->setup->gpio_func[1]);
970 snd_soc_add_component_controls(component, aic32x4_mfp2,
971 ARRAY_SIZE(aic32x4_mfp2));
972 }
973
974 /* MFP3 */
975 if (aic32x4->setup->gpio_func[2] != AIC32X4_MFPX_DEFAULT_VALUE) {
976 snd_soc_component_write(component, AIC32X4_SCLKCTL,
977 aic32x4->setup->gpio_func[2]);
978 snd_soc_add_component_controls(component, aic32x4_mfp3,
979 ARRAY_SIZE(aic32x4_mfp3));
980 }
981
982 /* MFP4 */
983 if (aic32x4->setup->gpio_func[3] != AIC32X4_MFPX_DEFAULT_VALUE) {
984 snd_soc_component_write(component, AIC32X4_MISOCTL,
985 aic32x4->setup->gpio_func[3]);
986 snd_soc_add_component_controls(component, aic32x4_mfp4,
987 ARRAY_SIZE(aic32x4_mfp4));
988 }
989
990 /* MFP5 */
991 if (aic32x4->setup->gpio_func[4] != AIC32X4_MFPX_DEFAULT_VALUE) {
992 snd_soc_component_write(component, AIC32X4_GPIOCTL,
993 aic32x4->setup->gpio_func[4]);
994 snd_soc_add_component_controls(component, aic32x4_mfp5,
995 ARRAY_SIZE(aic32x4_mfp5));
996 }
997}
998
999static int aic32x4_component_probe(struct snd_soc_component *component)
1000{
1001 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
1002 u32 tmp_reg;
1003 int ret;
1004
1005 static struct clk_bulk_data clocks[] = {
1006 { .id = "codec_clkin" },
1007 { .id = "pll" },
1008 { .id = "bdiv" },
1009 { .id = "mdac" },
1010 };
1011
1012 ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks);
1013 if (ret)
1014 return ret;
1015
1016 if (aic32x4->setup)
1017 aic32x4_setup_gpios(component);
1018
1019 clk_set_parent(clocks[0].clk, clocks[1].clk);
1020 clk_set_parent(clocks[2].clk, clocks[3].clk);
1021
1022 /* Power platform configuration */
1023 if (aic32x4->power_cfg & AIC32X4_PWR_MICBIAS_2075_LDOIN) {
1024 snd_soc_component_write(component, AIC32X4_MICBIAS,
1025 AIC32X4_MICBIAS_LDOIN | AIC32X4_MICBIAS_2075V);
1026 }
1027 if (aic32x4->power_cfg & AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE)
1028 snd_soc_component_write(component, AIC32X4_PWRCFG, AIC32X4_AVDDWEAKDISABLE);
1029
1030 tmp_reg = (aic32x4->power_cfg & AIC32X4_PWR_AIC32X4_LDO_ENABLE) ?
1031 AIC32X4_LDOCTLEN : 0;
1032 snd_soc_component_write(component, AIC32X4_LDOCTL, tmp_reg);
1033
1034 tmp_reg = snd_soc_component_read(component, AIC32X4_CMMODE);
1035 if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36)
1036 tmp_reg |= AIC32X4_LDOIN_18_36;
1037 if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_HP_LDOIN_POWERED)
1038 tmp_reg |= AIC32X4_LDOIN2HP;
1039 snd_soc_component_write(component, AIC32X4_CMMODE, tmp_reg);
1040
1041 /* Mic PGA routing */
1042 if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_LMIC_IN2R_10K)
1043 snd_soc_component_write(component, AIC32X4_LMICPGANIN,
1044 AIC32X4_LMICPGANIN_IN2R_10K);
1045 else
1046 snd_soc_component_write(component, AIC32X4_LMICPGANIN,
1047 AIC32X4_LMICPGANIN_CM1L_10K);
1048 if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_RMIC_IN1L_10K)
1049 snd_soc_component_write(component, AIC32X4_RMICPGANIN,
1050 AIC32X4_RMICPGANIN_IN1L_10K);
1051 else
1052 snd_soc_component_write(component, AIC32X4_RMICPGANIN,
1053 AIC32X4_RMICPGANIN_CM1R_10K);
1054
1055 /*
1056 * Workaround: for an unknown reason, the ADC needs to be powered up
1057 * and down for the first capture to work properly. It seems related to
1058 * a HW BUG or some kind of behavior not documented in the datasheet.
1059 */
1060 tmp_reg = snd_soc_component_read(component, AIC32X4_ADCSETUP);
1061 snd_soc_component_write(component, AIC32X4_ADCSETUP, tmp_reg |
1062 AIC32X4_LADC_EN | AIC32X4_RADC_EN);
1063 snd_soc_component_write(component, AIC32X4_ADCSETUP, tmp_reg);
1064
1065 /*
1066 * Enable the fast charging feature and ensure the needed 40ms ellapsed
1067 * before using the analog circuits.
1068 */
1069 snd_soc_component_write(component, AIC32X4_REFPOWERUP,
1070 AIC32X4_REFPOWERUP_40MS);
1071 msleep(40);
1072
1073 return 0;
1074}
1075
1076static int aic32x4_of_xlate_dai_id(struct snd_soc_component *component,
1077 struct device_node *endpoint)
1078{
1079 /* return dai id 0, whatever the endpoint index */
1080 return 0;
1081}
1082
1083static const struct snd_soc_component_driver soc_component_dev_aic32x4 = {
1084 .probe = aic32x4_component_probe,
1085 .set_bias_level = aic32x4_set_bias_level,
1086 .controls = aic32x4_snd_controls,
1087 .num_controls = ARRAY_SIZE(aic32x4_snd_controls),
1088 .dapm_widgets = aic32x4_dapm_widgets,
1089 .num_dapm_widgets = ARRAY_SIZE(aic32x4_dapm_widgets),
1090 .dapm_routes = aic32x4_dapm_routes,
1091 .num_dapm_routes = ARRAY_SIZE(aic32x4_dapm_routes),
1092 .of_xlate_dai_id = aic32x4_of_xlate_dai_id,
1093 .suspend_bias_off = 1,
1094 .idle_bias_on = 1,
1095 .use_pmdown_time = 1,
1096 .endianness = 1,
1097};
1098
1099static const struct snd_kcontrol_new aic32x4_tas2505_snd_controls[] = {
1100 SOC_SINGLE_S8_TLV("PCM Playback Volume",
1101 AIC32X4_LDACVOL, -0x7f, 0x30, tlv_pcm),
1102 SOC_ENUM("DAC Playback PowerTune Switch", l_ptm_enum),
1103
1104 SOC_SINGLE_TLV("HP Driver Gain Volume",
1105 AIC32X4_HPLGAIN, 0, 0x74, 1, tlv_tas_driver_gain),
1106 SOC_SINGLE("HP DAC Playback Switch", AIC32X4_HPLGAIN, 6, 1, 1),
1107
1108 SOC_SINGLE_TLV("Speaker Driver Playback Volume",
1109 TAS2505_SPKVOL1, 0, 0x74, 1, tlv_tas_driver_gain),
1110 SOC_SINGLE_TLV("Speaker Amplifier Playback Volume",
1111 TAS2505_SPKVOL2, 4, 5, 0, tlv_amp_vol),
1112
1113 SOC_SINGLE("Auto-mute Switch", AIC32X4_DACMUTE, 4, 7, 0),
1114};
1115
1116static const struct snd_kcontrol_new hp_output_mixer_controls[] = {
1117 SOC_DAPM_SINGLE("DAC Switch", AIC32X4_HPLROUTE, 3, 1, 0),
1118};
1119
1120static const struct snd_soc_dapm_widget aic32x4_tas2505_dapm_widgets[] = {
1121 SND_SOC_DAPM_DAC("DAC", "Playback", AIC32X4_DACSETUP, 7, 0),
1122 SND_SOC_DAPM_MIXER("HP Output Mixer", SND_SOC_NOPM, 0, 0,
1123 &hp_output_mixer_controls[0],
1124 ARRAY_SIZE(hp_output_mixer_controls)),
1125 SND_SOC_DAPM_PGA("HP Power", AIC32X4_OUTPWRCTL, 5, 0, NULL, 0),
1126
1127 SND_SOC_DAPM_PGA("Speaker Driver", TAS2505_SPK, 1, 0, NULL, 0),
1128
1129 SND_SOC_DAPM_OUTPUT("HP"),
1130 SND_SOC_DAPM_OUTPUT("Speaker"),
1131};
1132
1133static const struct snd_soc_dapm_route aic32x4_tas2505_dapm_routes[] = {
1134 /* Left Output */
1135 {"HP Output Mixer", "DAC Switch", "DAC"},
1136
1137 {"HP Power", NULL, "HP Output Mixer"},
1138 {"HP", NULL, "HP Power"},
1139
1140 {"Speaker Driver", NULL, "DAC"},
1141 {"Speaker", NULL, "Speaker Driver"},
1142};
1143
1144static struct snd_soc_dai_driver aic32x4_tas2505_dai = {
1145 .name = "tas2505-hifi",
1146 .playback = {
1147 .stream_name = "Playback",
1148 .channels_min = 1,
1149 .channels_max = 2,
1150 .rates = SNDRV_PCM_RATE_8000_96000,
1151 .formats = AIC32X4_FORMATS,},
1152 .ops = &aic32x4_ops,
1153 .symmetric_rate = 1,
1154};
1155
1156static int aic32x4_tas2505_component_probe(struct snd_soc_component *component)
1157{
1158 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
1159 u32 tmp_reg;
1160 int ret;
1161
1162 static struct clk_bulk_data clocks[] = {
1163 { .id = "codec_clkin" },
1164 { .id = "pll" },
1165 { .id = "bdiv" },
1166 { .id = "mdac" },
1167 };
1168
1169 ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks);
1170 if (ret)
1171 return ret;
1172
1173 if (aic32x4->setup)
1174 aic32x4_setup_gpios(component);
1175
1176 clk_set_parent(clocks[0].clk, clocks[1].clk);
1177 clk_set_parent(clocks[2].clk, clocks[3].clk);
1178
1179 /* Power platform configuration */
1180 if (aic32x4->power_cfg & AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE)
1181 snd_soc_component_write(component, AIC32X4_PWRCFG, AIC32X4_AVDDWEAKDISABLE);
1182
1183 tmp_reg = (aic32x4->power_cfg & AIC32X4_PWR_AIC32X4_LDO_ENABLE) ?
1184 AIC32X4_LDOCTLEN : 0;
1185 snd_soc_component_write(component, AIC32X4_LDOCTL, tmp_reg);
1186
1187 tmp_reg = snd_soc_component_read(component, AIC32X4_CMMODE);
1188 if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36)
1189 tmp_reg |= AIC32X4_LDOIN_18_36;
1190 if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_HP_LDOIN_POWERED)
1191 tmp_reg |= AIC32X4_LDOIN2HP;
1192 snd_soc_component_write(component, AIC32X4_CMMODE, tmp_reg);
1193
1194 /*
1195 * Enable the fast charging feature and ensure the needed 40ms ellapsed
1196 * before using the analog circuits.
1197 */
1198 snd_soc_component_write(component, TAS2505_REFPOWERUP,
1199 AIC32X4_REFPOWERUP_40MS);
1200 msleep(40);
1201
1202 return 0;
1203}
1204
1205static const struct snd_soc_component_driver soc_component_dev_aic32x4_tas2505 = {
1206 .probe = aic32x4_tas2505_component_probe,
1207 .set_bias_level = aic32x4_set_bias_level,
1208 .controls = aic32x4_tas2505_snd_controls,
1209 .num_controls = ARRAY_SIZE(aic32x4_tas2505_snd_controls),
1210 .dapm_widgets = aic32x4_tas2505_dapm_widgets,
1211 .num_dapm_widgets = ARRAY_SIZE(aic32x4_tas2505_dapm_widgets),
1212 .dapm_routes = aic32x4_tas2505_dapm_routes,
1213 .num_dapm_routes = ARRAY_SIZE(aic32x4_tas2505_dapm_routes),
1214 .of_xlate_dai_id = aic32x4_of_xlate_dai_id,
1215 .suspend_bias_off = 1,
1216 .idle_bias_on = 1,
1217 .use_pmdown_time = 1,
1218 .endianness = 1,
1219};
1220
1221static int aic32x4_parse_dt(struct aic32x4_priv *aic32x4,
1222 struct device_node *np)
1223{
1224 struct aic32x4_setup_data *aic32x4_setup;
1225 int ret;
1226
1227 aic32x4_setup = devm_kzalloc(aic32x4->dev, sizeof(*aic32x4_setup),
1228 GFP_KERNEL);
1229 if (!aic32x4_setup)
1230 return -ENOMEM;
1231
1232 ret = of_property_match_string(np, "clock-names", "mclk");
1233 if (ret < 0)
1234 return -EINVAL;
1235 aic32x4->mclk_name = of_clk_get_parent_name(np, ret);
1236
1237 aic32x4->swapdacs = false;
1238 aic32x4->micpga_routing = 0;
1239 aic32x4->rstn_gpio = of_get_named_gpio(np, "reset-gpios", 0);
1240
1241 if (of_property_read_u32_array(np, "aic32x4-gpio-func",
1242 aic32x4_setup->gpio_func, 5) >= 0)
1243 aic32x4->setup = aic32x4_setup;
1244 return 0;
1245}
1246
1247static void aic32x4_disable_regulators(struct aic32x4_priv *aic32x4)
1248{
1249 regulator_disable(aic32x4->supply_iov);
1250
1251 if (!IS_ERR(aic32x4->supply_ldo))
1252 regulator_disable(aic32x4->supply_ldo);
1253
1254 if (!IS_ERR(aic32x4->supply_dv))
1255 regulator_disable(aic32x4->supply_dv);
1256
1257 if (!IS_ERR(aic32x4->supply_av))
1258 regulator_disable(aic32x4->supply_av);
1259}
1260
1261static int aic32x4_setup_regulators(struct device *dev,
1262 struct aic32x4_priv *aic32x4)
1263{
1264 int ret = 0;
1265
1266 aic32x4->supply_ldo = devm_regulator_get_optional(dev, "ldoin");
1267 aic32x4->supply_iov = devm_regulator_get(dev, "iov");
1268 aic32x4->supply_dv = devm_regulator_get_optional(dev, "dv");
1269 aic32x4->supply_av = devm_regulator_get_optional(dev, "av");
1270
1271 /* Check if the regulator requirements are fulfilled */
1272
1273 if (IS_ERR(aic32x4->supply_iov)) {
1274 dev_err(dev, "Missing supply 'iov'\n");
1275 return PTR_ERR(aic32x4->supply_iov);
1276 }
1277
1278 if (IS_ERR(aic32x4->supply_ldo)) {
1279 if (PTR_ERR(aic32x4->supply_ldo) == -EPROBE_DEFER)
1280 return -EPROBE_DEFER;
1281
1282 if (IS_ERR(aic32x4->supply_dv)) {
1283 dev_err(dev, "Missing supply 'dv' or 'ldoin'\n");
1284 return PTR_ERR(aic32x4->supply_dv);
1285 }
1286 if (IS_ERR(aic32x4->supply_av)) {
1287 dev_err(dev, "Missing supply 'av' or 'ldoin'\n");
1288 return PTR_ERR(aic32x4->supply_av);
1289 }
1290 } else {
1291 if (PTR_ERR(aic32x4->supply_dv) == -EPROBE_DEFER)
1292 return -EPROBE_DEFER;
1293 if (PTR_ERR(aic32x4->supply_av) == -EPROBE_DEFER)
1294 return -EPROBE_DEFER;
1295 }
1296
1297 ret = regulator_enable(aic32x4->supply_iov);
1298 if (ret) {
1299 dev_err(dev, "Failed to enable regulator iov\n");
1300 return ret;
1301 }
1302
1303 if (!IS_ERR(aic32x4->supply_ldo)) {
1304 ret = regulator_enable(aic32x4->supply_ldo);
1305 if (ret) {
1306 dev_err(dev, "Failed to enable regulator ldo\n");
1307 goto error_ldo;
1308 }
1309 }
1310
1311 if (!IS_ERR(aic32x4->supply_dv)) {
1312 ret = regulator_enable(aic32x4->supply_dv);
1313 if (ret) {
1314 dev_err(dev, "Failed to enable regulator dv\n");
1315 goto error_dv;
1316 }
1317 }
1318
1319 if (!IS_ERR(aic32x4->supply_av)) {
1320 ret = regulator_enable(aic32x4->supply_av);
1321 if (ret) {
1322 dev_err(dev, "Failed to enable regulator av\n");
1323 goto error_av;
1324 }
1325 }
1326
1327 if (!IS_ERR(aic32x4->supply_ldo) && IS_ERR(aic32x4->supply_av))
1328 aic32x4->power_cfg |= AIC32X4_PWR_AIC32X4_LDO_ENABLE;
1329
1330 return 0;
1331
1332error_av:
1333 if (!IS_ERR(aic32x4->supply_dv))
1334 regulator_disable(aic32x4->supply_dv);
1335
1336error_dv:
1337 if (!IS_ERR(aic32x4->supply_ldo))
1338 regulator_disable(aic32x4->supply_ldo);
1339
1340error_ldo:
1341 regulator_disable(aic32x4->supply_iov);
1342 return ret;
1343}
1344
1345int aic32x4_probe(struct device *dev, struct regmap *regmap,
1346 enum aic32x4_type type)
1347{
1348 struct aic32x4_priv *aic32x4;
1349 struct aic32x4_pdata *pdata = dev->platform_data;
1350 struct device_node *np = dev->of_node;
1351 int ret;
1352
1353 if (IS_ERR(regmap))
1354 return PTR_ERR(regmap);
1355
1356 aic32x4 = devm_kzalloc(dev, sizeof(struct aic32x4_priv),
1357 GFP_KERNEL);
1358 if (aic32x4 == NULL)
1359 return -ENOMEM;
1360
1361 aic32x4->dev = dev;
1362 aic32x4->type = type;
1363
1364 dev_set_drvdata(dev, aic32x4);
1365
1366 if (pdata) {
1367 aic32x4->power_cfg = pdata->power_cfg;
1368 aic32x4->swapdacs = pdata->swapdacs;
1369 aic32x4->micpga_routing = pdata->micpga_routing;
1370 aic32x4->rstn_gpio = pdata->rstn_gpio;
1371 aic32x4->mclk_name = "mclk";
1372 } else if (np) {
1373 ret = aic32x4_parse_dt(aic32x4, np);
1374 if (ret) {
1375 dev_err(dev, "Failed to parse DT node\n");
1376 return ret;
1377 }
1378 } else {
1379 aic32x4->power_cfg = 0;
1380 aic32x4->swapdacs = false;
1381 aic32x4->micpga_routing = 0;
1382 aic32x4->rstn_gpio = -1;
1383 aic32x4->mclk_name = "mclk";
1384 }
1385
1386 if (gpio_is_valid(aic32x4->rstn_gpio)) {
1387 ret = devm_gpio_request_one(dev, aic32x4->rstn_gpio,
1388 GPIOF_OUT_INIT_LOW, "tlv320aic32x4 rstn");
1389 if (ret != 0)
1390 return ret;
1391 }
1392
1393 ret = aic32x4_setup_regulators(dev, aic32x4);
1394 if (ret) {
1395 dev_err(dev, "Failed to setup regulators\n");
1396 return ret;
1397 }
1398
1399 if (gpio_is_valid(aic32x4->rstn_gpio)) {
1400 ndelay(10);
1401 gpio_set_value_cansleep(aic32x4->rstn_gpio, 1);
1402 mdelay(1);
1403 }
1404
1405 ret = regmap_write(regmap, AIC32X4_RESET, 0x01);
1406 if (ret)
1407 goto err_disable_regulators;
1408
1409 ret = aic32x4_register_clocks(dev, aic32x4->mclk_name);
1410 if (ret)
1411 goto err_disable_regulators;
1412
1413 switch (aic32x4->type) {
1414 case AIC32X4_TYPE_TAS2505:
1415 ret = devm_snd_soc_register_component(dev,
1416 &soc_component_dev_aic32x4_tas2505, &aic32x4_tas2505_dai, 1);
1417 break;
1418 default:
1419 ret = devm_snd_soc_register_component(dev,
1420 &soc_component_dev_aic32x4, &aic32x4_dai, 1);
1421 }
1422
1423 if (ret) {
1424 dev_err(dev, "Failed to register component\n");
1425 goto err_disable_regulators;
1426 }
1427
1428 return 0;
1429
1430err_disable_regulators:
1431 aic32x4_disable_regulators(aic32x4);
1432
1433 return ret;
1434}
1435EXPORT_SYMBOL(aic32x4_probe);
1436
1437void aic32x4_remove(struct device *dev)
1438{
1439 struct aic32x4_priv *aic32x4 = dev_get_drvdata(dev);
1440
1441 aic32x4_disable_regulators(aic32x4);
1442}
1443EXPORT_SYMBOL(aic32x4_remove);
1444
1445MODULE_DESCRIPTION("ASoC tlv320aic32x4 codec driver");
1446MODULE_AUTHOR("Javier Martin <javier.martin@vista-silicon.com>");
1447MODULE_LICENSE("GPL");
1/*
2 * linux/sound/soc/codecs/tlv320aic32x4.c
3 *
4 * Copyright 2011 Vista Silicon S.L.
5 *
6 * Author: Javier Martin <javier.martin@vista-silicon.com>
7 *
8 * Based on sound/soc/codecs/wm8974 and TI driver for kernel 2.6.27.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
23 * MA 02110-1301, USA.
24 */
25
26#include <linux/module.h>
27#include <linux/moduleparam.h>
28#include <linux/init.h>
29#include <linux/delay.h>
30#include <linux/pm.h>
31#include <linux/i2c.h>
32#include <linux/cdev.h>
33#include <linux/slab.h>
34
35#include <sound/tlv320aic32x4.h>
36#include <sound/core.h>
37#include <sound/pcm.h>
38#include <sound/pcm_params.h>
39#include <sound/soc.h>
40#include <sound/soc-dapm.h>
41#include <sound/initval.h>
42#include <sound/tlv.h>
43
44#include "tlv320aic32x4.h"
45
46struct aic32x4_rate_divs {
47 u32 mclk;
48 u32 rate;
49 u8 p_val;
50 u8 pll_j;
51 u16 pll_d;
52 u16 dosr;
53 u8 ndac;
54 u8 mdac;
55 u8 aosr;
56 u8 nadc;
57 u8 madc;
58 u8 blck_N;
59};
60
61struct aic32x4_priv {
62 u32 sysclk;
63 u8 page_no;
64 void *control_data;
65 u32 power_cfg;
66 u32 micpga_routing;
67 bool swapdacs;
68};
69
70/* 0dB min, 1dB steps */
71static DECLARE_TLV_DB_SCALE(tlv_step_1, 0, 100, 0);
72/* 0dB min, 0.5dB steps */
73static DECLARE_TLV_DB_SCALE(tlv_step_0_5, 0, 50, 0);
74
75static const struct snd_kcontrol_new aic32x4_snd_controls[] = {
76 SOC_DOUBLE_R_TLV("PCM Playback Volume", AIC32X4_LDACVOL,
77 AIC32X4_RDACVOL, 0, 0x30, 0, tlv_step_0_5),
78 SOC_DOUBLE_R_TLV("HP Driver Gain Volume", AIC32X4_HPLGAIN,
79 AIC32X4_HPRGAIN, 0, 0x1D, 0, tlv_step_1),
80 SOC_DOUBLE_R_TLV("LO Driver Gain Volume", AIC32X4_LOLGAIN,
81 AIC32X4_LORGAIN, 0, 0x1D, 0, tlv_step_1),
82 SOC_DOUBLE_R("HP DAC Playback Switch", AIC32X4_HPLGAIN,
83 AIC32X4_HPRGAIN, 6, 0x01, 1),
84 SOC_DOUBLE_R("LO DAC Playback Switch", AIC32X4_LOLGAIN,
85 AIC32X4_LORGAIN, 6, 0x01, 1),
86 SOC_DOUBLE_R("Mic PGA Switch", AIC32X4_LMICPGAVOL,
87 AIC32X4_RMICPGAVOL, 7, 0x01, 1),
88
89 SOC_SINGLE("ADCFGA Left Mute Switch", AIC32X4_ADCFGA, 7, 1, 0),
90 SOC_SINGLE("ADCFGA Right Mute Switch", AIC32X4_ADCFGA, 3, 1, 0),
91
92 SOC_DOUBLE_R_TLV("ADC Level Volume", AIC32X4_LADCVOL,
93 AIC32X4_RADCVOL, 0, 0x28, 0, tlv_step_0_5),
94 SOC_DOUBLE_R_TLV("PGA Level Volume", AIC32X4_LMICPGAVOL,
95 AIC32X4_RMICPGAVOL, 0, 0x5f, 0, tlv_step_0_5),
96
97 SOC_SINGLE("Auto-mute Switch", AIC32X4_DACMUTE, 4, 7, 0),
98
99 SOC_SINGLE("AGC Left Switch", AIC32X4_LAGC1, 7, 1, 0),
100 SOC_SINGLE("AGC Right Switch", AIC32X4_RAGC1, 7, 1, 0),
101 SOC_DOUBLE_R("AGC Target Level", AIC32X4_LAGC1, AIC32X4_RAGC1,
102 4, 0x07, 0),
103 SOC_DOUBLE_R("AGC Gain Hysteresis", AIC32X4_LAGC1, AIC32X4_RAGC1,
104 0, 0x03, 0),
105 SOC_DOUBLE_R("AGC Hysteresis", AIC32X4_LAGC2, AIC32X4_RAGC2,
106 6, 0x03, 0),
107 SOC_DOUBLE_R("AGC Noise Threshold", AIC32X4_LAGC2, AIC32X4_RAGC2,
108 1, 0x1F, 0),
109 SOC_DOUBLE_R("AGC Max PGA", AIC32X4_LAGC3, AIC32X4_RAGC3,
110 0, 0x7F, 0),
111 SOC_DOUBLE_R("AGC Attack Time", AIC32X4_LAGC4, AIC32X4_RAGC4,
112 3, 0x1F, 0),
113 SOC_DOUBLE_R("AGC Decay Time", AIC32X4_LAGC5, AIC32X4_RAGC5,
114 3, 0x1F, 0),
115 SOC_DOUBLE_R("AGC Noise Debounce", AIC32X4_LAGC6, AIC32X4_RAGC6,
116 0, 0x1F, 0),
117 SOC_DOUBLE_R("AGC Signal Debounce", AIC32X4_LAGC7, AIC32X4_RAGC7,
118 0, 0x0F, 0),
119};
120
121static const struct aic32x4_rate_divs aic32x4_divs[] = {
122 /* 8k rate */
123 {AIC32X4_FREQ_12000000, 8000, 1, 7, 6800, 768, 5, 3, 128, 5, 18, 24},
124 {AIC32X4_FREQ_24000000, 8000, 2, 7, 6800, 768, 15, 1, 64, 45, 4, 24},
125 {AIC32X4_FREQ_25000000, 8000, 2, 7, 3728, 768, 15, 1, 64, 45, 4, 24},
126 /* 11.025k rate */
127 {AIC32X4_FREQ_12000000, 11025, 1, 7, 5264, 512, 8, 2, 128, 8, 8, 16},
128 {AIC32X4_FREQ_24000000, 11025, 2, 7, 5264, 512, 16, 1, 64, 32, 4, 16},
129 /* 16k rate */
130 {AIC32X4_FREQ_12000000, 16000, 1, 7, 6800, 384, 5, 3, 128, 5, 9, 12},
131 {AIC32X4_FREQ_24000000, 16000, 2, 7, 6800, 384, 15, 1, 64, 18, 5, 12},
132 {AIC32X4_FREQ_25000000, 16000, 2, 7, 3728, 384, 15, 1, 64, 18, 5, 12},
133 /* 22.05k rate */
134 {AIC32X4_FREQ_12000000, 22050, 1, 7, 5264, 256, 4, 4, 128, 4, 8, 8},
135 {AIC32X4_FREQ_24000000, 22050, 2, 7, 5264, 256, 16, 1, 64, 16, 4, 8},
136 {AIC32X4_FREQ_25000000, 22050, 2, 7, 2253, 256, 16, 1, 64, 16, 4, 8},
137 /* 32k rate */
138 {AIC32X4_FREQ_12000000, 32000, 1, 7, 1680, 192, 2, 7, 64, 2, 21, 6},
139 {AIC32X4_FREQ_24000000, 32000, 2, 7, 1680, 192, 7, 2, 64, 7, 6, 6},
140 /* 44.1k rate */
141 {AIC32X4_FREQ_12000000, 44100, 1, 7, 5264, 128, 2, 8, 128, 2, 8, 4},
142 {AIC32X4_FREQ_24000000, 44100, 2, 7, 5264, 128, 8, 2, 64, 8, 4, 4},
143 {AIC32X4_FREQ_25000000, 44100, 2, 7, 2253, 128, 8, 2, 64, 8, 4, 4},
144 /* 48k rate */
145 {AIC32X4_FREQ_12000000, 48000, 1, 8, 1920, 128, 2, 8, 128, 2, 8, 4},
146 {AIC32X4_FREQ_24000000, 48000, 2, 8, 1920, 128, 8, 2, 64, 8, 4, 4},
147 {AIC32X4_FREQ_25000000, 48000, 2, 7, 8643, 128, 8, 2, 64, 8, 4, 4}
148};
149
150static const struct snd_kcontrol_new hpl_output_mixer_controls[] = {
151 SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_HPLROUTE, 3, 1, 0),
152 SOC_DAPM_SINGLE("IN1_L Switch", AIC32X4_HPLROUTE, 2, 1, 0),
153};
154
155static const struct snd_kcontrol_new hpr_output_mixer_controls[] = {
156 SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_HPRROUTE, 3, 1, 0),
157 SOC_DAPM_SINGLE("IN1_R Switch", AIC32X4_HPRROUTE, 2, 1, 0),
158};
159
160static const struct snd_kcontrol_new lol_output_mixer_controls[] = {
161 SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_LOLROUTE, 3, 1, 0),
162};
163
164static const struct snd_kcontrol_new lor_output_mixer_controls[] = {
165 SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_LORROUTE, 3, 1, 0),
166};
167
168static const struct snd_kcontrol_new left_input_mixer_controls[] = {
169 SOC_DAPM_SINGLE("IN1_L P Switch", AIC32X4_LMICPGAPIN, 6, 1, 0),
170 SOC_DAPM_SINGLE("IN2_L P Switch", AIC32X4_LMICPGAPIN, 4, 1, 0),
171 SOC_DAPM_SINGLE("IN3_L P Switch", AIC32X4_LMICPGAPIN, 2, 1, 0),
172};
173
174static const struct snd_kcontrol_new right_input_mixer_controls[] = {
175 SOC_DAPM_SINGLE("IN1_R P Switch", AIC32X4_RMICPGAPIN, 6, 1, 0),
176 SOC_DAPM_SINGLE("IN2_R P Switch", AIC32X4_RMICPGAPIN, 4, 1, 0),
177 SOC_DAPM_SINGLE("IN3_R P Switch", AIC32X4_RMICPGAPIN, 2, 1, 0),
178};
179
180static const struct snd_soc_dapm_widget aic32x4_dapm_widgets[] = {
181 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", AIC32X4_DACSETUP, 7, 0),
182 SND_SOC_DAPM_MIXER("HPL Output Mixer", SND_SOC_NOPM, 0, 0,
183 &hpl_output_mixer_controls[0],
184 ARRAY_SIZE(hpl_output_mixer_controls)),
185 SND_SOC_DAPM_PGA("HPL Power", AIC32X4_OUTPWRCTL, 5, 0, NULL, 0),
186
187 SND_SOC_DAPM_MIXER("LOL Output Mixer", SND_SOC_NOPM, 0, 0,
188 &lol_output_mixer_controls[0],
189 ARRAY_SIZE(lol_output_mixer_controls)),
190 SND_SOC_DAPM_PGA("LOL Power", AIC32X4_OUTPWRCTL, 3, 0, NULL, 0),
191
192 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", AIC32X4_DACSETUP, 6, 0),
193 SND_SOC_DAPM_MIXER("HPR Output Mixer", SND_SOC_NOPM, 0, 0,
194 &hpr_output_mixer_controls[0],
195 ARRAY_SIZE(hpr_output_mixer_controls)),
196 SND_SOC_DAPM_PGA("HPR Power", AIC32X4_OUTPWRCTL, 4, 0, NULL, 0),
197 SND_SOC_DAPM_MIXER("LOR Output Mixer", SND_SOC_NOPM, 0, 0,
198 &lor_output_mixer_controls[0],
199 ARRAY_SIZE(lor_output_mixer_controls)),
200 SND_SOC_DAPM_PGA("LOR Power", AIC32X4_OUTPWRCTL, 2, 0, NULL, 0),
201 SND_SOC_DAPM_MIXER("Left Input Mixer", SND_SOC_NOPM, 0, 0,
202 &left_input_mixer_controls[0],
203 ARRAY_SIZE(left_input_mixer_controls)),
204 SND_SOC_DAPM_MIXER("Right Input Mixer", SND_SOC_NOPM, 0, 0,
205 &right_input_mixer_controls[0],
206 ARRAY_SIZE(right_input_mixer_controls)),
207 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", AIC32X4_ADCSETUP, 7, 0),
208 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", AIC32X4_ADCSETUP, 6, 0),
209 SND_SOC_DAPM_MICBIAS("Mic Bias", AIC32X4_MICBIAS, 6, 0),
210
211 SND_SOC_DAPM_OUTPUT("HPL"),
212 SND_SOC_DAPM_OUTPUT("HPR"),
213 SND_SOC_DAPM_OUTPUT("LOL"),
214 SND_SOC_DAPM_OUTPUT("LOR"),
215 SND_SOC_DAPM_INPUT("IN1_L"),
216 SND_SOC_DAPM_INPUT("IN1_R"),
217 SND_SOC_DAPM_INPUT("IN2_L"),
218 SND_SOC_DAPM_INPUT("IN2_R"),
219 SND_SOC_DAPM_INPUT("IN3_L"),
220 SND_SOC_DAPM_INPUT("IN3_R"),
221};
222
223static const struct snd_soc_dapm_route aic32x4_dapm_routes[] = {
224 /* Left Output */
225 {"HPL Output Mixer", "L_DAC Switch", "Left DAC"},
226 {"HPL Output Mixer", "IN1_L Switch", "IN1_L"},
227
228 {"HPL Power", NULL, "HPL Output Mixer"},
229 {"HPL", NULL, "HPL Power"},
230
231 {"LOL Output Mixer", "L_DAC Switch", "Left DAC"},
232
233 {"LOL Power", NULL, "LOL Output Mixer"},
234 {"LOL", NULL, "LOL Power"},
235
236 /* Right Output */
237 {"HPR Output Mixer", "R_DAC Switch", "Right DAC"},
238 {"HPR Output Mixer", "IN1_R Switch", "IN1_R"},
239
240 {"HPR Power", NULL, "HPR Output Mixer"},
241 {"HPR", NULL, "HPR Power"},
242
243 {"LOR Output Mixer", "R_DAC Switch", "Right DAC"},
244
245 {"LOR Power", NULL, "LOR Output Mixer"},
246 {"LOR", NULL, "LOR Power"},
247
248 /* Left input */
249 {"Left Input Mixer", "IN1_L P Switch", "IN1_L"},
250 {"Left Input Mixer", "IN2_L P Switch", "IN2_L"},
251 {"Left Input Mixer", "IN3_L P Switch", "IN3_L"},
252
253 {"Left ADC", NULL, "Left Input Mixer"},
254
255 /* Right Input */
256 {"Right Input Mixer", "IN1_R P Switch", "IN1_R"},
257 {"Right Input Mixer", "IN2_R P Switch", "IN2_R"},
258 {"Right Input Mixer", "IN3_R P Switch", "IN3_R"},
259
260 {"Right ADC", NULL, "Right Input Mixer"},
261};
262
263static inline int aic32x4_change_page(struct snd_soc_codec *codec,
264 unsigned int new_page)
265{
266 struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
267 u8 data[2];
268 int ret;
269
270 data[0] = 0x00;
271 data[1] = new_page & 0xff;
272
273 ret = codec->hw_write(codec->control_data, data, 2);
274 if (ret == 2) {
275 aic32x4->page_no = new_page;
276 return 0;
277 } else {
278 return ret;
279 }
280}
281
282static int aic32x4_write(struct snd_soc_codec *codec, unsigned int reg,
283 unsigned int val)
284{
285 struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
286 unsigned int page = reg / 128;
287 unsigned int fixed_reg = reg % 128;
288 u8 data[2];
289 int ret;
290
291 /* A write to AIC32X4_PSEL is really a non-explicit page change */
292 if (reg == AIC32X4_PSEL)
293 return aic32x4_change_page(codec, val);
294
295 if (aic32x4->page_no != page) {
296 ret = aic32x4_change_page(codec, page);
297 if (ret != 0)
298 return ret;
299 }
300
301 data[0] = fixed_reg & 0xff;
302 data[1] = val & 0xff;
303
304 if (codec->hw_write(codec->control_data, data, 2) == 2)
305 return 0;
306 else
307 return -EIO;
308}
309
310static unsigned int aic32x4_read(struct snd_soc_codec *codec, unsigned int reg)
311{
312 struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
313 unsigned int page = reg / 128;
314 unsigned int fixed_reg = reg % 128;
315 int ret;
316
317 if (aic32x4->page_no != page) {
318 ret = aic32x4_change_page(codec, page);
319 if (ret != 0)
320 return ret;
321 }
322 return i2c_smbus_read_byte_data(codec->control_data, fixed_reg & 0xff);
323}
324
325static inline int aic32x4_get_divs(int mclk, int rate)
326{
327 int i;
328
329 for (i = 0; i < ARRAY_SIZE(aic32x4_divs); i++) {
330 if ((aic32x4_divs[i].rate == rate)
331 && (aic32x4_divs[i].mclk == mclk)) {
332 return i;
333 }
334 }
335 printk(KERN_ERR "aic32x4: master clock and sample rate is not supported\n");
336 return -EINVAL;
337}
338
339static int aic32x4_add_widgets(struct snd_soc_codec *codec)
340{
341 snd_soc_dapm_new_controls(&codec->dapm, aic32x4_dapm_widgets,
342 ARRAY_SIZE(aic32x4_dapm_widgets));
343
344 snd_soc_dapm_add_routes(&codec->dapm, aic32x4_dapm_routes,
345 ARRAY_SIZE(aic32x4_dapm_routes));
346
347 snd_soc_dapm_new_widgets(&codec->dapm);
348 return 0;
349}
350
351static int aic32x4_set_dai_sysclk(struct snd_soc_dai *codec_dai,
352 int clk_id, unsigned int freq, int dir)
353{
354 struct snd_soc_codec *codec = codec_dai->codec;
355 struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
356
357 switch (freq) {
358 case AIC32X4_FREQ_12000000:
359 case AIC32X4_FREQ_24000000:
360 case AIC32X4_FREQ_25000000:
361 aic32x4->sysclk = freq;
362 return 0;
363 }
364 printk(KERN_ERR "aic32x4: invalid frequency to set DAI system clock\n");
365 return -EINVAL;
366}
367
368static int aic32x4_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
369{
370 struct snd_soc_codec *codec = codec_dai->codec;
371 u8 iface_reg_1;
372 u8 iface_reg_2;
373 u8 iface_reg_3;
374
375 iface_reg_1 = snd_soc_read(codec, AIC32X4_IFACE1);
376 iface_reg_1 = iface_reg_1 & ~(3 << 6 | 3 << 2);
377 iface_reg_2 = snd_soc_read(codec, AIC32X4_IFACE2);
378 iface_reg_2 = 0;
379 iface_reg_3 = snd_soc_read(codec, AIC32X4_IFACE3);
380 iface_reg_3 = iface_reg_3 & ~(1 << 3);
381
382 /* set master/slave audio interface */
383 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
384 case SND_SOC_DAIFMT_CBM_CFM:
385 iface_reg_1 |= AIC32X4_BCLKMASTER | AIC32X4_WCLKMASTER;
386 break;
387 case SND_SOC_DAIFMT_CBS_CFS:
388 break;
389 default:
390 printk(KERN_ERR "aic32x4: invalid DAI master/slave interface\n");
391 return -EINVAL;
392 }
393
394 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
395 case SND_SOC_DAIFMT_I2S:
396 break;
397 case SND_SOC_DAIFMT_DSP_A:
398 iface_reg_1 |= (AIC32X4_DSP_MODE << AIC32X4_PLLJ_SHIFT);
399 iface_reg_3 |= (1 << 3); /* invert bit clock */
400 iface_reg_2 = 0x01; /* add offset 1 */
401 break;
402 case SND_SOC_DAIFMT_DSP_B:
403 iface_reg_1 |= (AIC32X4_DSP_MODE << AIC32X4_PLLJ_SHIFT);
404 iface_reg_3 |= (1 << 3); /* invert bit clock */
405 break;
406 case SND_SOC_DAIFMT_RIGHT_J:
407 iface_reg_1 |=
408 (AIC32X4_RIGHT_JUSTIFIED_MODE << AIC32X4_PLLJ_SHIFT);
409 break;
410 case SND_SOC_DAIFMT_LEFT_J:
411 iface_reg_1 |=
412 (AIC32X4_LEFT_JUSTIFIED_MODE << AIC32X4_PLLJ_SHIFT);
413 break;
414 default:
415 printk(KERN_ERR "aic32x4: invalid DAI interface format\n");
416 return -EINVAL;
417 }
418
419 snd_soc_write(codec, AIC32X4_IFACE1, iface_reg_1);
420 snd_soc_write(codec, AIC32X4_IFACE2, iface_reg_2);
421 snd_soc_write(codec, AIC32X4_IFACE3, iface_reg_3);
422 return 0;
423}
424
425static int aic32x4_hw_params(struct snd_pcm_substream *substream,
426 struct snd_pcm_hw_params *params,
427 struct snd_soc_dai *dai)
428{
429 struct snd_soc_codec *codec = dai->codec;
430 struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
431 u8 data;
432 int i;
433
434 i = aic32x4_get_divs(aic32x4->sysclk, params_rate(params));
435 if (i < 0) {
436 printk(KERN_ERR "aic32x4: sampling rate not supported\n");
437 return i;
438 }
439
440 /* Use PLL as CODEC_CLKIN and DAC_MOD_CLK as BDIV_CLKIN */
441 snd_soc_write(codec, AIC32X4_CLKMUX, AIC32X4_PLLCLKIN);
442 snd_soc_write(codec, AIC32X4_IFACE3, AIC32X4_DACMOD2BCLK);
443
444 /* We will fix R value to 1 and will make P & J=K.D as varialble */
445 data = snd_soc_read(codec, AIC32X4_PLLPR);
446 data &= ~(7 << 4);
447 snd_soc_write(codec, AIC32X4_PLLPR,
448 (data | (aic32x4_divs[i].p_val << 4) | 0x01));
449
450 snd_soc_write(codec, AIC32X4_PLLJ, aic32x4_divs[i].pll_j);
451
452 snd_soc_write(codec, AIC32X4_PLLDMSB, (aic32x4_divs[i].pll_d >> 8));
453 snd_soc_write(codec, AIC32X4_PLLDLSB,
454 (aic32x4_divs[i].pll_d & 0xff));
455
456 /* NDAC divider value */
457 data = snd_soc_read(codec, AIC32X4_NDAC);
458 data &= ~(0x7f);
459 snd_soc_write(codec, AIC32X4_NDAC, data | aic32x4_divs[i].ndac);
460
461 /* MDAC divider value */
462 data = snd_soc_read(codec, AIC32X4_MDAC);
463 data &= ~(0x7f);
464 snd_soc_write(codec, AIC32X4_MDAC, data | aic32x4_divs[i].mdac);
465
466 /* DOSR MSB & LSB values */
467 snd_soc_write(codec, AIC32X4_DOSRMSB, aic32x4_divs[i].dosr >> 8);
468 snd_soc_write(codec, AIC32X4_DOSRLSB,
469 (aic32x4_divs[i].dosr & 0xff));
470
471 /* NADC divider value */
472 data = snd_soc_read(codec, AIC32X4_NADC);
473 data &= ~(0x7f);
474 snd_soc_write(codec, AIC32X4_NADC, data | aic32x4_divs[i].nadc);
475
476 /* MADC divider value */
477 data = snd_soc_read(codec, AIC32X4_MADC);
478 data &= ~(0x7f);
479 snd_soc_write(codec, AIC32X4_MADC, data | aic32x4_divs[i].madc);
480
481 /* AOSR value */
482 snd_soc_write(codec, AIC32X4_AOSR, aic32x4_divs[i].aosr);
483
484 /* BCLK N divider */
485 data = snd_soc_read(codec, AIC32X4_BCLKN);
486 data &= ~(0x7f);
487 snd_soc_write(codec, AIC32X4_BCLKN, data | aic32x4_divs[i].blck_N);
488
489 data = snd_soc_read(codec, AIC32X4_IFACE1);
490 data = data & ~(3 << 4);
491 switch (params_format(params)) {
492 case SNDRV_PCM_FORMAT_S16_LE:
493 break;
494 case SNDRV_PCM_FORMAT_S20_3LE:
495 data |= (AIC32X4_WORD_LEN_20BITS << AIC32X4_DOSRMSB_SHIFT);
496 break;
497 case SNDRV_PCM_FORMAT_S24_LE:
498 data |= (AIC32X4_WORD_LEN_24BITS << AIC32X4_DOSRMSB_SHIFT);
499 break;
500 case SNDRV_PCM_FORMAT_S32_LE:
501 data |= (AIC32X4_WORD_LEN_32BITS << AIC32X4_DOSRMSB_SHIFT);
502 break;
503 }
504 snd_soc_write(codec, AIC32X4_IFACE1, data);
505
506 return 0;
507}
508
509static int aic32x4_mute(struct snd_soc_dai *dai, int mute)
510{
511 struct snd_soc_codec *codec = dai->codec;
512 u8 dac_reg;
513
514 dac_reg = snd_soc_read(codec, AIC32X4_DACMUTE) & ~AIC32X4_MUTEON;
515 if (mute)
516 snd_soc_write(codec, AIC32X4_DACMUTE, dac_reg | AIC32X4_MUTEON);
517 else
518 snd_soc_write(codec, AIC32X4_DACMUTE, dac_reg);
519 return 0;
520}
521
522static int aic32x4_set_bias_level(struct snd_soc_codec *codec,
523 enum snd_soc_bias_level level)
524{
525 switch (level) {
526 case SND_SOC_BIAS_ON:
527 /* Switch on PLL */
528 snd_soc_update_bits(codec, AIC32X4_PLLPR,
529 AIC32X4_PLLEN, AIC32X4_PLLEN);
530
531 /* Switch on NDAC Divider */
532 snd_soc_update_bits(codec, AIC32X4_NDAC,
533 AIC32X4_NDACEN, AIC32X4_NDACEN);
534
535 /* Switch on MDAC Divider */
536 snd_soc_update_bits(codec, AIC32X4_MDAC,
537 AIC32X4_MDACEN, AIC32X4_MDACEN);
538
539 /* Switch on NADC Divider */
540 snd_soc_update_bits(codec, AIC32X4_NADC,
541 AIC32X4_NADCEN, AIC32X4_NADCEN);
542
543 /* Switch on MADC Divider */
544 snd_soc_update_bits(codec, AIC32X4_MADC,
545 AIC32X4_MADCEN, AIC32X4_MADCEN);
546
547 /* Switch on BCLK_N Divider */
548 snd_soc_update_bits(codec, AIC32X4_BCLKN,
549 AIC32X4_BCLKEN, AIC32X4_BCLKEN);
550 break;
551 case SND_SOC_BIAS_PREPARE:
552 break;
553 case SND_SOC_BIAS_STANDBY:
554 /* Switch off PLL */
555 snd_soc_update_bits(codec, AIC32X4_PLLPR,
556 AIC32X4_PLLEN, 0);
557
558 /* Switch off NDAC Divider */
559 snd_soc_update_bits(codec, AIC32X4_NDAC,
560 AIC32X4_NDACEN, 0);
561
562 /* Switch off MDAC Divider */
563 snd_soc_update_bits(codec, AIC32X4_MDAC,
564 AIC32X4_MDACEN, 0);
565
566 /* Switch off NADC Divider */
567 snd_soc_update_bits(codec, AIC32X4_NADC,
568 AIC32X4_NADCEN, 0);
569
570 /* Switch off MADC Divider */
571 snd_soc_update_bits(codec, AIC32X4_MADC,
572 AIC32X4_MADCEN, 0);
573
574 /* Switch off BCLK_N Divider */
575 snd_soc_update_bits(codec, AIC32X4_BCLKN,
576 AIC32X4_BCLKEN, 0);
577 break;
578 case SND_SOC_BIAS_OFF:
579 break;
580 }
581 codec->dapm.bias_level = level;
582 return 0;
583}
584
585#define AIC32X4_RATES SNDRV_PCM_RATE_8000_48000
586#define AIC32X4_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
587 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
588
589static const struct snd_soc_dai_ops aic32x4_ops = {
590 .hw_params = aic32x4_hw_params,
591 .digital_mute = aic32x4_mute,
592 .set_fmt = aic32x4_set_dai_fmt,
593 .set_sysclk = aic32x4_set_dai_sysclk,
594};
595
596static struct snd_soc_dai_driver aic32x4_dai = {
597 .name = "tlv320aic32x4-hifi",
598 .playback = {
599 .stream_name = "Playback",
600 .channels_min = 1,
601 .channels_max = 2,
602 .rates = AIC32X4_RATES,
603 .formats = AIC32X4_FORMATS,},
604 .capture = {
605 .stream_name = "Capture",
606 .channels_min = 1,
607 .channels_max = 2,
608 .rates = AIC32X4_RATES,
609 .formats = AIC32X4_FORMATS,},
610 .ops = &aic32x4_ops,
611 .symmetric_rates = 1,
612};
613
614static int aic32x4_suspend(struct snd_soc_codec *codec)
615{
616 aic32x4_set_bias_level(codec, SND_SOC_BIAS_OFF);
617 return 0;
618}
619
620static int aic32x4_resume(struct snd_soc_codec *codec)
621{
622 aic32x4_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
623 return 0;
624}
625
626static int aic32x4_probe(struct snd_soc_codec *codec)
627{
628 struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
629 u32 tmp_reg;
630
631 codec->hw_write = (hw_write_t) i2c_master_send;
632 codec->control_data = aic32x4->control_data;
633
634 snd_soc_write(codec, AIC32X4_RESET, 0x01);
635
636 /* Power platform configuration */
637 if (aic32x4->power_cfg & AIC32X4_PWR_MICBIAS_2075_LDOIN) {
638 snd_soc_write(codec, AIC32X4_MICBIAS, AIC32X4_MICBIAS_LDOIN |
639 AIC32X4_MICBIAS_2075V);
640 }
641 if (aic32x4->power_cfg & AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE) {
642 snd_soc_write(codec, AIC32X4_PWRCFG, AIC32X4_AVDDWEAKDISABLE);
643 }
644
645 tmp_reg = (aic32x4->power_cfg & AIC32X4_PWR_AIC32X4_LDO_ENABLE) ?
646 AIC32X4_LDOCTLEN : 0;
647 snd_soc_write(codec, AIC32X4_LDOCTL, tmp_reg);
648
649 tmp_reg = snd_soc_read(codec, AIC32X4_CMMODE);
650 if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36) {
651 tmp_reg |= AIC32X4_LDOIN_18_36;
652 }
653 if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_HP_LDOIN_POWERED) {
654 tmp_reg |= AIC32X4_LDOIN2HP;
655 }
656 snd_soc_write(codec, AIC32X4_CMMODE, tmp_reg);
657
658 /* Do DACs need to be swapped? */
659 if (aic32x4->swapdacs) {
660 snd_soc_write(codec, AIC32X4_DACSETUP, AIC32X4_LDAC2RCHN | AIC32X4_RDAC2LCHN);
661 } else {
662 snd_soc_write(codec, AIC32X4_DACSETUP, AIC32X4_LDAC2LCHN | AIC32X4_RDAC2RCHN);
663 }
664
665 /* Mic PGA routing */
666 if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_LMIC_IN2R_10K) {
667 snd_soc_write(codec, AIC32X4_LMICPGANIN, AIC32X4_LMICPGANIN_IN2R_10K);
668 }
669 if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_RMIC_IN1L_10K) {
670 snd_soc_write(codec, AIC32X4_RMICPGANIN, AIC32X4_RMICPGANIN_IN1L_10K);
671 }
672
673 aic32x4_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
674 snd_soc_add_codec_controls(codec, aic32x4_snd_controls,
675 ARRAY_SIZE(aic32x4_snd_controls));
676 aic32x4_add_widgets(codec);
677
678 return 0;
679}
680
681static int aic32x4_remove(struct snd_soc_codec *codec)
682{
683 aic32x4_set_bias_level(codec, SND_SOC_BIAS_OFF);
684 return 0;
685}
686
687static struct snd_soc_codec_driver soc_codec_dev_aic32x4 = {
688 .read = aic32x4_read,
689 .write = aic32x4_write,
690 .probe = aic32x4_probe,
691 .remove = aic32x4_remove,
692 .suspend = aic32x4_suspend,
693 .resume = aic32x4_resume,
694 .set_bias_level = aic32x4_set_bias_level,
695};
696
697static __devinit int aic32x4_i2c_probe(struct i2c_client *i2c,
698 const struct i2c_device_id *id)
699{
700 struct aic32x4_pdata *pdata = i2c->dev.platform_data;
701 struct aic32x4_priv *aic32x4;
702 int ret;
703
704 aic32x4 = devm_kzalloc(&i2c->dev, sizeof(struct aic32x4_priv),
705 GFP_KERNEL);
706 if (aic32x4 == NULL)
707 return -ENOMEM;
708
709 aic32x4->control_data = i2c;
710 i2c_set_clientdata(i2c, aic32x4);
711
712 if (pdata) {
713 aic32x4->power_cfg = pdata->power_cfg;
714 aic32x4->swapdacs = pdata->swapdacs;
715 aic32x4->micpga_routing = pdata->micpga_routing;
716 } else {
717 aic32x4->power_cfg = 0;
718 aic32x4->swapdacs = false;
719 aic32x4->micpga_routing = 0;
720 }
721
722 ret = snd_soc_register_codec(&i2c->dev,
723 &soc_codec_dev_aic32x4, &aic32x4_dai, 1);
724 return ret;
725}
726
727static __devexit int aic32x4_i2c_remove(struct i2c_client *client)
728{
729 snd_soc_unregister_codec(&client->dev);
730 return 0;
731}
732
733static const struct i2c_device_id aic32x4_i2c_id[] = {
734 { "tlv320aic32x4", 0 },
735 { }
736};
737MODULE_DEVICE_TABLE(i2c, aic32x4_i2c_id);
738
739static struct i2c_driver aic32x4_i2c_driver = {
740 .driver = {
741 .name = "tlv320aic32x4",
742 .owner = THIS_MODULE,
743 },
744 .probe = aic32x4_i2c_probe,
745 .remove = __devexit_p(aic32x4_i2c_remove),
746 .id_table = aic32x4_i2c_id,
747};
748
749static int __init aic32x4_modinit(void)
750{
751 int ret = 0;
752
753 ret = i2c_add_driver(&aic32x4_i2c_driver);
754 if (ret != 0) {
755 printk(KERN_ERR "Failed to register aic32x4 I2C driver: %d\n",
756 ret);
757 }
758 return ret;
759}
760module_init(aic32x4_modinit);
761
762static void __exit aic32x4_exit(void)
763{
764 i2c_del_driver(&aic32x4_i2c_driver);
765}
766module_exit(aic32x4_exit);
767
768MODULE_DESCRIPTION("ASoC tlv320aic32x4 codec driver");
769MODULE_AUTHOR("Javier Martin <javier.martin@vista-silicon.com>");
770MODULE_LICENSE("GPL");