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1// SPDX-License-Identifier: BSD-3-Clause-Clear
2/*
3 * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7#include <linux/module.h>
8#include <linux/msi.h>
9#include <linux/pci.h>
10#include <linux/time.h>
11#include <linux/vmalloc.h>
12
13#include "pci.h"
14#include "core.h"
15#include "hif.h"
16#include "mhi.h"
17#include "debug.h"
18
19#define ATH12K_PCI_BAR_NUM 0
20#define ATH12K_PCI_DMA_MASK 32
21
22#define ATH12K_PCI_IRQ_CE0_OFFSET 3
23
24#define WINDOW_ENABLE_BIT 0x40000000
25#define WINDOW_REG_ADDRESS 0x310c
26#define WINDOW_VALUE_MASK GENMASK(24, 19)
27#define WINDOW_START 0x80000
28#define WINDOW_RANGE_MASK GENMASK(18, 0)
29#define WINDOW_STATIC_MASK GENMASK(31, 6)
30
31#define TCSR_SOC_HW_VERSION 0x1B00000
32#define TCSR_SOC_HW_VERSION_MAJOR_MASK GENMASK(11, 8)
33#define TCSR_SOC_HW_VERSION_MINOR_MASK GENMASK(7, 4)
34
35/* BAR0 + 4k is always accessible, and no
36 * need to force wakeup.
37 * 4K - 32 = 0xFE0
38 */
39#define ACCESS_ALWAYS_OFF 0xFE0
40
41#define QCN9274_DEVICE_ID 0x1109
42#define WCN7850_DEVICE_ID 0x1107
43
44#define PCIE_LOCAL_REG_QRTR_NODE_ID 0x1E03164
45#define DOMAIN_NUMBER_MASK GENMASK(7, 4)
46#define BUS_NUMBER_MASK GENMASK(3, 0)
47
48static const struct pci_device_id ath12k_pci_id_table[] = {
49 { PCI_VDEVICE(QCOM, QCN9274_DEVICE_ID) },
50 { PCI_VDEVICE(QCOM, WCN7850_DEVICE_ID) },
51 {0}
52};
53
54MODULE_DEVICE_TABLE(pci, ath12k_pci_id_table);
55
56/* TODO: revisit IRQ mapping for new SRNG's */
57static const struct ath12k_msi_config ath12k_msi_config[] = {
58 {
59 .total_vectors = 16,
60 .total_users = 3,
61 .users = (struct ath12k_msi_user[]) {
62 { .name = "MHI", .num_vectors = 3, .base_vector = 0 },
63 { .name = "CE", .num_vectors = 5, .base_vector = 3 },
64 { .name = "DP", .num_vectors = 8, .base_vector = 8 },
65 },
66 },
67};
68
69static const struct ath12k_msi_config msi_config_one_msi = {
70 .total_vectors = 1,
71 .total_users = 4,
72 .users = (struct ath12k_msi_user[]) {
73 { .name = "MHI", .num_vectors = 3, .base_vector = 0 },
74 { .name = "CE", .num_vectors = 1, .base_vector = 0 },
75 { .name = "WAKE", .num_vectors = 1, .base_vector = 0 },
76 { .name = "DP", .num_vectors = 1, .base_vector = 0 },
77 },
78};
79
80static const char *irq_name[ATH12K_IRQ_NUM_MAX] = {
81 "bhi",
82 "mhi-er0",
83 "mhi-er1",
84 "ce0",
85 "ce1",
86 "ce2",
87 "ce3",
88 "ce4",
89 "ce5",
90 "ce6",
91 "ce7",
92 "ce8",
93 "ce9",
94 "ce10",
95 "ce11",
96 "ce12",
97 "ce13",
98 "ce14",
99 "ce15",
100 "host2wbm-desc-feed",
101 "host2reo-re-injection",
102 "host2reo-command",
103 "host2rxdma-monitor-ring3",
104 "host2rxdma-monitor-ring2",
105 "host2rxdma-monitor-ring1",
106 "reo2ost-exception",
107 "wbm2host-rx-release",
108 "reo2host-status",
109 "reo2host-destination-ring4",
110 "reo2host-destination-ring3",
111 "reo2host-destination-ring2",
112 "reo2host-destination-ring1",
113 "rxdma2host-monitor-destination-mac3",
114 "rxdma2host-monitor-destination-mac2",
115 "rxdma2host-monitor-destination-mac1",
116 "ppdu-end-interrupts-mac3",
117 "ppdu-end-interrupts-mac2",
118 "ppdu-end-interrupts-mac1",
119 "rxdma2host-monitor-status-ring-mac3",
120 "rxdma2host-monitor-status-ring-mac2",
121 "rxdma2host-monitor-status-ring-mac1",
122 "host2rxdma-host-buf-ring-mac3",
123 "host2rxdma-host-buf-ring-mac2",
124 "host2rxdma-host-buf-ring-mac1",
125 "rxdma2host-destination-ring-mac3",
126 "rxdma2host-destination-ring-mac2",
127 "rxdma2host-destination-ring-mac1",
128 "host2tcl-input-ring4",
129 "host2tcl-input-ring3",
130 "host2tcl-input-ring2",
131 "host2tcl-input-ring1",
132 "wbm2host-tx-completions-ring4",
133 "wbm2host-tx-completions-ring3",
134 "wbm2host-tx-completions-ring2",
135 "wbm2host-tx-completions-ring1",
136 "tcl2host-status-ring",
137};
138
139static int ath12k_pci_bus_wake_up(struct ath12k_base *ab)
140{
141 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);
142
143 return mhi_device_get_sync(ab_pci->mhi_ctrl->mhi_dev);
144}
145
146static void ath12k_pci_bus_release(struct ath12k_base *ab)
147{
148 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);
149
150 mhi_device_put(ab_pci->mhi_ctrl->mhi_dev);
151}
152
153static const struct ath12k_pci_ops ath12k_pci_ops_qcn9274 = {
154 .wakeup = NULL,
155 .release = NULL,
156};
157
158static const struct ath12k_pci_ops ath12k_pci_ops_wcn7850 = {
159 .wakeup = ath12k_pci_bus_wake_up,
160 .release = ath12k_pci_bus_release,
161};
162
163static void ath12k_pci_select_window(struct ath12k_pci *ab_pci, u32 offset)
164{
165 struct ath12k_base *ab = ab_pci->ab;
166
167 u32 window = u32_get_bits(offset, WINDOW_VALUE_MASK);
168 u32 static_window;
169
170 lockdep_assert_held(&ab_pci->window_lock);
171
172 /* Preserve the static window configuration and reset only dynamic window */
173 static_window = ab_pci->register_window & WINDOW_STATIC_MASK;
174 window |= static_window;
175
176 if (window != ab_pci->register_window) {
177 iowrite32(WINDOW_ENABLE_BIT | window,
178 ab->mem + WINDOW_REG_ADDRESS);
179 ioread32(ab->mem + WINDOW_REG_ADDRESS);
180 ab_pci->register_window = window;
181 }
182}
183
184static void ath12k_pci_select_static_window(struct ath12k_pci *ab_pci)
185{
186 u32 umac_window = u32_get_bits(HAL_SEQ_WCSS_UMAC_OFFSET, WINDOW_VALUE_MASK);
187 u32 ce_window = u32_get_bits(HAL_CE_WFSS_CE_REG_BASE, WINDOW_VALUE_MASK);
188 u32 window;
189
190 window = (umac_window << 12) | (ce_window << 6);
191
192 spin_lock_bh(&ab_pci->window_lock);
193 ab_pci->register_window = window;
194 spin_unlock_bh(&ab_pci->window_lock);
195
196 iowrite32(WINDOW_ENABLE_BIT | window, ab_pci->ab->mem + WINDOW_REG_ADDRESS);
197}
198
199static u32 ath12k_pci_get_window_start(struct ath12k_base *ab,
200 u32 offset)
201{
202 u32 window_start;
203
204 /* If offset lies within DP register range, use 3rd window */
205 if ((offset ^ HAL_SEQ_WCSS_UMAC_OFFSET) < WINDOW_RANGE_MASK)
206 window_start = 3 * WINDOW_START;
207 /* If offset lies within CE register range, use 2nd window */
208 else if ((offset ^ HAL_CE_WFSS_CE_REG_BASE) < WINDOW_RANGE_MASK)
209 window_start = 2 * WINDOW_START;
210 else
211 window_start = WINDOW_START;
212
213 return window_start;
214}
215
216static inline bool ath12k_pci_is_offset_within_mhi_region(u32 offset)
217{
218 return (offset >= PCI_MHIREGLEN_REG && offset <= PCI_MHI_REGION_END);
219}
220
221static void ath12k_pci_soc_global_reset(struct ath12k_base *ab)
222{
223 u32 val, delay;
224
225 val = ath12k_pci_read32(ab, PCIE_SOC_GLOBAL_RESET);
226
227 val |= PCIE_SOC_GLOBAL_RESET_V;
228
229 ath12k_pci_write32(ab, PCIE_SOC_GLOBAL_RESET, val);
230
231 /* TODO: exact time to sleep is uncertain */
232 delay = 10;
233 mdelay(delay);
234
235 /* Need to toggle V bit back otherwise stuck in reset status */
236 val &= ~PCIE_SOC_GLOBAL_RESET_V;
237
238 ath12k_pci_write32(ab, PCIE_SOC_GLOBAL_RESET, val);
239
240 mdelay(delay);
241
242 val = ath12k_pci_read32(ab, PCIE_SOC_GLOBAL_RESET);
243 if (val == 0xffffffff)
244 ath12k_warn(ab, "link down error during global reset\n");
245}
246
247static void ath12k_pci_clear_dbg_registers(struct ath12k_base *ab)
248{
249 u32 val;
250
251 /* read cookie */
252 val = ath12k_pci_read32(ab, PCIE_Q6_COOKIE_ADDR);
253 ath12k_dbg(ab, ATH12K_DBG_PCI, "cookie:0x%x\n", val);
254
255 val = ath12k_pci_read32(ab, WLAON_WARM_SW_ENTRY);
256 ath12k_dbg(ab, ATH12K_DBG_PCI, "WLAON_WARM_SW_ENTRY 0x%x\n", val);
257
258 /* TODO: exact time to sleep is uncertain */
259 mdelay(10);
260
261 /* write 0 to WLAON_WARM_SW_ENTRY to prevent Q6 from
262 * continuing warm path and entering dead loop.
263 */
264 ath12k_pci_write32(ab, WLAON_WARM_SW_ENTRY, 0);
265 mdelay(10);
266
267 val = ath12k_pci_read32(ab, WLAON_WARM_SW_ENTRY);
268 ath12k_dbg(ab, ATH12K_DBG_PCI, "WLAON_WARM_SW_ENTRY 0x%x\n", val);
269
270 /* A read clear register. clear the register to prevent
271 * Q6 from entering wrong code path.
272 */
273 val = ath12k_pci_read32(ab, WLAON_SOC_RESET_CAUSE_REG);
274 ath12k_dbg(ab, ATH12K_DBG_PCI, "soc reset cause:%d\n", val);
275}
276
277static void ath12k_pci_enable_ltssm(struct ath12k_base *ab)
278{
279 u32 val;
280 int i;
281
282 val = ath12k_pci_read32(ab, PCIE_PCIE_PARF_LTSSM);
283
284 /* PCIE link seems very unstable after the Hot Reset*/
285 for (i = 0; val != PARM_LTSSM_VALUE && i < 5; i++) {
286 if (val == 0xffffffff)
287 mdelay(5);
288
289 ath12k_pci_write32(ab, PCIE_PCIE_PARF_LTSSM, PARM_LTSSM_VALUE);
290 val = ath12k_pci_read32(ab, PCIE_PCIE_PARF_LTSSM);
291 }
292
293 ath12k_dbg(ab, ATH12K_DBG_PCI, "pci ltssm 0x%x\n", val);
294
295 val = ath12k_pci_read32(ab, GCC_GCC_PCIE_HOT_RST);
296 val |= GCC_GCC_PCIE_HOT_RST_VAL;
297 ath12k_pci_write32(ab, GCC_GCC_PCIE_HOT_RST, val);
298 val = ath12k_pci_read32(ab, GCC_GCC_PCIE_HOT_RST);
299
300 ath12k_dbg(ab, ATH12K_DBG_PCI, "pci pcie_hot_rst 0x%x\n", val);
301
302 mdelay(5);
303}
304
305static void ath12k_pci_clear_all_intrs(struct ath12k_base *ab)
306{
307 /* This is a WAR for PCIE Hotreset.
308 * When target receive Hotreset, but will set the interrupt.
309 * So when download SBL again, SBL will open Interrupt and
310 * receive it, and crash immediately.
311 */
312 ath12k_pci_write32(ab, PCIE_PCIE_INT_ALL_CLEAR, PCIE_INT_CLEAR_ALL);
313}
314
315static void ath12k_pci_set_wlaon_pwr_ctrl(struct ath12k_base *ab)
316{
317 u32 val;
318
319 val = ath12k_pci_read32(ab, WLAON_QFPROM_PWR_CTRL_REG);
320 val &= ~QFPROM_PWR_CTRL_VDD4BLOW_MASK;
321 ath12k_pci_write32(ab, WLAON_QFPROM_PWR_CTRL_REG, val);
322}
323
324static void ath12k_pci_force_wake(struct ath12k_base *ab)
325{
326 ath12k_pci_write32(ab, PCIE_SOC_WAKE_PCIE_LOCAL_REG, 1);
327 mdelay(5);
328}
329
330static void ath12k_pci_sw_reset(struct ath12k_base *ab, bool power_on)
331{
332 if (power_on) {
333 ath12k_pci_enable_ltssm(ab);
334 ath12k_pci_clear_all_intrs(ab);
335 ath12k_pci_set_wlaon_pwr_ctrl(ab);
336 }
337
338 ath12k_mhi_clear_vector(ab);
339 ath12k_pci_clear_dbg_registers(ab);
340 ath12k_pci_soc_global_reset(ab);
341 ath12k_mhi_set_mhictrl_reset(ab);
342}
343
344static void ath12k_pci_free_ext_irq(struct ath12k_base *ab)
345{
346 int i, j;
347
348 for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX; i++) {
349 struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
350
351 for (j = 0; j < irq_grp->num_irq; j++)
352 free_irq(ab->irq_num[irq_grp->irqs[j]], irq_grp);
353
354 netif_napi_del(&irq_grp->napi);
355 free_netdev(irq_grp->napi_ndev);
356 }
357}
358
359static void ath12k_pci_free_irq(struct ath12k_base *ab)
360{
361 int i, irq_idx;
362
363 for (i = 0; i < ab->hw_params->ce_count; i++) {
364 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
365 continue;
366 irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + i;
367 free_irq(ab->irq_num[irq_idx], &ab->ce.ce_pipe[i]);
368 }
369
370 ath12k_pci_free_ext_irq(ab);
371}
372
373static void ath12k_pci_ce_irq_enable(struct ath12k_base *ab, u16 ce_id)
374{
375 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);
376 u32 irq_idx;
377
378 /* In case of one MSI vector, we handle irq enable/disable in a
379 * uniform way since we only have one irq
380 */
381 if (!test_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags))
382 return;
383
384 irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + ce_id;
385 enable_irq(ab->irq_num[irq_idx]);
386}
387
388static void ath12k_pci_ce_irq_disable(struct ath12k_base *ab, u16 ce_id)
389{
390 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);
391 u32 irq_idx;
392
393 /* In case of one MSI vector, we handle irq enable/disable in a
394 * uniform way since we only have one irq
395 */
396 if (!test_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags))
397 return;
398
399 irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + ce_id;
400 disable_irq_nosync(ab->irq_num[irq_idx]);
401}
402
403static void ath12k_pci_ce_irqs_disable(struct ath12k_base *ab)
404{
405 int i;
406
407 clear_bit(ATH12K_FLAG_CE_IRQ_ENABLED, &ab->dev_flags);
408
409 for (i = 0; i < ab->hw_params->ce_count; i++) {
410 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
411 continue;
412 ath12k_pci_ce_irq_disable(ab, i);
413 }
414}
415
416static void ath12k_pci_sync_ce_irqs(struct ath12k_base *ab)
417{
418 int i;
419 int irq_idx;
420
421 for (i = 0; i < ab->hw_params->ce_count; i++) {
422 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
423 continue;
424
425 irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + i;
426 synchronize_irq(ab->irq_num[irq_idx]);
427 }
428}
429
430static void ath12k_pci_ce_workqueue(struct work_struct *work)
431{
432 struct ath12k_ce_pipe *ce_pipe = from_work(ce_pipe, work, intr_wq);
433 int irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + ce_pipe->pipe_num;
434
435 ath12k_ce_per_engine_service(ce_pipe->ab, ce_pipe->pipe_num);
436
437 enable_irq(ce_pipe->ab->irq_num[irq_idx]);
438}
439
440static irqreturn_t ath12k_pci_ce_interrupt_handler(int irq, void *arg)
441{
442 struct ath12k_ce_pipe *ce_pipe = arg;
443 struct ath12k_base *ab = ce_pipe->ab;
444 int irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + ce_pipe->pipe_num;
445
446 if (!test_bit(ATH12K_FLAG_CE_IRQ_ENABLED, &ab->dev_flags))
447 return IRQ_HANDLED;
448
449 /* last interrupt received for this CE */
450 ce_pipe->timestamp = jiffies;
451
452 disable_irq_nosync(ab->irq_num[irq_idx]);
453
454 queue_work(system_bh_wq, &ce_pipe->intr_wq);
455
456 return IRQ_HANDLED;
457}
458
459static void ath12k_pci_ext_grp_disable(struct ath12k_ext_irq_grp *irq_grp)
460{
461 struct ath12k_pci *ab_pci = ath12k_pci_priv(irq_grp->ab);
462 int i;
463
464 /* In case of one MSI vector, we handle irq enable/disable
465 * in a uniform way since we only have one irq
466 */
467 if (!test_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags))
468 return;
469
470 for (i = 0; i < irq_grp->num_irq; i++)
471 disable_irq_nosync(irq_grp->ab->irq_num[irq_grp->irqs[i]]);
472}
473
474static void __ath12k_pci_ext_irq_disable(struct ath12k_base *ab)
475{
476 int i;
477
478 if (!test_and_clear_bit(ATH12K_FLAG_EXT_IRQ_ENABLED, &ab->dev_flags))
479 return;
480
481 for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX; i++) {
482 struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
483
484 ath12k_pci_ext_grp_disable(irq_grp);
485
486 napi_synchronize(&irq_grp->napi);
487 napi_disable(&irq_grp->napi);
488 }
489}
490
491static void ath12k_pci_ext_grp_enable(struct ath12k_ext_irq_grp *irq_grp)
492{
493 struct ath12k_pci *ab_pci = ath12k_pci_priv(irq_grp->ab);
494 int i;
495
496 /* In case of one MSI vector, we handle irq enable/disable in a
497 * uniform way since we only have one irq
498 */
499 if (!test_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags))
500 return;
501
502 for (i = 0; i < irq_grp->num_irq; i++)
503 enable_irq(irq_grp->ab->irq_num[irq_grp->irqs[i]]);
504}
505
506static void ath12k_pci_sync_ext_irqs(struct ath12k_base *ab)
507{
508 int i, j, irq_idx;
509
510 for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX; i++) {
511 struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
512
513 for (j = 0; j < irq_grp->num_irq; j++) {
514 irq_idx = irq_grp->irqs[j];
515 synchronize_irq(ab->irq_num[irq_idx]);
516 }
517 }
518}
519
520static int ath12k_pci_ext_grp_napi_poll(struct napi_struct *napi, int budget)
521{
522 struct ath12k_ext_irq_grp *irq_grp = container_of(napi,
523 struct ath12k_ext_irq_grp,
524 napi);
525 struct ath12k_base *ab = irq_grp->ab;
526 int work_done;
527 int i;
528
529 work_done = ath12k_dp_service_srng(ab, irq_grp, budget);
530 if (work_done < budget) {
531 napi_complete_done(napi, work_done);
532 for (i = 0; i < irq_grp->num_irq; i++)
533 enable_irq(irq_grp->ab->irq_num[irq_grp->irqs[i]]);
534 }
535
536 if (work_done > budget)
537 work_done = budget;
538
539 return work_done;
540}
541
542static irqreturn_t ath12k_pci_ext_interrupt_handler(int irq, void *arg)
543{
544 struct ath12k_ext_irq_grp *irq_grp = arg;
545 struct ath12k_base *ab = irq_grp->ab;
546 int i;
547
548 if (!test_bit(ATH12K_FLAG_EXT_IRQ_ENABLED, &ab->dev_flags))
549 return IRQ_HANDLED;
550
551 ath12k_dbg(irq_grp->ab, ATH12K_DBG_PCI, "ext irq:%d\n", irq);
552
553 /* last interrupt received for this group */
554 irq_grp->timestamp = jiffies;
555
556 for (i = 0; i < irq_grp->num_irq; i++)
557 disable_irq_nosync(irq_grp->ab->irq_num[irq_grp->irqs[i]]);
558
559 napi_schedule(&irq_grp->napi);
560
561 return IRQ_HANDLED;
562}
563
564static int ath12k_pci_ext_irq_config(struct ath12k_base *ab)
565{
566 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);
567 int i, j, n, ret, num_vectors = 0;
568 u32 user_base_data = 0, base_vector = 0, base_idx;
569 struct ath12k_ext_irq_grp *irq_grp;
570
571 base_idx = ATH12K_PCI_IRQ_CE0_OFFSET + CE_COUNT_MAX;
572 ret = ath12k_pci_get_user_msi_assignment(ab, "DP",
573 &num_vectors,
574 &user_base_data,
575 &base_vector);
576 if (ret < 0)
577 return ret;
578
579 for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX; i++) {
580 irq_grp = &ab->ext_irq_grp[i];
581 u32 num_irq = 0;
582
583 irq_grp->ab = ab;
584 irq_grp->grp_id = i;
585 irq_grp->napi_ndev = alloc_netdev_dummy(0);
586 if (!irq_grp->napi_ndev) {
587 ret = -ENOMEM;
588 goto fail_allocate;
589 }
590
591 netif_napi_add(irq_grp->napi_ndev, &irq_grp->napi,
592 ath12k_pci_ext_grp_napi_poll);
593
594 if (ab->hw_params->ring_mask->tx[i] ||
595 ab->hw_params->ring_mask->rx[i] ||
596 ab->hw_params->ring_mask->rx_err[i] ||
597 ab->hw_params->ring_mask->rx_wbm_rel[i] ||
598 ab->hw_params->ring_mask->reo_status[i] ||
599 ab->hw_params->ring_mask->host2rxdma[i] ||
600 ab->hw_params->ring_mask->rx_mon_dest[i]) {
601 num_irq = 1;
602 }
603
604 irq_grp->num_irq = num_irq;
605 irq_grp->irqs[0] = base_idx + i;
606
607 for (j = 0; j < irq_grp->num_irq; j++) {
608 int irq_idx = irq_grp->irqs[j];
609 int vector = (i % num_vectors) + base_vector;
610 int irq = ath12k_pci_get_msi_irq(ab->dev, vector);
611
612 ab->irq_num[irq_idx] = irq;
613
614 ath12k_dbg(ab, ATH12K_DBG_PCI,
615 "irq:%d group:%d\n", irq, i);
616
617 irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY);
618 ret = request_irq(irq, ath12k_pci_ext_interrupt_handler,
619 ab_pci->irq_flags,
620 "DP_EXT_IRQ", irq_grp);
621 if (ret) {
622 ath12k_err(ab, "failed request irq %d: %d\n",
623 vector, ret);
624 goto fail_request;
625 }
626 }
627 ath12k_pci_ext_grp_disable(irq_grp);
628 }
629
630 return 0;
631
632fail_request:
633 /* i ->napi_ndev was properly allocated. Free it also */
634 i += 1;
635fail_allocate:
636 for (n = 0; n < i; n++) {
637 irq_grp = &ab->ext_irq_grp[n];
638 free_netdev(irq_grp->napi_ndev);
639 }
640 return ret;
641}
642
643static int ath12k_pci_set_irq_affinity_hint(struct ath12k_pci *ab_pci,
644 const struct cpumask *m)
645{
646 if (test_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags))
647 return 0;
648
649 return irq_set_affinity_hint(ab_pci->pdev->irq, m);
650}
651
652static int ath12k_pci_config_irq(struct ath12k_base *ab)
653{
654 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);
655 struct ath12k_ce_pipe *ce_pipe;
656 u32 msi_data_start;
657 u32 msi_data_count, msi_data_idx;
658 u32 msi_irq_start;
659 unsigned int msi_data;
660 int irq, i, ret, irq_idx;
661
662 ret = ath12k_pci_get_user_msi_assignment(ab,
663 "CE", &msi_data_count,
664 &msi_data_start, &msi_irq_start);
665 if (ret)
666 return ret;
667
668 /* Configure CE irqs */
669
670 for (i = 0, msi_data_idx = 0; i < ab->hw_params->ce_count; i++) {
671 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
672 continue;
673
674 msi_data = (msi_data_idx % msi_data_count) + msi_irq_start;
675 irq = ath12k_pci_get_msi_irq(ab->dev, msi_data);
676 ce_pipe = &ab->ce.ce_pipe[i];
677
678 irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + i;
679
680 INIT_WORK(&ce_pipe->intr_wq, ath12k_pci_ce_workqueue);
681
682 ret = request_irq(irq, ath12k_pci_ce_interrupt_handler,
683 ab_pci->irq_flags, irq_name[irq_idx],
684 ce_pipe);
685 if (ret) {
686 ath12k_err(ab, "failed to request irq %d: %d\n",
687 irq_idx, ret);
688 return ret;
689 }
690
691 ab->irq_num[irq_idx] = irq;
692 msi_data_idx++;
693
694 ath12k_pci_ce_irq_disable(ab, i);
695 }
696
697 ret = ath12k_pci_ext_irq_config(ab);
698 if (ret)
699 return ret;
700
701 return 0;
702}
703
704static void ath12k_pci_init_qmi_ce_config(struct ath12k_base *ab)
705{
706 struct ath12k_qmi_ce_cfg *cfg = &ab->qmi.ce_cfg;
707
708 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);
709 struct pci_bus *bus = ab_pci->pdev->bus;
710
711 cfg->tgt_ce = ab->hw_params->target_ce_config;
712 cfg->tgt_ce_len = ab->hw_params->target_ce_count;
713
714 cfg->svc_to_ce_map = ab->hw_params->svc_to_ce_map;
715 cfg->svc_to_ce_map_len = ab->hw_params->svc_to_ce_map_len;
716 ab->qmi.service_ins_id = ab->hw_params->qmi_service_ins_id;
717
718 if (test_bit(ATH12K_FW_FEATURE_MULTI_QRTR_ID, ab->fw.fw_features)) {
719 ab_pci->qmi_instance =
720 u32_encode_bits(pci_domain_nr(bus), DOMAIN_NUMBER_MASK) |
721 u32_encode_bits(bus->number, BUS_NUMBER_MASK);
722 ab->qmi.service_ins_id += ab_pci->qmi_instance;
723 }
724}
725
726static void ath12k_pci_ce_irqs_enable(struct ath12k_base *ab)
727{
728 int i;
729
730 set_bit(ATH12K_FLAG_CE_IRQ_ENABLED, &ab->dev_flags);
731
732 for (i = 0; i < ab->hw_params->ce_count; i++) {
733 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
734 continue;
735 ath12k_pci_ce_irq_enable(ab, i);
736 }
737}
738
739static void ath12k_pci_msi_config(struct ath12k_pci *ab_pci, bool enable)
740{
741 struct pci_dev *dev = ab_pci->pdev;
742 u16 control;
743
744 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
745
746 if (enable)
747 control |= PCI_MSI_FLAGS_ENABLE;
748 else
749 control &= ~PCI_MSI_FLAGS_ENABLE;
750
751 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
752}
753
754static void ath12k_pci_msi_enable(struct ath12k_pci *ab_pci)
755{
756 ath12k_pci_msi_config(ab_pci, true);
757}
758
759static void ath12k_pci_msi_disable(struct ath12k_pci *ab_pci)
760{
761 ath12k_pci_msi_config(ab_pci, false);
762}
763
764static int ath12k_pci_msi_alloc(struct ath12k_pci *ab_pci)
765{
766 struct ath12k_base *ab = ab_pci->ab;
767 const struct ath12k_msi_config *msi_config = ab_pci->msi_config;
768 struct msi_desc *msi_desc;
769 int num_vectors;
770 int ret;
771
772 num_vectors = pci_alloc_irq_vectors(ab_pci->pdev,
773 msi_config->total_vectors,
774 msi_config->total_vectors,
775 PCI_IRQ_MSI);
776
777 if (num_vectors == msi_config->total_vectors) {
778 set_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags);
779 ab_pci->irq_flags = IRQF_SHARED;
780 } else {
781 num_vectors = pci_alloc_irq_vectors(ab_pci->pdev,
782 1,
783 1,
784 PCI_IRQ_MSI);
785 if (num_vectors < 0) {
786 ret = -EINVAL;
787 goto reset_msi_config;
788 }
789 clear_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags);
790 ab_pci->msi_config = &msi_config_one_msi;
791 ab_pci->irq_flags = IRQF_SHARED | IRQF_NOBALANCING;
792 ath12k_dbg(ab, ATH12K_DBG_PCI, "request MSI one vector\n");
793 }
794
795 ath12k_info(ab, "MSI vectors: %d\n", num_vectors);
796
797 ath12k_pci_msi_disable(ab_pci);
798
799 msi_desc = irq_get_msi_desc(ab_pci->pdev->irq);
800 if (!msi_desc) {
801 ath12k_err(ab, "msi_desc is NULL!\n");
802 ret = -EINVAL;
803 goto free_msi_vector;
804 }
805
806 ab_pci->msi_ep_base_data = msi_desc->msg.data;
807 if (msi_desc->pci.msi_attrib.is_64)
808 set_bit(ATH12K_PCI_FLAG_IS_MSI_64, &ab_pci->flags);
809
810 ath12k_dbg(ab, ATH12K_DBG_PCI, "msi base data is %d\n", ab_pci->msi_ep_base_data);
811
812 return 0;
813
814free_msi_vector:
815 pci_free_irq_vectors(ab_pci->pdev);
816
817reset_msi_config:
818 return ret;
819}
820
821static void ath12k_pci_msi_free(struct ath12k_pci *ab_pci)
822{
823 pci_free_irq_vectors(ab_pci->pdev);
824}
825
826static int ath12k_pci_config_msi_data(struct ath12k_pci *ab_pci)
827{
828 struct msi_desc *msi_desc;
829
830 msi_desc = irq_get_msi_desc(ab_pci->pdev->irq);
831 if (!msi_desc) {
832 ath12k_err(ab_pci->ab, "msi_desc is NULL!\n");
833 pci_free_irq_vectors(ab_pci->pdev);
834 return -EINVAL;
835 }
836
837 ab_pci->msi_ep_base_data = msi_desc->msg.data;
838
839 ath12k_dbg(ab_pci->ab, ATH12K_DBG_PCI, "pci after request_irq msi_ep_base_data %d\n",
840 ab_pci->msi_ep_base_data);
841
842 return 0;
843}
844
845static int ath12k_pci_claim(struct ath12k_pci *ab_pci, struct pci_dev *pdev)
846{
847 struct ath12k_base *ab = ab_pci->ab;
848 u16 device_id;
849 int ret = 0;
850
851 pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id);
852 if (device_id != ab_pci->dev_id) {
853 ath12k_err(ab, "pci device id mismatch: 0x%x 0x%x\n",
854 device_id, ab_pci->dev_id);
855 ret = -EIO;
856 goto out;
857 }
858
859 ret = pci_assign_resource(pdev, ATH12K_PCI_BAR_NUM);
860 if (ret) {
861 ath12k_err(ab, "failed to assign pci resource: %d\n", ret);
862 goto out;
863 }
864
865 ret = pci_enable_device(pdev);
866 if (ret) {
867 ath12k_err(ab, "failed to enable pci device: %d\n", ret);
868 goto out;
869 }
870
871 ret = pci_request_region(pdev, ATH12K_PCI_BAR_NUM, "ath12k_pci");
872 if (ret) {
873 ath12k_err(ab, "failed to request pci region: %d\n", ret);
874 goto disable_device;
875 }
876
877 ret = dma_set_mask_and_coherent(&pdev->dev,
878 DMA_BIT_MASK(ATH12K_PCI_DMA_MASK));
879 if (ret) {
880 ath12k_err(ab, "failed to set pci dma mask to %d: %d\n",
881 ATH12K_PCI_DMA_MASK, ret);
882 goto release_region;
883 }
884
885 pci_set_master(pdev);
886
887 ab->mem_len = pci_resource_len(pdev, ATH12K_PCI_BAR_NUM);
888 ab->mem = pci_iomap(pdev, ATH12K_PCI_BAR_NUM, 0);
889 if (!ab->mem) {
890 ath12k_err(ab, "failed to map pci bar %d\n", ATH12K_PCI_BAR_NUM);
891 ret = -EIO;
892 goto release_region;
893 }
894
895 ath12k_dbg(ab, ATH12K_DBG_BOOT, "boot pci_mem 0x%p\n", ab->mem);
896 return 0;
897
898release_region:
899 pci_release_region(pdev, ATH12K_PCI_BAR_NUM);
900disable_device:
901 pci_disable_device(pdev);
902out:
903 return ret;
904}
905
906static void ath12k_pci_free_region(struct ath12k_pci *ab_pci)
907{
908 struct ath12k_base *ab = ab_pci->ab;
909 struct pci_dev *pci_dev = ab_pci->pdev;
910
911 pci_iounmap(pci_dev, ab->mem);
912 ab->mem = NULL;
913 pci_release_region(pci_dev, ATH12K_PCI_BAR_NUM);
914 if (pci_is_enabled(pci_dev))
915 pci_disable_device(pci_dev);
916}
917
918static void ath12k_pci_aspm_disable(struct ath12k_pci *ab_pci)
919{
920 struct ath12k_base *ab = ab_pci->ab;
921
922 pcie_capability_read_word(ab_pci->pdev, PCI_EXP_LNKCTL,
923 &ab_pci->link_ctl);
924
925 ath12k_dbg(ab, ATH12K_DBG_PCI, "pci link_ctl 0x%04x L0s %d L1 %d\n",
926 ab_pci->link_ctl,
927 u16_get_bits(ab_pci->link_ctl, PCI_EXP_LNKCTL_ASPM_L0S),
928 u16_get_bits(ab_pci->link_ctl, PCI_EXP_LNKCTL_ASPM_L1));
929
930 /* disable L0s and L1 */
931 pcie_capability_clear_word(ab_pci->pdev, PCI_EXP_LNKCTL,
932 PCI_EXP_LNKCTL_ASPMC);
933
934 set_bit(ATH12K_PCI_ASPM_RESTORE, &ab_pci->flags);
935}
936
937static void ath12k_pci_update_qrtr_node_id(struct ath12k_base *ab)
938{
939 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);
940 u32 reg;
941
942 /* On platforms with two or more identical mhi devices, qmi service run
943 * with identical qrtr-node-id. Because of this identical ID qrtr-lookup
944 * cannot register more than one qmi service with identical node ID.
945 *
946 * This generates a unique instance ID from PCIe domain number and bus number,
947 * writes to the given register, it is available for firmware when the QMI service
948 * is spawned.
949 */
950 reg = PCIE_LOCAL_REG_QRTR_NODE_ID & WINDOW_RANGE_MASK;
951 ath12k_pci_write32(ab, reg, ab_pci->qmi_instance);
952
953 ath12k_dbg(ab, ATH12K_DBG_PCI, "pci reg 0x%x instance 0x%x read val 0x%x\n",
954 reg, ab_pci->qmi_instance, ath12k_pci_read32(ab, reg));
955}
956
957static void ath12k_pci_aspm_restore(struct ath12k_pci *ab_pci)
958{
959 if (ab_pci->ab->hw_params->supports_aspm &&
960 test_and_clear_bit(ATH12K_PCI_ASPM_RESTORE, &ab_pci->flags))
961 pcie_capability_clear_and_set_word(ab_pci->pdev, PCI_EXP_LNKCTL,
962 PCI_EXP_LNKCTL_ASPMC,
963 ab_pci->link_ctl &
964 PCI_EXP_LNKCTL_ASPMC);
965}
966
967static void ath12k_pci_cancel_workqueue(struct ath12k_base *ab)
968{
969 int i;
970
971 for (i = 0; i < ab->hw_params->ce_count; i++) {
972 struct ath12k_ce_pipe *ce_pipe = &ab->ce.ce_pipe[i];
973
974 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
975 continue;
976
977 cancel_work_sync(&ce_pipe->intr_wq);
978 }
979}
980
981static void ath12k_pci_ce_irq_disable_sync(struct ath12k_base *ab)
982{
983 ath12k_pci_ce_irqs_disable(ab);
984 ath12k_pci_sync_ce_irqs(ab);
985 ath12k_pci_cancel_workqueue(ab);
986}
987
988int ath12k_pci_map_service_to_pipe(struct ath12k_base *ab, u16 service_id,
989 u8 *ul_pipe, u8 *dl_pipe)
990{
991 const struct service_to_pipe *entry;
992 bool ul_set = false, dl_set = false;
993 int i;
994
995 for (i = 0; i < ab->hw_params->svc_to_ce_map_len; i++) {
996 entry = &ab->hw_params->svc_to_ce_map[i];
997
998 if (__le32_to_cpu(entry->service_id) != service_id)
999 continue;
1000
1001 switch (__le32_to_cpu(entry->pipedir)) {
1002 case PIPEDIR_NONE:
1003 break;
1004 case PIPEDIR_IN:
1005 WARN_ON(dl_set);
1006 *dl_pipe = __le32_to_cpu(entry->pipenum);
1007 dl_set = true;
1008 break;
1009 case PIPEDIR_OUT:
1010 WARN_ON(ul_set);
1011 *ul_pipe = __le32_to_cpu(entry->pipenum);
1012 ul_set = true;
1013 break;
1014 case PIPEDIR_INOUT:
1015 WARN_ON(dl_set);
1016 WARN_ON(ul_set);
1017 *dl_pipe = __le32_to_cpu(entry->pipenum);
1018 *ul_pipe = __le32_to_cpu(entry->pipenum);
1019 dl_set = true;
1020 ul_set = true;
1021 break;
1022 }
1023 }
1024
1025 if (WARN_ON(!ul_set || !dl_set))
1026 return -ENOENT;
1027
1028 return 0;
1029}
1030
1031int ath12k_pci_get_msi_irq(struct device *dev, unsigned int vector)
1032{
1033 struct pci_dev *pci_dev = to_pci_dev(dev);
1034
1035 return pci_irq_vector(pci_dev, vector);
1036}
1037
1038int ath12k_pci_get_user_msi_assignment(struct ath12k_base *ab, char *user_name,
1039 int *num_vectors, u32 *user_base_data,
1040 u32 *base_vector)
1041{
1042 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);
1043 const struct ath12k_msi_config *msi_config = ab_pci->msi_config;
1044 int idx;
1045
1046 for (idx = 0; idx < msi_config->total_users; idx++) {
1047 if (strcmp(user_name, msi_config->users[idx].name) == 0) {
1048 *num_vectors = msi_config->users[idx].num_vectors;
1049 *base_vector = msi_config->users[idx].base_vector;
1050 *user_base_data = *base_vector + ab_pci->msi_ep_base_data;
1051
1052 ath12k_dbg(ab, ATH12K_DBG_PCI,
1053 "Assign MSI to user: %s, num_vectors: %d, user_base_data: %u, base_vector: %u\n",
1054 user_name, *num_vectors, *user_base_data,
1055 *base_vector);
1056
1057 return 0;
1058 }
1059 }
1060
1061 ath12k_err(ab, "Failed to find MSI assignment for %s!\n", user_name);
1062
1063 return -EINVAL;
1064}
1065
1066void ath12k_pci_get_msi_address(struct ath12k_base *ab, u32 *msi_addr_lo,
1067 u32 *msi_addr_hi)
1068{
1069 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);
1070 struct pci_dev *pci_dev = to_pci_dev(ab->dev);
1071
1072 pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_LO,
1073 msi_addr_lo);
1074
1075 if (test_bit(ATH12K_PCI_FLAG_IS_MSI_64, &ab_pci->flags)) {
1076 pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_HI,
1077 msi_addr_hi);
1078 } else {
1079 *msi_addr_hi = 0;
1080 }
1081}
1082
1083void ath12k_pci_get_ce_msi_idx(struct ath12k_base *ab, u32 ce_id,
1084 u32 *msi_idx)
1085{
1086 u32 i, msi_data_idx;
1087
1088 for (i = 0, msi_data_idx = 0; i < ab->hw_params->ce_count; i++) {
1089 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
1090 continue;
1091
1092 if (ce_id == i)
1093 break;
1094
1095 msi_data_idx++;
1096 }
1097 *msi_idx = msi_data_idx;
1098}
1099
1100void ath12k_pci_hif_ce_irq_enable(struct ath12k_base *ab)
1101{
1102 ath12k_pci_ce_irqs_enable(ab);
1103}
1104
1105void ath12k_pci_hif_ce_irq_disable(struct ath12k_base *ab)
1106{
1107 ath12k_pci_ce_irq_disable_sync(ab);
1108}
1109
1110void ath12k_pci_ext_irq_enable(struct ath12k_base *ab)
1111{
1112 int i;
1113
1114 for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX; i++) {
1115 struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
1116
1117 napi_enable(&irq_grp->napi);
1118 ath12k_pci_ext_grp_enable(irq_grp);
1119 }
1120
1121 set_bit(ATH12K_FLAG_EXT_IRQ_ENABLED, &ab->dev_flags);
1122}
1123
1124void ath12k_pci_ext_irq_disable(struct ath12k_base *ab)
1125{
1126 __ath12k_pci_ext_irq_disable(ab);
1127 ath12k_pci_sync_ext_irqs(ab);
1128}
1129
1130int ath12k_pci_hif_suspend(struct ath12k_base *ab)
1131{
1132 struct ath12k_pci *ar_pci = ath12k_pci_priv(ab);
1133
1134 ath12k_mhi_suspend(ar_pci);
1135
1136 return 0;
1137}
1138
1139int ath12k_pci_hif_resume(struct ath12k_base *ab)
1140{
1141 struct ath12k_pci *ar_pci = ath12k_pci_priv(ab);
1142
1143 ath12k_mhi_resume(ar_pci);
1144
1145 return 0;
1146}
1147
1148void ath12k_pci_stop(struct ath12k_base *ab)
1149{
1150 ath12k_pci_ce_irq_disable_sync(ab);
1151 ath12k_ce_cleanup_pipes(ab);
1152}
1153
1154int ath12k_pci_start(struct ath12k_base *ab)
1155{
1156 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);
1157
1158 set_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags);
1159
1160 if (test_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags))
1161 ath12k_pci_aspm_restore(ab_pci);
1162 else
1163 ath12k_info(ab, "leaving PCI ASPM disabled to avoid MHI M2 problems\n");
1164
1165 ath12k_pci_ce_irqs_enable(ab);
1166 ath12k_ce_rx_post_buf(ab);
1167
1168 return 0;
1169}
1170
1171u32 ath12k_pci_read32(struct ath12k_base *ab, u32 offset)
1172{
1173 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);
1174 u32 val, window_start;
1175 int ret = 0;
1176
1177 /* for offset beyond BAR + 4K - 32, may
1178 * need to wakeup MHI to access.
1179 */
1180 if (test_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags) &&
1181 offset >= ACCESS_ALWAYS_OFF && ab_pci->pci_ops->wakeup)
1182 ret = ab_pci->pci_ops->wakeup(ab);
1183
1184 if (offset < WINDOW_START) {
1185 val = ioread32(ab->mem + offset);
1186 } else {
1187 if (ab->static_window_map)
1188 window_start = ath12k_pci_get_window_start(ab, offset);
1189 else
1190 window_start = WINDOW_START;
1191
1192 if (window_start == WINDOW_START) {
1193 spin_lock_bh(&ab_pci->window_lock);
1194 ath12k_pci_select_window(ab_pci, offset);
1195
1196 if (ath12k_pci_is_offset_within_mhi_region(offset)) {
1197 offset = offset - PCI_MHIREGLEN_REG;
1198 val = ioread32(ab->mem +
1199 (offset & WINDOW_RANGE_MASK));
1200 } else {
1201 val = ioread32(ab->mem + window_start +
1202 (offset & WINDOW_RANGE_MASK));
1203 }
1204 spin_unlock_bh(&ab_pci->window_lock);
1205 } else {
1206 val = ioread32(ab->mem + window_start +
1207 (offset & WINDOW_RANGE_MASK));
1208 }
1209 }
1210
1211 if (test_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags) &&
1212 offset >= ACCESS_ALWAYS_OFF && ab_pci->pci_ops->release &&
1213 !ret)
1214 ab_pci->pci_ops->release(ab);
1215 return val;
1216}
1217
1218void ath12k_pci_write32(struct ath12k_base *ab, u32 offset, u32 value)
1219{
1220 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);
1221 u32 window_start;
1222 int ret = 0;
1223
1224 /* for offset beyond BAR + 4K - 32, may
1225 * need to wakeup MHI to access.
1226 */
1227 if (test_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags) &&
1228 offset >= ACCESS_ALWAYS_OFF && ab_pci->pci_ops->wakeup)
1229 ret = ab_pci->pci_ops->wakeup(ab);
1230
1231 if (offset < WINDOW_START) {
1232 iowrite32(value, ab->mem + offset);
1233 } else {
1234 if (ab->static_window_map)
1235 window_start = ath12k_pci_get_window_start(ab, offset);
1236 else
1237 window_start = WINDOW_START;
1238
1239 if (window_start == WINDOW_START) {
1240 spin_lock_bh(&ab_pci->window_lock);
1241 ath12k_pci_select_window(ab_pci, offset);
1242
1243 if (ath12k_pci_is_offset_within_mhi_region(offset)) {
1244 offset = offset - PCI_MHIREGLEN_REG;
1245 iowrite32(value, ab->mem +
1246 (offset & WINDOW_RANGE_MASK));
1247 } else {
1248 iowrite32(value, ab->mem + window_start +
1249 (offset & WINDOW_RANGE_MASK));
1250 }
1251 spin_unlock_bh(&ab_pci->window_lock);
1252 } else {
1253 iowrite32(value, ab->mem + window_start +
1254 (offset & WINDOW_RANGE_MASK));
1255 }
1256 }
1257
1258 if (test_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags) &&
1259 offset >= ACCESS_ALWAYS_OFF && ab_pci->pci_ops->release &&
1260 !ret)
1261 ab_pci->pci_ops->release(ab);
1262}
1263
1264#ifdef CONFIG_ATH12K_COREDUMP
1265static int ath12k_pci_coredump_calculate_size(struct ath12k_base *ab, u32 *dump_seg_sz)
1266{
1267 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);
1268 struct mhi_controller *mhi_ctrl = ab_pci->mhi_ctrl;
1269 struct image_info *rddm_img, *fw_img;
1270 struct ath12k_tlv_dump_data *dump_tlv;
1271 enum ath12k_fw_crash_dump_type mem_type;
1272 u32 len = 0, rddm_tlv_sz = 0, paging_tlv_sz = 0;
1273 struct ath12k_dump_file_data *file_data;
1274 int i;
1275
1276 rddm_img = mhi_ctrl->rddm_image;
1277 if (!rddm_img) {
1278 ath12k_err(ab, "No RDDM dump found\n");
1279 return 0;
1280 }
1281
1282 fw_img = mhi_ctrl->fbc_image;
1283
1284 for (i = 0; i < fw_img->entries ; i++) {
1285 if (!fw_img->mhi_buf[i].buf)
1286 continue;
1287
1288 paging_tlv_sz += fw_img->mhi_buf[i].len;
1289 }
1290 dump_seg_sz[FW_CRASH_DUMP_PAGING_DATA] = paging_tlv_sz;
1291
1292 for (i = 0; i < rddm_img->entries; i++) {
1293 if (!rddm_img->mhi_buf[i].buf)
1294 continue;
1295
1296 rddm_tlv_sz += rddm_img->mhi_buf[i].len;
1297 }
1298 dump_seg_sz[FW_CRASH_DUMP_RDDM_DATA] = rddm_tlv_sz;
1299
1300 for (i = 0; i < ab->qmi.mem_seg_count; i++) {
1301 mem_type = ath12k_coredump_get_dump_type(ab->qmi.target_mem[i].type);
1302
1303 if (mem_type == FW_CRASH_DUMP_NONE)
1304 continue;
1305
1306 if (mem_type == FW_CRASH_DUMP_TYPE_MAX) {
1307 ath12k_dbg(ab, ATH12K_DBG_PCI,
1308 "target mem region type %d not supported",
1309 ab->qmi.target_mem[i].type);
1310 continue;
1311 }
1312
1313 if (!ab->qmi.target_mem[i].paddr)
1314 continue;
1315
1316 dump_seg_sz[mem_type] += ab->qmi.target_mem[i].size;
1317 }
1318
1319 for (i = 0; i < FW_CRASH_DUMP_TYPE_MAX; i++) {
1320 if (!dump_seg_sz[i])
1321 continue;
1322
1323 len += sizeof(*dump_tlv) + dump_seg_sz[i];
1324 }
1325
1326 if (len)
1327 len += sizeof(*file_data);
1328
1329 return len;
1330}
1331
1332static void ath12k_pci_coredump_download(struct ath12k_base *ab)
1333{
1334 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);
1335 struct mhi_controller *mhi_ctrl = ab_pci->mhi_ctrl;
1336 struct image_info *rddm_img, *fw_img;
1337 struct timespec64 timestamp;
1338 int i, len, mem_idx;
1339 enum ath12k_fw_crash_dump_type mem_type;
1340 struct ath12k_dump_file_data *file_data;
1341 struct ath12k_tlv_dump_data *dump_tlv;
1342 size_t hdr_len = sizeof(*file_data);
1343 void *buf;
1344 u32 dump_seg_sz[FW_CRASH_DUMP_TYPE_MAX] = { 0 };
1345
1346 ath12k_mhi_coredump(mhi_ctrl, false);
1347
1348 len = ath12k_pci_coredump_calculate_size(ab, dump_seg_sz);
1349 if (!len) {
1350 ath12k_warn(ab, "No crash dump data found for devcoredump");
1351 return;
1352 }
1353
1354 rddm_img = mhi_ctrl->rddm_image;
1355 fw_img = mhi_ctrl->fbc_image;
1356
1357 /* dev_coredumpv() requires vmalloc data */
1358 buf = vzalloc(len);
1359 if (!buf)
1360 return;
1361
1362 ab->dump_data = buf;
1363 ab->ath12k_coredump_len = len;
1364 file_data = ab->dump_data;
1365 strscpy(file_data->df_magic, "ATH12K-FW-DUMP", sizeof(file_data->df_magic));
1366 file_data->len = cpu_to_le32(len);
1367 file_data->version = cpu_to_le32(ATH12K_FW_CRASH_DUMP_V2);
1368 file_data->chip_id = cpu_to_le32(ab_pci->dev_id);
1369 file_data->qrtr_id = cpu_to_le32(ab_pci->ab->qmi.service_ins_id);
1370 file_data->bus_id = cpu_to_le32(pci_domain_nr(ab_pci->pdev->bus));
1371 guid_gen(&file_data->guid);
1372 ktime_get_real_ts64(×tamp);
1373 file_data->tv_sec = cpu_to_le64(timestamp.tv_sec);
1374 file_data->tv_nsec = cpu_to_le64(timestamp.tv_nsec);
1375 buf += hdr_len;
1376 dump_tlv = buf;
1377 dump_tlv->type = cpu_to_le32(FW_CRASH_DUMP_PAGING_DATA);
1378 dump_tlv->tlv_len = cpu_to_le32(dump_seg_sz[FW_CRASH_DUMP_PAGING_DATA]);
1379 buf += COREDUMP_TLV_HDR_SIZE;
1380
1381 /* append all segments together as they are all part of a single contiguous
1382 * block of memory
1383 */
1384 for (i = 0; i < fw_img->entries ; i++) {
1385 if (!fw_img->mhi_buf[i].buf)
1386 continue;
1387
1388 memcpy_fromio(buf, (void const __iomem *)fw_img->mhi_buf[i].buf,
1389 fw_img->mhi_buf[i].len);
1390 buf += fw_img->mhi_buf[i].len;
1391 }
1392
1393 dump_tlv = buf;
1394 dump_tlv->type = cpu_to_le32(FW_CRASH_DUMP_RDDM_DATA);
1395 dump_tlv->tlv_len = cpu_to_le32(dump_seg_sz[FW_CRASH_DUMP_RDDM_DATA]);
1396 buf += COREDUMP_TLV_HDR_SIZE;
1397
1398 /* append all segments together as they are all part of a single contiguous
1399 * block of memory
1400 */
1401 for (i = 0; i < rddm_img->entries; i++) {
1402 if (!rddm_img->mhi_buf[i].buf)
1403 continue;
1404
1405 memcpy_fromio(buf, (void const __iomem *)rddm_img->mhi_buf[i].buf,
1406 rddm_img->mhi_buf[i].len);
1407 buf += rddm_img->mhi_buf[i].len;
1408 }
1409
1410 mem_idx = FW_CRASH_DUMP_REMOTE_MEM_DATA;
1411 for (; mem_idx < FW_CRASH_DUMP_TYPE_MAX; mem_idx++) {
1412 if (!dump_seg_sz[mem_idx] || mem_idx == FW_CRASH_DUMP_NONE)
1413 continue;
1414
1415 dump_tlv = buf;
1416 dump_tlv->type = cpu_to_le32(mem_idx);
1417 dump_tlv->tlv_len = cpu_to_le32(dump_seg_sz[mem_idx]);
1418 buf += COREDUMP_TLV_HDR_SIZE;
1419
1420 for (i = 0; i < ab->qmi.mem_seg_count; i++) {
1421 mem_type = ath12k_coredump_get_dump_type
1422 (ab->qmi.target_mem[i].type);
1423
1424 if (mem_type != mem_idx)
1425 continue;
1426
1427 if (!ab->qmi.target_mem[i].paddr) {
1428 ath12k_dbg(ab, ATH12K_DBG_PCI,
1429 "Skipping mem region type %d",
1430 ab->qmi.target_mem[i].type);
1431 continue;
1432 }
1433
1434 memcpy_fromio(buf, ab->qmi.target_mem[i].v.ioaddr,
1435 ab->qmi.target_mem[i].size);
1436 buf += ab->qmi.target_mem[i].size;
1437 }
1438 }
1439
1440 queue_work(ab->workqueue, &ab->dump_work);
1441}
1442#endif
1443
1444int ath12k_pci_power_up(struct ath12k_base *ab)
1445{
1446 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);
1447 int ret;
1448
1449 ab_pci->register_window = 0;
1450 clear_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags);
1451 ath12k_pci_sw_reset(ab_pci->ab, true);
1452
1453 /* Disable ASPM during firmware download due to problems switching
1454 * to AMSS state.
1455 */
1456 ath12k_pci_aspm_disable(ab_pci);
1457
1458 ath12k_pci_msi_enable(ab_pci);
1459
1460 if (test_bit(ATH12K_FW_FEATURE_MULTI_QRTR_ID, ab->fw.fw_features))
1461 ath12k_pci_update_qrtr_node_id(ab);
1462
1463 ret = ath12k_mhi_start(ab_pci);
1464 if (ret) {
1465 ath12k_err(ab, "failed to start mhi: %d\n", ret);
1466 return ret;
1467 }
1468
1469 if (ab->static_window_map)
1470 ath12k_pci_select_static_window(ab_pci);
1471
1472 return 0;
1473}
1474
1475void ath12k_pci_power_down(struct ath12k_base *ab, bool is_suspend)
1476{
1477 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);
1478
1479 /* restore aspm in case firmware bootup fails */
1480 ath12k_pci_aspm_restore(ab_pci);
1481
1482 ath12k_pci_force_wake(ab_pci->ab);
1483 ath12k_pci_msi_disable(ab_pci);
1484 ath12k_mhi_stop(ab_pci, is_suspend);
1485 clear_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags);
1486 ath12k_pci_sw_reset(ab_pci->ab, false);
1487}
1488
1489static int ath12k_pci_panic_handler(struct ath12k_base *ab)
1490{
1491 ath12k_pci_sw_reset(ab, false);
1492
1493 return NOTIFY_OK;
1494}
1495
1496static const struct ath12k_hif_ops ath12k_pci_hif_ops = {
1497 .start = ath12k_pci_start,
1498 .stop = ath12k_pci_stop,
1499 .read32 = ath12k_pci_read32,
1500 .write32 = ath12k_pci_write32,
1501 .power_down = ath12k_pci_power_down,
1502 .power_up = ath12k_pci_power_up,
1503 .suspend = ath12k_pci_hif_suspend,
1504 .resume = ath12k_pci_hif_resume,
1505 .irq_enable = ath12k_pci_ext_irq_enable,
1506 .irq_disable = ath12k_pci_ext_irq_disable,
1507 .get_msi_address = ath12k_pci_get_msi_address,
1508 .get_user_msi_vector = ath12k_pci_get_user_msi_assignment,
1509 .map_service_to_pipe = ath12k_pci_map_service_to_pipe,
1510 .ce_irq_enable = ath12k_pci_hif_ce_irq_enable,
1511 .ce_irq_disable = ath12k_pci_hif_ce_irq_disable,
1512 .get_ce_msi_idx = ath12k_pci_get_ce_msi_idx,
1513 .panic_handler = ath12k_pci_panic_handler,
1514#ifdef CONFIG_ATH12K_COREDUMP
1515 .coredump_download = ath12k_pci_coredump_download,
1516#endif
1517};
1518
1519static
1520void ath12k_pci_read_hw_version(struct ath12k_base *ab, u32 *major, u32 *minor)
1521{
1522 u32 soc_hw_version;
1523
1524 soc_hw_version = ath12k_pci_read32(ab, TCSR_SOC_HW_VERSION);
1525 *major = FIELD_GET(TCSR_SOC_HW_VERSION_MAJOR_MASK,
1526 soc_hw_version);
1527 *minor = FIELD_GET(TCSR_SOC_HW_VERSION_MINOR_MASK,
1528 soc_hw_version);
1529
1530 ath12k_dbg(ab, ATH12K_DBG_PCI,
1531 "pci tcsr_soc_hw_version major %d minor %d\n",
1532 *major, *minor);
1533}
1534
1535static int ath12k_pci_probe(struct pci_dev *pdev,
1536 const struct pci_device_id *pci_dev)
1537{
1538 struct ath12k_base *ab;
1539 struct ath12k_pci *ab_pci;
1540 u32 soc_hw_version_major, soc_hw_version_minor;
1541 int ret;
1542
1543 ab = ath12k_core_alloc(&pdev->dev, sizeof(*ab_pci), ATH12K_BUS_PCI);
1544 if (!ab) {
1545 dev_err(&pdev->dev, "failed to allocate ath12k base\n");
1546 return -ENOMEM;
1547 }
1548
1549 ab->dev = &pdev->dev;
1550 pci_set_drvdata(pdev, ab);
1551 ab_pci = ath12k_pci_priv(ab);
1552 ab_pci->dev_id = pci_dev->device;
1553 ab_pci->ab = ab;
1554 ab_pci->pdev = pdev;
1555 ab->hif.ops = &ath12k_pci_hif_ops;
1556 pci_set_drvdata(pdev, ab);
1557 spin_lock_init(&ab_pci->window_lock);
1558
1559 ret = ath12k_pci_claim(ab_pci, pdev);
1560 if (ret) {
1561 ath12k_err(ab, "failed to claim device: %d\n", ret);
1562 goto err_free_core;
1563 }
1564
1565 ath12k_dbg(ab, ATH12K_DBG_BOOT, "pci probe %04x:%04x %04x:%04x\n",
1566 pdev->vendor, pdev->device,
1567 pdev->subsystem_vendor, pdev->subsystem_device);
1568
1569 ab->id.vendor = pdev->vendor;
1570 ab->id.device = pdev->device;
1571 ab->id.subsystem_vendor = pdev->subsystem_vendor;
1572 ab->id.subsystem_device = pdev->subsystem_device;
1573
1574 switch (pci_dev->device) {
1575 case QCN9274_DEVICE_ID:
1576 ab_pci->msi_config = &ath12k_msi_config[0];
1577 ab->static_window_map = true;
1578 ab_pci->pci_ops = &ath12k_pci_ops_qcn9274;
1579 ab->hal_rx_ops = &hal_rx_qcn9274_ops;
1580 ath12k_pci_read_hw_version(ab, &soc_hw_version_major,
1581 &soc_hw_version_minor);
1582 switch (soc_hw_version_major) {
1583 case ATH12K_PCI_SOC_HW_VERSION_2:
1584 ab->hw_rev = ATH12K_HW_QCN9274_HW20;
1585 break;
1586 case ATH12K_PCI_SOC_HW_VERSION_1:
1587 ab->hw_rev = ATH12K_HW_QCN9274_HW10;
1588 break;
1589 default:
1590 dev_err(&pdev->dev,
1591 "Unknown hardware version found for QCN9274: 0x%x\n",
1592 soc_hw_version_major);
1593 ret = -EOPNOTSUPP;
1594 goto err_pci_free_region;
1595 }
1596 break;
1597 case WCN7850_DEVICE_ID:
1598 ab->id.bdf_search = ATH12K_BDF_SEARCH_BUS_AND_BOARD;
1599 ab_pci->msi_config = &ath12k_msi_config[0];
1600 ab->static_window_map = false;
1601 ab_pci->pci_ops = &ath12k_pci_ops_wcn7850;
1602 ab->hal_rx_ops = &hal_rx_wcn7850_ops;
1603 ath12k_pci_read_hw_version(ab, &soc_hw_version_major,
1604 &soc_hw_version_minor);
1605 switch (soc_hw_version_major) {
1606 case ATH12K_PCI_SOC_HW_VERSION_2:
1607 ab->hw_rev = ATH12K_HW_WCN7850_HW20;
1608 break;
1609 default:
1610 dev_err(&pdev->dev,
1611 "Unknown hardware version found for WCN7850: 0x%x\n",
1612 soc_hw_version_major);
1613 ret = -EOPNOTSUPP;
1614 goto err_pci_free_region;
1615 }
1616 break;
1617
1618 default:
1619 dev_err(&pdev->dev, "Unknown PCI device found: 0x%x\n",
1620 pci_dev->device);
1621 ret = -EOPNOTSUPP;
1622 goto err_pci_free_region;
1623 }
1624
1625 ret = ath12k_pci_msi_alloc(ab_pci);
1626 if (ret) {
1627 ath12k_err(ab, "failed to alloc msi: %d\n", ret);
1628 goto err_pci_free_region;
1629 }
1630
1631 ret = ath12k_core_pre_init(ab);
1632 if (ret)
1633 goto err_pci_msi_free;
1634
1635 ret = ath12k_pci_set_irq_affinity_hint(ab_pci, cpumask_of(0));
1636 if (ret) {
1637 ath12k_err(ab, "failed to set irq affinity %d\n", ret);
1638 goto err_pci_msi_free;
1639 }
1640
1641 ret = ath12k_mhi_register(ab_pci);
1642 if (ret) {
1643 ath12k_err(ab, "failed to register mhi: %d\n", ret);
1644 goto err_irq_affinity_cleanup;
1645 }
1646
1647 ret = ath12k_hal_srng_init(ab);
1648 if (ret)
1649 goto err_mhi_unregister;
1650
1651 ret = ath12k_ce_alloc_pipes(ab);
1652 if (ret) {
1653 ath12k_err(ab, "failed to allocate ce pipes: %d\n", ret);
1654 goto err_hal_srng_deinit;
1655 }
1656
1657 ath12k_pci_init_qmi_ce_config(ab);
1658
1659 ret = ath12k_pci_config_irq(ab);
1660 if (ret) {
1661 ath12k_err(ab, "failed to config irq: %d\n", ret);
1662 goto err_ce_free;
1663 }
1664
1665 /* kernel may allocate a dummy vector before request_irq and
1666 * then allocate a real vector when request_irq is called.
1667 * So get msi_data here again to avoid spurious interrupt
1668 * as msi_data will configured to srngs.
1669 */
1670 ret = ath12k_pci_config_msi_data(ab_pci);
1671 if (ret) {
1672 ath12k_err(ab, "failed to config msi_data: %d\n", ret);
1673 goto err_free_irq;
1674 }
1675
1676 ret = ath12k_core_init(ab);
1677 if (ret) {
1678 ath12k_err(ab, "failed to init core: %d\n", ret);
1679 goto err_free_irq;
1680 }
1681 return 0;
1682
1683err_free_irq:
1684 ath12k_pci_free_irq(ab);
1685
1686err_ce_free:
1687 ath12k_ce_free_pipes(ab);
1688
1689err_hal_srng_deinit:
1690 ath12k_hal_srng_deinit(ab);
1691
1692err_mhi_unregister:
1693 ath12k_mhi_unregister(ab_pci);
1694
1695err_pci_msi_free:
1696 ath12k_pci_msi_free(ab_pci);
1697
1698err_irq_affinity_cleanup:
1699 ath12k_pci_set_irq_affinity_hint(ab_pci, NULL);
1700
1701err_pci_free_region:
1702 ath12k_pci_free_region(ab_pci);
1703
1704err_free_core:
1705 ath12k_core_free(ab);
1706
1707 return ret;
1708}
1709
1710static void ath12k_pci_remove(struct pci_dev *pdev)
1711{
1712 struct ath12k_base *ab = pci_get_drvdata(pdev);
1713 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);
1714
1715 ath12k_pci_set_irq_affinity_hint(ab_pci, NULL);
1716
1717 if (test_bit(ATH12K_FLAG_QMI_FAIL, &ab->dev_flags)) {
1718 ath12k_pci_power_down(ab, false);
1719 ath12k_qmi_deinit_service(ab);
1720 goto qmi_fail;
1721 }
1722
1723 set_bit(ATH12K_FLAG_UNREGISTERING, &ab->dev_flags);
1724
1725 cancel_work_sync(&ab->reset_work);
1726 cancel_work_sync(&ab->dump_work);
1727 ath12k_core_deinit(ab);
1728
1729qmi_fail:
1730 ath12k_mhi_unregister(ab_pci);
1731
1732 ath12k_pci_free_irq(ab);
1733 ath12k_pci_msi_free(ab_pci);
1734 ath12k_pci_free_region(ab_pci);
1735
1736 ath12k_hal_srng_deinit(ab);
1737 ath12k_ce_free_pipes(ab);
1738 ath12k_core_free(ab);
1739}
1740
1741static void ath12k_pci_shutdown(struct pci_dev *pdev)
1742{
1743 struct ath12k_base *ab = pci_get_drvdata(pdev);
1744 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);
1745
1746 ath12k_pci_set_irq_affinity_hint(ab_pci, NULL);
1747 ath12k_pci_power_down(ab, false);
1748}
1749
1750static __maybe_unused int ath12k_pci_pm_suspend(struct device *dev)
1751{
1752 struct ath12k_base *ab = dev_get_drvdata(dev);
1753 int ret;
1754
1755 ret = ath12k_core_suspend(ab);
1756 if (ret)
1757 ath12k_warn(ab, "failed to suspend core: %d\n", ret);
1758
1759 return ret;
1760}
1761
1762static __maybe_unused int ath12k_pci_pm_resume(struct device *dev)
1763{
1764 struct ath12k_base *ab = dev_get_drvdata(dev);
1765 int ret;
1766
1767 ret = ath12k_core_resume(ab);
1768 if (ret)
1769 ath12k_warn(ab, "failed to resume core: %d\n", ret);
1770
1771 return ret;
1772}
1773
1774static __maybe_unused int ath12k_pci_pm_suspend_late(struct device *dev)
1775{
1776 struct ath12k_base *ab = dev_get_drvdata(dev);
1777 int ret;
1778
1779 ret = ath12k_core_suspend_late(ab);
1780 if (ret)
1781 ath12k_warn(ab, "failed to late suspend core: %d\n", ret);
1782
1783 return ret;
1784}
1785
1786static __maybe_unused int ath12k_pci_pm_resume_early(struct device *dev)
1787{
1788 struct ath12k_base *ab = dev_get_drvdata(dev);
1789 int ret;
1790
1791 ret = ath12k_core_resume_early(ab);
1792 if (ret)
1793 ath12k_warn(ab, "failed to early resume core: %d\n", ret);
1794
1795 return ret;
1796}
1797
1798static const struct dev_pm_ops __maybe_unused ath12k_pci_pm_ops = {
1799 SET_SYSTEM_SLEEP_PM_OPS(ath12k_pci_pm_suspend,
1800 ath12k_pci_pm_resume)
1801 SET_LATE_SYSTEM_SLEEP_PM_OPS(ath12k_pci_pm_suspend_late,
1802 ath12k_pci_pm_resume_early)
1803};
1804
1805static struct pci_driver ath12k_pci_driver = {
1806 .name = "ath12k_pci",
1807 .id_table = ath12k_pci_id_table,
1808 .probe = ath12k_pci_probe,
1809 .remove = ath12k_pci_remove,
1810 .shutdown = ath12k_pci_shutdown,
1811 .driver.pm = &ath12k_pci_pm_ops,
1812};
1813
1814static int ath12k_pci_init(void)
1815{
1816 int ret;
1817
1818 ret = pci_register_driver(&ath12k_pci_driver);
1819 if (ret) {
1820 pr_err("failed to register ath12k pci driver: %d\n",
1821 ret);
1822 return ret;
1823 }
1824
1825 return 0;
1826}
1827module_init(ath12k_pci_init);
1828
1829static void ath12k_pci_exit(void)
1830{
1831 pci_unregister_driver(&ath12k_pci_driver);
1832}
1833
1834module_exit(ath12k_pci_exit);
1835
1836MODULE_DESCRIPTION("Driver support for Qualcomm Technologies PCIe 802.11be WLAN devices");
1837MODULE_LICENSE("Dual BSD/GPL");