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1// SPDX-License-Identifier: GPL-2.0
2/* Copyright(c) 1999 - 2018 Intel Corporation. */
3
4#include <linux/pci.h>
5#include <linux/delay.h>
6#include <linux/sched.h>
7
8#include "ixgbe.h"
9#include "ixgbe_mbx.h"
10#include "ixgbe_phy.h"
11#include "ixgbe_x540.h"
12
13#define IXGBE_X540_MAX_TX_QUEUES 128
14#define IXGBE_X540_MAX_RX_QUEUES 128
15#define IXGBE_X540_RAR_ENTRIES 128
16#define IXGBE_X540_MC_TBL_SIZE 128
17#define IXGBE_X540_VFT_TBL_SIZE 128
18#define IXGBE_X540_RX_PB_SIZE 384
19
20static int ixgbe_update_flash_X540(struct ixgbe_hw *hw);
21static int ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw);
22static int ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw);
23static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw);
24
25enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw)
26{
27 return ixgbe_media_type_copper;
28}
29
30int ixgbe_get_invariants_X540(struct ixgbe_hw *hw)
31{
32 struct ixgbe_mac_info *mac = &hw->mac;
33 struct ixgbe_phy_info *phy = &hw->phy;
34
35 /* set_phy_power was set by default to NULL */
36 phy->ops.set_phy_power = ixgbe_set_copper_phy_power;
37
38 mac->mcft_size = IXGBE_X540_MC_TBL_SIZE;
39 mac->vft_size = IXGBE_X540_VFT_TBL_SIZE;
40 mac->num_rar_entries = IXGBE_X540_RAR_ENTRIES;
41 mac->rx_pb_size = IXGBE_X540_RX_PB_SIZE;
42 mac->max_rx_queues = IXGBE_X540_MAX_RX_QUEUES;
43 mac->max_tx_queues = IXGBE_X540_MAX_TX_QUEUES;
44 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
45
46 return 0;
47}
48
49/**
50 * ixgbe_setup_mac_link_X540 - Set the auto advertised capabilitires
51 * @hw: pointer to hardware structure
52 * @speed: new link speed
53 * @autoneg_wait_to_complete: true when waiting for completion is needed
54 **/
55int ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw, ixgbe_link_speed speed,
56 bool autoneg_wait_to_complete)
57{
58 return hw->phy.ops.setup_link_speed(hw, speed,
59 autoneg_wait_to_complete);
60}
61
62/**
63 * ixgbe_reset_hw_X540 - Perform hardware reset
64 * @hw: pointer to hardware structure
65 *
66 * Resets the hardware by resetting the transmit and receive units, masks
67 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
68 * reset.
69 **/
70int ixgbe_reset_hw_X540(struct ixgbe_hw *hw)
71{
72 u32 swfw_mask = hw->phy.phy_semaphore_mask;
73 u32 ctrl, i;
74 int status;
75
76 /* Call adapter stop to disable tx/rx and clear interrupts */
77 status = hw->mac.ops.stop_adapter(hw);
78 if (status)
79 return status;
80
81 /* flush pending Tx transactions */
82 ixgbe_clear_tx_pending(hw);
83
84mac_reset_top:
85 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
86 if (status) {
87 hw_dbg(hw, "semaphore failed with %d", status);
88 return -EBUSY;
89 }
90
91 ctrl = IXGBE_CTRL_RST;
92 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
93 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
94 IXGBE_WRITE_FLUSH(hw);
95 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
96 usleep_range(1000, 1200);
97
98 /* Poll for reset bit to self-clear indicating reset is complete */
99 for (i = 0; i < 10; i++) {
100 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
101 if (!(ctrl & IXGBE_CTRL_RST_MASK))
102 break;
103 udelay(1);
104 }
105
106 if (ctrl & IXGBE_CTRL_RST_MASK) {
107 status = -EIO;
108 hw_dbg(hw, "Reset polling failed to complete.\n");
109 }
110 msleep(100);
111
112 /*
113 * Double resets are required for recovery from certain error
114 * conditions. Between resets, it is necessary to stall to allow time
115 * for any pending HW events to complete.
116 */
117 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
118 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
119 goto mac_reset_top;
120 }
121
122 /* Set the Rx packet buffer size. */
123 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT);
124
125 /* Store the permanent mac address */
126 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
127
128 /*
129 * Store MAC address from RAR0, clear receive address registers, and
130 * clear the multicast table. Also reset num_rar_entries to 128,
131 * since we modify this value when programming the SAN MAC address.
132 */
133 hw->mac.num_rar_entries = IXGBE_X540_MAX_TX_QUEUES;
134 hw->mac.ops.init_rx_addrs(hw);
135
136 /* Store the permanent SAN mac address */
137 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
138
139 /* Add the SAN MAC address to the RAR only if it's a valid address */
140 if (is_valid_ether_addr(hw->mac.san_addr)) {
141 /* Save the SAN MAC RAR index */
142 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
143
144 hw->mac.ops.set_rar(hw, hw->mac.san_mac_rar_index,
145 hw->mac.san_addr, 0, IXGBE_RAH_AV);
146
147 /* clear VMDq pool/queue selection for this RAR */
148 hw->mac.ops.clear_vmdq(hw, hw->mac.san_mac_rar_index,
149 IXGBE_CLEAR_VMDQ_ALL);
150
151 /* Reserve the last RAR for the SAN MAC address */
152 hw->mac.num_rar_entries--;
153 }
154
155 /* Store the alternative WWNN/WWPN prefix */
156 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
157 &hw->mac.wwpn_prefix);
158
159 return status;
160}
161
162/**
163 * ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx
164 * @hw: pointer to hardware structure
165 *
166 * Starts the hardware using the generic start_hw function
167 * and the generation start_hw function.
168 * Then performs revision-specific operations, if any.
169 **/
170int ixgbe_start_hw_X540(struct ixgbe_hw *hw)
171{
172 int ret_val;
173
174 ret_val = ixgbe_start_hw_generic(hw);
175 if (ret_val)
176 return ret_val;
177
178 return ixgbe_start_hw_gen2(hw);
179}
180
181/**
182 * ixgbe_init_eeprom_params_X540 - Initialize EEPROM params
183 * @hw: pointer to hardware structure
184 *
185 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
186 * ixgbe_hw struct in order to set up EEPROM access.
187 **/
188int ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw)
189{
190 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
191
192 if (eeprom->type == ixgbe_eeprom_uninitialized) {
193 u16 eeprom_size;
194 u32 eec;
195
196 eeprom->semaphore_delay = 10;
197 eeprom->type = ixgbe_flash;
198
199 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
200 eeprom_size = FIELD_GET(IXGBE_EEC_SIZE, eec);
201 eeprom->word_size = BIT(eeprom_size +
202 IXGBE_EEPROM_WORD_SIZE_SHIFT);
203
204 hw_dbg(hw, "Eeprom params: type = %d, size = %d\n",
205 eeprom->type, eeprom->word_size);
206 }
207
208 return 0;
209}
210
211/**
212 * ixgbe_read_eerd_X540- Read EEPROM word using EERD
213 * @hw: pointer to hardware structure
214 * @offset: offset of word in the EEPROM to read
215 * @data: word read from the EEPROM
216 *
217 * Reads a 16 bit word from the EEPROM using the EERD register.
218 **/
219static int ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data)
220{
221 int status;
222
223 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
224 return -EBUSY;
225
226 status = ixgbe_read_eerd_generic(hw, offset, data);
227
228 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
229 return status;
230}
231
232/**
233 * ixgbe_read_eerd_buffer_X540 - Read EEPROM word(s) using EERD
234 * @hw: pointer to hardware structure
235 * @offset: offset of word in the EEPROM to read
236 * @words: number of words
237 * @data: word(s) read from the EEPROM
238 *
239 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
240 **/
241static int ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw,
242 u16 offset, u16 words, u16 *data)
243{
244 int status;
245
246 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
247 return -EBUSY;
248
249 status = ixgbe_read_eerd_buffer_generic(hw, offset, words, data);
250
251 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
252 return status;
253}
254
255/**
256 * ixgbe_write_eewr_X540 - Write EEPROM word using EEWR
257 * @hw: pointer to hardware structure
258 * @offset: offset of word in the EEPROM to write
259 * @data: word write to the EEPROM
260 *
261 * Write a 16 bit word to the EEPROM using the EEWR register.
262 **/
263static int ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data)
264{
265 int status;
266
267 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
268 return -EBUSY;
269
270 status = ixgbe_write_eewr_generic(hw, offset, data);
271
272 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
273 return status;
274}
275
276/**
277 * ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR
278 * @hw: pointer to hardware structure
279 * @offset: offset of word in the EEPROM to write
280 * @words: number of words
281 * @data: word(s) write to the EEPROM
282 *
283 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
284 **/
285static int ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw,
286 u16 offset, u16 words, u16 *data)
287{
288 int status;
289
290 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
291 return -EBUSY;
292
293 status = ixgbe_write_eewr_buffer_generic(hw, offset, words, data);
294
295 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
296 return status;
297}
298
299/**
300 * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum
301 *
302 * This function does not use synchronization for EERD and EEWR. It can
303 * be used internally by function which utilize ixgbe_acquire_swfw_sync_X540.
304 *
305 * @hw: pointer to hardware structure
306 **/
307static int ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)
308{
309 u16 i;
310 u16 j;
311 u16 checksum = 0;
312 u16 length = 0;
313 u16 pointer = 0;
314 u16 word = 0;
315 u16 checksum_last_word = IXGBE_EEPROM_CHECKSUM;
316 u16 ptr_start = IXGBE_PCIE_ANALOG_PTR;
317
318 /*
319 * Do not use hw->eeprom.ops.read because we do not want to take
320 * the synchronization semaphores here. Instead use
321 * ixgbe_read_eerd_generic
322 */
323
324 /* Include 0x0-0x3F in the checksum */
325 for (i = 0; i < checksum_last_word; i++) {
326 if (ixgbe_read_eerd_generic(hw, i, &word)) {
327 hw_dbg(hw, "EEPROM read failed\n");
328 return -EIO;
329 }
330 checksum += word;
331 }
332
333 /*
334 * Include all data from pointers 0x3, 0x6-0xE. This excludes the
335 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
336 */
337 for (i = ptr_start; i < IXGBE_FW_PTR; i++) {
338 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
339 continue;
340
341 if (ixgbe_read_eerd_generic(hw, i, &pointer)) {
342 hw_dbg(hw, "EEPROM read failed\n");
343 break;
344 }
345
346 /* Skip pointer section if the pointer is invalid. */
347 if (pointer == 0xFFFF || pointer == 0 ||
348 pointer >= hw->eeprom.word_size)
349 continue;
350
351 if (ixgbe_read_eerd_generic(hw, pointer, &length)) {
352 hw_dbg(hw, "EEPROM read failed\n");
353 return -EIO;
354 }
355
356 /* Skip pointer section if length is invalid. */
357 if (length == 0xFFFF || length == 0 ||
358 (pointer + length) >= hw->eeprom.word_size)
359 continue;
360
361 for (j = pointer + 1; j <= pointer + length; j++) {
362 if (ixgbe_read_eerd_generic(hw, j, &word)) {
363 hw_dbg(hw, "EEPROM read failed\n");
364 return -EIO;
365 }
366 checksum += word;
367 }
368 }
369
370 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
371
372 return (int)checksum;
373}
374
375/**
376 * ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum
377 * @hw: pointer to hardware structure
378 * @checksum_val: calculated checksum
379 *
380 * Performs checksum calculation and validates the EEPROM checksum. If the
381 * caller does not need checksum_val, the value can be NULL.
382 **/
383static int ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw,
384 u16 *checksum_val)
385{
386 u16 read_checksum = 0;
387 u16 checksum;
388 int status;
389
390 /* Read the first word from the EEPROM. If this times out or fails, do
391 * not continue or we could be in for a very long wait while every
392 * EEPROM read fails
393 */
394 status = hw->eeprom.ops.read(hw, 0, &checksum);
395 if (status) {
396 hw_dbg(hw, "EEPROM read failed\n");
397 return status;
398 }
399
400 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
401 return -EBUSY;
402
403 status = hw->eeprom.ops.calc_checksum(hw);
404 if (status < 0)
405 goto out;
406
407 checksum = (u16)(status & 0xffff);
408
409 /* Do not use hw->eeprom.ops.read because we do not want to take
410 * the synchronization semaphores twice here.
411 */
412 status = ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM,
413 &read_checksum);
414 if (status)
415 goto out;
416
417 /* Verify read checksum from EEPROM is the same as
418 * calculated checksum
419 */
420 if (read_checksum != checksum) {
421 hw_dbg(hw, "Invalid EEPROM checksum");
422 status = -EIO;
423 }
424
425 /* If the user cares, return the calculated checksum */
426 if (checksum_val)
427 *checksum_val = checksum;
428
429out:
430 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
431
432 return status;
433}
434
435/**
436 * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash
437 * @hw: pointer to hardware structure
438 *
439 * After writing EEPROM to shadow RAM using EEWR register, software calculates
440 * checksum and updates the EEPROM and instructs the hardware to update
441 * the flash.
442 **/
443static int ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw)
444{
445 u16 checksum;
446 int status;
447
448 /* Read the first word from the EEPROM. If this times out or fails, do
449 * not continue or we could be in for a very long wait while every
450 * EEPROM read fails
451 */
452 status = hw->eeprom.ops.read(hw, 0, &checksum);
453 if (status) {
454 hw_dbg(hw, "EEPROM read failed\n");
455 return status;
456 }
457
458 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
459 return -EBUSY;
460
461 status = hw->eeprom.ops.calc_checksum(hw);
462 if (status < 0)
463 goto out;
464
465 checksum = (u16)(status & 0xffff);
466
467 /* Do not use hw->eeprom.ops.write because we do not want to
468 * take the synchronization semaphores twice here.
469 */
470 status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM, checksum);
471 if (status)
472 goto out;
473
474 status = ixgbe_update_flash_X540(hw);
475
476out:
477 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
478 return status;
479}
480
481/**
482 * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device
483 * @hw: pointer to hardware structure
484 *
485 * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy
486 * EEPROM from shadow RAM to the flash device.
487 **/
488static int ixgbe_update_flash_X540(struct ixgbe_hw *hw)
489{
490 int status;
491 u32 flup;
492
493 status = ixgbe_poll_flash_update_done_X540(hw);
494 if (status == -EIO) {
495 hw_dbg(hw, "Flash update time out\n");
496 return status;
497 }
498
499 flup = IXGBE_READ_REG(hw, IXGBE_EEC(hw)) | IXGBE_EEC_FLUP;
500 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), flup);
501
502 status = ixgbe_poll_flash_update_done_X540(hw);
503 if (status == 0)
504 hw_dbg(hw, "Flash update complete\n");
505 else
506 hw_dbg(hw, "Flash update time out\n");
507
508 if (hw->revision_id == 0) {
509 flup = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
510
511 if (flup & IXGBE_EEC_SEC1VAL) {
512 flup |= IXGBE_EEC_FLUP;
513 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), flup);
514 }
515
516 status = ixgbe_poll_flash_update_done_X540(hw);
517 if (status == 0)
518 hw_dbg(hw, "Flash update complete\n");
519 else
520 hw_dbg(hw, "Flash update time out\n");
521 }
522
523 return status;
524}
525
526/**
527 * ixgbe_poll_flash_update_done_X540 - Poll flash update status
528 * @hw: pointer to hardware structure
529 *
530 * Polls the FLUDONE (bit 26) of the EEC Register to determine when the
531 * flash update is done.
532 **/
533static int ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw)
534{
535 u32 i;
536 u32 reg;
537
538 for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) {
539 reg = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
540 if (reg & IXGBE_EEC_FLUDONE)
541 return 0;
542 udelay(5);
543 }
544 return -EIO;
545}
546
547/**
548 * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore
549 * @hw: pointer to hardware structure
550 * @mask: Mask to specify which semaphore to acquire
551 *
552 * Acquires the SWFW semaphore thought the SW_FW_SYNC register for
553 * the specified function (CSR, PHY0, PHY1, NVM, Flash)
554 **/
555int ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
556{
557 u32 swmask = mask & IXGBE_GSSR_NVM_PHY_MASK;
558 u32 swi2c_mask = mask & IXGBE_GSSR_I2C_MASK;
559 u32 fwmask = swmask << 5;
560 u32 timeout = 200;
561 u32 hwmask = 0;
562 u32 swfw_sync;
563 u32 i;
564
565 if (swmask & IXGBE_GSSR_EEP_SM)
566 hwmask = IXGBE_GSSR_FLASH_SM;
567
568 /* SW only mask does not have FW bit pair */
569 if (mask & IXGBE_GSSR_SW_MNG_SM)
570 swmask |= IXGBE_GSSR_SW_MNG_SM;
571
572 swmask |= swi2c_mask;
573 fwmask |= swi2c_mask << 2;
574 for (i = 0; i < timeout; i++) {
575 /* SW NVM semaphore bit is used for access to all
576 * SW_FW_SYNC bits (not just NVM)
577 */
578 if (ixgbe_get_swfw_sync_semaphore(hw))
579 return -EBUSY;
580
581 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw));
582 if (!(swfw_sync & (fwmask | swmask | hwmask))) {
583 swfw_sync |= swmask;
584 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC(hw), swfw_sync);
585 ixgbe_release_swfw_sync_semaphore(hw);
586 usleep_range(5000, 6000);
587 return 0;
588 }
589 /* Firmware currently using resource (fwmask), hardware
590 * currently using resource (hwmask), or other software
591 * thread currently using resource (swmask)
592 */
593 ixgbe_release_swfw_sync_semaphore(hw);
594 usleep_range(5000, 10000);
595 }
596
597 /* If the resource is not released by the FW/HW the SW can assume that
598 * the FW/HW malfunctions. In that case the SW should set the SW bit(s)
599 * of the requested resource(s) while ignoring the corresponding FW/HW
600 * bits in the SW_FW_SYNC register.
601 */
602 if (ixgbe_get_swfw_sync_semaphore(hw))
603 return -EBUSY;
604 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw));
605 if (swfw_sync & (fwmask | hwmask)) {
606 swfw_sync |= swmask;
607 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC(hw), swfw_sync);
608 ixgbe_release_swfw_sync_semaphore(hw);
609 usleep_range(5000, 6000);
610 return 0;
611 }
612 /* If the resource is not released by other SW the SW can assume that
613 * the other SW malfunctions. In that case the SW should clear all SW
614 * flags that it does not own and then repeat the whole process once
615 * again.
616 */
617 if (swfw_sync & swmask) {
618 u32 rmask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_PHY0_SM |
619 IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_MAC_CSR_SM |
620 IXGBE_GSSR_SW_MNG_SM;
621
622 if (swi2c_mask)
623 rmask |= IXGBE_GSSR_I2C_MASK;
624 ixgbe_release_swfw_sync_X540(hw, rmask);
625 ixgbe_release_swfw_sync_semaphore(hw);
626 return -EBUSY;
627 }
628 ixgbe_release_swfw_sync_semaphore(hw);
629
630 return -EBUSY;
631}
632
633/**
634 * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore
635 * @hw: pointer to hardware structure
636 * @mask: Mask to specify which semaphore to release
637 *
638 * Releases the SWFW semaphore through the SW_FW_SYNC register
639 * for the specified function (CSR, PHY0, PHY1, EVM, Flash)
640 **/
641void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
642{
643 u32 swmask = mask & (IXGBE_GSSR_NVM_PHY_MASK | IXGBE_GSSR_SW_MNG_SM);
644 u32 swfw_sync;
645
646 if (mask & IXGBE_GSSR_I2C_MASK)
647 swmask |= mask & IXGBE_GSSR_I2C_MASK;
648 ixgbe_get_swfw_sync_semaphore(hw);
649
650 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw));
651 swfw_sync &= ~swmask;
652 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC(hw), swfw_sync);
653
654 ixgbe_release_swfw_sync_semaphore(hw);
655 usleep_range(5000, 6000);
656}
657
658/**
659 * ixgbe_get_swfw_sync_semaphore - Get hardware semaphore
660 * @hw: pointer to hardware structure
661 *
662 * Sets the hardware semaphores so SW/FW can gain control of shared resources
663 */
664static int ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw)
665{
666 u32 timeout = 2000;
667 u32 i;
668 u32 swsm;
669
670 /* Get SMBI software semaphore between device drivers first */
671 for (i = 0; i < timeout; i++) {
672 /* If the SMBI bit is 0 when we read it, then the bit will be
673 * set and we have the semaphore
674 */
675 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));
676 if (!(swsm & IXGBE_SWSM_SMBI))
677 break;
678 usleep_range(50, 100);
679 }
680
681 if (i == timeout) {
682 hw_dbg(hw,
683 "Software semaphore SMBI between device drivers not granted.\n");
684 return -EIO;
685 }
686
687 /* Now get the semaphore between SW/FW through the REGSMP bit */
688 for (i = 0; i < timeout; i++) {
689 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw));
690 if (!(swsm & IXGBE_SWFW_REGSMP))
691 return 0;
692
693 usleep_range(50, 100);
694 }
695
696 /* Release semaphores and return error if SW NVM semaphore
697 * was not granted because we do not have access to the EEPROM
698 */
699 hw_dbg(hw, "REGSMP Software NVM semaphore not granted\n");
700 ixgbe_release_swfw_sync_semaphore(hw);
701 return -EIO;
702}
703
704/**
705 * ixgbe_release_swfw_sync_semaphore - Release hardware semaphore
706 * @hw: pointer to hardware structure
707 *
708 * This function clears hardware semaphore bits.
709 **/
710static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw)
711{
712 u32 swsm;
713
714 /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */
715
716 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw));
717 swsm &= ~IXGBE_SWFW_REGSMP;
718 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC(hw), swsm);
719
720 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));
721 swsm &= ~IXGBE_SWSM_SMBI;
722 IXGBE_WRITE_REG(hw, IXGBE_SWSM(hw), swsm);
723
724 IXGBE_WRITE_FLUSH(hw);
725}
726
727/**
728 * ixgbe_init_swfw_sync_X540 - Release hardware semaphore
729 * @hw: pointer to hardware structure
730 *
731 * This function reset hardware semaphore bits for a semaphore that may
732 * have be left locked due to a catastrophic failure.
733 **/
734void ixgbe_init_swfw_sync_X540(struct ixgbe_hw *hw)
735{
736 u32 rmask;
737
738 /* First try to grab the semaphore but we don't need to bother
739 * looking to see whether we got the lock or not since we do
740 * the same thing regardless of whether we got the lock or not.
741 * We got the lock - we release it.
742 * We timeout trying to get the lock - we force its release.
743 */
744 ixgbe_get_swfw_sync_semaphore(hw);
745 ixgbe_release_swfw_sync_semaphore(hw);
746
747 /* Acquire and release all software resources. */
748 rmask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_PHY0_SM |
749 IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_MAC_CSR_SM |
750 IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_I2C_MASK;
751
752 ixgbe_acquire_swfw_sync_X540(hw, rmask);
753 ixgbe_release_swfw_sync_X540(hw, rmask);
754}
755
756/**
757 * ixgbe_blink_led_start_X540 - Blink LED based on index.
758 * @hw: pointer to hardware structure
759 * @index: led number to blink
760 *
761 * Devices that implement the version 2 interface:
762 * X540
763 **/
764int ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index)
765{
766 u32 macc_reg;
767 u32 ledctl_reg;
768 ixgbe_link_speed speed;
769 bool link_up;
770
771 if (index > 3)
772 return -EINVAL;
773
774 /* Link should be up in order for the blink bit in the LED control
775 * register to work. Force link and speed in the MAC if link is down.
776 * This will be reversed when we stop the blinking.
777 */
778 hw->mac.ops.check_link(hw, &speed, &link_up, false);
779 if (!link_up) {
780 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
781 macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS;
782 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
783 }
784 /* Set the LED to LINK_UP + BLINK. */
785 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
786 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
787 ledctl_reg |= IXGBE_LED_BLINK(index);
788 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
789 IXGBE_WRITE_FLUSH(hw);
790
791 return 0;
792}
793
794/**
795 * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index.
796 * @hw: pointer to hardware structure
797 * @index: led number to stop blinking
798 *
799 * Devices that implement the version 2 interface:
800 * X540
801 **/
802int ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index)
803{
804 u32 macc_reg;
805 u32 ledctl_reg;
806
807 if (index > 3)
808 return -EINVAL;
809
810 /* Restore the LED to its default value. */
811 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
812 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
813 ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
814 ledctl_reg &= ~IXGBE_LED_BLINK(index);
815 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
816
817 /* Unforce link and speed in the MAC. */
818 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
819 macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS);
820 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
821 IXGBE_WRITE_FLUSH(hw);
822
823 return 0;
824}
825static const struct ixgbe_mac_operations mac_ops_X540 = {
826 .init_hw = &ixgbe_init_hw_generic,
827 .reset_hw = &ixgbe_reset_hw_X540,
828 .start_hw = &ixgbe_start_hw_X540,
829 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
830 .get_media_type = &ixgbe_get_media_type_X540,
831 .enable_rx_dma = &ixgbe_enable_rx_dma_generic,
832 .get_mac_addr = &ixgbe_get_mac_addr_generic,
833 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic,
834 .get_device_caps = &ixgbe_get_device_caps_generic,
835 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic,
836 .stop_adapter = &ixgbe_stop_adapter_generic,
837 .get_bus_info = &ixgbe_get_bus_info_generic,
838 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
839 .read_analog_reg8 = NULL,
840 .write_analog_reg8 = NULL,
841 .setup_link = &ixgbe_setup_mac_link_X540,
842 .set_rxpba = &ixgbe_set_rxpba_generic,
843 .check_link = &ixgbe_check_mac_link_generic,
844 .get_link_capabilities = &ixgbe_get_copper_link_capabilities_generic,
845 .led_on = &ixgbe_led_on_generic,
846 .led_off = &ixgbe_led_off_generic,
847 .init_led_link_act = ixgbe_init_led_link_act_generic,
848 .blink_led_start = &ixgbe_blink_led_start_X540,
849 .blink_led_stop = &ixgbe_blink_led_stop_X540,
850 .set_rar = &ixgbe_set_rar_generic,
851 .clear_rar = &ixgbe_clear_rar_generic,
852 .set_vmdq = &ixgbe_set_vmdq_generic,
853 .set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic,
854 .clear_vmdq = &ixgbe_clear_vmdq_generic,
855 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
856 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
857 .enable_mc = &ixgbe_enable_mc_generic,
858 .disable_mc = &ixgbe_disable_mc_generic,
859 .clear_vfta = &ixgbe_clear_vfta_generic,
860 .set_vfta = &ixgbe_set_vfta_generic,
861 .fc_enable = &ixgbe_fc_enable_generic,
862 .setup_fc = ixgbe_setup_fc_generic,
863 .fc_autoneg = ixgbe_fc_autoneg,
864 .set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic,
865 .init_uta_tables = &ixgbe_init_uta_tables_generic,
866 .setup_sfp = NULL,
867 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing,
868 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing,
869 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540,
870 .release_swfw_sync = &ixgbe_release_swfw_sync_X540,
871 .init_swfw_sync = &ixgbe_init_swfw_sync_X540,
872 .disable_rx_buff = &ixgbe_disable_rx_buff_generic,
873 .enable_rx_buff = &ixgbe_enable_rx_buff_generic,
874 .get_thermal_sensor_data = NULL,
875 .init_thermal_sensor_thresh = NULL,
876 .prot_autoc_read = &prot_autoc_read_generic,
877 .prot_autoc_write = &prot_autoc_write_generic,
878 .enable_rx = &ixgbe_enable_rx_generic,
879 .disable_rx = &ixgbe_disable_rx_generic,
880};
881
882static const struct ixgbe_eeprom_operations eeprom_ops_X540 = {
883 .init_params = &ixgbe_init_eeprom_params_X540,
884 .read = &ixgbe_read_eerd_X540,
885 .read_buffer = &ixgbe_read_eerd_buffer_X540,
886 .write = &ixgbe_write_eewr_X540,
887 .write_buffer = &ixgbe_write_eewr_buffer_X540,
888 .calc_checksum = &ixgbe_calc_eeprom_checksum_X540,
889 .validate_checksum = &ixgbe_validate_eeprom_checksum_X540,
890 .update_checksum = &ixgbe_update_eeprom_checksum_X540,
891};
892
893static const struct ixgbe_phy_operations phy_ops_X540 = {
894 .identify = &ixgbe_identify_phy_generic,
895 .identify_sfp = &ixgbe_identify_sfp_module_generic,
896 .init = NULL,
897 .reset = NULL,
898 .read_reg = &ixgbe_read_phy_reg_generic,
899 .write_reg = &ixgbe_write_phy_reg_generic,
900 .setup_link = &ixgbe_setup_phy_link_generic,
901 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
902 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
903 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
904 .read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic,
905 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
906 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
907 .check_overtemp = &ixgbe_tn_check_overtemp,
908 .set_phy_power = &ixgbe_set_copper_phy_power,
909};
910
911static const u32 ixgbe_mvals_X540[IXGBE_MVALS_IDX_LIMIT] = {
912 IXGBE_MVALS_INIT(X540)
913};
914
915const struct ixgbe_info ixgbe_X540_info = {
916 .mac = ixgbe_mac_X540,
917 .get_invariants = &ixgbe_get_invariants_X540,
918 .mac_ops = &mac_ops_X540,
919 .eeprom_ops = &eeprom_ops_X540,
920 .phy_ops = &phy_ops_X540,
921 .mbx_ops = &mbx_ops_generic,
922 .mvals = ixgbe_mvals_X540,
923};
1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/pci.h>
29#include <linux/delay.h>
30#include <linux/sched.h>
31
32#include "ixgbe.h"
33#include "ixgbe_phy.h"
34
35#define IXGBE_X540_MAX_TX_QUEUES 128
36#define IXGBE_X540_MAX_RX_QUEUES 128
37#define IXGBE_X540_RAR_ENTRIES 128
38#define IXGBE_X540_MC_TBL_SIZE 128
39#define IXGBE_X540_VFT_TBL_SIZE 128
40#define IXGBE_X540_RX_PB_SIZE 384
41
42static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw);
43static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw);
44static s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask);
45static void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask);
46static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw);
47static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw);
48
49static enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw)
50{
51 return ixgbe_media_type_copper;
52}
53
54static s32 ixgbe_get_invariants_X540(struct ixgbe_hw *hw)
55{
56 struct ixgbe_mac_info *mac = &hw->mac;
57
58 /* Call PHY identify routine to get the phy type */
59 ixgbe_identify_phy_generic(hw);
60
61 mac->mcft_size = IXGBE_X540_MC_TBL_SIZE;
62 mac->vft_size = IXGBE_X540_VFT_TBL_SIZE;
63 mac->num_rar_entries = IXGBE_X540_RAR_ENTRIES;
64 mac->max_rx_queues = IXGBE_X540_MAX_RX_QUEUES;
65 mac->max_tx_queues = IXGBE_X540_MAX_TX_QUEUES;
66 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
67
68 return 0;
69}
70
71/**
72 * ixgbe_setup_mac_link_X540 - Set the auto advertised capabilitires
73 * @hw: pointer to hardware structure
74 * @speed: new link speed
75 * @autoneg: true if autonegotiation enabled
76 * @autoneg_wait_to_complete: true when waiting for completion is needed
77 **/
78static s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw,
79 ixgbe_link_speed speed, bool autoneg,
80 bool autoneg_wait_to_complete)
81{
82 return hw->phy.ops.setup_link_speed(hw, speed, autoneg,
83 autoneg_wait_to_complete);
84}
85
86/**
87 * ixgbe_reset_hw_X540 - Perform hardware reset
88 * @hw: pointer to hardware structure
89 *
90 * Resets the hardware by resetting the transmit and receive units, masks
91 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
92 * reset.
93 **/
94static s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw)
95{
96 s32 status;
97 u32 ctrl, i;
98
99 /* Call adapter stop to disable tx/rx and clear interrupts */
100 status = hw->mac.ops.stop_adapter(hw);
101 if (status != 0)
102 goto reset_hw_out;
103
104 /* flush pending Tx transactions */
105 ixgbe_clear_tx_pending(hw);
106
107mac_reset_top:
108 ctrl = IXGBE_CTRL_RST;
109 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
110 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
111 IXGBE_WRITE_FLUSH(hw);
112
113 /* Poll for reset bit to self-clear indicating reset is complete */
114 for (i = 0; i < 10; i++) {
115 udelay(1);
116 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
117 if (!(ctrl & IXGBE_CTRL_RST_MASK))
118 break;
119 }
120
121 if (ctrl & IXGBE_CTRL_RST_MASK) {
122 status = IXGBE_ERR_RESET_FAILED;
123 hw_dbg(hw, "Reset polling failed to complete.\n");
124 }
125 msleep(100);
126
127 /*
128 * Double resets are required for recovery from certain error
129 * conditions. Between resets, it is necessary to stall to allow time
130 * for any pending HW events to complete.
131 */
132 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
133 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
134 goto mac_reset_top;
135 }
136
137 /* Set the Rx packet buffer size. */
138 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT);
139
140 /* Store the permanent mac address */
141 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
142
143 /*
144 * Store MAC address from RAR0, clear receive address registers, and
145 * clear the multicast table. Also reset num_rar_entries to 128,
146 * since we modify this value when programming the SAN MAC address.
147 */
148 hw->mac.num_rar_entries = IXGBE_X540_MAX_TX_QUEUES;
149 hw->mac.ops.init_rx_addrs(hw);
150
151 /* Store the permanent SAN mac address */
152 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
153
154 /* Add the SAN MAC address to the RAR only if it's a valid address */
155 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
156 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
157 hw->mac.san_addr, 0, IXGBE_RAH_AV);
158
159 /* Reserve the last RAR for the SAN MAC address */
160 hw->mac.num_rar_entries--;
161 }
162
163 /* Store the alternative WWNN/WWPN prefix */
164 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
165 &hw->mac.wwpn_prefix);
166
167reset_hw_out:
168 return status;
169}
170
171/**
172 * ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx
173 * @hw: pointer to hardware structure
174 *
175 * Starts the hardware using the generic start_hw function
176 * and the generation start_hw function.
177 * Then performs revision-specific operations, if any.
178 **/
179static s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw)
180{
181 s32 ret_val = 0;
182
183 ret_val = ixgbe_start_hw_generic(hw);
184 if (ret_val != 0)
185 goto out;
186
187 ret_val = ixgbe_start_hw_gen2(hw);
188 hw->mac.rx_pb_size = IXGBE_X540_RX_PB_SIZE;
189out:
190 return ret_val;
191}
192
193/**
194 * ixgbe_get_supported_physical_layer_X540 - Returns physical layer type
195 * @hw: pointer to hardware structure
196 *
197 * Determines physical layer capabilities of the current configuration.
198 **/
199static u32 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw)
200{
201 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
202 u16 ext_ability = 0;
203
204 hw->phy.ops.identify(hw);
205
206 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
207 &ext_ability);
208 if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
209 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
210 if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
211 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
212 if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
213 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
214
215 return physical_layer;
216}
217
218/**
219 * ixgbe_init_eeprom_params_X540 - Initialize EEPROM params
220 * @hw: pointer to hardware structure
221 *
222 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
223 * ixgbe_hw struct in order to set up EEPROM access.
224 **/
225static s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw)
226{
227 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
228 u32 eec;
229 u16 eeprom_size;
230
231 if (eeprom->type == ixgbe_eeprom_uninitialized) {
232 eeprom->semaphore_delay = 10;
233 eeprom->type = ixgbe_flash;
234
235 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
236 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
237 IXGBE_EEC_SIZE_SHIFT);
238 eeprom->word_size = 1 << (eeprom_size +
239 IXGBE_EEPROM_WORD_SIZE_SHIFT);
240
241 hw_dbg(hw, "Eeprom params: type = %d, size = %d\n",
242 eeprom->type, eeprom->word_size);
243 }
244
245 return 0;
246}
247
248/**
249 * ixgbe_read_eerd_X540- Read EEPROM word using EERD
250 * @hw: pointer to hardware structure
251 * @offset: offset of word in the EEPROM to read
252 * @data: word read from the EEPROM
253 *
254 * Reads a 16 bit word from the EEPROM using the EERD register.
255 **/
256static s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data)
257{
258 s32 status = 0;
259
260 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
261 0)
262 status = ixgbe_read_eerd_generic(hw, offset, data);
263 else
264 status = IXGBE_ERR_SWFW_SYNC;
265
266 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
267 return status;
268}
269
270/**
271 * ixgbe_read_eerd_buffer_X540 - Read EEPROM word(s) using EERD
272 * @hw: pointer to hardware structure
273 * @offset: offset of word in the EEPROM to read
274 * @words: number of words
275 * @data: word(s) read from the EEPROM
276 *
277 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
278 **/
279static s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw,
280 u16 offset, u16 words, u16 *data)
281{
282 s32 status = 0;
283
284 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
285 0)
286 status = ixgbe_read_eerd_buffer_generic(hw, offset,
287 words, data);
288 else
289 status = IXGBE_ERR_SWFW_SYNC;
290
291 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
292 return status;
293}
294
295/**
296 * ixgbe_write_eewr_X540 - Write EEPROM word using EEWR
297 * @hw: pointer to hardware structure
298 * @offset: offset of word in the EEPROM to write
299 * @data: word write to the EEPROM
300 *
301 * Write a 16 bit word to the EEPROM using the EEWR register.
302 **/
303static s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data)
304{
305 s32 status = 0;
306
307 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0)
308 status = ixgbe_write_eewr_generic(hw, offset, data);
309 else
310 status = IXGBE_ERR_SWFW_SYNC;
311
312 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
313 return status;
314}
315
316/**
317 * ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR
318 * @hw: pointer to hardware structure
319 * @offset: offset of word in the EEPROM to write
320 * @words: number of words
321 * @data: word(s) write to the EEPROM
322 *
323 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
324 **/
325static s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw,
326 u16 offset, u16 words, u16 *data)
327{
328 s32 status = 0;
329
330 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
331 0)
332 status = ixgbe_write_eewr_buffer_generic(hw, offset,
333 words, data);
334 else
335 status = IXGBE_ERR_SWFW_SYNC;
336
337 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
338 return status;
339}
340
341/**
342 * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum
343 *
344 * This function does not use synchronization for EERD and EEWR. It can
345 * be used internally by function which utilize ixgbe_acquire_swfw_sync_X540.
346 *
347 * @hw: pointer to hardware structure
348 **/
349static u16 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)
350{
351 u16 i;
352 u16 j;
353 u16 checksum = 0;
354 u16 length = 0;
355 u16 pointer = 0;
356 u16 word = 0;
357
358 /*
359 * Do not use hw->eeprom.ops.read because we do not want to take
360 * the synchronization semaphores here. Instead use
361 * ixgbe_read_eerd_generic
362 */
363
364 /* Include 0x0-0x3F in the checksum */
365 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
366 if (ixgbe_read_eerd_generic(hw, i, &word) != 0) {
367 hw_dbg(hw, "EEPROM read failed\n");
368 break;
369 }
370 checksum += word;
371 }
372
373 /*
374 * Include all data from pointers 0x3, 0x6-0xE. This excludes the
375 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
376 */
377 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
378 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
379 continue;
380
381 if (ixgbe_read_eerd_generic(hw, i, &pointer) != 0) {
382 hw_dbg(hw, "EEPROM read failed\n");
383 break;
384 }
385
386 /* Skip pointer section if the pointer is invalid. */
387 if (pointer == 0xFFFF || pointer == 0 ||
388 pointer >= hw->eeprom.word_size)
389 continue;
390
391 if (ixgbe_read_eerd_generic(hw, pointer, &length) != 0) {
392 hw_dbg(hw, "EEPROM read failed\n");
393 break;
394 }
395
396 /* Skip pointer section if length is invalid. */
397 if (length == 0xFFFF || length == 0 ||
398 (pointer + length) >= hw->eeprom.word_size)
399 continue;
400
401 for (j = pointer+1; j <= pointer+length; j++) {
402 if (ixgbe_read_eerd_generic(hw, j, &word) != 0) {
403 hw_dbg(hw, "EEPROM read failed\n");
404 break;
405 }
406 checksum += word;
407 }
408 }
409
410 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
411
412 return checksum;
413}
414
415/**
416 * ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum
417 * @hw: pointer to hardware structure
418 * @checksum_val: calculated checksum
419 *
420 * Performs checksum calculation and validates the EEPROM checksum. If the
421 * caller does not need checksum_val, the value can be NULL.
422 **/
423static s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw,
424 u16 *checksum_val)
425{
426 s32 status;
427 u16 checksum;
428 u16 read_checksum = 0;
429
430 /*
431 * Read the first word from the EEPROM. If this times out or fails, do
432 * not continue or we could be in for a very long wait while every
433 * EEPROM read fails
434 */
435 status = hw->eeprom.ops.read(hw, 0, &checksum);
436
437 if (status != 0) {
438 hw_dbg(hw, "EEPROM read failed\n");
439 goto out;
440 }
441
442 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) {
443 checksum = hw->eeprom.ops.calc_checksum(hw);
444
445 /*
446 * Do not use hw->eeprom.ops.read because we do not want to take
447 * the synchronization semaphores twice here.
448 */
449 ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM,
450 &read_checksum);
451
452 /*
453 * Verify read checksum from EEPROM is the same as
454 * calculated checksum
455 */
456 if (read_checksum != checksum)
457 status = IXGBE_ERR_EEPROM_CHECKSUM;
458
459 /* If the user cares, return the calculated checksum */
460 if (checksum_val)
461 *checksum_val = checksum;
462 } else {
463 status = IXGBE_ERR_SWFW_SYNC;
464 }
465
466 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
467out:
468 return status;
469}
470
471/**
472 * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash
473 * @hw: pointer to hardware structure
474 *
475 * After writing EEPROM to shadow RAM using EEWR register, software calculates
476 * checksum and updates the EEPROM and instructs the hardware to update
477 * the flash.
478 **/
479static s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw)
480{
481 s32 status;
482 u16 checksum;
483
484 /*
485 * Read the first word from the EEPROM. If this times out or fails, do
486 * not continue or we could be in for a very long wait while every
487 * EEPROM read fails
488 */
489 status = hw->eeprom.ops.read(hw, 0, &checksum);
490
491 if (status != 0)
492 hw_dbg(hw, "EEPROM read failed\n");
493
494 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) {
495 checksum = hw->eeprom.ops.calc_checksum(hw);
496
497 /*
498 * Do not use hw->eeprom.ops.write because we do not want to
499 * take the synchronization semaphores twice here.
500 */
501 status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM,
502 checksum);
503
504 if (status == 0)
505 status = ixgbe_update_flash_X540(hw);
506 else
507 status = IXGBE_ERR_SWFW_SYNC;
508 }
509
510 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
511
512 return status;
513}
514
515/**
516 * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device
517 * @hw: pointer to hardware structure
518 *
519 * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy
520 * EEPROM from shadow RAM to the flash device.
521 **/
522static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)
523{
524 u32 flup;
525 s32 status = IXGBE_ERR_EEPROM;
526
527 status = ixgbe_poll_flash_update_done_X540(hw);
528 if (status == IXGBE_ERR_EEPROM) {
529 hw_dbg(hw, "Flash update time out\n");
530 goto out;
531 }
532
533 flup = IXGBE_READ_REG(hw, IXGBE_EEC) | IXGBE_EEC_FLUP;
534 IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
535
536 status = ixgbe_poll_flash_update_done_X540(hw);
537 if (status == 0)
538 hw_dbg(hw, "Flash update complete\n");
539 else
540 hw_dbg(hw, "Flash update time out\n");
541
542 if (hw->revision_id == 0) {
543 flup = IXGBE_READ_REG(hw, IXGBE_EEC);
544
545 if (flup & IXGBE_EEC_SEC1VAL) {
546 flup |= IXGBE_EEC_FLUP;
547 IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
548 }
549
550 status = ixgbe_poll_flash_update_done_X540(hw);
551 if (status == 0)
552 hw_dbg(hw, "Flash update complete\n");
553 else
554 hw_dbg(hw, "Flash update time out\n");
555 }
556out:
557 return status;
558}
559
560/**
561 * ixgbe_poll_flash_update_done_X540 - Poll flash update status
562 * @hw: pointer to hardware structure
563 *
564 * Polls the FLUDONE (bit 26) of the EEC Register to determine when the
565 * flash update is done.
566 **/
567static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw)
568{
569 u32 i;
570 u32 reg;
571 s32 status = IXGBE_ERR_EEPROM;
572
573 for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) {
574 reg = IXGBE_READ_REG(hw, IXGBE_EEC);
575 if (reg & IXGBE_EEC_FLUDONE) {
576 status = 0;
577 break;
578 }
579 udelay(5);
580 }
581 return status;
582}
583
584/**
585 * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore
586 * @hw: pointer to hardware structure
587 * @mask: Mask to specify which semaphore to acquire
588 *
589 * Acquires the SWFW semaphore thought the SW_FW_SYNC register for
590 * the specified function (CSR, PHY0, PHY1, NVM, Flash)
591 **/
592static s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
593{
594 u32 swfw_sync;
595 u32 swmask = mask;
596 u32 fwmask = mask << 5;
597 u32 hwmask = 0;
598 u32 timeout = 200;
599 u32 i;
600
601 if (swmask == IXGBE_GSSR_EEP_SM)
602 hwmask = IXGBE_GSSR_FLASH_SM;
603
604 for (i = 0; i < timeout; i++) {
605 /*
606 * SW NVM semaphore bit is used for access to all
607 * SW_FW_SYNC bits (not just NVM)
608 */
609 if (ixgbe_get_swfw_sync_semaphore(hw))
610 return IXGBE_ERR_SWFW_SYNC;
611
612 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
613 if (!(swfw_sync & (fwmask | swmask | hwmask))) {
614 swfw_sync |= swmask;
615 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
616 ixgbe_release_swfw_sync_semaphore(hw);
617 break;
618 } else {
619 /*
620 * Firmware currently using resource (fwmask),
621 * hardware currently using resource (hwmask),
622 * or other software thread currently using
623 * resource (swmask)
624 */
625 ixgbe_release_swfw_sync_semaphore(hw);
626 usleep_range(5000, 10000);
627 }
628 }
629
630 /*
631 * If the resource is not released by the FW/HW the SW can assume that
632 * the FW/HW malfunctions. In that case the SW should sets the
633 * SW bit(s) of the requested resource(s) while ignoring the
634 * corresponding FW/HW bits in the SW_FW_SYNC register.
635 */
636 if (i >= timeout) {
637 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
638 if (swfw_sync & (fwmask | hwmask)) {
639 if (ixgbe_get_swfw_sync_semaphore(hw))
640 return IXGBE_ERR_SWFW_SYNC;
641
642 swfw_sync |= swmask;
643 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
644 ixgbe_release_swfw_sync_semaphore(hw);
645 }
646 }
647
648 usleep_range(5000, 10000);
649 return 0;
650}
651
652/**
653 * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore
654 * @hw: pointer to hardware structure
655 * @mask: Mask to specify which semaphore to release
656 *
657 * Releases the SWFW semaphore through the SW_FW_SYNC register
658 * for the specified function (CSR, PHY0, PHY1, EVM, Flash)
659 **/
660static void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
661{
662 u32 swfw_sync;
663 u32 swmask = mask;
664
665 ixgbe_get_swfw_sync_semaphore(hw);
666
667 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
668 swfw_sync &= ~swmask;
669 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
670
671 ixgbe_release_swfw_sync_semaphore(hw);
672 usleep_range(5000, 10000);
673}
674
675/**
676 * ixgbe_get_nvm_semaphore - Get hardware semaphore
677 * @hw: pointer to hardware structure
678 *
679 * Sets the hardware semaphores so SW/FW can gain control of shared resources
680 **/
681static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw)
682{
683 s32 status = IXGBE_ERR_EEPROM;
684 u32 timeout = 2000;
685 u32 i;
686 u32 swsm;
687
688 /* Get SMBI software semaphore between device drivers first */
689 for (i = 0; i < timeout; i++) {
690 /*
691 * If the SMBI bit is 0 when we read it, then the bit will be
692 * set and we have the semaphore
693 */
694 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
695 if (!(swsm & IXGBE_SWSM_SMBI)) {
696 status = 0;
697 break;
698 }
699 udelay(50);
700 }
701
702 /* Now get the semaphore between SW/FW through the REGSMP bit */
703 if (status) {
704 for (i = 0; i < timeout; i++) {
705 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
706 if (!(swsm & IXGBE_SWFW_REGSMP))
707 break;
708
709 udelay(50);
710 }
711 } else {
712 hw_dbg(hw, "Software semaphore SMBI between device drivers "
713 "not granted.\n");
714 }
715
716 return status;
717}
718
719/**
720 * ixgbe_release_nvm_semaphore - Release hardware semaphore
721 * @hw: pointer to hardware structure
722 *
723 * This function clears hardware semaphore bits.
724 **/
725static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw)
726{
727 u32 swsm;
728
729 /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */
730
731 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
732 swsm &= ~IXGBE_SWSM_SMBI;
733 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
734
735 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
736 swsm &= ~IXGBE_SWFW_REGSMP;
737 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swsm);
738
739 IXGBE_WRITE_FLUSH(hw);
740}
741
742/**
743 * ixgbe_blink_led_start_X540 - Blink LED based on index.
744 * @hw: pointer to hardware structure
745 * @index: led number to blink
746 *
747 * Devices that implement the version 2 interface:
748 * X540
749 **/
750static s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index)
751{
752 u32 macc_reg;
753 u32 ledctl_reg;
754 ixgbe_link_speed speed;
755 bool link_up;
756
757 /*
758 * Link should be up in order for the blink bit in the LED control
759 * register to work. Force link and speed in the MAC if link is down.
760 * This will be reversed when we stop the blinking.
761 */
762 hw->mac.ops.check_link(hw, &speed, &link_up, false);
763 if (!link_up) {
764 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
765 macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS;
766 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
767 }
768 /* Set the LED to LINK_UP + BLINK. */
769 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
770 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
771 ledctl_reg |= IXGBE_LED_BLINK(index);
772 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
773 IXGBE_WRITE_FLUSH(hw);
774
775 return 0;
776}
777
778/**
779 * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index.
780 * @hw: pointer to hardware structure
781 * @index: led number to stop blinking
782 *
783 * Devices that implement the version 2 interface:
784 * X540
785 **/
786static s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index)
787{
788 u32 macc_reg;
789 u32 ledctl_reg;
790
791 /* Restore the LED to its default value. */
792 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
793 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
794 ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
795 ledctl_reg &= ~IXGBE_LED_BLINK(index);
796 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
797
798 /* Unforce link and speed in the MAC. */
799 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
800 macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS);
801 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
802 IXGBE_WRITE_FLUSH(hw);
803
804 return 0;
805}
806static struct ixgbe_mac_operations mac_ops_X540 = {
807 .init_hw = &ixgbe_init_hw_generic,
808 .reset_hw = &ixgbe_reset_hw_X540,
809 .start_hw = &ixgbe_start_hw_X540,
810 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
811 .get_media_type = &ixgbe_get_media_type_X540,
812 .get_supported_physical_layer =
813 &ixgbe_get_supported_physical_layer_X540,
814 .enable_rx_dma = &ixgbe_enable_rx_dma_generic,
815 .get_mac_addr = &ixgbe_get_mac_addr_generic,
816 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic,
817 .get_device_caps = &ixgbe_get_device_caps_generic,
818 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic,
819 .stop_adapter = &ixgbe_stop_adapter_generic,
820 .get_bus_info = &ixgbe_get_bus_info_generic,
821 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
822 .read_analog_reg8 = NULL,
823 .write_analog_reg8 = NULL,
824 .setup_link = &ixgbe_setup_mac_link_X540,
825 .set_rxpba = &ixgbe_set_rxpba_generic,
826 .check_link = &ixgbe_check_mac_link_generic,
827 .get_link_capabilities = &ixgbe_get_copper_link_capabilities_generic,
828 .led_on = &ixgbe_led_on_generic,
829 .led_off = &ixgbe_led_off_generic,
830 .blink_led_start = &ixgbe_blink_led_start_X540,
831 .blink_led_stop = &ixgbe_blink_led_stop_X540,
832 .set_rar = &ixgbe_set_rar_generic,
833 .clear_rar = &ixgbe_clear_rar_generic,
834 .set_vmdq = &ixgbe_set_vmdq_generic,
835 .clear_vmdq = &ixgbe_clear_vmdq_generic,
836 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
837 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
838 .enable_mc = &ixgbe_enable_mc_generic,
839 .disable_mc = &ixgbe_disable_mc_generic,
840 .clear_vfta = &ixgbe_clear_vfta_generic,
841 .set_vfta = &ixgbe_set_vfta_generic,
842 .fc_enable = &ixgbe_fc_enable_generic,
843 .set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic,
844 .init_uta_tables = &ixgbe_init_uta_tables_generic,
845 .setup_sfp = NULL,
846 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing,
847 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing,
848 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540,
849 .release_swfw_sync = &ixgbe_release_swfw_sync_X540,
850 .disable_rx_buff = &ixgbe_disable_rx_buff_generic,
851 .enable_rx_buff = &ixgbe_enable_rx_buff_generic,
852 .get_thermal_sensor_data = NULL,
853 .init_thermal_sensor_thresh = NULL,
854};
855
856static struct ixgbe_eeprom_operations eeprom_ops_X540 = {
857 .init_params = &ixgbe_init_eeprom_params_X540,
858 .read = &ixgbe_read_eerd_X540,
859 .read_buffer = &ixgbe_read_eerd_buffer_X540,
860 .write = &ixgbe_write_eewr_X540,
861 .write_buffer = &ixgbe_write_eewr_buffer_X540,
862 .calc_checksum = &ixgbe_calc_eeprom_checksum_X540,
863 .validate_checksum = &ixgbe_validate_eeprom_checksum_X540,
864 .update_checksum = &ixgbe_update_eeprom_checksum_X540,
865};
866
867static struct ixgbe_phy_operations phy_ops_X540 = {
868 .identify = &ixgbe_identify_phy_generic,
869 .identify_sfp = &ixgbe_identify_sfp_module_generic,
870 .init = NULL,
871 .reset = NULL,
872 .read_reg = &ixgbe_read_phy_reg_generic,
873 .write_reg = &ixgbe_write_phy_reg_generic,
874 .setup_link = &ixgbe_setup_phy_link_generic,
875 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
876 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
877 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
878 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
879 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
880 .check_overtemp = &ixgbe_tn_check_overtemp,
881 .get_firmware_version = &ixgbe_get_phy_firmware_version_generic,
882};
883
884struct ixgbe_info ixgbe_X540_info = {
885 .mac = ixgbe_mac_X540,
886 .get_invariants = &ixgbe_get_invariants_X540,
887 .mac_ops = &mac_ops_X540,
888 .eeprom_ops = &eeprom_ops_X540,
889 .phy_ops = &phy_ops_X540,
890 .mbx_ops = &mbx_ops_generic,
891};