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1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright (C) 2018-2021, Intel Corporation. */
3
4#ifndef _ICE_PTP_CONSTS_H_
5#define _ICE_PTP_CONSTS_H_
6
7/* Constant definitions related to the hardware clock used for PTP 1588
8 * features and functionality.
9 */
10/* Constants defined for the PTP 1588 clock hardware. */
11
12const struct ice_phy_reg_info_eth56g eth56g_phy_res[NUM_ETH56G_PHY_RES] = {
13 /* ETH56G_PHY_REG_PTP */
14 {
15 /* base_addr */
16 {
17 0x092000,
18 0x126000,
19 0x1BA000,
20 0x24E000,
21 0x2E2000,
22 },
23 /* step */
24 0x98,
25 },
26 /* ETH56G_PHY_MEM_PTP */
27 {
28 /* base_addr */
29 {
30 0x093000,
31 0x127000,
32 0x1BB000,
33 0x24F000,
34 0x2E3000,
35 },
36 /* step */
37 0x200,
38 },
39 /* ETH56G_PHY_REG_XPCS */
40 {
41 /* base_addr */
42 {
43 0x000000,
44 0x009400,
45 0x128000,
46 0x1BC000,
47 0x250000,
48 },
49 /* step */
50 0x21000,
51 },
52 /* ETH56G_PHY_REG_MAC */
53 {
54 /* base_addr */
55 {
56 0x085000,
57 0x119000,
58 0x1AD000,
59 0x241000,
60 0x2D5000,
61 },
62 /* step */
63 0x1000,
64 },
65 /* ETH56G_PHY_REG_GPCS */
66 {
67 /* base_addr */
68 {
69 0x084000,
70 0x118000,
71 0x1AC000,
72 0x240000,
73 0x2D4000,
74 },
75 /* step */
76 0x400,
77 },
78};
79
80const
81struct ice_eth56g_mac_reg_cfg eth56g_mac_cfg[NUM_ICE_ETH56G_LNK_SPD] = {
82 [ICE_ETH56G_LNK_SPD_1G] = {
83 .tx_mode = { .def = 6, },
84 .rx_mode = { .def = 6, },
85 .blks_per_clk = 1,
86 .blktime = 0x4000, /* 32 */
87 .tx_offset = {
88 .serdes = 0x6666, /* 51.2 */
89 .no_fec = 0xd066, /* 104.2 */
90 .sfd = 0x3000, /* 24 */
91 .onestep = 0x30000 /* 384 */
92 },
93 .rx_offset = {
94 .serdes = 0xffffc59a, /* -29.2 */
95 .no_fec = 0xffff0a80, /* -122.75 */
96 .sfd = 0x2c00, /* 22 */
97 .bs_ds = 0x19a /* 0.8 */
98 /* Dynamic bitslip 0 equals to 10 */
99 }
100 },
101 [ICE_ETH56G_LNK_SPD_2_5G] = {
102 .tx_mode = { .def = 6, },
103 .rx_mode = { .def = 6, },
104 .blks_per_clk = 1,
105 .blktime = 0x199a, /* 12.8 */
106 .tx_offset = {
107 .serdes = 0x28f6, /* 20.48 */
108 .no_fec = 0x53b8, /* 41.86 */
109 .sfd = 0x1333, /* 9.6 */
110 .onestep = 0x13333 /* 153.6 */
111 },
112 .rx_offset = {
113 .serdes = 0xffffe8a4, /* -11.68 */
114 .no_fec = 0xffff9a76, /* -50.77 */
115 .sfd = 0xf33, /* 7.6 */
116 .bs_ds = 0xa4 /* 0.32 */
117 }
118 },
119 [ICE_ETH56G_LNK_SPD_10G] = {
120 .tx_mode = { .def = 1, },
121 .rx_mode = { .def = 1, },
122 .blks_per_clk = 1,
123 .blktime = 0x666, /* 3.2 */
124 .tx_offset = {
125 .serdes = 0x234c, /* 17.6484848 */
126 .no_fec = 0x8e80, /* 71.25 */
127 .fc = 0xb4a4, /* 90.32 */
128 .sfd = 0x4a4, /* 2.32 */
129 .onestep = 0x4ccd /* 38.4 */
130 },
131 .rx_offset = {
132 .serdes = 0xffffeb27, /* -10.42424 */
133 .no_fec = 0xffffcccd, /* -25.6 */
134 .fc = 0xfffc557b, /* -469.26 */
135 .sfd = 0x4a4, /* 2.32 */
136 .bs_ds = 0x32 /* 0.0969697 */
137 }
138 },
139 [ICE_ETH56G_LNK_SPD_25G] = {
140 .tx_mode = {
141 .def = 1,
142 .rs = 4
143 },
144 .tx_mk_dly = 4,
145 .tx_cw_dly = {
146 .def = 1,
147 .onestep = 6
148 },
149 .rx_mode = {
150 .def = 1,
151 .rs = 4
152 },
153 .rx_mk_dly = {
154 .def = 1,
155 .rs = 1
156 },
157 .rx_cw_dly = {
158 .def = 1,
159 .rs = 1
160 },
161 .blks_per_clk = 1,
162 .blktime = 0x28f, /* 1.28 */
163 .mktime = 0x147b, /* 10.24, only if RS-FEC enabled */
164 .tx_offset = {
165 .serdes = 0xe1e, /* 7.0593939 */
166 .no_fec = 0x3857, /* 28.17 */
167 .fc = 0x48c3, /* 36.38 */
168 .rs = 0x8100, /* 64.5 */
169 .sfd = 0x1dc, /* 0.93 */
170 .onestep = 0x1eb8 /* 15.36 */
171 },
172 .rx_offset = {
173 .serdes = 0xfffff7a9, /* -4.1697 */
174 .no_fec = 0xffffe71a, /* -12.45 */
175 .fc = 0xfffe894d, /* -187.35 */
176 .rs = 0xfffff8cd, /* -3.6 */
177 .sfd = 0x1dc, /* 0.93 */
178 .bs_ds = 0x14 /* 0.0387879, RS-FEC 0 */
179 }
180 },
181 [ICE_ETH56G_LNK_SPD_40G] = {
182 .tx_mode = { .def = 3 },
183 .tx_mk_dly = 4,
184 .tx_cw_dly = {
185 .def = 1,
186 .onestep = 6
187 },
188 .rx_mode = { .def = 4 },
189 .rx_mk_dly = { .def = 1 },
190 .rx_cw_dly = { .def = 1 },
191 .blktime = 0x333, /* 1.6 */
192 .mktime = 0xccd, /* 6.4 */
193 .tx_offset = {
194 .serdes = 0x234c, /* 17.6484848 */
195 .no_fec = 0x5a8a, /* 45.27 */
196 .fc = 0x81b8, /* 64.86 */
197 .sfd = 0x4a4, /* 2.32 */
198 .onestep = 0x1333 /* 9.6 */
199 },
200 .rx_offset = {
201 .serdes = 0xffffeb27, /* -10.42424 */
202 .no_fec = 0xfffff594, /* -5.21 */
203 .fc = 0xfffe3080, /* -231.75 */
204 .sfd = 0x4a4, /* 2.32 */
205 .bs_ds = 0xccd /* 6.4 */
206 }
207 },
208 [ICE_ETH56G_LNK_SPD_50G] = {
209 .tx_mode = { .def = 5 },
210 .tx_mk_dly = 4,
211 .tx_cw_dly = {
212 .def = 1,
213 .onestep = 6
214 },
215 .rx_mode = { .def = 5 },
216 .rx_mk_dly = { .def = 1 },
217 .rx_cw_dly = { .def = 1 },
218 .blktime = 0x28f, /* 1.28 */
219 .mktime = 0xa3d, /* 5.12 */
220 .tx_offset = {
221 .serdes = 0x13ba, /* 9.86353 */
222 .rs = 0x5400, /* 42 */
223 .sfd = 0xe6, /* 0.45 */
224 .onestep = 0xf5c /* 7.68 */
225 },
226 .rx_offset = {
227 .serdes = 0xfffff7e8, /* -4.04706 */
228 .rs = 0xfffff994, /* -3.21 */
229 .sfd = 0xe6 /* 0.45 */
230 }
231 },
232 [ICE_ETH56G_LNK_SPD_50G2] = {
233 .tx_mode = {
234 .def = 3,
235 .rs = 2
236 },
237 .tx_mk_dly = 4,
238 .tx_cw_dly = {
239 .def = 1,
240 .onestep = 6
241 },
242 .rx_mode = {
243 .def = 4,
244 .rs = 1
245 },
246 .rx_mk_dly = { .def = 1 },
247 .rx_cw_dly = { .def = 1 },
248 .blktime = 0x28f, /* 1.28 */
249 .mktime = 0xa3d, /* 5.12 */
250 .tx_offset = {
251 .serdes = 0xe1e, /* 7.0593939 */
252 .no_fec = 0x3d33, /* 30.6 */
253 .rs = 0x5057, /* 40.17 */
254 .sfd = 0x1dc, /* 0.93 */
255 .onestep = 0xf5c /* 7.68 */
256 },
257 .rx_offset = {
258 .serdes = 0xfffff7a9, /* -4.1697 */
259 .no_fec = 0xfffff8cd, /* -3.6 */
260 .rs = 0xfffff21a, /* -6.95 */
261 .sfd = 0x1dc, /* 0.93 */
262 .bs_ds = 0xa3d /* 5.12, RS-FEC 0x633 (3.1) */
263 }
264 },
265 [ICE_ETH56G_LNK_SPD_100G] = {
266 .tx_mode = {
267 .def = 3,
268 .rs = 2
269 },
270 .tx_mk_dly = 10,
271 .tx_cw_dly = {
272 .def = 3,
273 .onestep = 6
274 },
275 .rx_mode = {
276 .def = 4,
277 .rs = 1
278 },
279 .rx_mk_dly = { .def = 5 },
280 .rx_cw_dly = { .def = 5 },
281 .blks_per_clk = 1,
282 .blktime = 0x148, /* 0.64 */
283 .mktime = 0x199a, /* 12.8 */
284 .tx_offset = {
285 .serdes = 0xe1e, /* 7.0593939 */
286 .no_fec = 0x67ec, /* 51.96 */
287 .rs = 0x44fb, /* 34.49 */
288 .sfd = 0x1dc, /* 0.93 */
289 .onestep = 0xf5c /* 7.68 */
290 },
291 .rx_offset = {
292 .serdes = 0xfffff7a9, /* -4.1697 */
293 .no_fec = 0xfffff5a9, /* -5.17 */
294 .rs = 0xfffff6e6, /* -4.55 */
295 .sfd = 0x1dc, /* 0.93 */
296 .bs_ds = 0x199a /* 12.8, RS-FEC 0x31b (1.552) */
297 }
298 },
299 [ICE_ETH56G_LNK_SPD_100G2] = {
300 .tx_mode = { .def = 5 },
301 .tx_mk_dly = 10,
302 .tx_cw_dly = {
303 .def = 3,
304 .onestep = 6
305 },
306 .rx_mode = { .def = 5 },
307 .rx_mk_dly = { .def = 5 },
308 .rx_cw_dly = { .def = 5 },
309 .blks_per_clk = 1,
310 .blktime = 0x148, /* 0.64 */
311 .mktime = 0x199a, /* 12.8 */
312 .tx_offset = {
313 .serdes = 0x13ba, /* 9.86353 */
314 .rs = 0x460a, /* 35.02 */
315 .sfd = 0xe6, /* 0.45 */
316 .onestep = 0xf5c /* 7.68 */
317 },
318 .rx_offset = {
319 .serdes = 0xfffff7e8, /* -4.04706 */
320 .rs = 0xfffff548, /* -5.36 */
321 .sfd = 0xe6, /* 0.45 */
322 .bs_ds = 0x303 /* 1.506 */
323 }
324 }
325};
326
327/* struct ice_time_ref_info_e82x
328 *
329 * E822 hardware can use different sources as the reference for the PTP
330 * hardware clock. Each clock has different characteristics such as a slightly
331 * different frequency, etc.
332 *
333 * This lookup table defines several constants that depend on the current time
334 * reference. See the struct ice_time_ref_info_e82x for information about the
335 * meaning of each constant.
336 */
337const struct ice_time_ref_info_e82x e82x_time_ref[NUM_ICE_TIME_REF_FREQ] = {
338 /* ICE_TIME_REF_FREQ_25_000 -> 25 MHz */
339 {
340 /* pll_freq */
341 823437500, /* 823.4375 MHz PLL */
342 /* nominal_incval */
343 0x136e44fabULL,
344 /* pps_delay */
345 11,
346 },
347
348 /* ICE_TIME_REF_FREQ_122_880 -> 122.88 MHz */
349 {
350 /* pll_freq */
351 783360000, /* 783.36 MHz */
352 /* nominal_incval */
353 0x146cc2177ULL,
354 /* pps_delay */
355 12,
356 },
357
358 /* ICE_TIME_REF_FREQ_125_000 -> 125 MHz */
359 {
360 /* pll_freq */
361 796875000, /* 796.875 MHz */
362 /* nominal_incval */
363 0x141414141ULL,
364 /* pps_delay */
365 12,
366 },
367
368 /* ICE_TIME_REF_FREQ_153_600 -> 153.6 MHz */
369 {
370 /* pll_freq */
371 816000000, /* 816 MHz */
372 /* nominal_incval */
373 0x139b9b9baULL,
374 /* pps_delay */
375 12,
376 },
377
378 /* ICE_TIME_REF_FREQ_156_250 -> 156.25 MHz */
379 {
380 /* pll_freq */
381 830078125, /* 830.78125 MHz */
382 /* nominal_incval */
383 0x134679aceULL,
384 /* pps_delay */
385 11,
386 },
387
388 /* ICE_TIME_REF_FREQ_245_760 -> 245.76 MHz */
389 {
390 /* pll_freq */
391 783360000, /* 783.36 MHz */
392 /* nominal_incval */
393 0x146cc2177ULL,
394 /* pps_delay */
395 12,
396 },
397};
398
399const struct ice_cgu_pll_params_e82x e822_cgu_params[NUM_ICE_TIME_REF_FREQ] = {
400 /* ICE_TIME_REF_FREQ_25_000 -> 25 MHz */
401 {
402 /* refclk_pre_div */
403 1,
404 /* feedback_div */
405 197,
406 /* frac_n_div */
407 2621440,
408 /* post_pll_div */
409 6,
410 },
411
412 /* ICE_TIME_REF_FREQ_122_880 -> 122.88 MHz */
413 {
414 /* refclk_pre_div */
415 5,
416 /* feedback_div */
417 223,
418 /* frac_n_div */
419 524288,
420 /* post_pll_div */
421 7,
422 },
423
424 /* ICE_TIME_REF_FREQ_125_000 -> 125 MHz */
425 {
426 /* refclk_pre_div */
427 5,
428 /* feedback_div */
429 223,
430 /* frac_n_div */
431 524288,
432 /* post_pll_div */
433 7,
434 },
435
436 /* ICE_TIME_REF_FREQ_153_600 -> 153.6 MHz */
437 {
438 /* refclk_pre_div */
439 5,
440 /* feedback_div */
441 159,
442 /* frac_n_div */
443 1572864,
444 /* post_pll_div */
445 6,
446 },
447
448 /* ICE_TIME_REF_FREQ_156_250 -> 156.25 MHz */
449 {
450 /* refclk_pre_div */
451 5,
452 /* feedback_div */
453 159,
454 /* frac_n_div */
455 1572864,
456 /* post_pll_div */
457 6,
458 },
459
460 /* ICE_TIME_REF_FREQ_245_760 -> 245.76 MHz */
461 {
462 /* refclk_pre_div */
463 10,
464 /* feedback_div */
465 223,
466 /* frac_n_div */
467 524288,
468 /* post_pll_div */
469 7,
470 },
471};
472
473const
474struct ice_cgu_pll_params_e825c e825c_cgu_params[NUM_ICE_TIME_REF_FREQ] = {
475 /* ICE_TIME_REF_FREQ_25_000 -> 25 MHz */
476 {
477 /* tspll_ck_refclkfreq */
478 0x19,
479 /* tspll_ndivratio */
480 1,
481 /* tspll_fbdiv_intgr */
482 320,
483 /* tspll_fbdiv_frac */
484 0,
485 /* ref1588_ck_div */
486 0,
487 },
488
489 /* ICE_TIME_REF_FREQ_122_880 -> 122.88 MHz */
490 {
491 /* tspll_ck_refclkfreq */
492 0x29,
493 /* tspll_ndivratio */
494 3,
495 /* tspll_fbdiv_intgr */
496 195,
497 /* tspll_fbdiv_frac */
498 1342177280UL,
499 /* ref1588_ck_div */
500 0,
501 },
502
503 /* ICE_TIME_REF_FREQ_125_000 -> 125 MHz */
504 {
505 /* tspll_ck_refclkfreq */
506 0x3E,
507 /* tspll_ndivratio */
508 2,
509 /* tspll_fbdiv_intgr */
510 128,
511 /* tspll_fbdiv_frac */
512 0,
513 /* ref1588_ck_div */
514 0,
515 },
516
517 /* ICE_TIME_REF_FREQ_153_600 -> 153.6 MHz */
518 {
519 /* tspll_ck_refclkfreq */
520 0x33,
521 /* tspll_ndivratio */
522 3,
523 /* tspll_fbdiv_intgr */
524 156,
525 /* tspll_fbdiv_frac */
526 1073741824UL,
527 /* ref1588_ck_div */
528 0,
529 },
530
531 /* ICE_TIME_REF_FREQ_156_250 -> 156.25 MHz */
532 {
533 /* tspll_ck_refclkfreq */
534 0x1F,
535 /* tspll_ndivratio */
536 5,
537 /* tspll_fbdiv_intgr */
538 256,
539 /* tspll_fbdiv_frac */
540 0,
541 /* ref1588_ck_div */
542 0,
543 },
544
545 /* ICE_TIME_REF_FREQ_245_760 -> 245.76 MHz */
546 {
547 /* tspll_ck_refclkfreq */
548 0x52,
549 /* tspll_ndivratio */
550 3,
551 /* tspll_fbdiv_intgr */
552 97,
553 /* tspll_fbdiv_frac */
554 2818572288UL,
555 /* ref1588_ck_div */
556 0,
557 },
558};
559
560/* struct ice_vernier_info_e82x
561 *
562 * E822 hardware calibrates the delay of the timestamp indication from the
563 * actual packet transmission or reception during the initialization of the
564 * PHY. To do this, the hardware mechanism uses some conversions between the
565 * various clocks within the PHY block. This table defines constants used to
566 * calculate the correct conversion ratios in the PHY registers.
567 *
568 * Many of the values relate to the PAR/PCS clock conversion registers. For
569 * these registers, a value of 0 means that the associated register is not
570 * used by this link speed, and that the register should be cleared by writing
571 * 0. Other values specify the clock frequency in Hz.
572 */
573const struct ice_vernier_info_e82x e822_vernier[NUM_ICE_PTP_LNK_SPD] = {
574 /* ICE_PTP_LNK_SPD_1G */
575 {
576 /* tx_par_clk */
577 31250000, /* 31.25 MHz */
578 /* rx_par_clk */
579 31250000, /* 31.25 MHz */
580 /* tx_pcs_clk */
581 125000000, /* 125 MHz */
582 /* rx_pcs_clk */
583 125000000, /* 125 MHz */
584 /* tx_desk_rsgb_par */
585 0, /* unused */
586 /* rx_desk_rsgb_par */
587 0, /* unused */
588 /* tx_desk_rsgb_pcs */
589 0, /* unused */
590 /* rx_desk_rsgb_pcs */
591 0, /* unused */
592 /* tx_fixed_delay */
593 25140,
594 /* pmd_adj_divisor */
595 10000000,
596 /* rx_fixed_delay */
597 17372,
598 },
599 /* ICE_PTP_LNK_SPD_10G */
600 {
601 /* tx_par_clk */
602 257812500, /* 257.8125 MHz */
603 /* rx_par_clk */
604 257812500, /* 257.8125 MHz */
605 /* tx_pcs_clk */
606 156250000, /* 156.25 MHz */
607 /* rx_pcs_clk */
608 156250000, /* 156.25 MHz */
609 /* tx_desk_rsgb_par */
610 0, /* unused */
611 /* rx_desk_rsgb_par */
612 0, /* unused */
613 /* tx_desk_rsgb_pcs */
614 0, /* unused */
615 /* rx_desk_rsgb_pcs */
616 0, /* unused */
617 /* tx_fixed_delay */
618 6938,
619 /* pmd_adj_divisor */
620 82500000,
621 /* rx_fixed_delay */
622 6212,
623 },
624 /* ICE_PTP_LNK_SPD_25G */
625 {
626 /* tx_par_clk */
627 644531250, /* 644.53125 MHZ */
628 /* rx_par_clk */
629 644531250, /* 644.53125 MHz */
630 /* tx_pcs_clk */
631 390625000, /* 390.625 MHz */
632 /* rx_pcs_clk */
633 390625000, /* 390.625 MHz */
634 /* tx_desk_rsgb_par */
635 0, /* unused */
636 /* rx_desk_rsgb_par */
637 0, /* unused */
638 /* tx_desk_rsgb_pcs */
639 0, /* unused */
640 /* rx_desk_rsgb_pcs */
641 0, /* unused */
642 /* tx_fixed_delay */
643 2778,
644 /* pmd_adj_divisor */
645 206250000,
646 /* rx_fixed_delay */
647 2491,
648 },
649 /* ICE_PTP_LNK_SPD_25G_RS */
650 {
651 /* tx_par_clk */
652 0, /* unused */
653 /* rx_par_clk */
654 0, /* unused */
655 /* tx_pcs_clk */
656 0, /* unused */
657 /* rx_pcs_clk */
658 0, /* unused */
659 /* tx_desk_rsgb_par */
660 161132812, /* 162.1328125 MHz Reed Solomon gearbox */
661 /* rx_desk_rsgb_par */
662 161132812, /* 162.1328125 MHz Reed Solomon gearbox */
663 /* tx_desk_rsgb_pcs */
664 97656250, /* 97.62625 MHz Reed Solomon gearbox */
665 /* rx_desk_rsgb_pcs */
666 97656250, /* 97.62625 MHz Reed Solomon gearbox */
667 /* tx_fixed_delay */
668 3928,
669 /* pmd_adj_divisor */
670 206250000,
671 /* rx_fixed_delay */
672 29535,
673 },
674 /* ICE_PTP_LNK_SPD_40G */
675 {
676 /* tx_par_clk */
677 257812500,
678 /* rx_par_clk */
679 257812500,
680 /* tx_pcs_clk */
681 156250000, /* 156.25 MHz */
682 /* rx_pcs_clk */
683 156250000, /* 156.25 MHz */
684 /* tx_desk_rsgb_par */
685 0, /* unused */
686 /* rx_desk_rsgb_par */
687 156250000, /* 156.25 MHz deskew clock */
688 /* tx_desk_rsgb_pcs */
689 0, /* unused */
690 /* rx_desk_rsgb_pcs */
691 156250000, /* 156.25 MHz deskew clock */
692 /* tx_fixed_delay */
693 5666,
694 /* pmd_adj_divisor */
695 82500000,
696 /* rx_fixed_delay */
697 4244,
698 },
699 /* ICE_PTP_LNK_SPD_50G */
700 {
701 /* tx_par_clk */
702 644531250, /* 644.53125 MHZ */
703 /* rx_par_clk */
704 644531250, /* 644.53125 MHZ */
705 /* tx_pcs_clk */
706 390625000, /* 390.625 MHz */
707 /* rx_pcs_clk */
708 390625000, /* 390.625 MHz */
709 /* tx_desk_rsgb_par */
710 0, /* unused */
711 /* rx_desk_rsgb_par */
712 195312500, /* 193.3125 MHz deskew clock */
713 /* tx_desk_rsgb_pcs */
714 0, /* unused */
715 /* rx_desk_rsgb_pcs */
716 195312500, /* 193.3125 MHz deskew clock */
717 /* tx_fixed_delay */
718 2778,
719 /* pmd_adj_divisor */
720 206250000,
721 /* rx_fixed_delay */
722 2868,
723 },
724 /* ICE_PTP_LNK_SPD_50G_RS */
725 {
726 /* tx_par_clk */
727 0, /* unused */
728 /* rx_par_clk */
729 644531250, /* 644.53125 MHz */
730 /* tx_pcs_clk */
731 0, /* unused */
732 /* rx_pcs_clk */
733 644531250, /* 644.53125 MHz */
734 /* tx_desk_rsgb_par */
735 322265625, /* 322.265625 MHz Reed Solomon gearbox */
736 /* rx_desk_rsgb_par */
737 322265625, /* 322.265625 MHz Reed Solomon gearbox */
738 /* tx_desk_rsgb_pcs */
739 644531250, /* 644.53125 MHz Reed Solomon gearbox */
740 /* rx_desk_rsgb_pcs */
741 644531250, /* 644.53125 MHz Reed Solomon gearbox */
742 /* tx_fixed_delay */
743 2095,
744 /* pmd_adj_divisor */
745 206250000,
746 /* rx_fixed_delay */
747 14524,
748 },
749 /* ICE_PTP_LNK_SPD_100G_RS */
750 {
751 /* tx_par_clk */
752 0, /* unused */
753 /* rx_par_clk */
754 644531250, /* 644.53125 MHz */
755 /* tx_pcs_clk */
756 0, /* unused */
757 /* rx_pcs_clk */
758 644531250, /* 644.53125 MHz */
759 /* tx_desk_rsgb_par */
760 644531250, /* 644.53125 MHz Reed Solomon gearbox */
761 /* rx_desk_rsgb_par */
762 644531250, /* 644.53125 MHz Reed Solomon gearbox */
763 /* tx_desk_rsgb_pcs */
764 390625000, /* 390.625 MHz Reed Solomon gearbox */
765 /* rx_desk_rsgb_pcs */
766 390625000, /* 390.625 MHz Reed Solomon gearbox */
767 /* tx_fixed_delay */
768 1620,
769 /* pmd_adj_divisor */
770 206250000,
771 /* rx_fixed_delay */
772 7775,
773 },
774};
775
776#endif /* _ICE_PTP_CONSTS_H_ */