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1// SPDX-License-Identifier: GPL-2.0
2/* Copyright (c) 2018-2023, Intel Corporation. */
3
4#include "ice_common.h"
5#include "ice_sched.h"
6#include "ice_adminq_cmd.h"
7#include "ice_flow.h"
8#include "ice_ptp_hw.h"
9
10#define ICE_PF_RESET_WAIT_COUNT 300
11#define ICE_MAX_NETLIST_SIZE 10
12
13static const char * const ice_link_mode_str_low[] = {
14 [0] = "100BASE_TX",
15 [1] = "100M_SGMII",
16 [2] = "1000BASE_T",
17 [3] = "1000BASE_SX",
18 [4] = "1000BASE_LX",
19 [5] = "1000BASE_KX",
20 [6] = "1G_SGMII",
21 [7] = "2500BASE_T",
22 [8] = "2500BASE_X",
23 [9] = "2500BASE_KX",
24 [10] = "5GBASE_T",
25 [11] = "5GBASE_KR",
26 [12] = "10GBASE_T",
27 [13] = "10G_SFI_DA",
28 [14] = "10GBASE_SR",
29 [15] = "10GBASE_LR",
30 [16] = "10GBASE_KR_CR1",
31 [17] = "10G_SFI_AOC_ACC",
32 [18] = "10G_SFI_C2C",
33 [19] = "25GBASE_T",
34 [20] = "25GBASE_CR",
35 [21] = "25GBASE_CR_S",
36 [22] = "25GBASE_CR1",
37 [23] = "25GBASE_SR",
38 [24] = "25GBASE_LR",
39 [25] = "25GBASE_KR",
40 [26] = "25GBASE_KR_S",
41 [27] = "25GBASE_KR1",
42 [28] = "25G_AUI_AOC_ACC",
43 [29] = "25G_AUI_C2C",
44 [30] = "40GBASE_CR4",
45 [31] = "40GBASE_SR4",
46 [32] = "40GBASE_LR4",
47 [33] = "40GBASE_KR4",
48 [34] = "40G_XLAUI_AOC_ACC",
49 [35] = "40G_XLAUI",
50 [36] = "50GBASE_CR2",
51 [37] = "50GBASE_SR2",
52 [38] = "50GBASE_LR2",
53 [39] = "50GBASE_KR2",
54 [40] = "50G_LAUI2_AOC_ACC",
55 [41] = "50G_LAUI2",
56 [42] = "50G_AUI2_AOC_ACC",
57 [43] = "50G_AUI2",
58 [44] = "50GBASE_CP",
59 [45] = "50GBASE_SR",
60 [46] = "50GBASE_FR",
61 [47] = "50GBASE_LR",
62 [48] = "50GBASE_KR_PAM4",
63 [49] = "50G_AUI1_AOC_ACC",
64 [50] = "50G_AUI1",
65 [51] = "100GBASE_CR4",
66 [52] = "100GBASE_SR4",
67 [53] = "100GBASE_LR4",
68 [54] = "100GBASE_KR4",
69 [55] = "100G_CAUI4_AOC_ACC",
70 [56] = "100G_CAUI4",
71 [57] = "100G_AUI4_AOC_ACC",
72 [58] = "100G_AUI4",
73 [59] = "100GBASE_CR_PAM4",
74 [60] = "100GBASE_KR_PAM4",
75 [61] = "100GBASE_CP2",
76 [62] = "100GBASE_SR2",
77 [63] = "100GBASE_DR",
78};
79
80static const char * const ice_link_mode_str_high[] = {
81 [0] = "100GBASE_KR2_PAM4",
82 [1] = "100G_CAUI2_AOC_ACC",
83 [2] = "100G_CAUI2",
84 [3] = "100G_AUI2_AOC_ACC",
85 [4] = "100G_AUI2",
86};
87
88/**
89 * ice_dump_phy_type - helper function to dump phy_type
90 * @hw: pointer to the HW structure
91 * @low: 64 bit value for phy_type_low
92 * @high: 64 bit value for phy_type_high
93 * @prefix: prefix string to differentiate multiple dumps
94 */
95static void
96ice_dump_phy_type(struct ice_hw *hw, u64 low, u64 high, const char *prefix)
97{
98 ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_low: 0x%016llx\n", prefix, low);
99
100 for (u32 i = 0; i < BITS_PER_TYPE(typeof(low)); i++) {
101 if (low & BIT_ULL(i))
102 ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n",
103 prefix, i, ice_link_mode_str_low[i]);
104 }
105
106 ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_high: 0x%016llx\n", prefix, high);
107
108 for (u32 i = 0; i < BITS_PER_TYPE(typeof(high)); i++) {
109 if (high & BIT_ULL(i))
110 ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n",
111 prefix, i, ice_link_mode_str_high[i]);
112 }
113}
114
115/**
116 * ice_set_mac_type - Sets MAC type
117 * @hw: pointer to the HW structure
118 *
119 * This function sets the MAC type of the adapter based on the
120 * vendor ID and device ID stored in the HW structure.
121 */
122static int ice_set_mac_type(struct ice_hw *hw)
123{
124 if (hw->vendor_id != PCI_VENDOR_ID_INTEL)
125 return -ENODEV;
126
127 switch (hw->device_id) {
128 case ICE_DEV_ID_E810C_BACKPLANE:
129 case ICE_DEV_ID_E810C_QSFP:
130 case ICE_DEV_ID_E810C_SFP:
131 case ICE_DEV_ID_E810_XXV_BACKPLANE:
132 case ICE_DEV_ID_E810_XXV_QSFP:
133 case ICE_DEV_ID_E810_XXV_SFP:
134 hw->mac_type = ICE_MAC_E810;
135 break;
136 case ICE_DEV_ID_E823C_10G_BASE_T:
137 case ICE_DEV_ID_E823C_BACKPLANE:
138 case ICE_DEV_ID_E823C_QSFP:
139 case ICE_DEV_ID_E823C_SFP:
140 case ICE_DEV_ID_E823C_SGMII:
141 case ICE_DEV_ID_E822C_10G_BASE_T:
142 case ICE_DEV_ID_E822C_BACKPLANE:
143 case ICE_DEV_ID_E822C_QSFP:
144 case ICE_DEV_ID_E822C_SFP:
145 case ICE_DEV_ID_E822C_SGMII:
146 case ICE_DEV_ID_E822L_10G_BASE_T:
147 case ICE_DEV_ID_E822L_BACKPLANE:
148 case ICE_DEV_ID_E822L_SFP:
149 case ICE_DEV_ID_E822L_SGMII:
150 case ICE_DEV_ID_E823L_10G_BASE_T:
151 case ICE_DEV_ID_E823L_1GBE:
152 case ICE_DEV_ID_E823L_BACKPLANE:
153 case ICE_DEV_ID_E823L_QSFP:
154 case ICE_DEV_ID_E823L_SFP:
155 hw->mac_type = ICE_MAC_GENERIC;
156 break;
157 case ICE_DEV_ID_E825C_BACKPLANE:
158 case ICE_DEV_ID_E825C_QSFP:
159 case ICE_DEV_ID_E825C_SFP:
160 case ICE_DEV_ID_E825C_SGMII:
161 hw->mac_type = ICE_MAC_GENERIC_3K_E825;
162 break;
163 case ICE_DEV_ID_E830CC_BACKPLANE:
164 case ICE_DEV_ID_E830CC_QSFP56:
165 case ICE_DEV_ID_E830CC_SFP:
166 case ICE_DEV_ID_E830CC_SFP_DD:
167 case ICE_DEV_ID_E830C_BACKPLANE:
168 case ICE_DEV_ID_E830_XXV_BACKPLANE:
169 case ICE_DEV_ID_E830C_QSFP:
170 case ICE_DEV_ID_E830_XXV_QSFP:
171 case ICE_DEV_ID_E830C_SFP:
172 case ICE_DEV_ID_E830_XXV_SFP:
173 hw->mac_type = ICE_MAC_E830;
174 break;
175 default:
176 hw->mac_type = ICE_MAC_UNKNOWN;
177 break;
178 }
179
180 ice_debug(hw, ICE_DBG_INIT, "mac_type: %d\n", hw->mac_type);
181 return 0;
182}
183
184/**
185 * ice_is_generic_mac - check if device's mac_type is generic
186 * @hw: pointer to the hardware structure
187 *
188 * Return: true if mac_type is generic (with SBQ support), false if not
189 */
190bool ice_is_generic_mac(struct ice_hw *hw)
191{
192 return (hw->mac_type == ICE_MAC_GENERIC ||
193 hw->mac_type == ICE_MAC_GENERIC_3K_E825);
194}
195
196/**
197 * ice_is_e810
198 * @hw: pointer to the hardware structure
199 *
200 * returns true if the device is E810 based, false if not.
201 */
202bool ice_is_e810(struct ice_hw *hw)
203{
204 return hw->mac_type == ICE_MAC_E810;
205}
206
207/**
208 * ice_is_e810t
209 * @hw: pointer to the hardware structure
210 *
211 * returns true if the device is E810T based, false if not.
212 */
213bool ice_is_e810t(struct ice_hw *hw)
214{
215 switch (hw->device_id) {
216 case ICE_DEV_ID_E810C_SFP:
217 switch (hw->subsystem_device_id) {
218 case ICE_SUBDEV_ID_E810T:
219 case ICE_SUBDEV_ID_E810T2:
220 case ICE_SUBDEV_ID_E810T3:
221 case ICE_SUBDEV_ID_E810T4:
222 case ICE_SUBDEV_ID_E810T6:
223 case ICE_SUBDEV_ID_E810T7:
224 return true;
225 }
226 break;
227 case ICE_DEV_ID_E810C_QSFP:
228 switch (hw->subsystem_device_id) {
229 case ICE_SUBDEV_ID_E810T2:
230 case ICE_SUBDEV_ID_E810T3:
231 case ICE_SUBDEV_ID_E810T5:
232 return true;
233 }
234 break;
235 default:
236 break;
237 }
238
239 return false;
240}
241
242/**
243 * ice_is_e822 - Check if a device is E822 family device
244 * @hw: pointer to the hardware structure
245 *
246 * Return: true if the device is E822 based, false if not.
247 */
248bool ice_is_e822(struct ice_hw *hw)
249{
250 switch (hw->device_id) {
251 case ICE_DEV_ID_E822C_BACKPLANE:
252 case ICE_DEV_ID_E822C_QSFP:
253 case ICE_DEV_ID_E822C_SFP:
254 case ICE_DEV_ID_E822C_10G_BASE_T:
255 case ICE_DEV_ID_E822C_SGMII:
256 case ICE_DEV_ID_E822L_BACKPLANE:
257 case ICE_DEV_ID_E822L_SFP:
258 case ICE_DEV_ID_E822L_10G_BASE_T:
259 case ICE_DEV_ID_E822L_SGMII:
260 return true;
261 default:
262 return false;
263 }
264}
265
266/**
267 * ice_is_e823
268 * @hw: pointer to the hardware structure
269 *
270 * returns true if the device is E823-L or E823-C based, false if not.
271 */
272bool ice_is_e823(struct ice_hw *hw)
273{
274 switch (hw->device_id) {
275 case ICE_DEV_ID_E823L_BACKPLANE:
276 case ICE_DEV_ID_E823L_SFP:
277 case ICE_DEV_ID_E823L_10G_BASE_T:
278 case ICE_DEV_ID_E823L_1GBE:
279 case ICE_DEV_ID_E823L_QSFP:
280 case ICE_DEV_ID_E823C_BACKPLANE:
281 case ICE_DEV_ID_E823C_QSFP:
282 case ICE_DEV_ID_E823C_SFP:
283 case ICE_DEV_ID_E823C_10G_BASE_T:
284 case ICE_DEV_ID_E823C_SGMII:
285 return true;
286 default:
287 return false;
288 }
289}
290
291/**
292 * ice_is_e825c - Check if a device is E825C family device
293 * @hw: pointer to the hardware structure
294 *
295 * Return: true if the device is E825-C based, false if not.
296 */
297bool ice_is_e825c(struct ice_hw *hw)
298{
299 switch (hw->device_id) {
300 case ICE_DEV_ID_E825C_BACKPLANE:
301 case ICE_DEV_ID_E825C_QSFP:
302 case ICE_DEV_ID_E825C_SFP:
303 case ICE_DEV_ID_E825C_SGMII:
304 return true;
305 default:
306 return false;
307 }
308}
309
310/**
311 * ice_clear_pf_cfg - Clear PF configuration
312 * @hw: pointer to the hardware structure
313 *
314 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port
315 * configuration, flow director filters, etc.).
316 */
317int ice_clear_pf_cfg(struct ice_hw *hw)
318{
319 struct ice_aq_desc desc;
320
321 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg);
322
323 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
324}
325
326/**
327 * ice_aq_manage_mac_read - manage MAC address read command
328 * @hw: pointer to the HW struct
329 * @buf: a virtual buffer to hold the manage MAC read response
330 * @buf_size: Size of the virtual buffer
331 * @cd: pointer to command details structure or NULL
332 *
333 * This function is used to return per PF station MAC address (0x0107).
334 * NOTE: Upon successful completion of this command, MAC address information
335 * is returned in user specified buffer. Please interpret user specified
336 * buffer as "manage_mac_read" response.
337 * Response such as various MAC addresses are stored in HW struct (port.mac)
338 * ice_discover_dev_caps is expected to be called before this function is
339 * called.
340 */
341static int
342ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size,
343 struct ice_sq_cd *cd)
344{
345 struct ice_aqc_manage_mac_read_resp *resp;
346 struct ice_aqc_manage_mac_read *cmd;
347 struct ice_aq_desc desc;
348 int status;
349 u16 flags;
350 u8 i;
351
352 cmd = &desc.params.mac_read;
353
354 if (buf_size < sizeof(*resp))
355 return -EINVAL;
356
357 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read);
358
359 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
360 if (status)
361 return status;
362
363 resp = buf;
364 flags = le16_to_cpu(cmd->flags) & ICE_AQC_MAN_MAC_READ_M;
365
366 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) {
367 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n");
368 return -EIO;
369 }
370
371 /* A single port can report up to two (LAN and WoL) addresses */
372 for (i = 0; i < cmd->num_addr; i++)
373 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) {
374 ether_addr_copy(hw->port_info->mac.lan_addr,
375 resp[i].mac_addr);
376 ether_addr_copy(hw->port_info->mac.perm_addr,
377 resp[i].mac_addr);
378 break;
379 }
380
381 return 0;
382}
383
384/**
385 * ice_aq_get_phy_caps - returns PHY capabilities
386 * @pi: port information structure
387 * @qual_mods: report qualified modules
388 * @report_mode: report mode capabilities
389 * @pcaps: structure for PHY capabilities to be filled
390 * @cd: pointer to command details structure or NULL
391 *
392 * Returns the various PHY capabilities supported on the Port (0x0600)
393 */
394int
395ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,
396 struct ice_aqc_get_phy_caps_data *pcaps,
397 struct ice_sq_cd *cd)
398{
399 struct ice_aqc_get_phy_caps *cmd;
400 u16 pcaps_size = sizeof(*pcaps);
401 struct ice_aq_desc desc;
402 const char *prefix;
403 struct ice_hw *hw;
404 int status;
405
406 cmd = &desc.params.get_phy;
407
408 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi)
409 return -EINVAL;
410 hw = pi->hw;
411
412 if (report_mode == ICE_AQC_REPORT_DFLT_CFG &&
413 !ice_fw_supports_report_dflt_cfg(hw))
414 return -EINVAL;
415
416 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps);
417
418 if (qual_mods)
419 cmd->param0 |= cpu_to_le16(ICE_AQC_GET_PHY_RQM);
420
421 cmd->param0 |= cpu_to_le16(report_mode);
422 status = ice_aq_send_cmd(hw, &desc, pcaps, pcaps_size, cd);
423
424 ice_debug(hw, ICE_DBG_LINK, "get phy caps dump\n");
425
426 switch (report_mode) {
427 case ICE_AQC_REPORT_TOPO_CAP_MEDIA:
428 prefix = "phy_caps_media";
429 break;
430 case ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA:
431 prefix = "phy_caps_no_media";
432 break;
433 case ICE_AQC_REPORT_ACTIVE_CFG:
434 prefix = "phy_caps_active";
435 break;
436 case ICE_AQC_REPORT_DFLT_CFG:
437 prefix = "phy_caps_default";
438 break;
439 default:
440 prefix = "phy_caps_invalid";
441 }
442
443 ice_dump_phy_type(hw, le64_to_cpu(pcaps->phy_type_low),
444 le64_to_cpu(pcaps->phy_type_high), prefix);
445
446 ice_debug(hw, ICE_DBG_LINK, "%s: report_mode = 0x%x\n",
447 prefix, report_mode);
448 ice_debug(hw, ICE_DBG_LINK, "%s: caps = 0x%x\n", prefix, pcaps->caps);
449 ice_debug(hw, ICE_DBG_LINK, "%s: low_power_ctrl_an = 0x%x\n", prefix,
450 pcaps->low_power_ctrl_an);
451 ice_debug(hw, ICE_DBG_LINK, "%s: eee_cap = 0x%x\n", prefix,
452 pcaps->eee_cap);
453 ice_debug(hw, ICE_DBG_LINK, "%s: eeer_value = 0x%x\n", prefix,
454 pcaps->eeer_value);
455 ice_debug(hw, ICE_DBG_LINK, "%s: link_fec_options = 0x%x\n", prefix,
456 pcaps->link_fec_options);
457 ice_debug(hw, ICE_DBG_LINK, "%s: module_compliance_enforcement = 0x%x\n",
458 prefix, pcaps->module_compliance_enforcement);
459 ice_debug(hw, ICE_DBG_LINK, "%s: extended_compliance_code = 0x%x\n",
460 prefix, pcaps->extended_compliance_code);
461 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[0] = 0x%x\n", prefix,
462 pcaps->module_type[0]);
463 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[1] = 0x%x\n", prefix,
464 pcaps->module_type[1]);
465 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[2] = 0x%x\n", prefix,
466 pcaps->module_type[2]);
467
468 if (!status && report_mode == ICE_AQC_REPORT_TOPO_CAP_MEDIA) {
469 pi->phy.phy_type_low = le64_to_cpu(pcaps->phy_type_low);
470 pi->phy.phy_type_high = le64_to_cpu(pcaps->phy_type_high);
471 memcpy(pi->phy.link_info.module_type, &pcaps->module_type,
472 sizeof(pi->phy.link_info.module_type));
473 }
474
475 return status;
476}
477
478/**
479 * ice_aq_get_link_topo_handle - get link topology node return status
480 * @pi: port information structure
481 * @node_type: requested node type
482 * @cd: pointer to command details structure or NULL
483 *
484 * Get link topology node return status for specified node type (0x06E0)
485 *
486 * Node type cage can be used to determine if cage is present. If AQC
487 * returns error (ENOENT), then no cage present. If no cage present, then
488 * connection type is backplane or BASE-T.
489 */
490static int
491ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type,
492 struct ice_sq_cd *cd)
493{
494 struct ice_aqc_get_link_topo *cmd;
495 struct ice_aq_desc desc;
496
497 cmd = &desc.params.get_link_topo;
498
499 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo);
500
501 cmd->addr.topo_params.node_type_ctx =
502 (ICE_AQC_LINK_TOPO_NODE_CTX_PORT <<
503 ICE_AQC_LINK_TOPO_NODE_CTX_S);
504
505 /* set node type */
506 cmd->addr.topo_params.node_type_ctx |=
507 (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type);
508
509 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
510}
511
512/**
513 * ice_aq_get_netlist_node
514 * @hw: pointer to the hw struct
515 * @cmd: get_link_topo AQ structure
516 * @node_part_number: output node part number if node found
517 * @node_handle: output node handle parameter if node found
518 *
519 * Get netlist node handle.
520 */
521int
522ice_aq_get_netlist_node(struct ice_hw *hw, struct ice_aqc_get_link_topo *cmd,
523 u8 *node_part_number, u16 *node_handle)
524{
525 struct ice_aq_desc desc;
526
527 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo);
528 desc.params.get_link_topo = *cmd;
529
530 if (ice_aq_send_cmd(hw, &desc, NULL, 0, NULL))
531 return -EINTR;
532
533 if (node_handle)
534 *node_handle =
535 le16_to_cpu(desc.params.get_link_topo.addr.handle);
536 if (node_part_number)
537 *node_part_number = desc.params.get_link_topo.node_part_num;
538
539 return 0;
540}
541
542/**
543 * ice_find_netlist_node
544 * @hw: pointer to the hw struct
545 * @node_type: type of netlist node to look for
546 * @ctx: context of the search
547 * @node_part_number: node part number to look for
548 * @node_handle: output parameter if node found - optional
549 *
550 * Scan the netlist for a node handle of the given node type and part number.
551 *
552 * If node_handle is non-NULL it will be modified on function exit. It is only
553 * valid if the function returns zero, and should be ignored on any non-zero
554 * return value.
555 *
556 * Return:
557 * * 0 if the node is found,
558 * * -ENOENT if no handle was found,
559 * * negative error code on failure to access the AQ.
560 */
561static int ice_find_netlist_node(struct ice_hw *hw, u8 node_type, u8 ctx,
562 u8 node_part_number, u16 *node_handle)
563{
564 u8 idx;
565
566 for (idx = 0; idx < ICE_MAX_NETLIST_SIZE; idx++) {
567 struct ice_aqc_get_link_topo cmd = {};
568 u8 rec_node_part_number;
569 int status;
570
571 cmd.addr.topo_params.node_type_ctx =
572 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_TYPE_M, node_type) |
573 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_CTX_M, ctx);
574 cmd.addr.topo_params.index = idx;
575
576 status = ice_aq_get_netlist_node(hw, &cmd,
577 &rec_node_part_number,
578 node_handle);
579 if (status)
580 return status;
581
582 if (rec_node_part_number == node_part_number)
583 return 0;
584 }
585
586 return -ENOENT;
587}
588
589/**
590 * ice_is_media_cage_present
591 * @pi: port information structure
592 *
593 * Returns true if media cage is present, else false. If no cage, then
594 * media type is backplane or BASE-T.
595 */
596static bool ice_is_media_cage_present(struct ice_port_info *pi)
597{
598 /* Node type cage can be used to determine if cage is present. If AQC
599 * returns error (ENOENT), then no cage present. If no cage present then
600 * connection type is backplane or BASE-T.
601 */
602 return !ice_aq_get_link_topo_handle(pi,
603 ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE,
604 NULL);
605}
606
607/**
608 * ice_get_media_type - Gets media type
609 * @pi: port information structure
610 */
611static enum ice_media_type ice_get_media_type(struct ice_port_info *pi)
612{
613 struct ice_link_status *hw_link_info;
614
615 if (!pi)
616 return ICE_MEDIA_UNKNOWN;
617
618 hw_link_info = &pi->phy.link_info;
619 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high)
620 /* If more than one media type is selected, report unknown */
621 return ICE_MEDIA_UNKNOWN;
622
623 if (hw_link_info->phy_type_low) {
624 /* 1G SGMII is a special case where some DA cable PHYs
625 * may show this as an option when it really shouldn't
626 * be since SGMII is meant to be between a MAC and a PHY
627 * in a backplane. Try to detect this case and handle it
628 */
629 if (hw_link_info->phy_type_low == ICE_PHY_TYPE_LOW_1G_SGMII &&
630 (hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] ==
631 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE ||
632 hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] ==
633 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE))
634 return ICE_MEDIA_DA;
635
636 switch (hw_link_info->phy_type_low) {
637 case ICE_PHY_TYPE_LOW_1000BASE_SX:
638 case ICE_PHY_TYPE_LOW_1000BASE_LX:
639 case ICE_PHY_TYPE_LOW_10GBASE_SR:
640 case ICE_PHY_TYPE_LOW_10GBASE_LR:
641 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
642 case ICE_PHY_TYPE_LOW_25GBASE_SR:
643 case ICE_PHY_TYPE_LOW_25GBASE_LR:
644 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
645 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
646 case ICE_PHY_TYPE_LOW_50GBASE_SR2:
647 case ICE_PHY_TYPE_LOW_50GBASE_LR2:
648 case ICE_PHY_TYPE_LOW_50GBASE_SR:
649 case ICE_PHY_TYPE_LOW_50GBASE_FR:
650 case ICE_PHY_TYPE_LOW_50GBASE_LR:
651 case ICE_PHY_TYPE_LOW_100GBASE_SR4:
652 case ICE_PHY_TYPE_LOW_100GBASE_LR4:
653 case ICE_PHY_TYPE_LOW_100GBASE_SR2:
654 case ICE_PHY_TYPE_LOW_100GBASE_DR:
655 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC:
656 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC:
657 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC:
658 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC:
659 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC:
660 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC:
661 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC:
662 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC:
663 return ICE_MEDIA_FIBER;
664 case ICE_PHY_TYPE_LOW_100BASE_TX:
665 case ICE_PHY_TYPE_LOW_1000BASE_T:
666 case ICE_PHY_TYPE_LOW_2500BASE_T:
667 case ICE_PHY_TYPE_LOW_5GBASE_T:
668 case ICE_PHY_TYPE_LOW_10GBASE_T:
669 case ICE_PHY_TYPE_LOW_25GBASE_T:
670 return ICE_MEDIA_BASET;
671 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
672 case ICE_PHY_TYPE_LOW_25GBASE_CR:
673 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
674 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
675 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
676 case ICE_PHY_TYPE_LOW_50GBASE_CR2:
677 case ICE_PHY_TYPE_LOW_50GBASE_CP:
678 case ICE_PHY_TYPE_LOW_100GBASE_CR4:
679 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
680 case ICE_PHY_TYPE_LOW_100GBASE_CP2:
681 return ICE_MEDIA_DA;
682 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
683 case ICE_PHY_TYPE_LOW_40G_XLAUI:
684 case ICE_PHY_TYPE_LOW_50G_LAUI2:
685 case ICE_PHY_TYPE_LOW_50G_AUI2:
686 case ICE_PHY_TYPE_LOW_50G_AUI1:
687 case ICE_PHY_TYPE_LOW_100G_AUI4:
688 case ICE_PHY_TYPE_LOW_100G_CAUI4:
689 if (ice_is_media_cage_present(pi))
690 return ICE_MEDIA_DA;
691 fallthrough;
692 case ICE_PHY_TYPE_LOW_1000BASE_KX:
693 case ICE_PHY_TYPE_LOW_2500BASE_KX:
694 case ICE_PHY_TYPE_LOW_2500BASE_X:
695 case ICE_PHY_TYPE_LOW_5GBASE_KR:
696 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
697 case ICE_PHY_TYPE_LOW_25GBASE_KR:
698 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
699 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
700 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
701 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
702 case ICE_PHY_TYPE_LOW_50GBASE_KR2:
703 case ICE_PHY_TYPE_LOW_100GBASE_KR4:
704 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
705 return ICE_MEDIA_BACKPLANE;
706 }
707 } else {
708 switch (hw_link_info->phy_type_high) {
709 case ICE_PHY_TYPE_HIGH_100G_AUI2:
710 case ICE_PHY_TYPE_HIGH_100G_CAUI2:
711 if (ice_is_media_cage_present(pi))
712 return ICE_MEDIA_DA;
713 fallthrough;
714 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
715 return ICE_MEDIA_BACKPLANE;
716 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC:
717 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC:
718 return ICE_MEDIA_FIBER;
719 }
720 }
721 return ICE_MEDIA_UNKNOWN;
722}
723
724/**
725 * ice_get_link_status_datalen
726 * @hw: pointer to the HW struct
727 *
728 * Returns datalength for the Get Link Status AQ command, which is bigger for
729 * newer adapter families handled by ice driver.
730 */
731static u16 ice_get_link_status_datalen(struct ice_hw *hw)
732{
733 switch (hw->mac_type) {
734 case ICE_MAC_E830:
735 return ICE_AQC_LS_DATA_SIZE_V2;
736 case ICE_MAC_E810:
737 default:
738 return ICE_AQC_LS_DATA_SIZE_V1;
739 }
740}
741
742/**
743 * ice_aq_get_link_info
744 * @pi: port information structure
745 * @ena_lse: enable/disable LinkStatusEvent reporting
746 * @link: pointer to link status structure - optional
747 * @cd: pointer to command details structure or NULL
748 *
749 * Get Link Status (0x607). Returns the link status of the adapter.
750 */
751int
752ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
753 struct ice_link_status *link, struct ice_sq_cd *cd)
754{
755 struct ice_aqc_get_link_status_data link_data = { 0 };
756 struct ice_aqc_get_link_status *resp;
757 struct ice_link_status *li_old, *li;
758 enum ice_media_type *hw_media_type;
759 struct ice_fc_info *hw_fc_info;
760 bool tx_pause, rx_pause;
761 struct ice_aq_desc desc;
762 struct ice_hw *hw;
763 u16 cmd_flags;
764 int status;
765
766 if (!pi)
767 return -EINVAL;
768 hw = pi->hw;
769 li_old = &pi->phy.link_info_old;
770 hw_media_type = &pi->phy.media_type;
771 li = &pi->phy.link_info;
772 hw_fc_info = &pi->fc;
773
774 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status);
775 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS;
776 resp = &desc.params.get_link_status;
777 resp->cmd_flags = cpu_to_le16(cmd_flags);
778 resp->lport_num = pi->lport;
779
780 status = ice_aq_send_cmd(hw, &desc, &link_data,
781 ice_get_link_status_datalen(hw), cd);
782 if (status)
783 return status;
784
785 /* save off old link status information */
786 *li_old = *li;
787
788 /* update current link status information */
789 li->link_speed = le16_to_cpu(link_data.link_speed);
790 li->phy_type_low = le64_to_cpu(link_data.phy_type_low);
791 li->phy_type_high = le64_to_cpu(link_data.phy_type_high);
792 *hw_media_type = ice_get_media_type(pi);
793 li->link_info = link_data.link_info;
794 li->link_cfg_err = link_data.link_cfg_err;
795 li->an_info = link_data.an_info;
796 li->ext_info = link_data.ext_info;
797 li->max_frame_size = le16_to_cpu(link_data.max_frame_size);
798 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK;
799 li->topo_media_conflict = link_data.topo_media_conflict;
800 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M |
801 ICE_AQ_CFG_PACING_TYPE_M);
802
803 /* update fc info */
804 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX);
805 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX);
806 if (tx_pause && rx_pause)
807 hw_fc_info->current_mode = ICE_FC_FULL;
808 else if (tx_pause)
809 hw_fc_info->current_mode = ICE_FC_TX_PAUSE;
810 else if (rx_pause)
811 hw_fc_info->current_mode = ICE_FC_RX_PAUSE;
812 else
813 hw_fc_info->current_mode = ICE_FC_NONE;
814
815 li->lse_ena = !!(resp->cmd_flags & cpu_to_le16(ICE_AQ_LSE_IS_ENABLED));
816
817 ice_debug(hw, ICE_DBG_LINK, "get link info\n");
818 ice_debug(hw, ICE_DBG_LINK, " link_speed = 0x%x\n", li->link_speed);
819 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n",
820 (unsigned long long)li->phy_type_low);
821 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n",
822 (unsigned long long)li->phy_type_high);
823 ice_debug(hw, ICE_DBG_LINK, " media_type = 0x%x\n", *hw_media_type);
824 ice_debug(hw, ICE_DBG_LINK, " link_info = 0x%x\n", li->link_info);
825 ice_debug(hw, ICE_DBG_LINK, " link_cfg_err = 0x%x\n", li->link_cfg_err);
826 ice_debug(hw, ICE_DBG_LINK, " an_info = 0x%x\n", li->an_info);
827 ice_debug(hw, ICE_DBG_LINK, " ext_info = 0x%x\n", li->ext_info);
828 ice_debug(hw, ICE_DBG_LINK, " fec_info = 0x%x\n", li->fec_info);
829 ice_debug(hw, ICE_DBG_LINK, " lse_ena = 0x%x\n", li->lse_ena);
830 ice_debug(hw, ICE_DBG_LINK, " max_frame = 0x%x\n",
831 li->max_frame_size);
832 ice_debug(hw, ICE_DBG_LINK, " pacing = 0x%x\n", li->pacing);
833
834 /* save link status information */
835 if (link)
836 *link = *li;
837
838 /* flag cleared so calling functions don't call AQ again */
839 pi->phy.get_link_info = false;
840
841 return 0;
842}
843
844/**
845 * ice_fill_tx_timer_and_fc_thresh
846 * @hw: pointer to the HW struct
847 * @cmd: pointer to MAC cfg structure
848 *
849 * Add Tx timer and FC refresh threshold info to Set MAC Config AQ command
850 * descriptor
851 */
852static void
853ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw,
854 struct ice_aqc_set_mac_cfg *cmd)
855{
856 u32 val, fc_thres_m;
857
858 /* We read back the transmit timer and FC threshold value of
859 * LFC. Thus, we will use index =
860 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX.
861 *
862 * Also, because we are operating on transmit timer and FC
863 * threshold of LFC, we don't turn on any bit in tx_tmr_priority
864 */
865#define E800_IDX_OF_LFC E800_PRTMAC_HSEC_CTL_TX_PS_QNT_MAX
866#define E800_REFRESH_TMR E800_PRTMAC_HSEC_CTL_TX_PS_RFSH_TMR
867
868 if (hw->mac_type == ICE_MAC_E830) {
869 /* Retrieve the transmit timer */
870 val = rd32(hw, E830_PRTMAC_CL01_PS_QNT);
871 cmd->tx_tmr_value =
872 le16_encode_bits(val, E830_PRTMAC_CL01_PS_QNT_CL0_M);
873
874 /* Retrieve the fc threshold */
875 val = rd32(hw, E830_PRTMAC_CL01_QNT_THR);
876 fc_thres_m = E830_PRTMAC_CL01_QNT_THR_CL0_M;
877 } else {
878 /* Retrieve the transmit timer */
879 val = rd32(hw,
880 E800_PRTMAC_HSEC_CTL_TX_PS_QNT(E800_IDX_OF_LFC));
881 cmd->tx_tmr_value =
882 le16_encode_bits(val,
883 E800_PRTMAC_HSEC_CTL_TX_PS_QNT_M);
884
885 /* Retrieve the fc threshold */
886 val = rd32(hw,
887 E800_REFRESH_TMR(E800_IDX_OF_LFC));
888 fc_thres_m = E800_PRTMAC_HSEC_CTL_TX_PS_RFSH_TMR_M;
889 }
890 cmd->fc_refresh_threshold = le16_encode_bits(val, fc_thres_m);
891}
892
893/**
894 * ice_aq_set_mac_cfg
895 * @hw: pointer to the HW struct
896 * @max_frame_size: Maximum Frame Size to be supported
897 * @cd: pointer to command details structure or NULL
898 *
899 * Set MAC configuration (0x0603)
900 */
901int
902ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd)
903{
904 struct ice_aqc_set_mac_cfg *cmd;
905 struct ice_aq_desc desc;
906
907 cmd = &desc.params.set_mac_cfg;
908
909 if (max_frame_size == 0)
910 return -EINVAL;
911
912 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg);
913
914 cmd->max_frame_size = cpu_to_le16(max_frame_size);
915
916 ice_fill_tx_timer_and_fc_thresh(hw, cmd);
917
918 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
919}
920
921/**
922 * ice_init_fltr_mgmt_struct - initializes filter management list and locks
923 * @hw: pointer to the HW struct
924 */
925static int ice_init_fltr_mgmt_struct(struct ice_hw *hw)
926{
927 struct ice_switch_info *sw;
928 int status;
929
930 hw->switch_info = devm_kzalloc(ice_hw_to_dev(hw),
931 sizeof(*hw->switch_info), GFP_KERNEL);
932 sw = hw->switch_info;
933
934 if (!sw)
935 return -ENOMEM;
936
937 INIT_LIST_HEAD(&sw->vsi_list_map_head);
938 sw->prof_res_bm_init = 0;
939
940 /* Initialize recipe count with default recipes read from NVM */
941 sw->recp_cnt = ICE_SW_LKUP_LAST;
942
943 status = ice_init_def_sw_recp(hw);
944 if (status) {
945 devm_kfree(ice_hw_to_dev(hw), hw->switch_info);
946 return status;
947 }
948 return 0;
949}
950
951/**
952 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks
953 * @hw: pointer to the HW struct
954 */
955static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw)
956{
957 struct ice_switch_info *sw = hw->switch_info;
958 struct ice_vsi_list_map_info *v_pos_map;
959 struct ice_vsi_list_map_info *v_tmp_map;
960 struct ice_sw_recipe *recps;
961 u8 i;
962
963 list_for_each_entry_safe(v_pos_map, v_tmp_map, &sw->vsi_list_map_head,
964 list_entry) {
965 list_del(&v_pos_map->list_entry);
966 devm_kfree(ice_hw_to_dev(hw), v_pos_map);
967 }
968 recps = sw->recp_list;
969 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) {
970 recps[i].root_rid = i;
971
972 if (recps[i].adv_rule) {
973 struct ice_adv_fltr_mgmt_list_entry *tmp_entry;
974 struct ice_adv_fltr_mgmt_list_entry *lst_itr;
975
976 mutex_destroy(&recps[i].filt_rule_lock);
977 list_for_each_entry_safe(lst_itr, tmp_entry,
978 &recps[i].filt_rules,
979 list_entry) {
980 list_del(&lst_itr->list_entry);
981 devm_kfree(ice_hw_to_dev(hw), lst_itr->lkups);
982 devm_kfree(ice_hw_to_dev(hw), lst_itr);
983 }
984 } else {
985 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry;
986
987 mutex_destroy(&recps[i].filt_rule_lock);
988 list_for_each_entry_safe(lst_itr, tmp_entry,
989 &recps[i].filt_rules,
990 list_entry) {
991 list_del(&lst_itr->list_entry);
992 devm_kfree(ice_hw_to_dev(hw), lst_itr);
993 }
994 }
995 }
996 ice_rm_all_sw_replay_rule_info(hw);
997 devm_kfree(ice_hw_to_dev(hw), sw->recp_list);
998 devm_kfree(ice_hw_to_dev(hw), sw);
999}
1000
1001/**
1002 * ice_get_itr_intrl_gran
1003 * @hw: pointer to the HW struct
1004 *
1005 * Determines the ITR/INTRL granularities based on the maximum aggregate
1006 * bandwidth according to the device's configuration during power-on.
1007 */
1008static void ice_get_itr_intrl_gran(struct ice_hw *hw)
1009{
1010 u8 max_agg_bw = FIELD_GET(GL_PWR_MODE_CTL_CAR_MAX_BW_M,
1011 rd32(hw, GL_PWR_MODE_CTL));
1012
1013 switch (max_agg_bw) {
1014 case ICE_MAX_AGG_BW_200G:
1015 case ICE_MAX_AGG_BW_100G:
1016 case ICE_MAX_AGG_BW_50G:
1017 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25;
1018 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25;
1019 break;
1020 case ICE_MAX_AGG_BW_25G:
1021 hw->itr_gran = ICE_ITR_GRAN_MAX_25;
1022 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25;
1023 break;
1024 }
1025}
1026
1027/**
1028 * ice_init_hw - main hardware initialization routine
1029 * @hw: pointer to the hardware structure
1030 */
1031int ice_init_hw(struct ice_hw *hw)
1032{
1033 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL;
1034 void *mac_buf __free(kfree) = NULL;
1035 u16 mac_buf_len;
1036 int status;
1037
1038 /* Set MAC type based on DeviceID */
1039 status = ice_set_mac_type(hw);
1040 if (status)
1041 return status;
1042
1043 hw->pf_id = FIELD_GET(PF_FUNC_RID_FUNC_NUM_M, rd32(hw, PF_FUNC_RID));
1044
1045 status = ice_reset(hw, ICE_RESET_PFR);
1046 if (status)
1047 return status;
1048
1049 ice_get_itr_intrl_gran(hw);
1050
1051 status = ice_create_all_ctrlq(hw);
1052 if (status)
1053 goto err_unroll_cqinit;
1054
1055 status = ice_fwlog_init(hw);
1056 if (status)
1057 ice_debug(hw, ICE_DBG_FW_LOG, "Error initializing FW logging: %d\n",
1058 status);
1059
1060 status = ice_clear_pf_cfg(hw);
1061 if (status)
1062 goto err_unroll_cqinit;
1063
1064 /* Set bit to enable Flow Director filters */
1065 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M);
1066 INIT_LIST_HEAD(&hw->fdir_list_head);
1067
1068 ice_clear_pxe_mode(hw);
1069
1070 status = ice_init_nvm(hw);
1071 if (status)
1072 goto err_unroll_cqinit;
1073
1074 status = ice_get_caps(hw);
1075 if (status)
1076 goto err_unroll_cqinit;
1077
1078 if (!hw->port_info)
1079 hw->port_info = devm_kzalloc(ice_hw_to_dev(hw),
1080 sizeof(*hw->port_info),
1081 GFP_KERNEL);
1082 if (!hw->port_info) {
1083 status = -ENOMEM;
1084 goto err_unroll_cqinit;
1085 }
1086
1087 hw->port_info->local_fwd_mode = ICE_LOCAL_FWD_MODE_ENABLED;
1088 /* set the back pointer to HW */
1089 hw->port_info->hw = hw;
1090
1091 /* Initialize port_info struct with switch configuration data */
1092 status = ice_get_initial_sw_cfg(hw);
1093 if (status)
1094 goto err_unroll_alloc;
1095
1096 hw->evb_veb = true;
1097
1098 /* init xarray for identifying scheduling nodes uniquely */
1099 xa_init_flags(&hw->port_info->sched_node_ids, XA_FLAGS_ALLOC);
1100
1101 /* Query the allocated resources for Tx scheduler */
1102 status = ice_sched_query_res_alloc(hw);
1103 if (status) {
1104 ice_debug(hw, ICE_DBG_SCHED, "Failed to get scheduler allocated resources\n");
1105 goto err_unroll_alloc;
1106 }
1107 ice_sched_get_psm_clk_freq(hw);
1108
1109 /* Initialize port_info struct with scheduler data */
1110 status = ice_sched_init_port(hw->port_info);
1111 if (status)
1112 goto err_unroll_sched;
1113
1114 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL);
1115 if (!pcaps) {
1116 status = -ENOMEM;
1117 goto err_unroll_sched;
1118 }
1119
1120 /* Initialize port_info struct with PHY capabilities */
1121 status = ice_aq_get_phy_caps(hw->port_info, false,
1122 ICE_AQC_REPORT_TOPO_CAP_MEDIA, pcaps,
1123 NULL);
1124 if (status)
1125 dev_warn(ice_hw_to_dev(hw), "Get PHY capabilities failed status = %d, continuing anyway\n",
1126 status);
1127
1128 /* Initialize port_info struct with link information */
1129 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL);
1130 if (status)
1131 goto err_unroll_sched;
1132
1133 /* need a valid SW entry point to build a Tx tree */
1134 if (!hw->sw_entry_point_layer) {
1135 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n");
1136 status = -EIO;
1137 goto err_unroll_sched;
1138 }
1139 INIT_LIST_HEAD(&hw->agg_list);
1140 /* Initialize max burst size */
1141 if (!hw->max_burst_size)
1142 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE);
1143
1144 status = ice_init_fltr_mgmt_struct(hw);
1145 if (status)
1146 goto err_unroll_sched;
1147
1148 /* Get MAC information */
1149 /* A single port can report up to two (LAN and WoL) addresses */
1150 mac_buf = kcalloc(2, sizeof(struct ice_aqc_manage_mac_read_resp),
1151 GFP_KERNEL);
1152 if (!mac_buf) {
1153 status = -ENOMEM;
1154 goto err_unroll_fltr_mgmt_struct;
1155 }
1156
1157 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp);
1158 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL);
1159
1160 if (status)
1161 goto err_unroll_fltr_mgmt_struct;
1162 /* enable jumbo frame support at MAC level */
1163 status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL);
1164 if (status)
1165 goto err_unroll_fltr_mgmt_struct;
1166 /* Obtain counter base index which would be used by flow director */
1167 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base);
1168 if (status)
1169 goto err_unroll_fltr_mgmt_struct;
1170 status = ice_init_hw_tbls(hw);
1171 if (status)
1172 goto err_unroll_fltr_mgmt_struct;
1173 mutex_init(&hw->tnl_lock);
1174 ice_init_chk_recipe_reuse_support(hw);
1175
1176 return 0;
1177
1178err_unroll_fltr_mgmt_struct:
1179 ice_cleanup_fltr_mgmt_struct(hw);
1180err_unroll_sched:
1181 ice_sched_cleanup_all(hw);
1182err_unroll_alloc:
1183 devm_kfree(ice_hw_to_dev(hw), hw->port_info);
1184err_unroll_cqinit:
1185 ice_destroy_all_ctrlq(hw);
1186 return status;
1187}
1188
1189/**
1190 * ice_deinit_hw - unroll initialization operations done by ice_init_hw
1191 * @hw: pointer to the hardware structure
1192 *
1193 * This should be called only during nominal operation, not as a result of
1194 * ice_init_hw() failing since ice_init_hw() will take care of unrolling
1195 * applicable initializations if it fails for any reason.
1196 */
1197void ice_deinit_hw(struct ice_hw *hw)
1198{
1199 ice_free_fd_res_cntr(hw, hw->fd_ctr_base);
1200 ice_cleanup_fltr_mgmt_struct(hw);
1201
1202 ice_sched_cleanup_all(hw);
1203 ice_sched_clear_agg(hw);
1204 ice_free_seg(hw);
1205 ice_free_hw_tbls(hw);
1206 mutex_destroy(&hw->tnl_lock);
1207
1208 ice_fwlog_deinit(hw);
1209 ice_destroy_all_ctrlq(hw);
1210
1211 /* Clear VSI contexts if not already cleared */
1212 ice_clear_all_vsi_ctx(hw);
1213}
1214
1215/**
1216 * ice_check_reset - Check to see if a global reset is complete
1217 * @hw: pointer to the hardware structure
1218 */
1219int ice_check_reset(struct ice_hw *hw)
1220{
1221 u32 cnt, reg = 0, grst_timeout, uld_mask;
1222
1223 /* Poll for Device Active state in case a recent CORER, GLOBR,
1224 * or EMPR has occurred. The grst delay value is in 100ms units.
1225 * Add 1sec for outstanding AQ commands that can take a long time.
1226 */
1227 grst_timeout = FIELD_GET(GLGEN_RSTCTL_GRSTDEL_M,
1228 rd32(hw, GLGEN_RSTCTL)) + 10;
1229
1230 for (cnt = 0; cnt < grst_timeout; cnt++) {
1231 mdelay(100);
1232 reg = rd32(hw, GLGEN_RSTAT);
1233 if (!(reg & GLGEN_RSTAT_DEVSTATE_M))
1234 break;
1235 }
1236
1237 if (cnt == grst_timeout) {
1238 ice_debug(hw, ICE_DBG_INIT, "Global reset polling failed to complete.\n");
1239 return -EIO;
1240 }
1241
1242#define ICE_RESET_DONE_MASK (GLNVM_ULD_PCIER_DONE_M |\
1243 GLNVM_ULD_PCIER_DONE_1_M |\
1244 GLNVM_ULD_CORER_DONE_M |\
1245 GLNVM_ULD_GLOBR_DONE_M |\
1246 GLNVM_ULD_POR_DONE_M |\
1247 GLNVM_ULD_POR_DONE_1_M |\
1248 GLNVM_ULD_PCIER_DONE_2_M)
1249
1250 uld_mask = ICE_RESET_DONE_MASK | (hw->func_caps.common_cap.rdma ?
1251 GLNVM_ULD_PE_DONE_M : 0);
1252
1253 /* Device is Active; check Global Reset processes are done */
1254 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {
1255 reg = rd32(hw, GLNVM_ULD) & uld_mask;
1256 if (reg == uld_mask) {
1257 ice_debug(hw, ICE_DBG_INIT, "Global reset processes done. %d\n", cnt);
1258 break;
1259 }
1260 mdelay(10);
1261 }
1262
1263 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
1264 ice_debug(hw, ICE_DBG_INIT, "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n",
1265 reg);
1266 return -EIO;
1267 }
1268
1269 return 0;
1270}
1271
1272/**
1273 * ice_pf_reset - Reset the PF
1274 * @hw: pointer to the hardware structure
1275 *
1276 * If a global reset has been triggered, this function checks
1277 * for its completion and then issues the PF reset
1278 */
1279static int ice_pf_reset(struct ice_hw *hw)
1280{
1281 u32 cnt, reg;
1282
1283 /* If at function entry a global reset was already in progress, i.e.
1284 * state is not 'device active' or any of the reset done bits are not
1285 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the
1286 * global reset is done.
1287 */
1288 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) ||
1289 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) {
1290 /* poll on global reset currently in progress until done */
1291 if (ice_check_reset(hw))
1292 return -EIO;
1293
1294 return 0;
1295 }
1296
1297 /* Reset the PF */
1298 reg = rd32(hw, PFGEN_CTRL);
1299
1300 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M));
1301
1302 /* Wait for the PFR to complete. The wait time is the global config lock
1303 * timeout plus the PFR timeout which will account for a possible reset
1304 * that is occurring during a download package operation.
1305 */
1306 for (cnt = 0; cnt < ICE_GLOBAL_CFG_LOCK_TIMEOUT +
1307 ICE_PF_RESET_WAIT_COUNT; cnt++) {
1308 reg = rd32(hw, PFGEN_CTRL);
1309 if (!(reg & PFGEN_CTRL_PFSWR_M))
1310 break;
1311
1312 mdelay(1);
1313 }
1314
1315 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
1316 ice_debug(hw, ICE_DBG_INIT, "PF reset polling failed to complete.\n");
1317 return -EIO;
1318 }
1319
1320 return 0;
1321}
1322
1323/**
1324 * ice_reset - Perform different types of reset
1325 * @hw: pointer to the hardware structure
1326 * @req: reset request
1327 *
1328 * This function triggers a reset as specified by the req parameter.
1329 *
1330 * Note:
1331 * If anything other than a PF reset is triggered, PXE mode is restored.
1332 * This has to be cleared using ice_clear_pxe_mode again, once the AQ
1333 * interface has been restored in the rebuild flow.
1334 */
1335int ice_reset(struct ice_hw *hw, enum ice_reset_req req)
1336{
1337 u32 val = 0;
1338
1339 switch (req) {
1340 case ICE_RESET_PFR:
1341 return ice_pf_reset(hw);
1342 case ICE_RESET_CORER:
1343 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n");
1344 val = GLGEN_RTRIG_CORER_M;
1345 break;
1346 case ICE_RESET_GLOBR:
1347 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n");
1348 val = GLGEN_RTRIG_GLOBR_M;
1349 break;
1350 default:
1351 return -EINVAL;
1352 }
1353
1354 val |= rd32(hw, GLGEN_RTRIG);
1355 wr32(hw, GLGEN_RTRIG, val);
1356 ice_flush(hw);
1357
1358 /* wait for the FW to be ready */
1359 return ice_check_reset(hw);
1360}
1361
1362/**
1363 * ice_copy_rxq_ctx_to_hw
1364 * @hw: pointer to the hardware structure
1365 * @ice_rxq_ctx: pointer to the rxq context
1366 * @rxq_index: the index of the Rx queue
1367 *
1368 * Copies rxq context from dense structure to HW register space
1369 */
1370static int
1371ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index)
1372{
1373 u8 i;
1374
1375 if (!ice_rxq_ctx)
1376 return -EINVAL;
1377
1378 if (rxq_index > QRX_CTRL_MAX_INDEX)
1379 return -EINVAL;
1380
1381 /* Copy each dword separately to HW */
1382 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) {
1383 wr32(hw, QRX_CONTEXT(i, rxq_index),
1384 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
1385
1386 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i,
1387 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
1388 }
1389
1390 return 0;
1391}
1392
1393/* LAN Rx Queue Context */
1394static const struct ice_ctx_ele ice_rlan_ctx_info[] = {
1395 /* Field Width LSB */
1396 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0),
1397 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13),
1398 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32),
1399 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89),
1400 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102),
1401 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109),
1402 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114),
1403 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116),
1404 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117),
1405 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119),
1406 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120),
1407 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124),
1408 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127),
1409 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174),
1410 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193),
1411 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194),
1412 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195),
1413 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196),
1414 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198),
1415 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201),
1416 { 0 }
1417};
1418
1419/**
1420 * ice_write_rxq_ctx
1421 * @hw: pointer to the hardware structure
1422 * @rlan_ctx: pointer to the rxq context
1423 * @rxq_index: the index of the Rx queue
1424 *
1425 * Converts rxq context from sparse to dense structure and then writes
1426 * it to HW register space and enables the hardware to prefetch descriptors
1427 * instead of only fetching them on demand
1428 */
1429int ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
1430 u32 rxq_index)
1431{
1432 u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 };
1433
1434 if (!rlan_ctx)
1435 return -EINVAL;
1436
1437 rlan_ctx->prefena = 1;
1438
1439 ice_set_ctx(hw, (u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info);
1440 return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index);
1441}
1442
1443/* LAN Tx Queue Context */
1444const struct ice_ctx_ele ice_tlan_ctx_info[] = {
1445 /* Field Width LSB */
1446 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0),
1447 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57),
1448 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60),
1449 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65),
1450 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68),
1451 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78),
1452 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80),
1453 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90),
1454 ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91),
1455 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92),
1456 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93),
1457 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101),
1458 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102),
1459 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103),
1460 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104),
1461 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105),
1462 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114),
1463 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128),
1464 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129),
1465 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135),
1466 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148),
1467 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152),
1468 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153),
1469 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164),
1470 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165),
1471 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166),
1472 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168),
1473 ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 122, 171),
1474 { 0 }
1475};
1476
1477/* Sideband Queue command wrappers */
1478
1479/**
1480 * ice_sbq_send_cmd - send Sideband Queue command to Sideband Queue
1481 * @hw: pointer to the HW struct
1482 * @desc: descriptor describing the command
1483 * @buf: buffer to use for indirect commands (NULL for direct commands)
1484 * @buf_size: size of buffer for indirect commands (0 for direct commands)
1485 * @cd: pointer to command details structure
1486 */
1487static int
1488ice_sbq_send_cmd(struct ice_hw *hw, struct ice_sbq_cmd_desc *desc,
1489 void *buf, u16 buf_size, struct ice_sq_cd *cd)
1490{
1491 return ice_sq_send_cmd(hw, ice_get_sbq(hw),
1492 (struct ice_aq_desc *)desc, buf, buf_size, cd);
1493}
1494
1495/**
1496 * ice_sbq_rw_reg - Fill Sideband Queue command
1497 * @hw: pointer to the HW struct
1498 * @in: message info to be filled in descriptor
1499 * @flags: control queue descriptor flags
1500 */
1501int ice_sbq_rw_reg(struct ice_hw *hw, struct ice_sbq_msg_input *in, u16 flags)
1502{
1503 struct ice_sbq_cmd_desc desc = {0};
1504 struct ice_sbq_msg_req msg = {0};
1505 u16 msg_len;
1506 int status;
1507
1508 msg_len = sizeof(msg);
1509
1510 msg.dest_dev = in->dest_dev;
1511 msg.opcode = in->opcode;
1512 msg.flags = ICE_SBQ_MSG_FLAGS;
1513 msg.sbe_fbe = ICE_SBQ_MSG_SBE_FBE;
1514 msg.msg_addr_low = cpu_to_le16(in->msg_addr_low);
1515 msg.msg_addr_high = cpu_to_le32(in->msg_addr_high);
1516
1517 if (in->opcode)
1518 msg.data = cpu_to_le32(in->data);
1519 else
1520 /* data read comes back in completion, so shorten the struct by
1521 * sizeof(msg.data)
1522 */
1523 msg_len -= sizeof(msg.data);
1524
1525 desc.flags = cpu_to_le16(flags);
1526 desc.opcode = cpu_to_le16(ice_sbq_opc_neigh_dev_req);
1527 desc.param0.cmd_len = cpu_to_le16(msg_len);
1528 status = ice_sbq_send_cmd(hw, &desc, &msg, msg_len, NULL);
1529 if (!status && !in->opcode)
1530 in->data = le32_to_cpu
1531 (((struct ice_sbq_msg_cmpl *)&msg)->data);
1532 return status;
1533}
1534
1535/* FW Admin Queue command wrappers */
1536
1537/* Software lock/mutex that is meant to be held while the Global Config Lock
1538 * in firmware is acquired by the software to prevent most (but not all) types
1539 * of AQ commands from being sent to FW
1540 */
1541DEFINE_MUTEX(ice_global_cfg_lock_sw);
1542
1543/**
1544 * ice_should_retry_sq_send_cmd
1545 * @opcode: AQ opcode
1546 *
1547 * Decide if we should retry the send command routine for the ATQ, depending
1548 * on the opcode.
1549 */
1550static bool ice_should_retry_sq_send_cmd(u16 opcode)
1551{
1552 switch (opcode) {
1553 case ice_aqc_opc_get_link_topo:
1554 case ice_aqc_opc_lldp_stop:
1555 case ice_aqc_opc_lldp_start:
1556 case ice_aqc_opc_lldp_filter_ctrl:
1557 return true;
1558 }
1559
1560 return false;
1561}
1562
1563/**
1564 * ice_sq_send_cmd_retry - send command to Control Queue (ATQ)
1565 * @hw: pointer to the HW struct
1566 * @cq: pointer to the specific Control queue
1567 * @desc: prefilled descriptor describing the command
1568 * @buf: buffer to use for indirect commands (or NULL for direct commands)
1569 * @buf_size: size of buffer for indirect commands (or 0 for direct commands)
1570 * @cd: pointer to command details structure
1571 *
1572 * Retry sending the FW Admin Queue command, multiple times, to the FW Admin
1573 * Queue if the EBUSY AQ error is returned.
1574 */
1575static int
1576ice_sq_send_cmd_retry(struct ice_hw *hw, struct ice_ctl_q_info *cq,
1577 struct ice_aq_desc *desc, void *buf, u16 buf_size,
1578 struct ice_sq_cd *cd)
1579{
1580 struct ice_aq_desc desc_cpy;
1581 bool is_cmd_for_retry;
1582 u8 idx = 0;
1583 u16 opcode;
1584 int status;
1585
1586 opcode = le16_to_cpu(desc->opcode);
1587 is_cmd_for_retry = ice_should_retry_sq_send_cmd(opcode);
1588 memset(&desc_cpy, 0, sizeof(desc_cpy));
1589
1590 if (is_cmd_for_retry) {
1591 /* All retryable cmds are direct, without buf. */
1592 WARN_ON(buf);
1593
1594 memcpy(&desc_cpy, desc, sizeof(desc_cpy));
1595 }
1596
1597 do {
1598 status = ice_sq_send_cmd(hw, cq, desc, buf, buf_size, cd);
1599
1600 if (!is_cmd_for_retry || !status ||
1601 hw->adminq.sq_last_status != ICE_AQ_RC_EBUSY)
1602 break;
1603
1604 memcpy(desc, &desc_cpy, sizeof(desc_cpy));
1605
1606 msleep(ICE_SQ_SEND_DELAY_TIME_MS);
1607
1608 } while (++idx < ICE_SQ_SEND_MAX_EXECUTE);
1609
1610 return status;
1611}
1612
1613/**
1614 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue
1615 * @hw: pointer to the HW struct
1616 * @desc: descriptor describing the command
1617 * @buf: buffer to use for indirect commands (NULL for direct commands)
1618 * @buf_size: size of buffer for indirect commands (0 for direct commands)
1619 * @cd: pointer to command details structure
1620 *
1621 * Helper function to send FW Admin Queue commands to the FW Admin Queue.
1622 */
1623int
1624ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf,
1625 u16 buf_size, struct ice_sq_cd *cd)
1626{
1627 struct ice_aqc_req_res *cmd = &desc->params.res_owner;
1628 bool lock_acquired = false;
1629 int status;
1630
1631 /* When a package download is in process (i.e. when the firmware's
1632 * Global Configuration Lock resource is held), only the Download
1633 * Package, Get Version, Get Package Info List, Upload Section,
1634 * Update Package, Set Port Parameters, Get/Set VLAN Mode Parameters,
1635 * Add Recipe, Set Recipes to Profile Association, Get Recipe, and Get
1636 * Recipes to Profile Association, and Release Resource (with resource
1637 * ID set to Global Config Lock) AdminQ commands are allowed; all others
1638 * must block until the package download completes and the Global Config
1639 * Lock is released. See also ice_acquire_global_cfg_lock().
1640 */
1641 switch (le16_to_cpu(desc->opcode)) {
1642 case ice_aqc_opc_download_pkg:
1643 case ice_aqc_opc_get_pkg_info_list:
1644 case ice_aqc_opc_get_ver:
1645 case ice_aqc_opc_upload_section:
1646 case ice_aqc_opc_update_pkg:
1647 case ice_aqc_opc_set_port_params:
1648 case ice_aqc_opc_get_vlan_mode_parameters:
1649 case ice_aqc_opc_set_vlan_mode_parameters:
1650 case ice_aqc_opc_set_tx_topo:
1651 case ice_aqc_opc_get_tx_topo:
1652 case ice_aqc_opc_add_recipe:
1653 case ice_aqc_opc_recipe_to_profile:
1654 case ice_aqc_opc_get_recipe:
1655 case ice_aqc_opc_get_recipe_to_profile:
1656 break;
1657 case ice_aqc_opc_release_res:
1658 if (le16_to_cpu(cmd->res_id) == ICE_AQC_RES_ID_GLBL_LOCK)
1659 break;
1660 fallthrough;
1661 default:
1662 mutex_lock(&ice_global_cfg_lock_sw);
1663 lock_acquired = true;
1664 break;
1665 }
1666
1667 status = ice_sq_send_cmd_retry(hw, &hw->adminq, desc, buf, buf_size, cd);
1668 if (lock_acquired)
1669 mutex_unlock(&ice_global_cfg_lock_sw);
1670
1671 return status;
1672}
1673
1674/**
1675 * ice_aq_get_fw_ver
1676 * @hw: pointer to the HW struct
1677 * @cd: pointer to command details structure or NULL
1678 *
1679 * Get the firmware version (0x0001) from the admin queue commands
1680 */
1681int ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd)
1682{
1683 struct ice_aqc_get_ver *resp;
1684 struct ice_aq_desc desc;
1685 int status;
1686
1687 resp = &desc.params.get_ver;
1688
1689 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver);
1690
1691 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1692
1693 if (!status) {
1694 hw->fw_branch = resp->fw_branch;
1695 hw->fw_maj_ver = resp->fw_major;
1696 hw->fw_min_ver = resp->fw_minor;
1697 hw->fw_patch = resp->fw_patch;
1698 hw->fw_build = le32_to_cpu(resp->fw_build);
1699 hw->api_branch = resp->api_branch;
1700 hw->api_maj_ver = resp->api_major;
1701 hw->api_min_ver = resp->api_minor;
1702 hw->api_patch = resp->api_patch;
1703 }
1704
1705 return status;
1706}
1707
1708/**
1709 * ice_aq_send_driver_ver
1710 * @hw: pointer to the HW struct
1711 * @dv: driver's major, minor version
1712 * @cd: pointer to command details structure or NULL
1713 *
1714 * Send the driver version (0x0002) to the firmware
1715 */
1716int
1717ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv,
1718 struct ice_sq_cd *cd)
1719{
1720 struct ice_aqc_driver_ver *cmd;
1721 struct ice_aq_desc desc;
1722 u16 len;
1723
1724 cmd = &desc.params.driver_ver;
1725
1726 if (!dv)
1727 return -EINVAL;
1728
1729 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver);
1730
1731 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
1732 cmd->major_ver = dv->major_ver;
1733 cmd->minor_ver = dv->minor_ver;
1734 cmd->build_ver = dv->build_ver;
1735 cmd->subbuild_ver = dv->subbuild_ver;
1736
1737 len = 0;
1738 while (len < sizeof(dv->driver_string) &&
1739 isascii(dv->driver_string[len]) && dv->driver_string[len])
1740 len++;
1741
1742 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd);
1743}
1744
1745/**
1746 * ice_aq_q_shutdown
1747 * @hw: pointer to the HW struct
1748 * @unloading: is the driver unloading itself
1749 *
1750 * Tell the Firmware that we're shutting down the AdminQ and whether
1751 * or not the driver is unloading as well (0x0003).
1752 */
1753int ice_aq_q_shutdown(struct ice_hw *hw, bool unloading)
1754{
1755 struct ice_aqc_q_shutdown *cmd;
1756 struct ice_aq_desc desc;
1757
1758 cmd = &desc.params.q_shutdown;
1759
1760 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown);
1761
1762 if (unloading)
1763 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING;
1764
1765 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
1766}
1767
1768/**
1769 * ice_aq_req_res
1770 * @hw: pointer to the HW struct
1771 * @res: resource ID
1772 * @access: access type
1773 * @sdp_number: resource number
1774 * @timeout: the maximum time in ms that the driver may hold the resource
1775 * @cd: pointer to command details structure or NULL
1776 *
1777 * Requests common resource using the admin queue commands (0x0008).
1778 * When attempting to acquire the Global Config Lock, the driver can
1779 * learn of three states:
1780 * 1) 0 - acquired lock, and can perform download package
1781 * 2) -EIO - did not get lock, driver should fail to load
1782 * 3) -EALREADY - did not get lock, but another driver has
1783 * successfully downloaded the package; the driver does
1784 * not have to download the package and can continue
1785 * loading
1786 *
1787 * Note that if the caller is in an acquire lock, perform action, release lock
1788 * phase of operation, it is possible that the FW may detect a timeout and issue
1789 * a CORER. In this case, the driver will receive a CORER interrupt and will
1790 * have to determine its cause. The calling thread that is handling this flow
1791 * will likely get an error propagated back to it indicating the Download
1792 * Package, Update Package or the Release Resource AQ commands timed out.
1793 */
1794static int
1795ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1796 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout,
1797 struct ice_sq_cd *cd)
1798{
1799 struct ice_aqc_req_res *cmd_resp;
1800 struct ice_aq_desc desc;
1801 int status;
1802
1803 cmd_resp = &desc.params.res_owner;
1804
1805 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res);
1806
1807 cmd_resp->res_id = cpu_to_le16(res);
1808 cmd_resp->access_type = cpu_to_le16(access);
1809 cmd_resp->res_number = cpu_to_le32(sdp_number);
1810 cmd_resp->timeout = cpu_to_le32(*timeout);
1811 *timeout = 0;
1812
1813 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1814
1815 /* The completion specifies the maximum time in ms that the driver
1816 * may hold the resource in the Timeout field.
1817 */
1818
1819 /* Global config lock response utilizes an additional status field.
1820 *
1821 * If the Global config lock resource is held by some other driver, the
1822 * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field
1823 * and the timeout field indicates the maximum time the current owner
1824 * of the resource has to free it.
1825 */
1826 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) {
1827 if (le16_to_cpu(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) {
1828 *timeout = le32_to_cpu(cmd_resp->timeout);
1829 return 0;
1830 } else if (le16_to_cpu(cmd_resp->status) ==
1831 ICE_AQ_RES_GLBL_IN_PROG) {
1832 *timeout = le32_to_cpu(cmd_resp->timeout);
1833 return -EIO;
1834 } else if (le16_to_cpu(cmd_resp->status) ==
1835 ICE_AQ_RES_GLBL_DONE) {
1836 return -EALREADY;
1837 }
1838
1839 /* invalid FW response, force a timeout immediately */
1840 *timeout = 0;
1841 return -EIO;
1842 }
1843
1844 /* If the resource is held by some other driver, the command completes
1845 * with a busy return value and the timeout field indicates the maximum
1846 * time the current owner of the resource has to free it.
1847 */
1848 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY)
1849 *timeout = le32_to_cpu(cmd_resp->timeout);
1850
1851 return status;
1852}
1853
1854/**
1855 * ice_aq_release_res
1856 * @hw: pointer to the HW struct
1857 * @res: resource ID
1858 * @sdp_number: resource number
1859 * @cd: pointer to command details structure or NULL
1860 *
1861 * release common resource using the admin queue commands (0x0009)
1862 */
1863static int
1864ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number,
1865 struct ice_sq_cd *cd)
1866{
1867 struct ice_aqc_req_res *cmd;
1868 struct ice_aq_desc desc;
1869
1870 cmd = &desc.params.res_owner;
1871
1872 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res);
1873
1874 cmd->res_id = cpu_to_le16(res);
1875 cmd->res_number = cpu_to_le32(sdp_number);
1876
1877 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1878}
1879
1880/**
1881 * ice_acquire_res
1882 * @hw: pointer to the HW structure
1883 * @res: resource ID
1884 * @access: access type (read or write)
1885 * @timeout: timeout in milliseconds
1886 *
1887 * This function will attempt to acquire the ownership of a resource.
1888 */
1889int
1890ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1891 enum ice_aq_res_access_type access, u32 timeout)
1892{
1893#define ICE_RES_POLLING_DELAY_MS 10
1894 u32 delay = ICE_RES_POLLING_DELAY_MS;
1895 u32 time_left = timeout;
1896 int status;
1897
1898 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
1899
1900 /* A return code of -EALREADY means that another driver has
1901 * previously acquired the resource and performed any necessary updates;
1902 * in this case the caller does not obtain the resource and has no
1903 * further work to do.
1904 */
1905 if (status == -EALREADY)
1906 goto ice_acquire_res_exit;
1907
1908 if (status)
1909 ice_debug(hw, ICE_DBG_RES, "resource %d acquire type %d failed.\n", res, access);
1910
1911 /* If necessary, poll until the current lock owner timeouts */
1912 timeout = time_left;
1913 while (status && timeout && time_left) {
1914 mdelay(delay);
1915 timeout = (timeout > delay) ? timeout - delay : 0;
1916 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
1917
1918 if (status == -EALREADY)
1919 /* lock free, but no work to do */
1920 break;
1921
1922 if (!status)
1923 /* lock acquired */
1924 break;
1925 }
1926 if (status && status != -EALREADY)
1927 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n");
1928
1929ice_acquire_res_exit:
1930 if (status == -EALREADY) {
1931 if (access == ICE_RES_WRITE)
1932 ice_debug(hw, ICE_DBG_RES, "resource indicates no work to do.\n");
1933 else
1934 ice_debug(hw, ICE_DBG_RES, "Warning: -EALREADY not expected\n");
1935 }
1936 return status;
1937}
1938
1939/**
1940 * ice_release_res
1941 * @hw: pointer to the HW structure
1942 * @res: resource ID
1943 *
1944 * This function will release a resource using the proper Admin Command.
1945 */
1946void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res)
1947{
1948 unsigned long timeout;
1949 int status;
1950
1951 /* there are some rare cases when trying to release the resource
1952 * results in an admin queue timeout, so handle them correctly
1953 */
1954 timeout = jiffies + 10 * ICE_CTL_Q_SQ_CMD_TIMEOUT;
1955 do {
1956 status = ice_aq_release_res(hw, res, 0, NULL);
1957 if (status != -EIO)
1958 break;
1959 usleep_range(1000, 2000);
1960 } while (time_before(jiffies, timeout));
1961}
1962
1963/**
1964 * ice_aq_alloc_free_res - command to allocate/free resources
1965 * @hw: pointer to the HW struct
1966 * @buf: Indirect buffer to hold data parameters and response
1967 * @buf_size: size of buffer for indirect commands
1968 * @opc: pass in the command opcode
1969 *
1970 * Helper function to allocate/free resources using the admin queue commands
1971 */
1972int ice_aq_alloc_free_res(struct ice_hw *hw,
1973 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size,
1974 enum ice_adminq_opc opc)
1975{
1976 struct ice_aqc_alloc_free_res_cmd *cmd;
1977 struct ice_aq_desc desc;
1978
1979 cmd = &desc.params.sw_res_ctrl;
1980
1981 if (!buf || buf_size < flex_array_size(buf, elem, 1))
1982 return -EINVAL;
1983
1984 ice_fill_dflt_direct_cmd_desc(&desc, opc);
1985
1986 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
1987
1988 cmd->num_entries = cpu_to_le16(1);
1989
1990 return ice_aq_send_cmd(hw, &desc, buf, buf_size, NULL);
1991}
1992
1993/**
1994 * ice_alloc_hw_res - allocate resource
1995 * @hw: pointer to the HW struct
1996 * @type: type of resource
1997 * @num: number of resources to allocate
1998 * @btm: allocate from bottom
1999 * @res: pointer to array that will receive the resources
2000 */
2001int
2002ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res)
2003{
2004 struct ice_aqc_alloc_free_res_elem *buf;
2005 u16 buf_len;
2006 int status;
2007
2008 buf_len = struct_size(buf, elem, num);
2009 buf = kzalloc(buf_len, GFP_KERNEL);
2010 if (!buf)
2011 return -ENOMEM;
2012
2013 /* Prepare buffer to allocate resource. */
2014 buf->num_elems = cpu_to_le16(num);
2015 buf->res_type = cpu_to_le16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED |
2016 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX);
2017 if (btm)
2018 buf->res_type |= cpu_to_le16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM);
2019
2020 status = ice_aq_alloc_free_res(hw, buf, buf_len, ice_aqc_opc_alloc_res);
2021 if (status)
2022 goto ice_alloc_res_exit;
2023
2024 memcpy(res, buf->elem, sizeof(*buf->elem) * num);
2025
2026ice_alloc_res_exit:
2027 kfree(buf);
2028 return status;
2029}
2030
2031/**
2032 * ice_free_hw_res - free allocated HW resource
2033 * @hw: pointer to the HW struct
2034 * @type: type of resource to free
2035 * @num: number of resources
2036 * @res: pointer to array that contains the resources to free
2037 */
2038int ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res)
2039{
2040 struct ice_aqc_alloc_free_res_elem *buf;
2041 u16 buf_len;
2042 int status;
2043
2044 buf_len = struct_size(buf, elem, num);
2045 buf = kzalloc(buf_len, GFP_KERNEL);
2046 if (!buf)
2047 return -ENOMEM;
2048
2049 /* Prepare buffer to free resource. */
2050 buf->num_elems = cpu_to_le16(num);
2051 buf->res_type = cpu_to_le16(type);
2052 memcpy(buf->elem, res, sizeof(*buf->elem) * num);
2053
2054 status = ice_aq_alloc_free_res(hw, buf, buf_len, ice_aqc_opc_free_res);
2055 if (status)
2056 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n");
2057
2058 kfree(buf);
2059 return status;
2060}
2061
2062/**
2063 * ice_get_num_per_func - determine number of resources per PF
2064 * @hw: pointer to the HW structure
2065 * @max: value to be evenly split between each PF
2066 *
2067 * Determine the number of valid functions by going through the bitmap returned
2068 * from parsing capabilities and use this to calculate the number of resources
2069 * per PF based on the max value passed in.
2070 */
2071static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max)
2072{
2073 u8 funcs;
2074
2075#define ICE_CAPS_VALID_FUNCS_M 0xFF
2076 funcs = hweight8(hw->dev_caps.common_cap.valid_functions &
2077 ICE_CAPS_VALID_FUNCS_M);
2078
2079 if (!funcs)
2080 return 0;
2081
2082 return max / funcs;
2083}
2084
2085/**
2086 * ice_parse_common_caps - parse common device/function capabilities
2087 * @hw: pointer to the HW struct
2088 * @caps: pointer to common capabilities structure
2089 * @elem: the capability element to parse
2090 * @prefix: message prefix for tracing capabilities
2091 *
2092 * Given a capability element, extract relevant details into the common
2093 * capability structure.
2094 *
2095 * Returns: true if the capability matches one of the common capability ids,
2096 * false otherwise.
2097 */
2098static bool
2099ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps,
2100 struct ice_aqc_list_caps_elem *elem, const char *prefix)
2101{
2102 u32 logical_id = le32_to_cpu(elem->logical_id);
2103 u32 phys_id = le32_to_cpu(elem->phys_id);
2104 u32 number = le32_to_cpu(elem->number);
2105 u16 cap = le16_to_cpu(elem->cap);
2106 bool found = true;
2107
2108 switch (cap) {
2109 case ICE_AQC_CAPS_VALID_FUNCTIONS:
2110 caps->valid_functions = number;
2111 ice_debug(hw, ICE_DBG_INIT, "%s: valid_functions (bitmap) = %d\n", prefix,
2112 caps->valid_functions);
2113 break;
2114 case ICE_AQC_CAPS_SRIOV:
2115 caps->sr_iov_1_1 = (number == 1);
2116 ice_debug(hw, ICE_DBG_INIT, "%s: sr_iov_1_1 = %d\n", prefix,
2117 caps->sr_iov_1_1);
2118 break;
2119 case ICE_AQC_CAPS_DCB:
2120 caps->dcb = (number == 1);
2121 caps->active_tc_bitmap = logical_id;
2122 caps->maxtc = phys_id;
2123 ice_debug(hw, ICE_DBG_INIT, "%s: dcb = %d\n", prefix, caps->dcb);
2124 ice_debug(hw, ICE_DBG_INIT, "%s: active_tc_bitmap = %d\n", prefix,
2125 caps->active_tc_bitmap);
2126 ice_debug(hw, ICE_DBG_INIT, "%s: maxtc = %d\n", prefix, caps->maxtc);
2127 break;
2128 case ICE_AQC_CAPS_RSS:
2129 caps->rss_table_size = number;
2130 caps->rss_table_entry_width = logical_id;
2131 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_size = %d\n", prefix,
2132 caps->rss_table_size);
2133 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_entry_width = %d\n", prefix,
2134 caps->rss_table_entry_width);
2135 break;
2136 case ICE_AQC_CAPS_RXQS:
2137 caps->num_rxq = number;
2138 caps->rxq_first_id = phys_id;
2139 ice_debug(hw, ICE_DBG_INIT, "%s: num_rxq = %d\n", prefix,
2140 caps->num_rxq);
2141 ice_debug(hw, ICE_DBG_INIT, "%s: rxq_first_id = %d\n", prefix,
2142 caps->rxq_first_id);
2143 break;
2144 case ICE_AQC_CAPS_TXQS:
2145 caps->num_txq = number;
2146 caps->txq_first_id = phys_id;
2147 ice_debug(hw, ICE_DBG_INIT, "%s: num_txq = %d\n", prefix,
2148 caps->num_txq);
2149 ice_debug(hw, ICE_DBG_INIT, "%s: txq_first_id = %d\n", prefix,
2150 caps->txq_first_id);
2151 break;
2152 case ICE_AQC_CAPS_MSIX:
2153 caps->num_msix_vectors = number;
2154 caps->msix_vector_first_id = phys_id;
2155 ice_debug(hw, ICE_DBG_INIT, "%s: num_msix_vectors = %d\n", prefix,
2156 caps->num_msix_vectors);
2157 ice_debug(hw, ICE_DBG_INIT, "%s: msix_vector_first_id = %d\n", prefix,
2158 caps->msix_vector_first_id);
2159 break;
2160 case ICE_AQC_CAPS_PENDING_NVM_VER:
2161 caps->nvm_update_pending_nvm = true;
2162 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_nvm\n", prefix);
2163 break;
2164 case ICE_AQC_CAPS_PENDING_OROM_VER:
2165 caps->nvm_update_pending_orom = true;
2166 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_orom\n", prefix);
2167 break;
2168 case ICE_AQC_CAPS_PENDING_NET_VER:
2169 caps->nvm_update_pending_netlist = true;
2170 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_netlist\n", prefix);
2171 break;
2172 case ICE_AQC_CAPS_NVM_MGMT:
2173 caps->nvm_unified_update =
2174 (number & ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT) ?
2175 true : false;
2176 ice_debug(hw, ICE_DBG_INIT, "%s: nvm_unified_update = %d\n", prefix,
2177 caps->nvm_unified_update);
2178 break;
2179 case ICE_AQC_CAPS_RDMA:
2180 caps->rdma = (number == 1);
2181 ice_debug(hw, ICE_DBG_INIT, "%s: rdma = %d\n", prefix, caps->rdma);
2182 break;
2183 case ICE_AQC_CAPS_MAX_MTU:
2184 caps->max_mtu = number;
2185 ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n",
2186 prefix, caps->max_mtu);
2187 break;
2188 case ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE:
2189 caps->pcie_reset_avoidance = (number > 0);
2190 ice_debug(hw, ICE_DBG_INIT,
2191 "%s: pcie_reset_avoidance = %d\n", prefix,
2192 caps->pcie_reset_avoidance);
2193 break;
2194 case ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT:
2195 caps->reset_restrict_support = (number == 1);
2196 ice_debug(hw, ICE_DBG_INIT,
2197 "%s: reset_restrict_support = %d\n", prefix,
2198 caps->reset_restrict_support);
2199 break;
2200 case ICE_AQC_CAPS_FW_LAG_SUPPORT:
2201 caps->roce_lag = !!(number & ICE_AQC_BIT_ROCEV2_LAG);
2202 ice_debug(hw, ICE_DBG_INIT, "%s: roce_lag = %u\n",
2203 prefix, caps->roce_lag);
2204 caps->sriov_lag = !!(number & ICE_AQC_BIT_SRIOV_LAG);
2205 ice_debug(hw, ICE_DBG_INIT, "%s: sriov_lag = %u\n",
2206 prefix, caps->sriov_lag);
2207 break;
2208 case ICE_AQC_CAPS_TX_SCHED_TOPO_COMP_MODE:
2209 caps->tx_sched_topo_comp_mode_en = (number == 1);
2210 break;
2211 default:
2212 /* Not one of the recognized common capabilities */
2213 found = false;
2214 }
2215
2216 return found;
2217}
2218
2219/**
2220 * ice_recalc_port_limited_caps - Recalculate port limited capabilities
2221 * @hw: pointer to the HW structure
2222 * @caps: pointer to capabilities structure to fix
2223 *
2224 * Re-calculate the capabilities that are dependent on the number of physical
2225 * ports; i.e. some features are not supported or function differently on
2226 * devices with more than 4 ports.
2227 */
2228static void
2229ice_recalc_port_limited_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps)
2230{
2231 /* This assumes device capabilities are always scanned before function
2232 * capabilities during the initialization flow.
2233 */
2234 if (hw->dev_caps.num_funcs > 4) {
2235 /* Max 4 TCs per port */
2236 caps->maxtc = 4;
2237 ice_debug(hw, ICE_DBG_INIT, "reducing maxtc to %d (based on #ports)\n",
2238 caps->maxtc);
2239 if (caps->rdma) {
2240 ice_debug(hw, ICE_DBG_INIT, "forcing RDMA off\n");
2241 caps->rdma = 0;
2242 }
2243
2244 /* print message only when processing device capabilities
2245 * during initialization.
2246 */
2247 if (caps == &hw->dev_caps.common_cap)
2248 dev_info(ice_hw_to_dev(hw), "RDMA functionality is not available with the current device configuration.\n");
2249 }
2250}
2251
2252/**
2253 * ice_parse_vf_func_caps - Parse ICE_AQC_CAPS_VF function caps
2254 * @hw: pointer to the HW struct
2255 * @func_p: pointer to function capabilities structure
2256 * @cap: pointer to the capability element to parse
2257 *
2258 * Extract function capabilities for ICE_AQC_CAPS_VF.
2259 */
2260static void
2261ice_parse_vf_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
2262 struct ice_aqc_list_caps_elem *cap)
2263{
2264 u32 logical_id = le32_to_cpu(cap->logical_id);
2265 u32 number = le32_to_cpu(cap->number);
2266
2267 func_p->num_allocd_vfs = number;
2268 func_p->vf_base_id = logical_id;
2269 ice_debug(hw, ICE_DBG_INIT, "func caps: num_allocd_vfs = %d\n",
2270 func_p->num_allocd_vfs);
2271 ice_debug(hw, ICE_DBG_INIT, "func caps: vf_base_id = %d\n",
2272 func_p->vf_base_id);
2273}
2274
2275/**
2276 * ice_parse_vsi_func_caps - Parse ICE_AQC_CAPS_VSI function caps
2277 * @hw: pointer to the HW struct
2278 * @func_p: pointer to function capabilities structure
2279 * @cap: pointer to the capability element to parse
2280 *
2281 * Extract function capabilities for ICE_AQC_CAPS_VSI.
2282 */
2283static void
2284ice_parse_vsi_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
2285 struct ice_aqc_list_caps_elem *cap)
2286{
2287 func_p->guar_num_vsi = ice_get_num_per_func(hw, ICE_MAX_VSI);
2288 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi (fw) = %d\n",
2289 le32_to_cpu(cap->number));
2290 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi = %d\n",
2291 func_p->guar_num_vsi);
2292}
2293
2294/**
2295 * ice_parse_1588_func_caps - Parse ICE_AQC_CAPS_1588 function caps
2296 * @hw: pointer to the HW struct
2297 * @func_p: pointer to function capabilities structure
2298 * @cap: pointer to the capability element to parse
2299 *
2300 * Extract function capabilities for ICE_AQC_CAPS_1588.
2301 */
2302static void
2303ice_parse_1588_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
2304 struct ice_aqc_list_caps_elem *cap)
2305{
2306 struct ice_ts_func_info *info = &func_p->ts_func_info;
2307 u32 number = le32_to_cpu(cap->number);
2308
2309 info->ena = ((number & ICE_TS_FUNC_ENA_M) != 0);
2310 func_p->common_cap.ieee_1588 = info->ena;
2311
2312 info->src_tmr_owned = ((number & ICE_TS_SRC_TMR_OWND_M) != 0);
2313 info->tmr_ena = ((number & ICE_TS_TMR_ENA_M) != 0);
2314 info->tmr_index_owned = ((number & ICE_TS_TMR_IDX_OWND_M) != 0);
2315 info->tmr_index_assoc = ((number & ICE_TS_TMR_IDX_ASSOC_M) != 0);
2316
2317 if (!ice_is_e825c(hw)) {
2318 info->clk_freq = FIELD_GET(ICE_TS_CLK_FREQ_M, number);
2319 info->clk_src = ((number & ICE_TS_CLK_SRC_M) != 0);
2320 } else {
2321 info->clk_freq = ICE_TIME_REF_FREQ_156_250;
2322 info->clk_src = ICE_CLK_SRC_TCXO;
2323 }
2324
2325 if (info->clk_freq < NUM_ICE_TIME_REF_FREQ) {
2326 info->time_ref = (enum ice_time_ref_freq)info->clk_freq;
2327 } else {
2328 /* Unknown clock frequency, so assume a (probably incorrect)
2329 * default to avoid out-of-bounds look ups of frequency
2330 * related information.
2331 */
2332 ice_debug(hw, ICE_DBG_INIT, "1588 func caps: unknown clock frequency %u\n",
2333 info->clk_freq);
2334 info->time_ref = ICE_TIME_REF_FREQ_25_000;
2335 }
2336
2337 ice_debug(hw, ICE_DBG_INIT, "func caps: ieee_1588 = %u\n",
2338 func_p->common_cap.ieee_1588);
2339 ice_debug(hw, ICE_DBG_INIT, "func caps: src_tmr_owned = %u\n",
2340 info->src_tmr_owned);
2341 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_ena = %u\n",
2342 info->tmr_ena);
2343 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_owned = %u\n",
2344 info->tmr_index_owned);
2345 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_assoc = %u\n",
2346 info->tmr_index_assoc);
2347 ice_debug(hw, ICE_DBG_INIT, "func caps: clk_freq = %u\n",
2348 info->clk_freq);
2349 ice_debug(hw, ICE_DBG_INIT, "func caps: clk_src = %u\n",
2350 info->clk_src);
2351}
2352
2353/**
2354 * ice_parse_fdir_func_caps - Parse ICE_AQC_CAPS_FD function caps
2355 * @hw: pointer to the HW struct
2356 * @func_p: pointer to function capabilities structure
2357 *
2358 * Extract function capabilities for ICE_AQC_CAPS_FD.
2359 */
2360static void
2361ice_parse_fdir_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p)
2362{
2363 u32 reg_val, gsize, bsize;
2364
2365 reg_val = rd32(hw, GLQF_FD_SIZE);
2366 switch (hw->mac_type) {
2367 case ICE_MAC_E830:
2368 gsize = FIELD_GET(E830_GLQF_FD_SIZE_FD_GSIZE_M, reg_val);
2369 bsize = FIELD_GET(E830_GLQF_FD_SIZE_FD_BSIZE_M, reg_val);
2370 break;
2371 case ICE_MAC_E810:
2372 default:
2373 gsize = FIELD_GET(E800_GLQF_FD_SIZE_FD_GSIZE_M, reg_val);
2374 bsize = FIELD_GET(E800_GLQF_FD_SIZE_FD_BSIZE_M, reg_val);
2375 }
2376 func_p->fd_fltr_guar = ice_get_num_per_func(hw, gsize);
2377 func_p->fd_fltr_best_effort = bsize;
2378
2379 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_guar = %d\n",
2380 func_p->fd_fltr_guar);
2381 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_best_effort = %d\n",
2382 func_p->fd_fltr_best_effort);
2383}
2384
2385/**
2386 * ice_parse_func_caps - Parse function capabilities
2387 * @hw: pointer to the HW struct
2388 * @func_p: pointer to function capabilities structure
2389 * @buf: buffer containing the function capability records
2390 * @cap_count: the number of capabilities
2391 *
2392 * Helper function to parse function (0x000A) capabilities list. For
2393 * capabilities shared between device and function, this relies on
2394 * ice_parse_common_caps.
2395 *
2396 * Loop through the list of provided capabilities and extract the relevant
2397 * data into the function capabilities structured.
2398 */
2399static void
2400ice_parse_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
2401 void *buf, u32 cap_count)
2402{
2403 struct ice_aqc_list_caps_elem *cap_resp;
2404 u32 i;
2405
2406 cap_resp = buf;
2407
2408 memset(func_p, 0, sizeof(*func_p));
2409
2410 for (i = 0; i < cap_count; i++) {
2411 u16 cap = le16_to_cpu(cap_resp[i].cap);
2412 bool found;
2413
2414 found = ice_parse_common_caps(hw, &func_p->common_cap,
2415 &cap_resp[i], "func caps");
2416
2417 switch (cap) {
2418 case ICE_AQC_CAPS_VF:
2419 ice_parse_vf_func_caps(hw, func_p, &cap_resp[i]);
2420 break;
2421 case ICE_AQC_CAPS_VSI:
2422 ice_parse_vsi_func_caps(hw, func_p, &cap_resp[i]);
2423 break;
2424 case ICE_AQC_CAPS_1588:
2425 ice_parse_1588_func_caps(hw, func_p, &cap_resp[i]);
2426 break;
2427 case ICE_AQC_CAPS_FD:
2428 ice_parse_fdir_func_caps(hw, func_p);
2429 break;
2430 default:
2431 /* Don't list common capabilities as unknown */
2432 if (!found)
2433 ice_debug(hw, ICE_DBG_INIT, "func caps: unknown capability[%d]: 0x%x\n",
2434 i, cap);
2435 break;
2436 }
2437 }
2438
2439 ice_recalc_port_limited_caps(hw, &func_p->common_cap);
2440}
2441
2442/**
2443 * ice_func_id_to_logical_id - map from function id to logical pf id
2444 * @active_function_bitmap: active function bitmap
2445 * @pf_id: function number of device
2446 *
2447 * Return: logical PF ID.
2448 */
2449static int ice_func_id_to_logical_id(u32 active_function_bitmap, u8 pf_id)
2450{
2451 u8 logical_id = 0;
2452 u8 i;
2453
2454 for (i = 0; i < pf_id; i++)
2455 if (active_function_bitmap & BIT(i))
2456 logical_id++;
2457
2458 return logical_id;
2459}
2460
2461/**
2462 * ice_parse_valid_functions_cap - Parse ICE_AQC_CAPS_VALID_FUNCTIONS caps
2463 * @hw: pointer to the HW struct
2464 * @dev_p: pointer to device capabilities structure
2465 * @cap: capability element to parse
2466 *
2467 * Parse ICE_AQC_CAPS_VALID_FUNCTIONS for device capabilities.
2468 */
2469static void
2470ice_parse_valid_functions_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2471 struct ice_aqc_list_caps_elem *cap)
2472{
2473 u32 number = le32_to_cpu(cap->number);
2474
2475 dev_p->num_funcs = hweight32(number);
2476 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_funcs = %d\n",
2477 dev_p->num_funcs);
2478
2479 hw->logical_pf_id = ice_func_id_to_logical_id(number, hw->pf_id);
2480}
2481
2482/**
2483 * ice_parse_vf_dev_caps - Parse ICE_AQC_CAPS_VF device caps
2484 * @hw: pointer to the HW struct
2485 * @dev_p: pointer to device capabilities structure
2486 * @cap: capability element to parse
2487 *
2488 * Parse ICE_AQC_CAPS_VF for device capabilities.
2489 */
2490static void
2491ice_parse_vf_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2492 struct ice_aqc_list_caps_elem *cap)
2493{
2494 u32 number = le32_to_cpu(cap->number);
2495
2496 dev_p->num_vfs_exposed = number;
2497 ice_debug(hw, ICE_DBG_INIT, "dev_caps: num_vfs_exposed = %d\n",
2498 dev_p->num_vfs_exposed);
2499}
2500
2501/**
2502 * ice_parse_vsi_dev_caps - Parse ICE_AQC_CAPS_VSI device caps
2503 * @hw: pointer to the HW struct
2504 * @dev_p: pointer to device capabilities structure
2505 * @cap: capability element to parse
2506 *
2507 * Parse ICE_AQC_CAPS_VSI for device capabilities.
2508 */
2509static void
2510ice_parse_vsi_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2511 struct ice_aqc_list_caps_elem *cap)
2512{
2513 u32 number = le32_to_cpu(cap->number);
2514
2515 dev_p->num_vsi_allocd_to_host = number;
2516 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_vsi_allocd_to_host = %d\n",
2517 dev_p->num_vsi_allocd_to_host);
2518}
2519
2520/**
2521 * ice_parse_1588_dev_caps - Parse ICE_AQC_CAPS_1588 device caps
2522 * @hw: pointer to the HW struct
2523 * @dev_p: pointer to device capabilities structure
2524 * @cap: capability element to parse
2525 *
2526 * Parse ICE_AQC_CAPS_1588 for device capabilities.
2527 */
2528static void
2529ice_parse_1588_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2530 struct ice_aqc_list_caps_elem *cap)
2531{
2532 struct ice_ts_dev_info *info = &dev_p->ts_dev_info;
2533 u32 logical_id = le32_to_cpu(cap->logical_id);
2534 u32 phys_id = le32_to_cpu(cap->phys_id);
2535 u32 number = le32_to_cpu(cap->number);
2536
2537 info->ena = ((number & ICE_TS_DEV_ENA_M) != 0);
2538 dev_p->common_cap.ieee_1588 = info->ena;
2539
2540 info->tmr0_owner = number & ICE_TS_TMR0_OWNR_M;
2541 info->tmr0_owned = ((number & ICE_TS_TMR0_OWND_M) != 0);
2542 info->tmr0_ena = ((number & ICE_TS_TMR0_ENA_M) != 0);
2543
2544 info->tmr1_owner = FIELD_GET(ICE_TS_TMR1_OWNR_M, number);
2545 info->tmr1_owned = ((number & ICE_TS_TMR1_OWND_M) != 0);
2546 info->tmr1_ena = ((number & ICE_TS_TMR1_ENA_M) != 0);
2547
2548 info->ts_ll_read = ((number & ICE_TS_LL_TX_TS_READ_M) != 0);
2549 info->ts_ll_int_read = ((number & ICE_TS_LL_TX_TS_INT_READ_M) != 0);
2550
2551 info->ena_ports = logical_id;
2552 info->tmr_own_map = phys_id;
2553
2554 ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 = %u\n",
2555 dev_p->common_cap.ieee_1588);
2556 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owner = %u\n",
2557 info->tmr0_owner);
2558 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owned = %u\n",
2559 info->tmr0_owned);
2560 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_ena = %u\n",
2561 info->tmr0_ena);
2562 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owner = %u\n",
2563 info->tmr1_owner);
2564 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owned = %u\n",
2565 info->tmr1_owned);
2566 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_ena = %u\n",
2567 info->tmr1_ena);
2568 ice_debug(hw, ICE_DBG_INIT, "dev caps: ts_ll_read = %u\n",
2569 info->ts_ll_read);
2570 ice_debug(hw, ICE_DBG_INIT, "dev caps: ts_ll_int_read = %u\n",
2571 info->ts_ll_int_read);
2572 ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 ena_ports = %u\n",
2573 info->ena_ports);
2574 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr_own_map = %u\n",
2575 info->tmr_own_map);
2576}
2577
2578/**
2579 * ice_parse_fdir_dev_caps - Parse ICE_AQC_CAPS_FD device caps
2580 * @hw: pointer to the HW struct
2581 * @dev_p: pointer to device capabilities structure
2582 * @cap: capability element to parse
2583 *
2584 * Parse ICE_AQC_CAPS_FD for device capabilities.
2585 */
2586static void
2587ice_parse_fdir_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2588 struct ice_aqc_list_caps_elem *cap)
2589{
2590 u32 number = le32_to_cpu(cap->number);
2591
2592 dev_p->num_flow_director_fltr = number;
2593 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_flow_director_fltr = %d\n",
2594 dev_p->num_flow_director_fltr);
2595}
2596
2597/**
2598 * ice_parse_sensor_reading_cap - Parse ICE_AQC_CAPS_SENSOR_READING cap
2599 * @hw: pointer to the HW struct
2600 * @dev_p: pointer to device capabilities structure
2601 * @cap: capability element to parse
2602 *
2603 * Parse ICE_AQC_CAPS_SENSOR_READING for device capability for reading
2604 * enabled sensors.
2605 */
2606static void
2607ice_parse_sensor_reading_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2608 struct ice_aqc_list_caps_elem *cap)
2609{
2610 dev_p->supported_sensors = le32_to_cpu(cap->number);
2611
2612 ice_debug(hw, ICE_DBG_INIT,
2613 "dev caps: supported sensors (bitmap) = 0x%x\n",
2614 dev_p->supported_sensors);
2615}
2616
2617/**
2618 * ice_parse_nac_topo_dev_caps - Parse ICE_AQC_CAPS_NAC_TOPOLOGY cap
2619 * @hw: pointer to the HW struct
2620 * @dev_p: pointer to device capabilities structure
2621 * @cap: capability element to parse
2622 *
2623 * Parse ICE_AQC_CAPS_NAC_TOPOLOGY for device capabilities.
2624 */
2625static void ice_parse_nac_topo_dev_caps(struct ice_hw *hw,
2626 struct ice_hw_dev_caps *dev_p,
2627 struct ice_aqc_list_caps_elem *cap)
2628{
2629 dev_p->nac_topo.mode = le32_to_cpu(cap->number);
2630 dev_p->nac_topo.id = le32_to_cpu(cap->phys_id) & ICE_NAC_TOPO_ID_M;
2631
2632 dev_info(ice_hw_to_dev(hw),
2633 "PF is configured in %s mode with IP instance ID %d\n",
2634 (dev_p->nac_topo.mode & ICE_NAC_TOPO_PRIMARY_M) ?
2635 "primary" : "secondary", dev_p->nac_topo.id);
2636
2637 ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology is_primary = %d\n",
2638 !!(dev_p->nac_topo.mode & ICE_NAC_TOPO_PRIMARY_M));
2639 ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology is_dual = %d\n",
2640 !!(dev_p->nac_topo.mode & ICE_NAC_TOPO_DUAL_M));
2641 ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology id = %d\n",
2642 dev_p->nac_topo.id);
2643}
2644
2645/**
2646 * ice_parse_dev_caps - Parse device capabilities
2647 * @hw: pointer to the HW struct
2648 * @dev_p: pointer to device capabilities structure
2649 * @buf: buffer containing the device capability records
2650 * @cap_count: the number of capabilities
2651 *
2652 * Helper device to parse device (0x000B) capabilities list. For
2653 * capabilities shared between device and function, this relies on
2654 * ice_parse_common_caps.
2655 *
2656 * Loop through the list of provided capabilities and extract the relevant
2657 * data into the device capabilities structured.
2658 */
2659static void
2660ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2661 void *buf, u32 cap_count)
2662{
2663 struct ice_aqc_list_caps_elem *cap_resp;
2664 u32 i;
2665
2666 cap_resp = buf;
2667
2668 memset(dev_p, 0, sizeof(*dev_p));
2669
2670 for (i = 0; i < cap_count; i++) {
2671 u16 cap = le16_to_cpu(cap_resp[i].cap);
2672 bool found;
2673
2674 found = ice_parse_common_caps(hw, &dev_p->common_cap,
2675 &cap_resp[i], "dev caps");
2676
2677 switch (cap) {
2678 case ICE_AQC_CAPS_VALID_FUNCTIONS:
2679 ice_parse_valid_functions_cap(hw, dev_p, &cap_resp[i]);
2680 break;
2681 case ICE_AQC_CAPS_VF:
2682 ice_parse_vf_dev_caps(hw, dev_p, &cap_resp[i]);
2683 break;
2684 case ICE_AQC_CAPS_VSI:
2685 ice_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]);
2686 break;
2687 case ICE_AQC_CAPS_1588:
2688 ice_parse_1588_dev_caps(hw, dev_p, &cap_resp[i]);
2689 break;
2690 case ICE_AQC_CAPS_FD:
2691 ice_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]);
2692 break;
2693 case ICE_AQC_CAPS_SENSOR_READING:
2694 ice_parse_sensor_reading_cap(hw, dev_p, &cap_resp[i]);
2695 break;
2696 case ICE_AQC_CAPS_NAC_TOPOLOGY:
2697 ice_parse_nac_topo_dev_caps(hw, dev_p, &cap_resp[i]);
2698 break;
2699 default:
2700 /* Don't list common capabilities as unknown */
2701 if (!found)
2702 ice_debug(hw, ICE_DBG_INIT, "dev caps: unknown capability[%d]: 0x%x\n",
2703 i, cap);
2704 break;
2705 }
2706 }
2707
2708 ice_recalc_port_limited_caps(hw, &dev_p->common_cap);
2709}
2710
2711/**
2712 * ice_is_pf_c827 - check if pf contains c827 phy
2713 * @hw: pointer to the hw struct
2714 */
2715bool ice_is_pf_c827(struct ice_hw *hw)
2716{
2717 struct ice_aqc_get_link_topo cmd = {};
2718 u8 node_part_number;
2719 u16 node_handle;
2720 int status;
2721
2722 if (hw->mac_type != ICE_MAC_E810)
2723 return false;
2724
2725 if (hw->device_id != ICE_DEV_ID_E810C_QSFP)
2726 return true;
2727
2728 cmd.addr.topo_params.node_type_ctx =
2729 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_TYPE_M, ICE_AQC_LINK_TOPO_NODE_TYPE_PHY) |
2730 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_CTX_M, ICE_AQC_LINK_TOPO_NODE_CTX_PORT);
2731 cmd.addr.topo_params.index = 0;
2732
2733 status = ice_aq_get_netlist_node(hw, &cmd, &node_part_number,
2734 &node_handle);
2735
2736 if (status || node_part_number != ICE_AQC_GET_LINK_TOPO_NODE_NR_C827)
2737 return false;
2738
2739 if (node_handle == E810C_QSFP_C827_0_HANDLE || node_handle == E810C_QSFP_C827_1_HANDLE)
2740 return true;
2741
2742 return false;
2743}
2744
2745/**
2746 * ice_is_phy_rclk_in_netlist
2747 * @hw: pointer to the hw struct
2748 *
2749 * Check if the PHY Recovered Clock device is present in the netlist
2750 */
2751bool ice_is_phy_rclk_in_netlist(struct ice_hw *hw)
2752{
2753 if (ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_PHY,
2754 ICE_AQC_LINK_TOPO_NODE_CTX_PORT,
2755 ICE_AQC_GET_LINK_TOPO_NODE_NR_C827, NULL) &&
2756 ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_PHY,
2757 ICE_AQC_LINK_TOPO_NODE_CTX_PORT,
2758 ICE_AQC_GET_LINK_TOPO_NODE_NR_E822_PHY, NULL))
2759 return false;
2760
2761 return true;
2762}
2763
2764/**
2765 * ice_is_clock_mux_in_netlist
2766 * @hw: pointer to the hw struct
2767 *
2768 * Check if the Clock Multiplexer device is present in the netlist
2769 */
2770bool ice_is_clock_mux_in_netlist(struct ice_hw *hw)
2771{
2772 if (ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_MUX,
2773 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL,
2774 ICE_AQC_GET_LINK_TOPO_NODE_NR_GEN_CLK_MUX,
2775 NULL))
2776 return false;
2777
2778 return true;
2779}
2780
2781/**
2782 * ice_is_cgu_in_netlist - check for CGU presence
2783 * @hw: pointer to the hw struct
2784 *
2785 * Check if the Clock Generation Unit (CGU) device is present in the netlist.
2786 * Save the CGU part number in the hw structure for later use.
2787 * Return:
2788 * * true - cgu is present
2789 * * false - cgu is not present
2790 */
2791bool ice_is_cgu_in_netlist(struct ice_hw *hw)
2792{
2793 if (!ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_CTRL,
2794 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL,
2795 ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032,
2796 NULL)) {
2797 hw->cgu_part_number = ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032;
2798 return true;
2799 } else if (!ice_find_netlist_node(hw,
2800 ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_CTRL,
2801 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL,
2802 ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384,
2803 NULL)) {
2804 hw->cgu_part_number = ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384;
2805 return true;
2806 }
2807
2808 return false;
2809}
2810
2811/**
2812 * ice_is_gps_in_netlist
2813 * @hw: pointer to the hw struct
2814 *
2815 * Check if the GPS generic device is present in the netlist
2816 */
2817bool ice_is_gps_in_netlist(struct ice_hw *hw)
2818{
2819 if (ice_find_netlist_node(hw, ICE_AQC_LINK_TOPO_NODE_TYPE_GPS,
2820 ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL,
2821 ICE_AQC_GET_LINK_TOPO_NODE_NR_GEN_GPS, NULL))
2822 return false;
2823
2824 return true;
2825}
2826
2827/**
2828 * ice_aq_list_caps - query function/device capabilities
2829 * @hw: pointer to the HW struct
2830 * @buf: a buffer to hold the capabilities
2831 * @buf_size: size of the buffer
2832 * @cap_count: if not NULL, set to the number of capabilities reported
2833 * @opc: capabilities type to discover, device or function
2834 * @cd: pointer to command details structure or NULL
2835 *
2836 * Get the function (0x000A) or device (0x000B) capabilities description from
2837 * firmware and store it in the buffer.
2838 *
2839 * If the cap_count pointer is not NULL, then it is set to the number of
2840 * capabilities firmware will report. Note that if the buffer size is too
2841 * small, it is possible the command will return ICE_AQ_ERR_ENOMEM. The
2842 * cap_count will still be updated in this case. It is recommended that the
2843 * buffer size be set to ICE_AQ_MAX_BUF_LEN (the largest possible buffer that
2844 * firmware could return) to avoid this.
2845 */
2846int
2847ice_aq_list_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count,
2848 enum ice_adminq_opc opc, struct ice_sq_cd *cd)
2849{
2850 struct ice_aqc_list_caps *cmd;
2851 struct ice_aq_desc desc;
2852 int status;
2853
2854 cmd = &desc.params.get_cap;
2855
2856 if (opc != ice_aqc_opc_list_func_caps &&
2857 opc != ice_aqc_opc_list_dev_caps)
2858 return -EINVAL;
2859
2860 ice_fill_dflt_direct_cmd_desc(&desc, opc);
2861 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
2862
2863 if (cap_count)
2864 *cap_count = le32_to_cpu(cmd->count);
2865
2866 return status;
2867}
2868
2869/**
2870 * ice_discover_dev_caps - Read and extract device capabilities
2871 * @hw: pointer to the hardware structure
2872 * @dev_caps: pointer to device capabilities structure
2873 *
2874 * Read the device capabilities and extract them into the dev_caps structure
2875 * for later use.
2876 */
2877int
2878ice_discover_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_caps)
2879{
2880 u32 cap_count = 0;
2881 void *cbuf;
2882 int status;
2883
2884 cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL);
2885 if (!cbuf)
2886 return -ENOMEM;
2887
2888 /* Although the driver doesn't know the number of capabilities the
2889 * device will return, we can simply send a 4KB buffer, the maximum
2890 * possible size that firmware can return.
2891 */
2892 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem);
2893
2894 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count,
2895 ice_aqc_opc_list_dev_caps, NULL);
2896 if (!status)
2897 ice_parse_dev_caps(hw, dev_caps, cbuf, cap_count);
2898 kfree(cbuf);
2899
2900 return status;
2901}
2902
2903/**
2904 * ice_discover_func_caps - Read and extract function capabilities
2905 * @hw: pointer to the hardware structure
2906 * @func_caps: pointer to function capabilities structure
2907 *
2908 * Read the function capabilities and extract them into the func_caps structure
2909 * for later use.
2910 */
2911static int
2912ice_discover_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_caps)
2913{
2914 u32 cap_count = 0;
2915 void *cbuf;
2916 int status;
2917
2918 cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL);
2919 if (!cbuf)
2920 return -ENOMEM;
2921
2922 /* Although the driver doesn't know the number of capabilities the
2923 * device will return, we can simply send a 4KB buffer, the maximum
2924 * possible size that firmware can return.
2925 */
2926 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem);
2927
2928 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count,
2929 ice_aqc_opc_list_func_caps, NULL);
2930 if (!status)
2931 ice_parse_func_caps(hw, func_caps, cbuf, cap_count);
2932 kfree(cbuf);
2933
2934 return status;
2935}
2936
2937/**
2938 * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode
2939 * @hw: pointer to the hardware structure
2940 */
2941void ice_set_safe_mode_caps(struct ice_hw *hw)
2942{
2943 struct ice_hw_func_caps *func_caps = &hw->func_caps;
2944 struct ice_hw_dev_caps *dev_caps = &hw->dev_caps;
2945 struct ice_hw_common_caps cached_caps;
2946 u32 num_funcs;
2947
2948 /* cache some func_caps values that should be restored after memset */
2949 cached_caps = func_caps->common_cap;
2950
2951 /* unset func capabilities */
2952 memset(func_caps, 0, sizeof(*func_caps));
2953
2954#define ICE_RESTORE_FUNC_CAP(name) \
2955 func_caps->common_cap.name = cached_caps.name
2956
2957 /* restore cached values */
2958 ICE_RESTORE_FUNC_CAP(valid_functions);
2959 ICE_RESTORE_FUNC_CAP(txq_first_id);
2960 ICE_RESTORE_FUNC_CAP(rxq_first_id);
2961 ICE_RESTORE_FUNC_CAP(msix_vector_first_id);
2962 ICE_RESTORE_FUNC_CAP(max_mtu);
2963 ICE_RESTORE_FUNC_CAP(nvm_unified_update);
2964 ICE_RESTORE_FUNC_CAP(nvm_update_pending_nvm);
2965 ICE_RESTORE_FUNC_CAP(nvm_update_pending_orom);
2966 ICE_RESTORE_FUNC_CAP(nvm_update_pending_netlist);
2967
2968 /* one Tx and one Rx queue in safe mode */
2969 func_caps->common_cap.num_rxq = 1;
2970 func_caps->common_cap.num_txq = 1;
2971
2972 /* two MSIX vectors, one for traffic and one for misc causes */
2973 func_caps->common_cap.num_msix_vectors = 2;
2974 func_caps->guar_num_vsi = 1;
2975
2976 /* cache some dev_caps values that should be restored after memset */
2977 cached_caps = dev_caps->common_cap;
2978 num_funcs = dev_caps->num_funcs;
2979
2980 /* unset dev capabilities */
2981 memset(dev_caps, 0, sizeof(*dev_caps));
2982
2983#define ICE_RESTORE_DEV_CAP(name) \
2984 dev_caps->common_cap.name = cached_caps.name
2985
2986 /* restore cached values */
2987 ICE_RESTORE_DEV_CAP(valid_functions);
2988 ICE_RESTORE_DEV_CAP(txq_first_id);
2989 ICE_RESTORE_DEV_CAP(rxq_first_id);
2990 ICE_RESTORE_DEV_CAP(msix_vector_first_id);
2991 ICE_RESTORE_DEV_CAP(max_mtu);
2992 ICE_RESTORE_DEV_CAP(nvm_unified_update);
2993 ICE_RESTORE_DEV_CAP(nvm_update_pending_nvm);
2994 ICE_RESTORE_DEV_CAP(nvm_update_pending_orom);
2995 ICE_RESTORE_DEV_CAP(nvm_update_pending_netlist);
2996 dev_caps->num_funcs = num_funcs;
2997
2998 /* one Tx and one Rx queue per function in safe mode */
2999 dev_caps->common_cap.num_rxq = num_funcs;
3000 dev_caps->common_cap.num_txq = num_funcs;
3001
3002 /* two MSIX vectors per function */
3003 dev_caps->common_cap.num_msix_vectors = 2 * num_funcs;
3004}
3005
3006/**
3007 * ice_get_caps - get info about the HW
3008 * @hw: pointer to the hardware structure
3009 */
3010int ice_get_caps(struct ice_hw *hw)
3011{
3012 int status;
3013
3014 status = ice_discover_dev_caps(hw, &hw->dev_caps);
3015 if (status)
3016 return status;
3017
3018 return ice_discover_func_caps(hw, &hw->func_caps);
3019}
3020
3021/**
3022 * ice_aq_manage_mac_write - manage MAC address write command
3023 * @hw: pointer to the HW struct
3024 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address
3025 * @flags: flags to control write behavior
3026 * @cd: pointer to command details structure or NULL
3027 *
3028 * This function is used to write MAC address to the NVM (0x0108).
3029 */
3030int
3031ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags,
3032 struct ice_sq_cd *cd)
3033{
3034 struct ice_aqc_manage_mac_write *cmd;
3035 struct ice_aq_desc desc;
3036
3037 cmd = &desc.params.mac_write;
3038 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write);
3039
3040 cmd->flags = flags;
3041 ether_addr_copy(cmd->mac_addr, mac_addr);
3042
3043 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
3044}
3045
3046/**
3047 * ice_aq_clear_pxe_mode
3048 * @hw: pointer to the HW struct
3049 *
3050 * Tell the firmware that the driver is taking over from PXE (0x0110).
3051 */
3052static int ice_aq_clear_pxe_mode(struct ice_hw *hw)
3053{
3054 struct ice_aq_desc desc;
3055
3056 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode);
3057 desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT;
3058
3059 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
3060}
3061
3062/**
3063 * ice_clear_pxe_mode - clear pxe operations mode
3064 * @hw: pointer to the HW struct
3065 *
3066 * Make sure all PXE mode settings are cleared, including things
3067 * like descriptor fetch/write-back mode.
3068 */
3069void ice_clear_pxe_mode(struct ice_hw *hw)
3070{
3071 if (ice_check_sq_alive(hw, &hw->adminq))
3072 ice_aq_clear_pxe_mode(hw);
3073}
3074
3075/**
3076 * ice_aq_set_port_params - set physical port parameters.
3077 * @pi: pointer to the port info struct
3078 * @double_vlan: if set double VLAN is enabled
3079 * @cd: pointer to command details structure or NULL
3080 *
3081 * Set Physical port parameters (0x0203)
3082 */
3083int
3084ice_aq_set_port_params(struct ice_port_info *pi, bool double_vlan,
3085 struct ice_sq_cd *cd)
3086
3087{
3088 struct ice_aqc_set_port_params *cmd;
3089 struct ice_hw *hw = pi->hw;
3090 struct ice_aq_desc desc;
3091 u16 cmd_flags = 0;
3092
3093 cmd = &desc.params.set_port_params;
3094
3095 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_params);
3096 if (double_vlan)
3097 cmd_flags |= ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA;
3098 cmd->cmd_flags = cpu_to_le16(cmd_flags);
3099
3100 cmd->local_fwd_mode = pi->local_fwd_mode |
3101 ICE_AQC_SET_P_PARAMS_LOCAL_FWD_MODE_VALID;
3102
3103 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
3104}
3105
3106/**
3107 * ice_is_100m_speed_supported
3108 * @hw: pointer to the HW struct
3109 *
3110 * returns true if 100M speeds are supported by the device,
3111 * false otherwise.
3112 */
3113bool ice_is_100m_speed_supported(struct ice_hw *hw)
3114{
3115 switch (hw->device_id) {
3116 case ICE_DEV_ID_E822C_SGMII:
3117 case ICE_DEV_ID_E822L_SGMII:
3118 case ICE_DEV_ID_E823L_1GBE:
3119 case ICE_DEV_ID_E823C_SGMII:
3120 return true;
3121 default:
3122 return false;
3123 }
3124}
3125
3126/**
3127 * ice_get_link_speed_based_on_phy_type - returns link speed
3128 * @phy_type_low: lower part of phy_type
3129 * @phy_type_high: higher part of phy_type
3130 *
3131 * This helper function will convert an entry in PHY type structure
3132 * [phy_type_low, phy_type_high] to its corresponding link speed.
3133 * Note: In the structure of [phy_type_low, phy_type_high], there should
3134 * be one bit set, as this function will convert one PHY type to its
3135 * speed.
3136 *
3137 * Return:
3138 * * PHY speed for recognized PHY type
3139 * * If no bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned
3140 * * If more than one bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned
3141 */
3142u16 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high)
3143{
3144 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
3145 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
3146
3147 switch (phy_type_low) {
3148 case ICE_PHY_TYPE_LOW_100BASE_TX:
3149 case ICE_PHY_TYPE_LOW_100M_SGMII:
3150 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB;
3151 break;
3152 case ICE_PHY_TYPE_LOW_1000BASE_T:
3153 case ICE_PHY_TYPE_LOW_1000BASE_SX:
3154 case ICE_PHY_TYPE_LOW_1000BASE_LX:
3155 case ICE_PHY_TYPE_LOW_1000BASE_KX:
3156 case ICE_PHY_TYPE_LOW_1G_SGMII:
3157 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB;
3158 break;
3159 case ICE_PHY_TYPE_LOW_2500BASE_T:
3160 case ICE_PHY_TYPE_LOW_2500BASE_X:
3161 case ICE_PHY_TYPE_LOW_2500BASE_KX:
3162 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB;
3163 break;
3164 case ICE_PHY_TYPE_LOW_5GBASE_T:
3165 case ICE_PHY_TYPE_LOW_5GBASE_KR:
3166 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB;
3167 break;
3168 case ICE_PHY_TYPE_LOW_10GBASE_T:
3169 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
3170 case ICE_PHY_TYPE_LOW_10GBASE_SR:
3171 case ICE_PHY_TYPE_LOW_10GBASE_LR:
3172 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
3173 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC:
3174 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
3175 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB;
3176 break;
3177 case ICE_PHY_TYPE_LOW_25GBASE_T:
3178 case ICE_PHY_TYPE_LOW_25GBASE_CR:
3179 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
3180 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
3181 case ICE_PHY_TYPE_LOW_25GBASE_SR:
3182 case ICE_PHY_TYPE_LOW_25GBASE_LR:
3183 case ICE_PHY_TYPE_LOW_25GBASE_KR:
3184 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
3185 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
3186 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC:
3187 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
3188 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB;
3189 break;
3190 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
3191 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
3192 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
3193 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
3194 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC:
3195 case ICE_PHY_TYPE_LOW_40G_XLAUI:
3196 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB;
3197 break;
3198 case ICE_PHY_TYPE_LOW_50GBASE_CR2:
3199 case ICE_PHY_TYPE_LOW_50GBASE_SR2:
3200 case ICE_PHY_TYPE_LOW_50GBASE_LR2:
3201 case ICE_PHY_TYPE_LOW_50GBASE_KR2:
3202 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC:
3203 case ICE_PHY_TYPE_LOW_50G_LAUI2:
3204 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC:
3205 case ICE_PHY_TYPE_LOW_50G_AUI2:
3206 case ICE_PHY_TYPE_LOW_50GBASE_CP:
3207 case ICE_PHY_TYPE_LOW_50GBASE_SR:
3208 case ICE_PHY_TYPE_LOW_50GBASE_FR:
3209 case ICE_PHY_TYPE_LOW_50GBASE_LR:
3210 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
3211 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC:
3212 case ICE_PHY_TYPE_LOW_50G_AUI1:
3213 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB;
3214 break;
3215 case ICE_PHY_TYPE_LOW_100GBASE_CR4:
3216 case ICE_PHY_TYPE_LOW_100GBASE_SR4:
3217 case ICE_PHY_TYPE_LOW_100GBASE_LR4:
3218 case ICE_PHY_TYPE_LOW_100GBASE_KR4:
3219 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC:
3220 case ICE_PHY_TYPE_LOW_100G_CAUI4:
3221 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC:
3222 case ICE_PHY_TYPE_LOW_100G_AUI4:
3223 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
3224 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
3225 case ICE_PHY_TYPE_LOW_100GBASE_CP2:
3226 case ICE_PHY_TYPE_LOW_100GBASE_SR2:
3227 case ICE_PHY_TYPE_LOW_100GBASE_DR:
3228 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB;
3229 break;
3230 default:
3231 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
3232 break;
3233 }
3234
3235 switch (phy_type_high) {
3236 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
3237 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC:
3238 case ICE_PHY_TYPE_HIGH_100G_CAUI2:
3239 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC:
3240 case ICE_PHY_TYPE_HIGH_100G_AUI2:
3241 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB;
3242 break;
3243 case ICE_PHY_TYPE_HIGH_200G_CR4_PAM4:
3244 case ICE_PHY_TYPE_HIGH_200G_SR4:
3245 case ICE_PHY_TYPE_HIGH_200G_FR4:
3246 case ICE_PHY_TYPE_HIGH_200G_LR4:
3247 case ICE_PHY_TYPE_HIGH_200G_DR4:
3248 case ICE_PHY_TYPE_HIGH_200G_KR4_PAM4:
3249 case ICE_PHY_TYPE_HIGH_200G_AUI4_AOC_ACC:
3250 case ICE_PHY_TYPE_HIGH_200G_AUI4:
3251 speed_phy_type_high = ICE_AQ_LINK_SPEED_200GB;
3252 break;
3253 default:
3254 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
3255 break;
3256 }
3257
3258 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN &&
3259 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
3260 return ICE_AQ_LINK_SPEED_UNKNOWN;
3261 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
3262 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN)
3263 return ICE_AQ_LINK_SPEED_UNKNOWN;
3264 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
3265 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
3266 return speed_phy_type_low;
3267 else
3268 return speed_phy_type_high;
3269}
3270
3271/**
3272 * ice_update_phy_type
3273 * @phy_type_low: pointer to the lower part of phy_type
3274 * @phy_type_high: pointer to the higher part of phy_type
3275 * @link_speeds_bitmap: targeted link speeds bitmap
3276 *
3277 * Note: For the link_speeds_bitmap structure, you can check it at
3278 * [ice_aqc_get_link_status->link_speed]. Caller can pass in
3279 * link_speeds_bitmap include multiple speeds.
3280 *
3281 * Each entry in this [phy_type_low, phy_type_high] structure will
3282 * present a certain link speed. This helper function will turn on bits
3283 * in [phy_type_low, phy_type_high] structure based on the value of
3284 * link_speeds_bitmap input parameter.
3285 */
3286void
3287ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high,
3288 u16 link_speeds_bitmap)
3289{
3290 u64 pt_high;
3291 u64 pt_low;
3292 int index;
3293 u16 speed;
3294
3295 /* We first check with low part of phy_type */
3296 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) {
3297 pt_low = BIT_ULL(index);
3298 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0);
3299
3300 if (link_speeds_bitmap & speed)
3301 *phy_type_low |= BIT_ULL(index);
3302 }
3303
3304 /* We then check with high part of phy_type */
3305 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) {
3306 pt_high = BIT_ULL(index);
3307 speed = ice_get_link_speed_based_on_phy_type(0, pt_high);
3308
3309 if (link_speeds_bitmap & speed)
3310 *phy_type_high |= BIT_ULL(index);
3311 }
3312}
3313
3314/**
3315 * ice_aq_set_phy_cfg
3316 * @hw: pointer to the HW struct
3317 * @pi: port info structure of the interested logical port
3318 * @cfg: structure with PHY configuration data to be set
3319 * @cd: pointer to command details structure or NULL
3320 *
3321 * Set the various PHY configuration parameters supported on the Port.
3322 * One or more of the Set PHY config parameters may be ignored in an MFP
3323 * mode as the PF may not have the privilege to set some of the PHY Config
3324 * parameters. This status will be indicated by the command response (0x0601).
3325 */
3326int
3327ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi,
3328 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd)
3329{
3330 struct ice_aq_desc desc;
3331 int status;
3332
3333 if (!cfg)
3334 return -EINVAL;
3335
3336 /* Ensure that only valid bits of cfg->caps can be turned on. */
3337 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) {
3338 ice_debug(hw, ICE_DBG_PHY, "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n",
3339 cfg->caps);
3340
3341 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK;
3342 }
3343
3344 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg);
3345 desc.params.set_phy.lport_num = pi->lport;
3346 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
3347
3348 ice_debug(hw, ICE_DBG_LINK, "set phy cfg\n");
3349 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n",
3350 (unsigned long long)le64_to_cpu(cfg->phy_type_low));
3351 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n",
3352 (unsigned long long)le64_to_cpu(cfg->phy_type_high));
3353 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", cfg->caps);
3354 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n",
3355 cfg->low_power_ctrl_an);
3356 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", cfg->eee_cap);
3357 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", cfg->eeer_value);
3358 ice_debug(hw, ICE_DBG_LINK, " link_fec_opt = 0x%x\n",
3359 cfg->link_fec_opt);
3360
3361 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd);
3362 if (hw->adminq.sq_last_status == ICE_AQ_RC_EMODE)
3363 status = 0;
3364
3365 if (!status)
3366 pi->phy.curr_user_phy_cfg = *cfg;
3367
3368 return status;
3369}
3370
3371/**
3372 * ice_update_link_info - update status of the HW network link
3373 * @pi: port info structure of the interested logical port
3374 */
3375int ice_update_link_info(struct ice_port_info *pi)
3376{
3377 struct ice_link_status *li;
3378 int status;
3379
3380 if (!pi)
3381 return -EINVAL;
3382
3383 li = &pi->phy.link_info;
3384
3385 status = ice_aq_get_link_info(pi, true, NULL, NULL);
3386 if (status)
3387 return status;
3388
3389 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) {
3390 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL;
3391
3392 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL);
3393 if (!pcaps)
3394 return -ENOMEM;
3395
3396 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP_MEDIA,
3397 pcaps, NULL);
3398 }
3399
3400 return status;
3401}
3402
3403/**
3404 * ice_aq_get_phy_equalization - function to read serdes equaliser
3405 * value from firmware using admin queue command.
3406 * @hw: pointer to the HW struct
3407 * @data_in: represents the serdes equalization parameter requested
3408 * @op_code: represents the serdes number and flag to represent tx or rx
3409 * @serdes_num: represents the serdes number
3410 * @output: pointer to the caller-supplied buffer to return serdes equaliser
3411 *
3412 * Return: non-zero status on error and 0 on success.
3413 */
3414int ice_aq_get_phy_equalization(struct ice_hw *hw, u16 data_in, u16 op_code,
3415 u8 serdes_num, int *output)
3416{
3417 struct ice_aqc_dnl_call_command *cmd;
3418 struct ice_aqc_dnl_call buf = {};
3419 struct ice_aq_desc desc;
3420 int err;
3421
3422 buf.sto.txrx_equa_reqs.data_in = cpu_to_le16(data_in);
3423 buf.sto.txrx_equa_reqs.op_code_serdes_sel =
3424 cpu_to_le16(op_code | (serdes_num & 0xF));
3425 cmd = &desc.params.dnl_call;
3426 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dnl_call);
3427 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_BUF |
3428 ICE_AQ_FLAG_RD |
3429 ICE_AQ_FLAG_SI);
3430 desc.datalen = cpu_to_le16(sizeof(struct ice_aqc_dnl_call));
3431 cmd->activity_id = cpu_to_le16(ICE_AQC_ACT_ID_DNL);
3432
3433 err = ice_aq_send_cmd(hw, &desc, &buf, sizeof(struct ice_aqc_dnl_call),
3434 NULL);
3435 *output = err ? 0 : buf.sto.txrx_equa_resp.val;
3436
3437 return err;
3438}
3439
3440#define FEC_REG_PORT(port) { \
3441 FEC_CORR_LOW_REG_PORT##port, \
3442 FEC_CORR_HIGH_REG_PORT##port, \
3443 FEC_UNCORR_LOW_REG_PORT##port, \
3444 FEC_UNCORR_HIGH_REG_PORT##port, \
3445}
3446
3447static const u32 fec_reg[][ICE_FEC_MAX] = {
3448 FEC_REG_PORT(0),
3449 FEC_REG_PORT(1),
3450 FEC_REG_PORT(2),
3451 FEC_REG_PORT(3)
3452};
3453
3454/**
3455 * ice_aq_get_fec_stats - reads fec stats from phy
3456 * @hw: pointer to the HW struct
3457 * @pcs_quad: represents pcsquad of user input serdes
3458 * @pcs_port: represents the pcs port number part of above pcs quad
3459 * @fec_type: represents FEC stats type
3460 * @output: pointer to the caller-supplied buffer to return requested fec stats
3461 *
3462 * Return: non-zero status on error and 0 on success.
3463 */
3464int ice_aq_get_fec_stats(struct ice_hw *hw, u16 pcs_quad, u16 pcs_port,
3465 enum ice_fec_stats_types fec_type, u32 *output)
3466{
3467 u16 flag = (ICE_AQ_FLAG_RD | ICE_AQ_FLAG_BUF | ICE_AQ_FLAG_SI);
3468 struct ice_sbq_msg_input msg = {};
3469 u32 receiver_id, reg_offset;
3470 int err;
3471
3472 if (pcs_port > 3)
3473 return -EINVAL;
3474
3475 reg_offset = fec_reg[pcs_port][fec_type];
3476
3477 if (pcs_quad == 0)
3478 receiver_id = FEC_RECEIVER_ID_PCS0;
3479 else if (pcs_quad == 1)
3480 receiver_id = FEC_RECEIVER_ID_PCS1;
3481 else
3482 return -EINVAL;
3483
3484 msg.msg_addr_low = lower_16_bits(reg_offset);
3485 msg.msg_addr_high = receiver_id;
3486 msg.opcode = ice_sbq_msg_rd;
3487 msg.dest_dev = rmn_0;
3488
3489 err = ice_sbq_rw_reg(hw, &msg, flag);
3490 if (err)
3491 return err;
3492
3493 *output = msg.data;
3494 return 0;
3495}
3496
3497/**
3498 * ice_cache_phy_user_req
3499 * @pi: port information structure
3500 * @cache_data: PHY logging data
3501 * @cache_mode: PHY logging mode
3502 *
3503 * Log the user request on (FC, FEC, SPEED) for later use.
3504 */
3505static void
3506ice_cache_phy_user_req(struct ice_port_info *pi,
3507 struct ice_phy_cache_mode_data cache_data,
3508 enum ice_phy_cache_mode cache_mode)
3509{
3510 if (!pi)
3511 return;
3512
3513 switch (cache_mode) {
3514 case ICE_FC_MODE:
3515 pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req;
3516 break;
3517 case ICE_SPEED_MODE:
3518 pi->phy.curr_user_speed_req =
3519 cache_data.data.curr_user_speed_req;
3520 break;
3521 case ICE_FEC_MODE:
3522 pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req;
3523 break;
3524 default:
3525 break;
3526 }
3527}
3528
3529/**
3530 * ice_caps_to_fc_mode
3531 * @caps: PHY capabilities
3532 *
3533 * Convert PHY FC capabilities to ice FC mode
3534 */
3535enum ice_fc_mode ice_caps_to_fc_mode(u8 caps)
3536{
3537 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE &&
3538 caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE)
3539 return ICE_FC_FULL;
3540
3541 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE)
3542 return ICE_FC_TX_PAUSE;
3543
3544 if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE)
3545 return ICE_FC_RX_PAUSE;
3546
3547 return ICE_FC_NONE;
3548}
3549
3550/**
3551 * ice_caps_to_fec_mode
3552 * @caps: PHY capabilities
3553 * @fec_options: Link FEC options
3554 *
3555 * Convert PHY FEC capabilities to ice FEC mode
3556 */
3557enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options)
3558{
3559 if (caps & ICE_AQC_PHY_EN_AUTO_FEC)
3560 return ICE_FEC_AUTO;
3561
3562 if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
3563 ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
3564 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN |
3565 ICE_AQC_PHY_FEC_25G_KR_REQ))
3566 return ICE_FEC_BASER;
3567
3568 if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ |
3569 ICE_AQC_PHY_FEC_25G_RS_544_REQ |
3570 ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN))
3571 return ICE_FEC_RS;
3572
3573 return ICE_FEC_NONE;
3574}
3575
3576/**
3577 * ice_cfg_phy_fc - Configure PHY FC data based on FC mode
3578 * @pi: port information structure
3579 * @cfg: PHY configuration data to set FC mode
3580 * @req_mode: FC mode to configure
3581 */
3582int
3583ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg,
3584 enum ice_fc_mode req_mode)
3585{
3586 struct ice_phy_cache_mode_data cache_data;
3587 u8 pause_mask = 0x0;
3588
3589 if (!pi || !cfg)
3590 return -EINVAL;
3591
3592 switch (req_mode) {
3593 case ICE_FC_FULL:
3594 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
3595 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
3596 break;
3597 case ICE_FC_RX_PAUSE:
3598 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
3599 break;
3600 case ICE_FC_TX_PAUSE:
3601 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
3602 break;
3603 default:
3604 break;
3605 }
3606
3607 /* clear the old pause settings */
3608 cfg->caps &= ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE |
3609 ICE_AQC_PHY_EN_RX_LINK_PAUSE);
3610
3611 /* set the new capabilities */
3612 cfg->caps |= pause_mask;
3613
3614 /* Cache user FC request */
3615 cache_data.data.curr_user_fc_req = req_mode;
3616 ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE);
3617
3618 return 0;
3619}
3620
3621/**
3622 * ice_set_fc
3623 * @pi: port information structure
3624 * @aq_failures: pointer to status code, specific to ice_set_fc routine
3625 * @ena_auto_link_update: enable automatic link update
3626 *
3627 * Set the requested flow control mode.
3628 */
3629int
3630ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update)
3631{
3632 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL;
3633 struct ice_aqc_set_phy_cfg_data cfg = { 0 };
3634 struct ice_hw *hw;
3635 int status;
3636
3637 if (!pi || !aq_failures)
3638 return -EINVAL;
3639
3640 *aq_failures = 0;
3641 hw = pi->hw;
3642
3643 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL);
3644 if (!pcaps)
3645 return -ENOMEM;
3646
3647 /* Get the current PHY config */
3648 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG,
3649 pcaps, NULL);
3650 if (status) {
3651 *aq_failures = ICE_SET_FC_AQ_FAIL_GET;
3652 goto out;
3653 }
3654
3655 ice_copy_phy_caps_to_cfg(pi, pcaps, &cfg);
3656
3657 /* Configure the set PHY data */
3658 status = ice_cfg_phy_fc(pi, &cfg, pi->fc.req_mode);
3659 if (status)
3660 goto out;
3661
3662 /* If the capabilities have changed, then set the new config */
3663 if (cfg.caps != pcaps->caps) {
3664 int retry_count, retry_max = 10;
3665
3666 /* Auto restart link so settings take effect */
3667 if (ena_auto_link_update)
3668 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
3669
3670 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
3671 if (status) {
3672 *aq_failures = ICE_SET_FC_AQ_FAIL_SET;
3673 goto out;
3674 }
3675
3676 /* Update the link info
3677 * It sometimes takes a really long time for link to
3678 * come back from the atomic reset. Thus, we wait a
3679 * little bit.
3680 */
3681 for (retry_count = 0; retry_count < retry_max; retry_count++) {
3682 status = ice_update_link_info(pi);
3683
3684 if (!status)
3685 break;
3686
3687 mdelay(100);
3688 }
3689
3690 if (status)
3691 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE;
3692 }
3693
3694out:
3695 return status;
3696}
3697
3698/**
3699 * ice_phy_caps_equals_cfg
3700 * @phy_caps: PHY capabilities
3701 * @phy_cfg: PHY configuration
3702 *
3703 * Helper function to determine if PHY capabilities matches PHY
3704 * configuration
3705 */
3706bool
3707ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps,
3708 struct ice_aqc_set_phy_cfg_data *phy_cfg)
3709{
3710 u8 caps_mask, cfg_mask;
3711
3712 if (!phy_caps || !phy_cfg)
3713 return false;
3714
3715 /* These bits are not common between capabilities and configuration.
3716 * Do not use them to determine equality.
3717 */
3718 caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE |
3719 ICE_AQC_GET_PHY_EN_MOD_QUAL);
3720 cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
3721
3722 if (phy_caps->phy_type_low != phy_cfg->phy_type_low ||
3723 phy_caps->phy_type_high != phy_cfg->phy_type_high ||
3724 ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) ||
3725 phy_caps->low_power_ctrl_an != phy_cfg->low_power_ctrl_an ||
3726 phy_caps->eee_cap != phy_cfg->eee_cap ||
3727 phy_caps->eeer_value != phy_cfg->eeer_value ||
3728 phy_caps->link_fec_options != phy_cfg->link_fec_opt)
3729 return false;
3730
3731 return true;
3732}
3733
3734/**
3735 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data
3736 * @pi: port information structure
3737 * @caps: PHY ability structure to copy date from
3738 * @cfg: PHY configuration structure to copy data to
3739 *
3740 * Helper function to copy AQC PHY get ability data to PHY set configuration
3741 * data structure
3742 */
3743void
3744ice_copy_phy_caps_to_cfg(struct ice_port_info *pi,
3745 struct ice_aqc_get_phy_caps_data *caps,
3746 struct ice_aqc_set_phy_cfg_data *cfg)
3747{
3748 if (!pi || !caps || !cfg)
3749 return;
3750
3751 memset(cfg, 0, sizeof(*cfg));
3752 cfg->phy_type_low = caps->phy_type_low;
3753 cfg->phy_type_high = caps->phy_type_high;
3754 cfg->caps = caps->caps;
3755 cfg->low_power_ctrl_an = caps->low_power_ctrl_an;
3756 cfg->eee_cap = caps->eee_cap;
3757 cfg->eeer_value = caps->eeer_value;
3758 cfg->link_fec_opt = caps->link_fec_options;
3759 cfg->module_compliance_enforcement =
3760 caps->module_compliance_enforcement;
3761}
3762
3763/**
3764 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode
3765 * @pi: port information structure
3766 * @cfg: PHY configuration data to set FEC mode
3767 * @fec: FEC mode to configure
3768 */
3769int
3770ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg,
3771 enum ice_fec_mode fec)
3772{
3773 struct ice_aqc_get_phy_caps_data *pcaps __free(kfree) = NULL;
3774 struct ice_hw *hw;
3775 int status;
3776
3777 if (!pi || !cfg)
3778 return -EINVAL;
3779
3780 hw = pi->hw;
3781
3782 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL);
3783 if (!pcaps)
3784 return -ENOMEM;
3785
3786 status = ice_aq_get_phy_caps(pi, false,
3787 (ice_fw_supports_report_dflt_cfg(hw) ?
3788 ICE_AQC_REPORT_DFLT_CFG :
3789 ICE_AQC_REPORT_TOPO_CAP_MEDIA), pcaps, NULL);
3790 if (status)
3791 goto out;
3792
3793 cfg->caps |= pcaps->caps & ICE_AQC_PHY_EN_AUTO_FEC;
3794 cfg->link_fec_opt = pcaps->link_fec_options;
3795
3796 switch (fec) {
3797 case ICE_FEC_BASER:
3798 /* Clear RS bits, and AND BASE-R ability
3799 * bits and OR request bits.
3800 */
3801 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
3802 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN;
3803 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
3804 ICE_AQC_PHY_FEC_25G_KR_REQ;
3805 break;
3806 case ICE_FEC_RS:
3807 /* Clear BASE-R bits, and AND RS ability
3808 * bits and OR request bits.
3809 */
3810 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN;
3811 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ |
3812 ICE_AQC_PHY_FEC_25G_RS_544_REQ;
3813 break;
3814 case ICE_FEC_NONE:
3815 /* Clear all FEC option bits. */
3816 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK;
3817 break;
3818 case ICE_FEC_AUTO:
3819 /* AND auto FEC bit, and all caps bits. */
3820 cfg->caps &= ICE_AQC_PHY_CAPS_MASK;
3821 cfg->link_fec_opt |= pcaps->link_fec_options;
3822 break;
3823 default:
3824 status = -EINVAL;
3825 break;
3826 }
3827
3828 if (fec == ICE_FEC_AUTO && ice_fw_supports_link_override(hw) &&
3829 !ice_fw_supports_report_dflt_cfg(hw)) {
3830 struct ice_link_default_override_tlv tlv = { 0 };
3831
3832 status = ice_get_link_default_override(&tlv, pi);
3833 if (status)
3834 goto out;
3835
3836 if (!(tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) &&
3837 (tlv.options & ICE_LINK_OVERRIDE_EN))
3838 cfg->link_fec_opt = tlv.fec_options;
3839 }
3840
3841out:
3842 return status;
3843}
3844
3845/**
3846 * ice_get_link_status - get status of the HW network link
3847 * @pi: port information structure
3848 * @link_up: pointer to bool (true/false = linkup/linkdown)
3849 *
3850 * Variable link_up is true if link is up, false if link is down.
3851 * The variable link_up is invalid if status is non zero. As a
3852 * result of this call, link status reporting becomes enabled
3853 */
3854int ice_get_link_status(struct ice_port_info *pi, bool *link_up)
3855{
3856 struct ice_phy_info *phy_info;
3857 int status = 0;
3858
3859 if (!pi || !link_up)
3860 return -EINVAL;
3861
3862 phy_info = &pi->phy;
3863
3864 if (phy_info->get_link_info) {
3865 status = ice_update_link_info(pi);
3866
3867 if (status)
3868 ice_debug(pi->hw, ICE_DBG_LINK, "get link status error, status = %d\n",
3869 status);
3870 }
3871
3872 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP;
3873
3874 return status;
3875}
3876
3877/**
3878 * ice_aq_set_link_restart_an
3879 * @pi: pointer to the port information structure
3880 * @ena_link: if true: enable link, if false: disable link
3881 * @cd: pointer to command details structure or NULL
3882 *
3883 * Sets up the link and restarts the Auto-Negotiation over the link.
3884 */
3885int
3886ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,
3887 struct ice_sq_cd *cd)
3888{
3889 struct ice_aqc_restart_an *cmd;
3890 struct ice_aq_desc desc;
3891
3892 cmd = &desc.params.restart_an;
3893
3894 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an);
3895
3896 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART;
3897 cmd->lport_num = pi->lport;
3898 if (ena_link)
3899 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE;
3900 else
3901 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE;
3902
3903 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
3904}
3905
3906/**
3907 * ice_aq_set_event_mask
3908 * @hw: pointer to the HW struct
3909 * @port_num: port number of the physical function
3910 * @mask: event mask to be set
3911 * @cd: pointer to command details structure or NULL
3912 *
3913 * Set event mask (0x0613)
3914 */
3915int
3916ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask,
3917 struct ice_sq_cd *cd)
3918{
3919 struct ice_aqc_set_event_mask *cmd;
3920 struct ice_aq_desc desc;
3921
3922 cmd = &desc.params.set_event_mask;
3923
3924 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask);
3925
3926 cmd->lport_num = port_num;
3927
3928 cmd->event_mask = cpu_to_le16(mask);
3929 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
3930}
3931
3932/**
3933 * ice_aq_set_mac_loopback
3934 * @hw: pointer to the HW struct
3935 * @ena_lpbk: Enable or Disable loopback
3936 * @cd: pointer to command details structure or NULL
3937 *
3938 * Enable/disable loopback on a given port
3939 */
3940int
3941ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd)
3942{
3943 struct ice_aqc_set_mac_lb *cmd;
3944 struct ice_aq_desc desc;
3945
3946 cmd = &desc.params.set_mac_lb;
3947
3948 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb);
3949 if (ena_lpbk)
3950 cmd->lb_mode = ICE_AQ_MAC_LB_EN;
3951
3952 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
3953}
3954
3955/**
3956 * ice_aq_set_port_id_led
3957 * @pi: pointer to the port information
3958 * @is_orig_mode: is this LED set to original mode (by the net-list)
3959 * @cd: pointer to command details structure or NULL
3960 *
3961 * Set LED value for the given port (0x06e9)
3962 */
3963int
3964ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,
3965 struct ice_sq_cd *cd)
3966{
3967 struct ice_aqc_set_port_id_led *cmd;
3968 struct ice_hw *hw = pi->hw;
3969 struct ice_aq_desc desc;
3970
3971 cmd = &desc.params.set_port_id_led;
3972
3973 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led);
3974
3975 if (is_orig_mode)
3976 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG;
3977 else
3978 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK;
3979
3980 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
3981}
3982
3983/**
3984 * ice_aq_get_port_options
3985 * @hw: pointer to the HW struct
3986 * @options: buffer for the resultant port options
3987 * @option_count: input - size of the buffer in port options structures,
3988 * output - number of returned port options
3989 * @lport: logical port to call the command with (optional)
3990 * @lport_valid: when false, FW uses port owned by the PF instead of lport,
3991 * when PF owns more than 1 port it must be true
3992 * @active_option_idx: index of active port option in returned buffer
3993 * @active_option_valid: active option in returned buffer is valid
3994 * @pending_option_idx: index of pending port option in returned buffer
3995 * @pending_option_valid: pending option in returned buffer is valid
3996 *
3997 * Calls Get Port Options AQC (0x06ea) and verifies result.
3998 */
3999int
4000ice_aq_get_port_options(struct ice_hw *hw,
4001 struct ice_aqc_get_port_options_elem *options,
4002 u8 *option_count, u8 lport, bool lport_valid,
4003 u8 *active_option_idx, bool *active_option_valid,
4004 u8 *pending_option_idx, bool *pending_option_valid)
4005{
4006 struct ice_aqc_get_port_options *cmd;
4007 struct ice_aq_desc desc;
4008 int status;
4009 u8 i;
4010
4011 /* options buffer shall be able to hold max returned options */
4012 if (*option_count < ICE_AQC_PORT_OPT_COUNT_M)
4013 return -EINVAL;
4014
4015 cmd = &desc.params.get_port_options;
4016 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_port_options);
4017
4018 if (lport_valid)
4019 cmd->lport_num = lport;
4020 cmd->lport_num_valid = lport_valid;
4021
4022 status = ice_aq_send_cmd(hw, &desc, options,
4023 *option_count * sizeof(*options), NULL);
4024 if (status)
4025 return status;
4026
4027 /* verify direct FW response & set output parameters */
4028 *option_count = FIELD_GET(ICE_AQC_PORT_OPT_COUNT_M,
4029 cmd->port_options_count);
4030 ice_debug(hw, ICE_DBG_PHY, "options: %x\n", *option_count);
4031 *active_option_valid = FIELD_GET(ICE_AQC_PORT_OPT_VALID,
4032 cmd->port_options);
4033 if (*active_option_valid) {
4034 *active_option_idx = FIELD_GET(ICE_AQC_PORT_OPT_ACTIVE_M,
4035 cmd->port_options);
4036 if (*active_option_idx > (*option_count - 1))
4037 return -EIO;
4038 ice_debug(hw, ICE_DBG_PHY, "active idx: %x\n",
4039 *active_option_idx);
4040 }
4041
4042 *pending_option_valid = FIELD_GET(ICE_AQC_PENDING_PORT_OPT_VALID,
4043 cmd->pending_port_option_status);
4044 if (*pending_option_valid) {
4045 *pending_option_idx = FIELD_GET(ICE_AQC_PENDING_PORT_OPT_IDX_M,
4046 cmd->pending_port_option_status);
4047 if (*pending_option_idx > (*option_count - 1))
4048 return -EIO;
4049 ice_debug(hw, ICE_DBG_PHY, "pending idx: %x\n",
4050 *pending_option_idx);
4051 }
4052
4053 /* mask output options fields */
4054 for (i = 0; i < *option_count; i++) {
4055 options[i].pmd = FIELD_GET(ICE_AQC_PORT_OPT_PMD_COUNT_M,
4056 options[i].pmd);
4057 options[i].max_lane_speed = FIELD_GET(ICE_AQC_PORT_OPT_MAX_LANE_M,
4058 options[i].max_lane_speed);
4059 ice_debug(hw, ICE_DBG_PHY, "pmds: %x max speed: %x\n",
4060 options[i].pmd, options[i].max_lane_speed);
4061 }
4062
4063 return 0;
4064}
4065
4066/**
4067 * ice_aq_set_port_option
4068 * @hw: pointer to the HW struct
4069 * @lport: logical port to call the command with
4070 * @lport_valid: when false, FW uses port owned by the PF instead of lport,
4071 * when PF owns more than 1 port it must be true
4072 * @new_option: new port option to be written
4073 *
4074 * Calls Set Port Options AQC (0x06eb).
4075 */
4076int
4077ice_aq_set_port_option(struct ice_hw *hw, u8 lport, u8 lport_valid,
4078 u8 new_option)
4079{
4080 struct ice_aqc_set_port_option *cmd;
4081 struct ice_aq_desc desc;
4082
4083 if (new_option > ICE_AQC_PORT_OPT_COUNT_M)
4084 return -EINVAL;
4085
4086 cmd = &desc.params.set_port_option;
4087 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_option);
4088
4089 if (lport_valid)
4090 cmd->lport_num = lport;
4091
4092 cmd->lport_num_valid = lport_valid;
4093 cmd->selected_port_option = new_option;
4094
4095 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
4096}
4097
4098/**
4099 * ice_get_phy_lane_number - Get PHY lane number for current adapter
4100 * @hw: pointer to the hw struct
4101 *
4102 * Return: PHY lane number on success, negative error code otherwise.
4103 */
4104int ice_get_phy_lane_number(struct ice_hw *hw)
4105{
4106 struct ice_aqc_get_port_options_elem *options;
4107 unsigned int lport = 0;
4108 unsigned int lane;
4109 int err;
4110
4111 options = kcalloc(ICE_AQC_PORT_OPT_MAX, sizeof(*options), GFP_KERNEL);
4112 if (!options)
4113 return -ENOMEM;
4114
4115 for (lane = 0; lane < ICE_MAX_PORT_PER_PCI_DEV; lane++) {
4116 u8 options_count = ICE_AQC_PORT_OPT_MAX;
4117 u8 speed, active_idx, pending_idx;
4118 bool active_valid, pending_valid;
4119
4120 err = ice_aq_get_port_options(hw, options, &options_count, lane,
4121 true, &active_idx, &active_valid,
4122 &pending_idx, &pending_valid);
4123 if (err)
4124 goto err;
4125
4126 if (!active_valid)
4127 continue;
4128
4129 speed = options[active_idx].max_lane_speed;
4130 /* If we don't get speed for this lane, it's unoccupied */
4131 if (speed > ICE_AQC_PORT_OPT_MAX_LANE_200G)
4132 continue;
4133
4134 if (hw->pf_id == lport) {
4135 kfree(options);
4136 return lane;
4137 }
4138
4139 lport++;
4140 }
4141
4142 /* PHY lane not found */
4143 err = -ENXIO;
4144err:
4145 kfree(options);
4146 return err;
4147}
4148
4149/**
4150 * ice_aq_sff_eeprom
4151 * @hw: pointer to the HW struct
4152 * @lport: bits [7:0] = logical port, bit [8] = logical port valid
4153 * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default)
4154 * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding.
4155 * @page: QSFP page
4156 * @set_page: set or ignore the page
4157 * @data: pointer to data buffer to be read/written to the I2C device.
4158 * @length: 1-16 for read, 1 for write.
4159 * @write: 0 read, 1 for write.
4160 * @cd: pointer to command details structure or NULL
4161 *
4162 * Read/Write SFF EEPROM (0x06EE)
4163 */
4164int
4165ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr,
4166 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length,
4167 bool write, struct ice_sq_cd *cd)
4168{
4169 struct ice_aqc_sff_eeprom *cmd;
4170 struct ice_aq_desc desc;
4171 u16 i2c_bus_addr;
4172 int status;
4173
4174 if (!data || (mem_addr & 0xff00))
4175 return -EINVAL;
4176
4177 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom);
4178 cmd = &desc.params.read_write_sff_param;
4179 desc.flags = cpu_to_le16(ICE_AQ_FLAG_RD);
4180 cmd->lport_num = (u8)(lport & 0xff);
4181 cmd->lport_num_valid = (u8)((lport >> 8) & 0x01);
4182 i2c_bus_addr = FIELD_PREP(ICE_AQC_SFF_I2CBUS_7BIT_M, bus_addr >> 1) |
4183 FIELD_PREP(ICE_AQC_SFF_SET_EEPROM_PAGE_M, set_page);
4184 if (write)
4185 i2c_bus_addr |= ICE_AQC_SFF_IS_WRITE;
4186 cmd->i2c_bus_addr = cpu_to_le16(i2c_bus_addr);
4187 cmd->i2c_mem_addr = cpu_to_le16(mem_addr & 0xff);
4188 cmd->eeprom_page = le16_encode_bits(page, ICE_AQC_SFF_EEPROM_PAGE_M);
4189
4190 status = ice_aq_send_cmd(hw, &desc, data, length, cd);
4191 return status;
4192}
4193
4194static enum ice_lut_size ice_lut_type_to_size(enum ice_lut_type type)
4195{
4196 switch (type) {
4197 case ICE_LUT_VSI:
4198 return ICE_LUT_VSI_SIZE;
4199 case ICE_LUT_GLOBAL:
4200 return ICE_LUT_GLOBAL_SIZE;
4201 case ICE_LUT_PF:
4202 return ICE_LUT_PF_SIZE;
4203 }
4204 WARN_ONCE(1, "incorrect type passed");
4205 return ICE_LUT_VSI_SIZE;
4206}
4207
4208static enum ice_aqc_lut_flags ice_lut_size_to_flag(enum ice_lut_size size)
4209{
4210 switch (size) {
4211 case ICE_LUT_VSI_SIZE:
4212 return ICE_AQC_LUT_SIZE_SMALL;
4213 case ICE_LUT_GLOBAL_SIZE:
4214 return ICE_AQC_LUT_SIZE_512;
4215 case ICE_LUT_PF_SIZE:
4216 return ICE_AQC_LUT_SIZE_2K;
4217 }
4218 WARN_ONCE(1, "incorrect size passed");
4219 return 0;
4220}
4221
4222/**
4223 * __ice_aq_get_set_rss_lut
4224 * @hw: pointer to the hardware structure
4225 * @params: RSS LUT parameters
4226 * @set: set true to set the table, false to get the table
4227 *
4228 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table
4229 */
4230static int
4231__ice_aq_get_set_rss_lut(struct ice_hw *hw,
4232 struct ice_aq_get_set_rss_lut_params *params, bool set)
4233{
4234 u16 opcode, vsi_id, vsi_handle = params->vsi_handle, glob_lut_idx = 0;
4235 enum ice_lut_type lut_type = params->lut_type;
4236 struct ice_aqc_get_set_rss_lut *desc_params;
4237 enum ice_aqc_lut_flags flags;
4238 enum ice_lut_size lut_size;
4239 struct ice_aq_desc desc;
4240 u8 *lut = params->lut;
4241
4242
4243 if (!lut || !ice_is_vsi_valid(hw, vsi_handle))
4244 return -EINVAL;
4245
4246 lut_size = ice_lut_type_to_size(lut_type);
4247 if (lut_size > params->lut_size)
4248 return -EINVAL;
4249 else if (set && lut_size != params->lut_size)
4250 return -EINVAL;
4251
4252 opcode = set ? ice_aqc_opc_set_rss_lut : ice_aqc_opc_get_rss_lut;
4253 ice_fill_dflt_direct_cmd_desc(&desc, opcode);
4254 if (set)
4255 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
4256
4257 desc_params = &desc.params.get_set_rss_lut;
4258 vsi_id = ice_get_hw_vsi_num(hw, vsi_handle);
4259 desc_params->vsi_id = cpu_to_le16(vsi_id | ICE_AQC_RSS_VSI_VALID);
4260
4261 if (lut_type == ICE_LUT_GLOBAL)
4262 glob_lut_idx = FIELD_PREP(ICE_AQC_LUT_GLOBAL_IDX,
4263 params->global_lut_id);
4264
4265 flags = lut_type | glob_lut_idx | ice_lut_size_to_flag(lut_size);
4266 desc_params->flags = cpu_to_le16(flags);
4267
4268 return ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL);
4269}
4270
4271/**
4272 * ice_aq_get_rss_lut
4273 * @hw: pointer to the hardware structure
4274 * @get_params: RSS LUT parameters used to specify which RSS LUT to get
4275 *
4276 * get the RSS lookup table, PF or VSI type
4277 */
4278int
4279ice_aq_get_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *get_params)
4280{
4281 return __ice_aq_get_set_rss_lut(hw, get_params, false);
4282}
4283
4284/**
4285 * ice_aq_set_rss_lut
4286 * @hw: pointer to the hardware structure
4287 * @set_params: RSS LUT parameters used to specify how to set the RSS LUT
4288 *
4289 * set the RSS lookup table, PF or VSI type
4290 */
4291int
4292ice_aq_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *set_params)
4293{
4294 return __ice_aq_get_set_rss_lut(hw, set_params, true);
4295}
4296
4297/**
4298 * __ice_aq_get_set_rss_key
4299 * @hw: pointer to the HW struct
4300 * @vsi_id: VSI FW index
4301 * @key: pointer to key info struct
4302 * @set: set true to set the key, false to get the key
4303 *
4304 * get (0x0B04) or set (0x0B02) the RSS key per VSI
4305 */
4306static int
4307__ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id,
4308 struct ice_aqc_get_set_rss_keys *key, bool set)
4309{
4310 struct ice_aqc_get_set_rss_key *desc_params;
4311 u16 key_size = sizeof(*key);
4312 struct ice_aq_desc desc;
4313
4314 if (set) {
4315 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key);
4316 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
4317 } else {
4318 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key);
4319 }
4320
4321 desc_params = &desc.params.get_set_rss_key;
4322 desc_params->vsi_id = cpu_to_le16(vsi_id | ICE_AQC_RSS_VSI_VALID);
4323
4324 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL);
4325}
4326
4327/**
4328 * ice_aq_get_rss_key
4329 * @hw: pointer to the HW struct
4330 * @vsi_handle: software VSI handle
4331 * @key: pointer to key info struct
4332 *
4333 * get the RSS key per VSI
4334 */
4335int
4336ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle,
4337 struct ice_aqc_get_set_rss_keys *key)
4338{
4339 if (!ice_is_vsi_valid(hw, vsi_handle) || !key)
4340 return -EINVAL;
4341
4342 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
4343 key, false);
4344}
4345
4346/**
4347 * ice_aq_set_rss_key
4348 * @hw: pointer to the HW struct
4349 * @vsi_handle: software VSI handle
4350 * @keys: pointer to key info struct
4351 *
4352 * set the RSS key per VSI
4353 */
4354int
4355ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle,
4356 struct ice_aqc_get_set_rss_keys *keys)
4357{
4358 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys)
4359 return -EINVAL;
4360
4361 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
4362 keys, true);
4363}
4364
4365/**
4366 * ice_aq_add_lan_txq
4367 * @hw: pointer to the hardware structure
4368 * @num_qgrps: Number of added queue groups
4369 * @qg_list: list of queue groups to be added
4370 * @buf_size: size of buffer for indirect command
4371 * @cd: pointer to command details structure or NULL
4372 *
4373 * Add Tx LAN queue (0x0C30)
4374 *
4375 * NOTE:
4376 * Prior to calling add Tx LAN queue:
4377 * Initialize the following as part of the Tx queue context:
4378 * Completion queue ID if the queue uses Completion queue, Quanta profile,
4379 * Cache profile and Packet shaper profile.
4380 *
4381 * After add Tx LAN queue AQ command is completed:
4382 * Interrupts should be associated with specific queues,
4383 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue
4384 * flow.
4385 */
4386static int
4387ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps,
4388 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size,
4389 struct ice_sq_cd *cd)
4390{
4391 struct ice_aqc_add_tx_qgrp *list;
4392 struct ice_aqc_add_txqs *cmd;
4393 struct ice_aq_desc desc;
4394 u16 i, sum_size = 0;
4395
4396 cmd = &desc.params.add_txqs;
4397
4398 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs);
4399
4400 if (!qg_list)
4401 return -EINVAL;
4402
4403 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
4404 return -EINVAL;
4405
4406 for (i = 0, list = qg_list; i < num_qgrps; i++) {
4407 sum_size += struct_size(list, txqs, list->num_txqs);
4408 list = (struct ice_aqc_add_tx_qgrp *)(list->txqs +
4409 list->num_txqs);
4410 }
4411
4412 if (buf_size != sum_size)
4413 return -EINVAL;
4414
4415 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
4416
4417 cmd->num_qgrps = num_qgrps;
4418
4419 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
4420}
4421
4422/**
4423 * ice_aq_dis_lan_txq
4424 * @hw: pointer to the hardware structure
4425 * @num_qgrps: number of groups in the list
4426 * @qg_list: the list of groups to disable
4427 * @buf_size: the total size of the qg_list buffer in bytes
4428 * @rst_src: if called due to reset, specifies the reset source
4429 * @vmvf_num: the relative VM or VF number that is undergoing the reset
4430 * @cd: pointer to command details structure or NULL
4431 *
4432 * Disable LAN Tx queue (0x0C31)
4433 */
4434static int
4435ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps,
4436 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size,
4437 enum ice_disq_rst_src rst_src, u16 vmvf_num,
4438 struct ice_sq_cd *cd)
4439{
4440 struct ice_aqc_dis_txq_item *item;
4441 struct ice_aqc_dis_txqs *cmd;
4442 struct ice_aq_desc desc;
4443 u16 vmvf_and_timeout;
4444 u16 i, sz = 0;
4445 int status;
4446
4447 cmd = &desc.params.dis_txqs;
4448 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs);
4449
4450 /* qg_list can be NULL only in VM/VF reset flow */
4451 if (!qg_list && !rst_src)
4452 return -EINVAL;
4453
4454 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
4455 return -EINVAL;
4456
4457 cmd->num_entries = num_qgrps;
4458
4459 vmvf_and_timeout = FIELD_PREP(ICE_AQC_Q_DIS_TIMEOUT_M, 5);
4460
4461 switch (rst_src) {
4462 case ICE_VM_RESET:
4463 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET;
4464 vmvf_and_timeout |= vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M;
4465 break;
4466 case ICE_VF_RESET:
4467 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VF_RESET;
4468 /* In this case, FW expects vmvf_num to be absolute VF ID */
4469 vmvf_and_timeout |= (vmvf_num + hw->func_caps.vf_base_id) &
4470 ICE_AQC_Q_DIS_VMVF_NUM_M;
4471 break;
4472 case ICE_NO_RESET:
4473 default:
4474 break;
4475 }
4476
4477 cmd->vmvf_and_timeout = cpu_to_le16(vmvf_and_timeout);
4478
4479 /* flush pipe on time out */
4480 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE;
4481 /* If no queue group info, we are in a reset flow. Issue the AQ */
4482 if (!qg_list)
4483 goto do_aq;
4484
4485 /* set RD bit to indicate that command buffer is provided by the driver
4486 * and it needs to be read by the firmware
4487 */
4488 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
4489
4490 for (i = 0, item = qg_list; i < num_qgrps; i++) {
4491 u16 item_size = struct_size(item, q_id, item->num_qs);
4492
4493 /* If the num of queues is even, add 2 bytes of padding */
4494 if ((item->num_qs % 2) == 0)
4495 item_size += 2;
4496
4497 sz += item_size;
4498
4499 item = (struct ice_aqc_dis_txq_item *)((u8 *)item + item_size);
4500 }
4501
4502 if (buf_size != sz)
4503 return -EINVAL;
4504
4505do_aq:
4506 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
4507 if (status) {
4508 if (!qg_list)
4509 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n",
4510 vmvf_num, hw->adminq.sq_last_status);
4511 else
4512 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n",
4513 le16_to_cpu(qg_list[0].q_id[0]),
4514 hw->adminq.sq_last_status);
4515 }
4516 return status;
4517}
4518
4519/**
4520 * ice_aq_cfg_lan_txq
4521 * @hw: pointer to the hardware structure
4522 * @buf: buffer for command
4523 * @buf_size: size of buffer in bytes
4524 * @num_qs: number of queues being configured
4525 * @oldport: origination lport
4526 * @newport: destination lport
4527 * @cd: pointer to command details structure or NULL
4528 *
4529 * Move/Configure LAN Tx queue (0x0C32)
4530 *
4531 * There is a better AQ command to use for moving nodes, so only coding
4532 * this one for configuring the node.
4533 */
4534int
4535ice_aq_cfg_lan_txq(struct ice_hw *hw, struct ice_aqc_cfg_txqs_buf *buf,
4536 u16 buf_size, u16 num_qs, u8 oldport, u8 newport,
4537 struct ice_sq_cd *cd)
4538{
4539 struct ice_aqc_cfg_txqs *cmd;
4540 struct ice_aq_desc desc;
4541 int status;
4542
4543 cmd = &desc.params.cfg_txqs;
4544 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_cfg_txqs);
4545 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
4546
4547 if (!buf)
4548 return -EINVAL;
4549
4550 cmd->cmd_type = ICE_AQC_Q_CFG_TC_CHNG;
4551 cmd->num_qs = num_qs;
4552 cmd->port_num_chng = (oldport & ICE_AQC_Q_CFG_SRC_PRT_M);
4553 cmd->port_num_chng |= FIELD_PREP(ICE_AQC_Q_CFG_DST_PRT_M, newport);
4554 cmd->time_out = FIELD_PREP(ICE_AQC_Q_CFG_TIMEOUT_M, 5);
4555 cmd->blocked_cgds = 0;
4556
4557 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
4558 if (status)
4559 ice_debug(hw, ICE_DBG_SCHED, "Failed to reconfigure nodes %d\n",
4560 hw->adminq.sq_last_status);
4561 return status;
4562}
4563
4564/**
4565 * ice_aq_add_rdma_qsets
4566 * @hw: pointer to the hardware structure
4567 * @num_qset_grps: Number of RDMA Qset groups
4568 * @qset_list: list of Qset groups to be added
4569 * @buf_size: size of buffer for indirect command
4570 * @cd: pointer to command details structure or NULL
4571 *
4572 * Add Tx RDMA Qsets (0x0C33)
4573 */
4574static int
4575ice_aq_add_rdma_qsets(struct ice_hw *hw, u8 num_qset_grps,
4576 struct ice_aqc_add_rdma_qset_data *qset_list,
4577 u16 buf_size, struct ice_sq_cd *cd)
4578{
4579 struct ice_aqc_add_rdma_qset_data *list;
4580 struct ice_aqc_add_rdma_qset *cmd;
4581 struct ice_aq_desc desc;
4582 u16 i, sum_size = 0;
4583
4584 cmd = &desc.params.add_rdma_qset;
4585
4586 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_rdma_qset);
4587
4588 if (num_qset_grps > ICE_LAN_TXQ_MAX_QGRPS)
4589 return -EINVAL;
4590
4591 for (i = 0, list = qset_list; i < num_qset_grps; i++) {
4592 u16 num_qsets = le16_to_cpu(list->num_qsets);
4593
4594 sum_size += struct_size(list, rdma_qsets, num_qsets);
4595 list = (struct ice_aqc_add_rdma_qset_data *)(list->rdma_qsets +
4596 num_qsets);
4597 }
4598
4599 if (buf_size != sum_size)
4600 return -EINVAL;
4601
4602 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
4603
4604 cmd->num_qset_grps = num_qset_grps;
4605
4606 return ice_aq_send_cmd(hw, &desc, qset_list, buf_size, cd);
4607}
4608
4609/* End of FW Admin Queue command wrappers */
4610
4611/**
4612 * ice_pack_ctx_byte - write a byte to a packed context structure
4613 * @src_ctx: unpacked source context structure
4614 * @dest_ctx: packed destination context data
4615 * @ce_info: context element description
4616 */
4617static void ice_pack_ctx_byte(u8 *src_ctx, u8 *dest_ctx,
4618 const struct ice_ctx_ele *ce_info)
4619{
4620 u8 src_byte, dest_byte, mask;
4621 u8 *from, *dest;
4622 u16 shift_width;
4623
4624 /* copy from the next struct field */
4625 from = src_ctx + ce_info->offset;
4626
4627 /* prepare the bits and mask */
4628 shift_width = ce_info->lsb % 8;
4629 mask = GENMASK(ce_info->width - 1 + shift_width, shift_width);
4630
4631 src_byte = *from;
4632 src_byte <<= shift_width;
4633 src_byte &= mask;
4634
4635 /* get the current bits from the target bit string */
4636 dest = dest_ctx + (ce_info->lsb / 8);
4637
4638 memcpy(&dest_byte, dest, sizeof(dest_byte));
4639
4640 dest_byte &= ~mask; /* get the bits not changing */
4641 dest_byte |= src_byte; /* add in the new bits */
4642
4643 /* put it all back */
4644 memcpy(dest, &dest_byte, sizeof(dest_byte));
4645}
4646
4647/**
4648 * ice_pack_ctx_word - write a word to a packed context structure
4649 * @src_ctx: unpacked source context structure
4650 * @dest_ctx: packed destination context data
4651 * @ce_info: context element description
4652 */
4653static void ice_pack_ctx_word(u8 *src_ctx, u8 *dest_ctx,
4654 const struct ice_ctx_ele *ce_info)
4655{
4656 u16 src_word, mask;
4657 __le16 dest_word;
4658 u8 *from, *dest;
4659 u16 shift_width;
4660
4661 /* copy from the next struct field */
4662 from = src_ctx + ce_info->offset;
4663
4664 /* prepare the bits and mask */
4665 shift_width = ce_info->lsb % 8;
4666 mask = GENMASK(ce_info->width - 1 + shift_width, shift_width);
4667
4668 /* don't swizzle the bits until after the mask because the mask bits
4669 * will be in a different bit position on big endian machines
4670 */
4671 src_word = *(u16 *)from;
4672 src_word <<= shift_width;
4673 src_word &= mask;
4674
4675 /* get the current bits from the target bit string */
4676 dest = dest_ctx + (ce_info->lsb / 8);
4677
4678 memcpy(&dest_word, dest, sizeof(dest_word));
4679
4680 dest_word &= ~(cpu_to_le16(mask)); /* get the bits not changing */
4681 dest_word |= cpu_to_le16(src_word); /* add in the new bits */
4682
4683 /* put it all back */
4684 memcpy(dest, &dest_word, sizeof(dest_word));
4685}
4686
4687/**
4688 * ice_pack_ctx_dword - write a dword to a packed context structure
4689 * @src_ctx: unpacked source context structure
4690 * @dest_ctx: packed destination context data
4691 * @ce_info: context element description
4692 */
4693static void ice_pack_ctx_dword(u8 *src_ctx, u8 *dest_ctx,
4694 const struct ice_ctx_ele *ce_info)
4695{
4696 u32 src_dword, mask;
4697 __le32 dest_dword;
4698 u8 *from, *dest;
4699 u16 shift_width;
4700
4701 /* copy from the next struct field */
4702 from = src_ctx + ce_info->offset;
4703
4704 /* prepare the bits and mask */
4705 shift_width = ce_info->lsb % 8;
4706 mask = GENMASK(ce_info->width - 1 + shift_width, shift_width);
4707
4708 /* don't swizzle the bits until after the mask because the mask bits
4709 * will be in a different bit position on big endian machines
4710 */
4711 src_dword = *(u32 *)from;
4712 src_dword <<= shift_width;
4713 src_dword &= mask;
4714
4715 /* get the current bits from the target bit string */
4716 dest = dest_ctx + (ce_info->lsb / 8);
4717
4718 memcpy(&dest_dword, dest, sizeof(dest_dword));
4719
4720 dest_dword &= ~(cpu_to_le32(mask)); /* get the bits not changing */
4721 dest_dword |= cpu_to_le32(src_dword); /* add in the new bits */
4722
4723 /* put it all back */
4724 memcpy(dest, &dest_dword, sizeof(dest_dword));
4725}
4726
4727/**
4728 * ice_pack_ctx_qword - write a qword to a packed context structure
4729 * @src_ctx: unpacked source context structure
4730 * @dest_ctx: packed destination context data
4731 * @ce_info: context element description
4732 */
4733static void ice_pack_ctx_qword(u8 *src_ctx, u8 *dest_ctx,
4734 const struct ice_ctx_ele *ce_info)
4735{
4736 u64 src_qword, mask;
4737 __le64 dest_qword;
4738 u8 *from, *dest;
4739 u16 shift_width;
4740
4741 /* copy from the next struct field */
4742 from = src_ctx + ce_info->offset;
4743
4744 /* prepare the bits and mask */
4745 shift_width = ce_info->lsb % 8;
4746 mask = GENMASK_ULL(ce_info->width - 1 + shift_width, shift_width);
4747
4748 /* don't swizzle the bits until after the mask because the mask bits
4749 * will be in a different bit position on big endian machines
4750 */
4751 src_qword = *(u64 *)from;
4752 src_qword <<= shift_width;
4753 src_qword &= mask;
4754
4755 /* get the current bits from the target bit string */
4756 dest = dest_ctx + (ce_info->lsb / 8);
4757
4758 memcpy(&dest_qword, dest, sizeof(dest_qword));
4759
4760 dest_qword &= ~(cpu_to_le64(mask)); /* get the bits not changing */
4761 dest_qword |= cpu_to_le64(src_qword); /* add in the new bits */
4762
4763 /* put it all back */
4764 memcpy(dest, &dest_qword, sizeof(dest_qword));
4765}
4766
4767/**
4768 * ice_set_ctx - set context bits in packed structure
4769 * @hw: pointer to the hardware structure
4770 * @src_ctx: pointer to a generic non-packed context structure
4771 * @dest_ctx: pointer to memory for the packed structure
4772 * @ce_info: List of Rx context elements
4773 */
4774int ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx,
4775 const struct ice_ctx_ele *ce_info)
4776{
4777 int f;
4778
4779 for (f = 0; ce_info[f].width; f++) {
4780 /* We have to deal with each element of the FW response
4781 * using the correct size so that we are correct regardless
4782 * of the endianness of the machine.
4783 */
4784 if (ce_info[f].width > (ce_info[f].size_of * BITS_PER_BYTE)) {
4785 ice_debug(hw, ICE_DBG_QCTX, "Field %d width of %d bits larger than size of %d byte(s) ... skipping write\n",
4786 f, ce_info[f].width, ce_info[f].size_of);
4787 continue;
4788 }
4789 switch (ce_info[f].size_of) {
4790 case sizeof(u8):
4791 ice_pack_ctx_byte(src_ctx, dest_ctx, &ce_info[f]);
4792 break;
4793 case sizeof(u16):
4794 ice_pack_ctx_word(src_ctx, dest_ctx, &ce_info[f]);
4795 break;
4796 case sizeof(u32):
4797 ice_pack_ctx_dword(src_ctx, dest_ctx, &ce_info[f]);
4798 break;
4799 case sizeof(u64):
4800 ice_pack_ctx_qword(src_ctx, dest_ctx, &ce_info[f]);
4801 break;
4802 default:
4803 return -EINVAL;
4804 }
4805 }
4806
4807 return 0;
4808}
4809
4810/**
4811 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC
4812 * @hw: pointer to the HW struct
4813 * @vsi_handle: software VSI handle
4814 * @tc: TC number
4815 * @q_handle: software queue handle
4816 */
4817struct ice_q_ctx *
4818ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle)
4819{
4820 struct ice_vsi_ctx *vsi;
4821 struct ice_q_ctx *q_ctx;
4822
4823 vsi = ice_get_vsi_ctx(hw, vsi_handle);
4824 if (!vsi)
4825 return NULL;
4826 if (q_handle >= vsi->num_lan_q_entries[tc])
4827 return NULL;
4828 if (!vsi->lan_q_ctx[tc])
4829 return NULL;
4830 q_ctx = vsi->lan_q_ctx[tc];
4831 return &q_ctx[q_handle];
4832}
4833
4834/**
4835 * ice_ena_vsi_txq
4836 * @pi: port information structure
4837 * @vsi_handle: software VSI handle
4838 * @tc: TC number
4839 * @q_handle: software queue handle
4840 * @num_qgrps: Number of added queue groups
4841 * @buf: list of queue groups to be added
4842 * @buf_size: size of buffer for indirect command
4843 * @cd: pointer to command details structure or NULL
4844 *
4845 * This function adds one LAN queue
4846 */
4847int
4848ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle,
4849 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size,
4850 struct ice_sq_cd *cd)
4851{
4852 struct ice_aqc_txsched_elem_data node = { 0 };
4853 struct ice_sched_node *parent;
4854 struct ice_q_ctx *q_ctx;
4855 struct ice_hw *hw;
4856 int status;
4857
4858 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
4859 return -EIO;
4860
4861 if (num_qgrps > 1 || buf->num_txqs > 1)
4862 return -ENOSPC;
4863
4864 hw = pi->hw;
4865
4866 if (!ice_is_vsi_valid(hw, vsi_handle))
4867 return -EINVAL;
4868
4869 mutex_lock(&pi->sched_lock);
4870
4871 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle);
4872 if (!q_ctx) {
4873 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n",
4874 q_handle);
4875 status = -EINVAL;
4876 goto ena_txq_exit;
4877 }
4878
4879 /* find a parent node */
4880 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc,
4881 ICE_SCHED_NODE_OWNER_LAN);
4882 if (!parent) {
4883 status = -EINVAL;
4884 goto ena_txq_exit;
4885 }
4886
4887 buf->parent_teid = parent->info.node_teid;
4888 node.parent_teid = parent->info.node_teid;
4889 /* Mark that the values in the "generic" section as valid. The default
4890 * value in the "generic" section is zero. This means that :
4891 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0.
4892 * - 0 priority among siblings, indicated by Bit 1-3.
4893 * - WFQ, indicated by Bit 4.
4894 * - 0 Adjustment value is used in PSM credit update flow, indicated by
4895 * Bit 5-6.
4896 * - Bit 7 is reserved.
4897 * Without setting the generic section as valid in valid_sections, the
4898 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL.
4899 */
4900 buf->txqs[0].info.valid_sections =
4901 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR |
4902 ICE_AQC_ELEM_VALID_EIR;
4903 buf->txqs[0].info.generic = 0;
4904 buf->txqs[0].info.cir_bw.bw_profile_idx =
4905 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID);
4906 buf->txqs[0].info.cir_bw.bw_alloc =
4907 cpu_to_le16(ICE_SCHED_DFLT_BW_WT);
4908 buf->txqs[0].info.eir_bw.bw_profile_idx =
4909 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID);
4910 buf->txqs[0].info.eir_bw.bw_alloc =
4911 cpu_to_le16(ICE_SCHED_DFLT_BW_WT);
4912
4913 /* add the LAN queue */
4914 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd);
4915 if (status) {
4916 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n",
4917 le16_to_cpu(buf->txqs[0].txq_id),
4918 hw->adminq.sq_last_status);
4919 goto ena_txq_exit;
4920 }
4921
4922 node.node_teid = buf->txqs[0].q_teid;
4923 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF;
4924 q_ctx->q_handle = q_handle;
4925 q_ctx->q_teid = le32_to_cpu(node.node_teid);
4926
4927 /* add a leaf node into scheduler tree queue layer */
4928 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node, NULL);
4929 if (!status)
4930 status = ice_sched_replay_q_bw(pi, q_ctx);
4931
4932ena_txq_exit:
4933 mutex_unlock(&pi->sched_lock);
4934 return status;
4935}
4936
4937/**
4938 * ice_dis_vsi_txq
4939 * @pi: port information structure
4940 * @vsi_handle: software VSI handle
4941 * @tc: TC number
4942 * @num_queues: number of queues
4943 * @q_handles: pointer to software queue handle array
4944 * @q_ids: pointer to the q_id array
4945 * @q_teids: pointer to queue node teids
4946 * @rst_src: if called due to reset, specifies the reset source
4947 * @vmvf_num: the relative VM or VF number that is undergoing the reset
4948 * @cd: pointer to command details structure or NULL
4949 *
4950 * This function removes queues and their corresponding nodes in SW DB
4951 */
4952int
4953ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues,
4954 u16 *q_handles, u16 *q_ids, u32 *q_teids,
4955 enum ice_disq_rst_src rst_src, u16 vmvf_num,
4956 struct ice_sq_cd *cd)
4957{
4958 DEFINE_RAW_FLEX(struct ice_aqc_dis_txq_item, qg_list, q_id, 1);
4959 u16 i, buf_size = __struct_size(qg_list);
4960 struct ice_q_ctx *q_ctx;
4961 int status = -ENOENT;
4962 struct ice_hw *hw;
4963
4964 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
4965 return -EIO;
4966
4967 hw = pi->hw;
4968
4969 if (!num_queues) {
4970 /* if queue is disabled already yet the disable queue command
4971 * has to be sent to complete the VF reset, then call
4972 * ice_aq_dis_lan_txq without any queue information
4973 */
4974 if (rst_src)
4975 return ice_aq_dis_lan_txq(hw, 0, NULL, 0, rst_src,
4976 vmvf_num, NULL);
4977 return -EIO;
4978 }
4979
4980 mutex_lock(&pi->sched_lock);
4981
4982 for (i = 0; i < num_queues; i++) {
4983 struct ice_sched_node *node;
4984
4985 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]);
4986 if (!node)
4987 continue;
4988 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handles[i]);
4989 if (!q_ctx) {
4990 ice_debug(hw, ICE_DBG_SCHED, "invalid queue handle%d\n",
4991 q_handles[i]);
4992 continue;
4993 }
4994 if (q_ctx->q_handle != q_handles[i]) {
4995 ice_debug(hw, ICE_DBG_SCHED, "Err:handles %d %d\n",
4996 q_ctx->q_handle, q_handles[i]);
4997 continue;
4998 }
4999 qg_list->parent_teid = node->info.parent_teid;
5000 qg_list->num_qs = 1;
5001 qg_list->q_id[0] = cpu_to_le16(q_ids[i]);
5002 status = ice_aq_dis_lan_txq(hw, 1, qg_list, buf_size, rst_src,
5003 vmvf_num, cd);
5004
5005 if (status)
5006 break;
5007 ice_free_sched_node(pi, node);
5008 q_ctx->q_handle = ICE_INVAL_Q_HANDLE;
5009 q_ctx->q_teid = ICE_INVAL_TEID;
5010 }
5011 mutex_unlock(&pi->sched_lock);
5012 return status;
5013}
5014
5015/**
5016 * ice_cfg_vsi_qs - configure the new/existing VSI queues
5017 * @pi: port information structure
5018 * @vsi_handle: software VSI handle
5019 * @tc_bitmap: TC bitmap
5020 * @maxqs: max queues array per TC
5021 * @owner: LAN or RDMA
5022 *
5023 * This function adds/updates the VSI queues per TC.
5024 */
5025static int
5026ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,
5027 u16 *maxqs, u8 owner)
5028{
5029 int status = 0;
5030 u8 i;
5031
5032 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
5033 return -EIO;
5034
5035 if (!ice_is_vsi_valid(pi->hw, vsi_handle))
5036 return -EINVAL;
5037
5038 mutex_lock(&pi->sched_lock);
5039
5040 ice_for_each_traffic_class(i) {
5041 /* configuration is possible only if TC node is present */
5042 if (!ice_sched_get_tc_node(pi, i))
5043 continue;
5044
5045 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner,
5046 ice_is_tc_ena(tc_bitmap, i));
5047 if (status)
5048 break;
5049 }
5050
5051 mutex_unlock(&pi->sched_lock);
5052 return status;
5053}
5054
5055/**
5056 * ice_cfg_vsi_lan - configure VSI LAN queues
5057 * @pi: port information structure
5058 * @vsi_handle: software VSI handle
5059 * @tc_bitmap: TC bitmap
5060 * @max_lanqs: max LAN queues array per TC
5061 *
5062 * This function adds/updates the VSI LAN queues per TC.
5063 */
5064int
5065ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,
5066 u16 *max_lanqs)
5067{
5068 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs,
5069 ICE_SCHED_NODE_OWNER_LAN);
5070}
5071
5072/**
5073 * ice_cfg_vsi_rdma - configure the VSI RDMA queues
5074 * @pi: port information structure
5075 * @vsi_handle: software VSI handle
5076 * @tc_bitmap: TC bitmap
5077 * @max_rdmaqs: max RDMA queues array per TC
5078 *
5079 * This function adds/updates the VSI RDMA queues per TC.
5080 */
5081int
5082ice_cfg_vsi_rdma(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap,
5083 u16 *max_rdmaqs)
5084{
5085 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_rdmaqs,
5086 ICE_SCHED_NODE_OWNER_RDMA);
5087}
5088
5089/**
5090 * ice_ena_vsi_rdma_qset
5091 * @pi: port information structure
5092 * @vsi_handle: software VSI handle
5093 * @tc: TC number
5094 * @rdma_qset: pointer to RDMA Qset
5095 * @num_qsets: number of RDMA Qsets
5096 * @qset_teid: pointer to Qset node TEIDs
5097 *
5098 * This function adds RDMA Qset
5099 */
5100int
5101ice_ena_vsi_rdma_qset(struct ice_port_info *pi, u16 vsi_handle, u8 tc,
5102 u16 *rdma_qset, u16 num_qsets, u32 *qset_teid)
5103{
5104 struct ice_aqc_txsched_elem_data node = { 0 };
5105 struct ice_aqc_add_rdma_qset_data *buf;
5106 struct ice_sched_node *parent;
5107 struct ice_hw *hw;
5108 u16 i, buf_size;
5109 int ret;
5110
5111 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
5112 return -EIO;
5113 hw = pi->hw;
5114
5115 if (!ice_is_vsi_valid(hw, vsi_handle))
5116 return -EINVAL;
5117
5118 buf_size = struct_size(buf, rdma_qsets, num_qsets);
5119 buf = kzalloc(buf_size, GFP_KERNEL);
5120 if (!buf)
5121 return -ENOMEM;
5122 mutex_lock(&pi->sched_lock);
5123
5124 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc,
5125 ICE_SCHED_NODE_OWNER_RDMA);
5126 if (!parent) {
5127 ret = -EINVAL;
5128 goto rdma_error_exit;
5129 }
5130 buf->parent_teid = parent->info.node_teid;
5131 node.parent_teid = parent->info.node_teid;
5132
5133 buf->num_qsets = cpu_to_le16(num_qsets);
5134 for (i = 0; i < num_qsets; i++) {
5135 buf->rdma_qsets[i].tx_qset_id = cpu_to_le16(rdma_qset[i]);
5136 buf->rdma_qsets[i].info.valid_sections =
5137 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR |
5138 ICE_AQC_ELEM_VALID_EIR;
5139 buf->rdma_qsets[i].info.generic = 0;
5140 buf->rdma_qsets[i].info.cir_bw.bw_profile_idx =
5141 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID);
5142 buf->rdma_qsets[i].info.cir_bw.bw_alloc =
5143 cpu_to_le16(ICE_SCHED_DFLT_BW_WT);
5144 buf->rdma_qsets[i].info.eir_bw.bw_profile_idx =
5145 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID);
5146 buf->rdma_qsets[i].info.eir_bw.bw_alloc =
5147 cpu_to_le16(ICE_SCHED_DFLT_BW_WT);
5148 }
5149 ret = ice_aq_add_rdma_qsets(hw, 1, buf, buf_size, NULL);
5150 if (ret) {
5151 ice_debug(hw, ICE_DBG_RDMA, "add RDMA qset failed\n");
5152 goto rdma_error_exit;
5153 }
5154 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF;
5155 for (i = 0; i < num_qsets; i++) {
5156 node.node_teid = buf->rdma_qsets[i].qset_teid;
5157 ret = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1,
5158 &node, NULL);
5159 if (ret)
5160 break;
5161 qset_teid[i] = le32_to_cpu(node.node_teid);
5162 }
5163rdma_error_exit:
5164 mutex_unlock(&pi->sched_lock);
5165 kfree(buf);
5166 return ret;
5167}
5168
5169/**
5170 * ice_dis_vsi_rdma_qset - free RDMA resources
5171 * @pi: port_info struct
5172 * @count: number of RDMA Qsets to free
5173 * @qset_teid: TEID of Qset node
5174 * @q_id: list of queue IDs being disabled
5175 */
5176int
5177ice_dis_vsi_rdma_qset(struct ice_port_info *pi, u16 count, u32 *qset_teid,
5178 u16 *q_id)
5179{
5180 DEFINE_RAW_FLEX(struct ice_aqc_dis_txq_item, qg_list, q_id, 1);
5181 u16 qg_size = __struct_size(qg_list);
5182 struct ice_hw *hw;
5183 int status = 0;
5184 int i;
5185
5186 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
5187 return -EIO;
5188
5189 hw = pi->hw;
5190
5191 mutex_lock(&pi->sched_lock);
5192
5193 for (i = 0; i < count; i++) {
5194 struct ice_sched_node *node;
5195
5196 node = ice_sched_find_node_by_teid(pi->root, qset_teid[i]);
5197 if (!node)
5198 continue;
5199
5200 qg_list->parent_teid = node->info.parent_teid;
5201 qg_list->num_qs = 1;
5202 qg_list->q_id[0] =
5203 cpu_to_le16(q_id[i] |
5204 ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET);
5205
5206 status = ice_aq_dis_lan_txq(hw, 1, qg_list, qg_size,
5207 ICE_NO_RESET, 0, NULL);
5208 if (status)
5209 break;
5210
5211 ice_free_sched_node(pi, node);
5212 }
5213
5214 mutex_unlock(&pi->sched_lock);
5215 return status;
5216}
5217
5218/**
5219 * ice_aq_get_cgu_abilities - get cgu abilities
5220 * @hw: pointer to the HW struct
5221 * @abilities: CGU abilities
5222 *
5223 * Get CGU abilities (0x0C61)
5224 * Return: 0 on success or negative value on failure.
5225 */
5226int
5227ice_aq_get_cgu_abilities(struct ice_hw *hw,
5228 struct ice_aqc_get_cgu_abilities *abilities)
5229{
5230 struct ice_aq_desc desc;
5231
5232 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_abilities);
5233 return ice_aq_send_cmd(hw, &desc, abilities, sizeof(*abilities), NULL);
5234}
5235
5236/**
5237 * ice_aq_set_input_pin_cfg - set input pin config
5238 * @hw: pointer to the HW struct
5239 * @input_idx: Input index
5240 * @flags1: Input flags
5241 * @flags2: Input flags
5242 * @freq: Frequency in Hz
5243 * @phase_delay: Delay in ps
5244 *
5245 * Set CGU input config (0x0C62)
5246 * Return: 0 on success or negative value on failure.
5247 */
5248int
5249ice_aq_set_input_pin_cfg(struct ice_hw *hw, u8 input_idx, u8 flags1, u8 flags2,
5250 u32 freq, s32 phase_delay)
5251{
5252 struct ice_aqc_set_cgu_input_config *cmd;
5253 struct ice_aq_desc desc;
5254
5255 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_input_config);
5256 cmd = &desc.params.set_cgu_input_config;
5257 cmd->input_idx = input_idx;
5258 cmd->flags1 = flags1;
5259 cmd->flags2 = flags2;
5260 cmd->freq = cpu_to_le32(freq);
5261 cmd->phase_delay = cpu_to_le32(phase_delay);
5262
5263 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
5264}
5265
5266/**
5267 * ice_aq_get_input_pin_cfg - get input pin config
5268 * @hw: pointer to the HW struct
5269 * @input_idx: Input index
5270 * @status: Pin status
5271 * @type: Pin type
5272 * @flags1: Input flags
5273 * @flags2: Input flags
5274 * @freq: Frequency in Hz
5275 * @phase_delay: Delay in ps
5276 *
5277 * Get CGU input config (0x0C63)
5278 * Return: 0 on success or negative value on failure.
5279 */
5280int
5281ice_aq_get_input_pin_cfg(struct ice_hw *hw, u8 input_idx, u8 *status, u8 *type,
5282 u8 *flags1, u8 *flags2, u32 *freq, s32 *phase_delay)
5283{
5284 struct ice_aqc_get_cgu_input_config *cmd;
5285 struct ice_aq_desc desc;
5286 int ret;
5287
5288 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_input_config);
5289 cmd = &desc.params.get_cgu_input_config;
5290 cmd->input_idx = input_idx;
5291
5292 ret = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
5293 if (!ret) {
5294 if (status)
5295 *status = cmd->status;
5296 if (type)
5297 *type = cmd->type;
5298 if (flags1)
5299 *flags1 = cmd->flags1;
5300 if (flags2)
5301 *flags2 = cmd->flags2;
5302 if (freq)
5303 *freq = le32_to_cpu(cmd->freq);
5304 if (phase_delay)
5305 *phase_delay = le32_to_cpu(cmd->phase_delay);
5306 }
5307
5308 return ret;
5309}
5310
5311/**
5312 * ice_aq_set_output_pin_cfg - set output pin config
5313 * @hw: pointer to the HW struct
5314 * @output_idx: Output index
5315 * @flags: Output flags
5316 * @src_sel: Index of DPLL block
5317 * @freq: Output frequency
5318 * @phase_delay: Output phase compensation
5319 *
5320 * Set CGU output config (0x0C64)
5321 * Return: 0 on success or negative value on failure.
5322 */
5323int
5324ice_aq_set_output_pin_cfg(struct ice_hw *hw, u8 output_idx, u8 flags,
5325 u8 src_sel, u32 freq, s32 phase_delay)
5326{
5327 struct ice_aqc_set_cgu_output_config *cmd;
5328 struct ice_aq_desc desc;
5329
5330 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_output_config);
5331 cmd = &desc.params.set_cgu_output_config;
5332 cmd->output_idx = output_idx;
5333 cmd->flags = flags;
5334 cmd->src_sel = src_sel;
5335 cmd->freq = cpu_to_le32(freq);
5336 cmd->phase_delay = cpu_to_le32(phase_delay);
5337
5338 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
5339}
5340
5341/**
5342 * ice_aq_get_output_pin_cfg - get output pin config
5343 * @hw: pointer to the HW struct
5344 * @output_idx: Output index
5345 * @flags: Output flags
5346 * @src_sel: Internal DPLL source
5347 * @freq: Output frequency
5348 * @src_freq: Source frequency
5349 *
5350 * Get CGU output config (0x0C65)
5351 * Return: 0 on success or negative value on failure.
5352 */
5353int
5354ice_aq_get_output_pin_cfg(struct ice_hw *hw, u8 output_idx, u8 *flags,
5355 u8 *src_sel, u32 *freq, u32 *src_freq)
5356{
5357 struct ice_aqc_get_cgu_output_config *cmd;
5358 struct ice_aq_desc desc;
5359 int ret;
5360
5361 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_output_config);
5362 cmd = &desc.params.get_cgu_output_config;
5363 cmd->output_idx = output_idx;
5364
5365 ret = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
5366 if (!ret) {
5367 if (flags)
5368 *flags = cmd->flags;
5369 if (src_sel)
5370 *src_sel = cmd->src_sel;
5371 if (freq)
5372 *freq = le32_to_cpu(cmd->freq);
5373 if (src_freq)
5374 *src_freq = le32_to_cpu(cmd->src_freq);
5375 }
5376
5377 return ret;
5378}
5379
5380/**
5381 * ice_aq_get_cgu_dpll_status - get dpll status
5382 * @hw: pointer to the HW struct
5383 * @dpll_num: DPLL index
5384 * @ref_state: Reference clock state
5385 * @config: current DPLL config
5386 * @dpll_state: current DPLL state
5387 * @phase_offset: Phase offset in ns
5388 * @eec_mode: EEC_mode
5389 *
5390 * Get CGU DPLL status (0x0C66)
5391 * Return: 0 on success or negative value on failure.
5392 */
5393int
5394ice_aq_get_cgu_dpll_status(struct ice_hw *hw, u8 dpll_num, u8 *ref_state,
5395 u8 *dpll_state, u8 *config, s64 *phase_offset,
5396 u8 *eec_mode)
5397{
5398 struct ice_aqc_get_cgu_dpll_status *cmd;
5399 struct ice_aq_desc desc;
5400 int status;
5401
5402 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_dpll_status);
5403 cmd = &desc.params.get_cgu_dpll_status;
5404 cmd->dpll_num = dpll_num;
5405
5406 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
5407 if (!status) {
5408 *ref_state = cmd->ref_state;
5409 *dpll_state = cmd->dpll_state;
5410 *config = cmd->config;
5411 *phase_offset = le32_to_cpu(cmd->phase_offset_h);
5412 *phase_offset <<= 32;
5413 *phase_offset += le32_to_cpu(cmd->phase_offset_l);
5414 *phase_offset = sign_extend64(*phase_offset, 47);
5415 *eec_mode = cmd->eec_mode;
5416 }
5417
5418 return status;
5419}
5420
5421/**
5422 * ice_aq_set_cgu_dpll_config - set dpll config
5423 * @hw: pointer to the HW struct
5424 * @dpll_num: DPLL index
5425 * @ref_state: Reference clock state
5426 * @config: DPLL config
5427 * @eec_mode: EEC mode
5428 *
5429 * Set CGU DPLL config (0x0C67)
5430 * Return: 0 on success or negative value on failure.
5431 */
5432int
5433ice_aq_set_cgu_dpll_config(struct ice_hw *hw, u8 dpll_num, u8 ref_state,
5434 u8 config, u8 eec_mode)
5435{
5436 struct ice_aqc_set_cgu_dpll_config *cmd;
5437 struct ice_aq_desc desc;
5438
5439 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_dpll_config);
5440 cmd = &desc.params.set_cgu_dpll_config;
5441 cmd->dpll_num = dpll_num;
5442 cmd->ref_state = ref_state;
5443 cmd->config = config;
5444 cmd->eec_mode = eec_mode;
5445
5446 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
5447}
5448
5449/**
5450 * ice_aq_set_cgu_ref_prio - set input reference priority
5451 * @hw: pointer to the HW struct
5452 * @dpll_num: DPLL index
5453 * @ref_idx: Reference pin index
5454 * @ref_priority: Reference input priority
5455 *
5456 * Set CGU reference priority (0x0C68)
5457 * Return: 0 on success or negative value on failure.
5458 */
5459int
5460ice_aq_set_cgu_ref_prio(struct ice_hw *hw, u8 dpll_num, u8 ref_idx,
5461 u8 ref_priority)
5462{
5463 struct ice_aqc_set_cgu_ref_prio *cmd;
5464 struct ice_aq_desc desc;
5465
5466 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_cgu_ref_prio);
5467 cmd = &desc.params.set_cgu_ref_prio;
5468 cmd->dpll_num = dpll_num;
5469 cmd->ref_idx = ref_idx;
5470 cmd->ref_priority = ref_priority;
5471
5472 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
5473}
5474
5475/**
5476 * ice_aq_get_cgu_ref_prio - get input reference priority
5477 * @hw: pointer to the HW struct
5478 * @dpll_num: DPLL index
5479 * @ref_idx: Reference pin index
5480 * @ref_prio: Reference input priority
5481 *
5482 * Get CGU reference priority (0x0C69)
5483 * Return: 0 on success or negative value on failure.
5484 */
5485int
5486ice_aq_get_cgu_ref_prio(struct ice_hw *hw, u8 dpll_num, u8 ref_idx,
5487 u8 *ref_prio)
5488{
5489 struct ice_aqc_get_cgu_ref_prio *cmd;
5490 struct ice_aq_desc desc;
5491 int status;
5492
5493 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_ref_prio);
5494 cmd = &desc.params.get_cgu_ref_prio;
5495 cmd->dpll_num = dpll_num;
5496 cmd->ref_idx = ref_idx;
5497
5498 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
5499 if (!status)
5500 *ref_prio = cmd->ref_priority;
5501
5502 return status;
5503}
5504
5505/**
5506 * ice_aq_get_cgu_info - get cgu info
5507 * @hw: pointer to the HW struct
5508 * @cgu_id: CGU ID
5509 * @cgu_cfg_ver: CGU config version
5510 * @cgu_fw_ver: CGU firmware version
5511 *
5512 * Get CGU info (0x0C6A)
5513 * Return: 0 on success or negative value on failure.
5514 */
5515int
5516ice_aq_get_cgu_info(struct ice_hw *hw, u32 *cgu_id, u32 *cgu_cfg_ver,
5517 u32 *cgu_fw_ver)
5518{
5519 struct ice_aqc_get_cgu_info *cmd;
5520 struct ice_aq_desc desc;
5521 int status;
5522
5523 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_cgu_info);
5524 cmd = &desc.params.get_cgu_info;
5525
5526 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
5527 if (!status) {
5528 *cgu_id = le32_to_cpu(cmd->cgu_id);
5529 *cgu_cfg_ver = le32_to_cpu(cmd->cgu_cfg_ver);
5530 *cgu_fw_ver = le32_to_cpu(cmd->cgu_fw_ver);
5531 }
5532
5533 return status;
5534}
5535
5536/**
5537 * ice_aq_set_phy_rec_clk_out - set RCLK phy out
5538 * @hw: pointer to the HW struct
5539 * @phy_output: PHY reference clock output pin
5540 * @enable: GPIO state to be applied
5541 * @freq: PHY output frequency
5542 *
5543 * Set phy recovered clock as reference (0x0630)
5544 * Return: 0 on success or negative value on failure.
5545 */
5546int
5547ice_aq_set_phy_rec_clk_out(struct ice_hw *hw, u8 phy_output, bool enable,
5548 u32 *freq)
5549{
5550 struct ice_aqc_set_phy_rec_clk_out *cmd;
5551 struct ice_aq_desc desc;
5552 int status;
5553
5554 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_rec_clk_out);
5555 cmd = &desc.params.set_phy_rec_clk_out;
5556 cmd->phy_output = phy_output;
5557 cmd->port_num = ICE_AQC_SET_PHY_REC_CLK_OUT_CURR_PORT;
5558 cmd->flags = enable & ICE_AQC_SET_PHY_REC_CLK_OUT_OUT_EN;
5559 cmd->freq = cpu_to_le32(*freq);
5560
5561 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
5562 if (!status)
5563 *freq = le32_to_cpu(cmd->freq);
5564
5565 return status;
5566}
5567
5568/**
5569 * ice_aq_get_phy_rec_clk_out - get phy recovered signal info
5570 * @hw: pointer to the HW struct
5571 * @phy_output: PHY reference clock output pin
5572 * @port_num: Port number
5573 * @flags: PHY flags
5574 * @node_handle: PHY output frequency
5575 *
5576 * Get PHY recovered clock output info (0x0631)
5577 * Return: 0 on success or negative value on failure.
5578 */
5579int
5580ice_aq_get_phy_rec_clk_out(struct ice_hw *hw, u8 *phy_output, u8 *port_num,
5581 u8 *flags, u16 *node_handle)
5582{
5583 struct ice_aqc_get_phy_rec_clk_out *cmd;
5584 struct ice_aq_desc desc;
5585 int status;
5586
5587 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_rec_clk_out);
5588 cmd = &desc.params.get_phy_rec_clk_out;
5589 cmd->phy_output = *phy_output;
5590
5591 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
5592 if (!status) {
5593 *phy_output = cmd->phy_output;
5594 if (port_num)
5595 *port_num = cmd->port_num;
5596 if (flags)
5597 *flags = cmd->flags;
5598 if (node_handle)
5599 *node_handle = le16_to_cpu(cmd->node_handle);
5600 }
5601
5602 return status;
5603}
5604
5605/**
5606 * ice_aq_get_sensor_reading
5607 * @hw: pointer to the HW struct
5608 * @data: pointer to data to be read from the sensor
5609 *
5610 * Get sensor reading (0x0632)
5611 */
5612int ice_aq_get_sensor_reading(struct ice_hw *hw,
5613 struct ice_aqc_get_sensor_reading_resp *data)
5614{
5615 struct ice_aqc_get_sensor_reading *cmd;
5616 struct ice_aq_desc desc;
5617 int status;
5618
5619 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_sensor_reading);
5620 cmd = &desc.params.get_sensor_reading;
5621#define ICE_INTERNAL_TEMP_SENSOR_FORMAT 0
5622#define ICE_INTERNAL_TEMP_SENSOR 0
5623 cmd->sensor = ICE_INTERNAL_TEMP_SENSOR;
5624 cmd->format = ICE_INTERNAL_TEMP_SENSOR_FORMAT;
5625
5626 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
5627 if (!status)
5628 memcpy(data, &desc.params.get_sensor_reading_resp,
5629 sizeof(*data));
5630
5631 return status;
5632}
5633
5634/**
5635 * ice_replay_pre_init - replay pre initialization
5636 * @hw: pointer to the HW struct
5637 *
5638 * Initializes required config data for VSI, FD, ACL, and RSS before replay.
5639 */
5640static int ice_replay_pre_init(struct ice_hw *hw)
5641{
5642 struct ice_switch_info *sw = hw->switch_info;
5643 u8 i;
5644
5645 /* Delete old entries from replay filter list head if there is any */
5646 ice_rm_all_sw_replay_rule_info(hw);
5647 /* In start of replay, move entries into replay_rules list, it
5648 * will allow adding rules entries back to filt_rules list,
5649 * which is operational list.
5650 */
5651 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++)
5652 list_replace_init(&sw->recp_list[i].filt_rules,
5653 &sw->recp_list[i].filt_replay_rules);
5654 ice_sched_replay_agg_vsi_preinit(hw);
5655
5656 return 0;
5657}
5658
5659/**
5660 * ice_replay_vsi - replay VSI configuration
5661 * @hw: pointer to the HW struct
5662 * @vsi_handle: driver VSI handle
5663 *
5664 * Restore all VSI configuration after reset. It is required to call this
5665 * function with main VSI first.
5666 */
5667int ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle)
5668{
5669 int status;
5670
5671 if (!ice_is_vsi_valid(hw, vsi_handle))
5672 return -EINVAL;
5673
5674 /* Replay pre-initialization if there is any */
5675 if (vsi_handle == ICE_MAIN_VSI_HANDLE) {
5676 status = ice_replay_pre_init(hw);
5677 if (status)
5678 return status;
5679 }
5680 /* Replay per VSI all RSS configurations */
5681 status = ice_replay_rss_cfg(hw, vsi_handle);
5682 if (status)
5683 return status;
5684 /* Replay per VSI all filters */
5685 status = ice_replay_vsi_all_fltr(hw, vsi_handle);
5686 if (!status)
5687 status = ice_replay_vsi_agg(hw, vsi_handle);
5688 return status;
5689}
5690
5691/**
5692 * ice_replay_post - post replay configuration cleanup
5693 * @hw: pointer to the HW struct
5694 *
5695 * Post replay cleanup.
5696 */
5697void ice_replay_post(struct ice_hw *hw)
5698{
5699 /* Delete old entries from replay filter list head */
5700 ice_rm_all_sw_replay_rule_info(hw);
5701 ice_sched_replay_agg(hw);
5702}
5703
5704/**
5705 * ice_stat_update40 - read 40 bit stat from the chip and update stat values
5706 * @hw: ptr to the hardware info
5707 * @reg: offset of 64 bit HW register to read from
5708 * @prev_stat_loaded: bool to specify if previous stats are loaded
5709 * @prev_stat: ptr to previous loaded stat value
5710 * @cur_stat: ptr to current stat value
5711 */
5712void
5713ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
5714 u64 *prev_stat, u64 *cur_stat)
5715{
5716 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1);
5717
5718 /* device stats are not reset at PFR, they likely will not be zeroed
5719 * when the driver starts. Thus, save the value from the first read
5720 * without adding to the statistic value so that we report stats which
5721 * count up from zero.
5722 */
5723 if (!prev_stat_loaded) {
5724 *prev_stat = new_data;
5725 return;
5726 }
5727
5728 /* Calculate the difference between the new and old values, and then
5729 * add it to the software stat value.
5730 */
5731 if (new_data >= *prev_stat)
5732 *cur_stat += new_data - *prev_stat;
5733 else
5734 /* to manage the potential roll-over */
5735 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat;
5736
5737 /* Update the previously stored value to prepare for next read */
5738 *prev_stat = new_data;
5739}
5740
5741/**
5742 * ice_stat_update32 - read 32 bit stat from the chip and update stat values
5743 * @hw: ptr to the hardware info
5744 * @reg: offset of HW register to read from
5745 * @prev_stat_loaded: bool to specify if previous stats are loaded
5746 * @prev_stat: ptr to previous loaded stat value
5747 * @cur_stat: ptr to current stat value
5748 */
5749void
5750ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
5751 u64 *prev_stat, u64 *cur_stat)
5752{
5753 u32 new_data;
5754
5755 new_data = rd32(hw, reg);
5756
5757 /* device stats are not reset at PFR, they likely will not be zeroed
5758 * when the driver starts. Thus, save the value from the first read
5759 * without adding to the statistic value so that we report stats which
5760 * count up from zero.
5761 */
5762 if (!prev_stat_loaded) {
5763 *prev_stat = new_data;
5764 return;
5765 }
5766
5767 /* Calculate the difference between the new and old values, and then
5768 * add it to the software stat value.
5769 */
5770 if (new_data >= *prev_stat)
5771 *cur_stat += new_data - *prev_stat;
5772 else
5773 /* to manage the potential roll-over */
5774 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat;
5775
5776 /* Update the previously stored value to prepare for next read */
5777 *prev_stat = new_data;
5778}
5779
5780/**
5781 * ice_sched_query_elem - query element information from HW
5782 * @hw: pointer to the HW struct
5783 * @node_teid: node TEID to be queried
5784 * @buf: buffer to element information
5785 *
5786 * This function queries HW element information
5787 */
5788int
5789ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
5790 struct ice_aqc_txsched_elem_data *buf)
5791{
5792 u16 buf_size, num_elem_ret = 0;
5793 int status;
5794
5795 buf_size = sizeof(*buf);
5796 memset(buf, 0, buf_size);
5797 buf->node_teid = cpu_to_le32(node_teid);
5798 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret,
5799 NULL);
5800 if (status || num_elem_ret != 1)
5801 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n");
5802 return status;
5803}
5804
5805/**
5806 * ice_aq_read_i2c
5807 * @hw: pointer to the hw struct
5808 * @topo_addr: topology address for a device to communicate with
5809 * @bus_addr: 7-bit I2C bus address
5810 * @addr: I2C memory address (I2C offset) with up to 16 bits
5811 * @params: I2C parameters: bit [7] - Repeated start,
5812 * bits [6:5] data offset size,
5813 * bit [4] - I2C address type,
5814 * bits [3:0] - data size to read (0-16 bytes)
5815 * @data: pointer to data (0 to 16 bytes) to be read from the I2C device
5816 * @cd: pointer to command details structure or NULL
5817 *
5818 * Read I2C (0x06E2)
5819 */
5820int
5821ice_aq_read_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr,
5822 u16 bus_addr, __le16 addr, u8 params, u8 *data,
5823 struct ice_sq_cd *cd)
5824{
5825 struct ice_aq_desc desc = { 0 };
5826 struct ice_aqc_i2c *cmd;
5827 u8 data_size;
5828 int status;
5829
5830 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_read_i2c);
5831 cmd = &desc.params.read_write_i2c;
5832
5833 if (!data)
5834 return -EINVAL;
5835
5836 data_size = FIELD_GET(ICE_AQC_I2C_DATA_SIZE_M, params);
5837
5838 cmd->i2c_bus_addr = cpu_to_le16(bus_addr);
5839 cmd->topo_addr = topo_addr;
5840 cmd->i2c_params = params;
5841 cmd->i2c_addr = addr;
5842
5843 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
5844 if (!status) {
5845 struct ice_aqc_read_i2c_resp *resp;
5846 u8 i;
5847
5848 resp = &desc.params.read_i2c_resp;
5849 for (i = 0; i < data_size; i++) {
5850 *data = resp->i2c_data[i];
5851 data++;
5852 }
5853 }
5854
5855 return status;
5856}
5857
5858/**
5859 * ice_aq_write_i2c
5860 * @hw: pointer to the hw struct
5861 * @topo_addr: topology address for a device to communicate with
5862 * @bus_addr: 7-bit I2C bus address
5863 * @addr: I2C memory address (I2C offset) with up to 16 bits
5864 * @params: I2C parameters: bit [4] - I2C address type, bits [3:0] - data size to write (0-7 bytes)
5865 * @data: pointer to data (0 to 4 bytes) to be written to the I2C device
5866 * @cd: pointer to command details structure or NULL
5867 *
5868 * Write I2C (0x06E3)
5869 *
5870 * * Return:
5871 * * 0 - Successful write to the i2c device
5872 * * -EINVAL - Data size greater than 4 bytes
5873 * * -EIO - FW error
5874 */
5875int
5876ice_aq_write_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr,
5877 u16 bus_addr, __le16 addr, u8 params, const u8 *data,
5878 struct ice_sq_cd *cd)
5879{
5880 struct ice_aq_desc desc = { 0 };
5881 struct ice_aqc_i2c *cmd;
5882 u8 data_size;
5883
5884 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_write_i2c);
5885 cmd = &desc.params.read_write_i2c;
5886
5887 data_size = FIELD_GET(ICE_AQC_I2C_DATA_SIZE_M, params);
5888
5889 /* data_size limited to 4 */
5890 if (data_size > 4)
5891 return -EINVAL;
5892
5893 cmd->i2c_bus_addr = cpu_to_le16(bus_addr);
5894 cmd->topo_addr = topo_addr;
5895 cmd->i2c_params = params;
5896 cmd->i2c_addr = addr;
5897
5898 memcpy(cmd->i2c_data, data, data_size);
5899
5900 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
5901}
5902
5903/**
5904 * ice_aq_set_gpio
5905 * @hw: pointer to the hw struct
5906 * @gpio_ctrl_handle: GPIO controller node handle
5907 * @pin_idx: IO Number of the GPIO that needs to be set
5908 * @value: SW provide IO value to set in the LSB
5909 * @cd: pointer to command details structure or NULL
5910 *
5911 * Sends 0x06EC AQ command to set the GPIO pin state that's part of the topology
5912 */
5913int
5914ice_aq_set_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, bool value,
5915 struct ice_sq_cd *cd)
5916{
5917 struct ice_aqc_gpio *cmd;
5918 struct ice_aq_desc desc;
5919
5920 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_gpio);
5921 cmd = &desc.params.read_write_gpio;
5922 cmd->gpio_ctrl_handle = cpu_to_le16(gpio_ctrl_handle);
5923 cmd->gpio_num = pin_idx;
5924 cmd->gpio_val = value ? 1 : 0;
5925
5926 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
5927}
5928
5929/**
5930 * ice_aq_get_gpio
5931 * @hw: pointer to the hw struct
5932 * @gpio_ctrl_handle: GPIO controller node handle
5933 * @pin_idx: IO Number of the GPIO that needs to be set
5934 * @value: IO value read
5935 * @cd: pointer to command details structure or NULL
5936 *
5937 * Sends 0x06ED AQ command to get the value of a GPIO signal which is part of
5938 * the topology
5939 */
5940int
5941ice_aq_get_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx,
5942 bool *value, struct ice_sq_cd *cd)
5943{
5944 struct ice_aqc_gpio *cmd;
5945 struct ice_aq_desc desc;
5946 int status;
5947
5948 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_gpio);
5949 cmd = &desc.params.read_write_gpio;
5950 cmd->gpio_ctrl_handle = cpu_to_le16(gpio_ctrl_handle);
5951 cmd->gpio_num = pin_idx;
5952
5953 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
5954 if (status)
5955 return status;
5956
5957 *value = !!cmd->gpio_val;
5958 return 0;
5959}
5960
5961/**
5962 * ice_is_fw_api_min_ver
5963 * @hw: pointer to the hardware structure
5964 * @maj: major version
5965 * @min: minor version
5966 * @patch: patch version
5967 *
5968 * Checks if the firmware API is minimum version
5969 */
5970static bool ice_is_fw_api_min_ver(struct ice_hw *hw, u8 maj, u8 min, u8 patch)
5971{
5972 if (hw->api_maj_ver == maj) {
5973 if (hw->api_min_ver > min)
5974 return true;
5975 if (hw->api_min_ver == min && hw->api_patch >= patch)
5976 return true;
5977 } else if (hw->api_maj_ver > maj) {
5978 return true;
5979 }
5980
5981 return false;
5982}
5983
5984/**
5985 * ice_fw_supports_link_override
5986 * @hw: pointer to the hardware structure
5987 *
5988 * Checks if the firmware supports link override
5989 */
5990bool ice_fw_supports_link_override(struct ice_hw *hw)
5991{
5992 return ice_is_fw_api_min_ver(hw, ICE_FW_API_LINK_OVERRIDE_MAJ,
5993 ICE_FW_API_LINK_OVERRIDE_MIN,
5994 ICE_FW_API_LINK_OVERRIDE_PATCH);
5995}
5996
5997/**
5998 * ice_get_link_default_override
5999 * @ldo: pointer to the link default override struct
6000 * @pi: pointer to the port info struct
6001 *
6002 * Gets the link default override for a port
6003 */
6004int
6005ice_get_link_default_override(struct ice_link_default_override_tlv *ldo,
6006 struct ice_port_info *pi)
6007{
6008 u16 i, tlv, tlv_len, tlv_start, buf, offset;
6009 struct ice_hw *hw = pi->hw;
6010 int status;
6011
6012 status = ice_get_pfa_module_tlv(hw, &tlv, &tlv_len,
6013 ICE_SR_LINK_DEFAULT_OVERRIDE_PTR);
6014 if (status) {
6015 ice_debug(hw, ICE_DBG_INIT, "Failed to read link override TLV.\n");
6016 return status;
6017 }
6018
6019 /* Each port has its own config; calculate for our port */
6020 tlv_start = tlv + pi->lport * ICE_SR_PFA_LINK_OVERRIDE_WORDS +
6021 ICE_SR_PFA_LINK_OVERRIDE_OFFSET;
6022
6023 /* link options first */
6024 status = ice_read_sr_word(hw, tlv_start, &buf);
6025 if (status) {
6026 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n");
6027 return status;
6028 }
6029 ldo->options = FIELD_GET(ICE_LINK_OVERRIDE_OPT_M, buf);
6030 ldo->phy_config = (buf & ICE_LINK_OVERRIDE_PHY_CFG_M) >>
6031 ICE_LINK_OVERRIDE_PHY_CFG_S;
6032
6033 /* link PHY config */
6034 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET;
6035 status = ice_read_sr_word(hw, offset, &buf);
6036 if (status) {
6037 ice_debug(hw, ICE_DBG_INIT, "Failed to read override phy config.\n");
6038 return status;
6039 }
6040 ldo->fec_options = buf & ICE_LINK_OVERRIDE_FEC_OPT_M;
6041
6042 /* PHY types low */
6043 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET;
6044 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) {
6045 status = ice_read_sr_word(hw, (offset + i), &buf);
6046 if (status) {
6047 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n");
6048 return status;
6049 }
6050 /* shift 16 bits at a time to fill 64 bits */
6051 ldo->phy_type_low |= ((u64)buf << (i * 16));
6052 }
6053
6054 /* PHY types high */
6055 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET +
6056 ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS;
6057 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) {
6058 status = ice_read_sr_word(hw, (offset + i), &buf);
6059 if (status) {
6060 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n");
6061 return status;
6062 }
6063 /* shift 16 bits at a time to fill 64 bits */
6064 ldo->phy_type_high |= ((u64)buf << (i * 16));
6065 }
6066
6067 return status;
6068}
6069
6070/**
6071 * ice_is_phy_caps_an_enabled - check if PHY capabilities autoneg is enabled
6072 * @caps: get PHY capability data
6073 */
6074bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps)
6075{
6076 if (caps->caps & ICE_AQC_PHY_AN_MODE ||
6077 caps->low_power_ctrl_an & (ICE_AQC_PHY_AN_EN_CLAUSE28 |
6078 ICE_AQC_PHY_AN_EN_CLAUSE73 |
6079 ICE_AQC_PHY_AN_EN_CLAUSE37))
6080 return true;
6081
6082 return false;
6083}
6084
6085/**
6086 * ice_aq_set_lldp_mib - Set the LLDP MIB
6087 * @hw: pointer to the HW struct
6088 * @mib_type: Local, Remote or both Local and Remote MIBs
6089 * @buf: pointer to the caller-supplied buffer to store the MIB block
6090 * @buf_size: size of the buffer (in bytes)
6091 * @cd: pointer to command details structure or NULL
6092 *
6093 * Set the LLDP MIB. (0x0A08)
6094 */
6095int
6096ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size,
6097 struct ice_sq_cd *cd)
6098{
6099 struct ice_aqc_lldp_set_local_mib *cmd;
6100 struct ice_aq_desc desc;
6101
6102 cmd = &desc.params.lldp_set_mib;
6103
6104 if (buf_size == 0 || !buf)
6105 return -EINVAL;
6106
6107 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_set_local_mib);
6108
6109 desc.flags |= cpu_to_le16((u16)ICE_AQ_FLAG_RD);
6110 desc.datalen = cpu_to_le16(buf_size);
6111
6112 cmd->type = mib_type;
6113 cmd->length = cpu_to_le16(buf_size);
6114
6115 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
6116}
6117
6118/**
6119 * ice_fw_supports_lldp_fltr_ctrl - check NVM version supports lldp_fltr_ctrl
6120 * @hw: pointer to HW struct
6121 */
6122bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw)
6123{
6124 if (hw->mac_type != ICE_MAC_E810)
6125 return false;
6126
6127 return ice_is_fw_api_min_ver(hw, ICE_FW_API_LLDP_FLTR_MAJ,
6128 ICE_FW_API_LLDP_FLTR_MIN,
6129 ICE_FW_API_LLDP_FLTR_PATCH);
6130}
6131
6132/**
6133 * ice_lldp_fltr_add_remove - add or remove a LLDP Rx switch filter
6134 * @hw: pointer to HW struct
6135 * @vsi_num: absolute HW index for VSI
6136 * @add: boolean for if adding or removing a filter
6137 */
6138int
6139ice_lldp_fltr_add_remove(struct ice_hw *hw, u16 vsi_num, bool add)
6140{
6141 struct ice_aqc_lldp_filter_ctrl *cmd;
6142 struct ice_aq_desc desc;
6143
6144 cmd = &desc.params.lldp_filter_ctrl;
6145
6146 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_filter_ctrl);
6147
6148 if (add)
6149 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_ADD;
6150 else
6151 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_DELETE;
6152
6153 cmd->vsi_num = cpu_to_le16(vsi_num);
6154
6155 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
6156}
6157
6158/**
6159 * ice_lldp_execute_pending_mib - execute LLDP pending MIB request
6160 * @hw: pointer to HW struct
6161 */
6162int ice_lldp_execute_pending_mib(struct ice_hw *hw)
6163{
6164 struct ice_aq_desc desc;
6165
6166 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_execute_pending_mib);
6167
6168 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
6169}
6170
6171/**
6172 * ice_fw_supports_report_dflt_cfg
6173 * @hw: pointer to the hardware structure
6174 *
6175 * Checks if the firmware supports report default configuration
6176 */
6177bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw)
6178{
6179 return ice_is_fw_api_min_ver(hw, ICE_FW_API_REPORT_DFLT_CFG_MAJ,
6180 ICE_FW_API_REPORT_DFLT_CFG_MIN,
6181 ICE_FW_API_REPORT_DFLT_CFG_PATCH);
6182}
6183
6184/* each of the indexes into the following array match the speed of a return
6185 * value from the list of AQ returned speeds like the range:
6186 * ICE_AQ_LINK_SPEED_10MB .. ICE_AQ_LINK_SPEED_100GB excluding
6187 * ICE_AQ_LINK_SPEED_UNKNOWN which is BIT(15) and maps to BIT(14) in this
6188 * array. The array is defined as 15 elements long because the link_speed
6189 * returned by the firmware is a 16 bit * value, but is indexed
6190 * by [fls(speed) - 1]
6191 */
6192static const u32 ice_aq_to_link_speed[] = {
6193 SPEED_10, /* BIT(0) */
6194 SPEED_100,
6195 SPEED_1000,
6196 SPEED_2500,
6197 SPEED_5000,
6198 SPEED_10000,
6199 SPEED_20000,
6200 SPEED_25000,
6201 SPEED_40000,
6202 SPEED_50000,
6203 SPEED_100000, /* BIT(10) */
6204 SPEED_200000,
6205};
6206
6207/**
6208 * ice_get_link_speed - get integer speed from table
6209 * @index: array index from fls(aq speed) - 1
6210 *
6211 * Returns: u32 value containing integer speed
6212 */
6213u32 ice_get_link_speed(u16 index)
6214{
6215 if (index >= ARRAY_SIZE(ice_aq_to_link_speed))
6216 return 0;
6217
6218 return ice_aq_to_link_speed[index];
6219}