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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Faraday FTGMAC100 Gigabit Ethernet
4 *
5 * (C) Copyright 2009-2011 Faraday Technology
6 * Po-Yu Chuang <ratbert@faraday-tech.com>
7 */
8
9#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10
11#include <linux/clk.h>
12#include <linux/dma-mapping.h>
13#include <linux/etherdevice.h>
14#include <linux/ethtool.h>
15#include <linux/interrupt.h>
16#include <linux/io.h>
17#include <linux/module.h>
18#include <linux/netdevice.h>
19#include <linux/of.h>
20#include <linux/of_mdio.h>
21#include <linux/phy.h>
22#include <linux/platform_device.h>
23#include <linux/property.h>
24#include <linux/crc32.h>
25#include <linux/if_vlan.h>
26#include <linux/of_net.h>
27#include <linux/phy_fixed.h>
28#include <net/ip.h>
29#include <net/ncsi.h>
30
31#include "ftgmac100.h"
32
33#define DRV_NAME "ftgmac100"
34
35/* Arbitrary values, I am not sure the HW has limits */
36#define MAX_RX_QUEUE_ENTRIES 1024
37#define MAX_TX_QUEUE_ENTRIES 1024
38#define MIN_RX_QUEUE_ENTRIES 32
39#define MIN_TX_QUEUE_ENTRIES 32
40
41/* Defaults */
42#define DEF_RX_QUEUE_ENTRIES 128
43#define DEF_TX_QUEUE_ENTRIES 128
44
45#define MAX_PKT_SIZE 1536
46#define RX_BUF_SIZE MAX_PKT_SIZE /* must be smaller than 0x3fff */
47
48/* Min number of tx ring entries before stopping queue */
49#define TX_THRESHOLD (MAX_SKB_FRAGS + 1)
50
51#define FTGMAC_100MHZ 100000000
52#define FTGMAC_25MHZ 25000000
53
54/* For NC-SI to register a fixed-link phy device */
55static struct fixed_phy_status ncsi_phy_status = {
56 .link = 1,
57 .speed = SPEED_100,
58 .duplex = DUPLEX_FULL,
59 .pause = 0,
60 .asym_pause = 0
61};
62
63struct ftgmac100 {
64 /* Registers */
65 struct resource *res;
66 void __iomem *base;
67
68 /* Rx ring */
69 unsigned int rx_q_entries;
70 struct ftgmac100_rxdes *rxdes;
71 dma_addr_t rxdes_dma;
72 struct sk_buff **rx_skbs;
73 unsigned int rx_pointer;
74 u32 rxdes0_edorr_mask;
75
76 /* Tx ring */
77 unsigned int tx_q_entries;
78 struct ftgmac100_txdes *txdes;
79 dma_addr_t txdes_dma;
80 struct sk_buff **tx_skbs;
81 unsigned int tx_clean_pointer;
82 unsigned int tx_pointer;
83 u32 txdes0_edotr_mask;
84
85 /* Used to signal the reset task of ring change request */
86 unsigned int new_rx_q_entries;
87 unsigned int new_tx_q_entries;
88
89 /* Scratch page to use when rx skb alloc fails */
90 void *rx_scratch;
91 dma_addr_t rx_scratch_dma;
92
93 /* Component structures */
94 struct net_device *netdev;
95 struct device *dev;
96 struct ncsi_dev *ndev;
97 struct napi_struct napi;
98 struct work_struct reset_task;
99 struct mii_bus *mii_bus;
100 struct clk *clk;
101
102 /* AST2500/AST2600 RMII ref clock gate */
103 struct clk *rclk;
104
105 /* Link management */
106 int cur_speed;
107 int cur_duplex;
108 bool use_ncsi;
109
110 /* Multicast filter settings */
111 u32 maht0;
112 u32 maht1;
113
114 /* Flow control settings */
115 bool tx_pause;
116 bool rx_pause;
117 bool aneg_pause;
118
119 /* Misc */
120 bool need_mac_restart;
121 bool is_aspeed;
122};
123
124static int ftgmac100_reset_mac(struct ftgmac100 *priv, u32 maccr)
125{
126 struct net_device *netdev = priv->netdev;
127 int i;
128
129 /* NOTE: reset clears all registers */
130 iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR);
131 iowrite32(maccr | FTGMAC100_MACCR_SW_RST,
132 priv->base + FTGMAC100_OFFSET_MACCR);
133 for (i = 0; i < 200; i++) {
134 unsigned int maccr;
135
136 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR);
137 if (!(maccr & FTGMAC100_MACCR_SW_RST))
138 return 0;
139
140 udelay(1);
141 }
142
143 netdev_err(netdev, "Hardware reset failed\n");
144 return -EIO;
145}
146
147static int ftgmac100_reset_and_config_mac(struct ftgmac100 *priv)
148{
149 u32 maccr = 0;
150
151 switch (priv->cur_speed) {
152 case SPEED_10:
153 case 0: /* no link */
154 break;
155
156 case SPEED_100:
157 maccr |= FTGMAC100_MACCR_FAST_MODE;
158 break;
159
160 case SPEED_1000:
161 maccr |= FTGMAC100_MACCR_GIGA_MODE;
162 break;
163 default:
164 netdev_err(priv->netdev, "Unknown speed %d !\n",
165 priv->cur_speed);
166 break;
167 }
168
169 /* (Re)initialize the queue pointers */
170 priv->rx_pointer = 0;
171 priv->tx_clean_pointer = 0;
172 priv->tx_pointer = 0;
173
174 /* The doc says reset twice with 10us interval */
175 if (ftgmac100_reset_mac(priv, maccr))
176 return -EIO;
177 usleep_range(10, 1000);
178 return ftgmac100_reset_mac(priv, maccr);
179}
180
181static void ftgmac100_write_mac_addr(struct ftgmac100 *priv, const u8 *mac)
182{
183 unsigned int maddr = mac[0] << 8 | mac[1];
184 unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5];
185
186 iowrite32(maddr, priv->base + FTGMAC100_OFFSET_MAC_MADR);
187 iowrite32(laddr, priv->base + FTGMAC100_OFFSET_MAC_LADR);
188}
189
190static int ftgmac100_initial_mac(struct ftgmac100 *priv)
191{
192 u8 mac[ETH_ALEN];
193 unsigned int m;
194 unsigned int l;
195 int err;
196
197 err = of_get_ethdev_address(priv->dev->of_node, priv->netdev);
198 if (err == -EPROBE_DEFER)
199 return err;
200 if (!err) {
201 dev_info(priv->dev, "Read MAC address %pM from device tree\n",
202 priv->netdev->dev_addr);
203 return 0;
204 }
205
206 m = ioread32(priv->base + FTGMAC100_OFFSET_MAC_MADR);
207 l = ioread32(priv->base + FTGMAC100_OFFSET_MAC_LADR);
208
209 mac[0] = (m >> 8) & 0xff;
210 mac[1] = m & 0xff;
211 mac[2] = (l >> 24) & 0xff;
212 mac[3] = (l >> 16) & 0xff;
213 mac[4] = (l >> 8) & 0xff;
214 mac[5] = l & 0xff;
215
216 if (is_valid_ether_addr(mac)) {
217 eth_hw_addr_set(priv->netdev, mac);
218 dev_info(priv->dev, "Read MAC address %pM from chip\n", mac);
219 } else {
220 eth_hw_addr_random(priv->netdev);
221 dev_info(priv->dev, "Generated random MAC address %pM\n",
222 priv->netdev->dev_addr);
223 }
224
225 return 0;
226}
227
228static int ftgmac100_set_mac_addr(struct net_device *dev, void *p)
229{
230 int ret;
231
232 ret = eth_prepare_mac_addr_change(dev, p);
233 if (ret < 0)
234 return ret;
235
236 eth_commit_mac_addr_change(dev, p);
237 ftgmac100_write_mac_addr(netdev_priv(dev), dev->dev_addr);
238
239 return 0;
240}
241
242static void ftgmac100_config_pause(struct ftgmac100 *priv)
243{
244 u32 fcr = FTGMAC100_FCR_PAUSE_TIME(16);
245
246 /* Throttle tx queue when receiving pause frames */
247 if (priv->rx_pause)
248 fcr |= FTGMAC100_FCR_FC_EN;
249
250 /* Enables sending pause frames when the RX queue is past a
251 * certain threshold.
252 */
253 if (priv->tx_pause)
254 fcr |= FTGMAC100_FCR_FCTHR_EN;
255
256 iowrite32(fcr, priv->base + FTGMAC100_OFFSET_FCR);
257}
258
259static void ftgmac100_init_hw(struct ftgmac100 *priv)
260{
261 u32 reg, rfifo_sz, tfifo_sz;
262
263 /* Clear stale interrupts */
264 reg = ioread32(priv->base + FTGMAC100_OFFSET_ISR);
265 iowrite32(reg, priv->base + FTGMAC100_OFFSET_ISR);
266
267 /* Setup RX ring buffer base */
268 iowrite32(priv->rxdes_dma, priv->base + FTGMAC100_OFFSET_RXR_BADR);
269
270 /* Setup TX ring buffer base */
271 iowrite32(priv->txdes_dma, priv->base + FTGMAC100_OFFSET_NPTXR_BADR);
272
273 /* Configure RX buffer size */
274 iowrite32(FTGMAC100_RBSR_SIZE(RX_BUF_SIZE),
275 priv->base + FTGMAC100_OFFSET_RBSR);
276
277 /* Set RX descriptor autopoll */
278 iowrite32(FTGMAC100_APTC_RXPOLL_CNT(1),
279 priv->base + FTGMAC100_OFFSET_APTC);
280
281 /* Write MAC address */
282 ftgmac100_write_mac_addr(priv, priv->netdev->dev_addr);
283
284 /* Write multicast filter */
285 iowrite32(priv->maht0, priv->base + FTGMAC100_OFFSET_MAHT0);
286 iowrite32(priv->maht1, priv->base + FTGMAC100_OFFSET_MAHT1);
287
288 /* Configure descriptor sizes and increase burst sizes according
289 * to values in Aspeed SDK. The FIFO arbitration is enabled and
290 * the thresholds set based on the recommended values in the
291 * AST2400 specification.
292 */
293 iowrite32(FTGMAC100_DBLAC_RXDES_SIZE(2) | /* 2*8 bytes RX descs */
294 FTGMAC100_DBLAC_TXDES_SIZE(2) | /* 2*8 bytes TX descs */
295 FTGMAC100_DBLAC_RXBURST_SIZE(3) | /* 512 bytes max RX bursts */
296 FTGMAC100_DBLAC_TXBURST_SIZE(3) | /* 512 bytes max TX bursts */
297 FTGMAC100_DBLAC_RX_THR_EN | /* Enable fifo threshold arb */
298 FTGMAC100_DBLAC_RXFIFO_HTHR(6) | /* 6/8 of FIFO high threshold */
299 FTGMAC100_DBLAC_RXFIFO_LTHR(2), /* 2/8 of FIFO low threshold */
300 priv->base + FTGMAC100_OFFSET_DBLAC);
301
302 /* Interrupt mitigation configured for 1 interrupt/packet. HW interrupt
303 * mitigation doesn't seem to provide any benefit with NAPI so leave
304 * it at that.
305 */
306 iowrite32(FTGMAC100_ITC_RXINT_THR(1) |
307 FTGMAC100_ITC_TXINT_THR(1),
308 priv->base + FTGMAC100_OFFSET_ITC);
309
310 /* Configure FIFO sizes in the TPAFCR register */
311 reg = ioread32(priv->base + FTGMAC100_OFFSET_FEAR);
312 rfifo_sz = reg & 0x00000007;
313 tfifo_sz = (reg >> 3) & 0x00000007;
314 reg = ioread32(priv->base + FTGMAC100_OFFSET_TPAFCR);
315 reg &= ~0x3f000000;
316 reg |= (tfifo_sz << 27);
317 reg |= (rfifo_sz << 24);
318 iowrite32(reg, priv->base + FTGMAC100_OFFSET_TPAFCR);
319}
320
321static void ftgmac100_start_hw(struct ftgmac100 *priv)
322{
323 u32 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR);
324
325 /* Keep the original GMAC and FAST bits */
326 maccr &= (FTGMAC100_MACCR_FAST_MODE | FTGMAC100_MACCR_GIGA_MODE);
327
328 /* Add all the main enable bits */
329 maccr |= FTGMAC100_MACCR_TXDMA_EN |
330 FTGMAC100_MACCR_RXDMA_EN |
331 FTGMAC100_MACCR_TXMAC_EN |
332 FTGMAC100_MACCR_RXMAC_EN |
333 FTGMAC100_MACCR_CRC_APD |
334 FTGMAC100_MACCR_PHY_LINK_LEVEL |
335 FTGMAC100_MACCR_RX_RUNT |
336 FTGMAC100_MACCR_RX_BROADPKT;
337
338 /* Add other bits as needed */
339 if (priv->cur_duplex == DUPLEX_FULL)
340 maccr |= FTGMAC100_MACCR_FULLDUP;
341 if (priv->netdev->flags & IFF_PROMISC)
342 maccr |= FTGMAC100_MACCR_RX_ALL;
343 if (priv->netdev->flags & IFF_ALLMULTI)
344 maccr |= FTGMAC100_MACCR_RX_MULTIPKT;
345 else if (netdev_mc_count(priv->netdev))
346 maccr |= FTGMAC100_MACCR_HT_MULTI_EN;
347
348 /* Vlan filtering enabled */
349 if (priv->netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
350 maccr |= FTGMAC100_MACCR_RM_VLAN;
351
352 /* Hit the HW */
353 iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR);
354}
355
356static void ftgmac100_stop_hw(struct ftgmac100 *priv)
357{
358 iowrite32(0, priv->base + FTGMAC100_OFFSET_MACCR);
359}
360
361static void ftgmac100_calc_mc_hash(struct ftgmac100 *priv)
362{
363 struct netdev_hw_addr *ha;
364
365 priv->maht1 = 0;
366 priv->maht0 = 0;
367 netdev_for_each_mc_addr(ha, priv->netdev) {
368 u32 crc_val = ether_crc_le(ETH_ALEN, ha->addr);
369
370 crc_val = (~(crc_val >> 2)) & 0x3f;
371 if (crc_val >= 32)
372 priv->maht1 |= 1ul << (crc_val - 32);
373 else
374 priv->maht0 |= 1ul << (crc_val);
375 }
376}
377
378static void ftgmac100_set_rx_mode(struct net_device *netdev)
379{
380 struct ftgmac100 *priv = netdev_priv(netdev);
381
382 /* Setup the hash filter */
383 ftgmac100_calc_mc_hash(priv);
384
385 /* Interface down ? that's all there is to do */
386 if (!netif_running(netdev))
387 return;
388
389 /* Update the HW */
390 iowrite32(priv->maht0, priv->base + FTGMAC100_OFFSET_MAHT0);
391 iowrite32(priv->maht1, priv->base + FTGMAC100_OFFSET_MAHT1);
392
393 /* Reconfigure MACCR */
394 ftgmac100_start_hw(priv);
395}
396
397static int ftgmac100_alloc_rx_buf(struct ftgmac100 *priv, unsigned int entry,
398 struct ftgmac100_rxdes *rxdes, gfp_t gfp)
399{
400 struct net_device *netdev = priv->netdev;
401 struct sk_buff *skb;
402 dma_addr_t map;
403 int err = 0;
404
405 skb = netdev_alloc_skb_ip_align(netdev, RX_BUF_SIZE);
406 if (unlikely(!skb)) {
407 if (net_ratelimit())
408 netdev_warn(netdev, "failed to allocate rx skb\n");
409 err = -ENOMEM;
410 map = priv->rx_scratch_dma;
411 } else {
412 map = dma_map_single(priv->dev, skb->data, RX_BUF_SIZE,
413 DMA_FROM_DEVICE);
414 if (unlikely(dma_mapping_error(priv->dev, map))) {
415 if (net_ratelimit())
416 netdev_err(netdev, "failed to map rx page\n");
417 dev_kfree_skb_any(skb);
418 map = priv->rx_scratch_dma;
419 skb = NULL;
420 err = -ENOMEM;
421 }
422 }
423
424 /* Store skb */
425 priv->rx_skbs[entry] = skb;
426
427 /* Store DMA address into RX desc */
428 rxdes->rxdes3 = cpu_to_le32(map);
429
430 /* Ensure the above is ordered vs clearing the OWN bit */
431 dma_wmb();
432
433 /* Clean status (which resets own bit) */
434 if (entry == (priv->rx_q_entries - 1))
435 rxdes->rxdes0 = cpu_to_le32(priv->rxdes0_edorr_mask);
436 else
437 rxdes->rxdes0 = 0;
438
439 return err;
440}
441
442static unsigned int ftgmac100_next_rx_pointer(struct ftgmac100 *priv,
443 unsigned int pointer)
444{
445 return (pointer + 1) & (priv->rx_q_entries - 1);
446}
447
448static void ftgmac100_rx_packet_error(struct ftgmac100 *priv, u32 status)
449{
450 struct net_device *netdev = priv->netdev;
451
452 if (status & FTGMAC100_RXDES0_RX_ERR)
453 netdev->stats.rx_errors++;
454
455 if (status & FTGMAC100_RXDES0_CRC_ERR)
456 netdev->stats.rx_crc_errors++;
457
458 if (status & (FTGMAC100_RXDES0_FTL |
459 FTGMAC100_RXDES0_RUNT |
460 FTGMAC100_RXDES0_RX_ODD_NB))
461 netdev->stats.rx_length_errors++;
462}
463
464static bool ftgmac100_rx_packet(struct ftgmac100 *priv, int *processed)
465{
466 struct net_device *netdev = priv->netdev;
467 struct ftgmac100_rxdes *rxdes;
468 struct sk_buff *skb;
469 unsigned int pointer, size;
470 u32 status, csum_vlan;
471 dma_addr_t map;
472
473 /* Grab next RX descriptor */
474 pointer = priv->rx_pointer;
475 rxdes = &priv->rxdes[pointer];
476
477 /* Grab descriptor status */
478 status = le32_to_cpu(rxdes->rxdes0);
479
480 /* Do we have a packet ? */
481 if (!(status & FTGMAC100_RXDES0_RXPKT_RDY))
482 return false;
483
484 /* Order subsequent reads with the test for the ready bit */
485 dma_rmb();
486
487 /* We don't cope with fragmented RX packets */
488 if (unlikely(!(status & FTGMAC100_RXDES0_FRS) ||
489 !(status & FTGMAC100_RXDES0_LRS)))
490 goto drop;
491
492 /* Grab received size and csum vlan field in the descriptor */
493 size = status & FTGMAC100_RXDES0_VDBC;
494 csum_vlan = le32_to_cpu(rxdes->rxdes1);
495
496 /* Any error (other than csum offload) flagged ? */
497 if (unlikely(status & RXDES0_ANY_ERROR)) {
498 /* Correct for incorrect flagging of runt packets
499 * with vlan tags... Just accept a runt packet that
500 * has been flagged as vlan and whose size is at
501 * least 60 bytes.
502 */
503 if ((status & FTGMAC100_RXDES0_RUNT) &&
504 (csum_vlan & FTGMAC100_RXDES1_VLANTAG_AVAIL) &&
505 (size >= 60))
506 status &= ~FTGMAC100_RXDES0_RUNT;
507
508 /* Any error still in there ? */
509 if (status & RXDES0_ANY_ERROR) {
510 ftgmac100_rx_packet_error(priv, status);
511 goto drop;
512 }
513 }
514
515 /* If the packet had no skb (failed to allocate earlier)
516 * then try to allocate one and skip
517 */
518 skb = priv->rx_skbs[pointer];
519 if (!unlikely(skb)) {
520 ftgmac100_alloc_rx_buf(priv, pointer, rxdes, GFP_ATOMIC);
521 goto drop;
522 }
523
524 if (unlikely(status & FTGMAC100_RXDES0_MULTICAST))
525 netdev->stats.multicast++;
526
527 /* If the HW found checksum errors, bounce it to software.
528 *
529 * If we didn't, we need to see if the packet was recognized
530 * by HW as one of the supported checksummed protocols before
531 * we accept the HW test results.
532 */
533 if (netdev->features & NETIF_F_RXCSUM) {
534 u32 err_bits = FTGMAC100_RXDES1_TCP_CHKSUM_ERR |
535 FTGMAC100_RXDES1_UDP_CHKSUM_ERR |
536 FTGMAC100_RXDES1_IP_CHKSUM_ERR;
537 if ((csum_vlan & err_bits) ||
538 !(csum_vlan & FTGMAC100_RXDES1_PROT_MASK))
539 skb->ip_summed = CHECKSUM_NONE;
540 else
541 skb->ip_summed = CHECKSUM_UNNECESSARY;
542 }
543
544 /* Transfer received size to skb */
545 skb_put(skb, size);
546
547 /* Extract vlan tag */
548 if ((netdev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
549 (csum_vlan & FTGMAC100_RXDES1_VLANTAG_AVAIL))
550 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
551 csum_vlan & 0xffff);
552
553 /* Tear down DMA mapping, do necessary cache management */
554 map = le32_to_cpu(rxdes->rxdes3);
555
556#if defined(CONFIG_ARM) && !defined(CONFIG_ARM_DMA_USE_IOMMU)
557 /* When we don't have an iommu, we can save cycles by not
558 * invalidating the cache for the part of the packet that
559 * wasn't received.
560 */
561 dma_unmap_single(priv->dev, map, size, DMA_FROM_DEVICE);
562#else
563 dma_unmap_single(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE);
564#endif
565
566
567 /* Resplenish rx ring */
568 ftgmac100_alloc_rx_buf(priv, pointer, rxdes, GFP_ATOMIC);
569 priv->rx_pointer = ftgmac100_next_rx_pointer(priv, pointer);
570
571 skb->protocol = eth_type_trans(skb, netdev);
572
573 netdev->stats.rx_packets++;
574 netdev->stats.rx_bytes += size;
575
576 /* push packet to protocol stack */
577 if (skb->ip_summed == CHECKSUM_NONE)
578 netif_receive_skb(skb);
579 else
580 napi_gro_receive(&priv->napi, skb);
581
582 (*processed)++;
583 return true;
584
585drop:
586 /* Clean rxdes0 (which resets own bit) */
587 rxdes->rxdes0 = cpu_to_le32(status & priv->rxdes0_edorr_mask);
588 priv->rx_pointer = ftgmac100_next_rx_pointer(priv, pointer);
589 netdev->stats.rx_dropped++;
590 return true;
591}
592
593static u32 ftgmac100_base_tx_ctlstat(struct ftgmac100 *priv,
594 unsigned int index)
595{
596 if (index == (priv->tx_q_entries - 1))
597 return priv->txdes0_edotr_mask;
598 else
599 return 0;
600}
601
602static unsigned int ftgmac100_next_tx_pointer(struct ftgmac100 *priv,
603 unsigned int pointer)
604{
605 return (pointer + 1) & (priv->tx_q_entries - 1);
606}
607
608static u32 ftgmac100_tx_buf_avail(struct ftgmac100 *priv)
609{
610 /* Returns the number of available slots in the TX queue
611 *
612 * This always leaves one free slot so we don't have to
613 * worry about empty vs. full, and this simplifies the
614 * test for ftgmac100_tx_buf_cleanable() below
615 */
616 return (priv->tx_clean_pointer - priv->tx_pointer - 1) &
617 (priv->tx_q_entries - 1);
618}
619
620static bool ftgmac100_tx_buf_cleanable(struct ftgmac100 *priv)
621{
622 return priv->tx_pointer != priv->tx_clean_pointer;
623}
624
625static void ftgmac100_free_tx_packet(struct ftgmac100 *priv,
626 unsigned int pointer,
627 struct sk_buff *skb,
628 struct ftgmac100_txdes *txdes,
629 u32 ctl_stat)
630{
631 dma_addr_t map = le32_to_cpu(txdes->txdes3);
632 size_t len;
633
634 if (ctl_stat & FTGMAC100_TXDES0_FTS) {
635 len = skb_headlen(skb);
636 dma_unmap_single(priv->dev, map, len, DMA_TO_DEVICE);
637 } else {
638 len = FTGMAC100_TXDES0_TXBUF_SIZE(ctl_stat);
639 dma_unmap_page(priv->dev, map, len, DMA_TO_DEVICE);
640 }
641
642 /* Free SKB on last segment */
643 if (ctl_stat & FTGMAC100_TXDES0_LTS)
644 dev_kfree_skb(skb);
645 priv->tx_skbs[pointer] = NULL;
646}
647
648static bool ftgmac100_tx_complete_packet(struct ftgmac100 *priv)
649{
650 struct net_device *netdev = priv->netdev;
651 struct ftgmac100_txdes *txdes;
652 struct sk_buff *skb;
653 unsigned int pointer;
654 u32 ctl_stat;
655
656 pointer = priv->tx_clean_pointer;
657 txdes = &priv->txdes[pointer];
658
659 ctl_stat = le32_to_cpu(txdes->txdes0);
660 if (ctl_stat & FTGMAC100_TXDES0_TXDMA_OWN)
661 return false;
662
663 skb = priv->tx_skbs[pointer];
664 netdev->stats.tx_packets++;
665 netdev->stats.tx_bytes += skb->len;
666 ftgmac100_free_tx_packet(priv, pointer, skb, txdes, ctl_stat);
667 txdes->txdes0 = cpu_to_le32(ctl_stat & priv->txdes0_edotr_mask);
668
669 /* Ensure the descriptor config is visible before setting the tx
670 * pointer.
671 */
672 smp_wmb();
673
674 priv->tx_clean_pointer = ftgmac100_next_tx_pointer(priv, pointer);
675
676 return true;
677}
678
679static void ftgmac100_tx_complete(struct ftgmac100 *priv)
680{
681 struct net_device *netdev = priv->netdev;
682
683 /* Process all completed packets */
684 while (ftgmac100_tx_buf_cleanable(priv) &&
685 ftgmac100_tx_complete_packet(priv))
686 ;
687
688 /* Restart queue if needed */
689 smp_mb();
690 if (unlikely(netif_queue_stopped(netdev) &&
691 ftgmac100_tx_buf_avail(priv) >= TX_THRESHOLD)) {
692 struct netdev_queue *txq;
693
694 txq = netdev_get_tx_queue(netdev, 0);
695 __netif_tx_lock(txq, smp_processor_id());
696 if (netif_queue_stopped(netdev) &&
697 ftgmac100_tx_buf_avail(priv) >= TX_THRESHOLD)
698 netif_wake_queue(netdev);
699 __netif_tx_unlock(txq);
700 }
701}
702
703static bool ftgmac100_prep_tx_csum(struct sk_buff *skb, u32 *csum_vlan)
704{
705 if (skb->protocol == cpu_to_be16(ETH_P_IP)) {
706 u8 ip_proto = ip_hdr(skb)->protocol;
707
708 *csum_vlan |= FTGMAC100_TXDES1_IP_CHKSUM;
709 switch(ip_proto) {
710 case IPPROTO_TCP:
711 *csum_vlan |= FTGMAC100_TXDES1_TCP_CHKSUM;
712 return true;
713 case IPPROTO_UDP:
714 *csum_vlan |= FTGMAC100_TXDES1_UDP_CHKSUM;
715 return true;
716 case IPPROTO_IP:
717 return true;
718 }
719 }
720 return skb_checksum_help(skb) == 0;
721}
722
723static netdev_tx_t ftgmac100_hard_start_xmit(struct sk_buff *skb,
724 struct net_device *netdev)
725{
726 struct ftgmac100 *priv = netdev_priv(netdev);
727 struct ftgmac100_txdes *txdes, *first;
728 unsigned int pointer, nfrags, len, i, j;
729 u32 f_ctl_stat, ctl_stat, csum_vlan;
730 dma_addr_t map;
731
732 /* The HW doesn't pad small frames */
733 if (eth_skb_pad(skb)) {
734 netdev->stats.tx_dropped++;
735 return NETDEV_TX_OK;
736 }
737
738 /* Reject oversize packets */
739 if (unlikely(skb->len > MAX_PKT_SIZE)) {
740 if (net_ratelimit())
741 netdev_dbg(netdev, "tx packet too big\n");
742 goto drop;
743 }
744
745 /* Do we have a limit on #fragments ? I yet have to get a reply
746 * from Aspeed. If there's one I haven't hit it.
747 */
748 nfrags = skb_shinfo(skb)->nr_frags;
749
750 /* Setup HW checksumming */
751 csum_vlan = 0;
752 if (skb->ip_summed == CHECKSUM_PARTIAL &&
753 !ftgmac100_prep_tx_csum(skb, &csum_vlan))
754 goto drop;
755
756 /* Add VLAN tag */
757 if (skb_vlan_tag_present(skb)) {
758 csum_vlan |= FTGMAC100_TXDES1_INS_VLANTAG;
759 csum_vlan |= skb_vlan_tag_get(skb) & 0xffff;
760 }
761
762 /* Get header len */
763 len = skb_headlen(skb);
764
765 /* Map the packet head */
766 map = dma_map_single(priv->dev, skb->data, len, DMA_TO_DEVICE);
767 if (dma_mapping_error(priv->dev, map)) {
768 if (net_ratelimit())
769 netdev_err(netdev, "map tx packet head failed\n");
770 goto drop;
771 }
772
773 /* Grab the next free tx descriptor */
774 pointer = priv->tx_pointer;
775 txdes = first = &priv->txdes[pointer];
776
777 /* Setup it up with the packet head. Don't write the head to the
778 * ring just yet
779 */
780 priv->tx_skbs[pointer] = skb;
781 f_ctl_stat = ftgmac100_base_tx_ctlstat(priv, pointer);
782 f_ctl_stat |= FTGMAC100_TXDES0_TXDMA_OWN;
783 f_ctl_stat |= FTGMAC100_TXDES0_TXBUF_SIZE(len);
784 f_ctl_stat |= FTGMAC100_TXDES0_FTS;
785 if (nfrags == 0)
786 f_ctl_stat |= FTGMAC100_TXDES0_LTS;
787 txdes->txdes3 = cpu_to_le32(map);
788 txdes->txdes1 = cpu_to_le32(csum_vlan);
789
790 /* Next descriptor */
791 pointer = ftgmac100_next_tx_pointer(priv, pointer);
792
793 /* Add the fragments */
794 for (i = 0; i < nfrags; i++) {
795 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
796
797 len = skb_frag_size(frag);
798
799 /* Map it */
800 map = skb_frag_dma_map(priv->dev, frag, 0, len,
801 DMA_TO_DEVICE);
802 if (dma_mapping_error(priv->dev, map))
803 goto dma_err;
804
805 /* Setup descriptor */
806 priv->tx_skbs[pointer] = skb;
807 txdes = &priv->txdes[pointer];
808 ctl_stat = ftgmac100_base_tx_ctlstat(priv, pointer);
809 ctl_stat |= FTGMAC100_TXDES0_TXDMA_OWN;
810 ctl_stat |= FTGMAC100_TXDES0_TXBUF_SIZE(len);
811 if (i == (nfrags - 1))
812 ctl_stat |= FTGMAC100_TXDES0_LTS;
813 txdes->txdes0 = cpu_to_le32(ctl_stat);
814 txdes->txdes1 = 0;
815 txdes->txdes3 = cpu_to_le32(map);
816
817 /* Next one */
818 pointer = ftgmac100_next_tx_pointer(priv, pointer);
819 }
820
821 /* Order the previous packet and descriptor udpates
822 * before setting the OWN bit on the first descriptor.
823 */
824 dma_wmb();
825 first->txdes0 = cpu_to_le32(f_ctl_stat);
826
827 /* Ensure the descriptor config is visible before setting the tx
828 * pointer.
829 */
830 smp_wmb();
831
832 /* Update next TX pointer */
833 priv->tx_pointer = pointer;
834
835 /* If there isn't enough room for all the fragments of a new packet
836 * in the TX ring, stop the queue. The sequence below is race free
837 * vs. a concurrent restart in ftgmac100_poll()
838 */
839 if (unlikely(ftgmac100_tx_buf_avail(priv) < TX_THRESHOLD)) {
840 netif_stop_queue(netdev);
841 /* Order the queue stop with the test below */
842 smp_mb();
843 if (ftgmac100_tx_buf_avail(priv) >= TX_THRESHOLD)
844 netif_wake_queue(netdev);
845 }
846
847 /* Poke transmitter to read the updated TX descriptors */
848 iowrite32(1, priv->base + FTGMAC100_OFFSET_NPTXPD);
849
850 return NETDEV_TX_OK;
851
852dma_err:
853 if (net_ratelimit())
854 netdev_err(netdev, "map tx fragment failed\n");
855
856 /* Free head */
857 pointer = priv->tx_pointer;
858 ftgmac100_free_tx_packet(priv, pointer, skb, first, f_ctl_stat);
859 first->txdes0 = cpu_to_le32(f_ctl_stat & priv->txdes0_edotr_mask);
860
861 /* Then all fragments */
862 for (j = 0; j < i; j++) {
863 pointer = ftgmac100_next_tx_pointer(priv, pointer);
864 txdes = &priv->txdes[pointer];
865 ctl_stat = le32_to_cpu(txdes->txdes0);
866 ftgmac100_free_tx_packet(priv, pointer, skb, txdes, ctl_stat);
867 txdes->txdes0 = cpu_to_le32(ctl_stat & priv->txdes0_edotr_mask);
868 }
869
870 /* This cannot be reached if we successfully mapped the
871 * last fragment, so we know ftgmac100_free_tx_packet()
872 * hasn't freed the skb yet.
873 */
874drop:
875 /* Drop the packet */
876 dev_kfree_skb_any(skb);
877 netdev->stats.tx_dropped++;
878
879 return NETDEV_TX_OK;
880}
881
882static void ftgmac100_free_buffers(struct ftgmac100 *priv)
883{
884 int i;
885
886 /* Free all RX buffers */
887 for (i = 0; i < priv->rx_q_entries; i++) {
888 struct ftgmac100_rxdes *rxdes = &priv->rxdes[i];
889 struct sk_buff *skb = priv->rx_skbs[i];
890 dma_addr_t map = le32_to_cpu(rxdes->rxdes3);
891
892 if (!skb)
893 continue;
894
895 priv->rx_skbs[i] = NULL;
896 dma_unmap_single(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE);
897 dev_kfree_skb_any(skb);
898 }
899
900 /* Free all TX buffers */
901 for (i = 0; i < priv->tx_q_entries; i++) {
902 struct ftgmac100_txdes *txdes = &priv->txdes[i];
903 struct sk_buff *skb = priv->tx_skbs[i];
904
905 if (!skb)
906 continue;
907 ftgmac100_free_tx_packet(priv, i, skb, txdes,
908 le32_to_cpu(txdes->txdes0));
909 }
910}
911
912static void ftgmac100_free_rings(struct ftgmac100 *priv)
913{
914 /* Free skb arrays */
915 kfree(priv->rx_skbs);
916 kfree(priv->tx_skbs);
917
918 /* Free descriptors */
919 if (priv->rxdes)
920 dma_free_coherent(priv->dev, MAX_RX_QUEUE_ENTRIES *
921 sizeof(struct ftgmac100_rxdes),
922 priv->rxdes, priv->rxdes_dma);
923 priv->rxdes = NULL;
924
925 if (priv->txdes)
926 dma_free_coherent(priv->dev, MAX_TX_QUEUE_ENTRIES *
927 sizeof(struct ftgmac100_txdes),
928 priv->txdes, priv->txdes_dma);
929 priv->txdes = NULL;
930
931 /* Free scratch packet buffer */
932 if (priv->rx_scratch)
933 dma_free_coherent(priv->dev, RX_BUF_SIZE,
934 priv->rx_scratch, priv->rx_scratch_dma);
935}
936
937static int ftgmac100_alloc_rings(struct ftgmac100 *priv)
938{
939 /* Allocate skb arrays */
940 priv->rx_skbs = kcalloc(MAX_RX_QUEUE_ENTRIES, sizeof(void *),
941 GFP_KERNEL);
942 if (!priv->rx_skbs)
943 return -ENOMEM;
944 priv->tx_skbs = kcalloc(MAX_TX_QUEUE_ENTRIES, sizeof(void *),
945 GFP_KERNEL);
946 if (!priv->tx_skbs)
947 return -ENOMEM;
948
949 /* Allocate descriptors */
950 priv->rxdes = dma_alloc_coherent(priv->dev,
951 MAX_RX_QUEUE_ENTRIES * sizeof(struct ftgmac100_rxdes),
952 &priv->rxdes_dma, GFP_KERNEL);
953 if (!priv->rxdes)
954 return -ENOMEM;
955 priv->txdes = dma_alloc_coherent(priv->dev,
956 MAX_TX_QUEUE_ENTRIES * sizeof(struct ftgmac100_txdes),
957 &priv->txdes_dma, GFP_KERNEL);
958 if (!priv->txdes)
959 return -ENOMEM;
960
961 /* Allocate scratch packet buffer */
962 priv->rx_scratch = dma_alloc_coherent(priv->dev,
963 RX_BUF_SIZE,
964 &priv->rx_scratch_dma,
965 GFP_KERNEL);
966 if (!priv->rx_scratch)
967 return -ENOMEM;
968
969 return 0;
970}
971
972static void ftgmac100_init_rings(struct ftgmac100 *priv)
973{
974 struct ftgmac100_rxdes *rxdes = NULL;
975 struct ftgmac100_txdes *txdes = NULL;
976 int i;
977
978 /* Update entries counts */
979 priv->rx_q_entries = priv->new_rx_q_entries;
980 priv->tx_q_entries = priv->new_tx_q_entries;
981
982 if (WARN_ON(priv->rx_q_entries < MIN_RX_QUEUE_ENTRIES))
983 return;
984
985 /* Initialize RX ring */
986 for (i = 0; i < priv->rx_q_entries; i++) {
987 rxdes = &priv->rxdes[i];
988 rxdes->rxdes0 = 0;
989 rxdes->rxdes3 = cpu_to_le32(priv->rx_scratch_dma);
990 }
991 /* Mark the end of the ring */
992 rxdes->rxdes0 |= cpu_to_le32(priv->rxdes0_edorr_mask);
993
994 if (WARN_ON(priv->tx_q_entries < MIN_RX_QUEUE_ENTRIES))
995 return;
996
997 /* Initialize TX ring */
998 for (i = 0; i < priv->tx_q_entries; i++) {
999 txdes = &priv->txdes[i];
1000 txdes->txdes0 = 0;
1001 }
1002 txdes->txdes0 |= cpu_to_le32(priv->txdes0_edotr_mask);
1003}
1004
1005static int ftgmac100_alloc_rx_buffers(struct ftgmac100 *priv)
1006{
1007 int i;
1008
1009 for (i = 0; i < priv->rx_q_entries; i++) {
1010 struct ftgmac100_rxdes *rxdes = &priv->rxdes[i];
1011
1012 if (ftgmac100_alloc_rx_buf(priv, i, rxdes, GFP_KERNEL))
1013 return -ENOMEM;
1014 }
1015 return 0;
1016}
1017
1018static int ftgmac100_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
1019{
1020 struct net_device *netdev = bus->priv;
1021 struct ftgmac100 *priv = netdev_priv(netdev);
1022 unsigned int phycr;
1023 int i;
1024
1025 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
1026
1027 /* preserve MDC cycle threshold */
1028 phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK;
1029
1030 phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) |
1031 FTGMAC100_PHYCR_REGAD(regnum) |
1032 FTGMAC100_PHYCR_MIIRD;
1033
1034 iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR);
1035
1036 for (i = 0; i < 10; i++) {
1037 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
1038
1039 if ((phycr & FTGMAC100_PHYCR_MIIRD) == 0) {
1040 int data;
1041
1042 data = ioread32(priv->base + FTGMAC100_OFFSET_PHYDATA);
1043 return FTGMAC100_PHYDATA_MIIRDATA(data);
1044 }
1045
1046 udelay(100);
1047 }
1048
1049 netdev_err(netdev, "mdio read timed out\n");
1050 return -EIO;
1051}
1052
1053static int ftgmac100_mdiobus_write(struct mii_bus *bus, int phy_addr,
1054 int regnum, u16 value)
1055{
1056 struct net_device *netdev = bus->priv;
1057 struct ftgmac100 *priv = netdev_priv(netdev);
1058 unsigned int phycr;
1059 int data;
1060 int i;
1061
1062 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
1063
1064 /* preserve MDC cycle threshold */
1065 phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK;
1066
1067 phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) |
1068 FTGMAC100_PHYCR_REGAD(regnum) |
1069 FTGMAC100_PHYCR_MIIWR;
1070
1071 data = FTGMAC100_PHYDATA_MIIWDATA(value);
1072
1073 iowrite32(data, priv->base + FTGMAC100_OFFSET_PHYDATA);
1074 iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR);
1075
1076 for (i = 0; i < 10; i++) {
1077 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
1078
1079 if ((phycr & FTGMAC100_PHYCR_MIIWR) == 0)
1080 return 0;
1081
1082 udelay(100);
1083 }
1084
1085 netdev_err(netdev, "mdio write timed out\n");
1086 return -EIO;
1087}
1088
1089static void ftgmac100_get_drvinfo(struct net_device *netdev,
1090 struct ethtool_drvinfo *info)
1091{
1092 strscpy(info->driver, DRV_NAME, sizeof(info->driver));
1093 strscpy(info->bus_info, dev_name(&netdev->dev), sizeof(info->bus_info));
1094}
1095
1096static void
1097ftgmac100_get_ringparam(struct net_device *netdev,
1098 struct ethtool_ringparam *ering,
1099 struct kernel_ethtool_ringparam *kernel_ering,
1100 struct netlink_ext_ack *extack)
1101{
1102 struct ftgmac100 *priv = netdev_priv(netdev);
1103
1104 memset(ering, 0, sizeof(*ering));
1105 ering->rx_max_pending = MAX_RX_QUEUE_ENTRIES;
1106 ering->tx_max_pending = MAX_TX_QUEUE_ENTRIES;
1107 ering->rx_pending = priv->rx_q_entries;
1108 ering->tx_pending = priv->tx_q_entries;
1109}
1110
1111static int
1112ftgmac100_set_ringparam(struct net_device *netdev,
1113 struct ethtool_ringparam *ering,
1114 struct kernel_ethtool_ringparam *kernel_ering,
1115 struct netlink_ext_ack *extack)
1116{
1117 struct ftgmac100 *priv = netdev_priv(netdev);
1118
1119 if (ering->rx_pending > MAX_RX_QUEUE_ENTRIES ||
1120 ering->tx_pending > MAX_TX_QUEUE_ENTRIES ||
1121 ering->rx_pending < MIN_RX_QUEUE_ENTRIES ||
1122 ering->tx_pending < MIN_TX_QUEUE_ENTRIES ||
1123 !is_power_of_2(ering->rx_pending) ||
1124 !is_power_of_2(ering->tx_pending))
1125 return -EINVAL;
1126
1127 priv->new_rx_q_entries = ering->rx_pending;
1128 priv->new_tx_q_entries = ering->tx_pending;
1129 if (netif_running(netdev))
1130 schedule_work(&priv->reset_task);
1131
1132 return 0;
1133}
1134
1135static void ftgmac100_get_pauseparam(struct net_device *netdev,
1136 struct ethtool_pauseparam *pause)
1137{
1138 struct ftgmac100 *priv = netdev_priv(netdev);
1139
1140 pause->autoneg = priv->aneg_pause;
1141 pause->tx_pause = priv->tx_pause;
1142 pause->rx_pause = priv->rx_pause;
1143}
1144
1145static int ftgmac100_set_pauseparam(struct net_device *netdev,
1146 struct ethtool_pauseparam *pause)
1147{
1148 struct ftgmac100 *priv = netdev_priv(netdev);
1149 struct phy_device *phydev = netdev->phydev;
1150
1151 priv->aneg_pause = pause->autoneg;
1152 priv->tx_pause = pause->tx_pause;
1153 priv->rx_pause = pause->rx_pause;
1154
1155 if (phydev)
1156 phy_set_asym_pause(phydev, pause->rx_pause, pause->tx_pause);
1157
1158 if (netif_running(netdev)) {
1159 if (!(phydev && priv->aneg_pause))
1160 ftgmac100_config_pause(priv);
1161 }
1162
1163 return 0;
1164}
1165
1166static const struct ethtool_ops ftgmac100_ethtool_ops = {
1167 .get_drvinfo = ftgmac100_get_drvinfo,
1168 .get_link = ethtool_op_get_link,
1169 .get_link_ksettings = phy_ethtool_get_link_ksettings,
1170 .set_link_ksettings = phy_ethtool_set_link_ksettings,
1171 .nway_reset = phy_ethtool_nway_reset,
1172 .get_ringparam = ftgmac100_get_ringparam,
1173 .set_ringparam = ftgmac100_set_ringparam,
1174 .get_pauseparam = ftgmac100_get_pauseparam,
1175 .set_pauseparam = ftgmac100_set_pauseparam,
1176};
1177
1178static irqreturn_t ftgmac100_interrupt(int irq, void *dev_id)
1179{
1180 struct net_device *netdev = dev_id;
1181 struct ftgmac100 *priv = netdev_priv(netdev);
1182 unsigned int status, new_mask = FTGMAC100_INT_BAD;
1183
1184 /* Fetch and clear interrupt bits, process abnormal ones */
1185 status = ioread32(priv->base + FTGMAC100_OFFSET_ISR);
1186 iowrite32(status, priv->base + FTGMAC100_OFFSET_ISR);
1187 if (unlikely(status & FTGMAC100_INT_BAD)) {
1188
1189 /* RX buffer unavailable */
1190 if (status & FTGMAC100_INT_NO_RXBUF)
1191 netdev->stats.rx_over_errors++;
1192
1193 /* received packet lost due to RX FIFO full */
1194 if (status & FTGMAC100_INT_RPKT_LOST)
1195 netdev->stats.rx_fifo_errors++;
1196
1197 /* sent packet lost due to excessive TX collision */
1198 if (status & FTGMAC100_INT_XPKT_LOST)
1199 netdev->stats.tx_fifo_errors++;
1200
1201 /* AHB error -> Reset the chip */
1202 if (status & FTGMAC100_INT_AHB_ERR) {
1203 if (net_ratelimit())
1204 netdev_warn(netdev,
1205 "AHB bus error ! Resetting chip.\n");
1206 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1207 schedule_work(&priv->reset_task);
1208 return IRQ_HANDLED;
1209 }
1210
1211 /* We may need to restart the MAC after such errors, delay
1212 * this until after we have freed some Rx buffers though
1213 */
1214 priv->need_mac_restart = true;
1215
1216 /* Disable those errors until we restart */
1217 new_mask &= ~status;
1218 }
1219
1220 /* Only enable "bad" interrupts while NAPI is on */
1221 iowrite32(new_mask, priv->base + FTGMAC100_OFFSET_IER);
1222
1223 /* Schedule NAPI bh */
1224 napi_schedule_irqoff(&priv->napi);
1225
1226 return IRQ_HANDLED;
1227}
1228
1229static bool ftgmac100_check_rx(struct ftgmac100 *priv)
1230{
1231 struct ftgmac100_rxdes *rxdes = &priv->rxdes[priv->rx_pointer];
1232
1233 /* Do we have a packet ? */
1234 return !!(rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RXPKT_RDY));
1235}
1236
1237static int ftgmac100_poll(struct napi_struct *napi, int budget)
1238{
1239 struct ftgmac100 *priv = container_of(napi, struct ftgmac100, napi);
1240 int work_done = 0;
1241 bool more;
1242
1243 /* Handle TX completions */
1244 if (ftgmac100_tx_buf_cleanable(priv))
1245 ftgmac100_tx_complete(priv);
1246
1247 /* Handle RX packets */
1248 do {
1249 more = ftgmac100_rx_packet(priv, &work_done);
1250 } while (more && work_done < budget);
1251
1252
1253 /* The interrupt is telling us to kick the MAC back to life
1254 * after an RX overflow
1255 */
1256 if (unlikely(priv->need_mac_restart)) {
1257 ftgmac100_start_hw(priv);
1258 priv->need_mac_restart = false;
1259
1260 /* Re-enable "bad" interrupts */
1261 iowrite32(FTGMAC100_INT_BAD,
1262 priv->base + FTGMAC100_OFFSET_IER);
1263 }
1264
1265 /* As long as we are waiting for transmit packets to be
1266 * completed we keep NAPI going
1267 */
1268 if (ftgmac100_tx_buf_cleanable(priv))
1269 work_done = budget;
1270
1271 if (work_done < budget) {
1272 /* We are about to re-enable all interrupts. However
1273 * the HW has been latching RX/TX packet interrupts while
1274 * they were masked. So we clear them first, then we need
1275 * to re-check if there's something to process
1276 */
1277 iowrite32(FTGMAC100_INT_RXTX,
1278 priv->base + FTGMAC100_OFFSET_ISR);
1279
1280 /* Push the above (and provides a barrier vs. subsequent
1281 * reads of the descriptor).
1282 */
1283 ioread32(priv->base + FTGMAC100_OFFSET_ISR);
1284
1285 /* Check RX and TX descriptors for more work to do */
1286 if (ftgmac100_check_rx(priv) ||
1287 ftgmac100_tx_buf_cleanable(priv))
1288 return budget;
1289
1290 /* deschedule NAPI */
1291 napi_complete(napi);
1292
1293 /* enable all interrupts */
1294 iowrite32(FTGMAC100_INT_ALL,
1295 priv->base + FTGMAC100_OFFSET_IER);
1296 }
1297
1298 return work_done;
1299}
1300
1301static int ftgmac100_init_all(struct ftgmac100 *priv, bool ignore_alloc_err)
1302{
1303 int err = 0;
1304
1305 /* Re-init descriptors (adjust queue sizes) */
1306 ftgmac100_init_rings(priv);
1307
1308 /* Realloc rx descriptors */
1309 err = ftgmac100_alloc_rx_buffers(priv);
1310 if (err && !ignore_alloc_err)
1311 return err;
1312
1313 /* Reinit and restart HW */
1314 ftgmac100_init_hw(priv);
1315 ftgmac100_config_pause(priv);
1316 ftgmac100_start_hw(priv);
1317
1318 /* Re-enable the device */
1319 napi_enable(&priv->napi);
1320 netif_start_queue(priv->netdev);
1321
1322 /* Enable all interrupts */
1323 iowrite32(FTGMAC100_INT_ALL, priv->base + FTGMAC100_OFFSET_IER);
1324
1325 return err;
1326}
1327
1328static void ftgmac100_reset(struct ftgmac100 *priv)
1329{
1330 struct net_device *netdev = priv->netdev;
1331 int err;
1332
1333 netdev_dbg(netdev, "Resetting NIC...\n");
1334
1335 /* Lock the world */
1336 rtnl_lock();
1337 if (netdev->phydev)
1338 mutex_lock(&netdev->phydev->lock);
1339 if (priv->mii_bus)
1340 mutex_lock(&priv->mii_bus->mdio_lock);
1341
1342
1343 /* Check if the interface is still up */
1344 if (!netif_running(netdev))
1345 goto bail;
1346
1347 /* Stop the network stack */
1348 netif_trans_update(netdev);
1349 napi_disable(&priv->napi);
1350 netif_tx_disable(netdev);
1351
1352 /* Stop and reset the MAC */
1353 ftgmac100_stop_hw(priv);
1354 err = ftgmac100_reset_and_config_mac(priv);
1355 if (err) {
1356 /* Not much we can do ... it might come back... */
1357 netdev_err(netdev, "attempting to continue...\n");
1358 }
1359
1360 /* Free all rx and tx buffers */
1361 ftgmac100_free_buffers(priv);
1362
1363 /* Setup everything again and restart chip */
1364 ftgmac100_init_all(priv, true);
1365
1366 netdev_dbg(netdev, "Reset done !\n");
1367bail:
1368 if (priv->mii_bus)
1369 mutex_unlock(&priv->mii_bus->mdio_lock);
1370 if (netdev->phydev)
1371 mutex_unlock(&netdev->phydev->lock);
1372 rtnl_unlock();
1373}
1374
1375static void ftgmac100_reset_task(struct work_struct *work)
1376{
1377 struct ftgmac100 *priv = container_of(work, struct ftgmac100,
1378 reset_task);
1379
1380 ftgmac100_reset(priv);
1381}
1382
1383static void ftgmac100_adjust_link(struct net_device *netdev)
1384{
1385 struct ftgmac100 *priv = netdev_priv(netdev);
1386 struct phy_device *phydev = netdev->phydev;
1387 bool tx_pause, rx_pause;
1388 int new_speed;
1389
1390 /* We store "no link" as speed 0 */
1391 if (!phydev->link)
1392 new_speed = 0;
1393 else
1394 new_speed = phydev->speed;
1395
1396 /* Grab pause settings from PHY if configured to do so */
1397 if (priv->aneg_pause) {
1398 rx_pause = tx_pause = phydev->pause;
1399 if (phydev->asym_pause)
1400 tx_pause = !rx_pause;
1401 } else {
1402 rx_pause = priv->rx_pause;
1403 tx_pause = priv->tx_pause;
1404 }
1405
1406 /* Link hasn't changed, do nothing */
1407 if (phydev->speed == priv->cur_speed &&
1408 phydev->duplex == priv->cur_duplex &&
1409 rx_pause == priv->rx_pause &&
1410 tx_pause == priv->tx_pause)
1411 return;
1412
1413 /* Print status if we have a link or we had one and just lost it,
1414 * don't print otherwise.
1415 */
1416 if (new_speed || priv->cur_speed)
1417 phy_print_status(phydev);
1418
1419 priv->cur_speed = new_speed;
1420 priv->cur_duplex = phydev->duplex;
1421 priv->rx_pause = rx_pause;
1422 priv->tx_pause = tx_pause;
1423
1424 /* Link is down, do nothing else */
1425 if (!new_speed)
1426 return;
1427
1428 /* Disable all interrupts */
1429 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1430
1431 /* Release phy lock to allow ftgmac100_reset to aquire it, keeping lock
1432 * order consistent to prevent dead lock.
1433 */
1434 if (netdev->phydev)
1435 mutex_unlock(&netdev->phydev->lock);
1436
1437 ftgmac100_reset(priv);
1438
1439 if (netdev->phydev)
1440 mutex_lock(&netdev->phydev->lock);
1441
1442}
1443
1444static int ftgmac100_mii_probe(struct net_device *netdev)
1445{
1446 struct ftgmac100 *priv = netdev_priv(netdev);
1447 struct platform_device *pdev = to_platform_device(priv->dev);
1448 struct device_node *np = pdev->dev.of_node;
1449 struct phy_device *phydev;
1450 phy_interface_t phy_intf;
1451 int err;
1452
1453 /* Default to RGMII. It's a gigabit part after all */
1454 err = of_get_phy_mode(np, &phy_intf);
1455 if (err)
1456 phy_intf = PHY_INTERFACE_MODE_RGMII;
1457
1458 /* Aspeed only supports these. I don't know about other IP
1459 * block vendors so I'm going to just let them through for
1460 * now. Note that this is only a warning if for some obscure
1461 * reason the DT really means to lie about it or it's a newer
1462 * part we don't know about.
1463 *
1464 * On the Aspeed SoC there are additionally straps and SCU
1465 * control bits that could tell us what the interface is
1466 * (or allow us to configure it while the IP block is held
1467 * in reset). For now I chose to keep this driver away from
1468 * those SoC specific bits and assume the device-tree is
1469 * right and the SCU has been configured properly by pinmux
1470 * or the firmware.
1471 */
1472 if (priv->is_aspeed && !(phy_interface_mode_is_rgmii(phy_intf))) {
1473 netdev_warn(netdev,
1474 "Unsupported PHY mode %s !\n",
1475 phy_modes(phy_intf));
1476 }
1477
1478 phydev = phy_find_first(priv->mii_bus);
1479 if (!phydev) {
1480 netdev_info(netdev, "%s: no PHY found\n", netdev->name);
1481 return -ENODEV;
1482 }
1483
1484 phydev = phy_connect(netdev, phydev_name(phydev),
1485 &ftgmac100_adjust_link, phy_intf);
1486
1487 if (IS_ERR(phydev)) {
1488 netdev_err(netdev, "%s: Could not attach to PHY\n", netdev->name);
1489 return PTR_ERR(phydev);
1490 }
1491
1492 /* Indicate that we support PAUSE frames (see comment in
1493 * Documentation/networking/phy.rst)
1494 */
1495 phy_support_asym_pause(phydev);
1496
1497 /* Display what we found */
1498 phy_attached_info(phydev);
1499
1500 return 0;
1501}
1502
1503static int ftgmac100_open(struct net_device *netdev)
1504{
1505 struct ftgmac100 *priv = netdev_priv(netdev);
1506 int err;
1507
1508 /* Allocate ring buffers */
1509 err = ftgmac100_alloc_rings(priv);
1510 if (err) {
1511 netdev_err(netdev, "Failed to allocate descriptors\n");
1512 return err;
1513 }
1514
1515 /* When using NC-SI we force the speed to 100Mbit/s full duplex,
1516 *
1517 * Otherwise we leave it set to 0 (no link), the link
1518 * message from the PHY layer will handle setting it up to
1519 * something else if needed.
1520 */
1521 if (priv->use_ncsi) {
1522 priv->cur_duplex = DUPLEX_FULL;
1523 priv->cur_speed = SPEED_100;
1524 } else {
1525 priv->cur_duplex = 0;
1526 priv->cur_speed = 0;
1527 }
1528
1529 /* Reset the hardware */
1530 err = ftgmac100_reset_and_config_mac(priv);
1531 if (err)
1532 goto err_hw;
1533
1534 /* Initialize NAPI */
1535 netif_napi_add(netdev, &priv->napi, ftgmac100_poll);
1536
1537 /* Grab our interrupt */
1538 err = request_irq(netdev->irq, ftgmac100_interrupt, 0, netdev->name, netdev);
1539 if (err) {
1540 netdev_err(netdev, "failed to request irq %d\n", netdev->irq);
1541 goto err_irq;
1542 }
1543
1544 /* Start things up */
1545 err = ftgmac100_init_all(priv, false);
1546 if (err) {
1547 netdev_err(netdev, "Failed to allocate packet buffers\n");
1548 goto err_alloc;
1549 }
1550
1551 if (netdev->phydev) {
1552 /* If we have a PHY, start polling */
1553 phy_start(netdev->phydev);
1554 }
1555 if (priv->use_ncsi) {
1556 /* If using NC-SI, set our carrier on and start the stack */
1557 netif_carrier_on(netdev);
1558
1559 /* Start the NCSI device */
1560 err = ncsi_start_dev(priv->ndev);
1561 if (err)
1562 goto err_ncsi;
1563 }
1564
1565 return 0;
1566
1567err_ncsi:
1568 phy_stop(netdev->phydev);
1569 napi_disable(&priv->napi);
1570 netif_stop_queue(netdev);
1571err_alloc:
1572 ftgmac100_free_buffers(priv);
1573 free_irq(netdev->irq, netdev);
1574err_irq:
1575 netif_napi_del(&priv->napi);
1576err_hw:
1577 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1578 ftgmac100_free_rings(priv);
1579 return err;
1580}
1581
1582static int ftgmac100_stop(struct net_device *netdev)
1583{
1584 struct ftgmac100 *priv = netdev_priv(netdev);
1585
1586 /* Note about the reset task: We are called with the rtnl lock
1587 * held, so we are synchronized against the core of the reset
1588 * task. We must not try to synchronously cancel it otherwise
1589 * we can deadlock. But since it will test for netif_running()
1590 * which has already been cleared by the net core, we don't
1591 * anything special to do.
1592 */
1593
1594 /* disable all interrupts */
1595 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1596
1597 netif_stop_queue(netdev);
1598 napi_disable(&priv->napi);
1599 netif_napi_del(&priv->napi);
1600 if (netdev->phydev)
1601 phy_stop(netdev->phydev);
1602 if (priv->use_ncsi)
1603 ncsi_stop_dev(priv->ndev);
1604
1605 ftgmac100_stop_hw(priv);
1606 free_irq(netdev->irq, netdev);
1607 ftgmac100_free_buffers(priv);
1608 ftgmac100_free_rings(priv);
1609
1610 return 0;
1611}
1612
1613static void ftgmac100_tx_timeout(struct net_device *netdev, unsigned int txqueue)
1614{
1615 struct ftgmac100 *priv = netdev_priv(netdev);
1616
1617 /* Disable all interrupts */
1618 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1619
1620 /* Do the reset outside of interrupt context */
1621 schedule_work(&priv->reset_task);
1622}
1623
1624static int ftgmac100_set_features(struct net_device *netdev,
1625 netdev_features_t features)
1626{
1627 struct ftgmac100 *priv = netdev_priv(netdev);
1628 netdev_features_t changed = netdev->features ^ features;
1629
1630 if (!netif_running(netdev))
1631 return 0;
1632
1633 /* Update the vlan filtering bit */
1634 if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
1635 u32 maccr;
1636
1637 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR);
1638 if (priv->netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
1639 maccr |= FTGMAC100_MACCR_RM_VLAN;
1640 else
1641 maccr &= ~FTGMAC100_MACCR_RM_VLAN;
1642 iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR);
1643 }
1644
1645 return 0;
1646}
1647
1648#ifdef CONFIG_NET_POLL_CONTROLLER
1649static void ftgmac100_poll_controller(struct net_device *netdev)
1650{
1651 unsigned long flags;
1652
1653 local_irq_save(flags);
1654 ftgmac100_interrupt(netdev->irq, netdev);
1655 local_irq_restore(flags);
1656}
1657#endif
1658
1659static const struct net_device_ops ftgmac100_netdev_ops = {
1660 .ndo_open = ftgmac100_open,
1661 .ndo_stop = ftgmac100_stop,
1662 .ndo_start_xmit = ftgmac100_hard_start_xmit,
1663 .ndo_set_mac_address = ftgmac100_set_mac_addr,
1664 .ndo_validate_addr = eth_validate_addr,
1665 .ndo_eth_ioctl = phy_do_ioctl,
1666 .ndo_tx_timeout = ftgmac100_tx_timeout,
1667 .ndo_set_rx_mode = ftgmac100_set_rx_mode,
1668 .ndo_set_features = ftgmac100_set_features,
1669#ifdef CONFIG_NET_POLL_CONTROLLER
1670 .ndo_poll_controller = ftgmac100_poll_controller,
1671#endif
1672 .ndo_vlan_rx_add_vid = ncsi_vlan_rx_add_vid,
1673 .ndo_vlan_rx_kill_vid = ncsi_vlan_rx_kill_vid,
1674};
1675
1676static int ftgmac100_setup_mdio(struct net_device *netdev)
1677{
1678 struct ftgmac100 *priv = netdev_priv(netdev);
1679 struct platform_device *pdev = to_platform_device(priv->dev);
1680 struct device_node *np = pdev->dev.of_node;
1681 struct device_node *mdio_np;
1682 int i, err = 0;
1683 u32 reg;
1684
1685 /* initialize mdio bus */
1686 priv->mii_bus = mdiobus_alloc();
1687 if (!priv->mii_bus)
1688 return -EIO;
1689
1690 if (of_device_is_compatible(np, "aspeed,ast2400-mac") ||
1691 of_device_is_compatible(np, "aspeed,ast2500-mac")) {
1692 /* The AST2600 has a separate MDIO controller */
1693
1694 /* For the AST2400 and AST2500 this driver only supports the
1695 * old MDIO interface
1696 */
1697 reg = ioread32(priv->base + FTGMAC100_OFFSET_REVR);
1698 reg &= ~FTGMAC100_REVR_NEW_MDIO_INTERFACE;
1699 iowrite32(reg, priv->base + FTGMAC100_OFFSET_REVR);
1700 }
1701
1702 priv->mii_bus->name = "ftgmac100_mdio";
1703 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%d",
1704 pdev->name, pdev->id);
1705 priv->mii_bus->parent = priv->dev;
1706 priv->mii_bus->priv = priv->netdev;
1707 priv->mii_bus->read = ftgmac100_mdiobus_read;
1708 priv->mii_bus->write = ftgmac100_mdiobus_write;
1709
1710 for (i = 0; i < PHY_MAX_ADDR; i++)
1711 priv->mii_bus->irq[i] = PHY_POLL;
1712
1713 mdio_np = of_get_child_by_name(np, "mdio");
1714
1715 err = of_mdiobus_register(priv->mii_bus, mdio_np);
1716 if (err) {
1717 dev_err(priv->dev, "Cannot register MDIO bus!\n");
1718 goto err_register_mdiobus;
1719 }
1720
1721 of_node_put(mdio_np);
1722
1723 return 0;
1724
1725err_register_mdiobus:
1726 mdiobus_free(priv->mii_bus);
1727 return err;
1728}
1729
1730static void ftgmac100_phy_disconnect(struct net_device *netdev)
1731{
1732 struct ftgmac100 *priv = netdev_priv(netdev);
1733
1734 if (!netdev->phydev)
1735 return;
1736
1737 phy_disconnect(netdev->phydev);
1738 if (of_phy_is_fixed_link(priv->dev->of_node))
1739 of_phy_deregister_fixed_link(priv->dev->of_node);
1740
1741 if (priv->use_ncsi)
1742 fixed_phy_unregister(netdev->phydev);
1743}
1744
1745static void ftgmac100_destroy_mdio(struct net_device *netdev)
1746{
1747 struct ftgmac100 *priv = netdev_priv(netdev);
1748
1749 if (!priv->mii_bus)
1750 return;
1751
1752 mdiobus_unregister(priv->mii_bus);
1753 mdiobus_free(priv->mii_bus);
1754}
1755
1756static void ftgmac100_ncsi_handler(struct ncsi_dev *nd)
1757{
1758 if (unlikely(nd->state != ncsi_dev_state_functional))
1759 return;
1760
1761 netdev_dbg(nd->dev, "NCSI interface %s\n",
1762 nd->link_up ? "up" : "down");
1763}
1764
1765static int ftgmac100_setup_clk(struct ftgmac100 *priv)
1766{
1767 struct clk *clk;
1768 int rc;
1769
1770 clk = devm_clk_get(priv->dev, NULL /* MACCLK */);
1771 if (IS_ERR(clk))
1772 return PTR_ERR(clk);
1773 priv->clk = clk;
1774 rc = clk_prepare_enable(priv->clk);
1775 if (rc)
1776 return rc;
1777
1778 /* Aspeed specifies a 100MHz clock is required for up to
1779 * 1000Mbit link speeds. As NCSI is limited to 100Mbit, 25MHz
1780 * is sufficient
1781 */
1782 rc = clk_set_rate(priv->clk, priv->use_ncsi ? FTGMAC_25MHZ :
1783 FTGMAC_100MHZ);
1784 if (rc)
1785 goto cleanup_clk;
1786
1787 /* RCLK is for RMII, typically used for NCSI. Optional because it's not
1788 * necessary if it's the AST2400 MAC, or the MAC is configured for
1789 * RGMII, or the controller is not an ASPEED-based controller.
1790 */
1791 priv->rclk = devm_clk_get_optional(priv->dev, "RCLK");
1792 rc = clk_prepare_enable(priv->rclk);
1793 if (!rc)
1794 return 0;
1795
1796cleanup_clk:
1797 clk_disable_unprepare(priv->clk);
1798
1799 return rc;
1800}
1801
1802static bool ftgmac100_has_child_node(struct device_node *np, const char *name)
1803{
1804 struct device_node *child_np = of_get_child_by_name(np, name);
1805 bool ret = false;
1806
1807 if (child_np) {
1808 ret = true;
1809 of_node_put(child_np);
1810 }
1811
1812 return ret;
1813}
1814
1815static int ftgmac100_probe(struct platform_device *pdev)
1816{
1817 struct resource *res;
1818 int irq;
1819 struct net_device *netdev;
1820 struct phy_device *phydev;
1821 struct ftgmac100 *priv;
1822 struct device_node *np;
1823 int err = 0;
1824
1825 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1826 if (!res)
1827 return -ENXIO;
1828
1829 irq = platform_get_irq(pdev, 0);
1830 if (irq < 0)
1831 return irq;
1832
1833 /* setup net_device */
1834 netdev = alloc_etherdev(sizeof(*priv));
1835 if (!netdev) {
1836 err = -ENOMEM;
1837 goto err_alloc_etherdev;
1838 }
1839
1840 SET_NETDEV_DEV(netdev, &pdev->dev);
1841
1842 netdev->ethtool_ops = &ftgmac100_ethtool_ops;
1843 netdev->netdev_ops = &ftgmac100_netdev_ops;
1844 netdev->watchdog_timeo = 5 * HZ;
1845
1846 platform_set_drvdata(pdev, netdev);
1847
1848 /* setup private data */
1849 priv = netdev_priv(netdev);
1850 priv->netdev = netdev;
1851 priv->dev = &pdev->dev;
1852 INIT_WORK(&priv->reset_task, ftgmac100_reset_task);
1853
1854 /* map io memory */
1855 priv->res = request_mem_region(res->start, resource_size(res),
1856 dev_name(&pdev->dev));
1857 if (!priv->res) {
1858 dev_err(&pdev->dev, "Could not reserve memory region\n");
1859 err = -ENOMEM;
1860 goto err_req_mem;
1861 }
1862
1863 priv->base = ioremap(res->start, resource_size(res));
1864 if (!priv->base) {
1865 dev_err(&pdev->dev, "Failed to ioremap ethernet registers\n");
1866 err = -EIO;
1867 goto err_ioremap;
1868 }
1869
1870 netdev->irq = irq;
1871
1872 /* Enable pause */
1873 priv->tx_pause = true;
1874 priv->rx_pause = true;
1875 priv->aneg_pause = true;
1876
1877 /* MAC address from chip or random one */
1878 err = ftgmac100_initial_mac(priv);
1879 if (err)
1880 goto err_phy_connect;
1881
1882 np = pdev->dev.of_node;
1883 if (np && (of_device_is_compatible(np, "aspeed,ast2400-mac") ||
1884 of_device_is_compatible(np, "aspeed,ast2500-mac") ||
1885 of_device_is_compatible(np, "aspeed,ast2600-mac"))) {
1886 priv->rxdes0_edorr_mask = BIT(30);
1887 priv->txdes0_edotr_mask = BIT(30);
1888 priv->is_aspeed = true;
1889 } else {
1890 priv->rxdes0_edorr_mask = BIT(15);
1891 priv->txdes0_edotr_mask = BIT(15);
1892 }
1893
1894 if (np && of_get_property(np, "use-ncsi", NULL)) {
1895 if (!IS_ENABLED(CONFIG_NET_NCSI)) {
1896 dev_err(&pdev->dev, "NCSI stack not enabled\n");
1897 err = -EINVAL;
1898 goto err_phy_connect;
1899 }
1900
1901 dev_info(&pdev->dev, "Using NCSI interface\n");
1902 priv->use_ncsi = true;
1903 priv->ndev = ncsi_register_dev(netdev, ftgmac100_ncsi_handler);
1904 if (!priv->ndev) {
1905 err = -EINVAL;
1906 goto err_phy_connect;
1907 }
1908
1909 phydev = fixed_phy_register(PHY_POLL, &ncsi_phy_status, np);
1910 if (IS_ERR(phydev)) {
1911 dev_err(&pdev->dev, "failed to register fixed PHY device\n");
1912 err = PTR_ERR(phydev);
1913 goto err_phy_connect;
1914 }
1915 err = phy_connect_direct(netdev, phydev, ftgmac100_adjust_link,
1916 PHY_INTERFACE_MODE_RMII);
1917 if (err) {
1918 dev_err(&pdev->dev, "Connecting PHY failed\n");
1919 goto err_phy_connect;
1920 }
1921 } else if (np && (of_phy_is_fixed_link(np) ||
1922 of_get_property(np, "phy-handle", NULL))) {
1923 struct phy_device *phy;
1924
1925 /* Support "mdio"/"phy" child nodes for ast2400/2500 with
1926 * an embedded MDIO controller. Automatically scan the DTS for
1927 * available PHYs and register them.
1928 */
1929 if (of_get_property(np, "phy-handle", NULL) &&
1930 (of_device_is_compatible(np, "aspeed,ast2400-mac") ||
1931 of_device_is_compatible(np, "aspeed,ast2500-mac"))) {
1932 err = ftgmac100_setup_mdio(netdev);
1933 if (err)
1934 goto err_setup_mdio;
1935 }
1936
1937 phy = of_phy_get_and_connect(priv->netdev, np,
1938 &ftgmac100_adjust_link);
1939 if (!phy) {
1940 dev_err(&pdev->dev, "Failed to connect to phy\n");
1941 err = -EINVAL;
1942 goto err_phy_connect;
1943 }
1944
1945 /* Indicate that we support PAUSE frames (see comment in
1946 * Documentation/networking/phy.rst)
1947 */
1948 phy_support_asym_pause(phy);
1949
1950 /* Display what we found */
1951 phy_attached_info(phy);
1952 } else if (np && !ftgmac100_has_child_node(np, "mdio")) {
1953 /* Support legacy ASPEED devicetree descriptions that decribe a
1954 * MAC with an embedded MDIO controller but have no "mdio"
1955 * child node. Automatically scan the MDIO bus for available
1956 * PHYs.
1957 */
1958 priv->use_ncsi = false;
1959 err = ftgmac100_setup_mdio(netdev);
1960 if (err)
1961 goto err_setup_mdio;
1962
1963 err = ftgmac100_mii_probe(netdev);
1964 if (err) {
1965 dev_err(priv->dev, "MII probe failed!\n");
1966 goto err_ncsi_dev;
1967 }
1968
1969 }
1970
1971 if (priv->is_aspeed) {
1972 err = ftgmac100_setup_clk(priv);
1973 if (err)
1974 goto err_phy_connect;
1975
1976 /* Disable ast2600 problematic HW arbitration */
1977 if (of_device_is_compatible(np, "aspeed,ast2600-mac"))
1978 iowrite32(FTGMAC100_TM_DEFAULT,
1979 priv->base + FTGMAC100_OFFSET_TM);
1980 }
1981
1982 /* Default ring sizes */
1983 priv->rx_q_entries = priv->new_rx_q_entries = DEF_RX_QUEUE_ENTRIES;
1984 priv->tx_q_entries = priv->new_tx_q_entries = DEF_TX_QUEUE_ENTRIES;
1985
1986 /* Base feature set */
1987 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_HW_CSUM |
1988 NETIF_F_GRO | NETIF_F_SG | NETIF_F_HW_VLAN_CTAG_RX |
1989 NETIF_F_HW_VLAN_CTAG_TX;
1990
1991 if (priv->use_ncsi)
1992 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
1993
1994 /* AST2400 doesn't have working HW checksum generation */
1995 if (np && (of_device_is_compatible(np, "aspeed,ast2400-mac")))
1996 netdev->hw_features &= ~NETIF_F_HW_CSUM;
1997
1998 /* AST2600 tx checksum with NCSI is broken */
1999 if (priv->use_ncsi && of_device_is_compatible(np, "aspeed,ast2600-mac"))
2000 netdev->hw_features &= ~NETIF_F_HW_CSUM;
2001
2002 if (np && of_get_property(np, "no-hw-checksum", NULL))
2003 netdev->hw_features &= ~(NETIF_F_HW_CSUM | NETIF_F_RXCSUM);
2004 netdev->features |= netdev->hw_features;
2005
2006 /* register network device */
2007 err = register_netdev(netdev);
2008 if (err) {
2009 dev_err(&pdev->dev, "Failed to register netdev\n");
2010 goto err_register_netdev;
2011 }
2012
2013 netdev_info(netdev, "irq %d, mapped at %p\n", netdev->irq, priv->base);
2014
2015 return 0;
2016
2017err_register_netdev:
2018 clk_disable_unprepare(priv->rclk);
2019 clk_disable_unprepare(priv->clk);
2020err_phy_connect:
2021 ftgmac100_phy_disconnect(netdev);
2022err_ncsi_dev:
2023 if (priv->ndev)
2024 ncsi_unregister_dev(priv->ndev);
2025 ftgmac100_destroy_mdio(netdev);
2026err_setup_mdio:
2027 iounmap(priv->base);
2028err_ioremap:
2029 release_resource(priv->res);
2030err_req_mem:
2031 free_netdev(netdev);
2032err_alloc_etherdev:
2033 return err;
2034}
2035
2036static void ftgmac100_remove(struct platform_device *pdev)
2037{
2038 struct net_device *netdev;
2039 struct ftgmac100 *priv;
2040
2041 netdev = platform_get_drvdata(pdev);
2042 priv = netdev_priv(netdev);
2043
2044 if (priv->ndev)
2045 ncsi_unregister_dev(priv->ndev);
2046 unregister_netdev(netdev);
2047
2048 clk_disable_unprepare(priv->rclk);
2049 clk_disable_unprepare(priv->clk);
2050
2051 /* There's a small chance the reset task will have been re-queued,
2052 * during stop, make sure it's gone before we free the structure.
2053 */
2054 cancel_work_sync(&priv->reset_task);
2055
2056 ftgmac100_phy_disconnect(netdev);
2057 ftgmac100_destroy_mdio(netdev);
2058
2059 iounmap(priv->base);
2060 release_resource(priv->res);
2061
2062 netif_napi_del(&priv->napi);
2063 free_netdev(netdev);
2064}
2065
2066static const struct of_device_id ftgmac100_of_match[] = {
2067 { .compatible = "faraday,ftgmac100" },
2068 { }
2069};
2070MODULE_DEVICE_TABLE(of, ftgmac100_of_match);
2071
2072static struct platform_driver ftgmac100_driver = {
2073 .probe = ftgmac100_probe,
2074 .remove = ftgmac100_remove,
2075 .driver = {
2076 .name = DRV_NAME,
2077 .of_match_table = ftgmac100_of_match,
2078 },
2079};
2080module_platform_driver(ftgmac100_driver);
2081
2082MODULE_AUTHOR("Po-Yu Chuang <ratbert@faraday-tech.com>");
2083MODULE_DESCRIPTION("FTGMAC100 driver");
2084MODULE_LICENSE("GPL");
1/*
2 * Faraday FTGMAC100 Gigabit Ethernet
3 *
4 * (C) Copyright 2009-2011 Faraday Technology
5 * Po-Yu Chuang <ratbert@faraday-tech.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
23
24#include <linux/dma-mapping.h>
25#include <linux/etherdevice.h>
26#include <linux/ethtool.h>
27#include <linux/init.h>
28#include <linux/interrupt.h>
29#include <linux/io.h>
30#include <linux/module.h>
31#include <linux/netdevice.h>
32#include <linux/phy.h>
33#include <linux/platform_device.h>
34#include <net/ip.h>
35
36#include "ftgmac100.h"
37
38#define DRV_NAME "ftgmac100"
39#define DRV_VERSION "0.7"
40
41#define RX_QUEUE_ENTRIES 256 /* must be power of 2 */
42#define TX_QUEUE_ENTRIES 512 /* must be power of 2 */
43
44#define MAX_PKT_SIZE 1518
45#define RX_BUF_SIZE PAGE_SIZE /* must be smaller than 0x3fff */
46
47/******************************************************************************
48 * private data
49 *****************************************************************************/
50struct ftgmac100_descs {
51 struct ftgmac100_rxdes rxdes[RX_QUEUE_ENTRIES];
52 struct ftgmac100_txdes txdes[TX_QUEUE_ENTRIES];
53};
54
55struct ftgmac100 {
56 struct resource *res;
57 void __iomem *base;
58 int irq;
59
60 struct ftgmac100_descs *descs;
61 dma_addr_t descs_dma_addr;
62
63 unsigned int rx_pointer;
64 unsigned int tx_clean_pointer;
65 unsigned int tx_pointer;
66 unsigned int tx_pending;
67
68 spinlock_t tx_lock;
69
70 struct net_device *netdev;
71 struct device *dev;
72 struct napi_struct napi;
73
74 struct mii_bus *mii_bus;
75 int phy_irq[PHY_MAX_ADDR];
76 struct phy_device *phydev;
77 int old_speed;
78};
79
80static int ftgmac100_alloc_rx_page(struct ftgmac100 *priv,
81 struct ftgmac100_rxdes *rxdes, gfp_t gfp);
82
83/******************************************************************************
84 * internal functions (hardware register access)
85 *****************************************************************************/
86#define INT_MASK_ALL_ENABLED (FTGMAC100_INT_RPKT_LOST | \
87 FTGMAC100_INT_XPKT_ETH | \
88 FTGMAC100_INT_XPKT_LOST | \
89 FTGMAC100_INT_AHB_ERR | \
90 FTGMAC100_INT_PHYSTS_CHG | \
91 FTGMAC100_INT_RPKT_BUF | \
92 FTGMAC100_INT_NO_RXBUF)
93
94static void ftgmac100_set_rx_ring_base(struct ftgmac100 *priv, dma_addr_t addr)
95{
96 iowrite32(addr, priv->base + FTGMAC100_OFFSET_RXR_BADR);
97}
98
99static void ftgmac100_set_rx_buffer_size(struct ftgmac100 *priv,
100 unsigned int size)
101{
102 size = FTGMAC100_RBSR_SIZE(size);
103 iowrite32(size, priv->base + FTGMAC100_OFFSET_RBSR);
104}
105
106static void ftgmac100_set_normal_prio_tx_ring_base(struct ftgmac100 *priv,
107 dma_addr_t addr)
108{
109 iowrite32(addr, priv->base + FTGMAC100_OFFSET_NPTXR_BADR);
110}
111
112static void ftgmac100_txdma_normal_prio_start_polling(struct ftgmac100 *priv)
113{
114 iowrite32(1, priv->base + FTGMAC100_OFFSET_NPTXPD);
115}
116
117static int ftgmac100_reset_hw(struct ftgmac100 *priv)
118{
119 struct net_device *netdev = priv->netdev;
120 int i;
121
122 /* NOTE: reset clears all registers */
123 iowrite32(FTGMAC100_MACCR_SW_RST, priv->base + FTGMAC100_OFFSET_MACCR);
124 for (i = 0; i < 5; i++) {
125 unsigned int maccr;
126
127 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR);
128 if (!(maccr & FTGMAC100_MACCR_SW_RST))
129 return 0;
130
131 udelay(1000);
132 }
133
134 netdev_err(netdev, "software reset failed\n");
135 return -EIO;
136}
137
138static void ftgmac100_set_mac(struct ftgmac100 *priv, const unsigned char *mac)
139{
140 unsigned int maddr = mac[0] << 8 | mac[1];
141 unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5];
142
143 iowrite32(maddr, priv->base + FTGMAC100_OFFSET_MAC_MADR);
144 iowrite32(laddr, priv->base + FTGMAC100_OFFSET_MAC_LADR);
145}
146
147static void ftgmac100_init_hw(struct ftgmac100 *priv)
148{
149 /* setup ring buffer base registers */
150 ftgmac100_set_rx_ring_base(priv,
151 priv->descs_dma_addr +
152 offsetof(struct ftgmac100_descs, rxdes));
153 ftgmac100_set_normal_prio_tx_ring_base(priv,
154 priv->descs_dma_addr +
155 offsetof(struct ftgmac100_descs, txdes));
156
157 ftgmac100_set_rx_buffer_size(priv, RX_BUF_SIZE);
158
159 iowrite32(FTGMAC100_APTC_RXPOLL_CNT(1), priv->base + FTGMAC100_OFFSET_APTC);
160
161 ftgmac100_set_mac(priv, priv->netdev->dev_addr);
162}
163
164#define MACCR_ENABLE_ALL (FTGMAC100_MACCR_TXDMA_EN | \
165 FTGMAC100_MACCR_RXDMA_EN | \
166 FTGMAC100_MACCR_TXMAC_EN | \
167 FTGMAC100_MACCR_RXMAC_EN | \
168 FTGMAC100_MACCR_FULLDUP | \
169 FTGMAC100_MACCR_CRC_APD | \
170 FTGMAC100_MACCR_RX_RUNT | \
171 FTGMAC100_MACCR_RX_BROADPKT)
172
173static void ftgmac100_start_hw(struct ftgmac100 *priv, int speed)
174{
175 int maccr = MACCR_ENABLE_ALL;
176
177 switch (speed) {
178 default:
179 case 10:
180 break;
181
182 case 100:
183 maccr |= FTGMAC100_MACCR_FAST_MODE;
184 break;
185
186 case 1000:
187 maccr |= FTGMAC100_MACCR_GIGA_MODE;
188 break;
189 }
190
191 iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR);
192}
193
194static void ftgmac100_stop_hw(struct ftgmac100 *priv)
195{
196 iowrite32(0, priv->base + FTGMAC100_OFFSET_MACCR);
197}
198
199/******************************************************************************
200 * internal functions (receive descriptor)
201 *****************************************************************************/
202static bool ftgmac100_rxdes_first_segment(struct ftgmac100_rxdes *rxdes)
203{
204 return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_FRS);
205}
206
207static bool ftgmac100_rxdes_last_segment(struct ftgmac100_rxdes *rxdes)
208{
209 return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_LRS);
210}
211
212static bool ftgmac100_rxdes_packet_ready(struct ftgmac100_rxdes *rxdes)
213{
214 return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RXPKT_RDY);
215}
216
217static void ftgmac100_rxdes_set_dma_own(struct ftgmac100_rxdes *rxdes)
218{
219 /* clear status bits */
220 rxdes->rxdes0 &= cpu_to_le32(FTGMAC100_RXDES0_EDORR);
221}
222
223static bool ftgmac100_rxdes_rx_error(struct ftgmac100_rxdes *rxdes)
224{
225 return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RX_ERR);
226}
227
228static bool ftgmac100_rxdes_crc_error(struct ftgmac100_rxdes *rxdes)
229{
230 return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_CRC_ERR);
231}
232
233static bool ftgmac100_rxdes_frame_too_long(struct ftgmac100_rxdes *rxdes)
234{
235 return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_FTL);
236}
237
238static bool ftgmac100_rxdes_runt(struct ftgmac100_rxdes *rxdes)
239{
240 return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RUNT);
241}
242
243static bool ftgmac100_rxdes_odd_nibble(struct ftgmac100_rxdes *rxdes)
244{
245 return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RX_ODD_NB);
246}
247
248static unsigned int ftgmac100_rxdes_data_length(struct ftgmac100_rxdes *rxdes)
249{
250 return le32_to_cpu(rxdes->rxdes0) & FTGMAC100_RXDES0_VDBC;
251}
252
253static bool ftgmac100_rxdes_multicast(struct ftgmac100_rxdes *rxdes)
254{
255 return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_MULTICAST);
256}
257
258static void ftgmac100_rxdes_set_end_of_ring(struct ftgmac100_rxdes *rxdes)
259{
260 rxdes->rxdes0 |= cpu_to_le32(FTGMAC100_RXDES0_EDORR);
261}
262
263static void ftgmac100_rxdes_set_dma_addr(struct ftgmac100_rxdes *rxdes,
264 dma_addr_t addr)
265{
266 rxdes->rxdes3 = cpu_to_le32(addr);
267}
268
269static dma_addr_t ftgmac100_rxdes_get_dma_addr(struct ftgmac100_rxdes *rxdes)
270{
271 return le32_to_cpu(rxdes->rxdes3);
272}
273
274static bool ftgmac100_rxdes_is_tcp(struct ftgmac100_rxdes *rxdes)
275{
276 return (rxdes->rxdes1 & cpu_to_le32(FTGMAC100_RXDES1_PROT_MASK)) ==
277 cpu_to_le32(FTGMAC100_RXDES1_PROT_TCPIP);
278}
279
280static bool ftgmac100_rxdes_is_udp(struct ftgmac100_rxdes *rxdes)
281{
282 return (rxdes->rxdes1 & cpu_to_le32(FTGMAC100_RXDES1_PROT_MASK)) ==
283 cpu_to_le32(FTGMAC100_RXDES1_PROT_UDPIP);
284}
285
286static bool ftgmac100_rxdes_tcpcs_err(struct ftgmac100_rxdes *rxdes)
287{
288 return rxdes->rxdes1 & cpu_to_le32(FTGMAC100_RXDES1_TCP_CHKSUM_ERR);
289}
290
291static bool ftgmac100_rxdes_udpcs_err(struct ftgmac100_rxdes *rxdes)
292{
293 return rxdes->rxdes1 & cpu_to_le32(FTGMAC100_RXDES1_UDP_CHKSUM_ERR);
294}
295
296static bool ftgmac100_rxdes_ipcs_err(struct ftgmac100_rxdes *rxdes)
297{
298 return rxdes->rxdes1 & cpu_to_le32(FTGMAC100_RXDES1_IP_CHKSUM_ERR);
299}
300
301/*
302 * rxdes2 is not used by hardware. We use it to keep track of page.
303 * Since hardware does not touch it, we can skip cpu_to_le32()/le32_to_cpu().
304 */
305static void ftgmac100_rxdes_set_page(struct ftgmac100_rxdes *rxdes, struct page *page)
306{
307 rxdes->rxdes2 = (unsigned int)page;
308}
309
310static struct page *ftgmac100_rxdes_get_page(struct ftgmac100_rxdes *rxdes)
311{
312 return (struct page *)rxdes->rxdes2;
313}
314
315/******************************************************************************
316 * internal functions (receive)
317 *****************************************************************************/
318static int ftgmac100_next_rx_pointer(int pointer)
319{
320 return (pointer + 1) & (RX_QUEUE_ENTRIES - 1);
321}
322
323static void ftgmac100_rx_pointer_advance(struct ftgmac100 *priv)
324{
325 priv->rx_pointer = ftgmac100_next_rx_pointer(priv->rx_pointer);
326}
327
328static struct ftgmac100_rxdes *ftgmac100_current_rxdes(struct ftgmac100 *priv)
329{
330 return &priv->descs->rxdes[priv->rx_pointer];
331}
332
333static struct ftgmac100_rxdes *
334ftgmac100_rx_locate_first_segment(struct ftgmac100 *priv)
335{
336 struct ftgmac100_rxdes *rxdes = ftgmac100_current_rxdes(priv);
337
338 while (ftgmac100_rxdes_packet_ready(rxdes)) {
339 if (ftgmac100_rxdes_first_segment(rxdes))
340 return rxdes;
341
342 ftgmac100_rxdes_set_dma_own(rxdes);
343 ftgmac100_rx_pointer_advance(priv);
344 rxdes = ftgmac100_current_rxdes(priv);
345 }
346
347 return NULL;
348}
349
350static bool ftgmac100_rx_packet_error(struct ftgmac100 *priv,
351 struct ftgmac100_rxdes *rxdes)
352{
353 struct net_device *netdev = priv->netdev;
354 bool error = false;
355
356 if (unlikely(ftgmac100_rxdes_rx_error(rxdes))) {
357 if (net_ratelimit())
358 netdev_info(netdev, "rx err\n");
359
360 netdev->stats.rx_errors++;
361 error = true;
362 }
363
364 if (unlikely(ftgmac100_rxdes_crc_error(rxdes))) {
365 if (net_ratelimit())
366 netdev_info(netdev, "rx crc err\n");
367
368 netdev->stats.rx_crc_errors++;
369 error = true;
370 } else if (unlikely(ftgmac100_rxdes_ipcs_err(rxdes))) {
371 if (net_ratelimit())
372 netdev_info(netdev, "rx IP checksum err\n");
373
374 error = true;
375 }
376
377 if (unlikely(ftgmac100_rxdes_frame_too_long(rxdes))) {
378 if (net_ratelimit())
379 netdev_info(netdev, "rx frame too long\n");
380
381 netdev->stats.rx_length_errors++;
382 error = true;
383 } else if (unlikely(ftgmac100_rxdes_runt(rxdes))) {
384 if (net_ratelimit())
385 netdev_info(netdev, "rx runt\n");
386
387 netdev->stats.rx_length_errors++;
388 error = true;
389 } else if (unlikely(ftgmac100_rxdes_odd_nibble(rxdes))) {
390 if (net_ratelimit())
391 netdev_info(netdev, "rx odd nibble\n");
392
393 netdev->stats.rx_length_errors++;
394 error = true;
395 }
396
397 return error;
398}
399
400static void ftgmac100_rx_drop_packet(struct ftgmac100 *priv)
401{
402 struct net_device *netdev = priv->netdev;
403 struct ftgmac100_rxdes *rxdes = ftgmac100_current_rxdes(priv);
404 bool done = false;
405
406 if (net_ratelimit())
407 netdev_dbg(netdev, "drop packet %p\n", rxdes);
408
409 do {
410 if (ftgmac100_rxdes_last_segment(rxdes))
411 done = true;
412
413 ftgmac100_rxdes_set_dma_own(rxdes);
414 ftgmac100_rx_pointer_advance(priv);
415 rxdes = ftgmac100_current_rxdes(priv);
416 } while (!done && ftgmac100_rxdes_packet_ready(rxdes));
417
418 netdev->stats.rx_dropped++;
419}
420
421static bool ftgmac100_rx_packet(struct ftgmac100 *priv, int *processed)
422{
423 struct net_device *netdev = priv->netdev;
424 struct ftgmac100_rxdes *rxdes;
425 struct sk_buff *skb;
426 bool done = false;
427
428 rxdes = ftgmac100_rx_locate_first_segment(priv);
429 if (!rxdes)
430 return false;
431
432 if (unlikely(ftgmac100_rx_packet_error(priv, rxdes))) {
433 ftgmac100_rx_drop_packet(priv);
434 return true;
435 }
436
437 /* start processing */
438 skb = netdev_alloc_skb_ip_align(netdev, 128);
439 if (unlikely(!skb)) {
440 if (net_ratelimit())
441 netdev_err(netdev, "rx skb alloc failed\n");
442
443 ftgmac100_rx_drop_packet(priv);
444 return true;
445 }
446
447 if (unlikely(ftgmac100_rxdes_multicast(rxdes)))
448 netdev->stats.multicast++;
449
450 /*
451 * It seems that HW does checksum incorrectly with fragmented packets,
452 * so we are conservative here - if HW checksum error, let software do
453 * the checksum again.
454 */
455 if ((ftgmac100_rxdes_is_tcp(rxdes) && !ftgmac100_rxdes_tcpcs_err(rxdes)) ||
456 (ftgmac100_rxdes_is_udp(rxdes) && !ftgmac100_rxdes_udpcs_err(rxdes)))
457 skb->ip_summed = CHECKSUM_UNNECESSARY;
458
459 do {
460 dma_addr_t map = ftgmac100_rxdes_get_dma_addr(rxdes);
461 struct page *page = ftgmac100_rxdes_get_page(rxdes);
462 unsigned int size;
463
464 dma_unmap_page(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE);
465
466 size = ftgmac100_rxdes_data_length(rxdes);
467 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags, page, 0, size);
468
469 skb->len += size;
470 skb->data_len += size;
471 skb->truesize += PAGE_SIZE;
472
473 if (ftgmac100_rxdes_last_segment(rxdes))
474 done = true;
475
476 ftgmac100_alloc_rx_page(priv, rxdes, GFP_ATOMIC);
477
478 ftgmac100_rx_pointer_advance(priv);
479 rxdes = ftgmac100_current_rxdes(priv);
480 } while (!done);
481
482 if (skb->len <= 64)
483 skb->truesize -= PAGE_SIZE;
484 __pskb_pull_tail(skb, min(skb->len, 64U));
485 skb->protocol = eth_type_trans(skb, netdev);
486
487 netdev->stats.rx_packets++;
488 netdev->stats.rx_bytes += skb->len;
489
490 /* push packet to protocol stack */
491 napi_gro_receive(&priv->napi, skb);
492
493 (*processed)++;
494 return true;
495}
496
497/******************************************************************************
498 * internal functions (transmit descriptor)
499 *****************************************************************************/
500static void ftgmac100_txdes_reset(struct ftgmac100_txdes *txdes)
501{
502 /* clear all except end of ring bit */
503 txdes->txdes0 &= cpu_to_le32(FTGMAC100_TXDES0_EDOTR);
504 txdes->txdes1 = 0;
505 txdes->txdes2 = 0;
506 txdes->txdes3 = 0;
507}
508
509static bool ftgmac100_txdes_owned_by_dma(struct ftgmac100_txdes *txdes)
510{
511 return txdes->txdes0 & cpu_to_le32(FTGMAC100_TXDES0_TXDMA_OWN);
512}
513
514static void ftgmac100_txdes_set_dma_own(struct ftgmac100_txdes *txdes)
515{
516 /*
517 * Make sure dma own bit will not be set before any other
518 * descriptor fields.
519 */
520 wmb();
521 txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_TXDMA_OWN);
522}
523
524static void ftgmac100_txdes_set_end_of_ring(struct ftgmac100_txdes *txdes)
525{
526 txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_EDOTR);
527}
528
529static void ftgmac100_txdes_set_first_segment(struct ftgmac100_txdes *txdes)
530{
531 txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_FTS);
532}
533
534static void ftgmac100_txdes_set_last_segment(struct ftgmac100_txdes *txdes)
535{
536 txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_LTS);
537}
538
539static void ftgmac100_txdes_set_buffer_size(struct ftgmac100_txdes *txdes,
540 unsigned int len)
541{
542 txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_TXBUF_SIZE(len));
543}
544
545static void ftgmac100_txdes_set_txint(struct ftgmac100_txdes *txdes)
546{
547 txdes->txdes1 |= cpu_to_le32(FTGMAC100_TXDES1_TXIC);
548}
549
550static void ftgmac100_txdes_set_tcpcs(struct ftgmac100_txdes *txdes)
551{
552 txdes->txdes1 |= cpu_to_le32(FTGMAC100_TXDES1_TCP_CHKSUM);
553}
554
555static void ftgmac100_txdes_set_udpcs(struct ftgmac100_txdes *txdes)
556{
557 txdes->txdes1 |= cpu_to_le32(FTGMAC100_TXDES1_UDP_CHKSUM);
558}
559
560static void ftgmac100_txdes_set_ipcs(struct ftgmac100_txdes *txdes)
561{
562 txdes->txdes1 |= cpu_to_le32(FTGMAC100_TXDES1_IP_CHKSUM);
563}
564
565static void ftgmac100_txdes_set_dma_addr(struct ftgmac100_txdes *txdes,
566 dma_addr_t addr)
567{
568 txdes->txdes3 = cpu_to_le32(addr);
569}
570
571static dma_addr_t ftgmac100_txdes_get_dma_addr(struct ftgmac100_txdes *txdes)
572{
573 return le32_to_cpu(txdes->txdes3);
574}
575
576/*
577 * txdes2 is not used by hardware. We use it to keep track of socket buffer.
578 * Since hardware does not touch it, we can skip cpu_to_le32()/le32_to_cpu().
579 */
580static void ftgmac100_txdes_set_skb(struct ftgmac100_txdes *txdes,
581 struct sk_buff *skb)
582{
583 txdes->txdes2 = (unsigned int)skb;
584}
585
586static struct sk_buff *ftgmac100_txdes_get_skb(struct ftgmac100_txdes *txdes)
587{
588 return (struct sk_buff *)txdes->txdes2;
589}
590
591/******************************************************************************
592 * internal functions (transmit)
593 *****************************************************************************/
594static int ftgmac100_next_tx_pointer(int pointer)
595{
596 return (pointer + 1) & (TX_QUEUE_ENTRIES - 1);
597}
598
599static void ftgmac100_tx_pointer_advance(struct ftgmac100 *priv)
600{
601 priv->tx_pointer = ftgmac100_next_tx_pointer(priv->tx_pointer);
602}
603
604static void ftgmac100_tx_clean_pointer_advance(struct ftgmac100 *priv)
605{
606 priv->tx_clean_pointer = ftgmac100_next_tx_pointer(priv->tx_clean_pointer);
607}
608
609static struct ftgmac100_txdes *ftgmac100_current_txdes(struct ftgmac100 *priv)
610{
611 return &priv->descs->txdes[priv->tx_pointer];
612}
613
614static struct ftgmac100_txdes *
615ftgmac100_current_clean_txdes(struct ftgmac100 *priv)
616{
617 return &priv->descs->txdes[priv->tx_clean_pointer];
618}
619
620static bool ftgmac100_tx_complete_packet(struct ftgmac100 *priv)
621{
622 struct net_device *netdev = priv->netdev;
623 struct ftgmac100_txdes *txdes;
624 struct sk_buff *skb;
625 dma_addr_t map;
626
627 if (priv->tx_pending == 0)
628 return false;
629
630 txdes = ftgmac100_current_clean_txdes(priv);
631
632 if (ftgmac100_txdes_owned_by_dma(txdes))
633 return false;
634
635 skb = ftgmac100_txdes_get_skb(txdes);
636 map = ftgmac100_txdes_get_dma_addr(txdes);
637
638 netdev->stats.tx_packets++;
639 netdev->stats.tx_bytes += skb->len;
640
641 dma_unmap_single(priv->dev, map, skb_headlen(skb), DMA_TO_DEVICE);
642
643 dev_kfree_skb(skb);
644
645 ftgmac100_txdes_reset(txdes);
646
647 ftgmac100_tx_clean_pointer_advance(priv);
648
649 spin_lock(&priv->tx_lock);
650 priv->tx_pending--;
651 spin_unlock(&priv->tx_lock);
652 netif_wake_queue(netdev);
653
654 return true;
655}
656
657static void ftgmac100_tx_complete(struct ftgmac100 *priv)
658{
659 while (ftgmac100_tx_complete_packet(priv))
660 ;
661}
662
663static int ftgmac100_xmit(struct ftgmac100 *priv, struct sk_buff *skb,
664 dma_addr_t map)
665{
666 struct net_device *netdev = priv->netdev;
667 struct ftgmac100_txdes *txdes;
668 unsigned int len = (skb->len < ETH_ZLEN) ? ETH_ZLEN : skb->len;
669
670 txdes = ftgmac100_current_txdes(priv);
671 ftgmac100_tx_pointer_advance(priv);
672
673 /* setup TX descriptor */
674 ftgmac100_txdes_set_skb(txdes, skb);
675 ftgmac100_txdes_set_dma_addr(txdes, map);
676 ftgmac100_txdes_set_buffer_size(txdes, len);
677
678 ftgmac100_txdes_set_first_segment(txdes);
679 ftgmac100_txdes_set_last_segment(txdes);
680 ftgmac100_txdes_set_txint(txdes);
681 if (skb->ip_summed == CHECKSUM_PARTIAL) {
682 __be16 protocol = skb->protocol;
683
684 if (protocol == cpu_to_be16(ETH_P_IP)) {
685 u8 ip_proto = ip_hdr(skb)->protocol;
686
687 ftgmac100_txdes_set_ipcs(txdes);
688 if (ip_proto == IPPROTO_TCP)
689 ftgmac100_txdes_set_tcpcs(txdes);
690 else if (ip_proto == IPPROTO_UDP)
691 ftgmac100_txdes_set_udpcs(txdes);
692 }
693 }
694
695 spin_lock(&priv->tx_lock);
696 priv->tx_pending++;
697 if (priv->tx_pending == TX_QUEUE_ENTRIES)
698 netif_stop_queue(netdev);
699
700 /* start transmit */
701 ftgmac100_txdes_set_dma_own(txdes);
702 spin_unlock(&priv->tx_lock);
703
704 ftgmac100_txdma_normal_prio_start_polling(priv);
705
706 return NETDEV_TX_OK;
707}
708
709/******************************************************************************
710 * internal functions (buffer)
711 *****************************************************************************/
712static int ftgmac100_alloc_rx_page(struct ftgmac100 *priv,
713 struct ftgmac100_rxdes *rxdes, gfp_t gfp)
714{
715 struct net_device *netdev = priv->netdev;
716 struct page *page;
717 dma_addr_t map;
718
719 page = alloc_page(gfp);
720 if (!page) {
721 if (net_ratelimit())
722 netdev_err(netdev, "failed to allocate rx page\n");
723 return -ENOMEM;
724 }
725
726 map = dma_map_page(priv->dev, page, 0, RX_BUF_SIZE, DMA_FROM_DEVICE);
727 if (unlikely(dma_mapping_error(priv->dev, map))) {
728 if (net_ratelimit())
729 netdev_err(netdev, "failed to map rx page\n");
730 __free_page(page);
731 return -ENOMEM;
732 }
733
734 ftgmac100_rxdes_set_page(rxdes, page);
735 ftgmac100_rxdes_set_dma_addr(rxdes, map);
736 ftgmac100_rxdes_set_dma_own(rxdes);
737 return 0;
738}
739
740static void ftgmac100_free_buffers(struct ftgmac100 *priv)
741{
742 int i;
743
744 for (i = 0; i < RX_QUEUE_ENTRIES; i++) {
745 struct ftgmac100_rxdes *rxdes = &priv->descs->rxdes[i];
746 struct page *page = ftgmac100_rxdes_get_page(rxdes);
747 dma_addr_t map = ftgmac100_rxdes_get_dma_addr(rxdes);
748
749 if (!page)
750 continue;
751
752 dma_unmap_page(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE);
753 __free_page(page);
754 }
755
756 for (i = 0; i < TX_QUEUE_ENTRIES; i++) {
757 struct ftgmac100_txdes *txdes = &priv->descs->txdes[i];
758 struct sk_buff *skb = ftgmac100_txdes_get_skb(txdes);
759 dma_addr_t map = ftgmac100_txdes_get_dma_addr(txdes);
760
761 if (!skb)
762 continue;
763
764 dma_unmap_single(priv->dev, map, skb_headlen(skb), DMA_TO_DEVICE);
765 dev_kfree_skb(skb);
766 }
767
768 dma_free_coherent(priv->dev, sizeof(struct ftgmac100_descs),
769 priv->descs, priv->descs_dma_addr);
770}
771
772static int ftgmac100_alloc_buffers(struct ftgmac100 *priv)
773{
774 int i;
775
776 priv->descs = dma_alloc_coherent(priv->dev,
777 sizeof(struct ftgmac100_descs),
778 &priv->descs_dma_addr, GFP_KERNEL);
779 if (!priv->descs)
780 return -ENOMEM;
781
782 memset(priv->descs, 0, sizeof(struct ftgmac100_descs));
783
784 /* initialize RX ring */
785 ftgmac100_rxdes_set_end_of_ring(&priv->descs->rxdes[RX_QUEUE_ENTRIES - 1]);
786
787 for (i = 0; i < RX_QUEUE_ENTRIES; i++) {
788 struct ftgmac100_rxdes *rxdes = &priv->descs->rxdes[i];
789
790 if (ftgmac100_alloc_rx_page(priv, rxdes, GFP_KERNEL))
791 goto err;
792 }
793
794 /* initialize TX ring */
795 ftgmac100_txdes_set_end_of_ring(&priv->descs->txdes[TX_QUEUE_ENTRIES - 1]);
796 return 0;
797
798err:
799 ftgmac100_free_buffers(priv);
800 return -ENOMEM;
801}
802
803/******************************************************************************
804 * internal functions (mdio)
805 *****************************************************************************/
806static void ftgmac100_adjust_link(struct net_device *netdev)
807{
808 struct ftgmac100 *priv = netdev_priv(netdev);
809 struct phy_device *phydev = priv->phydev;
810 int ier;
811
812 if (phydev->speed == priv->old_speed)
813 return;
814
815 priv->old_speed = phydev->speed;
816
817 ier = ioread32(priv->base + FTGMAC100_OFFSET_IER);
818
819 /* disable all interrupts */
820 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
821
822 netif_stop_queue(netdev);
823 ftgmac100_stop_hw(priv);
824
825 netif_start_queue(netdev);
826 ftgmac100_init_hw(priv);
827 ftgmac100_start_hw(priv, phydev->speed);
828
829 /* re-enable interrupts */
830 iowrite32(ier, priv->base + FTGMAC100_OFFSET_IER);
831}
832
833static int ftgmac100_mii_probe(struct ftgmac100 *priv)
834{
835 struct net_device *netdev = priv->netdev;
836 struct phy_device *phydev = NULL;
837 int i;
838
839 /* search for connect PHY device */
840 for (i = 0; i < PHY_MAX_ADDR; i++) {
841 struct phy_device *tmp = priv->mii_bus->phy_map[i];
842
843 if (tmp) {
844 phydev = tmp;
845 break;
846 }
847 }
848
849 /* now we are supposed to have a proper phydev, to attach to... */
850 if (!phydev) {
851 netdev_info(netdev, "%s: no PHY found\n", netdev->name);
852 return -ENODEV;
853 }
854
855 phydev = phy_connect(netdev, dev_name(&phydev->dev),
856 &ftgmac100_adjust_link, 0,
857 PHY_INTERFACE_MODE_GMII);
858
859 if (IS_ERR(phydev)) {
860 netdev_err(netdev, "%s: Could not attach to PHY\n", netdev->name);
861 return PTR_ERR(phydev);
862 }
863
864 priv->phydev = phydev;
865 return 0;
866}
867
868/******************************************************************************
869 * struct mii_bus functions
870 *****************************************************************************/
871static int ftgmac100_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
872{
873 struct net_device *netdev = bus->priv;
874 struct ftgmac100 *priv = netdev_priv(netdev);
875 unsigned int phycr;
876 int i;
877
878 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
879
880 /* preserve MDC cycle threshold */
881 phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK;
882
883 phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) |
884 FTGMAC100_PHYCR_REGAD(regnum) |
885 FTGMAC100_PHYCR_MIIRD;
886
887 iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR);
888
889 for (i = 0; i < 10; i++) {
890 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
891
892 if ((phycr & FTGMAC100_PHYCR_MIIRD) == 0) {
893 int data;
894
895 data = ioread32(priv->base + FTGMAC100_OFFSET_PHYDATA);
896 return FTGMAC100_PHYDATA_MIIRDATA(data);
897 }
898
899 udelay(100);
900 }
901
902 netdev_err(netdev, "mdio read timed out\n");
903 return -EIO;
904}
905
906static int ftgmac100_mdiobus_write(struct mii_bus *bus, int phy_addr,
907 int regnum, u16 value)
908{
909 struct net_device *netdev = bus->priv;
910 struct ftgmac100 *priv = netdev_priv(netdev);
911 unsigned int phycr;
912 int data;
913 int i;
914
915 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
916
917 /* preserve MDC cycle threshold */
918 phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK;
919
920 phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) |
921 FTGMAC100_PHYCR_REGAD(regnum) |
922 FTGMAC100_PHYCR_MIIWR;
923
924 data = FTGMAC100_PHYDATA_MIIWDATA(value);
925
926 iowrite32(data, priv->base + FTGMAC100_OFFSET_PHYDATA);
927 iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR);
928
929 for (i = 0; i < 10; i++) {
930 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
931
932 if ((phycr & FTGMAC100_PHYCR_MIIWR) == 0)
933 return 0;
934
935 udelay(100);
936 }
937
938 netdev_err(netdev, "mdio write timed out\n");
939 return -EIO;
940}
941
942static int ftgmac100_mdiobus_reset(struct mii_bus *bus)
943{
944 return 0;
945}
946
947/******************************************************************************
948 * struct ethtool_ops functions
949 *****************************************************************************/
950static void ftgmac100_get_drvinfo(struct net_device *netdev,
951 struct ethtool_drvinfo *info)
952{
953 strcpy(info->driver, DRV_NAME);
954 strcpy(info->version, DRV_VERSION);
955 strcpy(info->bus_info, dev_name(&netdev->dev));
956}
957
958static int ftgmac100_get_settings(struct net_device *netdev,
959 struct ethtool_cmd *cmd)
960{
961 struct ftgmac100 *priv = netdev_priv(netdev);
962
963 return phy_ethtool_gset(priv->phydev, cmd);
964}
965
966static int ftgmac100_set_settings(struct net_device *netdev,
967 struct ethtool_cmd *cmd)
968{
969 struct ftgmac100 *priv = netdev_priv(netdev);
970
971 return phy_ethtool_sset(priv->phydev, cmd);
972}
973
974static const struct ethtool_ops ftgmac100_ethtool_ops = {
975 .set_settings = ftgmac100_set_settings,
976 .get_settings = ftgmac100_get_settings,
977 .get_drvinfo = ftgmac100_get_drvinfo,
978 .get_link = ethtool_op_get_link,
979};
980
981/******************************************************************************
982 * interrupt handler
983 *****************************************************************************/
984static irqreturn_t ftgmac100_interrupt(int irq, void *dev_id)
985{
986 struct net_device *netdev = dev_id;
987 struct ftgmac100 *priv = netdev_priv(netdev);
988
989 if (likely(netif_running(netdev))) {
990 /* Disable interrupts for polling */
991 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
992 napi_schedule(&priv->napi);
993 }
994
995 return IRQ_HANDLED;
996}
997
998/******************************************************************************
999 * struct napi_struct functions
1000 *****************************************************************************/
1001static int ftgmac100_poll(struct napi_struct *napi, int budget)
1002{
1003 struct ftgmac100 *priv = container_of(napi, struct ftgmac100, napi);
1004 struct net_device *netdev = priv->netdev;
1005 unsigned int status;
1006 bool completed = true;
1007 int rx = 0;
1008
1009 status = ioread32(priv->base + FTGMAC100_OFFSET_ISR);
1010 iowrite32(status, priv->base + FTGMAC100_OFFSET_ISR);
1011
1012 if (status & (FTGMAC100_INT_RPKT_BUF | FTGMAC100_INT_NO_RXBUF)) {
1013 /*
1014 * FTGMAC100_INT_RPKT_BUF:
1015 * RX DMA has received packets into RX buffer successfully
1016 *
1017 * FTGMAC100_INT_NO_RXBUF:
1018 * RX buffer unavailable
1019 */
1020 bool retry;
1021
1022 do {
1023 retry = ftgmac100_rx_packet(priv, &rx);
1024 } while (retry && rx < budget);
1025
1026 if (retry && rx == budget)
1027 completed = false;
1028 }
1029
1030 if (status & (FTGMAC100_INT_XPKT_ETH | FTGMAC100_INT_XPKT_LOST)) {
1031 /*
1032 * FTGMAC100_INT_XPKT_ETH:
1033 * packet transmitted to ethernet successfully
1034 *
1035 * FTGMAC100_INT_XPKT_LOST:
1036 * packet transmitted to ethernet lost due to late
1037 * collision or excessive collision
1038 */
1039 ftgmac100_tx_complete(priv);
1040 }
1041
1042 if (status & (FTGMAC100_INT_NO_RXBUF | FTGMAC100_INT_RPKT_LOST |
1043 FTGMAC100_INT_AHB_ERR | FTGMAC100_INT_PHYSTS_CHG)) {
1044 if (net_ratelimit())
1045 netdev_info(netdev, "[ISR] = 0x%x: %s%s%s%s\n", status,
1046 status & FTGMAC100_INT_NO_RXBUF ? "NO_RXBUF " : "",
1047 status & FTGMAC100_INT_RPKT_LOST ? "RPKT_LOST " : "",
1048 status & FTGMAC100_INT_AHB_ERR ? "AHB_ERR " : "",
1049 status & FTGMAC100_INT_PHYSTS_CHG ? "PHYSTS_CHG" : "");
1050
1051 if (status & FTGMAC100_INT_NO_RXBUF) {
1052 /* RX buffer unavailable */
1053 netdev->stats.rx_over_errors++;
1054 }
1055
1056 if (status & FTGMAC100_INT_RPKT_LOST) {
1057 /* received packet lost due to RX FIFO full */
1058 netdev->stats.rx_fifo_errors++;
1059 }
1060 }
1061
1062 if (completed) {
1063 napi_complete(napi);
1064
1065 /* enable all interrupts */
1066 iowrite32(INT_MASK_ALL_ENABLED, priv->base + FTGMAC100_OFFSET_IER);
1067 }
1068
1069 return rx;
1070}
1071
1072/******************************************************************************
1073 * struct net_device_ops functions
1074 *****************************************************************************/
1075static int ftgmac100_open(struct net_device *netdev)
1076{
1077 struct ftgmac100 *priv = netdev_priv(netdev);
1078 int err;
1079
1080 err = ftgmac100_alloc_buffers(priv);
1081 if (err) {
1082 netdev_err(netdev, "failed to allocate buffers\n");
1083 goto err_alloc;
1084 }
1085
1086 err = request_irq(priv->irq, ftgmac100_interrupt, 0, netdev->name, netdev);
1087 if (err) {
1088 netdev_err(netdev, "failed to request irq %d\n", priv->irq);
1089 goto err_irq;
1090 }
1091
1092 priv->rx_pointer = 0;
1093 priv->tx_clean_pointer = 0;
1094 priv->tx_pointer = 0;
1095 priv->tx_pending = 0;
1096
1097 err = ftgmac100_reset_hw(priv);
1098 if (err)
1099 goto err_hw;
1100
1101 ftgmac100_init_hw(priv);
1102 ftgmac100_start_hw(priv, 10);
1103
1104 phy_start(priv->phydev);
1105
1106 napi_enable(&priv->napi);
1107 netif_start_queue(netdev);
1108
1109 /* enable all interrupts */
1110 iowrite32(INT_MASK_ALL_ENABLED, priv->base + FTGMAC100_OFFSET_IER);
1111 return 0;
1112
1113err_hw:
1114 free_irq(priv->irq, netdev);
1115err_irq:
1116 ftgmac100_free_buffers(priv);
1117err_alloc:
1118 return err;
1119}
1120
1121static int ftgmac100_stop(struct net_device *netdev)
1122{
1123 struct ftgmac100 *priv = netdev_priv(netdev);
1124
1125 /* disable all interrupts */
1126 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1127
1128 netif_stop_queue(netdev);
1129 napi_disable(&priv->napi);
1130 phy_stop(priv->phydev);
1131
1132 ftgmac100_stop_hw(priv);
1133 free_irq(priv->irq, netdev);
1134 ftgmac100_free_buffers(priv);
1135
1136 return 0;
1137}
1138
1139static int ftgmac100_hard_start_xmit(struct sk_buff *skb,
1140 struct net_device *netdev)
1141{
1142 struct ftgmac100 *priv = netdev_priv(netdev);
1143 dma_addr_t map;
1144
1145 if (unlikely(skb->len > MAX_PKT_SIZE)) {
1146 if (net_ratelimit())
1147 netdev_dbg(netdev, "tx packet too big\n");
1148
1149 netdev->stats.tx_dropped++;
1150 dev_kfree_skb(skb);
1151 return NETDEV_TX_OK;
1152 }
1153
1154 map = dma_map_single(priv->dev, skb->data, skb_headlen(skb), DMA_TO_DEVICE);
1155 if (unlikely(dma_mapping_error(priv->dev, map))) {
1156 /* drop packet */
1157 if (net_ratelimit())
1158 netdev_err(netdev, "map socket buffer failed\n");
1159
1160 netdev->stats.tx_dropped++;
1161 dev_kfree_skb(skb);
1162 return NETDEV_TX_OK;
1163 }
1164
1165 return ftgmac100_xmit(priv, skb, map);
1166}
1167
1168/* optional */
1169static int ftgmac100_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1170{
1171 struct ftgmac100 *priv = netdev_priv(netdev);
1172
1173 return phy_mii_ioctl(priv->phydev, ifr, cmd);
1174}
1175
1176static const struct net_device_ops ftgmac100_netdev_ops = {
1177 .ndo_open = ftgmac100_open,
1178 .ndo_stop = ftgmac100_stop,
1179 .ndo_start_xmit = ftgmac100_hard_start_xmit,
1180 .ndo_set_mac_address = eth_mac_addr,
1181 .ndo_validate_addr = eth_validate_addr,
1182 .ndo_do_ioctl = ftgmac100_do_ioctl,
1183};
1184
1185/******************************************************************************
1186 * struct platform_driver functions
1187 *****************************************************************************/
1188static int ftgmac100_probe(struct platform_device *pdev)
1189{
1190 struct resource *res;
1191 int irq;
1192 struct net_device *netdev;
1193 struct ftgmac100 *priv;
1194 int err;
1195 int i;
1196
1197 if (!pdev)
1198 return -ENODEV;
1199
1200 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1201 if (!res)
1202 return -ENXIO;
1203
1204 irq = platform_get_irq(pdev, 0);
1205 if (irq < 0)
1206 return irq;
1207
1208 /* setup net_device */
1209 netdev = alloc_etherdev(sizeof(*priv));
1210 if (!netdev) {
1211 err = -ENOMEM;
1212 goto err_alloc_etherdev;
1213 }
1214
1215 SET_NETDEV_DEV(netdev, &pdev->dev);
1216
1217 SET_ETHTOOL_OPS(netdev, &ftgmac100_ethtool_ops);
1218 netdev->netdev_ops = &ftgmac100_netdev_ops;
1219 netdev->features = NETIF_F_IP_CSUM | NETIF_F_GRO;
1220
1221 platform_set_drvdata(pdev, netdev);
1222
1223 /* setup private data */
1224 priv = netdev_priv(netdev);
1225 priv->netdev = netdev;
1226 priv->dev = &pdev->dev;
1227
1228 spin_lock_init(&priv->tx_lock);
1229
1230 /* initialize NAPI */
1231 netif_napi_add(netdev, &priv->napi, ftgmac100_poll, 64);
1232
1233 /* map io memory */
1234 priv->res = request_mem_region(res->start, resource_size(res),
1235 dev_name(&pdev->dev));
1236 if (!priv->res) {
1237 dev_err(&pdev->dev, "Could not reserve memory region\n");
1238 err = -ENOMEM;
1239 goto err_req_mem;
1240 }
1241
1242 priv->base = ioremap(res->start, resource_size(res));
1243 if (!priv->base) {
1244 dev_err(&pdev->dev, "Failed to ioremap ethernet registers\n");
1245 err = -EIO;
1246 goto err_ioremap;
1247 }
1248
1249 priv->irq = irq;
1250
1251 /* initialize mdio bus */
1252 priv->mii_bus = mdiobus_alloc();
1253 if (!priv->mii_bus) {
1254 err = -EIO;
1255 goto err_alloc_mdiobus;
1256 }
1257
1258 priv->mii_bus->name = "ftgmac100_mdio";
1259 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "ftgmac100_mii");
1260
1261 priv->mii_bus->priv = netdev;
1262 priv->mii_bus->read = ftgmac100_mdiobus_read;
1263 priv->mii_bus->write = ftgmac100_mdiobus_write;
1264 priv->mii_bus->reset = ftgmac100_mdiobus_reset;
1265 priv->mii_bus->irq = priv->phy_irq;
1266
1267 for (i = 0; i < PHY_MAX_ADDR; i++)
1268 priv->mii_bus->irq[i] = PHY_POLL;
1269
1270 err = mdiobus_register(priv->mii_bus);
1271 if (err) {
1272 dev_err(&pdev->dev, "Cannot register MDIO bus!\n");
1273 goto err_register_mdiobus;
1274 }
1275
1276 err = ftgmac100_mii_probe(priv);
1277 if (err) {
1278 dev_err(&pdev->dev, "MII Probe failed!\n");
1279 goto err_mii_probe;
1280 }
1281
1282 /* register network device */
1283 err = register_netdev(netdev);
1284 if (err) {
1285 dev_err(&pdev->dev, "Failed to register netdev\n");
1286 goto err_register_netdev;
1287 }
1288
1289 netdev_info(netdev, "irq %d, mapped at %p\n", priv->irq, priv->base);
1290
1291 if (!is_valid_ether_addr(netdev->dev_addr)) {
1292 eth_hw_addr_random(netdev);
1293 netdev_info(netdev, "generated random MAC address %pM\n",
1294 netdev->dev_addr);
1295 }
1296
1297 return 0;
1298
1299err_register_netdev:
1300 phy_disconnect(priv->phydev);
1301err_mii_probe:
1302 mdiobus_unregister(priv->mii_bus);
1303err_register_mdiobus:
1304 mdiobus_free(priv->mii_bus);
1305err_alloc_mdiobus:
1306 iounmap(priv->base);
1307err_ioremap:
1308 release_resource(priv->res);
1309err_req_mem:
1310 netif_napi_del(&priv->napi);
1311 platform_set_drvdata(pdev, NULL);
1312 free_netdev(netdev);
1313err_alloc_etherdev:
1314 return err;
1315}
1316
1317static int __exit ftgmac100_remove(struct platform_device *pdev)
1318{
1319 struct net_device *netdev;
1320 struct ftgmac100 *priv;
1321
1322 netdev = platform_get_drvdata(pdev);
1323 priv = netdev_priv(netdev);
1324
1325 unregister_netdev(netdev);
1326
1327 phy_disconnect(priv->phydev);
1328 mdiobus_unregister(priv->mii_bus);
1329 mdiobus_free(priv->mii_bus);
1330
1331 iounmap(priv->base);
1332 release_resource(priv->res);
1333
1334 netif_napi_del(&priv->napi);
1335 platform_set_drvdata(pdev, NULL);
1336 free_netdev(netdev);
1337 return 0;
1338}
1339
1340static struct platform_driver ftgmac100_driver = {
1341 .probe = ftgmac100_probe,
1342 .remove = __exit_p(ftgmac100_remove),
1343 .driver = {
1344 .name = DRV_NAME,
1345 .owner = THIS_MODULE,
1346 },
1347};
1348
1349/******************************************************************************
1350 * initialization / finalization
1351 *****************************************************************************/
1352static int __init ftgmac100_init(void)
1353{
1354 pr_info("Loading version " DRV_VERSION " ...\n");
1355 return platform_driver_register(&ftgmac100_driver);
1356}
1357
1358static void __exit ftgmac100_exit(void)
1359{
1360 platform_driver_unregister(&ftgmac100_driver);
1361}
1362
1363module_init(ftgmac100_init);
1364module_exit(ftgmac100_exit);
1365
1366MODULE_AUTHOR("Po-Yu Chuang <ratbert@faraday-tech.com>");
1367MODULE_DESCRIPTION("FTGMAC100 driver");
1368MODULE_LICENSE("GPL");