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1/*
2 * Copyright (C) 2008 Maarten Maathuis.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 *
25 */
26
27#define NOUVEAU_DMA_DEBUG (nouveau_reg_debug & NOUVEAU_REG_DEBUG_EVO)
28#include "nv50_display.h"
29#include "nouveau_crtc.h"
30#include "nouveau_encoder.h"
31#include "nouveau_connector.h"
32#include "nouveau_fb.h"
33#include "nouveau_fbcon.h"
34#include "nouveau_ramht.h"
35#include "nouveau_software.h"
36#include "drm_crtc_helper.h"
37
38static void nv50_display_isr(struct drm_device *);
39static void nv50_display_bh(unsigned long);
40
41static inline int
42nv50_sor_nr(struct drm_device *dev)
43{
44 struct drm_nouveau_private *dev_priv = dev->dev_private;
45
46 if (dev_priv->chipset < 0x90 ||
47 dev_priv->chipset == 0x92 ||
48 dev_priv->chipset == 0xa0)
49 return 2;
50
51 return 4;
52}
53
54u32
55nv50_display_active_crtcs(struct drm_device *dev)
56{
57 struct drm_nouveau_private *dev_priv = dev->dev_private;
58 u32 mask = 0;
59 int i;
60
61 if (dev_priv->chipset < 0x90 ||
62 dev_priv->chipset == 0x92 ||
63 dev_priv->chipset == 0xa0) {
64 for (i = 0; i < 2; i++)
65 mask |= nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_C(i));
66 } else {
67 for (i = 0; i < 4; i++)
68 mask |= nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_C(i));
69 }
70
71 for (i = 0; i < 3; i++)
72 mask |= nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_C(i));
73
74 return mask & 3;
75}
76
77static int
78evo_icmd(struct drm_device *dev, int ch, u32 mthd, u32 data)
79{
80 int ret = 0;
81 nv_mask(dev, 0x610300 + (ch * 0x08), 0x00000001, 0x00000001);
82 nv_wr32(dev, 0x610304 + (ch * 0x08), data);
83 nv_wr32(dev, 0x610300 + (ch * 0x08), 0x80000001 | mthd);
84 if (!nv_wait(dev, 0x610300 + (ch * 0x08), 0x80000000, 0x00000000))
85 ret = -EBUSY;
86 if (ret || (nouveau_reg_debug & NOUVEAU_REG_DEBUG_EVO))
87 NV_INFO(dev, "EvoPIO: %d 0x%04x 0x%08x\n", ch, mthd, data);
88 nv_mask(dev, 0x610300 + (ch * 0x08), 0x00000001, 0x00000000);
89 return ret;
90}
91
92int
93nv50_display_early_init(struct drm_device *dev)
94{
95 u32 ctrl = nv_rd32(dev, 0x610200);
96 int i;
97
98 /* check if master evo channel is already active, a good a sign as any
99 * that the display engine is in a weird state (hibernate/kexec), if
100 * it is, do our best to reset the display engine...
101 */
102 if ((ctrl & 0x00000003) == 0x00000003) {
103 NV_INFO(dev, "PDISP: EVO(0) 0x%08x, resetting...\n", ctrl);
104
105 /* deactivate both heads first, PDISP will disappear forever
106 * (well, until you power cycle) on some boards as soon as
107 * PMC_ENABLE is hit unless they are..
108 */
109 for (i = 0; i < 2; i++) {
110 evo_icmd(dev, 0, 0x0880 + (i * 0x400), 0x05000000);
111 evo_icmd(dev, 0, 0x089c + (i * 0x400), 0);
112 evo_icmd(dev, 0, 0x0840 + (i * 0x400), 0);
113 evo_icmd(dev, 0, 0x0844 + (i * 0x400), 0);
114 evo_icmd(dev, 0, 0x085c + (i * 0x400), 0);
115 evo_icmd(dev, 0, 0x0874 + (i * 0x400), 0);
116 }
117 evo_icmd(dev, 0, 0x0080, 0);
118
119 /* reset PDISP */
120 nv_mask(dev, 0x000200, 0x40000000, 0x00000000);
121 nv_mask(dev, 0x000200, 0x40000000, 0x40000000);
122 }
123
124 return 0;
125}
126
127void
128nv50_display_late_takedown(struct drm_device *dev)
129{
130}
131
132int
133nv50_display_sync(struct drm_device *dev)
134{
135 struct drm_nouveau_private *dev_priv = dev->dev_private;
136 struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
137 struct nv50_display *disp = nv50_display(dev);
138 struct nouveau_channel *evo = disp->master;
139 u64 start;
140 int ret;
141
142 ret = RING_SPACE(evo, 6);
143 if (ret == 0) {
144 BEGIN_NV04(evo, 0, 0x0084, 1);
145 OUT_RING (evo, 0x80000000);
146 BEGIN_NV04(evo, 0, 0x0080, 1);
147 OUT_RING (evo, 0);
148 BEGIN_NV04(evo, 0, 0x0084, 1);
149 OUT_RING (evo, 0x00000000);
150
151 nv_wo32(disp->ntfy, 0x000, 0x00000000);
152 FIRE_RING (evo);
153
154 start = ptimer->read(dev);
155 do {
156 if (nv_ro32(disp->ntfy, 0x000))
157 return 0;
158 } while (ptimer->read(dev) - start < 2000000000ULL);
159 }
160
161 return -EBUSY;
162}
163
164int
165nv50_display_init(struct drm_device *dev)
166{
167 struct nouveau_channel *evo;
168 int ret, i;
169 u32 val;
170
171 NV_DEBUG_KMS(dev, "\n");
172
173 nv_wr32(dev, 0x00610184, nv_rd32(dev, 0x00614004));
174
175 /*
176 * I think the 0x006101XX range is some kind of main control area
177 * that enables things.
178 */
179 /* CRTC? */
180 for (i = 0; i < 2; i++) {
181 val = nv_rd32(dev, 0x00616100 + (i * 0x800));
182 nv_wr32(dev, 0x00610190 + (i * 0x10), val);
183 val = nv_rd32(dev, 0x00616104 + (i * 0x800));
184 nv_wr32(dev, 0x00610194 + (i * 0x10), val);
185 val = nv_rd32(dev, 0x00616108 + (i * 0x800));
186 nv_wr32(dev, 0x00610198 + (i * 0x10), val);
187 val = nv_rd32(dev, 0x0061610c + (i * 0x800));
188 nv_wr32(dev, 0x0061019c + (i * 0x10), val);
189 }
190
191 /* DAC */
192 for (i = 0; i < 3; i++) {
193 val = nv_rd32(dev, 0x0061a000 + (i * 0x800));
194 nv_wr32(dev, 0x006101d0 + (i * 0x04), val);
195 }
196
197 /* SOR */
198 for (i = 0; i < nv50_sor_nr(dev); i++) {
199 val = nv_rd32(dev, 0x0061c000 + (i * 0x800));
200 nv_wr32(dev, 0x006101e0 + (i * 0x04), val);
201 }
202
203 /* EXT */
204 for (i = 0; i < 3; i++) {
205 val = nv_rd32(dev, 0x0061e000 + (i * 0x800));
206 nv_wr32(dev, 0x006101f0 + (i * 0x04), val);
207 }
208
209 for (i = 0; i < 3; i++) {
210 nv_wr32(dev, NV50_PDISPLAY_DAC_DPMS_CTRL(i), 0x00550000 |
211 NV50_PDISPLAY_DAC_DPMS_CTRL_PENDING);
212 nv_wr32(dev, NV50_PDISPLAY_DAC_CLK_CTRL1(i), 0x00000001);
213 }
214
215 /* The precise purpose is unknown, i suspect it has something to do
216 * with text mode.
217 */
218 if (nv_rd32(dev, NV50_PDISPLAY_INTR_1) & 0x100) {
219 nv_wr32(dev, NV50_PDISPLAY_INTR_1, 0x100);
220 nv_wr32(dev, 0x006194e8, nv_rd32(dev, 0x006194e8) & ~1);
221 if (!nv_wait(dev, 0x006194e8, 2, 0)) {
222 NV_ERROR(dev, "timeout: (0x6194e8 & 2) != 0\n");
223 NV_ERROR(dev, "0x6194e8 = 0x%08x\n",
224 nv_rd32(dev, 0x6194e8));
225 return -EBUSY;
226 }
227 }
228
229 for (i = 0; i < 2; i++) {
230 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 0x2000);
231 if (!nv_wait(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
232 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS, 0)) {
233 NV_ERROR(dev, "timeout: CURSOR_CTRL2_STATUS == 0\n");
234 NV_ERROR(dev, "CURSOR_CTRL2 = 0x%08x\n",
235 nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
236 return -EBUSY;
237 }
238
239 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
240 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_ON);
241 if (!nv_wait(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
242 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS,
243 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS_ACTIVE)) {
244 NV_ERROR(dev, "timeout: "
245 "CURSOR_CTRL2_STATUS_ACTIVE(%d)\n", i);
246 NV_ERROR(dev, "CURSOR_CTRL2(%d) = 0x%08x\n", i,
247 nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
248 return -EBUSY;
249 }
250 }
251
252 nv_wr32(dev, NV50_PDISPLAY_PIO_CTRL, 0x00000000);
253 nv_mask(dev, NV50_PDISPLAY_INTR_0, 0x00000000, 0x00000000);
254 nv_wr32(dev, NV50_PDISPLAY_INTR_EN_0, 0x00000000);
255 nv_mask(dev, NV50_PDISPLAY_INTR_1, 0x00000000, 0x00000000);
256 nv_wr32(dev, NV50_PDISPLAY_INTR_EN_1,
257 NV50_PDISPLAY_INTR_EN_1_CLK_UNK10 |
258 NV50_PDISPLAY_INTR_EN_1_CLK_UNK20 |
259 NV50_PDISPLAY_INTR_EN_1_CLK_UNK40);
260
261 ret = nv50_evo_init(dev);
262 if (ret)
263 return ret;
264 evo = nv50_display(dev)->master;
265
266 nv_wr32(dev, NV50_PDISPLAY_OBJECTS, (evo->ramin->vinst >> 8) | 9);
267
268 ret = RING_SPACE(evo, 3);
269 if (ret)
270 return ret;
271 BEGIN_NV04(evo, 0, NV50_EVO_UNK84, 2);
272 OUT_RING (evo, NV50_EVO_UNK84_NOTIFY_DISABLED);
273 OUT_RING (evo, NvEvoSync);
274
275 return nv50_display_sync(dev);
276}
277
278void
279nv50_display_fini(struct drm_device *dev)
280{
281 struct nv50_display *disp = nv50_display(dev);
282 struct nouveau_channel *evo = disp->master;
283 struct drm_crtc *drm_crtc;
284 int ret, i;
285
286 NV_DEBUG_KMS(dev, "\n");
287
288 list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) {
289 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc);
290
291 nv50_crtc_blank(crtc, true);
292 }
293
294 ret = RING_SPACE(evo, 2);
295 if (ret == 0) {
296 BEGIN_NV04(evo, 0, NV50_EVO_UPDATE, 1);
297 OUT_RING(evo, 0);
298 }
299 FIRE_RING(evo);
300
301 /* Almost like ack'ing a vblank interrupt, maybe in the spirit of
302 * cleaning up?
303 */
304 list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) {
305 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc);
306 uint32_t mask = NV50_PDISPLAY_INTR_1_VBLANK_CRTC_(crtc->index);
307
308 if (!crtc->base.enabled)
309 continue;
310
311 nv_wr32(dev, NV50_PDISPLAY_INTR_1, mask);
312 if (!nv_wait(dev, NV50_PDISPLAY_INTR_1, mask, mask)) {
313 NV_ERROR(dev, "timeout: (0x610024 & 0x%08x) == "
314 "0x%08x\n", mask, mask);
315 NV_ERROR(dev, "0x610024 = 0x%08x\n",
316 nv_rd32(dev, NV50_PDISPLAY_INTR_1));
317 }
318 }
319
320 for (i = 0; i < 2; i++) {
321 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 0);
322 if (!nv_wait(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
323 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS, 0)) {
324 NV_ERROR(dev, "timeout: CURSOR_CTRL2_STATUS == 0\n");
325 NV_ERROR(dev, "CURSOR_CTRL2 = 0x%08x\n",
326 nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
327 }
328 }
329
330 nv50_evo_fini(dev);
331
332 for (i = 0; i < 3; i++) {
333 if (!nv_wait(dev, NV50_PDISPLAY_SOR_DPMS_STATE(i),
334 NV50_PDISPLAY_SOR_DPMS_STATE_WAIT, 0)) {
335 NV_ERROR(dev, "timeout: SOR_DPMS_STATE_WAIT(%d) == 0\n", i);
336 NV_ERROR(dev, "SOR_DPMS_STATE(%d) = 0x%08x\n", i,
337 nv_rd32(dev, NV50_PDISPLAY_SOR_DPMS_STATE(i)));
338 }
339 }
340
341 /* disable interrupts. */
342 nv_wr32(dev, NV50_PDISPLAY_INTR_EN_1, 0x00000000);
343}
344
345int
346nv50_display_create(struct drm_device *dev)
347{
348 struct drm_nouveau_private *dev_priv = dev->dev_private;
349 struct dcb_table *dcb = &dev_priv->vbios.dcb;
350 struct drm_connector *connector, *ct;
351 struct nv50_display *priv;
352 int ret, i;
353
354 NV_DEBUG_KMS(dev, "\n");
355
356 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
357 if (!priv)
358 return -ENOMEM;
359 dev_priv->engine.display.priv = priv;
360
361 /* Create CRTC objects */
362 for (i = 0; i < 2; i++) {
363 ret = nv50_crtc_create(dev, i);
364 if (ret)
365 return ret;
366 }
367
368 /* We setup the encoders from the BIOS table */
369 for (i = 0 ; i < dcb->entries; i++) {
370 struct dcb_entry *entry = &dcb->entry[i];
371
372 if (entry->location != DCB_LOC_ON_CHIP) {
373 NV_WARN(dev, "Off-chip encoder %d/%d unsupported\n",
374 entry->type, ffs(entry->or) - 1);
375 continue;
376 }
377
378 connector = nouveau_connector_create(dev, entry->connector);
379 if (IS_ERR(connector))
380 continue;
381
382 switch (entry->type) {
383 case OUTPUT_TMDS:
384 case OUTPUT_LVDS:
385 case OUTPUT_DP:
386 nv50_sor_create(connector, entry);
387 break;
388 case OUTPUT_ANALOG:
389 nv50_dac_create(connector, entry);
390 break;
391 default:
392 NV_WARN(dev, "DCB encoder %d unknown\n", entry->type);
393 continue;
394 }
395 }
396
397 list_for_each_entry_safe(connector, ct,
398 &dev->mode_config.connector_list, head) {
399 if (!connector->encoder_ids[0]) {
400 NV_WARN(dev, "%s has no encoders, removing\n",
401 drm_get_connector_name(connector));
402 connector->funcs->destroy(connector);
403 }
404 }
405
406 tasklet_init(&priv->tasklet, nv50_display_bh, (unsigned long)dev);
407 nouveau_irq_register(dev, 26, nv50_display_isr);
408
409 ret = nv50_evo_create(dev);
410 if (ret) {
411 nv50_display_destroy(dev);
412 return ret;
413 }
414
415 return 0;
416}
417
418void
419nv50_display_destroy(struct drm_device *dev)
420{
421 struct nv50_display *disp = nv50_display(dev);
422
423 NV_DEBUG_KMS(dev, "\n");
424
425 nv50_evo_destroy(dev);
426 nouveau_irq_unregister(dev, 26);
427 kfree(disp);
428}
429
430void
431nv50_display_flip_stop(struct drm_crtc *crtc)
432{
433 struct nv50_display *disp = nv50_display(crtc->dev);
434 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
435 struct nv50_display_crtc *dispc = &disp->crtc[nv_crtc->index];
436 struct nouveau_channel *evo = dispc->sync;
437 int ret;
438
439 ret = RING_SPACE(evo, 8);
440 if (ret) {
441 WARN_ON(1);
442 return;
443 }
444
445 BEGIN_NV04(evo, 0, 0x0084, 1);
446 OUT_RING (evo, 0x00000000);
447 BEGIN_NV04(evo, 0, 0x0094, 1);
448 OUT_RING (evo, 0x00000000);
449 BEGIN_NV04(evo, 0, 0x00c0, 1);
450 OUT_RING (evo, 0x00000000);
451 BEGIN_NV04(evo, 0, 0x0080, 1);
452 OUT_RING (evo, 0x00000000);
453 FIRE_RING (evo);
454}
455
456int
457nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
458 struct nouveau_channel *chan)
459{
460 struct drm_nouveau_private *dev_priv = crtc->dev->dev_private;
461 struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
462 struct nv50_display *disp = nv50_display(crtc->dev);
463 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
464 struct nv50_display_crtc *dispc = &disp->crtc[nv_crtc->index];
465 struct nouveau_channel *evo = dispc->sync;
466 int ret;
467
468 ret = RING_SPACE(evo, chan ? 25 : 27);
469 if (unlikely(ret))
470 return ret;
471
472 /* synchronise with the rendering channel, if necessary */
473 if (likely(chan)) {
474 ret = RING_SPACE(chan, 10);
475 if (ret) {
476 WIND_RING(evo);
477 return ret;
478 }
479
480 if (dev_priv->chipset < 0xc0) {
481 BEGIN_NV04(chan, 0, 0x0060, 2);
482 OUT_RING (chan, NvEvoSema0 + nv_crtc->index);
483 OUT_RING (chan, dispc->sem.offset);
484 BEGIN_NV04(chan, 0, 0x006c, 1);
485 OUT_RING (chan, 0xf00d0000 | dispc->sem.value);
486 BEGIN_NV04(chan, 0, 0x0064, 2);
487 OUT_RING (chan, dispc->sem.offset ^ 0x10);
488 OUT_RING (chan, 0x74b1e000);
489 BEGIN_NV04(chan, 0, 0x0060, 1);
490 if (dev_priv->chipset < 0x84)
491 OUT_RING (chan, NvSema);
492 else
493 OUT_RING (chan, chan->vram_handle);
494 } else {
495 u64 offset = nvc0_software_crtc(chan, nv_crtc->index);
496 offset += dispc->sem.offset;
497 BEGIN_NVC0(chan, 0, 0x0010, 4);
498 OUT_RING (chan, upper_32_bits(offset));
499 OUT_RING (chan, lower_32_bits(offset));
500 OUT_RING (chan, 0xf00d0000 | dispc->sem.value);
501 OUT_RING (chan, 0x1002);
502 BEGIN_NVC0(chan, 0, 0x0010, 4);
503 OUT_RING (chan, upper_32_bits(offset));
504 OUT_RING (chan, lower_32_bits(offset ^ 0x10));
505 OUT_RING (chan, 0x74b1e000);
506 OUT_RING (chan, 0x1001);
507 }
508 FIRE_RING (chan);
509 } else {
510 nouveau_bo_wr32(dispc->sem.bo, dispc->sem.offset / 4,
511 0xf00d0000 | dispc->sem.value);
512 }
513
514 /* queue the flip on the crtc's "display sync" channel */
515 BEGIN_NV04(evo, 0, 0x0100, 1);
516 OUT_RING (evo, 0xfffe0000);
517 if (chan) {
518 BEGIN_NV04(evo, 0, 0x0084, 1);
519 OUT_RING (evo, 0x00000100);
520 } else {
521 BEGIN_NV04(evo, 0, 0x0084, 1);
522 OUT_RING (evo, 0x00000010);
523 /* allows gamma somehow, PDISP will bitch at you if
524 * you don't wait for vblank before changing this..
525 */
526 BEGIN_NV04(evo, 0, 0x00e0, 1);
527 OUT_RING (evo, 0x40000000);
528 }
529 BEGIN_NV04(evo, 0, 0x0088, 4);
530 OUT_RING (evo, dispc->sem.offset);
531 OUT_RING (evo, 0xf00d0000 | dispc->sem.value);
532 OUT_RING (evo, 0x74b1e000);
533 OUT_RING (evo, NvEvoSync);
534 BEGIN_NV04(evo, 0, 0x00a0, 2);
535 OUT_RING (evo, 0x00000000);
536 OUT_RING (evo, 0x00000000);
537 BEGIN_NV04(evo, 0, 0x00c0, 1);
538 OUT_RING (evo, nv_fb->r_dma);
539 BEGIN_NV04(evo, 0, 0x0110, 2);
540 OUT_RING (evo, 0x00000000);
541 OUT_RING (evo, 0x00000000);
542 BEGIN_NV04(evo, 0, 0x0800, 5);
543 OUT_RING (evo, nv_fb->nvbo->bo.offset >> 8);
544 OUT_RING (evo, 0);
545 OUT_RING (evo, (fb->height << 16) | fb->width);
546 OUT_RING (evo, nv_fb->r_pitch);
547 OUT_RING (evo, nv_fb->r_format);
548 BEGIN_NV04(evo, 0, 0x0080, 1);
549 OUT_RING (evo, 0x00000000);
550 FIRE_RING (evo);
551
552 dispc->sem.offset ^= 0x10;
553 dispc->sem.value++;
554 return 0;
555}
556
557static u16
558nv50_display_script_select(struct drm_device *dev, struct dcb_entry *dcb,
559 u32 mc, int pxclk)
560{
561 struct drm_nouveau_private *dev_priv = dev->dev_private;
562 struct nouveau_connector *nv_connector = NULL;
563 struct drm_encoder *encoder;
564 struct nvbios *bios = &dev_priv->vbios;
565 u32 script = 0, or;
566
567 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
568 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
569
570 if (nv_encoder->dcb != dcb)
571 continue;
572
573 nv_connector = nouveau_encoder_connector_get(nv_encoder);
574 break;
575 }
576
577 or = ffs(dcb->or) - 1;
578 switch (dcb->type) {
579 case OUTPUT_LVDS:
580 script = (mc >> 8) & 0xf;
581 if (bios->fp_no_ddc) {
582 if (bios->fp.dual_link)
583 script |= 0x0100;
584 if (bios->fp.if_is_24bit)
585 script |= 0x0200;
586 } else {
587 /* determine number of lvds links */
588 if (nv_connector && nv_connector->edid &&
589 nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
590 /* http://www.spwg.org */
591 if (((u8 *)nv_connector->edid)[121] == 2)
592 script |= 0x0100;
593 } else
594 if (pxclk >= bios->fp.duallink_transition_clk) {
595 script |= 0x0100;
596 }
597
598 /* determine panel depth */
599 if (script & 0x0100) {
600 if (bios->fp.strapless_is_24bit & 2)
601 script |= 0x0200;
602 } else {
603 if (bios->fp.strapless_is_24bit & 1)
604 script |= 0x0200;
605 }
606
607 if (nv_connector && nv_connector->edid &&
608 (nv_connector->edid->revision >= 4) &&
609 (nv_connector->edid->input & 0x70) >= 0x20)
610 script |= 0x0200;
611 }
612
613 if (nouveau_uscript_lvds >= 0) {
614 NV_INFO(dev, "override script 0x%04x with 0x%04x "
615 "for output LVDS-%d\n", script,
616 nouveau_uscript_lvds, or);
617 script = nouveau_uscript_lvds;
618 }
619 break;
620 case OUTPUT_TMDS:
621 script = (mc >> 8) & 0xf;
622 if (pxclk >= 165000)
623 script |= 0x0100;
624
625 if (nouveau_uscript_tmds >= 0) {
626 NV_INFO(dev, "override script 0x%04x with 0x%04x "
627 "for output TMDS-%d\n", script,
628 nouveau_uscript_tmds, or);
629 script = nouveau_uscript_tmds;
630 }
631 break;
632 case OUTPUT_DP:
633 script = (mc >> 8) & 0xf;
634 break;
635 case OUTPUT_ANALOG:
636 script = 0xff;
637 break;
638 default:
639 NV_ERROR(dev, "modeset on unsupported output type!\n");
640 break;
641 }
642
643 return script;
644}
645
646static void
647nv50_display_vblank_crtc_handler(struct drm_device *dev, int crtc)
648{
649 nouveau_software_vblank(dev, crtc);
650 drm_handle_vblank(dev, crtc);
651}
652
653static void
654nv50_display_vblank_handler(struct drm_device *dev, uint32_t intr)
655{
656 if (intr & NV50_PDISPLAY_INTR_1_VBLANK_CRTC_0)
657 nv50_display_vblank_crtc_handler(dev, 0);
658
659 if (intr & NV50_PDISPLAY_INTR_1_VBLANK_CRTC_1)
660 nv50_display_vblank_crtc_handler(dev, 1);
661
662 nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_VBLANK_CRTC);
663}
664
665static void
666nv50_display_unk10_handler(struct drm_device *dev)
667{
668 struct drm_nouveau_private *dev_priv = dev->dev_private;
669 struct nv50_display *disp = nv50_display(dev);
670 u32 unk30 = nv_rd32(dev, 0x610030), mc;
671 int i, crtc, or = 0, type = OUTPUT_ANY;
672
673 NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
674 disp->irq.dcb = NULL;
675
676 nv_wr32(dev, 0x619494, nv_rd32(dev, 0x619494) & ~8);
677
678 /* Determine which CRTC we're dealing with, only 1 ever will be
679 * signalled at the same time with the current nouveau code.
680 */
681 crtc = ffs((unk30 & 0x00000060) >> 5) - 1;
682 if (crtc < 0)
683 goto ack;
684
685 /* Nothing needs to be done for the encoder */
686 crtc = ffs((unk30 & 0x00000180) >> 7) - 1;
687 if (crtc < 0)
688 goto ack;
689
690 /* Find which encoder was connected to the CRTC */
691 for (i = 0; type == OUTPUT_ANY && i < 3; i++) {
692 mc = nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_C(i));
693 NV_DEBUG_KMS(dev, "DAC-%d mc: 0x%08x\n", i, mc);
694 if (!(mc & (1 << crtc)))
695 continue;
696
697 switch ((mc & 0x00000f00) >> 8) {
698 case 0: type = OUTPUT_ANALOG; break;
699 case 1: type = OUTPUT_TV; break;
700 default:
701 NV_ERROR(dev, "invalid mc, DAC-%d: 0x%08x\n", i, mc);
702 goto ack;
703 }
704
705 or = i;
706 }
707
708 for (i = 0; type == OUTPUT_ANY && i < nv50_sor_nr(dev); i++) {
709 if (dev_priv->chipset < 0x90 ||
710 dev_priv->chipset == 0x92 ||
711 dev_priv->chipset == 0xa0)
712 mc = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_C(i));
713 else
714 mc = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_C(i));
715
716 NV_DEBUG_KMS(dev, "SOR-%d mc: 0x%08x\n", i, mc);
717 if (!(mc & (1 << crtc)))
718 continue;
719
720 switch ((mc & 0x00000f00) >> 8) {
721 case 0: type = OUTPUT_LVDS; break;
722 case 1: type = OUTPUT_TMDS; break;
723 case 2: type = OUTPUT_TMDS; break;
724 case 5: type = OUTPUT_TMDS; break;
725 case 8: type = OUTPUT_DP; break;
726 case 9: type = OUTPUT_DP; break;
727 default:
728 NV_ERROR(dev, "invalid mc, SOR-%d: 0x%08x\n", i, mc);
729 goto ack;
730 }
731
732 or = i;
733 }
734
735 /* There was no encoder to disable */
736 if (type == OUTPUT_ANY)
737 goto ack;
738
739 /* Disable the encoder */
740 for (i = 0; i < dev_priv->vbios.dcb.entries; i++) {
741 struct dcb_entry *dcb = &dev_priv->vbios.dcb.entry[i];
742
743 if (dcb->type == type && (dcb->or & (1 << or))) {
744 nouveau_bios_run_display_table(dev, 0, -1, dcb, -1);
745 disp->irq.dcb = dcb;
746 goto ack;
747 }
748 }
749
750 NV_ERROR(dev, "no dcb for %d %d 0x%08x\n", or, type, mc);
751ack:
752 nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK10);
753 nv_wr32(dev, 0x610030, 0x80000000);
754}
755
756static void
757nv50_display_unk20_handler(struct drm_device *dev)
758{
759 struct drm_nouveau_private *dev_priv = dev->dev_private;
760 struct nv50_display *disp = nv50_display(dev);
761 u32 unk30 = nv_rd32(dev, 0x610030), tmp, pclk, script, mc = 0;
762 struct dcb_entry *dcb;
763 int i, crtc, or = 0, type = OUTPUT_ANY;
764
765 NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
766 dcb = disp->irq.dcb;
767 if (dcb) {
768 nouveau_bios_run_display_table(dev, 0, -2, dcb, -1);
769 disp->irq.dcb = NULL;
770 }
771
772 /* CRTC clock change requested? */
773 crtc = ffs((unk30 & 0x00000600) >> 9) - 1;
774 if (crtc >= 0) {
775 pclk = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(crtc, CLOCK));
776 pclk &= 0x003fffff;
777 if (pclk)
778 nv50_crtc_set_clock(dev, crtc, pclk);
779
780 tmp = nv_rd32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(crtc));
781 tmp &= ~0x000000f;
782 nv_wr32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(crtc), tmp);
783 }
784
785 /* Nothing needs to be done for the encoder */
786 crtc = ffs((unk30 & 0x00000180) >> 7) - 1;
787 if (crtc < 0)
788 goto ack;
789 pclk = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(crtc, CLOCK)) & 0x003fffff;
790
791 /* Find which encoder is connected to the CRTC */
792 for (i = 0; type == OUTPUT_ANY && i < 3; i++) {
793 mc = nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_P(i));
794 NV_DEBUG_KMS(dev, "DAC-%d mc: 0x%08x\n", i, mc);
795 if (!(mc & (1 << crtc)))
796 continue;
797
798 switch ((mc & 0x00000f00) >> 8) {
799 case 0: type = OUTPUT_ANALOG; break;
800 case 1: type = OUTPUT_TV; break;
801 default:
802 NV_ERROR(dev, "invalid mc, DAC-%d: 0x%08x\n", i, mc);
803 goto ack;
804 }
805
806 or = i;
807 }
808
809 for (i = 0; type == OUTPUT_ANY && i < nv50_sor_nr(dev); i++) {
810 if (dev_priv->chipset < 0x90 ||
811 dev_priv->chipset == 0x92 ||
812 dev_priv->chipset == 0xa0)
813 mc = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_P(i));
814 else
815 mc = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_P(i));
816
817 NV_DEBUG_KMS(dev, "SOR-%d mc: 0x%08x\n", i, mc);
818 if (!(mc & (1 << crtc)))
819 continue;
820
821 switch ((mc & 0x00000f00) >> 8) {
822 case 0: type = OUTPUT_LVDS; break;
823 case 1: type = OUTPUT_TMDS; break;
824 case 2: type = OUTPUT_TMDS; break;
825 case 5: type = OUTPUT_TMDS; break;
826 case 8: type = OUTPUT_DP; break;
827 case 9: type = OUTPUT_DP; break;
828 default:
829 NV_ERROR(dev, "invalid mc, SOR-%d: 0x%08x\n", i, mc);
830 goto ack;
831 }
832
833 or = i;
834 }
835
836 if (type == OUTPUT_ANY)
837 goto ack;
838
839 /* Enable the encoder */
840 for (i = 0; i < dev_priv->vbios.dcb.entries; i++) {
841 dcb = &dev_priv->vbios.dcb.entry[i];
842 if (dcb->type == type && (dcb->or & (1 << or)))
843 break;
844 }
845
846 if (i == dev_priv->vbios.dcb.entries) {
847 NV_ERROR(dev, "no dcb for %d %d 0x%08x\n", or, type, mc);
848 goto ack;
849 }
850
851 script = nv50_display_script_select(dev, dcb, mc, pclk);
852 nouveau_bios_run_display_table(dev, script, pclk, dcb, -1);
853
854 if (type == OUTPUT_DP) {
855 int link = !(dcb->dpconf.sor.link & 1);
856 if ((mc & 0x000f0000) == 0x00020000)
857 nv50_sor_dp_calc_tu(dev, or, link, pclk, 18);
858 else
859 nv50_sor_dp_calc_tu(dev, or, link, pclk, 24);
860 }
861
862 if (dcb->type != OUTPUT_ANALOG) {
863 tmp = nv_rd32(dev, NV50_PDISPLAY_SOR_CLK_CTRL2(or));
864 tmp &= ~0x00000f0f;
865 if (script & 0x0100)
866 tmp |= 0x00000101;
867 nv_wr32(dev, NV50_PDISPLAY_SOR_CLK_CTRL2(or), tmp);
868 } else {
869 nv_wr32(dev, NV50_PDISPLAY_DAC_CLK_CTRL2(or), 0);
870 }
871
872 disp->irq.dcb = dcb;
873 disp->irq.pclk = pclk;
874 disp->irq.script = script;
875
876ack:
877 nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK20);
878 nv_wr32(dev, 0x610030, 0x80000000);
879}
880
881/* If programming a TMDS output on a SOR that can also be configured for
882 * DisplayPort, make sure NV50_SOR_DP_CTRL_ENABLE is forced off.
883 *
884 * It looks like the VBIOS TMDS scripts make an attempt at this, however,
885 * the VBIOS scripts on at least one board I have only switch it off on
886 * link 0, causing a blank display if the output has previously been
887 * programmed for DisplayPort.
888 */
889static void
890nv50_display_unk40_dp_set_tmds(struct drm_device *dev, struct dcb_entry *dcb)
891{
892 int or = ffs(dcb->or) - 1, link = !(dcb->dpconf.sor.link & 1);
893 struct drm_encoder *encoder;
894 u32 tmp;
895
896 if (dcb->type != OUTPUT_TMDS)
897 return;
898
899 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
900 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
901
902 if (nv_encoder->dcb->type == OUTPUT_DP &&
903 nv_encoder->dcb->or & (1 << or)) {
904 tmp = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
905 tmp &= ~NV50_SOR_DP_CTRL_ENABLED;
906 nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp);
907 break;
908 }
909 }
910}
911
912static void
913nv50_display_unk40_handler(struct drm_device *dev)
914{
915 struct nv50_display *disp = nv50_display(dev);
916 struct dcb_entry *dcb = disp->irq.dcb;
917 u16 script = disp->irq.script;
918 u32 unk30 = nv_rd32(dev, 0x610030), pclk = disp->irq.pclk;
919
920 NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
921 disp->irq.dcb = NULL;
922 if (!dcb)
923 goto ack;
924
925 nouveau_bios_run_display_table(dev, script, -pclk, dcb, -1);
926 nv50_display_unk40_dp_set_tmds(dev, dcb);
927
928ack:
929 nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK40);
930 nv_wr32(dev, 0x610030, 0x80000000);
931 nv_wr32(dev, 0x619494, nv_rd32(dev, 0x619494) | 8);
932}
933
934static void
935nv50_display_bh(unsigned long data)
936{
937 struct drm_device *dev = (struct drm_device *)data;
938
939 for (;;) {
940 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0);
941 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1);
942
943 NV_DEBUG_KMS(dev, "PDISPLAY_INTR_BH 0x%08x 0x%08x\n", intr0, intr1);
944
945 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK10)
946 nv50_display_unk10_handler(dev);
947 else
948 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK20)
949 nv50_display_unk20_handler(dev);
950 else
951 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK40)
952 nv50_display_unk40_handler(dev);
953 else
954 break;
955 }
956
957 nv_wr32(dev, NV03_PMC_INTR_EN_0, 1);
958}
959
960static void
961nv50_display_error_handler(struct drm_device *dev)
962{
963 u32 channels = (nv_rd32(dev, NV50_PDISPLAY_INTR_0) & 0x001f0000) >> 16;
964 u32 addr, data;
965 int chid;
966
967 for (chid = 0; chid < 5; chid++) {
968 if (!(channels & (1 << chid)))
969 continue;
970
971 nv_wr32(dev, NV50_PDISPLAY_INTR_0, 0x00010000 << chid);
972 addr = nv_rd32(dev, NV50_PDISPLAY_TRAPPED_ADDR(chid));
973 data = nv_rd32(dev, NV50_PDISPLAY_TRAPPED_DATA(chid));
974 NV_ERROR(dev, "EvoCh %d Mthd 0x%04x Data 0x%08x "
975 "(0x%04x 0x%02x)\n", chid,
976 addr & 0xffc, data, addr >> 16, (addr >> 12) & 0xf);
977
978 nv_wr32(dev, NV50_PDISPLAY_TRAPPED_ADDR(chid), 0x90000000);
979 }
980}
981
982static void
983nv50_display_isr(struct drm_device *dev)
984{
985 struct nv50_display *disp = nv50_display(dev);
986 uint32_t delayed = 0;
987
988 while (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_DISPLAY) {
989 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0);
990 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1);
991 uint32_t clock;
992
993 NV_DEBUG_KMS(dev, "PDISPLAY_INTR 0x%08x 0x%08x\n", intr0, intr1);
994
995 if (!intr0 && !(intr1 & ~delayed))
996 break;
997
998 if (intr0 & 0x001f0000) {
999 nv50_display_error_handler(dev);
1000 intr0 &= ~0x001f0000;
1001 }
1002
1003 if (intr1 & NV50_PDISPLAY_INTR_1_VBLANK_CRTC) {
1004 nv50_display_vblank_handler(dev, intr1);
1005 intr1 &= ~NV50_PDISPLAY_INTR_1_VBLANK_CRTC;
1006 }
1007
1008 clock = (intr1 & (NV50_PDISPLAY_INTR_1_CLK_UNK10 |
1009 NV50_PDISPLAY_INTR_1_CLK_UNK20 |
1010 NV50_PDISPLAY_INTR_1_CLK_UNK40));
1011 if (clock) {
1012 nv_wr32(dev, NV03_PMC_INTR_EN_0, 0);
1013 tasklet_schedule(&disp->tasklet);
1014 delayed |= clock;
1015 intr1 &= ~clock;
1016 }
1017
1018 if (intr0) {
1019 NV_ERROR(dev, "unknown PDISPLAY_INTR_0: 0x%08x\n", intr0);
1020 nv_wr32(dev, NV50_PDISPLAY_INTR_0, intr0);
1021 }
1022
1023 if (intr1) {
1024 NV_ERROR(dev,
1025 "unknown PDISPLAY_INTR_1: 0x%08x\n", intr1);
1026 nv_wr32(dev, NV50_PDISPLAY_INTR_1, intr1);
1027 }
1028 }
1029}