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1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/firmware.h>
25#include "amdgpu.h"
26#include "amdgpu_vcn.h"
27#include "amdgpu_pm.h"
28#include "amdgpu_cs.h"
29#include "soc15.h"
30#include "soc15d.h"
31#include "vcn_v2_0.h"
32#include "mmsch_v3_0.h"
33#include "vcn_sw_ring.h"
34
35#include "vcn/vcn_3_0_0_offset.h"
36#include "vcn/vcn_3_0_0_sh_mask.h"
37#include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"
38
39#include <drm/drm_drv.h>
40
41#define VCN_VID_SOC_ADDRESS_2_0 0x1fa00
42#define VCN1_VID_SOC_ADDRESS_3_0 0x48200
43
44#define mmUVD_CONTEXT_ID_INTERNAL_OFFSET 0x27
45#define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET 0x0f
46#define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET 0x10
47#define mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET 0x11
48#define mmUVD_NO_OP_INTERNAL_OFFSET 0x29
49#define mmUVD_GP_SCRATCH8_INTERNAL_OFFSET 0x66
50#define mmUVD_SCRATCH9_INTERNAL_OFFSET 0xc01d
51
52#define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET 0x431
53#define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x3b4
54#define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x3b5
55#define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET 0x25c
56
57#define VCN_INSTANCES_SIENNA_CICHLID 2
58#define DEC_SW_RING_ENABLED FALSE
59
60#define RDECODE_MSG_CREATE 0x00000000
61#define RDECODE_MESSAGE_CREATE 0x00000001
62
63static const struct amdgpu_hwip_reg_entry vcn_reg_list_3_0[] = {
64 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_POWER_STATUS),
65 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_STATUS),
66 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID),
67 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID2),
68 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA0),
69 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA1),
70 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_CMD),
71 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI),
72 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO),
73 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI2),
74 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO2),
75 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI3),
76 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO3),
77 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI4),
78 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO4),
79 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR),
80 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR),
81 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR2),
82 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR2),
83 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR3),
84 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR3),
85 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR4),
86 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR4),
87 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE),
88 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE2),
89 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE3),
90 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE4),
91 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_CONFIG),
92 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_STATUS),
93 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_CTL),
94 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_DATA),
95 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_MASK),
96 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_PAUSE)
97};
98
99static int amdgpu_ih_clientid_vcns[] = {
100 SOC15_IH_CLIENTID_VCN,
101 SOC15_IH_CLIENTID_VCN1
102};
103
104static int vcn_v3_0_start_sriov(struct amdgpu_device *adev);
105static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev);
106static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev);
107static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev);
108static int vcn_v3_0_set_powergating_state(void *handle,
109 enum amd_powergating_state state);
110static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev,
111 int inst_idx, struct dpg_pause_state *new_state);
112
113static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring);
114static void vcn_v3_0_enc_ring_set_wptr(struct amdgpu_ring *ring);
115
116/**
117 * vcn_v3_0_early_init - set function pointers and load microcode
118 *
119 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
120 *
121 * Set ring and irq function pointers
122 * Load microcode from filesystem
123 */
124static int vcn_v3_0_early_init(struct amdgpu_ip_block *ip_block)
125{
126 struct amdgpu_device *adev = ip_block->adev;
127
128 if (amdgpu_sriov_vf(adev)) {
129 adev->vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID;
130 adev->vcn.harvest_config = 0;
131 adev->vcn.num_enc_rings = 1;
132
133 } else {
134 if (adev->vcn.harvest_config == (AMDGPU_VCN_HARVEST_VCN0 |
135 AMDGPU_VCN_HARVEST_VCN1))
136 /* both instances are harvested, disable the block */
137 return -ENOENT;
138
139 if (amdgpu_ip_version(adev, UVD_HWIP, 0) ==
140 IP_VERSION(3, 0, 33))
141 adev->vcn.num_enc_rings = 0;
142 else
143 adev->vcn.num_enc_rings = 2;
144 }
145
146 vcn_v3_0_set_dec_ring_funcs(adev);
147 vcn_v3_0_set_enc_ring_funcs(adev);
148 vcn_v3_0_set_irq_funcs(adev);
149
150 return amdgpu_vcn_early_init(adev);
151}
152
153/**
154 * vcn_v3_0_sw_init - sw init for VCN block
155 *
156 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
157 *
158 * Load firmware and sw initialization
159 */
160static int vcn_v3_0_sw_init(struct amdgpu_ip_block *ip_block)
161{
162 struct amdgpu_ring *ring;
163 int i, j, r;
164 int vcn_doorbell_index = 0;
165 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_3_0);
166 uint32_t *ptr;
167 struct amdgpu_device *adev = ip_block->adev;
168
169 r = amdgpu_vcn_sw_init(adev);
170 if (r)
171 return r;
172
173 amdgpu_vcn_setup_ucode(adev);
174
175 r = amdgpu_vcn_resume(adev);
176 if (r)
177 return r;
178
179 /*
180 * Note: doorbell assignment is fixed for SRIOV multiple VCN engines
181 * Formula:
182 * vcn_db_base = adev->doorbell_index.vcn.vcn_ring0_1 << 1;
183 * dec_ring_i = vcn_db_base + i * (adev->vcn.num_enc_rings + 1)
184 * enc_ring_i,j = vcn_db_base + i * (adev->vcn.num_enc_rings + 1) + 1 + j
185 */
186 if (amdgpu_sriov_vf(adev)) {
187 vcn_doorbell_index = adev->doorbell_index.vcn.vcn_ring0_1;
188 /* get DWORD offset */
189 vcn_doorbell_index = vcn_doorbell_index << 1;
190 }
191
192 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
193 volatile struct amdgpu_fw_shared *fw_shared;
194
195 if (adev->vcn.harvest_config & (1 << i))
196 continue;
197
198 adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET;
199 adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET;
200 adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET;
201 adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET;
202 adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET;
203 adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET;
204
205 adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET;
206 adev->vcn.inst[i].external.scratch9 = SOC15_REG_OFFSET(VCN, i, mmUVD_SCRATCH9);
207 adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET;
208 adev->vcn.inst[i].external.data0 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA0);
209 adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET;
210 adev->vcn.inst[i].external.data1 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA1);
211 adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET;
212 adev->vcn.inst[i].external.cmd = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_CMD);
213 adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET;
214 adev->vcn.inst[i].external.nop = SOC15_REG_OFFSET(VCN, i, mmUVD_NO_OP);
215
216 /* VCN DEC TRAP */
217 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
218 VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst[i].irq);
219 if (r)
220 return r;
221
222 atomic_set(&adev->vcn.inst[i].sched_score, 0);
223
224 ring = &adev->vcn.inst[i].ring_dec;
225 ring->use_doorbell = true;
226 if (amdgpu_sriov_vf(adev)) {
227 ring->doorbell_index = vcn_doorbell_index + i * (adev->vcn.num_enc_rings + 1);
228 } else {
229 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i;
230 }
231 ring->vm_hub = AMDGPU_MMHUB0(0);
232 sprintf(ring->name, "vcn_dec_%d", i);
233 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0,
234 AMDGPU_RING_PRIO_DEFAULT,
235 &adev->vcn.inst[i].sched_score);
236 if (r)
237 return r;
238
239 for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
240 enum amdgpu_ring_priority_level hw_prio = amdgpu_vcn_get_enc_ring_prio(j);
241
242 /* VCN ENC TRAP */
243 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
244 j + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq);
245 if (r)
246 return r;
247
248 ring = &adev->vcn.inst[i].ring_enc[j];
249 ring->use_doorbell = true;
250 if (amdgpu_sriov_vf(adev)) {
251 ring->doorbell_index = vcn_doorbell_index + i * (adev->vcn.num_enc_rings + 1) + 1 + j;
252 } else {
253 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + j + 8 * i;
254 }
255 ring->vm_hub = AMDGPU_MMHUB0(0);
256 sprintf(ring->name, "vcn_enc_%d.%d", i, j);
257 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0,
258 hw_prio, &adev->vcn.inst[i].sched_score);
259 if (r)
260 return r;
261 }
262
263 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
264 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_SW_RING_FLAG) |
265 cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG) |
266 cpu_to_le32(AMDGPU_VCN_FW_SHARED_FLAG_0_RB);
267 fw_shared->sw_ring.is_enabled = cpu_to_le32(DEC_SW_RING_ENABLED);
268 fw_shared->present_flag_0 |= AMDGPU_VCN_SMU_VERSION_INFO_FLAG;
269 if (amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(3, 1, 2))
270 fw_shared->smu_interface_info.smu_interface_type = 2;
271 else if (amdgpu_ip_version(adev, UVD_HWIP, 0) ==
272 IP_VERSION(3, 1, 1))
273 fw_shared->smu_interface_info.smu_interface_type = 1;
274
275 if (amdgpu_vcnfw_log)
276 amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]);
277 }
278
279 if (amdgpu_sriov_vf(adev)) {
280 r = amdgpu_virt_alloc_mm_table(adev);
281 if (r)
282 return r;
283 }
284 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
285 adev->vcn.pause_dpg_mode = vcn_v3_0_pause_dpg_mode;
286
287 /* Allocate memory for VCN IP Dump buffer */
288 ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL);
289 if (ptr == NULL) {
290 DRM_ERROR("Failed to allocate memory for VCN IP Dump\n");
291 adev->vcn.ip_dump = NULL;
292 } else {
293 adev->vcn.ip_dump = ptr;
294 }
295
296 return 0;
297}
298
299/**
300 * vcn_v3_0_sw_fini - sw fini for VCN block
301 *
302 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
303 *
304 * VCN suspend and free up sw allocation
305 */
306static int vcn_v3_0_sw_fini(struct amdgpu_ip_block *ip_block)
307{
308 struct amdgpu_device *adev = ip_block->adev;
309 int i, r, idx;
310
311 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
312 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
313 volatile struct amdgpu_fw_shared *fw_shared;
314
315 if (adev->vcn.harvest_config & (1 << i))
316 continue;
317 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
318 fw_shared->present_flag_0 = 0;
319 fw_shared->sw_ring.is_enabled = false;
320 }
321
322 drm_dev_exit(idx);
323 }
324
325 if (amdgpu_sriov_vf(adev))
326 amdgpu_virt_free_mm_table(adev);
327
328 r = amdgpu_vcn_suspend(adev);
329 if (r)
330 return r;
331
332 r = amdgpu_vcn_sw_fini(adev);
333
334 kfree(adev->vcn.ip_dump);
335 return r;
336}
337
338/**
339 * vcn_v3_0_hw_init - start and test VCN block
340 *
341 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
342 *
343 * Initialize the hardware, boot up the VCPU and do some testing
344 */
345static int vcn_v3_0_hw_init(struct amdgpu_ip_block *ip_block)
346{
347 struct amdgpu_device *adev = ip_block->adev;
348 struct amdgpu_ring *ring;
349 int i, j, r;
350
351 if (amdgpu_sriov_vf(adev)) {
352 r = vcn_v3_0_start_sriov(adev);
353 if (r)
354 return r;
355
356 /* initialize VCN dec and enc ring buffers */
357 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
358 if (adev->vcn.harvest_config & (1 << i))
359 continue;
360
361 ring = &adev->vcn.inst[i].ring_dec;
362 if (amdgpu_vcn_is_disabled_vcn(adev, VCN_DECODE_RING, i)) {
363 ring->sched.ready = false;
364 ring->no_scheduler = true;
365 dev_info(adev->dev, "ring %s is disabled by hypervisor\n", ring->name);
366 } else {
367 ring->wptr = 0;
368 ring->wptr_old = 0;
369 vcn_v3_0_dec_ring_set_wptr(ring);
370 ring->sched.ready = true;
371 }
372
373 for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
374 ring = &adev->vcn.inst[i].ring_enc[j];
375 if (amdgpu_vcn_is_disabled_vcn(adev, VCN_ENCODE_RING, i)) {
376 ring->sched.ready = false;
377 ring->no_scheduler = true;
378 dev_info(adev->dev, "ring %s is disabled by hypervisor\n", ring->name);
379 } else {
380 ring->wptr = 0;
381 ring->wptr_old = 0;
382 vcn_v3_0_enc_ring_set_wptr(ring);
383 ring->sched.ready = true;
384 }
385 }
386 }
387 } else {
388 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
389 if (adev->vcn.harvest_config & (1 << i))
390 continue;
391
392 ring = &adev->vcn.inst[i].ring_dec;
393
394 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
395 ring->doorbell_index, i);
396
397 r = amdgpu_ring_test_helper(ring);
398 if (r)
399 return r;
400
401 for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
402 ring = &adev->vcn.inst[i].ring_enc[j];
403 r = amdgpu_ring_test_helper(ring);
404 if (r)
405 return r;
406 }
407 }
408 }
409
410 return 0;
411}
412
413/**
414 * vcn_v3_0_hw_fini - stop the hardware block
415 *
416 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
417 *
418 * Stop the VCN block, mark ring as not ready any more
419 */
420static int vcn_v3_0_hw_fini(struct amdgpu_ip_block *ip_block)
421{
422 struct amdgpu_device *adev = ip_block->adev;
423 int i;
424
425 cancel_delayed_work_sync(&adev->vcn.idle_work);
426
427 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
428 if (adev->vcn.harvest_config & (1 << i))
429 continue;
430
431 if (!amdgpu_sriov_vf(adev)) {
432 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
433 (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
434 RREG32_SOC15(VCN, i, mmUVD_STATUS))) {
435 vcn_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
436 }
437 }
438 }
439
440 return 0;
441}
442
443/**
444 * vcn_v3_0_suspend - suspend VCN block
445 *
446 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
447 *
448 * HW fini and suspend VCN block
449 */
450static int vcn_v3_0_suspend(struct amdgpu_ip_block *ip_block)
451{
452 int r;
453
454 r = vcn_v3_0_hw_fini(ip_block);
455 if (r)
456 return r;
457
458 r = amdgpu_vcn_suspend(ip_block->adev);
459
460 return r;
461}
462
463/**
464 * vcn_v3_0_resume - resume VCN block
465 *
466 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
467 *
468 * Resume firmware and hw init VCN block
469 */
470static int vcn_v3_0_resume(struct amdgpu_ip_block *ip_block)
471{
472 int r;
473
474 r = amdgpu_vcn_resume(ip_block->adev);
475 if (r)
476 return r;
477
478 r = vcn_v3_0_hw_init(ip_block);
479
480 return r;
481}
482
483/**
484 * vcn_v3_0_mc_resume - memory controller programming
485 *
486 * @adev: amdgpu_device pointer
487 * @inst: instance number
488 *
489 * Let the VCN memory controller know it's offsets
490 */
491static void vcn_v3_0_mc_resume(struct amdgpu_device *adev, int inst)
492{
493 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[inst]->size + 4);
494 uint32_t offset;
495
496 /* cache window 0: fw */
497 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
498 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
499 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo));
500 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
501 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi));
502 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0, 0);
503 offset = 0;
504 } else {
505 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
506 lower_32_bits(adev->vcn.inst[inst].gpu_addr));
507 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
508 upper_32_bits(adev->vcn.inst[inst].gpu_addr));
509 offset = size;
510 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0,
511 AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
512 }
513 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE0, size);
514
515 /* cache window 1: stack */
516 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
517 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset));
518 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
519 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset));
520 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET1, 0);
521 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);
522
523 /* cache window 2: context */
524 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
525 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
526 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
527 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
528 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET2, 0);
529 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
530
531 /* non-cache window */
532 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW,
533 lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr));
534 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH,
535 upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr));
536 WREG32_SOC15(VCN, inst, mmUVD_VCPU_NONCACHE_OFFSET0, 0);
537 WREG32_SOC15(VCN, inst, mmUVD_VCPU_NONCACHE_SIZE0,
538 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)));
539}
540
541static void vcn_v3_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
542{
543 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[inst_idx]->size + 4);
544 uint32_t offset;
545
546 /* cache window 0: fw */
547 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
548 if (!indirect) {
549 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
550 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
551 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect);
552 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
553 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
554 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect);
555 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
556 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
557 } else {
558 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
559 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);
560 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
561 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
562 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
563 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
564 }
565 offset = 0;
566 } else {
567 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
568 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
569 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
570 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
571 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
572 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
573 offset = size;
574 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
575 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0),
576 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
577 }
578
579 if (!indirect)
580 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
581 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
582 else
583 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
584 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
585
586 /* cache window 1: stack */
587 if (!indirect) {
588 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
589 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
590 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
591 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
592 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
593 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
594 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
595 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
596 } else {
597 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
598 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);
599 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
600 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);
601 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
602 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
603 }
604 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
605 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);
606
607 /* cache window 2: context */
608 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
609 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
610 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
611 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
612 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
613 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
614 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
615 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
616 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
617 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
618
619 /* non-cache window */
620 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
621 VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),
622 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
623 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
624 VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),
625 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
626 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
627 VCN, inst_idx, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
628 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
629 VCN, inst_idx, mmUVD_VCPU_NONCACHE_SIZE0),
630 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect);
631
632 /* VCN global tiling registers */
633 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
634 UVD, inst_idx, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
635}
636
637static void vcn_v3_0_disable_static_power_gating(struct amdgpu_device *adev, int inst)
638{
639 uint32_t data = 0;
640
641 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
642 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
643 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
644 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
645 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
646 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
647 | 2 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT
648 | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT
649 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
650 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
651 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
652 | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT
653 | 2 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT
654 | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT
655 | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT);
656
657 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data);
658 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS,
659 UVD_PGFSM_STATUS__UVDM_UVDU_UVDLM_PWR_ON_3_0, 0x3F3FFFFF);
660 } else {
661 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
662 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
663 | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
664 | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
665 | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
666 | 1 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT
667 | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT
668 | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
669 | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
670 | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
671 | 1 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT
672 | 1 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT
673 | 1 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT
674 | 1 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT);
675 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data);
676 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, 0, 0x3F3FFFFF);
677 }
678
679 data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS);
680 data &= ~0x103;
681 if (adev->pg_flags & AMD_PG_SUPPORT_VCN)
682 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON |
683 UVD_POWER_STATUS__UVD_PG_EN_MASK;
684
685 WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data);
686}
687
688static void vcn_v3_0_enable_static_power_gating(struct amdgpu_device *adev, int inst)
689{
690 uint32_t data;
691
692 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
693 /* Before power off, this indicator has to be turned on */
694 data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS);
695 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK;
696 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF;
697 WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data);
698
699 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
700 | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
701 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
702 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
703 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
704 | 2 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT
705 | 2 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT
706 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
707 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
708 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
709 | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT
710 | 2 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT
711 | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT
712 | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT);
713 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data);
714
715 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT
716 | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT
717 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT
718 | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT
719 | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT
720 | 2 << UVD_PGFSM_STATUS__UVDIRL_PWR_STATUS__SHIFT
721 | 2 << UVD_PGFSM_STATUS__UVDLM_PWR_STATUS__SHIFT
722 | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT
723 | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT
724 | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT
725 | 2 << UVD_PGFSM_STATUS__UVDAB_PWR_STATUS__SHIFT
726 | 2 << UVD_PGFSM_STATUS__UVDATD_PWR_STATUS__SHIFT
727 | 2 << UVD_PGFSM_STATUS__UVDNA_PWR_STATUS__SHIFT
728 | 2 << UVD_PGFSM_STATUS__UVDNB_PWR_STATUS__SHIFT);
729 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, data, 0x3F3FFFFF);
730 }
731}
732
733/**
734 * vcn_v3_0_disable_clock_gating - disable VCN clock gating
735 *
736 * @adev: amdgpu_device pointer
737 * @inst: instance number
738 *
739 * Disable clock gating for VCN block
740 */
741static void vcn_v3_0_disable_clock_gating(struct amdgpu_device *adev, int inst)
742{
743 uint32_t data;
744
745 /* VCN disable CGC */
746 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL);
747 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
748 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
749 else
750 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
751 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
752 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
753 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data);
754
755 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_GATE);
756 data &= ~(UVD_CGC_GATE__SYS_MASK
757 | UVD_CGC_GATE__UDEC_MASK
758 | UVD_CGC_GATE__MPEG2_MASK
759 | UVD_CGC_GATE__REGS_MASK
760 | UVD_CGC_GATE__RBC_MASK
761 | UVD_CGC_GATE__LMI_MC_MASK
762 | UVD_CGC_GATE__LMI_UMC_MASK
763 | UVD_CGC_GATE__IDCT_MASK
764 | UVD_CGC_GATE__MPRD_MASK
765 | UVD_CGC_GATE__MPC_MASK
766 | UVD_CGC_GATE__LBSI_MASK
767 | UVD_CGC_GATE__LRBBM_MASK
768 | UVD_CGC_GATE__UDEC_RE_MASK
769 | UVD_CGC_GATE__UDEC_CM_MASK
770 | UVD_CGC_GATE__UDEC_IT_MASK
771 | UVD_CGC_GATE__UDEC_DB_MASK
772 | UVD_CGC_GATE__UDEC_MP_MASK
773 | UVD_CGC_GATE__WCB_MASK
774 | UVD_CGC_GATE__VCPU_MASK
775 | UVD_CGC_GATE__MMSCH_MASK);
776
777 WREG32_SOC15(VCN, inst, mmUVD_CGC_GATE, data);
778
779 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_CGC_GATE, 0, 0xFFFFFFFF);
780
781 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL);
782 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK
783 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
784 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
785 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
786 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
787 | UVD_CGC_CTRL__SYS_MODE_MASK
788 | UVD_CGC_CTRL__UDEC_MODE_MASK
789 | UVD_CGC_CTRL__MPEG2_MODE_MASK
790 | UVD_CGC_CTRL__REGS_MODE_MASK
791 | UVD_CGC_CTRL__RBC_MODE_MASK
792 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
793 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
794 | UVD_CGC_CTRL__IDCT_MODE_MASK
795 | UVD_CGC_CTRL__MPRD_MODE_MASK
796 | UVD_CGC_CTRL__MPC_MODE_MASK
797 | UVD_CGC_CTRL__LBSI_MODE_MASK
798 | UVD_CGC_CTRL__LRBBM_MODE_MASK
799 | UVD_CGC_CTRL__WCB_MODE_MASK
800 | UVD_CGC_CTRL__VCPU_MODE_MASK
801 | UVD_CGC_CTRL__MMSCH_MODE_MASK);
802 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data);
803
804 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE);
805 data |= (UVD_SUVD_CGC_GATE__SRE_MASK
806 | UVD_SUVD_CGC_GATE__SIT_MASK
807 | UVD_SUVD_CGC_GATE__SMP_MASK
808 | UVD_SUVD_CGC_GATE__SCM_MASK
809 | UVD_SUVD_CGC_GATE__SDB_MASK
810 | UVD_SUVD_CGC_GATE__SRE_H264_MASK
811 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
812 | UVD_SUVD_CGC_GATE__SIT_H264_MASK
813 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
814 | UVD_SUVD_CGC_GATE__SCM_H264_MASK
815 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
816 | UVD_SUVD_CGC_GATE__SDB_H264_MASK
817 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
818 | UVD_SUVD_CGC_GATE__SCLR_MASK
819 | UVD_SUVD_CGC_GATE__ENT_MASK
820 | UVD_SUVD_CGC_GATE__IME_MASK
821 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
822 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
823 | UVD_SUVD_CGC_GATE__SITE_MASK
824 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK
825 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK
826 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
827 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK
828 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK
829 | UVD_SUVD_CGC_GATE__EFC_MASK
830 | UVD_SUVD_CGC_GATE__SAOE_MASK
831 | UVD_SUVD_CGC_GATE__SRE_AV1_MASK
832 | UVD_SUVD_CGC_GATE__FBC_PCLK_MASK
833 | UVD_SUVD_CGC_GATE__FBC_CCLK_MASK
834 | UVD_SUVD_CGC_GATE__SCM_AV1_MASK
835 | UVD_SUVD_CGC_GATE__SMPA_MASK);
836 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE, data);
837
838 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2);
839 data |= (UVD_SUVD_CGC_GATE2__MPBE0_MASK
840 | UVD_SUVD_CGC_GATE2__MPBE1_MASK
841 | UVD_SUVD_CGC_GATE2__SIT_AV1_MASK
842 | UVD_SUVD_CGC_GATE2__SDB_AV1_MASK
843 | UVD_SUVD_CGC_GATE2__MPC1_MASK);
844 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2, data);
845
846 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL);
847 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
848 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
849 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
850 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
851 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
852 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
853 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
854 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
855 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK
856 | UVD_SUVD_CGC_CTRL__EFC_MODE_MASK
857 | UVD_SUVD_CGC_CTRL__SAOE_MODE_MASK
858 | UVD_SUVD_CGC_CTRL__SMPA_MODE_MASK
859 | UVD_SUVD_CGC_CTRL__MPBE0_MODE_MASK
860 | UVD_SUVD_CGC_CTRL__MPBE1_MODE_MASK
861 | UVD_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK
862 | UVD_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK
863 | UVD_SUVD_CGC_CTRL__MPC1_MODE_MASK
864 | UVD_SUVD_CGC_CTRL__FBC_PCLK_MASK
865 | UVD_SUVD_CGC_CTRL__FBC_CCLK_MASK);
866 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data);
867}
868
869static void vcn_v3_0_clock_gating_dpg_mode(struct amdgpu_device *adev,
870 uint8_t sram_sel, int inst_idx, uint8_t indirect)
871{
872 uint32_t reg_data = 0;
873
874 /* enable sw clock gating control */
875 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
876 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
877 else
878 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
879 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
880 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
881 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
882 UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
883 UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
884 UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
885 UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
886 UVD_CGC_CTRL__SYS_MODE_MASK |
887 UVD_CGC_CTRL__UDEC_MODE_MASK |
888 UVD_CGC_CTRL__MPEG2_MODE_MASK |
889 UVD_CGC_CTRL__REGS_MODE_MASK |
890 UVD_CGC_CTRL__RBC_MODE_MASK |
891 UVD_CGC_CTRL__LMI_MC_MODE_MASK |
892 UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
893 UVD_CGC_CTRL__IDCT_MODE_MASK |
894 UVD_CGC_CTRL__MPRD_MODE_MASK |
895 UVD_CGC_CTRL__MPC_MODE_MASK |
896 UVD_CGC_CTRL__LBSI_MODE_MASK |
897 UVD_CGC_CTRL__LRBBM_MODE_MASK |
898 UVD_CGC_CTRL__WCB_MODE_MASK |
899 UVD_CGC_CTRL__VCPU_MODE_MASK |
900 UVD_CGC_CTRL__MMSCH_MODE_MASK);
901 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
902 VCN, inst_idx, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
903
904 /* turn off clock gating */
905 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
906 VCN, inst_idx, mmUVD_CGC_GATE), 0, sram_sel, indirect);
907
908 /* turn on SUVD clock gating */
909 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
910 VCN, inst_idx, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
911
912 /* turn on sw mode in UVD_SUVD_CGC_CTRL */
913 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
914 VCN, inst_idx, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
915}
916
917/**
918 * vcn_v3_0_enable_clock_gating - enable VCN clock gating
919 *
920 * @adev: amdgpu_device pointer
921 * @inst: instance number
922 *
923 * Enable clock gating for VCN block
924 */
925static void vcn_v3_0_enable_clock_gating(struct amdgpu_device *adev, int inst)
926{
927 uint32_t data;
928
929 /* enable VCN CGC */
930 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL);
931 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
932 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
933 else
934 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
935 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
936 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
937 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data);
938
939 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL);
940 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK
941 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
942 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
943 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
944 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
945 | UVD_CGC_CTRL__SYS_MODE_MASK
946 | UVD_CGC_CTRL__UDEC_MODE_MASK
947 | UVD_CGC_CTRL__MPEG2_MODE_MASK
948 | UVD_CGC_CTRL__REGS_MODE_MASK
949 | UVD_CGC_CTRL__RBC_MODE_MASK
950 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
951 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
952 | UVD_CGC_CTRL__IDCT_MODE_MASK
953 | UVD_CGC_CTRL__MPRD_MODE_MASK
954 | UVD_CGC_CTRL__MPC_MODE_MASK
955 | UVD_CGC_CTRL__LBSI_MODE_MASK
956 | UVD_CGC_CTRL__LRBBM_MODE_MASK
957 | UVD_CGC_CTRL__WCB_MODE_MASK
958 | UVD_CGC_CTRL__VCPU_MODE_MASK
959 | UVD_CGC_CTRL__MMSCH_MODE_MASK);
960 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data);
961
962 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL);
963 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
964 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
965 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
966 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
967 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
968 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
969 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
970 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
971 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK
972 | UVD_SUVD_CGC_CTRL__EFC_MODE_MASK
973 | UVD_SUVD_CGC_CTRL__SAOE_MODE_MASK
974 | UVD_SUVD_CGC_CTRL__SMPA_MODE_MASK
975 | UVD_SUVD_CGC_CTRL__MPBE0_MODE_MASK
976 | UVD_SUVD_CGC_CTRL__MPBE1_MODE_MASK
977 | UVD_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK
978 | UVD_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK
979 | UVD_SUVD_CGC_CTRL__MPC1_MODE_MASK
980 | UVD_SUVD_CGC_CTRL__FBC_PCLK_MASK
981 | UVD_SUVD_CGC_CTRL__FBC_CCLK_MASK);
982 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data);
983}
984
985static int vcn_v3_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
986{
987 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
988 struct amdgpu_ring *ring;
989 uint32_t rb_bufsz, tmp;
990
991 /* disable register anti-hang mechanism */
992 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1,
993 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
994 /* enable dynamic power gating mode */
995 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS);
996 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
997 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK;
998 WREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS, tmp);
999
1000 if (indirect)
1001 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr;
1002
1003 /* enable clock gating */
1004 vcn_v3_0_clock_gating_dpg_mode(adev, 0, inst_idx, indirect);
1005
1006 /* enable VCPU clock */
1007 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
1008 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
1009 tmp |= UVD_VCPU_CNTL__BLK_RST_MASK;
1010 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
1011 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);
1012
1013 /* disable master interupt */
1014 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
1015 VCN, inst_idx, mmUVD_MASTINT_EN), 0, 0, indirect);
1016
1017 /* setup mmUVD_LMI_CTRL */
1018 tmp = (0x8 | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
1019 UVD_LMI_CTRL__REQ_MODE_MASK |
1020 UVD_LMI_CTRL__CRC_RESET_MASK |
1021 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
1022 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
1023 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
1024 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
1025 0x00100000L);
1026 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
1027 VCN, inst_idx, mmUVD_LMI_CTRL), tmp, 0, indirect);
1028
1029 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
1030 VCN, inst_idx, mmUVD_MPC_CNTL),
1031 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);
1032
1033 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
1034 VCN, inst_idx, mmUVD_MPC_SET_MUXA0),
1035 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
1036 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
1037 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
1038 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);
1039
1040 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
1041 VCN, inst_idx, mmUVD_MPC_SET_MUXB0),
1042 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
1043 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
1044 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
1045 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);
1046
1047 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
1048 VCN, inst_idx, mmUVD_MPC_SET_MUX),
1049 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
1050 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
1051 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
1052
1053 vcn_v3_0_mc_resume_dpg_mode(adev, inst_idx, indirect);
1054
1055 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
1056 VCN, inst_idx, mmUVD_REG_XX_MASK), 0x10, 0, indirect);
1057 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
1058 VCN, inst_idx, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);
1059
1060 /* enable LMI MC and UMC channels */
1061 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
1062 VCN, inst_idx, mmUVD_LMI_CTRL2), 0, 0, indirect);
1063
1064 /* unblock VCPU register access */
1065 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
1066 VCN, inst_idx, mmUVD_RB_ARB_CTRL), 0, 0, indirect);
1067
1068 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
1069 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
1070 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
1071 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);
1072
1073 /* enable master interrupt */
1074 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
1075 VCN, inst_idx, mmUVD_MASTINT_EN),
1076 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
1077
1078 /* add nop to workaround PSP size check */
1079 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
1080 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);
1081
1082 if (indirect)
1083 amdgpu_vcn_psp_update_sram(adev, inst_idx, 0);
1084
1085 ring = &adev->vcn.inst[inst_idx].ring_dec;
1086 /* force RBC into idle state */
1087 rb_bufsz = order_base_2(ring->ring_size);
1088 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
1089 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1090 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1091 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1092 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1093 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_CNTL, tmp);
1094
1095 /* Stall DPG before WPTR/RPTR reset */
1096 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),
1097 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK,
1098 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
1099 fw_shared->multi_queue.decode_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);
1100
1101 /* set the write pointer delay */
1102 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR_CNTL, 0);
1103
1104 /* set the wb address */
1105 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR_ADDR,
1106 (upper_32_bits(ring->gpu_addr) >> 2));
1107
1108 /* programm the RB_BASE for ring buffer */
1109 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
1110 lower_32_bits(ring->gpu_addr));
1111 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
1112 upper_32_bits(ring->gpu_addr));
1113
1114 /* Initialize the ring buffer's read and write pointers */
1115 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, 0);
1116
1117 WREG32_SOC15(VCN, inst_idx, mmUVD_SCRATCH2, 0);
1118
1119 ring->wptr = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR);
1120 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR,
1121 lower_32_bits(ring->wptr));
1122
1123 /* Reset FW shared memory RBC WPTR/RPTR */
1124 fw_shared->rb.rptr = 0;
1125 fw_shared->rb.wptr = lower_32_bits(ring->wptr);
1126
1127 /*resetting done, fw can check RB ring */
1128 fw_shared->multi_queue.decode_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET);
1129
1130 /* Unstall DPG */
1131 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),
1132 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
1133
1134 return 0;
1135}
1136
1137static int vcn_v3_0_start(struct amdgpu_device *adev)
1138{
1139 volatile struct amdgpu_fw_shared *fw_shared;
1140 struct amdgpu_ring *ring;
1141 uint32_t rb_bufsz, tmp;
1142 int i, j, k, r;
1143
1144 if (adev->pm.dpm_enabled)
1145 amdgpu_dpm_enable_uvd(adev, true);
1146
1147 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1148 if (adev->vcn.harvest_config & (1 << i))
1149 continue;
1150
1151 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1152 r = vcn_v3_0_start_dpg_mode(adev, i, adev->vcn.indirect_sram);
1153 continue;
1154 }
1155
1156 /* disable VCN power gating */
1157 vcn_v3_0_disable_static_power_gating(adev, i);
1158
1159 /* set VCN status busy */
1160 tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;
1161 WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp);
1162
1163 /*SW clock gating */
1164 vcn_v3_0_disable_clock_gating(adev, i);
1165
1166 /* enable VCPU clock */
1167 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
1168 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
1169
1170 /* disable master interrupt */
1171 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0,
1172 ~UVD_MASTINT_EN__VCPU_EN_MASK);
1173
1174 /* enable LMI MC and UMC channels */
1175 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_LMI_CTRL2), 0,
1176 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
1177
1178 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET);
1179 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
1180 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
1181 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp);
1182
1183 /* setup mmUVD_LMI_CTRL */
1184 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL);
1185 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL, tmp |
1186 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
1187 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
1188 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
1189 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
1190
1191 /* setup mmUVD_MPC_CNTL */
1192 tmp = RREG32_SOC15(VCN, i, mmUVD_MPC_CNTL);
1193 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
1194 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
1195 WREG32_SOC15(VCN, i, mmUVD_MPC_CNTL, tmp);
1196
1197 /* setup UVD_MPC_SET_MUXA0 */
1198 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXA0,
1199 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
1200 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
1201 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
1202 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
1203
1204 /* setup UVD_MPC_SET_MUXB0 */
1205 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXB0,
1206 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
1207 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
1208 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
1209 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
1210
1211 /* setup mmUVD_MPC_SET_MUX */
1212 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUX,
1213 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
1214 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
1215 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
1216
1217 vcn_v3_0_mc_resume(adev, i);
1218
1219 /* VCN global tiling registers */
1220 WREG32_SOC15(VCN, i, mmUVD_GFX10_ADDR_CONFIG,
1221 adev->gfx.config.gb_addr_config);
1222
1223 /* unblock VCPU register access */
1224 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 0,
1225 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
1226
1227 /* release VCPU reset to boot */
1228 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,
1229 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1230
1231 for (j = 0; j < 10; ++j) {
1232 uint32_t status;
1233
1234 for (k = 0; k < 100; ++k) {
1235 status = RREG32_SOC15(VCN, i, mmUVD_STATUS);
1236 if (status & 2)
1237 break;
1238 mdelay(10);
1239 }
1240 r = 0;
1241 if (status & 2)
1242 break;
1243
1244 DRM_ERROR("VCN[%d] decode not responding, trying to reset the VCPU!!!\n", i);
1245 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
1246 UVD_VCPU_CNTL__BLK_RST_MASK,
1247 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1248 mdelay(10);
1249 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,
1250 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1251
1252 mdelay(10);
1253 r = -1;
1254 }
1255
1256 if (r) {
1257 DRM_ERROR("VCN[%d] decode not responding, giving up!!!\n", i);
1258 return r;
1259 }
1260
1261 /* enable master interrupt */
1262 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN),
1263 UVD_MASTINT_EN__VCPU_EN_MASK,
1264 ~UVD_MASTINT_EN__VCPU_EN_MASK);
1265
1266 /* clear the busy bit of VCN_STATUS */
1267 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0,
1268 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
1269
1270 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_VMID, 0);
1271
1272 ring = &adev->vcn.inst[i].ring_dec;
1273 /* force RBC into idle state */
1274 rb_bufsz = order_base_2(ring->ring_size);
1275 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
1276 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1277 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1278 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1279 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1280 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_CNTL, tmp);
1281
1282 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
1283 fw_shared->multi_queue.decode_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);
1284
1285 /* programm the RB_BASE for ring buffer */
1286 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
1287 lower_32_bits(ring->gpu_addr));
1288 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
1289 upper_32_bits(ring->gpu_addr));
1290
1291 /* Initialize the ring buffer's read and write pointers */
1292 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR, 0);
1293
1294 WREG32_SOC15(VCN, i, mmUVD_SCRATCH2, 0);
1295 ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR);
1296 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR,
1297 lower_32_bits(ring->wptr));
1298 fw_shared->rb.wptr = lower_32_bits(ring->wptr);
1299 fw_shared->multi_queue.decode_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET);
1300
1301 if (amdgpu_ip_version(adev, UVD_HWIP, 0) !=
1302 IP_VERSION(3, 0, 33)) {
1303 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);
1304 ring = &adev->vcn.inst[i].ring_enc[0];
1305 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1306 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1307 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring->gpu_addr);
1308 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1309 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring->ring_size / 4);
1310 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET);
1311
1312 fw_shared->multi_queue.encode_lowlatency_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);
1313 ring = &adev->vcn.inst[i].ring_enc[1];
1314 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1315 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1316 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1317 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1318 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring->ring_size / 4);
1319 fw_shared->multi_queue.encode_lowlatency_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET);
1320 }
1321 }
1322
1323 return 0;
1324}
1325
1326static int vcn_v3_0_start_sriov(struct amdgpu_device *adev)
1327{
1328 int i, j;
1329 struct amdgpu_ring *ring;
1330 uint64_t cache_addr;
1331 uint64_t rb_addr;
1332 uint64_t ctx_addr;
1333 uint32_t param, resp, expected;
1334 uint32_t offset, cache_size;
1335 uint32_t tmp, timeout;
1336
1337 struct amdgpu_mm_table *table = &adev->virt.mm_table;
1338 uint32_t *table_loc;
1339 uint32_t table_size;
1340 uint32_t size, size_dw;
1341
1342 struct mmsch_v3_0_cmd_direct_write
1343 direct_wt = { {0} };
1344 struct mmsch_v3_0_cmd_direct_read_modify_write
1345 direct_rd_mod_wt = { {0} };
1346 struct mmsch_v3_0_cmd_end end = { {0} };
1347 struct mmsch_v3_0_init_header header;
1348
1349 direct_wt.cmd_header.command_type =
1350 MMSCH_COMMAND__DIRECT_REG_WRITE;
1351 direct_rd_mod_wt.cmd_header.command_type =
1352 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE;
1353 end.cmd_header.command_type =
1354 MMSCH_COMMAND__END;
1355
1356 header.version = MMSCH_VERSION;
1357 header.total_size = sizeof(struct mmsch_v3_0_init_header) >> 2;
1358 for (i = 0; i < MMSCH_V3_0_VCN_INSTANCES; i++) {
1359 header.inst[i].init_status = 0;
1360 header.inst[i].table_offset = 0;
1361 header.inst[i].table_size = 0;
1362 }
1363
1364 table_loc = (uint32_t *)table->cpu_addr;
1365 table_loc += header.total_size;
1366 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1367 if (adev->vcn.harvest_config & (1 << i))
1368 continue;
1369
1370 table_size = 0;
1371
1372 MMSCH_V3_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, i,
1373 mmUVD_STATUS),
1374 ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY);
1375
1376 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[i]->size + 4);
1377
1378 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1379 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1380 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
1381 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo);
1382 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1383 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
1384 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi);
1385 offset = 0;
1386 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1387 mmUVD_VCPU_CACHE_OFFSET0),
1388 0);
1389 } else {
1390 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1391 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
1392 lower_32_bits(adev->vcn.inst[i].gpu_addr));
1393 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1394 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
1395 upper_32_bits(adev->vcn.inst[i].gpu_addr));
1396 offset = cache_size;
1397 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1398 mmUVD_VCPU_CACHE_OFFSET0),
1399 AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
1400 }
1401
1402 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1403 mmUVD_VCPU_CACHE_SIZE0),
1404 cache_size);
1405
1406 cache_addr = adev->vcn.inst[i].gpu_addr + offset;
1407 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1408 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
1409 lower_32_bits(cache_addr));
1410 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1411 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
1412 upper_32_bits(cache_addr));
1413 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1414 mmUVD_VCPU_CACHE_OFFSET1),
1415 0);
1416 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1417 mmUVD_VCPU_CACHE_SIZE1),
1418 AMDGPU_VCN_STACK_SIZE);
1419
1420 cache_addr = adev->vcn.inst[i].gpu_addr + offset +
1421 AMDGPU_VCN_STACK_SIZE;
1422 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1423 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
1424 lower_32_bits(cache_addr));
1425 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1426 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
1427 upper_32_bits(cache_addr));
1428 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1429 mmUVD_VCPU_CACHE_OFFSET2),
1430 0);
1431 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1432 mmUVD_VCPU_CACHE_SIZE2),
1433 AMDGPU_VCN_CONTEXT_SIZE);
1434
1435 for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
1436 ring = &adev->vcn.inst[i].ring_enc[j];
1437 ring->wptr = 0;
1438 rb_addr = ring->gpu_addr;
1439 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1440 mmUVD_RB_BASE_LO),
1441 lower_32_bits(rb_addr));
1442 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1443 mmUVD_RB_BASE_HI),
1444 upper_32_bits(rb_addr));
1445 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1446 mmUVD_RB_SIZE),
1447 ring->ring_size / 4);
1448 }
1449
1450 ring = &adev->vcn.inst[i].ring_dec;
1451 ring->wptr = 0;
1452 rb_addr = ring->gpu_addr;
1453 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1454 mmUVD_LMI_RBC_RB_64BIT_BAR_LOW),
1455 lower_32_bits(rb_addr));
1456 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1457 mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH),
1458 upper_32_bits(rb_addr));
1459 /* force RBC into idle state */
1460 tmp = order_base_2(ring->ring_size);
1461 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, tmp);
1462 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1463 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1464 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1465 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1466 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1467 mmUVD_RBC_RB_CNTL),
1468 tmp);
1469
1470 /* add end packet */
1471 MMSCH_V3_0_INSERT_END();
1472
1473 /* refine header */
1474 header.inst[i].init_status = 0;
1475 header.inst[i].table_offset = header.total_size;
1476 header.inst[i].table_size = table_size;
1477 header.total_size += table_size;
1478 }
1479
1480 /* Update init table header in memory */
1481 size = sizeof(struct mmsch_v3_0_init_header);
1482 table_loc = (uint32_t *)table->cpu_addr;
1483 memcpy((void *)table_loc, &header, size);
1484
1485 /* message MMSCH (in VCN[0]) to initialize this client
1486 * 1, write to mmsch_vf_ctx_addr_lo/hi register with GPU mc addr
1487 * of memory descriptor location
1488 */
1489 ctx_addr = table->gpu_addr;
1490 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr));
1491 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr));
1492
1493 /* 2, update vmid of descriptor */
1494 tmp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID);
1495 tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK;
1496 /* use domain0 for MM scheduler */
1497 tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT);
1498 WREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID, tmp);
1499
1500 /* 3, notify mmsch about the size of this descriptor */
1501 size = header.total_size;
1502 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_SIZE, size);
1503
1504 /* 4, set resp to zero */
1505 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP, 0);
1506
1507 /* 5, kick off the initialization and wait until
1508 * MMSCH_VF_MAILBOX_RESP becomes non-zero
1509 */
1510 param = 0x10000001;
1511 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_HOST, param);
1512 tmp = 0;
1513 timeout = 1000;
1514 resp = 0;
1515 expected = param + 1;
1516 while (resp != expected) {
1517 resp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP);
1518 if (resp == expected)
1519 break;
1520
1521 udelay(10);
1522 tmp = tmp + 10;
1523 if (tmp >= timeout) {
1524 DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\
1525 " waiting for mmMMSCH_VF_MAILBOX_RESP "\
1526 "(expected=0x%08x, readback=0x%08x)\n",
1527 tmp, expected, resp);
1528 return -EBUSY;
1529 }
1530 }
1531
1532 return 0;
1533}
1534
1535static int vcn_v3_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)
1536{
1537 struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__UNPAUSE};
1538 uint32_t tmp;
1539
1540 vcn_v3_0_pause_dpg_mode(adev, inst_idx, &state);
1541
1542 /* Wait for power status to be 1 */
1543 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1,
1544 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1545
1546 /* wait for read ptr to be equal to write ptr */
1547 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR);
1548 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF);
1549
1550 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2);
1551 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF);
1552
1553 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;
1554 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF);
1555
1556 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1,
1557 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1558
1559 /* disable dynamic power gating mode */
1560 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 0,
1561 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
1562
1563 return 0;
1564}
1565
1566static int vcn_v3_0_stop(struct amdgpu_device *adev)
1567{
1568 uint32_t tmp;
1569 int i, r = 0;
1570
1571 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1572 if (adev->vcn.harvest_config & (1 << i))
1573 continue;
1574
1575 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1576 r = vcn_v3_0_stop_dpg_mode(adev, i);
1577 continue;
1578 }
1579
1580 /* wait for vcn idle */
1581 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7);
1582 if (r)
1583 return r;
1584
1585 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
1586 UVD_LMI_STATUS__READ_CLEAN_MASK |
1587 UVD_LMI_STATUS__WRITE_CLEAN_MASK |
1588 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
1589 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp);
1590 if (r)
1591 return r;
1592
1593 /* disable LMI UMC channel */
1594 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2);
1595 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
1596 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp);
1597 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK|
1598 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
1599 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp);
1600 if (r)
1601 return r;
1602
1603 /* block VCPU register access */
1604 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL),
1605 UVD_RB_ARB_CTRL__VCPU_DIS_MASK,
1606 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
1607
1608 /* reset VCPU */
1609 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
1610 UVD_VCPU_CNTL__BLK_RST_MASK,
1611 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1612
1613 /* disable VCPU clock */
1614 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,
1615 ~(UVD_VCPU_CNTL__CLK_EN_MASK));
1616
1617 /* apply soft reset */
1618 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET);
1619 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
1620 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp);
1621 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET);
1622 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
1623 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp);
1624
1625 /* clear status */
1626 WREG32_SOC15(VCN, i, mmUVD_STATUS, 0);
1627
1628 /* apply HW clock gating */
1629 vcn_v3_0_enable_clock_gating(adev, i);
1630
1631 /* enable VCN power gating */
1632 vcn_v3_0_enable_static_power_gating(adev, i);
1633 }
1634
1635 if (adev->pm.dpm_enabled)
1636 amdgpu_dpm_enable_uvd(adev, false);
1637
1638 return 0;
1639}
1640
1641static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev,
1642 int inst_idx, struct dpg_pause_state *new_state)
1643{
1644 volatile struct amdgpu_fw_shared *fw_shared;
1645 struct amdgpu_ring *ring;
1646 uint32_t reg_data = 0;
1647 int ret_code;
1648
1649 /* pause/unpause if state is changed */
1650 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {
1651 DRM_DEBUG("dpg pause state changed %d -> %d",
1652 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based);
1653 reg_data = RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE) &
1654 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1655
1656 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) {
1657 ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1,
1658 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1659
1660 if (!ret_code) {
1661 /* pause DPG */
1662 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1663 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data);
1664
1665 /* wait for ACK */
1666 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_DPG_PAUSE,
1667 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK,
1668 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1669
1670 /* Stall DPG before WPTR/RPTR reset */
1671 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),
1672 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK,
1673 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
1674
1675 if (amdgpu_ip_version(adev, UVD_HWIP, 0) !=
1676 IP_VERSION(3, 0, 33)) {
1677 /* Restore */
1678 fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
1679 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);
1680 ring = &adev->vcn.inst[inst_idx].ring_enc[0];
1681 ring->wptr = 0;
1682 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO, ring->gpu_addr);
1683 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1684 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE, ring->ring_size / 4);
1685 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1686 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1687 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET);
1688
1689 fw_shared->multi_queue.encode_lowlatency_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);
1690 ring = &adev->vcn.inst[inst_idx].ring_enc[1];
1691 ring->wptr = 0;
1692 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1693 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1694 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE2, ring->ring_size / 4);
1695 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1696 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1697 fw_shared->multi_queue.encode_lowlatency_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET);
1698
1699 /* restore wptr/rptr with pointers saved in FW shared memory*/
1700 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, fw_shared->rb.rptr);
1701 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, fw_shared->rb.wptr);
1702 }
1703
1704 /* Unstall DPG */
1705 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),
1706 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
1707
1708 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS,
1709 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1710 }
1711 } else {
1712 /* unpause dpg, no need to wait */
1713 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1714 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data);
1715 }
1716 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;
1717 }
1718
1719 return 0;
1720}
1721
1722/**
1723 * vcn_v3_0_dec_ring_get_rptr - get read pointer
1724 *
1725 * @ring: amdgpu_ring pointer
1726 *
1727 * Returns the current hardware read pointer
1728 */
1729static uint64_t vcn_v3_0_dec_ring_get_rptr(struct amdgpu_ring *ring)
1730{
1731 struct amdgpu_device *adev = ring->adev;
1732
1733 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_RPTR);
1734}
1735
1736/**
1737 * vcn_v3_0_dec_ring_get_wptr - get write pointer
1738 *
1739 * @ring: amdgpu_ring pointer
1740 *
1741 * Returns the current hardware write pointer
1742 */
1743static uint64_t vcn_v3_0_dec_ring_get_wptr(struct amdgpu_ring *ring)
1744{
1745 struct amdgpu_device *adev = ring->adev;
1746
1747 if (ring->use_doorbell)
1748 return *ring->wptr_cpu_addr;
1749 else
1750 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR);
1751}
1752
1753/**
1754 * vcn_v3_0_dec_ring_set_wptr - set write pointer
1755 *
1756 * @ring: amdgpu_ring pointer
1757 *
1758 * Commits the write pointer to the hardware
1759 */
1760static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
1761{
1762 struct amdgpu_device *adev = ring->adev;
1763 volatile struct amdgpu_fw_shared *fw_shared;
1764
1765 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1766 /*whenever update RBC_RB_WPTR, we save the wptr in shared rb.wptr and scratch2 */
1767 fw_shared = adev->vcn.inst[ring->me].fw_shared.cpu_addr;
1768 fw_shared->rb.wptr = lower_32_bits(ring->wptr);
1769 WREG32_SOC15(VCN, ring->me, mmUVD_SCRATCH2,
1770 lower_32_bits(ring->wptr));
1771 }
1772
1773 if (ring->use_doorbell) {
1774 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
1775 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1776 } else {
1777 WREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
1778 }
1779}
1780
1781static const struct amdgpu_ring_funcs vcn_v3_0_dec_sw_ring_vm_funcs = {
1782 .type = AMDGPU_RING_TYPE_VCN_DEC,
1783 .align_mask = 0x3f,
1784 .nop = VCN_DEC_SW_CMD_NO_OP,
1785 .secure_submission_supported = true,
1786 .get_rptr = vcn_v3_0_dec_ring_get_rptr,
1787 .get_wptr = vcn_v3_0_dec_ring_get_wptr,
1788 .set_wptr = vcn_v3_0_dec_ring_set_wptr,
1789 .emit_frame_size =
1790 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1791 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
1792 VCN_SW_RING_EMIT_FRAME_SIZE,
1793 .emit_ib_size = 5, /* vcn_dec_sw_ring_emit_ib */
1794 .emit_ib = vcn_dec_sw_ring_emit_ib,
1795 .emit_fence = vcn_dec_sw_ring_emit_fence,
1796 .emit_vm_flush = vcn_dec_sw_ring_emit_vm_flush,
1797 .test_ring = amdgpu_vcn_dec_sw_ring_test_ring,
1798 .test_ib = NULL,//amdgpu_vcn_dec_sw_ring_test_ib,
1799 .insert_nop = amdgpu_ring_insert_nop,
1800 .insert_end = vcn_dec_sw_ring_insert_end,
1801 .pad_ib = amdgpu_ring_generic_pad_ib,
1802 .begin_use = amdgpu_vcn_ring_begin_use,
1803 .end_use = amdgpu_vcn_ring_end_use,
1804 .emit_wreg = vcn_dec_sw_ring_emit_wreg,
1805 .emit_reg_wait = vcn_dec_sw_ring_emit_reg_wait,
1806 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1807};
1808
1809static int vcn_v3_0_limit_sched(struct amdgpu_cs_parser *p,
1810 struct amdgpu_job *job)
1811{
1812 struct drm_gpu_scheduler **scheds;
1813
1814 /* The create msg must be in the first IB submitted */
1815 if (atomic_read(&job->base.entity->fence_seq))
1816 return -EINVAL;
1817
1818 /* if VCN0 is harvested, we can't support AV1 */
1819 if (p->adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0)
1820 return -EINVAL;
1821
1822 scheds = p->adev->gpu_sched[AMDGPU_HW_IP_VCN_DEC]
1823 [AMDGPU_RING_PRIO_DEFAULT].sched;
1824 drm_sched_entity_modify_sched(job->base.entity, scheds, 1);
1825 return 0;
1826}
1827
1828static int vcn_v3_0_dec_msg(struct amdgpu_cs_parser *p, struct amdgpu_job *job,
1829 uint64_t addr)
1830{
1831 struct ttm_operation_ctx ctx = { false, false };
1832 struct amdgpu_bo_va_mapping *map;
1833 uint32_t *msg, num_buffers;
1834 struct amdgpu_bo *bo;
1835 uint64_t start, end;
1836 unsigned int i;
1837 void *ptr;
1838 int r;
1839
1840 addr &= AMDGPU_GMC_HOLE_MASK;
1841 r = amdgpu_cs_find_mapping(p, addr, &bo, &map);
1842 if (r) {
1843 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr);
1844 return r;
1845 }
1846
1847 start = map->start * AMDGPU_GPU_PAGE_SIZE;
1848 end = (map->last + 1) * AMDGPU_GPU_PAGE_SIZE;
1849 if (addr & 0x7) {
1850 DRM_ERROR("VCN messages must be 8 byte aligned!\n");
1851 return -EINVAL;
1852 }
1853
1854 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
1855 amdgpu_bo_placement_from_domain(bo, bo->allowed_domains);
1856 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
1857 if (r) {
1858 DRM_ERROR("Failed validating the VCN message BO (%d)!\n", r);
1859 return r;
1860 }
1861
1862 r = amdgpu_bo_kmap(bo, &ptr);
1863 if (r) {
1864 DRM_ERROR("Failed mapping the VCN message (%d)!\n", r);
1865 return r;
1866 }
1867
1868 msg = ptr + addr - start;
1869
1870 /* Check length */
1871 if (msg[1] > end - addr) {
1872 r = -EINVAL;
1873 goto out;
1874 }
1875
1876 if (msg[3] != RDECODE_MSG_CREATE)
1877 goto out;
1878
1879 num_buffers = msg[2];
1880 for (i = 0, msg = &msg[6]; i < num_buffers; ++i, msg += 4) {
1881 uint32_t offset, size, *create;
1882
1883 if (msg[0] != RDECODE_MESSAGE_CREATE)
1884 continue;
1885
1886 offset = msg[1];
1887 size = msg[2];
1888
1889 if (offset + size > end) {
1890 r = -EINVAL;
1891 goto out;
1892 }
1893
1894 create = ptr + addr + offset - start;
1895
1896 /* H246, HEVC and VP9 can run on any instance */
1897 if (create[0] == 0x7 || create[0] == 0x10 || create[0] == 0x11)
1898 continue;
1899
1900 r = vcn_v3_0_limit_sched(p, job);
1901 if (r)
1902 goto out;
1903 }
1904
1905out:
1906 amdgpu_bo_kunmap(bo);
1907 return r;
1908}
1909
1910static int vcn_v3_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p,
1911 struct amdgpu_job *job,
1912 struct amdgpu_ib *ib)
1913{
1914 struct amdgpu_ring *ring = amdgpu_job_ring(job);
1915 uint32_t msg_lo = 0, msg_hi = 0;
1916 unsigned i;
1917 int r;
1918
1919 /* The first instance can decode anything */
1920 if (!ring->me)
1921 return 0;
1922
1923 for (i = 0; i < ib->length_dw; i += 2) {
1924 uint32_t reg = amdgpu_ib_get_value(ib, i);
1925 uint32_t val = amdgpu_ib_get_value(ib, i + 1);
1926
1927 if (reg == PACKET0(p->adev->vcn.internal.data0, 0)) {
1928 msg_lo = val;
1929 } else if (reg == PACKET0(p->adev->vcn.internal.data1, 0)) {
1930 msg_hi = val;
1931 } else if (reg == PACKET0(p->adev->vcn.internal.cmd, 0) &&
1932 val == 0) {
1933 r = vcn_v3_0_dec_msg(p, job,
1934 ((u64)msg_hi) << 32 | msg_lo);
1935 if (r)
1936 return r;
1937 }
1938 }
1939 return 0;
1940}
1941
1942static const struct amdgpu_ring_funcs vcn_v3_0_dec_ring_vm_funcs = {
1943 .type = AMDGPU_RING_TYPE_VCN_DEC,
1944 .align_mask = 0xf,
1945 .secure_submission_supported = true,
1946 .get_rptr = vcn_v3_0_dec_ring_get_rptr,
1947 .get_wptr = vcn_v3_0_dec_ring_get_wptr,
1948 .set_wptr = vcn_v3_0_dec_ring_set_wptr,
1949 .patch_cs_in_place = vcn_v3_0_ring_patch_cs_in_place,
1950 .emit_frame_size =
1951 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
1952 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
1953 8 + /* vcn_v2_0_dec_ring_emit_vm_flush */
1954 14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */
1955 6,
1956 .emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */
1957 .emit_ib = vcn_v2_0_dec_ring_emit_ib,
1958 .emit_fence = vcn_v2_0_dec_ring_emit_fence,
1959 .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush,
1960 .test_ring = vcn_v2_0_dec_ring_test_ring,
1961 .test_ib = amdgpu_vcn_dec_ring_test_ib,
1962 .insert_nop = vcn_v2_0_dec_ring_insert_nop,
1963 .insert_start = vcn_v2_0_dec_ring_insert_start,
1964 .insert_end = vcn_v2_0_dec_ring_insert_end,
1965 .pad_ib = amdgpu_ring_generic_pad_ib,
1966 .begin_use = amdgpu_vcn_ring_begin_use,
1967 .end_use = amdgpu_vcn_ring_end_use,
1968 .emit_wreg = vcn_v2_0_dec_ring_emit_wreg,
1969 .emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait,
1970 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1971};
1972
1973/**
1974 * vcn_v3_0_enc_ring_get_rptr - get enc read pointer
1975 *
1976 * @ring: amdgpu_ring pointer
1977 *
1978 * Returns the current hardware enc read pointer
1979 */
1980static uint64_t vcn_v3_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
1981{
1982 struct amdgpu_device *adev = ring->adev;
1983
1984 if (ring == &adev->vcn.inst[ring->me].ring_enc[0])
1985 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR);
1986 else
1987 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR2);
1988}
1989
1990/**
1991 * vcn_v3_0_enc_ring_get_wptr - get enc write pointer
1992 *
1993 * @ring: amdgpu_ring pointer
1994 *
1995 * Returns the current hardware enc write pointer
1996 */
1997static uint64_t vcn_v3_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
1998{
1999 struct amdgpu_device *adev = ring->adev;
2000
2001 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) {
2002 if (ring->use_doorbell)
2003 return *ring->wptr_cpu_addr;
2004 else
2005 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR);
2006 } else {
2007 if (ring->use_doorbell)
2008 return *ring->wptr_cpu_addr;
2009 else
2010 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2);
2011 }
2012}
2013
2014/**
2015 * vcn_v3_0_enc_ring_set_wptr - set enc write pointer
2016 *
2017 * @ring: amdgpu_ring pointer
2018 *
2019 * Commits the enc write pointer to the hardware
2020 */
2021static void vcn_v3_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
2022{
2023 struct amdgpu_device *adev = ring->adev;
2024
2025 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) {
2026 if (ring->use_doorbell) {
2027 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
2028 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
2029 } else {
2030 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
2031 }
2032 } else {
2033 if (ring->use_doorbell) {
2034 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
2035 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
2036 } else {
2037 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
2038 }
2039 }
2040}
2041
2042static const struct amdgpu_ring_funcs vcn_v3_0_enc_ring_vm_funcs = {
2043 .type = AMDGPU_RING_TYPE_VCN_ENC,
2044 .align_mask = 0x3f,
2045 .nop = VCN_ENC_CMD_NO_OP,
2046 .get_rptr = vcn_v3_0_enc_ring_get_rptr,
2047 .get_wptr = vcn_v3_0_enc_ring_get_wptr,
2048 .set_wptr = vcn_v3_0_enc_ring_set_wptr,
2049 .emit_frame_size =
2050 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2051 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
2052 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */
2053 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */
2054 1, /* vcn_v2_0_enc_ring_insert_end */
2055 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */
2056 .emit_ib = vcn_v2_0_enc_ring_emit_ib,
2057 .emit_fence = vcn_v2_0_enc_ring_emit_fence,
2058 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush,
2059 .test_ring = amdgpu_vcn_enc_ring_test_ring,
2060 .test_ib = amdgpu_vcn_enc_ring_test_ib,
2061 .insert_nop = amdgpu_ring_insert_nop,
2062 .insert_end = vcn_v2_0_enc_ring_insert_end,
2063 .pad_ib = amdgpu_ring_generic_pad_ib,
2064 .begin_use = amdgpu_vcn_ring_begin_use,
2065 .end_use = amdgpu_vcn_ring_end_use,
2066 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg,
2067 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait,
2068 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2069};
2070
2071static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev)
2072{
2073 int i;
2074
2075 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
2076 if (adev->vcn.harvest_config & (1 << i))
2077 continue;
2078
2079 if (!DEC_SW_RING_ENABLED)
2080 adev->vcn.inst[i].ring_dec.funcs = &vcn_v3_0_dec_ring_vm_funcs;
2081 else
2082 adev->vcn.inst[i].ring_dec.funcs = &vcn_v3_0_dec_sw_ring_vm_funcs;
2083 adev->vcn.inst[i].ring_dec.me = i;
2084 }
2085}
2086
2087static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev)
2088{
2089 int i, j;
2090
2091 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
2092 if (adev->vcn.harvest_config & (1 << i))
2093 continue;
2094
2095 for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
2096 adev->vcn.inst[i].ring_enc[j].funcs = &vcn_v3_0_enc_ring_vm_funcs;
2097 adev->vcn.inst[i].ring_enc[j].me = i;
2098 }
2099 }
2100}
2101
2102static bool vcn_v3_0_is_idle(void *handle)
2103{
2104 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2105 int i, ret = 1;
2106
2107 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
2108 if (adev->vcn.harvest_config & (1 << i))
2109 continue;
2110
2111 ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE);
2112 }
2113
2114 return ret;
2115}
2116
2117static int vcn_v3_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
2118{
2119 struct amdgpu_device *adev = ip_block->adev;
2120 int i, ret = 0;
2121
2122 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
2123 if (adev->vcn.harvest_config & (1 << i))
2124 continue;
2125
2126 ret = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE,
2127 UVD_STATUS__IDLE);
2128 if (ret)
2129 return ret;
2130 }
2131
2132 return ret;
2133}
2134
2135static int vcn_v3_0_set_clockgating_state(void *handle,
2136 enum amd_clockgating_state state)
2137{
2138 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2139 bool enable = state == AMD_CG_STATE_GATE;
2140 int i;
2141
2142 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
2143 if (adev->vcn.harvest_config & (1 << i))
2144 continue;
2145
2146 if (enable) {
2147 if (RREG32_SOC15(VCN, i, mmUVD_STATUS) != UVD_STATUS__IDLE)
2148 return -EBUSY;
2149 vcn_v3_0_enable_clock_gating(adev, i);
2150 } else {
2151 vcn_v3_0_disable_clock_gating(adev, i);
2152 }
2153 }
2154
2155 return 0;
2156}
2157
2158static int vcn_v3_0_set_powergating_state(void *handle,
2159 enum amd_powergating_state state)
2160{
2161 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2162 int ret;
2163
2164 /* for SRIOV, guest should not control VCN Power-gating
2165 * MMSCH FW should control Power-gating and clock-gating
2166 * guest should avoid touching CGC and PG
2167 */
2168 if (amdgpu_sriov_vf(adev)) {
2169 adev->vcn.cur_state = AMD_PG_STATE_UNGATE;
2170 return 0;
2171 }
2172
2173 if (state == adev->vcn.cur_state)
2174 return 0;
2175
2176 if (state == AMD_PG_STATE_GATE)
2177 ret = vcn_v3_0_stop(adev);
2178 else
2179 ret = vcn_v3_0_start(adev);
2180
2181 if (!ret)
2182 adev->vcn.cur_state = state;
2183
2184 return ret;
2185}
2186
2187static int vcn_v3_0_set_interrupt_state(struct amdgpu_device *adev,
2188 struct amdgpu_irq_src *source,
2189 unsigned type,
2190 enum amdgpu_interrupt_state state)
2191{
2192 return 0;
2193}
2194
2195static int vcn_v3_0_process_interrupt(struct amdgpu_device *adev,
2196 struct amdgpu_irq_src *source,
2197 struct amdgpu_iv_entry *entry)
2198{
2199 uint32_t ip_instance;
2200
2201 switch (entry->client_id) {
2202 case SOC15_IH_CLIENTID_VCN:
2203 ip_instance = 0;
2204 break;
2205 case SOC15_IH_CLIENTID_VCN1:
2206 ip_instance = 1;
2207 break;
2208 default:
2209 DRM_ERROR("Unhandled client id: %d\n", entry->client_id);
2210 return 0;
2211 }
2212
2213 DRM_DEBUG("IH: VCN TRAP\n");
2214
2215 switch (entry->src_id) {
2216 case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT:
2217 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_dec);
2218 break;
2219 case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE:
2220 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]);
2221 break;
2222 case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY:
2223 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[1]);
2224 break;
2225 default:
2226 DRM_ERROR("Unhandled interrupt: %d %d\n",
2227 entry->src_id, entry->src_data[0]);
2228 break;
2229 }
2230
2231 return 0;
2232}
2233
2234static const struct amdgpu_irq_src_funcs vcn_v3_0_irq_funcs = {
2235 .set = vcn_v3_0_set_interrupt_state,
2236 .process = vcn_v3_0_process_interrupt,
2237};
2238
2239static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev)
2240{
2241 int i;
2242
2243 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
2244 if (adev->vcn.harvest_config & (1 << i))
2245 continue;
2246
2247 adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 1;
2248 adev->vcn.inst[i].irq.funcs = &vcn_v3_0_irq_funcs;
2249 }
2250}
2251
2252static void vcn_v3_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p)
2253{
2254 struct amdgpu_device *adev = ip_block->adev;
2255 int i, j;
2256 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_3_0);
2257 uint32_t inst_off;
2258 bool is_powered;
2259
2260 if (!adev->vcn.ip_dump)
2261 return;
2262
2263 drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst);
2264 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
2265 if (adev->vcn.harvest_config & (1 << i)) {
2266 drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i);
2267 continue;
2268 }
2269
2270 inst_off = i * reg_count;
2271 is_powered = (adev->vcn.ip_dump[inst_off] &
2272 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
2273
2274 if (is_powered) {
2275 drm_printf(p, "\nActive Instance:VCN%d\n", i);
2276 for (j = 0; j < reg_count; j++)
2277 drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_3_0[j].reg_name,
2278 adev->vcn.ip_dump[inst_off + j]);
2279 } else {
2280 drm_printf(p, "\nInactive Instance:VCN%d\n", i);
2281 }
2282 }
2283}
2284
2285static void vcn_v3_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
2286{
2287 struct amdgpu_device *adev = ip_block->adev;
2288 int i, j;
2289 bool is_powered;
2290 uint32_t inst_off;
2291 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_3_0);
2292
2293 if (!adev->vcn.ip_dump)
2294 return;
2295
2296 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
2297 if (adev->vcn.harvest_config & (1 << i))
2298 continue;
2299
2300 inst_off = i * reg_count;
2301 /* mmUVD_POWER_STATUS is always readable and is first element of the array */
2302 adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, mmUVD_POWER_STATUS);
2303 is_powered = (adev->vcn.ip_dump[inst_off] &
2304 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
2305
2306 if (is_powered)
2307 for (j = 1; j < reg_count; j++)
2308 adev->vcn.ip_dump[inst_off + j] =
2309 RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_3_0[j], i));
2310 }
2311}
2312
2313static const struct amd_ip_funcs vcn_v3_0_ip_funcs = {
2314 .name = "vcn_v3_0",
2315 .early_init = vcn_v3_0_early_init,
2316 .sw_init = vcn_v3_0_sw_init,
2317 .sw_fini = vcn_v3_0_sw_fini,
2318 .hw_init = vcn_v3_0_hw_init,
2319 .hw_fini = vcn_v3_0_hw_fini,
2320 .suspend = vcn_v3_0_suspend,
2321 .resume = vcn_v3_0_resume,
2322 .is_idle = vcn_v3_0_is_idle,
2323 .wait_for_idle = vcn_v3_0_wait_for_idle,
2324 .set_clockgating_state = vcn_v3_0_set_clockgating_state,
2325 .set_powergating_state = vcn_v3_0_set_powergating_state,
2326 .dump_ip_state = vcn_v3_0_dump_ip_state,
2327 .print_ip_state = vcn_v3_0_print_ip_state,
2328};
2329
2330const struct amdgpu_ip_block_version vcn_v3_0_ip_block = {
2331 .type = AMD_IP_BLOCK_TYPE_VCN,
2332 .major = 3,
2333 .minor = 0,
2334 .rev = 0,
2335 .funcs = &vcn_v3_0_ip_funcs,
2336};