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1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <drm/amdgpu_drm.h>
25#include "amdgpu.h"
26#include "atomfirmware.h"
27#include "amdgpu_atomfirmware.h"
28#include "atom.h"
29#include "atombios.h"
30#include "soc15_hw_ip.h"
31
32union firmware_info {
33 struct atom_firmware_info_v3_1 v31;
34 struct atom_firmware_info_v3_2 v32;
35 struct atom_firmware_info_v3_3 v33;
36 struct atom_firmware_info_v3_4 v34;
37 struct atom_firmware_info_v3_5 v35;
38};
39
40/*
41 * Helper function to query firmware capability
42 *
43 * @adev: amdgpu_device pointer
44 *
45 * Return firmware_capability in firmwareinfo table on success or 0 if not
46 */
47uint32_t amdgpu_atomfirmware_query_firmware_capability(struct amdgpu_device *adev)
48{
49 struct amdgpu_mode_info *mode_info = &adev->mode_info;
50 int index;
51 u16 data_offset, size;
52 union firmware_info *firmware_info;
53 u8 frev, crev;
54 u32 fw_cap = 0;
55
56 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
57 firmwareinfo);
58
59 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context,
60 index, &size, &frev, &crev, &data_offset)) {
61 /* support firmware_info 3.1 + */
62 if ((frev == 3 && crev >= 1) || (frev > 3)) {
63 firmware_info = (union firmware_info *)
64 (mode_info->atom_context->bios + data_offset);
65 fw_cap = le32_to_cpu(firmware_info->v31.firmware_capability);
66 }
67 }
68
69 return fw_cap;
70}
71
72/*
73 * Helper function to query gpu virtualizaiton capability
74 *
75 * @adev: amdgpu_device pointer
76 *
77 * Return true if gpu virtualization is supported or false if not
78 */
79bool amdgpu_atomfirmware_gpu_virtualization_supported(struct amdgpu_device *adev)
80{
81 u32 fw_cap;
82
83 fw_cap = adev->mode_info.firmware_flags;
84
85 return (fw_cap & ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION) ? true : false;
86}
87
88void amdgpu_atomfirmware_scratch_regs_init(struct amdgpu_device *adev)
89{
90 int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
91 firmwareinfo);
92 uint16_t data_offset;
93
94 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, NULL,
95 NULL, NULL, &data_offset)) {
96 struct atom_firmware_info_v3_1 *firmware_info =
97 (struct atom_firmware_info_v3_1 *)(adev->mode_info.atom_context->bios +
98 data_offset);
99
100 adev->bios_scratch_reg_offset =
101 le32_to_cpu(firmware_info->bios_scratch_reg_startaddr);
102 }
103}
104
105static int amdgpu_atomfirmware_allocate_fb_v2_1(struct amdgpu_device *adev,
106 struct vram_usagebyfirmware_v2_1 *fw_usage, int *usage_bytes)
107{
108 u32 start_addr, fw_size, drv_size;
109
110 start_addr = le32_to_cpu(fw_usage->start_address_in_kb);
111 fw_size = le16_to_cpu(fw_usage->used_by_firmware_in_kb);
112 drv_size = le16_to_cpu(fw_usage->used_by_driver_in_kb);
113
114 DRM_DEBUG("atom firmware v2_1 requested %08x %dkb fw %dkb drv\n",
115 start_addr,
116 fw_size,
117 drv_size);
118
119 if ((start_addr & ATOM_VRAM_OPERATION_FLAGS_MASK) ==
120 (u32)(ATOM_VRAM_BLOCK_SRIOV_MSG_SHARE_RESERVATION <<
121 ATOM_VRAM_OPERATION_FLAGS_SHIFT)) {
122 /* Firmware request VRAM reservation for SR-IOV */
123 adev->mman.fw_vram_usage_start_offset = (start_addr &
124 (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10;
125 adev->mman.fw_vram_usage_size = fw_size << 10;
126 /* Use the default scratch size */
127 *usage_bytes = 0;
128 } else {
129 *usage_bytes = drv_size << 10;
130 }
131 return 0;
132}
133
134static int amdgpu_atomfirmware_allocate_fb_v2_2(struct amdgpu_device *adev,
135 struct vram_usagebyfirmware_v2_2 *fw_usage, int *usage_bytes)
136{
137 u32 fw_start_addr, fw_size, drv_start_addr, drv_size;
138
139 fw_start_addr = le32_to_cpu(fw_usage->fw_region_start_address_in_kb);
140 fw_size = le16_to_cpu(fw_usage->used_by_firmware_in_kb);
141
142 drv_start_addr = le32_to_cpu(fw_usage->driver_region0_start_address_in_kb);
143 drv_size = le32_to_cpu(fw_usage->used_by_driver_region0_in_kb);
144
145 DRM_DEBUG("atom requested fw start at %08x %dkb and drv start at %08x %dkb\n",
146 fw_start_addr,
147 fw_size,
148 drv_start_addr,
149 drv_size);
150
151 if (amdgpu_sriov_vf(adev) &&
152 ((fw_start_addr & (ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION <<
153 ATOM_VRAM_OPERATION_FLAGS_SHIFT)) == 0)) {
154 /* Firmware request VRAM reservation for SR-IOV */
155 adev->mman.fw_vram_usage_start_offset = (fw_start_addr &
156 (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10;
157 adev->mman.fw_vram_usage_size = fw_size << 10;
158 }
159
160 if (amdgpu_sriov_vf(adev) &&
161 ((drv_start_addr & (ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION <<
162 ATOM_VRAM_OPERATION_FLAGS_SHIFT)) == 0)) {
163 /* driver request VRAM reservation for SR-IOV */
164 adev->mman.drv_vram_usage_start_offset = (drv_start_addr &
165 (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10;
166 adev->mman.drv_vram_usage_size = drv_size << 10;
167 }
168
169 *usage_bytes = 0;
170 return 0;
171}
172
173int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev)
174{
175 struct atom_context *ctx = adev->mode_info.atom_context;
176 int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
177 vram_usagebyfirmware);
178 struct vram_usagebyfirmware_v2_1 *fw_usage_v2_1;
179 struct vram_usagebyfirmware_v2_2 *fw_usage_v2_2;
180 u16 data_offset;
181 u8 frev, crev;
182 int usage_bytes = 0;
183
184 if (amdgpu_atom_parse_data_header(ctx, index, NULL, &frev, &crev, &data_offset)) {
185 if (frev == 2 && crev == 1) {
186 fw_usage_v2_1 =
187 (struct vram_usagebyfirmware_v2_1 *)(ctx->bios + data_offset);
188 amdgpu_atomfirmware_allocate_fb_v2_1(adev,
189 fw_usage_v2_1,
190 &usage_bytes);
191 } else if (frev >= 2 && crev >= 2) {
192 fw_usage_v2_2 =
193 (struct vram_usagebyfirmware_v2_2 *)(ctx->bios + data_offset);
194 amdgpu_atomfirmware_allocate_fb_v2_2(adev,
195 fw_usage_v2_2,
196 &usage_bytes);
197 }
198 }
199
200 ctx->scratch_size_bytes = 0;
201 if (usage_bytes == 0)
202 usage_bytes = 20 * 1024;
203 /* allocate some scratch memory */
204 ctx->scratch = kzalloc(usage_bytes, GFP_KERNEL);
205 if (!ctx->scratch)
206 return -ENOMEM;
207 ctx->scratch_size_bytes = usage_bytes;
208 return 0;
209}
210
211union igp_info {
212 struct atom_integrated_system_info_v1_11 v11;
213 struct atom_integrated_system_info_v1_12 v12;
214 struct atom_integrated_system_info_v2_1 v21;
215 struct atom_integrated_system_info_v2_3 v23;
216};
217
218union umc_info {
219 struct atom_umc_info_v3_1 v31;
220 struct atom_umc_info_v3_2 v32;
221 struct atom_umc_info_v3_3 v33;
222 struct atom_umc_info_v4_0 v40;
223};
224
225union vram_info {
226 struct atom_vram_info_header_v2_3 v23;
227 struct atom_vram_info_header_v2_4 v24;
228 struct atom_vram_info_header_v2_5 v25;
229 struct atom_vram_info_header_v2_6 v26;
230 struct atom_vram_info_header_v3_0 v30;
231};
232
233union vram_module {
234 struct atom_vram_module_v9 v9;
235 struct atom_vram_module_v10 v10;
236 struct atom_vram_module_v11 v11;
237 struct atom_vram_module_v3_0 v30;
238};
239
240static int convert_atom_mem_type_to_vram_type(struct amdgpu_device *adev,
241 int atom_mem_type)
242{
243 int vram_type;
244
245 if (adev->flags & AMD_IS_APU) {
246 switch (atom_mem_type) {
247 case Ddr2MemType:
248 case LpDdr2MemType:
249 vram_type = AMDGPU_VRAM_TYPE_DDR2;
250 break;
251 case Ddr3MemType:
252 case LpDdr3MemType:
253 vram_type = AMDGPU_VRAM_TYPE_DDR3;
254 break;
255 case Ddr4MemType:
256 vram_type = AMDGPU_VRAM_TYPE_DDR4;
257 break;
258 case LpDdr4MemType:
259 vram_type = AMDGPU_VRAM_TYPE_LPDDR4;
260 break;
261 case Ddr5MemType:
262 vram_type = AMDGPU_VRAM_TYPE_DDR5;
263 break;
264 case LpDdr5MemType:
265 vram_type = AMDGPU_VRAM_TYPE_LPDDR5;
266 break;
267 default:
268 vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
269 break;
270 }
271 } else {
272 switch (atom_mem_type) {
273 case ATOM_DGPU_VRAM_TYPE_GDDR5:
274 vram_type = AMDGPU_VRAM_TYPE_GDDR5;
275 break;
276 case ATOM_DGPU_VRAM_TYPE_HBM2:
277 case ATOM_DGPU_VRAM_TYPE_HBM2E:
278 case ATOM_DGPU_VRAM_TYPE_HBM3:
279 vram_type = AMDGPU_VRAM_TYPE_HBM;
280 break;
281 case ATOM_DGPU_VRAM_TYPE_GDDR6:
282 vram_type = AMDGPU_VRAM_TYPE_GDDR6;
283 break;
284 default:
285 vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
286 break;
287 }
288 }
289
290 return vram_type;
291}
292
293int
294amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
295 int *vram_width, int *vram_type,
296 int *vram_vendor)
297{
298 struct amdgpu_mode_info *mode_info = &adev->mode_info;
299 int index, i = 0;
300 u16 data_offset, size;
301 union igp_info *igp_info;
302 union vram_info *vram_info;
303 union umc_info *umc_info;
304 union vram_module *vram_module;
305 u8 frev, crev;
306 u8 mem_type;
307 u8 mem_vendor;
308 u32 mem_channel_number;
309 u32 mem_channel_width;
310 u32 module_id;
311
312 if (adev->flags & AMD_IS_APU)
313 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
314 integratedsysteminfo);
315 else {
316 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
317 case IP_VERSION(12, 0, 0):
318 case IP_VERSION(12, 0, 1):
319 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, umc_info);
320 break;
321 default:
322 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, vram_info);
323 }
324 }
325 if (amdgpu_atom_parse_data_header(mode_info->atom_context,
326 index, &size,
327 &frev, &crev, &data_offset)) {
328 if (adev->flags & AMD_IS_APU) {
329 igp_info = (union igp_info *)
330 (mode_info->atom_context->bios + data_offset);
331 switch (frev) {
332 case 1:
333 switch (crev) {
334 case 11:
335 case 12:
336 mem_channel_number = igp_info->v11.umachannelnumber;
337 if (!mem_channel_number)
338 mem_channel_number = 1;
339 mem_type = igp_info->v11.memorytype;
340 if (mem_type == LpDdr5MemType)
341 mem_channel_width = 32;
342 else
343 mem_channel_width = 64;
344 if (vram_width)
345 *vram_width = mem_channel_number * mem_channel_width;
346 if (vram_type)
347 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
348 break;
349 default:
350 return -EINVAL;
351 }
352 break;
353 case 2:
354 switch (crev) {
355 case 1:
356 case 2:
357 mem_channel_number = igp_info->v21.umachannelnumber;
358 if (!mem_channel_number)
359 mem_channel_number = 1;
360 mem_type = igp_info->v21.memorytype;
361 if (mem_type == LpDdr5MemType)
362 mem_channel_width = 32;
363 else
364 mem_channel_width = 64;
365 if (vram_width)
366 *vram_width = mem_channel_number * mem_channel_width;
367 if (vram_type)
368 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
369 break;
370 case 3:
371 mem_channel_number = igp_info->v23.umachannelnumber;
372 if (!mem_channel_number)
373 mem_channel_number = 1;
374 mem_type = igp_info->v23.memorytype;
375 if (mem_type == LpDdr5MemType)
376 mem_channel_width = 32;
377 else
378 mem_channel_width = 64;
379 if (vram_width)
380 *vram_width = mem_channel_number * mem_channel_width;
381 if (vram_type)
382 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
383 break;
384 default:
385 return -EINVAL;
386 }
387 break;
388 default:
389 return -EINVAL;
390 }
391 } else {
392 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
393 case IP_VERSION(12, 0, 0):
394 case IP_VERSION(12, 0, 1):
395 umc_info = (union umc_info *)(mode_info->atom_context->bios + data_offset);
396
397 if (frev == 4) {
398 switch (crev) {
399 case 0:
400 mem_channel_number = le32_to_cpu(umc_info->v40.channel_num);
401 mem_type = le32_to_cpu(umc_info->v40.vram_type);
402 mem_channel_width = le32_to_cpu(umc_info->v40.channel_width);
403 mem_vendor = RREG32(adev->bios_scratch_reg_offset + 4) & 0xF;
404 if (vram_vendor)
405 *vram_vendor = mem_vendor;
406 if (vram_type)
407 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
408 if (vram_width)
409 *vram_width = mem_channel_number * (1 << mem_channel_width);
410 break;
411 default:
412 return -EINVAL;
413 }
414 } else
415 return -EINVAL;
416 break;
417 default:
418 vram_info = (union vram_info *)
419 (mode_info->atom_context->bios + data_offset);
420
421 module_id = (RREG32(adev->bios_scratch_reg_offset + 4) & 0x00ff0000) >> 16;
422 if (frev == 3) {
423 switch (crev) {
424 /* v30 */
425 case 0:
426 vram_module = (union vram_module *)vram_info->v30.vram_module;
427 mem_vendor = (vram_module->v30.dram_vendor_id) & 0xF;
428 if (vram_vendor)
429 *vram_vendor = mem_vendor;
430 mem_type = vram_info->v30.memory_type;
431 if (vram_type)
432 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
433 mem_channel_number = vram_info->v30.channel_num;
434 mem_channel_width = vram_info->v30.channel_width;
435 if (vram_width)
436 *vram_width = mem_channel_number * 16;
437 break;
438 default:
439 return -EINVAL;
440 }
441 } else if (frev == 2) {
442 switch (crev) {
443 /* v23 */
444 case 3:
445 if (module_id > vram_info->v23.vram_module_num)
446 module_id = 0;
447 vram_module = (union vram_module *)vram_info->v23.vram_module;
448 while (i < module_id) {
449 vram_module = (union vram_module *)
450 ((u8 *)vram_module + vram_module->v9.vram_module_size);
451 i++;
452 }
453 mem_type = vram_module->v9.memory_type;
454 if (vram_type)
455 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
456 mem_channel_number = vram_module->v9.channel_num;
457 mem_channel_width = vram_module->v9.channel_width;
458 if (vram_width)
459 *vram_width = mem_channel_number * (1 << mem_channel_width);
460 mem_vendor = (vram_module->v9.vender_rev_id) & 0xF;
461 if (vram_vendor)
462 *vram_vendor = mem_vendor;
463 break;
464 /* v24 */
465 case 4:
466 if (module_id > vram_info->v24.vram_module_num)
467 module_id = 0;
468 vram_module = (union vram_module *)vram_info->v24.vram_module;
469 while (i < module_id) {
470 vram_module = (union vram_module *)
471 ((u8 *)vram_module + vram_module->v10.vram_module_size);
472 i++;
473 }
474 mem_type = vram_module->v10.memory_type;
475 if (vram_type)
476 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
477 mem_channel_number = vram_module->v10.channel_num;
478 mem_channel_width = vram_module->v10.channel_width;
479 if (vram_width)
480 *vram_width = mem_channel_number * (1 << mem_channel_width);
481 mem_vendor = (vram_module->v10.vender_rev_id) & 0xF;
482 if (vram_vendor)
483 *vram_vendor = mem_vendor;
484 break;
485 /* v25 */
486 case 5:
487 if (module_id > vram_info->v25.vram_module_num)
488 module_id = 0;
489 vram_module = (union vram_module *)vram_info->v25.vram_module;
490 while (i < module_id) {
491 vram_module = (union vram_module *)
492 ((u8 *)vram_module + vram_module->v11.vram_module_size);
493 i++;
494 }
495 mem_type = vram_module->v11.memory_type;
496 if (vram_type)
497 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
498 mem_channel_number = vram_module->v11.channel_num;
499 mem_channel_width = vram_module->v11.channel_width;
500 if (vram_width)
501 *vram_width = mem_channel_number * (1 << mem_channel_width);
502 mem_vendor = (vram_module->v11.vender_rev_id) & 0xF;
503 if (vram_vendor)
504 *vram_vendor = mem_vendor;
505 break;
506 /* v26 */
507 case 6:
508 if (module_id > vram_info->v26.vram_module_num)
509 module_id = 0;
510 vram_module = (union vram_module *)vram_info->v26.vram_module;
511 while (i < module_id) {
512 vram_module = (union vram_module *)
513 ((u8 *)vram_module + vram_module->v9.vram_module_size);
514 i++;
515 }
516 mem_type = vram_module->v9.memory_type;
517 if (vram_type)
518 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
519 mem_channel_number = vram_module->v9.channel_num;
520 mem_channel_width = vram_module->v9.channel_width;
521 if (vram_width)
522 *vram_width = mem_channel_number * (1 << mem_channel_width);
523 mem_vendor = (vram_module->v9.vender_rev_id) & 0xF;
524 if (vram_vendor)
525 *vram_vendor = mem_vendor;
526 break;
527 default:
528 return -EINVAL;
529 }
530 } else {
531 /* invalid frev */
532 return -EINVAL;
533 }
534 }
535 }
536 }
537
538 return 0;
539}
540
541/*
542 * Return true if vbios enabled ecc by default, if umc info table is available
543 * or false if ecc is not enabled or umc info table is not available
544 */
545bool amdgpu_atomfirmware_mem_ecc_supported(struct amdgpu_device *adev)
546{
547 struct amdgpu_mode_info *mode_info = &adev->mode_info;
548 int index;
549 u16 data_offset, size;
550 union umc_info *umc_info;
551 u8 frev, crev;
552 bool ecc_default_enabled = false;
553 u8 umc_config;
554 u32 umc_config1;
555
556 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
557 umc_info);
558
559 if (amdgpu_atom_parse_data_header(mode_info->atom_context,
560 index, &size, &frev, &crev, &data_offset)) {
561 umc_info = (union umc_info *)(mode_info->atom_context->bios + data_offset);
562 if (frev == 3) {
563 switch (crev) {
564 case 1:
565 umc_config = le32_to_cpu(umc_info->v31.umc_config);
566 ecc_default_enabled =
567 (umc_config & UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ? true : false;
568 break;
569 case 2:
570 umc_config = le32_to_cpu(umc_info->v32.umc_config);
571 ecc_default_enabled =
572 (umc_config & UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ? true : false;
573 break;
574 case 3:
575 umc_config = le32_to_cpu(umc_info->v33.umc_config);
576 umc_config1 = le32_to_cpu(umc_info->v33.umc_config1);
577 ecc_default_enabled =
578 ((umc_config & UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ||
579 (umc_config1 & UMC_CONFIG1__ENABLE_ECC_CAPABLE)) ? true : false;
580 break;
581 default:
582 /* unsupported crev */
583 return false;
584 }
585 } else if (frev == 4) {
586 switch (crev) {
587 case 0:
588 umc_config1 = le32_to_cpu(umc_info->v40.umc_config1);
589 ecc_default_enabled =
590 (umc_config1 & UMC_CONFIG1__ENABLE_ECC_CAPABLE) ? true : false;
591 break;
592 default:
593 /* unsupported crev */
594 return false;
595 }
596 } else {
597 /* unsupported frev */
598 return false;
599 }
600 }
601
602 return ecc_default_enabled;
603}
604
605/*
606 * Helper function to query sram ecc capablity
607 *
608 * @adev: amdgpu_device pointer
609 *
610 * Return true if vbios supports sram ecc or false if not
611 */
612bool amdgpu_atomfirmware_sram_ecc_supported(struct amdgpu_device *adev)
613{
614 u32 fw_cap;
615
616 fw_cap = adev->mode_info.firmware_flags;
617
618 return (fw_cap & ATOM_FIRMWARE_CAP_SRAM_ECC) ? true : false;
619}
620
621/*
622 * Helper function to query dynamic boot config capability
623 *
624 * @adev: amdgpu_device pointer
625 *
626 * Return true if vbios supports dynamic boot config or false if not
627 */
628bool amdgpu_atomfirmware_dynamic_boot_config_supported(struct amdgpu_device *adev)
629{
630 u32 fw_cap;
631
632 fw_cap = adev->mode_info.firmware_flags;
633
634 return (fw_cap & ATOM_FIRMWARE_CAP_DYNAMIC_BOOT_CFG_ENABLE) ? true : false;
635}
636
637/**
638 * amdgpu_atomfirmware_ras_rom_addr -- Get the RAS EEPROM addr from VBIOS
639 * @adev: amdgpu_device pointer
640 * @i2c_address: pointer to u8; if not NULL, will contain
641 * the RAS EEPROM address if the function returns true
642 *
643 * Return true if VBIOS supports RAS EEPROM address reporting,
644 * else return false. If true and @i2c_address is not NULL,
645 * will contain the RAS ROM address.
646 */
647bool amdgpu_atomfirmware_ras_rom_addr(struct amdgpu_device *adev,
648 u8 *i2c_address)
649{
650 struct amdgpu_mode_info *mode_info = &adev->mode_info;
651 int index;
652 u16 data_offset, size;
653 union firmware_info *firmware_info;
654 u8 frev, crev;
655
656 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
657 firmwareinfo);
658
659 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context,
660 index, &size, &frev, &crev,
661 &data_offset)) {
662 /* support firmware_info 3.4 + */
663 if ((frev == 3 && crev >= 4) || (frev > 3)) {
664 firmware_info = (union firmware_info *)
665 (mode_info->atom_context->bios + data_offset);
666 /* The ras_rom_i2c_slave_addr should ideally
667 * be a 19-bit EEPROM address, which would be
668 * used as is by the driver; see top of
669 * amdgpu_eeprom.c.
670 *
671 * When this is the case, 0 is of course a
672 * valid RAS EEPROM address, in which case,
673 * we'll drop the first "if (firm...)" and only
674 * leave the check for the pointer.
675 *
676 * The reason this works right now is because
677 * ras_rom_i2c_slave_addr contains the EEPROM
678 * device type qualifier 1010b in the top 4
679 * bits.
680 */
681 if (firmware_info->v34.ras_rom_i2c_slave_addr) {
682 if (i2c_address)
683 *i2c_address = firmware_info->v34.ras_rom_i2c_slave_addr;
684 return true;
685 }
686 }
687 }
688
689 return false;
690}
691
692
693union smu_info {
694 struct atom_smu_info_v3_1 v31;
695 struct atom_smu_info_v4_0 v40;
696};
697
698union gfx_info {
699 struct atom_gfx_info_v2_2 v22;
700 struct atom_gfx_info_v2_4 v24;
701 struct atom_gfx_info_v2_7 v27;
702 struct atom_gfx_info_v3_0 v30;
703};
704
705int amdgpu_atomfirmware_get_clock_info(struct amdgpu_device *adev)
706{
707 struct amdgpu_mode_info *mode_info = &adev->mode_info;
708 struct amdgpu_pll *spll = &adev->clock.spll;
709 struct amdgpu_pll *mpll = &adev->clock.mpll;
710 uint8_t frev, crev;
711 uint16_t data_offset;
712 int ret = -EINVAL, index;
713
714 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
715 firmwareinfo);
716 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
717 &frev, &crev, &data_offset)) {
718 union firmware_info *firmware_info =
719 (union firmware_info *)(mode_info->atom_context->bios +
720 data_offset);
721
722 adev->clock.default_sclk =
723 le32_to_cpu(firmware_info->v31.bootup_sclk_in10khz);
724 adev->clock.default_mclk =
725 le32_to_cpu(firmware_info->v31.bootup_mclk_in10khz);
726
727 adev->pm.current_sclk = adev->clock.default_sclk;
728 adev->pm.current_mclk = adev->clock.default_mclk;
729
730 ret = 0;
731 }
732
733 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
734 smu_info);
735 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
736 &frev, &crev, &data_offset)) {
737 union smu_info *smu_info =
738 (union smu_info *)(mode_info->atom_context->bios +
739 data_offset);
740
741 /* system clock */
742 if (frev == 3)
743 spll->reference_freq = le32_to_cpu(smu_info->v31.core_refclk_10khz);
744 else if (frev == 4)
745 spll->reference_freq = le32_to_cpu(smu_info->v40.core_refclk_10khz);
746
747 spll->reference_div = 0;
748 spll->min_post_div = 1;
749 spll->max_post_div = 1;
750 spll->min_ref_div = 2;
751 spll->max_ref_div = 0xff;
752 spll->min_feedback_div = 4;
753 spll->max_feedback_div = 0xff;
754 spll->best_vco = 0;
755
756 ret = 0;
757 }
758
759 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
760 umc_info);
761 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
762 &frev, &crev, &data_offset)) {
763 union umc_info *umc_info =
764 (union umc_info *)(mode_info->atom_context->bios +
765 data_offset);
766
767 /* memory clock */
768 mpll->reference_freq = le32_to_cpu(umc_info->v31.mem_refclk_10khz);
769
770 mpll->reference_div = 0;
771 mpll->min_post_div = 1;
772 mpll->max_post_div = 1;
773 mpll->min_ref_div = 2;
774 mpll->max_ref_div = 0xff;
775 mpll->min_feedback_div = 4;
776 mpll->max_feedback_div = 0xff;
777 mpll->best_vco = 0;
778
779 ret = 0;
780 }
781
782 /* if asic is Navi+, the rlc reference clock is used for system clock
783 * from vbios gfx_info table */
784 if (adev->asic_type >= CHIP_NAVI10) {
785 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
786 gfx_info);
787 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
788 &frev, &crev, &data_offset)) {
789 union gfx_info *gfx_info = (union gfx_info *)
790 (mode_info->atom_context->bios + data_offset);
791 if ((frev == 3) ||
792 (frev == 2 && crev == 6)) {
793 spll->reference_freq = le32_to_cpu(gfx_info->v30.golden_tsc_count_lower_refclk);
794 ret = 0;
795 } else if ((frev == 2) &&
796 (crev >= 2) &&
797 (crev != 6)) {
798 spll->reference_freq = le32_to_cpu(gfx_info->v22.rlc_gpu_timer_refclk);
799 ret = 0;
800 } else {
801 BUG();
802 }
803 }
804 }
805
806 return ret;
807}
808
809int amdgpu_atomfirmware_get_gfx_info(struct amdgpu_device *adev)
810{
811 struct amdgpu_mode_info *mode_info = &adev->mode_info;
812 int index;
813 uint8_t frev, crev;
814 uint16_t data_offset;
815
816 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
817 gfx_info);
818 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
819 &frev, &crev, &data_offset)) {
820 union gfx_info *gfx_info = (union gfx_info *)
821 (mode_info->atom_context->bios + data_offset);
822 if (frev == 2) {
823 switch (crev) {
824 case 4:
825 adev->gfx.config.max_shader_engines = gfx_info->v24.max_shader_engines;
826 adev->gfx.config.max_cu_per_sh = gfx_info->v24.max_cu_per_sh;
827 adev->gfx.config.max_sh_per_se = gfx_info->v24.max_sh_per_se;
828 adev->gfx.config.max_backends_per_se = gfx_info->v24.max_backends_per_se;
829 adev->gfx.config.max_texture_channel_caches = gfx_info->v24.max_texture_channel_caches;
830 adev->gfx.config.max_gprs = le16_to_cpu(gfx_info->v24.gc_num_gprs);
831 adev->gfx.config.max_gs_threads = gfx_info->v24.gc_num_max_gs_thds;
832 adev->gfx.config.gs_vgt_table_depth = gfx_info->v24.gc_gs_table_depth;
833 adev->gfx.config.gs_prim_buffer_depth =
834 le16_to_cpu(gfx_info->v24.gc_gsprim_buff_depth);
835 adev->gfx.config.double_offchip_lds_buf =
836 gfx_info->v24.gc_double_offchip_lds_buffer;
837 adev->gfx.cu_info.wave_front_size = le16_to_cpu(gfx_info->v24.gc_wave_size);
838 adev->gfx.cu_info.max_waves_per_simd = le16_to_cpu(gfx_info->v24.gc_max_waves_per_simd);
839 adev->gfx.cu_info.max_scratch_slots_per_cu = gfx_info->v24.gc_max_scratch_slots_per_cu;
840 adev->gfx.cu_info.lds_size = le16_to_cpu(gfx_info->v24.gc_lds_size);
841 return 0;
842 case 7:
843 adev->gfx.config.max_shader_engines = gfx_info->v27.max_shader_engines;
844 adev->gfx.config.max_cu_per_sh = gfx_info->v27.max_cu_per_sh;
845 adev->gfx.config.max_sh_per_se = gfx_info->v27.max_sh_per_se;
846 adev->gfx.config.max_backends_per_se = gfx_info->v27.max_backends_per_se;
847 adev->gfx.config.max_texture_channel_caches = gfx_info->v27.max_texture_channel_caches;
848 adev->gfx.config.max_gprs = le16_to_cpu(gfx_info->v27.gc_num_gprs);
849 adev->gfx.config.max_gs_threads = gfx_info->v27.gc_num_max_gs_thds;
850 adev->gfx.config.gs_vgt_table_depth = gfx_info->v27.gc_gs_table_depth;
851 adev->gfx.config.gs_prim_buffer_depth = le16_to_cpu(gfx_info->v27.gc_gsprim_buff_depth);
852 adev->gfx.config.double_offchip_lds_buf = gfx_info->v27.gc_double_offchip_lds_buffer;
853 adev->gfx.cu_info.wave_front_size = le16_to_cpu(gfx_info->v27.gc_wave_size);
854 adev->gfx.cu_info.max_waves_per_simd = le16_to_cpu(gfx_info->v27.gc_max_waves_per_simd);
855 adev->gfx.cu_info.max_scratch_slots_per_cu = gfx_info->v27.gc_max_scratch_slots_per_cu;
856 adev->gfx.cu_info.lds_size = le16_to_cpu(gfx_info->v27.gc_lds_size);
857 return 0;
858 default:
859 return -EINVAL;
860 }
861 } else if (frev == 3) {
862 switch (crev) {
863 case 0:
864 adev->gfx.config.max_shader_engines = gfx_info->v30.max_shader_engines;
865 adev->gfx.config.max_cu_per_sh = gfx_info->v30.max_cu_per_sh;
866 adev->gfx.config.max_sh_per_se = gfx_info->v30.max_sh_per_se;
867 adev->gfx.config.max_backends_per_se = gfx_info->v30.max_backends_per_se;
868 adev->gfx.config.max_texture_channel_caches = gfx_info->v30.max_texture_channel_caches;
869 return 0;
870 default:
871 return -EINVAL;
872 }
873 } else {
874 return -EINVAL;
875 }
876
877 }
878 return -EINVAL;
879}
880
881/*
882 * Helper function to query two stage mem training capability
883 *
884 * @adev: amdgpu_device pointer
885 *
886 * Return true if two stage mem training is supported or false if not
887 */
888bool amdgpu_atomfirmware_mem_training_supported(struct amdgpu_device *adev)
889{
890 u32 fw_cap;
891
892 fw_cap = adev->mode_info.firmware_flags;
893
894 return (fw_cap & ATOM_FIRMWARE_CAP_ENABLE_2STAGE_BIST_TRAINING) ? true : false;
895}
896
897int amdgpu_atomfirmware_get_fw_reserved_fb_size(struct amdgpu_device *adev)
898{
899 struct atom_context *ctx = adev->mode_info.atom_context;
900 union firmware_info *firmware_info;
901 int index;
902 u16 data_offset, size;
903 u8 frev, crev;
904 int fw_reserved_fb_size;
905
906 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
907 firmwareinfo);
908
909 if (!amdgpu_atom_parse_data_header(ctx, index, &size,
910 &frev, &crev, &data_offset))
911 /* fail to parse data_header */
912 return 0;
913
914 firmware_info = (union firmware_info *)(ctx->bios + data_offset);
915
916 if (frev != 3)
917 return -EINVAL;
918
919 switch (crev) {
920 case 4:
921 fw_reserved_fb_size =
922 (firmware_info->v34.fw_reserved_size_in_kb << 10);
923 break;
924 case 5:
925 fw_reserved_fb_size =
926 (firmware_info->v35.fw_reserved_size_in_kb << 10);
927 break;
928 default:
929 fw_reserved_fb_size = 0;
930 break;
931 }
932
933 return fw_reserved_fb_size;
934}
935
936/*
937 * Helper function to execute asic_init table
938 *
939 * @adev: amdgpu_device pointer
940 * @fb_reset: flag to indicate whether fb is reset or not
941 *
942 * Return 0 if succeed, otherwise failed
943 */
944int amdgpu_atomfirmware_asic_init(struct amdgpu_device *adev, bool fb_reset)
945{
946 struct amdgpu_mode_info *mode_info = &adev->mode_info;
947 struct atom_context *ctx;
948 uint8_t frev, crev;
949 uint16_t data_offset;
950 uint32_t bootup_sclk_in10khz, bootup_mclk_in10khz;
951 struct asic_init_ps_allocation_v2_1 asic_init_ps_v2_1;
952 int index;
953
954 if (!mode_info)
955 return -EINVAL;
956
957 ctx = mode_info->atom_context;
958 if (!ctx)
959 return -EINVAL;
960
961 /* query bootup sclk/mclk from firmware_info table */
962 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
963 firmwareinfo);
964 if (amdgpu_atom_parse_data_header(ctx, index, NULL,
965 &frev, &crev, &data_offset)) {
966 union firmware_info *firmware_info =
967 (union firmware_info *)(ctx->bios +
968 data_offset);
969
970 bootup_sclk_in10khz =
971 le32_to_cpu(firmware_info->v31.bootup_sclk_in10khz);
972 bootup_mclk_in10khz =
973 le32_to_cpu(firmware_info->v31.bootup_mclk_in10khz);
974 } else {
975 return -EINVAL;
976 }
977
978 index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
979 asic_init);
980 if (amdgpu_atom_parse_cmd_header(mode_info->atom_context, index, &frev, &crev)) {
981 if (frev == 2 && crev >= 1) {
982 memset(&asic_init_ps_v2_1, 0, sizeof(asic_init_ps_v2_1));
983 asic_init_ps_v2_1.param.engineparam.sclkfreqin10khz = bootup_sclk_in10khz;
984 asic_init_ps_v2_1.param.memparam.mclkfreqin10khz = bootup_mclk_in10khz;
985 asic_init_ps_v2_1.param.engineparam.engineflag = b3NORMAL_ENGINE_INIT;
986 if (!fb_reset)
987 asic_init_ps_v2_1.param.memparam.memflag = b3DRAM_SELF_REFRESH_EXIT;
988 else
989 asic_init_ps_v2_1.param.memparam.memflag = 0;
990 } else {
991 return -EINVAL;
992 }
993 } else {
994 return -EINVAL;
995 }
996
997 return amdgpu_atom_execute_table(ctx, ATOM_CMD_INIT, (uint32_t *)&asic_init_ps_v2_1,
998 sizeof(asic_init_ps_v2_1));
999}