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1// SPDX-License-Identifier: GPL-2.0+
2//
3// MXS GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
4// Copyright 2008 Juergen Beisert, kernel@pengutronix.de
5//
6// Based on code from Freescale,
7// Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
8
9#include <linux/err.h>
10#include <linux/init.h>
11#include <linux/interrupt.h>
12#include <linux/io.h>
13#include <linux/irq.h>
14#include <linux/irqdomain.h>
15#include <linux/of.h>
16#include <linux/of_address.h>
17#include <linux/platform_device.h>
18#include <linux/slab.h>
19#include <linux/gpio/driver.h>
20#include <linux/module.h>
21
22#define MXS_SET 0x4
23#define MXS_CLR 0x8
24
25#define PINCTRL_DOUT(p) ((is_imx23_gpio(p) ? 0x0500 : 0x0700) + (p->id) * 0x10)
26#define PINCTRL_DIN(p) ((is_imx23_gpio(p) ? 0x0600 : 0x0900) + (p->id) * 0x10)
27#define PINCTRL_DOE(p) ((is_imx23_gpio(p) ? 0x0700 : 0x0b00) + (p->id) * 0x10)
28#define PINCTRL_PIN2IRQ(p) ((is_imx23_gpio(p) ? 0x0800 : 0x1000) + (p->id) * 0x10)
29#define PINCTRL_IRQEN(p) ((is_imx23_gpio(p) ? 0x0900 : 0x1100) + (p->id) * 0x10)
30#define PINCTRL_IRQLEV(p) ((is_imx23_gpio(p) ? 0x0a00 : 0x1200) + (p->id) * 0x10)
31#define PINCTRL_IRQPOL(p) ((is_imx23_gpio(p) ? 0x0b00 : 0x1300) + (p->id) * 0x10)
32#define PINCTRL_IRQSTAT(p) ((is_imx23_gpio(p) ? 0x0c00 : 0x1400) + (p->id) * 0x10)
33
34#define GPIO_INT_FALL_EDGE 0x0
35#define GPIO_INT_LOW_LEV 0x1
36#define GPIO_INT_RISE_EDGE 0x2
37#define GPIO_INT_HIGH_LEV 0x3
38#define GPIO_INT_LEV_MASK (1 << 0)
39#define GPIO_INT_POL_MASK (1 << 1)
40
41enum mxs_gpio_id {
42 IMX23_GPIO,
43 IMX28_GPIO,
44};
45
46struct mxs_gpio_port {
47 void __iomem *base;
48 int id;
49 int irq;
50 struct irq_domain *domain;
51 struct gpio_chip gc;
52 struct device *dev;
53 enum mxs_gpio_id devid;
54 u32 both_edges;
55};
56
57static inline int is_imx23_gpio(struct mxs_gpio_port *port)
58{
59 return port->devid == IMX23_GPIO;
60}
61
62/* Note: This driver assumes 32 GPIOs are handled in one register */
63
64static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
65{
66 u32 val;
67 u32 pin_mask = 1 << d->hwirq;
68 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
69 struct irq_chip_type *ct = irq_data_get_chip_type(d);
70 struct mxs_gpio_port *port = gc->private;
71 void __iomem *pin_addr;
72 int edge;
73
74 if (!(ct->type & type))
75 if (irq_setup_alt_chip(d, type))
76 return -EINVAL;
77
78 port->both_edges &= ~pin_mask;
79 switch (type) {
80 case IRQ_TYPE_EDGE_BOTH:
81 val = readl(port->base + PINCTRL_DIN(port)) & pin_mask;
82 if (val)
83 edge = GPIO_INT_FALL_EDGE;
84 else
85 edge = GPIO_INT_RISE_EDGE;
86 port->both_edges |= pin_mask;
87 break;
88 case IRQ_TYPE_EDGE_RISING:
89 edge = GPIO_INT_RISE_EDGE;
90 break;
91 case IRQ_TYPE_EDGE_FALLING:
92 edge = GPIO_INT_FALL_EDGE;
93 break;
94 case IRQ_TYPE_LEVEL_LOW:
95 edge = GPIO_INT_LOW_LEV;
96 break;
97 case IRQ_TYPE_LEVEL_HIGH:
98 edge = GPIO_INT_HIGH_LEV;
99 break;
100 default:
101 return -EINVAL;
102 }
103
104 /* set level or edge */
105 pin_addr = port->base + PINCTRL_IRQLEV(port);
106 if (edge & GPIO_INT_LEV_MASK) {
107 writel(pin_mask, pin_addr + MXS_SET);
108 writel(pin_mask, port->base + PINCTRL_IRQEN(port) + MXS_SET);
109 } else {
110 writel(pin_mask, pin_addr + MXS_CLR);
111 writel(pin_mask, port->base + PINCTRL_PIN2IRQ(port) + MXS_SET);
112 }
113
114 /* set polarity */
115 pin_addr = port->base + PINCTRL_IRQPOL(port);
116 if (edge & GPIO_INT_POL_MASK)
117 writel(pin_mask, pin_addr + MXS_SET);
118 else
119 writel(pin_mask, pin_addr + MXS_CLR);
120
121 writel(pin_mask, port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
122
123 return 0;
124}
125
126static void mxs_flip_edge(struct mxs_gpio_port *port, u32 gpio)
127{
128 u32 bit, val, edge;
129 void __iomem *pin_addr;
130
131 bit = 1 << gpio;
132
133 pin_addr = port->base + PINCTRL_IRQPOL(port);
134 val = readl(pin_addr);
135 edge = val & bit;
136
137 if (edge)
138 writel(bit, pin_addr + MXS_CLR);
139 else
140 writel(bit, pin_addr + MXS_SET);
141}
142
143/* MXS has one interrupt *per* gpio port */
144static void mxs_gpio_irq_handler(struct irq_desc *desc)
145{
146 u32 irq_stat;
147 struct mxs_gpio_port *port = irq_desc_get_handler_data(desc);
148
149 desc->irq_data.chip->irq_ack(&desc->irq_data);
150
151 irq_stat = readl(port->base + PINCTRL_IRQSTAT(port)) &
152 readl(port->base + PINCTRL_IRQEN(port));
153
154 while (irq_stat != 0) {
155 int irqoffset = fls(irq_stat) - 1;
156 if (port->both_edges & (1 << irqoffset))
157 mxs_flip_edge(port, irqoffset);
158
159 generic_handle_domain_irq(port->domain, irqoffset);
160 irq_stat &= ~(1 << irqoffset);
161 }
162}
163
164/*
165 * Set interrupt number "irq" in the GPIO as a wake-up source.
166 * While system is running, all registered GPIO interrupts need to have
167 * wake-up enabled. When system is suspended, only selected GPIO interrupts
168 * need to have wake-up enabled.
169 * @param irq interrupt source number
170 * @param enable enable as wake-up if equal to non-zero
171 * @return This function returns 0 on success.
172 */
173static int mxs_gpio_set_wake_irq(struct irq_data *d, unsigned int enable)
174{
175 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
176 struct mxs_gpio_port *port = gc->private;
177
178 if (enable)
179 enable_irq_wake(port->irq);
180 else
181 disable_irq_wake(port->irq);
182
183 return 0;
184}
185
186static int mxs_gpio_init_gc(struct mxs_gpio_port *port, int irq_base)
187{
188 struct irq_chip_generic *gc;
189 struct irq_chip_type *ct;
190 int rv;
191
192 gc = devm_irq_alloc_generic_chip(port->dev, "gpio-mxs", 2, irq_base,
193 port->base, handle_level_irq);
194 if (!gc)
195 return -ENOMEM;
196
197 gc->private = port;
198
199 ct = &gc->chip_types[0];
200 ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
201 ct->chip.irq_ack = irq_gc_ack_set_bit;
202 ct->chip.irq_mask = irq_gc_mask_disable_reg;
203 ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
204 ct->chip.irq_set_type = mxs_gpio_set_irq_type;
205 ct->chip.irq_set_wake = mxs_gpio_set_wake_irq;
206 ct->chip.flags = IRQCHIP_SET_TYPE_MASKED;
207 ct->regs.ack = PINCTRL_IRQSTAT(port) + MXS_CLR;
208 ct->regs.enable = PINCTRL_PIN2IRQ(port) + MXS_SET;
209 ct->regs.disable = PINCTRL_PIN2IRQ(port) + MXS_CLR;
210
211 ct = &gc->chip_types[1];
212 ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
213 ct->chip.irq_ack = irq_gc_ack_set_bit;
214 ct->chip.irq_mask = irq_gc_mask_disable_reg;
215 ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
216 ct->chip.irq_set_type = mxs_gpio_set_irq_type;
217 ct->chip.irq_set_wake = mxs_gpio_set_wake_irq;
218 ct->chip.flags = IRQCHIP_SET_TYPE_MASKED;
219 ct->regs.ack = PINCTRL_IRQSTAT(port) + MXS_CLR;
220 ct->regs.enable = PINCTRL_IRQEN(port) + MXS_SET;
221 ct->regs.disable = PINCTRL_IRQEN(port) + MXS_CLR;
222 ct->handler = handle_level_irq;
223
224 rv = devm_irq_setup_generic_chip(port->dev, gc, IRQ_MSK(32),
225 IRQ_GC_INIT_NESTED_LOCK,
226 IRQ_NOREQUEST, 0);
227
228 return rv;
229}
230
231static int mxs_gpio_to_irq(struct gpio_chip *gc, unsigned int offset)
232{
233 struct mxs_gpio_port *port = gpiochip_get_data(gc);
234
235 return irq_find_mapping(port->domain, offset);
236}
237
238static int mxs_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
239{
240 struct mxs_gpio_port *port = gpiochip_get_data(gc);
241 u32 mask = 1 << offset;
242 u32 dir;
243
244 dir = readl(port->base + PINCTRL_DOE(port));
245 if (dir & mask)
246 return GPIO_LINE_DIRECTION_OUT;
247
248 return GPIO_LINE_DIRECTION_IN;
249}
250
251static const struct of_device_id mxs_gpio_dt_ids[] = {
252 { .compatible = "fsl,imx23-gpio", .data = (void *) IMX23_GPIO, },
253 { .compatible = "fsl,imx28-gpio", .data = (void *) IMX28_GPIO, },
254 { /* sentinel */ }
255};
256MODULE_DEVICE_TABLE(of, mxs_gpio_dt_ids);
257
258static int mxs_gpio_probe(struct platform_device *pdev)
259{
260 struct device_node *np = pdev->dev.of_node;
261 struct device_node *parent;
262 static void __iomem *base;
263 struct mxs_gpio_port *port;
264 int irq_base;
265 int err;
266
267 port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
268 if (!port)
269 return -ENOMEM;
270
271 port->id = of_alias_get_id(np, "gpio");
272 if (port->id < 0)
273 return port->id;
274 port->devid = (uintptr_t)of_device_get_match_data(&pdev->dev);
275 port->dev = &pdev->dev;
276 port->irq = platform_get_irq(pdev, 0);
277 if (port->irq < 0)
278 return port->irq;
279
280 /*
281 * map memory region only once, as all the gpio ports
282 * share the same one
283 */
284 if (!base) {
285 parent = of_get_parent(np);
286 base = of_iomap(parent, 0);
287 of_node_put(parent);
288 if (!base)
289 return -EADDRNOTAVAIL;
290 }
291 port->base = base;
292
293 /* initially disable the interrupts */
294 writel(0, port->base + PINCTRL_PIN2IRQ(port));
295 writel(0, port->base + PINCTRL_IRQEN(port));
296
297 /* clear address has to be used to clear IRQSTAT bits */
298 writel(~0U, port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
299
300 irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, 32, numa_node_id());
301 if (irq_base < 0) {
302 err = irq_base;
303 goto out_iounmap;
304 }
305
306 port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
307 &irq_domain_simple_ops, NULL);
308 if (!port->domain) {
309 err = -ENODEV;
310 goto out_iounmap;
311 }
312
313 /* gpio-mxs can be a generic irq chip */
314 err = mxs_gpio_init_gc(port, irq_base);
315 if (err < 0)
316 goto out_irqdomain_remove;
317
318 /* setup one handler for each entry */
319 irq_set_chained_handler_and_data(port->irq, mxs_gpio_irq_handler,
320 port);
321
322 err = bgpio_init(&port->gc, &pdev->dev, 4,
323 port->base + PINCTRL_DIN(port),
324 port->base + PINCTRL_DOUT(port) + MXS_SET,
325 port->base + PINCTRL_DOUT(port) + MXS_CLR,
326 port->base + PINCTRL_DOE(port), NULL, 0);
327 if (err)
328 goto out_irqdomain_remove;
329
330 port->gc.to_irq = mxs_gpio_to_irq;
331 port->gc.get_direction = mxs_gpio_get_direction;
332 port->gc.base = port->id * 32;
333
334 err = gpiochip_add_data(&port->gc, port);
335 if (err)
336 goto out_irqdomain_remove;
337
338 return 0;
339
340out_irqdomain_remove:
341 irq_domain_remove(port->domain);
342out_iounmap:
343 iounmap(port->base);
344 return err;
345}
346
347static struct platform_driver mxs_gpio_driver = {
348 .driver = {
349 .name = "gpio-mxs",
350 .of_match_table = mxs_gpio_dt_ids,
351 .suppress_bind_attrs = true,
352 },
353 .probe = mxs_gpio_probe,
354};
355
356static int __init mxs_gpio_init(void)
357{
358 return platform_driver_register(&mxs_gpio_driver);
359}
360postcore_initcall(mxs_gpio_init);
361
362MODULE_AUTHOR("Freescale Semiconductor, "
363 "Daniel Mack <danielncaiaq.de>, "
364 "Juergen Beisert <kernel@pengutronix.de>");
365MODULE_DESCRIPTION("Freescale MXS GPIO");
1/*
2 * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 *
5 * Based on code from Freescale,
6 * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
20 * MA 02110-1301, USA.
21 */
22
23#include <linux/init.h>
24#include <linux/interrupt.h>
25#include <linux/io.h>
26#include <linux/irq.h>
27#include <linux/gpio.h>
28#include <linux/of.h>
29#include <linux/of_address.h>
30#include <linux/of_device.h>
31#include <linux/platform_device.h>
32#include <linux/slab.h>
33#include <linux/basic_mmio_gpio.h>
34#include <linux/module.h>
35
36#define MXS_SET 0x4
37#define MXS_CLR 0x8
38
39#define PINCTRL_DOUT(p) ((is_imx23_gpio(p) ? 0x0500 : 0x0700) + (p->id) * 0x10)
40#define PINCTRL_DIN(p) ((is_imx23_gpio(p) ? 0x0600 : 0x0900) + (p->id) * 0x10)
41#define PINCTRL_DOE(p) ((is_imx23_gpio(p) ? 0x0700 : 0x0b00) + (p->id) * 0x10)
42#define PINCTRL_PIN2IRQ(p) ((is_imx23_gpio(p) ? 0x0800 : 0x1000) + (p->id) * 0x10)
43#define PINCTRL_IRQEN(p) ((is_imx23_gpio(p) ? 0x0900 : 0x1100) + (p->id) * 0x10)
44#define PINCTRL_IRQLEV(p) ((is_imx23_gpio(p) ? 0x0a00 : 0x1200) + (p->id) * 0x10)
45#define PINCTRL_IRQPOL(p) ((is_imx23_gpio(p) ? 0x0b00 : 0x1300) + (p->id) * 0x10)
46#define PINCTRL_IRQSTAT(p) ((is_imx23_gpio(p) ? 0x0c00 : 0x1400) + (p->id) * 0x10)
47
48#define GPIO_INT_FALL_EDGE 0x0
49#define GPIO_INT_LOW_LEV 0x1
50#define GPIO_INT_RISE_EDGE 0x2
51#define GPIO_INT_HIGH_LEV 0x3
52#define GPIO_INT_LEV_MASK (1 << 0)
53#define GPIO_INT_POL_MASK (1 << 1)
54
55#define irq_to_gpio(irq) ((irq) - MXS_GPIO_IRQ_START)
56
57enum mxs_gpio_id {
58 IMX23_GPIO,
59 IMX28_GPIO,
60};
61
62struct mxs_gpio_port {
63 void __iomem *base;
64 int id;
65 int irq;
66 int virtual_irq_start;
67 struct bgpio_chip bgc;
68 enum mxs_gpio_id devid;
69};
70
71static inline int is_imx23_gpio(struct mxs_gpio_port *port)
72{
73 return port->devid == IMX23_GPIO;
74}
75
76static inline int is_imx28_gpio(struct mxs_gpio_port *port)
77{
78 return port->devid == IMX28_GPIO;
79}
80
81/* Note: This driver assumes 32 GPIOs are handled in one register */
82
83static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
84{
85 u32 gpio = irq_to_gpio(d->irq);
86 u32 pin_mask = 1 << (gpio & 31);
87 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
88 struct mxs_gpio_port *port = gc->private;
89 void __iomem *pin_addr;
90 int edge;
91
92 switch (type) {
93 case IRQ_TYPE_EDGE_RISING:
94 edge = GPIO_INT_RISE_EDGE;
95 break;
96 case IRQ_TYPE_EDGE_FALLING:
97 edge = GPIO_INT_FALL_EDGE;
98 break;
99 case IRQ_TYPE_LEVEL_LOW:
100 edge = GPIO_INT_LOW_LEV;
101 break;
102 case IRQ_TYPE_LEVEL_HIGH:
103 edge = GPIO_INT_HIGH_LEV;
104 break;
105 default:
106 return -EINVAL;
107 }
108
109 /* set level or edge */
110 pin_addr = port->base + PINCTRL_IRQLEV(port);
111 if (edge & GPIO_INT_LEV_MASK)
112 writel(pin_mask, pin_addr + MXS_SET);
113 else
114 writel(pin_mask, pin_addr + MXS_CLR);
115
116 /* set polarity */
117 pin_addr = port->base + PINCTRL_IRQPOL(port);
118 if (edge & GPIO_INT_POL_MASK)
119 writel(pin_mask, pin_addr + MXS_SET);
120 else
121 writel(pin_mask, pin_addr + MXS_CLR);
122
123 writel(1 << (gpio & 0x1f),
124 port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
125
126 return 0;
127}
128
129/* MXS has one interrupt *per* gpio port */
130static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc)
131{
132 u32 irq_stat;
133 struct mxs_gpio_port *port = irq_get_handler_data(irq);
134 u32 gpio_irq_no_base = port->virtual_irq_start;
135
136 desc->irq_data.chip->irq_ack(&desc->irq_data);
137
138 irq_stat = readl(port->base + PINCTRL_IRQSTAT(port)) &
139 readl(port->base + PINCTRL_IRQEN(port));
140
141 while (irq_stat != 0) {
142 int irqoffset = fls(irq_stat) - 1;
143 generic_handle_irq(gpio_irq_no_base + irqoffset);
144 irq_stat &= ~(1 << irqoffset);
145 }
146}
147
148/*
149 * Set interrupt number "irq" in the GPIO as a wake-up source.
150 * While system is running, all registered GPIO interrupts need to have
151 * wake-up enabled. When system is suspended, only selected GPIO interrupts
152 * need to have wake-up enabled.
153 * @param irq interrupt source number
154 * @param enable enable as wake-up if equal to non-zero
155 * @return This function returns 0 on success.
156 */
157static int mxs_gpio_set_wake_irq(struct irq_data *d, unsigned int enable)
158{
159 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
160 struct mxs_gpio_port *port = gc->private;
161
162 if (enable)
163 enable_irq_wake(port->irq);
164 else
165 disable_irq_wake(port->irq);
166
167 return 0;
168}
169
170static void __init mxs_gpio_init_gc(struct mxs_gpio_port *port)
171{
172 struct irq_chip_generic *gc;
173 struct irq_chip_type *ct;
174
175 gc = irq_alloc_generic_chip("gpio-mxs", 1, port->virtual_irq_start,
176 port->base, handle_level_irq);
177 gc->private = port;
178
179 ct = gc->chip_types;
180 ct->chip.irq_ack = irq_gc_ack_set_bit;
181 ct->chip.irq_mask = irq_gc_mask_clr_bit;
182 ct->chip.irq_unmask = irq_gc_mask_set_bit;
183 ct->chip.irq_set_type = mxs_gpio_set_irq_type;
184 ct->chip.irq_set_wake = mxs_gpio_set_wake_irq;
185 ct->regs.ack = PINCTRL_IRQSTAT(port) + MXS_CLR;
186 ct->regs.mask = PINCTRL_IRQEN(port);
187
188 irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);
189}
190
191static int mxs_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
192{
193 struct bgpio_chip *bgc = to_bgpio_chip(gc);
194 struct mxs_gpio_port *port =
195 container_of(bgc, struct mxs_gpio_port, bgc);
196
197 return port->virtual_irq_start + offset;
198}
199
200static struct platform_device_id mxs_gpio_ids[] = {
201 {
202 .name = "imx23-gpio",
203 .driver_data = IMX23_GPIO,
204 }, {
205 .name = "imx28-gpio",
206 .driver_data = IMX28_GPIO,
207 }, {
208 /* sentinel */
209 }
210};
211MODULE_DEVICE_TABLE(platform, mxs_gpio_ids);
212
213static const struct of_device_id mxs_gpio_dt_ids[] = {
214 { .compatible = "fsl,imx23-gpio", .data = (void *) IMX23_GPIO, },
215 { .compatible = "fsl,imx28-gpio", .data = (void *) IMX28_GPIO, },
216 { /* sentinel */ }
217};
218MODULE_DEVICE_TABLE(of, mxs_gpio_dt_ids);
219
220static int __devinit mxs_gpio_probe(struct platform_device *pdev)
221{
222 const struct of_device_id *of_id =
223 of_match_device(mxs_gpio_dt_ids, &pdev->dev);
224 struct device_node *np = pdev->dev.of_node;
225 struct device_node *parent;
226 static void __iomem *base;
227 struct mxs_gpio_port *port;
228 struct resource *iores = NULL;
229 int err;
230
231 port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
232 if (!port)
233 return -ENOMEM;
234
235 if (np) {
236 port->id = of_alias_get_id(np, "gpio");
237 if (port->id < 0)
238 return port->id;
239 port->devid = (enum mxs_gpio_id) of_id->data;
240 } else {
241 port->id = pdev->id;
242 port->devid = pdev->id_entry->driver_data;
243 }
244 port->virtual_irq_start = MXS_GPIO_IRQ_START + port->id * 32;
245
246 port->irq = platform_get_irq(pdev, 0);
247 if (port->irq < 0)
248 return port->irq;
249
250 /*
251 * map memory region only once, as all the gpio ports
252 * share the same one
253 */
254 if (!base) {
255 if (np) {
256 parent = of_get_parent(np);
257 base = of_iomap(parent, 0);
258 of_node_put(parent);
259 } else {
260 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
261 base = devm_request_and_ioremap(&pdev->dev, iores);
262 }
263 if (!base)
264 return -EADDRNOTAVAIL;
265 }
266 port->base = base;
267
268 /*
269 * select the pin interrupt functionality but initially
270 * disable the interrupts
271 */
272 writel(~0U, port->base + PINCTRL_PIN2IRQ(port));
273 writel(0, port->base + PINCTRL_IRQEN(port));
274
275 /* clear address has to be used to clear IRQSTAT bits */
276 writel(~0U, port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
277
278 /* gpio-mxs can be a generic irq chip */
279 mxs_gpio_init_gc(port);
280
281 /* setup one handler for each entry */
282 irq_set_chained_handler(port->irq, mxs_gpio_irq_handler);
283 irq_set_handler_data(port->irq, port);
284
285 err = bgpio_init(&port->bgc, &pdev->dev, 4,
286 port->base + PINCTRL_DIN(port),
287 port->base + PINCTRL_DOUT(port), NULL,
288 port->base + PINCTRL_DOE(port), NULL, 0);
289 if (err)
290 return err;
291
292 port->bgc.gc.to_irq = mxs_gpio_to_irq;
293 port->bgc.gc.base = port->id * 32;
294
295 err = gpiochip_add(&port->bgc.gc);
296 if (err) {
297 bgpio_remove(&port->bgc);
298 return err;
299 }
300
301 return 0;
302}
303
304static struct platform_driver mxs_gpio_driver = {
305 .driver = {
306 .name = "gpio-mxs",
307 .owner = THIS_MODULE,
308 .of_match_table = mxs_gpio_dt_ids,
309 },
310 .probe = mxs_gpio_probe,
311 .id_table = mxs_gpio_ids,
312};
313
314static int __init mxs_gpio_init(void)
315{
316 return platform_driver_register(&mxs_gpio_driver);
317}
318postcore_initcall(mxs_gpio_init);
319
320MODULE_AUTHOR("Freescale Semiconductor, "
321 "Daniel Mack <danielncaiaq.de>, "
322 "Juergen Beisert <kernel@pengutronix.de>");
323MODULE_DESCRIPTION("Freescale MXS GPIO");
324MODULE_LICENSE("GPL");