1// SPDX-License-Identifier: GPL-2.0-only
   2/* cpu_feature_enabled() cannot be used this early */
   3#define USE_EARLY_PGTABLE_L5
   4
   5#include <linux/memblock.h>
   6#include <linux/linkage.h>
   7#include <linux/bitops.h>
   8#include <linux/kernel.h>
   9#include <linux/export.h>
  10#include <linux/percpu.h>
  11#include <linux/string.h>
  12#include <linux/ctype.h>
  13#include <linux/delay.h>
  14#include <linux/sched/mm.h>
  15#include <linux/sched/clock.h>
  16#include <linux/sched/task.h>
  17#include <linux/sched/smt.h>
  18#include <linux/init.h>
  19#include <linux/kprobes.h>
  20#include <linux/kgdb.h>
  21#include <linux/mem_encrypt.h>
  22#include <linux/smp.h>
  23#include <linux/cpu.h>
  24#include <linux/io.h>
  25#include <linux/syscore_ops.h>
  26#include <linux/pgtable.h>
  27#include <linux/stackprotector.h>
  28#include <linux/utsname.h>
  29
  30#include <asm/alternative.h>
  31#include <asm/cmdline.h>
  32#include <asm/perf_event.h>
  33#include <asm/mmu_context.h>
  34#include <asm/doublefault.h>
  35#include <asm/archrandom.h>
  36#include <asm/hypervisor.h>
  37#include <asm/processor.h>
  38#include <asm/tlbflush.h>
  39#include <asm/debugreg.h>
  40#include <asm/sections.h>
  41#include <asm/vsyscall.h>
  42#include <linux/topology.h>
  43#include <linux/cpumask.h>
 
  44#include <linux/atomic.h>
  45#include <asm/proto.h>
  46#include <asm/setup.h>
  47#include <asm/apic.h>
  48#include <asm/desc.h>
  49#include <asm/fpu/api.h>
 
  50#include <asm/mtrr.h>
  51#include <asm/hwcap2.h>
  52#include <linux/numa.h>
  53#include <asm/numa.h>
  54#include <asm/asm.h>
  55#include <asm/bugs.h>
  56#include <asm/cpu.h>
  57#include <asm/mce.h>
  58#include <asm/msr.h>
  59#include <asm/cacheinfo.h>
  60#include <asm/memtype.h>
  61#include <asm/microcode.h>
  62#include <asm/intel-family.h>
  63#include <asm/cpu_device_id.h>
  64#include <asm/fred.h>
  65#include <asm/uv/uv.h>
  66#include <asm/ia32.h>
  67#include <asm/set_memory.h>
  68#include <asm/traps.h>
  69#include <asm/sev.h>
  70#include <asm/tdx.h>
  71#include <asm/posted_intr.h>
  72#include <asm/runtime-const.h>
  73
  74#include "cpu.h"
  75
  76DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
  77EXPORT_PER_CPU_SYMBOL(cpu_info);
  78
  79u32 elf_hwcap2 __read_mostly;
  80
  81/* Number of siblings per CPU package */
  82unsigned int __max_threads_per_core __ro_after_init = 1;
  83EXPORT_SYMBOL(__max_threads_per_core);
  84
  85unsigned int __max_dies_per_package __ro_after_init = 1;
  86EXPORT_SYMBOL(__max_dies_per_package);
  87
  88unsigned int __max_logical_packages __ro_after_init = 1;
  89EXPORT_SYMBOL(__max_logical_packages);
  90
  91unsigned int __num_cores_per_package __ro_after_init = 1;
  92EXPORT_SYMBOL(__num_cores_per_package);
  93
  94unsigned int __num_threads_per_package __ro_after_init = 1;
  95EXPORT_SYMBOL(__num_threads_per_package);
  96
  97static struct ppin_info {
  98	int	feature;
  99	int	msr_ppin_ctl;
 100	int	msr_ppin;
 101} ppin_info[] = {
 102	[X86_VENDOR_INTEL] = {
 103		.feature = X86_FEATURE_INTEL_PPIN,
 104		.msr_ppin_ctl = MSR_PPIN_CTL,
 105		.msr_ppin = MSR_PPIN
 106	},
 107	[X86_VENDOR_AMD] = {
 108		.feature = X86_FEATURE_AMD_PPIN,
 109		.msr_ppin_ctl = MSR_AMD_PPIN_CTL,
 110		.msr_ppin = MSR_AMD_PPIN
 111	},
 112};
 113
 114static const struct x86_cpu_id ppin_cpuids[] = {
 115	X86_MATCH_FEATURE(X86_FEATURE_AMD_PPIN, &ppin_info[X86_VENDOR_AMD]),
 116	X86_MATCH_FEATURE(X86_FEATURE_INTEL_PPIN, &ppin_info[X86_VENDOR_INTEL]),
 117
 118	/* Legacy models without CPUID enumeration */
 119	X86_MATCH_VFM(INTEL_IVYBRIDGE_X, &ppin_info[X86_VENDOR_INTEL]),
 120	X86_MATCH_VFM(INTEL_HASWELL_X, &ppin_info[X86_VENDOR_INTEL]),
 121	X86_MATCH_VFM(INTEL_BROADWELL_D, &ppin_info[X86_VENDOR_INTEL]),
 122	X86_MATCH_VFM(INTEL_BROADWELL_X, &ppin_info[X86_VENDOR_INTEL]),
 123	X86_MATCH_VFM(INTEL_SKYLAKE_X, &ppin_info[X86_VENDOR_INTEL]),
 124	X86_MATCH_VFM(INTEL_ICELAKE_X, &ppin_info[X86_VENDOR_INTEL]),
 125	X86_MATCH_VFM(INTEL_ICELAKE_D, &ppin_info[X86_VENDOR_INTEL]),
 126	X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X, &ppin_info[X86_VENDOR_INTEL]),
 127	X86_MATCH_VFM(INTEL_EMERALDRAPIDS_X, &ppin_info[X86_VENDOR_INTEL]),
 128	X86_MATCH_VFM(INTEL_XEON_PHI_KNL, &ppin_info[X86_VENDOR_INTEL]),
 129	X86_MATCH_VFM(INTEL_XEON_PHI_KNM, &ppin_info[X86_VENDOR_INTEL]),
 130
 131	{}
 132};
 133
 134static void ppin_init(struct cpuinfo_x86 *c)
 
 135{
 136	const struct x86_cpu_id *id;
 137	unsigned long long val;
 138	struct ppin_info *info;
 139
 140	id = x86_match_cpu(ppin_cpuids);
 141	if (!id)
 142		return;
 143
 144	/*
 145	 * Testing the presence of the MSR is not enough. Need to check
 146	 * that the PPIN_CTL allows reading of the PPIN.
 147	 */
 148	info = (struct ppin_info *)id->driver_data;
 149
 150	if (rdmsrl_safe(info->msr_ppin_ctl, &val))
 151		goto clear_ppin;
 152
 153	if ((val & 3UL) == 1UL) {
 154		/* PPIN locked in disabled mode */
 155		goto clear_ppin;
 156	}
 157
 158	/* If PPIN is disabled, try to enable */
 159	if (!(val & 2UL)) {
 160		wrmsrl_safe(info->msr_ppin_ctl,  val | 2UL);
 161		rdmsrl_safe(info->msr_ppin_ctl, &val);
 162	}
 163
 164	/* Is the enable bit set? */
 165	if (val & 2UL) {
 166		c->ppin = __rdmsr(info->msr_ppin);
 167		set_cpu_cap(c, info->feature);
 168		return;
 169	}
 170
 171clear_ppin:
 172	setup_clear_cpu_cap(info->feature);
 173}
 174
 175static void default_init(struct cpuinfo_x86 *c)
 176{
 177#ifdef CONFIG_X86_64
 178	cpu_detect_cache_sizes(c);
 179#else
 180	/* Not much we can do here... */
 181	/* Check if at least it has cpuid */
 182	if (c->cpuid_level == -1) {
 183		/* No cpuid. It must be an ancient CPU */
 184		if (c->x86 == 4)
 185			strcpy(c->x86_model_id, "486");
 186		else if (c->x86 == 3)
 187			strcpy(c->x86_model_id, "386");
 188	}
 189#endif
 190}
 191
 192static const struct cpu_dev default_cpu = {
 193	.c_init		= default_init,
 194	.c_vendor	= "Unknown",
 195	.c_x86_vendor	= X86_VENDOR_UNKNOWN,
 196};
 197
 198static const struct cpu_dev *this_cpu = &default_cpu;
 199
 200DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
 201#ifdef CONFIG_X86_64
 202	/*
 203	 * We need valid kernel segments for data and code in long mode too
 204	 * IRET will check the segment types  kkeil 2000/10/28
 205	 * Also sysret mandates a special GDT layout
 206	 *
 207	 * TLS descriptors are currently at a different place compared to i386.
 208	 * Hopefully nobody expects them at a fixed place (Wine?)
 209	 */
 210	[GDT_ENTRY_KERNEL32_CS]		= GDT_ENTRY_INIT(DESC_CODE32, 0, 0xfffff),
 211	[GDT_ENTRY_KERNEL_CS]		= GDT_ENTRY_INIT(DESC_CODE64, 0, 0xfffff),
 212	[GDT_ENTRY_KERNEL_DS]		= GDT_ENTRY_INIT(DESC_DATA64, 0, 0xfffff),
 213	[GDT_ENTRY_DEFAULT_USER32_CS]	= GDT_ENTRY_INIT(DESC_CODE32 | DESC_USER, 0, 0xfffff),
 214	[GDT_ENTRY_DEFAULT_USER_DS]	= GDT_ENTRY_INIT(DESC_DATA64 | DESC_USER, 0, 0xfffff),
 215	[GDT_ENTRY_DEFAULT_USER_CS]	= GDT_ENTRY_INIT(DESC_CODE64 | DESC_USER, 0, 0xfffff),
 216#else
 217	[GDT_ENTRY_KERNEL_CS]		= GDT_ENTRY_INIT(DESC_CODE32, 0, 0xfffff),
 218	[GDT_ENTRY_KERNEL_DS]		= GDT_ENTRY_INIT(DESC_DATA32, 0, 0xfffff),
 219	[GDT_ENTRY_DEFAULT_USER_CS]	= GDT_ENTRY_INIT(DESC_CODE32 | DESC_USER, 0, 0xfffff),
 220	[GDT_ENTRY_DEFAULT_USER_DS]	= GDT_ENTRY_INIT(DESC_DATA32 | DESC_USER, 0, 0xfffff),
 221	/*
 222	 * Segments used for calling PnP BIOS have byte granularity.
 223	 * They code segments and data segments have fixed 64k limits,
 224	 * the transfer segment sizes are set at run time.
 225	 */
 226	[GDT_ENTRY_PNPBIOS_CS32]	= GDT_ENTRY_INIT(DESC_CODE32_BIOS, 0, 0xffff),
 227	[GDT_ENTRY_PNPBIOS_CS16]	= GDT_ENTRY_INIT(DESC_CODE16, 0, 0xffff),
 228	[GDT_ENTRY_PNPBIOS_DS]		= GDT_ENTRY_INIT(DESC_DATA16, 0, 0xffff),
 229	[GDT_ENTRY_PNPBIOS_TS1]		= GDT_ENTRY_INIT(DESC_DATA16, 0, 0),
 230	[GDT_ENTRY_PNPBIOS_TS2]		= GDT_ENTRY_INIT(DESC_DATA16, 0, 0),
 
 
 
 
 
 231	/*
 232	 * The APM segments have byte granularity and their bases
 233	 * are set at run time.  All have 64k limits.
 234	 */
 235	[GDT_ENTRY_APMBIOS_BASE]	= GDT_ENTRY_INIT(DESC_CODE32_BIOS, 0, 0xffff),
 236	[GDT_ENTRY_APMBIOS_BASE+1]	= GDT_ENTRY_INIT(DESC_CODE16, 0, 0xffff),
 237	[GDT_ENTRY_APMBIOS_BASE+2]	= GDT_ENTRY_INIT(DESC_DATA32_BIOS, 0, 0xffff),
 238
 239	[GDT_ENTRY_ESPFIX_SS]		= GDT_ENTRY_INIT(DESC_DATA32, 0, 0xfffff),
 240	[GDT_ENTRY_PERCPU]		= GDT_ENTRY_INIT(DESC_DATA32, 0, 0xfffff),
 
 
 
 
 241#endif
 242} };
 243EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
 244
 245#ifdef CONFIG_X86_64
 246static int __init x86_nopcid_setup(char *s)
 247{
 248	/* nopcid doesn't accept parameters */
 249	if (s)
 250		return -EINVAL;
 251
 252	/* do not emit a message if the feature is not present */
 253	if (!boot_cpu_has(X86_FEATURE_PCID))
 254		return 0;
 255
 256	setup_clear_cpu_cap(X86_FEATURE_PCID);
 257	pr_info("nopcid: PCID feature disabled\n");
 258	return 0;
 
 259}
 260early_param("nopcid", x86_nopcid_setup);
 261#endif
 262
 263static int __init x86_noinvpcid_setup(char *s)
 
 
 
 
 264{
 265	/* noinvpcid doesn't accept parameters */
 266	if (s)
 267		return -EINVAL;
 
 268
 269	/* do not emit a message if the feature is not present */
 270	if (!boot_cpu_has(X86_FEATURE_INVPCID))
 271		return 0;
 
 
 
 
 272
 273	setup_clear_cpu_cap(X86_FEATURE_INVPCID);
 274	pr_info("noinvpcid: INVPCID feature disabled\n");
 275	return 0;
 
 276}
 277early_param("noinvpcid", x86_noinvpcid_setup);
 278
 279/* Standard macro to see if a specific flag is changeable */
 280static inline bool flag_is_changeable_p(unsigned long flag)
 281{
 282	unsigned long f1, f2;
 283
 284	if (!IS_ENABLED(CONFIG_X86_32))
 285		return true;
 286
 287	/*
 288	 * Cyrix and IDT cpus allow disabling of CPUID
 289	 * so the code below may return different results
 290	 * when it is executed before and after enabling
 291	 * the CPUID. Add "volatile" to not allow gcc to
 292	 * optimize the subsequent calls to this function.
 293	 */
 294	asm volatile ("pushfl		\n\t"
 295		      "pushfl		\n\t"
 296		      "popl %0		\n\t"
 297		      "movl %0, %1	\n\t"
 298		      "xorl %2, %0	\n\t"
 299		      "pushl %0		\n\t"
 300		      "popfl		\n\t"
 301		      "pushfl		\n\t"
 302		      "popl %0		\n\t"
 303		      "popfl		\n\t"
 304
 305		      : "=&r" (f1), "=&r" (f2)
 306		      : "ir" (flag));
 307
 308	return (f1 ^ f2) & flag;
 309}
 310
 311#ifdef CONFIG_X86_32
 312static int cachesize_override = -1;
 313static int disable_x86_serial_nr = 1;
 314
 315static int __init cachesize_setup(char *str)
 316{
 317	get_option(&str, &cachesize_override);
 318	return 1;
 319}
 320__setup("cachesize=", cachesize_setup);
 321
 322/* Probe for the CPUID instruction */
 323bool have_cpuid_p(void)
 324{
 325	return flag_is_changeable_p(X86_EFLAGS_ID);
 326}
 327
 328static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
 329{
 330	unsigned long lo, hi;
 331
 332	if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr)
 333		return;
 334
 335	/* Disable processor serial number: */
 336
 337	rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
 338	lo |= 0x200000;
 339	wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
 340
 341	pr_notice("CPU serial number disabled.\n");
 342	clear_cpu_cap(c, X86_FEATURE_PN);
 343
 344	/* Disabling the serial number may affect the cpuid level */
 345	c->cpuid_level = cpuid_eax(0);
 346}
 347
 348static int __init x86_serial_nr_setup(char *s)
 349{
 350	disable_x86_serial_nr = 0;
 351	return 1;
 352}
 353__setup("serialnumber", x86_serial_nr_setup);
 354#else
 355static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
 356{
 357}
 358#endif
 359
 360static __always_inline void setup_smep(struct cpuinfo_x86 *c)
 361{
 362	if (cpu_has(c, X86_FEATURE_SMEP))
 363		cr4_set_bits(X86_CR4_SMEP);
 364}
 365
 366static __always_inline void setup_smap(struct cpuinfo_x86 *c)
 367{
 368	unsigned long eflags = native_save_fl();
 369
 370	/* This should have been cleared long ago */
 371	BUG_ON(eflags & X86_EFLAGS_AC);
 372
 373	if (cpu_has(c, X86_FEATURE_SMAP))
 374		cr4_set_bits(X86_CR4_SMAP);
 375}
 376
 377static __always_inline void setup_umip(struct cpuinfo_x86 *c)
 378{
 379	/* Check the boot processor, plus build option for UMIP. */
 380	if (!cpu_feature_enabled(X86_FEATURE_UMIP))
 381		goto out;
 382
 383	/* Check the current processor's cpuid bits. */
 384	if (!cpu_has(c, X86_FEATURE_UMIP))
 385		goto out;
 386
 387	cr4_set_bits(X86_CR4_UMIP);
 388
 389	pr_info_once("x86/cpu: User Mode Instruction Prevention (UMIP) activated\n");
 390
 391	return;
 392
 393out:
 394	/*
 395	 * Make sure UMIP is disabled in case it was enabled in a
 396	 * previous boot (e.g., via kexec).
 397	 */
 398	cr4_clear_bits(X86_CR4_UMIP);
 399}
 400
 401/* These bits should not change their value after CPU init is finished. */
 402static const unsigned long cr4_pinned_mask = X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP |
 403					     X86_CR4_FSGSBASE | X86_CR4_CET | X86_CR4_FRED;
 404static DEFINE_STATIC_KEY_FALSE_RO(cr_pinning);
 405static unsigned long cr4_pinned_bits __ro_after_init;
 406
 407void native_write_cr0(unsigned long val)
 408{
 409	unsigned long bits_missing = 0;
 410
 411set_register:
 412	asm volatile("mov %0,%%cr0": "+r" (val) : : "memory");
 413
 414	if (static_branch_likely(&cr_pinning)) {
 415		if (unlikely((val & X86_CR0_WP) != X86_CR0_WP)) {
 416			bits_missing = X86_CR0_WP;
 417			val |= bits_missing;
 418			goto set_register;
 419		}
 420		/* Warn after we've set the missing bits. */
 421		WARN_ONCE(bits_missing, "CR0 WP bit went missing!?\n");
 422	}
 423}
 424EXPORT_SYMBOL(native_write_cr0);
 425
 426void __no_profile native_write_cr4(unsigned long val)
 427{
 428	unsigned long bits_changed = 0;
 429
 430set_register:
 431	asm volatile("mov %0,%%cr4": "+r" (val) : : "memory");
 432
 433	if (static_branch_likely(&cr_pinning)) {
 434		if (unlikely((val & cr4_pinned_mask) != cr4_pinned_bits)) {
 435			bits_changed = (val & cr4_pinned_mask) ^ cr4_pinned_bits;
 436			val = (val & ~cr4_pinned_mask) | cr4_pinned_bits;
 437			goto set_register;
 438		}
 439		/* Warn after we've corrected the changed bits. */
 440		WARN_ONCE(bits_changed, "pinned CR4 bits changed: 0x%lx!?\n",
 441			  bits_changed);
 442	}
 443}
 444#if IS_MODULE(CONFIG_LKDTM)
 445EXPORT_SYMBOL_GPL(native_write_cr4);
 446#endif
 447
 448void cr4_update_irqsoff(unsigned long set, unsigned long clear)
 449{
 450	unsigned long newval, cr4 = this_cpu_read(cpu_tlbstate.cr4);
 451
 452	lockdep_assert_irqs_disabled();
 453
 454	newval = (cr4 & ~clear) | set;
 455	if (newval != cr4) {
 456		this_cpu_write(cpu_tlbstate.cr4, newval);
 457		__write_cr4(newval);
 458	}
 459}
 460EXPORT_SYMBOL(cr4_update_irqsoff);
 461
 462/* Read the CR4 shadow. */
 463unsigned long cr4_read_shadow(void)
 464{
 465	return this_cpu_read(cpu_tlbstate.cr4);
 466}
 467EXPORT_SYMBOL_GPL(cr4_read_shadow);
 468
 469void cr4_init(void)
 470{
 471	unsigned long cr4 = __read_cr4();
 472
 473	if (boot_cpu_has(X86_FEATURE_PCID))
 474		cr4 |= X86_CR4_PCIDE;
 475	if (static_branch_likely(&cr_pinning))
 476		cr4 = (cr4 & ~cr4_pinned_mask) | cr4_pinned_bits;
 477
 478	__write_cr4(cr4);
 479
 480	/* Initialize cr4 shadow for this CPU. */
 481	this_cpu_write(cpu_tlbstate.cr4, cr4);
 482}
 483
 484/*
 485 * Once CPU feature detection is finished (and boot params have been
 486 * parsed), record any of the sensitive CR bits that are set, and
 487 * enable CR pinning.
 488 */
 489static void __init setup_cr_pinning(void)
 490{
 491	cr4_pinned_bits = this_cpu_read(cpu_tlbstate.cr4) & cr4_pinned_mask;
 492	static_key_enable(&cr_pinning.key);
 493}
 494
 495static __init int x86_nofsgsbase_setup(char *arg)
 496{
 497	/* Require an exact match without trailing characters. */
 498	if (strlen(arg))
 499		return 0;
 500
 501	/* Do not emit a message if the feature is not present. */
 502	if (!boot_cpu_has(X86_FEATURE_FSGSBASE))
 503		return 1;
 504
 505	setup_clear_cpu_cap(X86_FEATURE_FSGSBASE);
 506	pr_info("FSGSBASE disabled via kernel command line\n");
 507	return 1;
 508}
 509__setup("nofsgsbase", x86_nofsgsbase_setup);
 510
 511/*
 512 * Protection Keys are not available in 32-bit mode.
 513 */
 514static bool pku_disabled;
 515
 516static __always_inline void setup_pku(struct cpuinfo_x86 *c)
 517{
 518	if (c == &boot_cpu_data) {
 519		if (pku_disabled || !cpu_feature_enabled(X86_FEATURE_PKU))
 520			return;
 521		/*
 522		 * Setting CR4.PKE will cause the X86_FEATURE_OSPKE cpuid
 523		 * bit to be set.  Enforce it.
 524		 */
 525		setup_force_cpu_cap(X86_FEATURE_OSPKE);
 526
 527	} else if (!cpu_feature_enabled(X86_FEATURE_OSPKE)) {
 528		return;
 529	}
 530
 531	cr4_set_bits(X86_CR4_PKE);
 532	/* Load the default PKRU value */
 533	pkru_write_default();
 534}
 535
 536#ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
 537static __init int setup_disable_pku(char *arg)
 538{
 539	/*
 540	 * Do not clear the X86_FEATURE_PKU bit.  All of the
 541	 * runtime checks are against OSPKE so clearing the
 542	 * bit does nothing.
 543	 *
 544	 * This way, we will see "pku" in cpuinfo, but not
 545	 * "ospke", which is exactly what we want.  It shows
 546	 * that the CPU has PKU, but the OS has not enabled it.
 547	 * This happens to be exactly how a system would look
 548	 * if we disabled the config option.
 549	 */
 550	pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n");
 551	pku_disabled = true;
 552	return 1;
 553}
 554__setup("nopku", setup_disable_pku);
 555#endif
 556
 557#ifdef CONFIG_X86_KERNEL_IBT
 558
 559__noendbr u64 ibt_save(bool disable)
 560{
 561	u64 msr = 0;
 562
 563	if (cpu_feature_enabled(X86_FEATURE_IBT)) {
 564		rdmsrl(MSR_IA32_S_CET, msr);
 565		if (disable)
 566			wrmsrl(MSR_IA32_S_CET, msr & ~CET_ENDBR_EN);
 567	}
 568
 569	return msr;
 570}
 571
 572__noendbr void ibt_restore(u64 save)
 573{
 574	u64 msr;
 575
 576	if (cpu_feature_enabled(X86_FEATURE_IBT)) {
 577		rdmsrl(MSR_IA32_S_CET, msr);
 578		msr &= ~CET_ENDBR_EN;
 579		msr |= (save & CET_ENDBR_EN);
 580		wrmsrl(MSR_IA32_S_CET, msr);
 581	}
 582}
 583
 584#endif
 585
 586static __always_inline void setup_cet(struct cpuinfo_x86 *c)
 
 587{
 588	bool user_shstk, kernel_ibt;
 589
 590	if (!IS_ENABLED(CONFIG_X86_CET))
 591		return;
 592
 593	kernel_ibt = HAS_KERNEL_IBT && cpu_feature_enabled(X86_FEATURE_IBT);
 594	user_shstk = cpu_feature_enabled(X86_FEATURE_SHSTK) &&
 595		     IS_ENABLED(CONFIG_X86_USER_SHADOW_STACK);
 596
 597	if (!kernel_ibt && !user_shstk)
 598		return;
 599
 600	if (user_shstk)
 601		set_cpu_cap(c, X86_FEATURE_USER_SHSTK);
 602
 603	if (kernel_ibt)
 604		wrmsrl(MSR_IA32_S_CET, CET_ENDBR_EN);
 605	else
 606		wrmsrl(MSR_IA32_S_CET, 0);
 607
 608	cr4_set_bits(X86_CR4_CET);
 609
 610	if (kernel_ibt && ibt_selftest()) {
 611		pr_err("IBT selftest: Failed!\n");
 612		wrmsrl(MSR_IA32_S_CET, 0);
 613		setup_clear_cpu_cap(X86_FEATURE_IBT);
 614	}
 615}
 
 616
 617__noendbr void cet_disable(void)
 618{
 619	if (!(cpu_feature_enabled(X86_FEATURE_IBT) ||
 620	      cpu_feature_enabled(X86_FEATURE_SHSTK)))
 621		return;
 622
 623	wrmsrl(MSR_IA32_S_CET, 0);
 624	wrmsrl(MSR_IA32_U_CET, 0);
 
 625}
 626
 627/*
 628 * Some CPU features depend on higher CPUID levels, which may not always
 629 * be available due to CPUID level capping or broken virtualization
 630 * software.  Add those features to this table to auto-disable them.
 631 */
 632struct cpuid_dependent_feature {
 633	u32 feature;
 634	u32 level;
 635};
 636
 637static const struct cpuid_dependent_feature
 638cpuid_dependent_features[] = {
 639	{ X86_FEATURE_MWAIT,		0x00000005 },
 640	{ X86_FEATURE_DCA,		0x00000009 },
 641	{ X86_FEATURE_XSAVE,		0x0000000d },
 642	{ 0, 0 }
 643};
 644
 645static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
 646{
 647	const struct cpuid_dependent_feature *df;
 648
 649	for (df = cpuid_dependent_features; df->feature; df++) {
 650
 651		if (!cpu_has(c, df->feature))
 652			continue;
 653		/*
 654		 * Note: cpuid_level is set to -1 if unavailable, but
 655		 * extended_extended_level is set to 0 if unavailable
 656		 * and the legitimate extended levels are all negative
 657		 * when signed; hence the weird messing around with
 658		 * signs here...
 659		 */
 660		if (!((s32)df->level < 0 ?
 661		     (u32)df->level > (u32)c->extended_cpuid_level :
 662		     (s32)df->level > (s32)c->cpuid_level))
 663			continue;
 664
 665		clear_cpu_cap(c, df->feature);
 666		if (!warn)
 667			continue;
 668
 669		pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n",
 670			x86_cap_flag(df->feature), df->level);
 
 671	}
 672}
 673
 674/*
 675 * Naming convention should be: <Name> [(<Codename>)]
 676 * This table only is used unless init_<vendor>() below doesn't set it;
 677 * in particular, if CPUID levels 0x80000002..4 are supported, this
 678 * isn't used
 679 */
 680
 681/* Look up CPU names by table lookup. */
 682static const char *table_lookup_model(struct cpuinfo_x86 *c)
 683{
 684#ifdef CONFIG_X86_32
 685	const struct legacy_cpu_model_info *info;
 686
 687	if (c->x86_model >= 16)
 688		return NULL;	/* Range check */
 689
 690	if (!this_cpu)
 691		return NULL;
 692
 693	info = this_cpu->legacy_models;
 694
 695	while (info->family) {
 696		if (info->family == c->x86)
 697			return info->model_names[c->x86_model];
 698		info++;
 699	}
 700#endif
 701	return NULL;		/* Not found */
 702}
 703
 704/* Aligned to unsigned long to avoid split lock in atomic bitmap ops */
 705__u32 cpu_caps_cleared[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long));
 706__u32 cpu_caps_set[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long));
 707
 
 
 708#ifdef CONFIG_X86_32
 709/* The 32-bit entry code needs to find cpu_entry_area. */
 710DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area);
 
 
 711#endif
 712
 713/* Load the original GDT from the per-cpu structure */
 714void load_direct_gdt(int cpu)
 715{
 716	struct desc_ptr gdt_descr;
 717
 718	gdt_descr.address = (long)get_cpu_gdt_rw(cpu);
 719	gdt_descr.size = GDT_SIZE - 1;
 720	load_gdt(&gdt_descr);
 721}
 722EXPORT_SYMBOL_GPL(load_direct_gdt);
 723
 724/* Load a fixmap remapping of the per-cpu GDT */
 725void load_fixmap_gdt(int cpu)
 
 
 
 726{
 727	struct desc_ptr gdt_descr;
 728
 729	gdt_descr.address = (long)get_cpu_gdt_ro(cpu);
 730	gdt_descr.size = GDT_SIZE - 1;
 731	load_gdt(&gdt_descr);
 732}
 733EXPORT_SYMBOL_GPL(load_fixmap_gdt);
 734
 735/**
 736 * switch_gdt_and_percpu_base - Switch to direct GDT and runtime per CPU base
 737 * @cpu:	The CPU number for which this is invoked
 738 *
 739 * Invoked during early boot to switch from early GDT and early per CPU to
 740 * the direct GDT and the runtime per CPU area. On 32-bit the percpu base
 741 * switch is implicit by loading the direct GDT. On 64bit this requires
 742 * to update GSBASE.
 743 */
 744void __init switch_gdt_and_percpu_base(int cpu)
 745{
 746	load_direct_gdt(cpu);
 747
 748#ifdef CONFIG_X86_64
 749	/*
 750	 * No need to load %gs. It is already correct.
 751	 *
 752	 * Writing %gs on 64bit would zero GSBASE which would make any per
 753	 * CPU operation up to the point of the wrmsrl() fault.
 754	 *
 755	 * Set GSBASE to the new offset. Until the wrmsrl() happens the
 756	 * early mapping is still valid. That means the GSBASE update will
 757	 * lose any prior per CPU data which was not copied over in
 758	 * setup_per_cpu_areas().
 759	 *
 760	 * This works even with stackprotector enabled because the
 761	 * per CPU stack canary is 0 in both per CPU areas.
 762	 */
 763	wrmsrl(MSR_GS_BASE, cpu_kernelmode_gs_base(cpu));
 764#else
 765	/*
 766	 * %fs is already set to __KERNEL_PERCPU, but after switching GDT
 767	 * it is required to load FS again so that the 'hidden' part is
 768	 * updated from the new GDT. Up to this point the early per CPU
 769	 * translation is active. Any content of the early per CPU data
 770	 * which was not copied over in setup_per_cpu_areas() is lost.
 771	 */
 772	loadsegment(fs, __KERNEL_PERCPU);
 773#endif
 774}
 775
 776static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
 777
 778static void get_model_name(struct cpuinfo_x86 *c)
 779{
 780	unsigned int *v;
 781	char *p, *q, *s;
 782
 783	if (c->extended_cpuid_level < 0x80000004)
 784		return;
 785
 786	v = (unsigned int *)c->x86_model_id;
 787	cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
 788	cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
 789	cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
 790	c->x86_model_id[48] = 0;
 791
 792	/* Trim whitespace */
 793	p = q = s = &c->x86_model_id[0];
 794
 
 
 795	while (*p == ' ')
 796		p++;
 797
 798	while (*p) {
 799		/* Note the last non-whitespace index */
 800		if (!isspace(*p))
 801			s = q;
 802
 803		*q++ = *p++;
 804	}
 805
 806	*(s + 1) = '\0';
 807}
 808
 809void cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
 810{
 811	unsigned int n, dummy, ebx, ecx, edx, l2size;
 812
 813	n = c->extended_cpuid_level;
 814
 815	if (n >= 0x80000005) {
 816		cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
 817		c->x86_cache_size = (ecx>>24) + (edx>>24);
 818#ifdef CONFIG_X86_64
 819		/* On K8 L1 TLB is inclusive, so don't count it */
 820		c->x86_tlbsize = 0;
 821#endif
 822	}
 823
 824	if (n < 0x80000006)	/* Some chips just has a large L1. */
 825		return;
 826
 827	cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
 828	l2size = ecx >> 16;
 829
 830#ifdef CONFIG_X86_64
 831	c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
 832#else
 833	/* do processor-specific cache resizing */
 834	if (this_cpu->legacy_cache_size)
 835		l2size = this_cpu->legacy_cache_size(c, l2size);
 836
 837	/* Allow user to override all this if necessary. */
 838	if (cachesize_override != -1)
 839		l2size = cachesize_override;
 840
 841	if (l2size == 0)
 842		return;		/* Again, no L2 cache is possible */
 843#endif
 844
 845	c->x86_cache_size = l2size;
 846}
 847
 848u16 __read_mostly tlb_lli_4k[NR_INFO];
 849u16 __read_mostly tlb_lli_2m[NR_INFO];
 850u16 __read_mostly tlb_lli_4m[NR_INFO];
 851u16 __read_mostly tlb_lld_4k[NR_INFO];
 852u16 __read_mostly tlb_lld_2m[NR_INFO];
 853u16 __read_mostly tlb_lld_4m[NR_INFO];
 854u16 __read_mostly tlb_lld_1g[NR_INFO];
 855
 856static void cpu_detect_tlb(struct cpuinfo_x86 *c)
 857{
 858	if (this_cpu->c_detect_tlb)
 859		this_cpu->c_detect_tlb(c);
 
 
 860
 861	pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n",
 862		tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES],
 863		tlb_lli_4m[ENTRIES]);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 864
 865	pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n",
 866		tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES],
 867		tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]);
 
 
 
 
 
 
 868}
 869
 870void get_cpu_vendor(struct cpuinfo_x86 *c)
 871{
 872	char *v = c->x86_vendor_id;
 873	int i;
 874
 875	for (i = 0; i < X86_VENDOR_NUM; i++) {
 876		if (!cpu_devs[i])
 877			break;
 878
 879		if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
 880		    (cpu_devs[i]->c_ident[1] &&
 881		     !strcmp(v, cpu_devs[i]->c_ident[1]))) {
 882
 883			this_cpu = cpu_devs[i];
 884			c->x86_vendor = this_cpu->c_x86_vendor;
 885			return;
 886		}
 887	}
 888
 889	pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \
 890		    "CPU: Your system may be unstable.\n", v);
 
 891
 892	c->x86_vendor = X86_VENDOR_UNKNOWN;
 893	this_cpu = &default_cpu;
 894}
 895
 896void cpu_detect(struct cpuinfo_x86 *c)
 897{
 898	/* Get vendor name */
 899	cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
 900	      (unsigned int *)&c->x86_vendor_id[0],
 901	      (unsigned int *)&c->x86_vendor_id[8],
 902	      (unsigned int *)&c->x86_vendor_id[4]);
 903
 904	c->x86 = 4;
 905	/* Intel-defined flags: level 0x00000001 */
 906	if (c->cpuid_level >= 0x00000001) {
 907		u32 junk, tfms, cap0, misc;
 908
 909		cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
 910		c->x86		= x86_family(tfms);
 911		c->x86_model	= x86_model(tfms);
 912		c->x86_stepping	= x86_stepping(tfms);
 
 
 
 
 
 913
 914		if (cap0 & (1<<19)) {
 915			c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
 916			c->x86_cache_alignment = c->x86_clflush_size;
 917		}
 918	}
 919}
 920
 921static void apply_forced_caps(struct cpuinfo_x86 *c)
 922{
 923	int i;
 924
 925	for (i = 0; i < NCAPINTS + NBUGINTS; i++) {
 926		c->x86_capability[i] &= ~cpu_caps_cleared[i];
 927		c->x86_capability[i] |= cpu_caps_set[i];
 928	}
 929}
 930
 931static void init_speculation_control(struct cpuinfo_x86 *c)
 932{
 933	/*
 934	 * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support,
 935	 * and they also have a different bit for STIBP support. Also,
 936	 * a hypervisor might have set the individual AMD bits even on
 937	 * Intel CPUs, for finer-grained selection of what's available.
 938	 */
 939	if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) {
 940		set_cpu_cap(c, X86_FEATURE_IBRS);
 941		set_cpu_cap(c, X86_FEATURE_IBPB);
 942		set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
 943	}
 944
 945	if (cpu_has(c, X86_FEATURE_INTEL_STIBP))
 946		set_cpu_cap(c, X86_FEATURE_STIBP);
 947
 948	if (cpu_has(c, X86_FEATURE_SPEC_CTRL_SSBD) ||
 949	    cpu_has(c, X86_FEATURE_VIRT_SSBD))
 950		set_cpu_cap(c, X86_FEATURE_SSBD);
 951
 952	if (cpu_has(c, X86_FEATURE_AMD_IBRS)) {
 953		set_cpu_cap(c, X86_FEATURE_IBRS);
 954		set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
 955	}
 956
 957	if (cpu_has(c, X86_FEATURE_AMD_IBPB))
 958		set_cpu_cap(c, X86_FEATURE_IBPB);
 959
 960	if (cpu_has(c, X86_FEATURE_AMD_STIBP)) {
 961		set_cpu_cap(c, X86_FEATURE_STIBP);
 962		set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
 963	}
 964
 965	if (cpu_has(c, X86_FEATURE_AMD_SSBD)) {
 966		set_cpu_cap(c, X86_FEATURE_SSBD);
 967		set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
 968		clear_cpu_cap(c, X86_FEATURE_VIRT_SSBD);
 969	}
 970}
 971
 972void get_cpu_cap(struct cpuinfo_x86 *c)
 973{
 974	u32 eax, ebx, ecx, edx;
 975
 976	/* Intel-defined flags: level 0x00000001 */
 977	if (c->cpuid_level >= 0x00000001) {
 978		cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
 979
 980		c->x86_capability[CPUID_1_ECX] = ecx;
 981		c->x86_capability[CPUID_1_EDX] = edx;
 
 982	}
 983
 984	/* Thermal and Power Management Leaf: level 0x00000006 (eax) */
 985	if (c->cpuid_level >= 0x00000006)
 986		c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006);
 987
 988	/* Additional Intel-defined flags: level 0x00000007 */
 989	if (c->cpuid_level >= 0x00000007) {
 990		cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);
 991		c->x86_capability[CPUID_7_0_EBX] = ebx;
 992		c->x86_capability[CPUID_7_ECX] = ecx;
 993		c->x86_capability[CPUID_7_EDX] = edx;
 994
 995		/* Check valid sub-leaf index before accessing it */
 996		if (eax >= 1) {
 997			cpuid_count(0x00000007, 1, &eax, &ebx, &ecx, &edx);
 998			c->x86_capability[CPUID_7_1_EAX] = eax;
 999		}
1000	}
1001
1002	/* Extended state features: level 0x0000000d */
1003	if (c->cpuid_level >= 0x0000000d) {
1004		cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx);
1005
1006		c->x86_capability[CPUID_D_1_EAX] = eax;
1007	}
1008
1009	/* AMD-defined flags: level 0x80000001 */
1010	eax = cpuid_eax(0x80000000);
1011	c->extended_cpuid_level = eax;
1012
1013	if ((eax & 0xffff0000) == 0x80000000) {
1014		if (eax >= 0x80000001) {
1015			cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
1016
1017			c->x86_capability[CPUID_8000_0001_ECX] = ecx;
1018			c->x86_capability[CPUID_8000_0001_EDX] = edx;
 
 
1019		}
1020	}
1021
1022	if (c->extended_cpuid_level >= 0x80000007) {
1023		cpuid(0x80000007, &eax, &ebx, &ecx, &edx);
1024
1025		c->x86_capability[CPUID_8000_0007_EBX] = ebx;
1026		c->x86_power = edx;
1027	}
1028
1029	if (c->extended_cpuid_level >= 0x80000008) {
1030		cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
1031		c->x86_capability[CPUID_8000_0008_EBX] = ebx;
1032	}
1033
1034	if (c->extended_cpuid_level >= 0x8000000a)
1035		c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a);
1036
1037	if (c->extended_cpuid_level >= 0x8000001f)
1038		c->x86_capability[CPUID_8000_001F_EAX] = cpuid_eax(0x8000001f);
1039
1040	if (c->extended_cpuid_level >= 0x80000021)
1041		c->x86_capability[CPUID_8000_0021_EAX] = cpuid_eax(0x80000021);
1042
1043	init_scattered_cpuid_features(c);
1044	init_speculation_control(c);
1045
1046	/*
1047	 * Clear/Set all flags overridden by options, after probe.
1048	 * This needs to happen each time we re-probe, which may happen
1049	 * several times during CPU initialization.
1050	 */
1051	apply_forced_caps(c);
1052}
1053
1054void get_cpu_address_sizes(struct cpuinfo_x86 *c)
1055{
1056	u32 eax, ebx, ecx, edx;
1057
1058	if (!cpu_has(c, X86_FEATURE_CPUID) ||
1059	    (c->extended_cpuid_level < 0x80000008)) {
1060		if (IS_ENABLED(CONFIG_X86_64)) {
1061			c->x86_clflush_size = 64;
1062			c->x86_phys_bits = 36;
1063			c->x86_virt_bits = 48;
1064		} else {
1065			c->x86_clflush_size = 32;
1066			c->x86_virt_bits = 32;
1067			c->x86_phys_bits = 32;
1068
1069			if (cpu_has(c, X86_FEATURE_PAE) ||
1070			    cpu_has(c, X86_FEATURE_PSE36))
1071				c->x86_phys_bits = 36;
1072		}
1073	} else {
1074		cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
1075
1076		c->x86_virt_bits = (eax >> 8) & 0xff;
1077		c->x86_phys_bits = eax & 0xff;
1078
1079		/* Provide a sane default if not enumerated: */
1080		if (!c->x86_clflush_size)
1081			c->x86_clflush_size = 32;
1082	}
 
 
 
 
1083
1084	c->x86_cache_bits = c->x86_phys_bits;
1085	c->x86_cache_alignment = c->x86_clflush_size;
 
 
1086}
1087
1088static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
1089{
 
1090	int i;
1091
1092	/*
1093	 * First of all, decide if this is a 486 or higher
1094	 * It's a 486 if we can modify the AC flag
1095	 */
1096	if (flag_is_changeable_p(X86_EFLAGS_AC))
1097		c->x86 = 4;
1098	else
1099		c->x86 = 3;
1100
1101	for (i = 0; i < X86_VENDOR_NUM; i++)
1102		if (cpu_devs[i] && cpu_devs[i]->c_identify) {
1103			c->x86_vendor_id[0] = 0;
1104			cpu_devs[i]->c_identify(c);
1105			if (c->x86_vendor_id[0]) {
1106				get_cpu_vendor(c);
1107				break;
1108			}
1109		}
1110}
1111
1112#define NO_SPECULATION		BIT(0)
1113#define NO_MELTDOWN		BIT(1)
1114#define NO_SSB			BIT(2)
1115#define NO_L1TF			BIT(3)
1116#define NO_MDS			BIT(4)
1117#define MSBDS_ONLY		BIT(5)
1118#define NO_SWAPGS		BIT(6)
1119#define NO_ITLB_MULTIHIT	BIT(7)
1120#define NO_SPECTRE_V2		BIT(8)
1121#define NO_MMIO			BIT(9)
1122#define NO_EIBRS_PBRSB		BIT(10)
1123#define NO_BHI			BIT(11)
1124
1125#define VULNWL(vendor, family, model, whitelist)	\
1126	X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, whitelist)
1127
1128#define VULNWL_INTEL(vfm, whitelist)		\
1129	X86_MATCH_VFM(vfm, whitelist)
1130
1131#define VULNWL_AMD(family, whitelist)		\
1132	VULNWL(AMD, family, X86_MODEL_ANY, whitelist)
1133
1134#define VULNWL_HYGON(family, whitelist)		\
1135	VULNWL(HYGON, family, X86_MODEL_ANY, whitelist)
1136
1137static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = {
1138	VULNWL(ANY,	4, X86_MODEL_ANY,	NO_SPECULATION),
1139	VULNWL(CENTAUR,	5, X86_MODEL_ANY,	NO_SPECULATION),
1140	VULNWL(INTEL,	5, X86_MODEL_ANY,	NO_SPECULATION),
1141	VULNWL(NSC,	5, X86_MODEL_ANY,	NO_SPECULATION),
1142	VULNWL(VORTEX,	5, X86_MODEL_ANY,	NO_SPECULATION),
1143	VULNWL(VORTEX,	6, X86_MODEL_ANY,	NO_SPECULATION),
1144
1145	/* Intel Family 6 */
1146	VULNWL_INTEL(INTEL_TIGERLAKE,		NO_MMIO),
1147	VULNWL_INTEL(INTEL_TIGERLAKE_L,		NO_MMIO),
1148	VULNWL_INTEL(INTEL_ALDERLAKE,		NO_MMIO),
1149	VULNWL_INTEL(INTEL_ALDERLAKE_L,		NO_MMIO),
1150
1151	VULNWL_INTEL(INTEL_ATOM_SALTWELL,	NO_SPECULATION | NO_ITLB_MULTIHIT),
1152	VULNWL_INTEL(INTEL_ATOM_SALTWELL_TABLET, NO_SPECULATION | NO_ITLB_MULTIHIT),
1153	VULNWL_INTEL(INTEL_ATOM_SALTWELL_MID,	NO_SPECULATION | NO_ITLB_MULTIHIT),
1154	VULNWL_INTEL(INTEL_ATOM_BONNELL,	NO_SPECULATION | NO_ITLB_MULTIHIT),
1155	VULNWL_INTEL(INTEL_ATOM_BONNELL_MID,	NO_SPECULATION | NO_ITLB_MULTIHIT),
1156
1157	VULNWL_INTEL(INTEL_ATOM_SILVERMONT,	NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1158	VULNWL_INTEL(INTEL_ATOM_SILVERMONT_D,	NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1159	VULNWL_INTEL(INTEL_ATOM_SILVERMONT_MID,	NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1160	VULNWL_INTEL(INTEL_ATOM_AIRMONT,	NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1161	VULNWL_INTEL(INTEL_XEON_PHI_KNL,	NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1162	VULNWL_INTEL(INTEL_XEON_PHI_KNM,	NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1163
1164	VULNWL_INTEL(INTEL_CORE_YONAH,		NO_SSB),
1165
1166	VULNWL_INTEL(INTEL_ATOM_AIRMONT_MID,	NO_SSB | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | MSBDS_ONLY),
1167	VULNWL_INTEL(INTEL_ATOM_AIRMONT_NP,	NO_SSB | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT),
1168
1169	VULNWL_INTEL(INTEL_ATOM_GOLDMONT,	NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
1170	VULNWL_INTEL(INTEL_ATOM_GOLDMONT_D,	NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
1171	VULNWL_INTEL(INTEL_ATOM_GOLDMONT_PLUS,	NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB),
1172
1173	/*
1174	 * Technically, swapgs isn't serializing on AMD (despite it previously
1175	 * being documented as such in the APM).  But according to AMD, %gs is
1176	 * updated non-speculatively, and the issuing of %gs-relative memory
1177	 * operands will be blocked until the %gs update completes, which is
1178	 * good enough for our purposes.
1179	 */
1180
1181	VULNWL_INTEL(INTEL_ATOM_TREMONT,	NO_EIBRS_PBRSB),
1182	VULNWL_INTEL(INTEL_ATOM_TREMONT_L,	NO_EIBRS_PBRSB),
1183	VULNWL_INTEL(INTEL_ATOM_TREMONT_D,	NO_ITLB_MULTIHIT | NO_EIBRS_PBRSB),
1184
1185	/* AMD Family 0xf - 0x12 */
1186	VULNWL_AMD(0x0f,	NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_BHI),
1187	VULNWL_AMD(0x10,	NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_BHI),
1188	VULNWL_AMD(0x11,	NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_BHI),
1189	VULNWL_AMD(0x12,	NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_BHI),
1190
1191	/* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */
1192	VULNWL_AMD(X86_FAMILY_ANY,	NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB | NO_BHI),
1193	VULNWL_HYGON(X86_FAMILY_ANY,	NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB | NO_BHI),
1194
1195	/* Zhaoxin Family 7 */
1196	VULNWL(CENTAUR,	7, X86_MODEL_ANY,	NO_SPECTRE_V2 | NO_SWAPGS | NO_MMIO | NO_BHI),
1197	VULNWL(ZHAOXIN,	7, X86_MODEL_ANY,	NO_SPECTRE_V2 | NO_SWAPGS | NO_MMIO | NO_BHI),
1198	{}
1199};
1200
1201#define VULNBL(vendor, family, model, blacklist)	\
1202	X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, blacklist)
1203
1204#define VULNBL_INTEL_STEPPINGS(vfm, steppings, issues)		   \
1205	X86_MATCH_VFM_STEPPINGS(vfm, steppings, issues)
1206
1207#define VULNBL_AMD(family, blacklist)		\
1208	VULNBL(AMD, family, X86_MODEL_ANY, blacklist)
1209
1210#define VULNBL_HYGON(family, blacklist)		\
1211	VULNBL(HYGON, family, X86_MODEL_ANY, blacklist)
1212
1213#define SRBDS		BIT(0)
1214/* CPU is affected by X86_BUG_MMIO_STALE_DATA */
1215#define MMIO		BIT(1)
1216/* CPU is affected by Shared Buffers Data Sampling (SBDS), a variant of X86_BUG_MMIO_STALE_DATA */
1217#define MMIO_SBDS	BIT(2)
1218/* CPU is affected by RETbleed, speculating where you would not expect it */
1219#define RETBLEED	BIT(3)
1220/* CPU is affected by SMT (cross-thread) return predictions */
1221#define SMT_RSB		BIT(4)
1222/* CPU is affected by SRSO */
1223#define SRSO		BIT(5)
1224/* CPU is affected by GDS */
1225#define GDS		BIT(6)
1226/* CPU is affected by Register File Data Sampling */
1227#define RFDS		BIT(7)
1228
1229static const struct x86_cpu_id cpu_vuln_blacklist[] __initconst = {
1230	VULNBL_INTEL_STEPPINGS(INTEL_IVYBRIDGE,		X86_STEPPING_ANY,		SRBDS),
1231	VULNBL_INTEL_STEPPINGS(INTEL_HASWELL,		X86_STEPPING_ANY,		SRBDS),
1232	VULNBL_INTEL_STEPPINGS(INTEL_HASWELL_L,		X86_STEPPING_ANY,		SRBDS),
1233	VULNBL_INTEL_STEPPINGS(INTEL_HASWELL_G,		X86_STEPPING_ANY,		SRBDS),
1234	VULNBL_INTEL_STEPPINGS(INTEL_HASWELL_X,		X86_STEPPING_ANY,		MMIO),
1235	VULNBL_INTEL_STEPPINGS(INTEL_BROADWELL_D,	X86_STEPPING_ANY,		MMIO),
1236	VULNBL_INTEL_STEPPINGS(INTEL_BROADWELL_G,	X86_STEPPING_ANY,		SRBDS),
1237	VULNBL_INTEL_STEPPINGS(INTEL_BROADWELL_X,	X86_STEPPING_ANY,		MMIO),
1238	VULNBL_INTEL_STEPPINGS(INTEL_BROADWELL,		X86_STEPPING_ANY,		SRBDS),
1239	VULNBL_INTEL_STEPPINGS(INTEL_SKYLAKE_X,		X86_STEPPING_ANY,		MMIO | RETBLEED | GDS),
1240	VULNBL_INTEL_STEPPINGS(INTEL_SKYLAKE_L,		X86_STEPPING_ANY,		MMIO | RETBLEED | GDS | SRBDS),
1241	VULNBL_INTEL_STEPPINGS(INTEL_SKYLAKE,		X86_STEPPING_ANY,		MMIO | RETBLEED | GDS | SRBDS),
1242	VULNBL_INTEL_STEPPINGS(INTEL_KABYLAKE_L,	X86_STEPPING_ANY,		MMIO | RETBLEED | GDS | SRBDS),
1243	VULNBL_INTEL_STEPPINGS(INTEL_KABYLAKE,		X86_STEPPING_ANY,		MMIO | RETBLEED | GDS | SRBDS),
1244	VULNBL_INTEL_STEPPINGS(INTEL_CANNONLAKE_L,	X86_STEPPING_ANY,		RETBLEED),
1245	VULNBL_INTEL_STEPPINGS(INTEL_ICELAKE_L,		X86_STEPPING_ANY,		MMIO | MMIO_SBDS | RETBLEED | GDS),
1246	VULNBL_INTEL_STEPPINGS(INTEL_ICELAKE_D,		X86_STEPPING_ANY,		MMIO | GDS),
1247	VULNBL_INTEL_STEPPINGS(INTEL_ICELAKE_X,		X86_STEPPING_ANY,		MMIO | GDS),
1248	VULNBL_INTEL_STEPPINGS(INTEL_COMETLAKE,		X86_STEPPING_ANY,		MMIO | MMIO_SBDS | RETBLEED | GDS),
1249	VULNBL_INTEL_STEPPINGS(INTEL_COMETLAKE_L,	X86_STEPPINGS(0x0, 0x0),	MMIO | RETBLEED),
1250	VULNBL_INTEL_STEPPINGS(INTEL_COMETLAKE_L,	X86_STEPPING_ANY,		MMIO | MMIO_SBDS | RETBLEED | GDS),
1251	VULNBL_INTEL_STEPPINGS(INTEL_TIGERLAKE_L,	X86_STEPPING_ANY,		GDS),
1252	VULNBL_INTEL_STEPPINGS(INTEL_TIGERLAKE,		X86_STEPPING_ANY,		GDS),
1253	VULNBL_INTEL_STEPPINGS(INTEL_LAKEFIELD,		X86_STEPPING_ANY,		MMIO | MMIO_SBDS | RETBLEED),
1254	VULNBL_INTEL_STEPPINGS(INTEL_ROCKETLAKE,	X86_STEPPING_ANY,		MMIO | RETBLEED | GDS),
1255	VULNBL_INTEL_STEPPINGS(INTEL_ALDERLAKE,		X86_STEPPING_ANY,		RFDS),
1256	VULNBL_INTEL_STEPPINGS(INTEL_ALDERLAKE_L,	X86_STEPPING_ANY,		RFDS),
1257	VULNBL_INTEL_STEPPINGS(INTEL_RAPTORLAKE,	X86_STEPPING_ANY,		RFDS),
1258	VULNBL_INTEL_STEPPINGS(INTEL_RAPTORLAKE_P,	X86_STEPPING_ANY,		RFDS),
1259	VULNBL_INTEL_STEPPINGS(INTEL_RAPTORLAKE_S,	X86_STEPPING_ANY,		RFDS),
1260	VULNBL_INTEL_STEPPINGS(INTEL_ATOM_GRACEMONT,	X86_STEPPING_ANY,		RFDS),
1261	VULNBL_INTEL_STEPPINGS(INTEL_ATOM_TREMONT,	X86_STEPPING_ANY,		MMIO | MMIO_SBDS | RFDS),
1262	VULNBL_INTEL_STEPPINGS(INTEL_ATOM_TREMONT_D,	X86_STEPPING_ANY,		MMIO | RFDS),
1263	VULNBL_INTEL_STEPPINGS(INTEL_ATOM_TREMONT_L,	X86_STEPPING_ANY,		MMIO | MMIO_SBDS | RFDS),
1264	VULNBL_INTEL_STEPPINGS(INTEL_ATOM_GOLDMONT,	X86_STEPPING_ANY,		RFDS),
1265	VULNBL_INTEL_STEPPINGS(INTEL_ATOM_GOLDMONT_D,	X86_STEPPING_ANY,		RFDS),
1266	VULNBL_INTEL_STEPPINGS(INTEL_ATOM_GOLDMONT_PLUS, X86_STEPPING_ANY,		RFDS),
1267
1268	VULNBL_AMD(0x15, RETBLEED),
1269	VULNBL_AMD(0x16, RETBLEED),
1270	VULNBL_AMD(0x17, RETBLEED | SMT_RSB | SRSO),
1271	VULNBL_HYGON(0x18, RETBLEED | SMT_RSB | SRSO),
1272	VULNBL_AMD(0x19, SRSO),
1273	{}
1274};
1275
1276static bool __init cpu_matches(const struct x86_cpu_id *table, unsigned long which)
1277{
1278	const struct x86_cpu_id *m = x86_match_cpu(table);
1279
1280	return m && !!(m->driver_data & which);
1281}
1282
1283u64 x86_read_arch_cap_msr(void)
1284{
1285	u64 x86_arch_cap_msr = 0;
1286
1287	if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1288		rdmsrl(MSR_IA32_ARCH_CAPABILITIES, x86_arch_cap_msr);
1289
1290	return x86_arch_cap_msr;
1291}
1292
1293static bool arch_cap_mmio_immune(u64 x86_arch_cap_msr)
1294{
1295	return (x86_arch_cap_msr & ARCH_CAP_FBSDP_NO &&
1296		x86_arch_cap_msr & ARCH_CAP_PSDP_NO &&
1297		x86_arch_cap_msr & ARCH_CAP_SBDR_SSDP_NO);
1298}
1299
1300static bool __init vulnerable_to_rfds(u64 x86_arch_cap_msr)
1301{
1302	/* The "immunity" bit trumps everything else: */
1303	if (x86_arch_cap_msr & ARCH_CAP_RFDS_NO)
1304		return false;
1305
1306	/*
1307	 * VMMs set ARCH_CAP_RFDS_CLEAR for processors not in the blacklist to
1308	 * indicate that mitigation is needed because guest is running on a
1309	 * vulnerable hardware or may migrate to such hardware:
1310	 */
1311	if (x86_arch_cap_msr & ARCH_CAP_RFDS_CLEAR)
1312		return true;
1313
1314	/* Only consult the blacklist when there is no enumeration: */
1315	return cpu_matches(cpu_vuln_blacklist, RFDS);
1316}
1317
1318static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c)
1319{
1320	u64 x86_arch_cap_msr = x86_read_arch_cap_msr();
1321
1322	/* Set ITLB_MULTIHIT bug if cpu is not in the whitelist and not mitigated */
1323	if (!cpu_matches(cpu_vuln_whitelist, NO_ITLB_MULTIHIT) &&
1324	    !(x86_arch_cap_msr & ARCH_CAP_PSCHANGE_MC_NO))
1325		setup_force_cpu_bug(X86_BUG_ITLB_MULTIHIT);
1326
1327	if (cpu_matches(cpu_vuln_whitelist, NO_SPECULATION))
1328		return;
1329
1330	setup_force_cpu_bug(X86_BUG_SPECTRE_V1);
1331
1332	if (!cpu_matches(cpu_vuln_whitelist, NO_SPECTRE_V2))
1333		setup_force_cpu_bug(X86_BUG_SPECTRE_V2);
1334
1335	if (!cpu_matches(cpu_vuln_whitelist, NO_SSB) &&
1336	    !(x86_arch_cap_msr & ARCH_CAP_SSB_NO) &&
1337	   !cpu_has(c, X86_FEATURE_AMD_SSB_NO))
1338		setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS);
1339
1340	/*
1341	 * AMD's AutoIBRS is equivalent to Intel's eIBRS - use the Intel feature
1342	 * flag and protect from vendor-specific bugs via the whitelist.
1343	 *
1344	 * Don't use AutoIBRS when SNP is enabled because it degrades host
1345	 * userspace indirect branch performance.
1346	 */
1347	if ((x86_arch_cap_msr & ARCH_CAP_IBRS_ALL) ||
1348	    (cpu_has(c, X86_FEATURE_AUTOIBRS) &&
1349	     !cpu_feature_enabled(X86_FEATURE_SEV_SNP))) {
1350		setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED);
1351		if (!cpu_matches(cpu_vuln_whitelist, NO_EIBRS_PBRSB) &&
1352		    !(x86_arch_cap_msr & ARCH_CAP_PBRSB_NO))
1353			setup_force_cpu_bug(X86_BUG_EIBRS_PBRSB);
1354	}
1355
1356	if (!cpu_matches(cpu_vuln_whitelist, NO_MDS) &&
1357	    !(x86_arch_cap_msr & ARCH_CAP_MDS_NO)) {
1358		setup_force_cpu_bug(X86_BUG_MDS);
1359		if (cpu_matches(cpu_vuln_whitelist, MSBDS_ONLY))
1360			setup_force_cpu_bug(X86_BUG_MSBDS_ONLY);
1361	}
1362
1363	if (!cpu_matches(cpu_vuln_whitelist, NO_SWAPGS))
1364		setup_force_cpu_bug(X86_BUG_SWAPGS);
1365
1366	/*
1367	 * When the CPU is not mitigated for TAA (TAA_NO=0) set TAA bug when:
1368	 *	- TSX is supported or
1369	 *	- TSX_CTRL is present
1370	 *
1371	 * TSX_CTRL check is needed for cases when TSX could be disabled before
1372	 * the kernel boot e.g. kexec.
1373	 * TSX_CTRL check alone is not sufficient for cases when the microcode
1374	 * update is not present or running as guest that don't get TSX_CTRL.
1375	 */
1376	if (!(x86_arch_cap_msr & ARCH_CAP_TAA_NO) &&
1377	    (cpu_has(c, X86_FEATURE_RTM) ||
1378	     (x86_arch_cap_msr & ARCH_CAP_TSX_CTRL_MSR)))
1379		setup_force_cpu_bug(X86_BUG_TAA);
1380
1381	/*
1382	 * SRBDS affects CPUs which support RDRAND or RDSEED and are listed
1383	 * in the vulnerability blacklist.
1384	 *
1385	 * Some of the implications and mitigation of Shared Buffers Data
1386	 * Sampling (SBDS) are similar to SRBDS. Give SBDS same treatment as
1387	 * SRBDS.
1388	 */
1389	if ((cpu_has(c, X86_FEATURE_RDRAND) ||
1390	     cpu_has(c, X86_FEATURE_RDSEED)) &&
1391	    cpu_matches(cpu_vuln_blacklist, SRBDS | MMIO_SBDS))
1392		    setup_force_cpu_bug(X86_BUG_SRBDS);
1393
1394	/*
1395	 * Processor MMIO Stale Data bug enumeration
1396	 *
1397	 * Affected CPU list is generally enough to enumerate the vulnerability,
1398	 * but for virtualization case check for ARCH_CAP MSR bits also, VMM may
1399	 * not want the guest to enumerate the bug.
1400	 *
1401	 * Set X86_BUG_MMIO_UNKNOWN for CPUs that are neither in the blacklist,
1402	 * nor in the whitelist and also don't enumerate MSR ARCH_CAP MMIO bits.
1403	 */
1404	if (!arch_cap_mmio_immune(x86_arch_cap_msr)) {
1405		if (cpu_matches(cpu_vuln_blacklist, MMIO))
1406			setup_force_cpu_bug(X86_BUG_MMIO_STALE_DATA);
1407		else if (!cpu_matches(cpu_vuln_whitelist, NO_MMIO))
1408			setup_force_cpu_bug(X86_BUG_MMIO_UNKNOWN);
1409	}
1410
1411	if (!cpu_has(c, X86_FEATURE_BTC_NO)) {
1412		if (cpu_matches(cpu_vuln_blacklist, RETBLEED) || (x86_arch_cap_msr & ARCH_CAP_RSBA))
1413			setup_force_cpu_bug(X86_BUG_RETBLEED);
1414	}
1415
1416	if (cpu_matches(cpu_vuln_blacklist, SMT_RSB))
1417		setup_force_cpu_bug(X86_BUG_SMT_RSB);
1418
1419	if (!cpu_has(c, X86_FEATURE_SRSO_NO)) {
1420		if (cpu_matches(cpu_vuln_blacklist, SRSO))
1421			setup_force_cpu_bug(X86_BUG_SRSO);
1422	}
1423
1424	/*
1425	 * Check if CPU is vulnerable to GDS. If running in a virtual machine on
1426	 * an affected processor, the VMM may have disabled the use of GATHER by
1427	 * disabling AVX2. The only way to do this in HW is to clear XCR0[2],
1428	 * which means that AVX will be disabled.
1429	 */
1430	if (cpu_matches(cpu_vuln_blacklist, GDS) && !(x86_arch_cap_msr & ARCH_CAP_GDS_NO) &&
1431	    boot_cpu_has(X86_FEATURE_AVX))
1432		setup_force_cpu_bug(X86_BUG_GDS);
1433
1434	if (vulnerable_to_rfds(x86_arch_cap_msr))
1435		setup_force_cpu_bug(X86_BUG_RFDS);
1436
1437	/* When virtualized, eIBRS could be hidden, assume vulnerable */
1438	if (!(x86_arch_cap_msr & ARCH_CAP_BHI_NO) &&
1439	    !cpu_matches(cpu_vuln_whitelist, NO_BHI) &&
1440	    (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED) ||
1441	     boot_cpu_has(X86_FEATURE_HYPERVISOR)))
1442		setup_force_cpu_bug(X86_BUG_BHI);
1443
1444	if (cpu_has(c, X86_FEATURE_AMD_IBPB) && !cpu_has(c, X86_FEATURE_AMD_IBPB_RET))
1445		setup_force_cpu_bug(X86_BUG_IBPB_NO_RET);
1446
1447	if (cpu_matches(cpu_vuln_whitelist, NO_MELTDOWN))
1448		return;
1449
1450	/* Rogue Data Cache Load? No! */
1451	if (x86_arch_cap_msr & ARCH_CAP_RDCL_NO)
1452		return;
1453
1454	setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN);
1455
1456	if (cpu_matches(cpu_vuln_whitelist, NO_L1TF))
1457		return;
1458
1459	setup_force_cpu_bug(X86_BUG_L1TF);
1460}
1461
1462/*
1463 * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
1464 * unfortunately, that's not true in practice because of early VIA
1465 * chips and (more importantly) broken virtualizers that are not easy
1466 * to detect. In the latter case it doesn't even *fail* reliably, so
1467 * probing for it doesn't even work. Disable it completely on 32-bit
1468 * unless we can find a reliable way to detect all the broken cases.
1469 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
1470 */
1471static void detect_nopl(void)
1472{
1473#ifdef CONFIG_X86_32
1474	setup_clear_cpu_cap(X86_FEATURE_NOPL);
1475#else
1476	setup_force_cpu_cap(X86_FEATURE_NOPL);
1477#endif
1478}
1479
1480/*
1481 * We parse cpu parameters early because fpu__init_system() is executed
1482 * before parse_early_param().
1483 */
1484static void __init cpu_parse_early_param(void)
1485{
1486	char arg[128];
1487	char *argptr = arg, *opt;
1488	int arglen, taint = 0;
1489
1490#ifdef CONFIG_X86_32
1491	if (cmdline_find_option_bool(boot_command_line, "no387"))
1492#ifdef CONFIG_MATH_EMULATION
1493		setup_clear_cpu_cap(X86_FEATURE_FPU);
1494#else
1495		pr_err("Option 'no387' required CONFIG_MATH_EMULATION enabled.\n");
1496#endif
1497
1498	if (cmdline_find_option_bool(boot_command_line, "nofxsr"))
1499		setup_clear_cpu_cap(X86_FEATURE_FXSR);
1500#endif
1501
1502	if (cmdline_find_option_bool(boot_command_line, "noxsave"))
1503		setup_clear_cpu_cap(X86_FEATURE_XSAVE);
1504
1505	if (cmdline_find_option_bool(boot_command_line, "noxsaveopt"))
1506		setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT);
1507
1508	if (cmdline_find_option_bool(boot_command_line, "noxsaves"))
1509		setup_clear_cpu_cap(X86_FEATURE_XSAVES);
1510
1511	if (cmdline_find_option_bool(boot_command_line, "nousershstk"))
1512		setup_clear_cpu_cap(X86_FEATURE_USER_SHSTK);
1513
1514	/* Minimize the gap between FRED is available and available but disabled. */
1515	arglen = cmdline_find_option(boot_command_line, "fred", arg, sizeof(arg));
1516	if (arglen != 2 || strncmp(arg, "on", 2))
1517		setup_clear_cpu_cap(X86_FEATURE_FRED);
1518
1519	arglen = cmdline_find_option(boot_command_line, "clearcpuid", arg, sizeof(arg));
1520	if (arglen <= 0)
1521		return;
1522
1523	pr_info("Clearing CPUID bits:");
1524
1525	while (argptr) {
1526		bool found __maybe_unused = false;
1527		unsigned int bit;
1528
1529		opt = strsep(&argptr, ",");
1530
1531		/*
1532		 * Handle naked numbers first for feature flags which don't
1533		 * have names.
1534		 */
1535		if (!kstrtouint(opt, 10, &bit)) {
1536			if (bit < NCAPINTS * 32) {
1537
1538				/* empty-string, i.e., ""-defined feature flags */
1539				if (!x86_cap_flags[bit])
1540					pr_cont(" " X86_CAP_FMT_NUM, x86_cap_flag_num(bit));
1541				else
1542					pr_cont(" " X86_CAP_FMT, x86_cap_flag(bit));
1543
1544				setup_clear_cpu_cap(bit);
1545				taint++;
1546			}
1547			/*
1548			 * The assumption is that there are no feature names with only
1549			 * numbers in the name thus go to the next argument.
1550			 */
1551			continue;
1552		}
1553
1554		for (bit = 0; bit < 32 * NCAPINTS; bit++) {
1555			if (!x86_cap_flag(bit))
1556				continue;
1557
1558			if (strcmp(x86_cap_flag(bit), opt))
1559				continue;
1560
1561			pr_cont(" %s", opt);
1562			setup_clear_cpu_cap(bit);
1563			taint++;
1564			found = true;
1565			break;
1566		}
1567
1568		if (!found)
1569			pr_cont(" (unknown: %s)", opt);
1570	}
1571	pr_cont("\n");
1572
1573	if (taint)
1574		add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
1575}
1576
1577/*
1578 * Do minimum CPU detection early.
1579 * Fields really needed: vendor, cpuid_level, family, model, mask,
1580 * cache alignment.
1581 * The others are not touched to avoid unwanted side effects.
1582 *
1583 * WARNING: this function is only called on the boot CPU.  Don't add code
1584 * here that is supposed to run on all CPUs.
1585 */
1586static void __init early_identify_cpu(struct cpuinfo_x86 *c)
1587{
1588	memset(&c->x86_capability, 0, sizeof(c->x86_capability));
 
 
 
 
 
 
 
 
 
 
 
1589	c->extended_cpuid_level = 0;
1590
1591	if (!have_cpuid_p())
1592		identify_cpu_without_cpuid(c);
1593
1594	/* cyrix could have cpuid enabled via c_identify()*/
1595	if (have_cpuid_p()) {
1596		cpu_detect(c);
1597		get_cpu_vendor(c);
1598		intel_unlock_cpuid_leafs(c);
1599		get_cpu_cap(c);
1600		setup_force_cpu_cap(X86_FEATURE_CPUID);
1601		get_cpu_address_sizes(c);
1602		cpu_parse_early_param();
1603
1604		cpu_init_topology(c);
1605
1606		if (this_cpu->c_early_init)
1607			this_cpu->c_early_init(c);
1608
1609		c->cpu_index = 0;
1610		filter_cpuid_features(c, false);
1611
1612		if (this_cpu->c_bsp_init)
1613			this_cpu->c_bsp_init(c);
1614	} else {
1615		setup_clear_cpu_cap(X86_FEATURE_CPUID);
1616		get_cpu_address_sizes(c);
1617		cpu_init_topology(c);
1618	}
1619
1620	setup_force_cpu_cap(X86_FEATURE_ALWAYS);
1621
1622	cpu_set_bug_bits(c);
1623
1624	sld_setup(c);
 
1625
1626#ifdef CONFIG_X86_32
1627	/*
1628	 * Regardless of whether PCID is enumerated, the SDM says
1629	 * that it can't be enabled in 32-bit mode.
1630	 */
1631	setup_clear_cpu_cap(X86_FEATURE_PCID);
1632#endif
1633
1634	/*
1635	 * Later in the boot process pgtable_l5_enabled() relies on
1636	 * cpu_feature_enabled(X86_FEATURE_LA57). If 5-level paging is not
1637	 * enabled by this point we need to clear the feature bit to avoid
1638	 * false-positives at the later stage.
1639	 *
1640	 * pgtable_l5_enabled() can be false here for several reasons:
1641	 *  - 5-level paging is disabled compile-time;
1642	 *  - it's 32-bit kernel;
1643	 *  - machine doesn't support 5-level paging;
1644	 *  - user specified 'no5lvl' in kernel command line.
1645	 */
1646	if (!pgtable_l5_enabled())
1647		setup_clear_cpu_cap(X86_FEATURE_LA57);
1648
1649	detect_nopl();
 
1650}
1651
1652void __init init_cpu_devs(void)
1653{
1654	const struct cpu_dev *const *cdev;
1655	int count = 0;
1656
 
 
 
 
1657	for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
1658		const struct cpu_dev *cpudev = *cdev;
1659
1660		if (count >= X86_VENDOR_NUM)
1661			break;
1662		cpu_devs[count] = cpudev;
1663		count++;
1664	}
1665}
1666
1667void __init early_cpu_init(void)
1668{
1669#ifdef CONFIG_PROCESSOR_SELECT
1670	unsigned int i, j;
 
1671
1672	pr_info("KERNEL supported cpus:\n");
1673#endif
1674
1675	init_cpu_devs();
1676
1677#ifdef CONFIG_PROCESSOR_SELECT
1678	for (i = 0; i < X86_VENDOR_NUM && cpu_devs[i]; i++) {
1679		for (j = 0; j < 2; j++) {
1680			if (!cpu_devs[i]->c_ident[j])
1681				continue;
1682			pr_info("  %s %s\n", cpu_devs[i]->c_vendor,
1683				cpu_devs[i]->c_ident[j]);
1684		}
1685	}
1686#endif
1687
1688	early_identify_cpu(&boot_cpu_data);
1689}
1690
1691static bool detect_null_seg_behavior(void)
1692{
1693	/*
1694	 * Empirically, writing zero to a segment selector on AMD does
1695	 * not clear the base, whereas writing zero to a segment
1696	 * selector on Intel does clear the base.  Intel's behavior
1697	 * allows slightly faster context switches in the common case
1698	 * where GS is unused by the prev and next threads.
1699	 *
1700	 * Since neither vendor documents this anywhere that I can see,
1701	 * detect it directly instead of hard-coding the choice by
1702	 * vendor.
1703	 *
1704	 * I've designated AMD's behavior as the "bug" because it's
1705	 * counterintuitive and less friendly.
1706	 */
1707
1708	unsigned long old_base, tmp;
1709	rdmsrl(MSR_FS_BASE, old_base);
1710	wrmsrl(MSR_FS_BASE, 1);
1711	loadsegment(fs, 0);
1712	rdmsrl(MSR_FS_BASE, tmp);
1713	wrmsrl(MSR_FS_BASE, old_base);
1714	return tmp == 0;
1715}
1716
1717void check_null_seg_clears_base(struct cpuinfo_x86 *c)
1718{
1719	/* BUG_NULL_SEG is only relevant with 64bit userspace */
1720	if (!IS_ENABLED(CONFIG_X86_64))
1721		return;
1722
1723	if (cpu_has(c, X86_FEATURE_NULL_SEL_CLR_BASE))
1724		return;
1725
1726	/*
1727	 * CPUID bit above wasn't set. If this kernel is still running
1728	 * as a HV guest, then the HV has decided not to advertize
1729	 * that CPUID bit for whatever reason.	For example, one
1730	 * member of the migration pool might be vulnerable.  Which
1731	 * means, the bug is present: set the BUG flag and return.
1732	 */
1733	if (cpu_has(c, X86_FEATURE_HYPERVISOR)) {
1734		set_cpu_bug(c, X86_BUG_NULL_SEG);
1735		return;
1736	}
1737
1738	/*
1739	 * Zen2 CPUs also have this behaviour, but no CPUID bit.
1740	 * 0x18 is the respective family for Hygon.
1741	 */
1742	if ((c->x86 == 0x17 || c->x86 == 0x18) &&
1743	    detect_null_seg_behavior())
1744		return;
1745
1746	/* All the remaining ones are affected */
1747	set_cpu_bug(c, X86_BUG_NULL_SEG);
1748}
1749
1750static void generic_identify(struct cpuinfo_x86 *c)
1751{
1752	c->extended_cpuid_level = 0;
1753
1754	if (!have_cpuid_p())
1755		identify_cpu_without_cpuid(c);
1756
1757	/* cyrix could have cpuid enabled via c_identify()*/
1758	if (!have_cpuid_p())
1759		return;
1760
1761	cpu_detect(c);
1762
1763	get_cpu_vendor(c);
1764	intel_unlock_cpuid_leafs(c);
1765	get_cpu_cap(c);
1766
1767	get_cpu_address_sizes(c);
 
 
 
 
 
 
 
 
 
 
 
 
1768
1769	get_model_name(c); /* Default name */
1770
1771	/*
1772	 * ESPFIX is a strange bug.  All real CPUs have it.  Paravirt
1773	 * systems that run Linux at CPL > 0 may or may not have the
1774	 * issue, but, even if they have the issue, there's absolutely
1775	 * nothing we can do about it because we can't use the real IRET
1776	 * instruction.
1777	 *
1778	 * NB: For the time being, only 32-bit kernels support
1779	 * X86_BUG_ESPFIX as such.  64-bit kernels directly choose
1780	 * whether to apply espfix using paravirt hooks.  If any
1781	 * non-paravirt system ever shows up that does *not* have the
1782	 * ESPFIX issue, we can change this.
1783	 */
1784#ifdef CONFIG_X86_32
1785	set_cpu_bug(c, X86_BUG_ESPFIX);
1786#endif
1787}
1788
1789/*
1790 * This does the hard work of actually picking apart the CPU stuff...
1791 */
1792static void identify_cpu(struct cpuinfo_x86 *c)
1793{
1794	int i;
1795
1796	c->loops_per_jiffy = loops_per_jiffy;
1797	c->x86_cache_size = 0;
1798	c->x86_vendor = X86_VENDOR_UNKNOWN;
1799	c->x86_model = c->x86_stepping = 0;	/* So far unknown... */
1800	c->x86_vendor_id[0] = '\0'; /* Unset */
1801	c->x86_model_id[0] = '\0';  /* Unset */
 
 
1802#ifdef CONFIG_X86_64
1803	c->x86_clflush_size = 64;
1804	c->x86_phys_bits = 36;
1805	c->x86_virt_bits = 48;
1806#else
1807	c->cpuid_level = -1;	/* CPUID not detected */
1808	c->x86_clflush_size = 32;
1809	c->x86_phys_bits = 32;
1810	c->x86_virt_bits = 32;
1811#endif
1812	c->x86_cache_alignment = c->x86_clflush_size;
1813	memset(&c->x86_capability, 0, sizeof(c->x86_capability));
1814#ifdef CONFIG_X86_VMX_FEATURE_NAMES
1815	memset(&c->vmx_capability, 0, sizeof(c->vmx_capability));
1816#endif
1817
1818	generic_identify(c);
1819
1820	cpu_parse_topology(c);
1821
1822	if (this_cpu->c_identify)
1823		this_cpu->c_identify(c);
1824
1825	/* Clear/Set all flags overridden by options, after probe */
1826	apply_forced_caps(c);
 
 
 
1827
1828	/*
1829	 * Set default APIC and TSC_DEADLINE MSR fencing flag. AMD and
1830	 * Hygon will clear it in ->c_init() below.
1831	 */
1832	set_cpu_cap(c, X86_FEATURE_APIC_MSRS_FENCE);
1833
1834	/*
1835	 * Vendor-specific initialization.  In this section we
1836	 * canonicalize the feature flags, meaning if there are
1837	 * features a certain CPU supports which CPUID doesn't
1838	 * tell us, CPUID claiming incorrect flags, or other bugs,
1839	 * we handle them here.
1840	 *
1841	 * At the end of this section, c->x86_capability better
1842	 * indicate the features this CPU genuinely supports!
1843	 */
1844	if (this_cpu->c_init)
1845		this_cpu->c_init(c);
1846
1847	bus_lock_init();
1848
1849	/* Disable the PN if appropriate */
1850	squash_the_stupid_serial_number(c);
1851
1852	/* Set up SMEP/SMAP/UMIP */
1853	setup_smep(c);
1854	setup_smap(c);
1855	setup_umip(c);
1856
1857	/* Enable FSGSBASE instructions if available. */
1858	if (cpu_has(c, X86_FEATURE_FSGSBASE)) {
1859		cr4_set_bits(X86_CR4_FSGSBASE);
1860		elf_hwcap2 |= HWCAP2_FSGSBASE;
1861	}
1862
1863	/*
1864	 * The vendor-specific functions might have changed features.
1865	 * Now we do "generic changes."
1866	 */
1867
1868	/* Filter out anything that depends on CPUID levels we don't have */
1869	filter_cpuid_features(c, true);
1870
1871	/* If the model name is still unset, do table lookup. */
1872	if (!c->x86_model_id[0]) {
1873		const char *p;
1874		p = table_lookup_model(c);
1875		if (p)
1876			strcpy(c->x86_model_id, p);
1877		else
1878			/* Last resort... */
1879			sprintf(c->x86_model_id, "%02x/%02x",
1880				c->x86, c->x86_model);
1881	}
1882
 
 
 
 
 
1883	x86_init_rdrand(c);
1884	setup_pku(c);
1885	setup_cet(c);
1886
1887	/*
1888	 * Clear/Set all flags overridden by options, need do it
1889	 * before following smp all cpus cap AND.
1890	 */
1891	apply_forced_caps(c);
 
 
 
1892
1893	/*
1894	 * On SMP, boot_cpu_data holds the common feature set between
1895	 * all CPUs; so make sure that we indicate which features are
1896	 * common between the CPUs.  The first time this routine gets
1897	 * executed, c == &boot_cpu_data.
1898	 */
1899	if (c != &boot_cpu_data) {
1900		/* AND the already accumulated flags with these */
1901		for (i = 0; i < NCAPINTS; i++)
1902			boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1903
1904		/* OR, i.e. replicate the bug flags */
1905		for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++)
1906			c->x86_capability[i] |= boot_cpu_data.x86_capability[i];
1907	}
1908
1909	ppin_init(c);
1910
1911	/* Init Machine Check Exception if available. */
1912	mcheck_cpu_init(c);
1913
 
 
 
1914	numa_add_cpu(smp_processor_id());
 
1915}
1916
1917/*
1918 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions
1919 * on 32-bit kernels:
1920 */
1921#ifdef CONFIG_X86_32
1922void enable_sep_cpu(void)
1923{
1924	struct tss_struct *tss;
1925	int cpu;
1926
1927	if (!boot_cpu_has(X86_FEATURE_SEP))
1928		return;
1929
1930	cpu = get_cpu();
1931	tss = &per_cpu(cpu_tss_rw, cpu);
1932
1933	/*
1934	 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field --
1935	 * see the big comment in struct x86_hw_tss's definition.
1936	 */
1937
1938	tss->x86_tss.ss1 = __KERNEL_CS;
1939	wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0);
1940	wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1), 0);
1941	wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0);
1942
1943	put_cpu();
1944}
1945#endif
1946
1947static __init void identify_boot_cpu(void)
1948{
1949	identify_cpu(&boot_cpu_data);
1950	if (HAS_KERNEL_IBT && cpu_feature_enabled(X86_FEATURE_IBT))
1951		pr_info("CET detected: Indirect Branch Tracking enabled\n");
1952#ifdef CONFIG_X86_32
 
1953	enable_sep_cpu();
 
 
1954#endif
1955	cpu_detect_tlb(&boot_cpu_data);
1956	setup_cr_pinning();
1957
1958	tsx_init();
1959	tdx_init();
1960	lkgs_init();
1961}
1962
1963void identify_secondary_cpu(struct cpuinfo_x86 *c)
1964{
1965	BUG_ON(c == &boot_cpu_data);
1966	identify_cpu(c);
1967#ifdef CONFIG_X86_32
1968	enable_sep_cpu();
1969#endif
1970	x86_spec_ctrl_setup_ap();
1971	update_srbds_msr();
1972	if (boot_cpu_has_bug(X86_BUG_GDS))
1973		update_gds_msr();
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1974
1975	tsx_ap_init();
 
 
 
 
 
1976}
1977
1978void print_cpu_info(struct cpuinfo_x86 *c)
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1979{
1980	const char *vendor = NULL;
1981
1982	if (c->x86_vendor < X86_VENDOR_NUM) {
1983		vendor = this_cpu->c_vendor;
1984	} else {
1985		if (c->cpuid_level >= 0)
1986			vendor = c->x86_vendor_id;
1987	}
1988
1989	if (vendor && !strstr(c->x86_model_id, vendor))
1990		pr_cont("%s ", vendor);
1991
1992	if (c->x86_model_id[0])
1993		pr_cont("%s", c->x86_model_id);
1994	else
1995		pr_cont("%d86", c->x86);
1996
1997	pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model);
1998
1999	if (c->x86_stepping || c->cpuid_level >= 0)
2000		pr_cont(", stepping: 0x%x)\n", c->x86_stepping);
2001	else
2002		pr_cont(")\n");
 
 
2003}
2004
2005/*
2006 * clearcpuid= was already parsed in cpu_parse_early_param().  This dummy
2007 * function prevents it from becoming an environment variable for init.
2008 */
2009static __init int setup_clearcpuid(char *arg)
2010{
 
 
 
 
 
 
 
 
 
 
 
 
 
2011	return 1;
2012}
2013__setup("clearcpuid=", setup_clearcpuid);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
2014
2015DEFINE_PER_CPU_ALIGNED(struct pcpu_hot, pcpu_hot) = {
2016	.current_task	= &init_task,
2017	.preempt_count	= INIT_PREEMPT_COUNT,
2018	.top_of_stack	= TOP_OF_INIT_STACK,
 
 
 
 
 
 
 
2019};
2020EXPORT_PER_CPU_SYMBOL(pcpu_hot);
2021EXPORT_PER_CPU_SYMBOL(const_pcpu_hot);
2022
2023#ifdef CONFIG_X86_64
2024DEFINE_PER_CPU_FIRST(struct fixed_percpu_data,
2025		     fixed_percpu_data) __aligned(PAGE_SIZE) __visible;
2026EXPORT_PER_CPU_SYMBOL_GPL(fixed_percpu_data);
2027
2028static void wrmsrl_cstar(unsigned long val)
 
2029{
2030	/*
2031	 * Intel CPUs do not support 32-bit SYSCALL. Writing to MSR_CSTAR
2032	 * is so far ignored by the CPU, but raises a #VE trap in a TDX
2033	 * guest. Avoid the pointless write on all Intel CPUs.
2034	 */
2035	if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
2036		wrmsrl(MSR_CSTAR, val);
 
 
 
 
 
 
 
 
 
2037}
2038
2039static inline void idt_syscall_init(void)
2040{
2041	wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64);
2042
2043	if (ia32_enabled()) {
2044		wrmsrl_cstar((unsigned long)entry_SYSCALL_compat);
2045		/*
2046		 * This only works on Intel CPUs.
2047		 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP.
2048		 * This does not cause SYSENTER to jump to the wrong location, because
2049		 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit).
2050		 */
2051		wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS);
2052		wrmsrl_safe(MSR_IA32_SYSENTER_ESP,
2053			    (unsigned long)(cpu_entry_stack(smp_processor_id()) + 1));
2054		wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat);
2055	} else {
2056		wrmsrl_cstar((unsigned long)entry_SYSCALL32_ignore);
2057		wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG);
2058		wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL);
2059		wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL);
2060	}
2061
2062	/*
2063	 * Flags to clear on syscall; clear as much as possible
2064	 * to minimize user space-kernel interference.
2065	 */
2066	wrmsrl(MSR_SYSCALL_MASK,
2067	       X86_EFLAGS_CF|X86_EFLAGS_PF|X86_EFLAGS_AF|
2068	       X86_EFLAGS_ZF|X86_EFLAGS_SF|X86_EFLAGS_TF|
2069	       X86_EFLAGS_IF|X86_EFLAGS_DF|X86_EFLAGS_OF|
2070	       X86_EFLAGS_IOPL|X86_EFLAGS_NT|X86_EFLAGS_RF|
2071	       X86_EFLAGS_AC|X86_EFLAGS_ID);
2072}
2073
2074/* May not be marked __init: used by software suspend */
2075void syscall_init(void)
 
2076{
2077	/* The default user and kernel segments */
2078	wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS);
 
2079
2080	/*
2081	 * Except the IA32_STAR MSR, there is NO need to setup SYSCALL and
2082	 * SYSENTER MSRs for FRED, because FRED uses the ring 3 FRED
2083	 * entrypoint for SYSCALL and SYSENTER, and ERETU is the only legit
2084	 * instruction to return to ring 3 (both sysexit and sysret cause
2085	 * #UD when FRED is enabled).
2086	 */
2087	if (!cpu_feature_enabled(X86_FEATURE_FRED))
2088		idt_syscall_init();
2089}
2090
2091#else	/* CONFIG_X86_64 */
2092
2093#ifdef CONFIG_STACKPROTECTOR
2094DEFINE_PER_CPU(unsigned long, __stack_chk_guard);
2095#ifndef CONFIG_SMP
2096EXPORT_PER_CPU_SYMBOL(__stack_chk_guard);
2097#endif
 
2098#endif
2099
 
 
 
 
 
 
 
 
 
2100#endif	/* CONFIG_X86_64 */
2101
2102/*
2103 * Clear all 6 debug registers:
2104 */
2105static void clear_all_debug_regs(void)
2106{
2107	int i;
2108
2109	for (i = 0; i < 8; i++) {
2110		/* Ignore db4, db5 */
2111		if ((i == 4) || (i == 5))
2112			continue;
2113
2114		set_debugreg(0, i);
2115	}
2116}
2117
2118#ifdef CONFIG_KGDB
2119/*
2120 * Restore debug regs if using kgdbwait and you have a kernel debugger
2121 * connection established.
2122 */
2123static void dbg_restore_debug_regs(void)
2124{
2125	if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break))
2126		arch_kgdb_ops.correct_hw_break();
2127}
2128#else /* ! CONFIG_KGDB */
2129#define dbg_restore_debug_regs()
2130#endif /* ! CONFIG_KGDB */
2131
2132static inline void setup_getcpu(int cpu)
2133{
2134	unsigned long cpudata = vdso_encode_cpunode(cpu, early_cpu_to_node(cpu));
2135	struct desc_struct d = { };
2136
2137	if (boot_cpu_has(X86_FEATURE_RDTSCP) || boot_cpu_has(X86_FEATURE_RDPID))
2138		wrmsr(MSR_TSC_AUX, cpudata, 0);
2139
2140	/* Store CPU and node number in limit. */
2141	d.limit0 = cpudata;
2142	d.limit1 = cpudata >> 16;
2143
2144	d.type = 5;		/* RO data, expand down, accessed */
2145	d.dpl = 3;		/* Visible to user code */
2146	d.s = 1;		/* Not a system segment */
2147	d.p = 1;		/* Present */
2148	d.d = 1;		/* 32-bit */
2149
2150	write_gdt_entry(get_cpu_gdt_rw(cpu), GDT_ENTRY_CPUNODE, &d, DESCTYPE_S);
2151}
2152
2153#ifdef CONFIG_X86_64
2154static inline void tss_setup_ist(struct tss_struct *tss)
2155{
2156	/* Set up the per-CPU TSS IST stacks */
2157	tss->x86_tss.ist[IST_INDEX_DF] = __this_cpu_ist_top_va(DF);
2158	tss->x86_tss.ist[IST_INDEX_NMI] = __this_cpu_ist_top_va(NMI);
2159	tss->x86_tss.ist[IST_INDEX_DB] = __this_cpu_ist_top_va(DB);
2160	tss->x86_tss.ist[IST_INDEX_MCE] = __this_cpu_ist_top_va(MCE);
2161	/* Only mapped when SEV-ES is active */
2162	tss->x86_tss.ist[IST_INDEX_VC] = __this_cpu_ist_top_va(VC);
2163}
2164#else /* CONFIG_X86_64 */
2165static inline void tss_setup_ist(struct tss_struct *tss) { }
2166#endif /* !CONFIG_X86_64 */
2167
2168static inline void tss_setup_io_bitmap(struct tss_struct *tss)
2169{
2170	tss->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET_INVALID;
2171
2172#ifdef CONFIG_X86_IOPL_IOPERM
2173	tss->io_bitmap.prev_max = 0;
2174	tss->io_bitmap.prev_sequence = 0;
2175	memset(tss->io_bitmap.bitmap, 0xff, sizeof(tss->io_bitmap.bitmap));
2176	/*
2177	 * Invalidate the extra array entry past the end of the all
2178	 * permission bitmap as required by the hardware.
2179	 */
2180	tss->io_bitmap.mapall[IO_BITMAP_LONGS] = ~0UL;
2181#endif
2182}
2183
2184/*
2185 * Setup everything needed to handle exceptions from the IDT, including the IST
2186 * exceptions which use paranoid_entry().
 
 
 
2187 */
2188void cpu_init_exception_handling(bool boot_cpu)
2189{
2190	struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw);
2191	int cpu = raw_smp_processor_id();
2192
2193	/* paranoid_entry() gets the CPU number from the GDT */
2194	setup_getcpu(cpu);
2195
2196	/* For IDT mode, IST vectors need to be set in TSS. */
2197	if (!cpu_feature_enabled(X86_FEATURE_FRED))
2198		tss_setup_ist(tss);
2199	tss_setup_io_bitmap(tss);
2200	set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss);
2201
2202	load_TR_desc();
2203
2204	/* GHCB needs to be setup to handle #VC. */
2205	setup_ghcb();
2206
2207	if (cpu_feature_enabled(X86_FEATURE_FRED)) {
2208		/* The boot CPU has enabled FRED during early boot */
2209		if (!boot_cpu)
2210			cpu_init_fred_exceptions();
2211
2212		cpu_init_fred_rsps();
2213	} else {
2214		load_current_idt();
2215	}
2216}
2217
2218void __init cpu_init_replace_early_idt(void)
2219{
2220	if (cpu_feature_enabled(X86_FEATURE_FRED))
2221		cpu_init_fred_exceptions();
2222	else
2223		idt_setup_early_pf();
2224}
 
2225
2226/*
2227 * cpu_init() initializes state that is per-CPU. Some data is already
2228 * initialized (naturally) in the bootstrap process, such as the GDT.  We
2229 * reload it nevertheless, this function acts as a 'CPU state barrier',
2230 * nothing should get across.
2231 */
2232void cpu_init(void)
2233{
2234	struct task_struct *cur = current;
2235	int cpu = raw_smp_processor_id();
2236
2237#ifdef CONFIG_NUMA
2238	if (this_cpu_read(numa_node) == 0 &&
2239	    early_cpu_to_node(cpu) != NUMA_NO_NODE)
2240		set_numa_node(early_cpu_to_node(cpu));
2241#endif
2242	pr_debug("Initializing CPU#%d\n", cpu);
2243
2244	if (IS_ENABLED(CONFIG_X86_64) || cpu_feature_enabled(X86_FEATURE_VME) ||
2245	    boot_cpu_has(X86_FEATURE_TSC) || boot_cpu_has(X86_FEATURE_DE))
2246		cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
2247
2248	if (IS_ENABLED(CONFIG_X86_64)) {
2249		loadsegment(fs, 0);
2250		memset(cur->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
2251		syscall_init();
2252
2253		wrmsrl(MSR_FS_BASE, 0);
2254		wrmsrl(MSR_KERNEL_GS_BASE, 0);
2255		barrier();
2256
2257		x2apic_setup();
 
2258
2259		intel_posted_msi_init();
2260	}
2261
2262	mmgrab(&init_mm);
2263	cur->active_mm = &init_mm;
2264	BUG_ON(cur->mm);
2265	initialize_tlbstate_and_flush();
2266	enter_lazy_tlb(&init_mm, cur);
2267
2268	/*
2269	 * sp0 points to the entry trampoline stack regardless of what task
2270	 * is running.
2271	 */
2272	load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1));
2273
2274	load_mm_ldt(&init_mm);
 
2275
2276	clear_all_debug_regs();
2277	dbg_restore_debug_regs();
2278
2279	doublefault_init_cpu_tss();
 
2280
2281	if (is_uv_system())
2282		uv_cpu_init();
 
2283
2284	load_fixmap_gdt(cpu);
2285}
 
2286
2287#ifdef CONFIG_MICROCODE_LATE_LOADING
2288/**
2289 * store_cpu_caps() - Store a snapshot of CPU capabilities
2290 * @curr_info: Pointer where to store it
2291 *
2292 * Returns: None
2293 */
2294void store_cpu_caps(struct cpuinfo_x86 *curr_info)
2295{
2296	/* Reload CPUID max function as it might've changed. */
2297	curr_info->cpuid_level = cpuid_eax(0);
2298
2299	/* Copy all capability leafs and pick up the synthetic ones. */
2300	memcpy(&curr_info->x86_capability, &boot_cpu_data.x86_capability,
2301	       sizeof(curr_info->x86_capability));
 
 
 
 
 
2302
2303	/* Get the hardware CPUID leafs */
2304	get_cpu_cap(curr_info);
2305}
2306
2307/**
2308 * microcode_check() - Check if any CPU capabilities changed after an update.
2309 * @prev_info:	CPU capabilities stored before an update.
2310 *
2311 * The microcode loader calls this upon late microcode load to recheck features,
2312 * only when microcode has been updated. Caller holds and CPU hotplug lock.
2313 *
2314 * Return: None
2315 */
2316void microcode_check(struct cpuinfo_x86 *prev_info)
2317{
2318	struct cpuinfo_x86 curr_info;
2319
2320	perf_check_microcode();
 
 
 
2321
2322	amd_check_microcode();
 
 
 
2323
2324	store_cpu_caps(&curr_info);
 
2325
2326	if (!memcmp(&prev_info->x86_capability, &curr_info.x86_capability,
2327		    sizeof(prev_info->x86_capability)))
2328		return;
2329
2330	pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n");
2331	pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n");
2332}
2333#endif
2334
2335/*
2336 * Invoked from core CPU hotplug code after hotplug operations
2337 */
2338void arch_smt_update(void)
2339{
2340	/* Handle the speculative execution misfeatures */
2341	cpu_bugs_smt_update();
2342	/* Check whether IPI broadcasting can be enabled */
2343	apic_smt_update();
2344}
2345
2346void __init arch_cpu_finalize_init(void)
2347{
2348	struct cpuinfo_x86 *c = this_cpu_ptr(&cpu_info);
2349
2350	identify_boot_cpu();
2351
2352	select_idle_routine();
2353
2354	/*
2355	 * identify_boot_cpu() initialized SMT support information, let the
2356	 * core code know.
2357	 */
2358	cpu_smt_set_num_threads(__max_threads_per_core, __max_threads_per_core);
 
2359
2360	if (!IS_ENABLED(CONFIG_SMP)) {
2361		pr_info("CPU: ");
2362		print_cpu_info(&boot_cpu_data);
 
2363	}
2364
2365	cpu_select_mitigations();
2366
2367	arch_smt_update();
2368
2369	if (IS_ENABLED(CONFIG_X86_32)) {
2370		/*
2371		 * Check whether this is a real i386 which is not longer
2372		 * supported and fixup the utsname.
2373		 */
2374		if (boot_cpu_data.x86 < 4)
2375			panic("Kernel requires i486+ for 'invlpg' and other features");
2376
2377		init_utsname()->machine[1] =
2378			'0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86);
2379	}
2380
2381	/*
2382	 * Must be before alternatives because it might set or clear
2383	 * feature bits.
2384	 */
2385	fpu__init_system();
2386	fpu__init_cpu();
 
 
2387
2388	/*
2389	 * Ensure that access to the per CPU representation has the initial
2390	 * boot CPU configuration.
2391	 */
2392	*c = boot_cpu_data;
2393	c->initialized = true;
2394
2395	alternative_instructions();
2396
2397	if (IS_ENABLED(CONFIG_X86_64)) {
2398		unsigned long USER_PTR_MAX = TASK_SIZE_MAX;
2399
2400		/*
2401		 * Enable this when LAM is gated on LASS support
2402		if (cpu_feature_enabled(X86_FEATURE_LAM))
2403			USER_PTR_MAX = (1ul << 63) - PAGE_SIZE;
2404		 */
2405		runtime_const_init(ptr, USER_PTR_MAX);
2406
2407		/*
2408		 * Make sure the first 2MB area is not mapped by huge pages
2409		 * There are typically fixed size MTRRs in there and overlapping
2410		 * MTRRs into large pages causes slow downs.
2411		 *
2412		 * Right now we don't do that with gbpages because there seems
2413		 * very little benefit for that case.
2414		 */
2415		if (!direct_gbpages)
2416			set_memory_4k((unsigned long)__va(0), 1);
2417	} else {
2418		fpu__init_check_bugs();
2419	}
2420
2421	/*
2422	 * This needs to be called before any devices perform DMA
2423	 * operations that might use the SWIOTLB bounce buffers. It will
2424	 * mark the bounce buffers as decrypted so that their usage will
2425	 * not cause "plain-text" data to be decrypted when accessed. It
2426	 * must be called after late_time_init() so that Hyper-V x86/x64
2427	 * hypercalls work when the SWIOTLB bounce buffers are decrypted.
2428	 */
2429	mem_encrypt_init();
2430}