1/*
  2 * P3060 Silicon/SoC Device Tree Source (pre include)
  3 *
  4 * Copyright 2011 Freescale Semiconductor Inc.
  5 *
  6 * Redistribution and use in source and binary forms, with or without
  7 * modification, are permitted provided that the following conditions are met:
  8 *     * Redistributions of source code must retain the above copyright
  9 *       notice, this list of conditions and the following disclaimer.
 10 *     * Redistributions in binary form must reproduce the above copyright
 11 *       notice, this list of conditions and the following disclaimer in the
 12 *       documentation and/or other materials provided with the distribution.
 13 *     * Neither the name of Freescale Semiconductor nor the
 14 *       names of its contributors may be used to endorse or promote products
 15 *       derived from this software without specific prior written permission.
 16 *
 17 *
 18 * ALTERNATIVELY, this software may be distributed under the terms of the
 19 * GNU General Public License ("GPL") as published by the Free Software
 20 * Foundation, either version 2 of that License or (at your option) any
 21 * later version.
 22 *
 23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
 24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
 27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 33 */
 34
 35/dts-v1/;
 36/ {
 37	compatible = "fsl,P3060";
 38	#address-cells = <2>;
 39	#size-cells = <2>;
 40	interrupt-parent = <&mpic>;
 41
 42	aliases {
 43		ccsr = &soc;
 44		dcsr = &dcsr;
 45
 46		serial0 = &serial0;
 47		serial1 = &serial1;
 48		serial2 = &serial2;
 49		serial3 = &serial3;
 50		pci0 = &pci0;
 51		pci1 = &pci1;
 52		usb0 = &usb0;
 53		usb1 = &usb1;
 54		dma0 = &dma0;
 55		dma1 = &dma1;
 56		msi0 = &msi0;
 57		msi1 = &msi1;
 58		msi2 = &msi2;
 59
 60		crypto = &crypto;
 61		sec_jr0 = &sec_jr0;
 62		sec_jr1 = &sec_jr1;
 63		sec_jr2 = &sec_jr2;
 64		sec_jr3 = &sec_jr3;
 65		rtic_a = &rtic_a;
 66		rtic_b = &rtic_b;
 67		rtic_c = &rtic_c;
 68		rtic_d = &rtic_d;
 69		sec_mon = &sec_mon;
 70	};
 71
 72	cpus {
 73		#address-cells = <1>;
 74		#size-cells = <0>;
 75
 76		cpu0: PowerPC,e500mc@0 {
 77			device_type = "cpu";
 78			reg = <0>;
 79			next-level-cache = <&L2_0>;
 80			L2_0: l2-cache {
 81				next-level-cache = <&cpc>;
 82			};
 83		};
 84		cpu1: PowerPC,e500mc@1 {
 85			device_type = "cpu";
 86			reg = <1>;
 87			next-level-cache = <&L2_1>;
 88			L2_1: l2-cache {
 89				next-level-cache = <&cpc>;
 90			};
 91		};
 92		cpu4: PowerPC,e500mc@4 {
 93			device_type = "cpu";
 94			reg = <4>;
 95			next-level-cache = <&L2_4>;
 96			L2_4: l2-cache {
 97				next-level-cache = <&cpc>;
 98			};
 99		};
100		cpu5: PowerPC,e500mc@5 {
101			device_type = "cpu";
102			reg = <5>;
103			next-level-cache = <&L2_5>;
104			L2_5: l2-cache {
105				next-level-cache = <&cpc>;
106			};
107		};
108		cpu6: PowerPC,e500mc@6 {
109			device_type = "cpu";
110			reg = <6>;
111			next-level-cache = <&L2_6>;
112			L2_6: l2-cache {
113				next-level-cache = <&cpc>;
114			};
115		};
116		cpu7: PowerPC,e500mc@7 {
117			device_type = "cpu";
118			reg = <7>;
119			next-level-cache = <&L2_7>;
120			L2_7: l2-cache {
121				next-level-cache = <&cpc>;
122			};
123		};
124	};
125};