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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * a4m072 board Device Tree Source
4 *
5 * Copyright (C) 2011 DENX Software Engineering GmbH
6 * Heiko Schocher <hs@denx.de>
7 *
8 * Copyright (C) 2007 Semihalf
9 * Marian Balakowicz <m8@semihalf.com>
10 */
11
12/include/ "mpc5200b.dtsi"
13
14&gpt0 { fsl,has-wdt; };
15&gpt3 { gpio-controller; };
16&gpt4 { gpio-controller; };
17&gpt5 { gpio-controller; };
18
19/ {
20 model = "anonymous,a4m072";
21 compatible = "anonymous,a4m072";
22
23 soc5200@f0000000 {
24 #address-cells = <1>;
25 #size-cells = <1>;
26 compatible = "fsl,mpc5200b-immr";
27 ranges = <0 0xf0000000 0x0000c000>;
28 reg = <0xf0000000 0x00000100>;
29 bus-frequency = <0>; /* From boot loader */
30 system-frequency = <0>; /* From boot loader */
31
32 cdm@200 {
33 fsl,init-ext-48mhz-en = <0x0>;
34 fsl,init-fd-enable = <0x01>;
35 fsl,init-fd-counters = <0x3333>;
36 };
37
38 spi@f00 {
39 status = "disabled";
40 };
41
42 psc@2000 {
43 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
44 reg = <0x2000 0x100>;
45 interrupts = <2 1 0>;
46 };
47
48 psc@2200 {
49 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
50 reg = <0x2200 0x100>;
51 interrupts = <2 2 0>;
52 };
53
54 psc@2400 {
55 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
56 reg = <0x2400 0x100>;
57 interrupts = <2 3 0>;
58 };
59
60 psc@2600 {
61 status = "disabled";
62 };
63
64 psc@2800 {
65 status = "disabled";
66 };
67
68 psc@2c00 {
69 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
70 reg = <0x2c00 0x100>;
71 interrupts = <2 4 0>;
72 };
73
74 ethernet@3000 {
75 phy-handle = <&phy0>;
76 };
77
78 mdio@3000 {
79 phy0: ethernet-phy@1f {
80 reg = <0x1f>;
81 interrupts = <1 2 0>; /* IRQ 2 active low */
82 };
83 };
84
85 i2c@3d00 {
86 status = "disabled";
87 };
88
89 i2c@3d40 {
90 hwmon@2e {
91 compatible = "nsc,lm87";
92 reg = <0x2e>;
93 };
94 rtc@51 {
95 compatible = "nxp,rtc8564";
96 reg = <0x51>;
97 };
98 };
99 };
100
101 localbus {
102 compatible = "fsl,mpc5200b-lpb","simple-bus";
103 #address-cells = <2>;
104 #size-cells = <1>;
105 ranges = <0 0 0xfe000000 0x02000000
106 1 0 0x62000000 0x00400000
107 2 0 0x64000000 0x00200000
108 3 0 0x66000000 0x01000000
109 6 0 0x68000000 0x01000000
110 7 0 0x6a000000 0x00000004>;
111
112 flash@0,0 {
113 compatible = "cfi-flash";
114 reg = <0 0 0x02000000>;
115 bank-width = <2>;
116 #size-cells = <1>;
117 #address-cells = <1>;
118 };
119 sram0@1,0 {
120 compatible = "mtd-ram";
121 reg = <1 0x00000 0x00400000>;
122 bank-width = <2>;
123 };
124 };
125
126 pci@f0000d00 {
127 #interrupt-cells = <1>;
128 #size-cells = <2>;
129 #address-cells = <3>;
130 device_type = "pci";
131 compatible = "fsl,mpc5200-pci";
132 reg = <0xf0000d00 0x100>;
133 interrupt-map-mask = <0xf800 0 0 7>;
134 interrupt-map = <
135 /* IDSEL 0x16 */
136 0xc000 0 0 1 &mpc5200_pic 1 3 3
137 0xc000 0 0 2 &mpc5200_pic 1 3 3
138 0xc000 0 0 3 &mpc5200_pic 1 3 3
139 0xc000 0 0 4 &mpc5200_pic 1 3 3>;
140 clock-frequency = <0>; /* From boot loader */
141 interrupts = <2 8 0 2 9 0 2 10 0>;
142 bus-range = <0 0>;
143 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x10000000>,
144 <0x02000000 0 0x90000000 0x90000000 0 0x10000000>,
145 <0x01000000 0 0x00000000 0xa0000000 0 0x01000000>;
146 };
147};
1/*
2 * a4m072 board Device Tree Source
3 *
4 * Copyright (C) 2011 DENX Software Engineering GmbH
5 * Heiko Schocher <hs@denx.de>
6 *
7 * Copyright (C) 2007 Semihalf
8 * Marian Balakowicz <m8@semihalf.com>
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16/include/ "mpc5200b.dtsi"
17
18/ {
19 model = "anonymous,a4m072";
20 compatible = "anonymous,a4m072";
21
22 soc5200@f0000000 {
23 #address-cells = <1>;
24 #size-cells = <1>;
25 compatible = "fsl,mpc5200b-immr";
26 ranges = <0 0xf0000000 0x0000c000>;
27 reg = <0xf0000000 0x00000100>;
28 bus-frequency = <0>; /* From boot loader */
29 system-frequency = <0>; /* From boot loader */
30
31 cdm@200 {
32 fsl,init-ext-48mhz-en = <0x0>;
33 fsl,init-fd-enable = <0x01>;
34 fsl,init-fd-counters = <0x3333>;
35 };
36
37 timer@600 {
38 fsl,has-wdt;
39 };
40
41 gpt3: timer@630 { /* General Purpose Timer in GPIO mode */
42 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
43 gpio-controller;
44 #gpio-cells = <2>;
45 };
46
47 gpt4: timer@640 { /* General Purpose Timer in GPIO mode */
48 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
49 gpio-controller;
50 #gpio-cells = <2>;
51 };
52
53 gpt5: timer@650 { /* General Purpose Timer in GPIO mode */
54 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
55 gpio-controller;
56 #gpio-cells = <2>;
57 };
58
59 spi@f00 {
60 status = "disabled";
61 };
62
63 psc@2000 {
64 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
65 reg = <0x2000 0x100>;
66 interrupts = <2 1 0>;
67 };
68
69 psc@2200 {
70 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
71 reg = <0x2200 0x100>;
72 interrupts = <2 2 0>;
73 };
74
75 psc@2400 {
76 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
77 reg = <0x2400 0x100>;
78 interrupts = <2 3 0>;
79 };
80
81 psc@2600 {
82 status = "disabled";
83 };
84
85 psc@2800 {
86 status = "disabled";
87 };
88
89 psc@2c00 {
90 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
91 reg = <0x2c00 0x100>;
92 interrupts = <2 4 0>;
93 };
94
95 ethernet@3000 {
96 phy-handle = <&phy0>;
97 };
98
99 mdio@3000 {
100 phy0: ethernet-phy@1f {
101 reg = <0x1f>;
102 interrupts = <1 2 0>; /* IRQ 2 active low */
103 };
104 };
105
106 i2c@3d00 {
107 status = "disabled";
108 };
109
110 i2c@3d40 {
111 hwmon@2e {
112 compatible = "nsc,lm87";
113 reg = <0x2e>;
114 };
115 rtc@51 {
116 compatible = "nxp,rtc8564";
117 reg = <0x51>;
118 };
119 };
120 };
121
122 localbus {
123 compatible = "fsl,mpc5200b-lpb","simple-bus";
124 #address-cells = <2>;
125 #size-cells = <1>;
126 ranges = <0 0 0xfe000000 0x02000000
127 1 0 0x62000000 0x00400000
128 2 0 0x64000000 0x00200000
129 3 0 0x66000000 0x01000000
130 6 0 0x68000000 0x01000000
131 7 0 0x6a000000 0x00000004>;
132
133 flash@0,0 {
134 compatible = "cfi-flash";
135 reg = <0 0 0x02000000>;
136 bank-width = <2>;
137 #size-cells = <1>;
138 #address-cells = <1>;
139 };
140 sram0@1,0 {
141 compatible = "mtd-ram";
142 reg = <1 0x00000 0x00400000>;
143 bank-width = <2>;
144 };
145 };
146
147 pci@f0000d00 {
148 #interrupt-cells = <1>;
149 #size-cells = <2>;
150 #address-cells = <3>;
151 device_type = "pci";
152 compatible = "fsl,mpc5200-pci";
153 reg = <0xf0000d00 0x100>;
154 interrupt-map-mask = <0xf800 0 0 7>;
155 interrupt-map = <
156 /* IDSEL 0x16 */
157 0xc000 0 0 1 &mpc5200_pic 1 3 3
158 0xc000 0 0 2 &mpc5200_pic 1 3 3
159 0xc000 0 0 3 &mpc5200_pic 1 3 3
160 0xc000 0 0 4 &mpc5200_pic 1 3 3>;
161 clock-frequency = <0>; /* From boot loader */
162 interrupts = <2 8 0 2 9 0 2 10 0>;
163 bus-range = <0 0>;
164 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x10000000
165 0x02000000 0 0x90000000 0x90000000 0 0x10000000
166 0x01000000 0 0x00000000 0xa0000000 0 0x01000000>;
167 };
168};