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1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2022 BayLibre, SAS.
4 * Author: Fabien Parent <fparent@baylibre.com>
5 */
6/dts-v1/;
7
8#include "mt8195.dtsi"
9#include "mt6359.dtsi"
10
11#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/input/input.h>
13#include <dt-bindings/pinctrl/mt8195-pinfunc.h>
14#include <dt-bindings/regulator/mediatek,mt6360-regulator.h>
15
16/ {
17 model = "MediaTek MT8195 demo board";
18 compatible = "mediatek,mt8195-demo", "mediatek,mt8195";
19
20 aliases {
21 serial0 = &uart0;
22 };
23
24 chosen {
25 stdout-path = "serial0:921600n8";
26 };
27
28 firmware {
29 optee {
30 compatible = "linaro,optee-tz";
31 method = "smc";
32 };
33 };
34
35 gpio-keys {
36 compatible = "gpio-keys";
37 pinctrl-names = "default";
38 pinctrl-0 = <&gpio_keys_pins>;
39
40 key-0 {
41 gpios = <&pio 106 GPIO_ACTIVE_LOW>;
42 label = "volume_up";
43 linux,code = <KEY_VOLUMEUP>;
44 wakeup-source;
45 debounce-interval = <15>;
46 };
47 };
48
49 memory@40000000 {
50 device_type = "memory";
51 reg = <0 0x40000000 0x2 0x00000000>;
52 };
53
54 reserved-memory {
55 #address-cells = <2>;
56 #size-cells = <2>;
57 ranges;
58
59 /*
60 * 12 MiB reserved for OP-TEE (BL32)
61 * +-----------------------+ 0x43e0_0000
62 * | SHMEM 2MiB |
63 * +-----------------------+ 0x43c0_0000
64 * | | TA_RAM 8MiB |
65 * + TZDRAM +--------------+ 0x4340_0000
66 * | | TEE_RAM 2MiB |
67 * +-----------------------+ 0x4320_0000
68 */
69 optee_reserved: optee@43200000 {
70 no-map;
71 reg = <0 0x43200000 0 0x00c00000>;
72 };
73
74 scp_mem: memory@50000000 {
75 compatible = "shared-dma-pool";
76 reg = <0 0x50000000 0 0x2900000>;
77 no-map;
78 };
79
80 vpu_mem: memory@53000000 {
81 compatible = "shared-dma-pool";
82 reg = <0 0x53000000 0 0x1400000>; /* 20 MB */
83 };
84
85 /* 2 MiB reserved for ARM Trusted Firmware (BL31) */
86 bl31_secmon_mem: memory@54600000 {
87 no-map;
88 reg = <0 0x54600000 0x0 0x200000>;
89 };
90
91 snd_dma_mem: memory@60000000 {
92 compatible = "shared-dma-pool";
93 reg = <0 0x60000000 0 0x1100000>;
94 no-map;
95 };
96
97 apu_mem: memory@62000000 {
98 compatible = "shared-dma-pool";
99 reg = <0 0x62000000 0 0x1400000>; /* 20 MB */
100 };
101 };
102};
103
104ð {
105 phy-mode = "rgmii-id";
106 phy-handle = <ðernet_phy0>;
107 snps,reset-gpio = <&pio 93 GPIO_ACTIVE_HIGH>;
108 snps,reset-delays-us = <0 10000 80000>;
109 pinctrl-names = "default", "sleep";
110 pinctrl-0 = <ð_default_pins>;
111 pinctrl-1 = <ð_sleep_pins>;
112 status = "okay";
113
114 mdio {
115 ethernet_phy0: ethernet-phy@1 {
116 reg = <0x1>;
117 };
118 };
119};
120
121&i2c6 {
122 clock-frequency = <400000>;
123 pinctrl-0 = <&i2c6_pins>;
124 pinctrl-names = "default";
125 status = "okay";
126
127 mt6360: pmic@34 {
128 compatible = "mediatek,mt6360";
129 reg = <0x34>;
130 interrupt-controller;
131 #interrupt-cells = <1>;
132 interrupts-extended = <&pio 101 IRQ_TYPE_EDGE_FALLING>;
133 interrupt-names = "IRQB";
134
135 charger {
136 compatible = "mediatek,mt6360-chg";
137 richtek,vinovp-microvolt = <14500000>;
138
139 otg_vbus_regulator: usb-otg-vbus-regulator {
140 regulator-name = "usb-otg-vbus";
141 regulator-min-microvolt = <4425000>;
142 regulator-max-microvolt = <5825000>;
143 };
144 };
145
146 regulator {
147 compatible = "mediatek,mt6360-regulator";
148 LDO_VIN3-supply = <&mt6360_buck2>;
149
150 mt6360_buck1: buck1 {
151 regulator-name = "mt6360,buck1";
152 regulator-min-microvolt = <300000>;
153 regulator-max-microvolt = <1300000>;
154 regulator-allowed-modes = <MT6360_OPMODE_NORMAL
155 MT6360_OPMODE_LP
156 MT6360_OPMODE_ULP>;
157 regulator-always-on;
158 };
159
160 mt6360_buck2: buck2 {
161 regulator-name = "mt6360,buck2";
162 regulator-min-microvolt = <300000>;
163 regulator-max-microvolt = <1300000>;
164 regulator-allowed-modes = <MT6360_OPMODE_NORMAL
165 MT6360_OPMODE_LP
166 MT6360_OPMODE_ULP>;
167 regulator-always-on;
168 };
169
170 mt6360_ldo1: ldo1 {
171 regulator-name = "mt6360,ldo1";
172 regulator-min-microvolt = <1200000>;
173 regulator-max-microvolt = <3600000>;
174 regulator-allowed-modes = <MT6360_OPMODE_NORMAL
175 MT6360_OPMODE_LP>;
176 };
177
178 mt6360_ldo2: ldo2 {
179 regulator-name = "mt6360,ldo2";
180 regulator-min-microvolt = <1200000>;
181 regulator-max-microvolt = <3600000>;
182 regulator-allowed-modes = <MT6360_OPMODE_NORMAL
183 MT6360_OPMODE_LP>;
184 };
185
186 mt6360_ldo3: ldo3 {
187 regulator-name = "mt6360,ldo3";
188 regulator-min-microvolt = <1200000>;
189 regulator-max-microvolt = <3600000>;
190 regulator-allowed-modes = <MT6360_OPMODE_NORMAL
191 MT6360_OPMODE_LP>;
192 };
193
194 mt6360_ldo5: ldo5 {
195 regulator-name = "mt6360,ldo5";
196 regulator-min-microvolt = <2700000>;
197 regulator-max-microvolt = <3600000>;
198 regulator-allowed-modes = <MT6360_OPMODE_NORMAL
199 MT6360_OPMODE_LP>;
200 };
201
202 mt6360_ldo6: ldo6 {
203 regulator-name = "mt6360,ldo6";
204 regulator-min-microvolt = <500000>;
205 regulator-max-microvolt = <2100000>;
206 regulator-allowed-modes = <MT6360_OPMODE_NORMAL
207 MT6360_OPMODE_LP>;
208 };
209
210 mt6360_ldo7: ldo7 {
211 regulator-name = "mt6360,ldo7";
212 regulator-min-microvolt = <500000>;
213 regulator-max-microvolt = <2100000>;
214 regulator-allowed-modes = <MT6360_OPMODE_NORMAL
215 MT6360_OPMODE_LP>;
216 regulator-always-on;
217 };
218 };
219 };
220};
221
222&mmc0 {
223 status = "okay";
224 pinctrl-names = "default", "state_uhs";
225 pinctrl-0 = <&mmc0_default_pins>;
226 pinctrl-1 = <&mmc0_uhs_pins>;
227 bus-width = <8>;
228 max-frequency = <200000000>;
229 cap-mmc-highspeed;
230 mmc-hs200-1_8v;
231 mmc-hs400-1_8v;
232 cap-mmc-hw-reset;
233 no-sdio;
234 no-sd;
235 hs400-ds-delay = <0x14c11>;
236 vmmc-supply = <&mt6359_vemc_1_ldo_reg>;
237 vqmmc-supply = <&mt6359_vufs_ldo_reg>;
238 non-removable;
239};
240
241&mmc1 {
242 pinctrl-names = "default", "state_uhs";
243 pinctrl-0 = <&mmc1_default_pins>;
244 pinctrl-1 = <&mmc1_uhs_pins>;
245 cd-gpios = <&pio 129 GPIO_ACTIVE_LOW>;
246 bus-width = <4>;
247 max-frequency = <200000000>;
248 cap-sd-highspeed;
249 sd-uhs-sdr50;
250 sd-uhs-sdr104;
251 vmmc-supply = <&mt6360_ldo5>;
252 vqmmc-supply = <&mt6360_ldo3>;
253 status = "okay";
254};
255
256&mt6359_vbbck_ldo_reg {
257 regulator-always-on;
258};
259
260&mt6359_vcore_buck_reg {
261 regulator-always-on;
262};
263
264&mt6359_vgpu11_buck_reg {
265 regulator-always-on;
266};
267
268&mt6359_vproc1_buck_reg {
269 regulator-always-on;
270};
271
272&mt6359_vproc2_buck_reg {
273 regulator-always-on;
274};
275
276&mt6359_vpu_buck_reg {
277 regulator-always-on;
278};
279
280&mt6359_vrf12_ldo_reg {
281 regulator-always-on;
282};
283
284&mt6359_vsram_md_ldo_reg {
285 regulator-always-on;
286};
287
288&mt6359_vsram_others_ldo_reg {
289 regulator-always-on;
290};
291
292&pio {
293 eth_default_pins: eth-default-pins {
294 pins-txd {
295 pinmux = <PINMUX_GPIO77__FUNC_GBE_TXD3>,
296 <PINMUX_GPIO78__FUNC_GBE_TXD2>,
297 <PINMUX_GPIO79__FUNC_GBE_TXD1>,
298 <PINMUX_GPIO80__FUNC_GBE_TXD0>;
299 drive-strength = <8>;
300 };
301 pins-cc {
302 pinmux = <PINMUX_GPIO85__FUNC_GBE_TXC>,
303 <PINMUX_GPIO88__FUNC_GBE_TXEN>,
304 <PINMUX_GPIO87__FUNC_GBE_RXDV>,
305 <PINMUX_GPIO86__FUNC_GBE_RXC>;
306 drive-strength = <8>;
307 };
308 pins-rxd {
309 pinmux = <PINMUX_GPIO81__FUNC_GBE_RXD3>,
310 <PINMUX_GPIO82__FUNC_GBE_RXD2>,
311 <PINMUX_GPIO83__FUNC_GBE_RXD1>,
312 <PINMUX_GPIO84__FUNC_GBE_RXD0>;
313 };
314 pins-mdio {
315 pinmux = <PINMUX_GPIO89__FUNC_GBE_MDC>,
316 <PINMUX_GPIO90__FUNC_GBE_MDIO>;
317 input-enable;
318 };
319 pins-power {
320 pinmux = <PINMUX_GPIO91__FUNC_GPIO91>,
321 <PINMUX_GPIO92__FUNC_GPIO92>;
322 output-high;
323 };
324 };
325
326 eth_sleep_pins: eth-sleep-pins {
327 pins-txd {
328 pinmux = <PINMUX_GPIO77__FUNC_GPIO77>,
329 <PINMUX_GPIO78__FUNC_GPIO78>,
330 <PINMUX_GPIO79__FUNC_GPIO79>,
331 <PINMUX_GPIO80__FUNC_GPIO80>;
332 };
333 pins-cc {
334 pinmux = <PINMUX_GPIO85__FUNC_GPIO85>,
335 <PINMUX_GPIO88__FUNC_GPIO88>,
336 <PINMUX_GPIO87__FUNC_GPIO87>,
337 <PINMUX_GPIO86__FUNC_GPIO86>;
338 };
339 pins-rxd {
340 pinmux = <PINMUX_GPIO81__FUNC_GPIO81>,
341 <PINMUX_GPIO82__FUNC_GPIO82>,
342 <PINMUX_GPIO83__FUNC_GPIO83>,
343 <PINMUX_GPIO84__FUNC_GPIO84>;
344 };
345 pins-mdio {
346 pinmux = <PINMUX_GPIO89__FUNC_GPIO89>,
347 <PINMUX_GPIO90__FUNC_GPIO90>;
348 input-disable;
349 bias-disable;
350 };
351 };
352
353 gpio_keys_pins: gpio-keys-pins {
354 pins {
355 pinmux = <PINMUX_GPIO106__FUNC_GPIO106>;
356 input-enable;
357 };
358 };
359
360 i2c6_pins: i2c6-pins {
361 pins {
362 pinmux = <PINMUX_GPIO25__FUNC_SDA6>,
363 <PINMUX_GPIO26__FUNC_SCL6>;
364 bias-pull-up;
365 };
366 };
367
368 mmc0_default_pins: mmc0-default-pins {
369 pins-clk {
370 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
371 drive-strength = <6>;
372 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
373 };
374
375 pins-cmd-dat {
376 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>,
377 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>,
378 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>,
379 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>,
380 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>,
381 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>,
382 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>,
383 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
384 <PINMUX_GPIO121__FUNC_MSDC0_CMD>;
385 input-enable;
386 drive-strength = <6>;
387 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
388 };
389
390 pins-rst {
391 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
392 drive-strength = <6>;
393 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
394 };
395 };
396
397 mmc0_uhs_pins: mmc0-uhs-pins {
398 pins-clk {
399 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
400 drive-strength = <8>;
401 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
402 };
403
404 pins-cmd-dat {
405 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>,
406 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>,
407 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>,
408 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>,
409 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>,
410 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>,
411 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>,
412 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
413 <PINMUX_GPIO121__FUNC_MSDC0_CMD>;
414 input-enable;
415 drive-strength = <8>;
416 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
417 };
418
419 pins-ds {
420 pinmux = <PINMUX_GPIO127__FUNC_MSDC0_DSL>;
421 drive-strength = <8>;
422 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
423 };
424
425 pins-rst {
426 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
427 drive-strength = <8>;
428 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
429 };
430 };
431
432 mmc1_default_pins: mmc1-default-pins {
433 pins-clk {
434 pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>;
435 drive-strength = <8>;
436 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
437 };
438
439 pins-cmd-dat {
440 pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>,
441 <PINMUX_GPIO112__FUNC_MSDC1_DAT0>,
442 <PINMUX_GPIO113__FUNC_MSDC1_DAT1>,
443 <PINMUX_GPIO114__FUNC_MSDC1_DAT2>,
444 <PINMUX_GPIO115__FUNC_MSDC1_DAT3>;
445 input-enable;
446 drive-strength = <8>;
447 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
448 };
449
450 pins-insert {
451 pinmux = <PINMUX_GPIO129__FUNC_GPIO129>;
452 bias-pull-up;
453 };
454 };
455
456 mmc1_uhs_pins: mmc1-uhs-pins {
457 pins-clk {
458 pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>;
459 drive-strength = <8>;
460 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
461 };
462
463 pins-cmd-dat {
464 pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>,
465 <PINMUX_GPIO112__FUNC_MSDC1_DAT0>,
466 <PINMUX_GPIO113__FUNC_MSDC1_DAT1>,
467 <PINMUX_GPIO114__FUNC_MSDC1_DAT2>,
468 <PINMUX_GPIO115__FUNC_MSDC1_DAT3>;
469 input-enable;
470 drive-strength = <8>;
471 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
472 };
473 };
474
475 uart0_pins: uart0-pins {
476 pins {
477 pinmux = <PINMUX_GPIO98__FUNC_UTXD0>,
478 <PINMUX_GPIO99__FUNC_URXD0>;
479 };
480 };
481
482 uart1_pins: uart1-pins {
483 pins {
484 pinmux = <PINMUX_GPIO102__FUNC_UTXD1>,
485 <PINMUX_GPIO103__FUNC_URXD1>;
486 };
487 };
488};
489
490
491&pmic {
492 interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>;
493};
494
495&uart0 {
496 pinctrl-names = "default";
497 pinctrl-0 = <&uart0_pins>;
498 status = "okay";
499};
500
501&uart1 {
502 pinctrl-names = "default";
503 pinctrl-0 = <&uart1_pins>;
504 status = "okay";
505};
506
507&u3phy0 {
508 status = "okay";
509};
510
511&u3phy1 {
512 status = "okay";
513};
514
515&u3phy2 {
516 status = "okay";
517};
518
519&u3phy3 {
520 status = "okay";
521};
522
523&ssusb0 {
524 vusb33-supply = <&mt6359_vusb_ldo_reg>;
525 status = "okay";
526};
527
528&ssusb2 {
529 vusb33-supply = <&mt6359_vusb_ldo_reg>;
530 status = "okay";
531};
532
533&ssusb3 {
534 vusb33-supply = <&mt6359_vusb_ldo_reg>;
535 status = "okay";
536};
537
538&xhci0 {
539 vbus-supply = <&otg_vbus_regulator>;
540 status = "okay";
541};
542
543&xhci1 {
544 vusb33-supply = <&mt6359_vusb_ldo_reg>;
545 status = "okay";
546};
547
548&xhci2 {
549 status = "okay";
550};
551
552&xhci3 {
553 status = "okay";
554};