1/*
  2 *  linux/arch/arm/common/gic.c
  3 *
  4 *  Copyright (C) 2002 ARM Limited, All Rights Reserved.
  5 *
  6 * This program is free software; you can redistribute it and/or modify
  7 * it under the terms of the GNU General Public License version 2 as
  8 * published by the Free Software Foundation.
  9 *
 10 * Interrupt architecture for the GIC:
 11 *
 12 * o There is one Interrupt Distributor, which receives interrupts
 13 *   from system devices and sends them to the Interrupt Controllers.
 14 *
 15 * o There is one CPU Interface per CPU, which sends interrupts sent
 16 *   by the Distributor, and interrupts generated locally, to the
 17 *   associated CPU. The base address of the CPU interface is usually
 18 *   aliased so that the same address points to different chips depending
 19 *   on the CPU it is accessed from.
 20 *
 21 * Note that IRQs 0-31 are special - they are local to each CPU.
 22 * As such, the enable set/clear, pending set/clear and active bit
 23 * registers are banked per-cpu for these sources.
 24 */
 25#include <linux/init.h>
 26#include <linux/kernel.h>
 27#include <linux/err.h>
 28#include <linux/module.h>
 29#include <linux/list.h>
 30#include <linux/smp.h>
 31#include <linux/cpu_pm.h>
 32#include <linux/cpumask.h>
 33#include <linux/io.h>
 34#include <linux/of.h>
 35#include <linux/of_address.h>
 36#include <linux/of_irq.h>
 37#include <linux/irqdomain.h>
 38#include <linux/interrupt.h>
 39#include <linux/percpu.h>
 40#include <linux/slab.h>
 41
 42#include <asm/irq.h>
 43#include <asm/exception.h>
 44#include <asm/smp_plat.h>
 45#include <asm/mach/irq.h>
 46#include <asm/hardware/gic.h>
 47
 48union gic_base {
 49	void __iomem *common_base;
 50	void __percpu __iomem **percpu_base;
 51};
 52
 53struct gic_chip_data {
 54	union gic_base dist_base;
 55	union gic_base cpu_base;
 56#ifdef CONFIG_CPU_PM
 57	u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
 58	u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];
 59	u32 saved_spi_target[DIV_ROUND_UP(1020, 4)];
 60	u32 __percpu *saved_ppi_enable;
 61	u32 __percpu *saved_ppi_conf;
 62#endif
 63	struct irq_domain *domain;
 64	unsigned int gic_irqs;
 65#ifdef CONFIG_GIC_NON_BANKED
 66	void __iomem *(*get_base)(union gic_base *);
 67#endif
 68};
 69
 70static DEFINE_RAW_SPINLOCK(irq_controller_lock);
 71
 72/*
 73 * Supported arch specific GIC irq extension.
 74 * Default make them NULL.
 75 */
 76struct irq_chip gic_arch_extn = {
 77	.irq_eoi	= NULL,
 78	.irq_mask	= NULL,
 79	.irq_unmask	= NULL,
 80	.irq_retrigger	= NULL,
 81	.irq_set_type	= NULL,
 82	.irq_set_wake	= NULL,
 83};
 84
 85#ifndef MAX_GIC_NR
 86#define MAX_GIC_NR	1
 87#endif
 88
 89static struct gic_chip_data gic_data[MAX_GIC_NR] __read_mostly;
 90
 91#ifdef CONFIG_GIC_NON_BANKED
 92static void __iomem *gic_get_percpu_base(union gic_base *base)
 93{
 94	return *__this_cpu_ptr(base->percpu_base);
 95}
 96
 97static void __iomem *gic_get_common_base(union gic_base *base)
 98{
 99	return base->common_base;
100}
101
102static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data)
103{
104	return data->get_base(&data->dist_base);
105}
106
107static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data)
108{
109	return data->get_base(&data->cpu_base);
110}
111
112static inline void gic_set_base_accessor(struct gic_chip_data *data,
113					 void __iomem *(*f)(union gic_base *))
114{
115	data->get_base = f;
116}
117#else
118#define gic_data_dist_base(d)	((d)->dist_base.common_base)
119#define gic_data_cpu_base(d)	((d)->cpu_base.common_base)
120#define gic_set_base_accessor(d,f)
121#endif
122
123static inline void __iomem *gic_dist_base(struct irq_data *d)
124{
125	struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
126	return gic_data_dist_base(gic_data);
127}
128
129static inline void __iomem *gic_cpu_base(struct irq_data *d)
130{
131	struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
132	return gic_data_cpu_base(gic_data);
133}
134
135static inline unsigned int gic_irq(struct irq_data *d)
136{
137	return d->hwirq;
138}
139
140/*
141 * Routines to acknowledge, disable and enable interrupts
142 */
143static void gic_mask_irq(struct irq_data *d)
144{
145	u32 mask = 1 << (gic_irq(d) % 32);
146
147	raw_spin_lock(&irq_controller_lock);
148	writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4);
149	if (gic_arch_extn.irq_mask)
150		gic_arch_extn.irq_mask(d);
151	raw_spin_unlock(&irq_controller_lock);
152}
153
154static void gic_unmask_irq(struct irq_data *d)
155{
156	u32 mask = 1 << (gic_irq(d) % 32);
157
158	raw_spin_lock(&irq_controller_lock);
159	if (gic_arch_extn.irq_unmask)
160		gic_arch_extn.irq_unmask(d);
161	writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4);
162	raw_spin_unlock(&irq_controller_lock);
163}
164
165static void gic_eoi_irq(struct irq_data *d)
166{
167	if (gic_arch_extn.irq_eoi) {
168		raw_spin_lock(&irq_controller_lock);
169		gic_arch_extn.irq_eoi(d);
170		raw_spin_unlock(&irq_controller_lock);
171	}
172
173	writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
174}
175
176static int gic_set_type(struct irq_data *d, unsigned int type)
177{
178	void __iomem *base = gic_dist_base(d);
179	unsigned int gicirq = gic_irq(d);
180	u32 enablemask = 1 << (gicirq % 32);
181	u32 enableoff = (gicirq / 32) * 4;
182	u32 confmask = 0x2 << ((gicirq % 16) * 2);
183	u32 confoff = (gicirq / 16) * 4;
184	bool enabled = false;
185	u32 val;
186
187	/* Interrupt configuration for SGIs can't be changed */
188	if (gicirq < 16)
189		return -EINVAL;
190
191	if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING)
192		return -EINVAL;
193
194	raw_spin_lock(&irq_controller_lock);
195
196	if (gic_arch_extn.irq_set_type)
197		gic_arch_extn.irq_set_type(d, type);
198
199	val = readl_relaxed(base + GIC_DIST_CONFIG + confoff);
200	if (type == IRQ_TYPE_LEVEL_HIGH)
201		val &= ~confmask;
202	else if (type == IRQ_TYPE_EDGE_RISING)
203		val |= confmask;
204
205	/*
206	 * As recommended by the spec, disable the interrupt before changing
207	 * the configuration
208	 */
209	if (readl_relaxed(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) {
210		writel_relaxed(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff);
211		enabled = true;
212	}
213
214	writel_relaxed(val, base + GIC_DIST_CONFIG + confoff);
215
216	if (enabled)
217		writel_relaxed(enablemask, base + GIC_DIST_ENABLE_SET + enableoff);
218
219	raw_spin_unlock(&irq_controller_lock);
220
221	return 0;
222}
223
224static int gic_retrigger(struct irq_data *d)
225{
226	if (gic_arch_extn.irq_retrigger)
227		return gic_arch_extn.irq_retrigger(d);
228
229	return -ENXIO;
230}
231
232#ifdef CONFIG_SMP
233static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
234			    bool force)
235{
236	void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3);
237	unsigned int shift = (gic_irq(d) % 4) * 8;
238	unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask);
239	u32 val, mask, bit;
240
241	if (cpu >= 8 || cpu >= nr_cpu_ids)
242		return -EINVAL;
243
244	mask = 0xff << shift;
245	bit = 1 << (cpu_logical_map(cpu) + shift);
246
247	raw_spin_lock(&irq_controller_lock);
248	val = readl_relaxed(reg) & ~mask;
249	writel_relaxed(val | bit, reg);
250	raw_spin_unlock(&irq_controller_lock);
251
252	return IRQ_SET_MASK_OK;
253}
254#endif
255
256#ifdef CONFIG_PM
257static int gic_set_wake(struct irq_data *d, unsigned int on)
258{
259	int ret = -ENXIO;
260
261	if (gic_arch_extn.irq_set_wake)
262		ret = gic_arch_extn.irq_set_wake(d, on);
263
264	return ret;
265}
266
267#else
268#define gic_set_wake	NULL
269#endif
270
271asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
272{
273	u32 irqstat, irqnr;
274	struct gic_chip_data *gic = &gic_data[0];
275	void __iomem *cpu_base = gic_data_cpu_base(gic);
276
277	do {
278		irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK);
279		irqnr = irqstat & ~0x1c00;
280
281		if (likely(irqnr > 15 && irqnr < 1021)) {
282			irqnr = irq_find_mapping(gic->domain, irqnr);
283			handle_IRQ(irqnr, regs);
284			continue;
285		}
286		if (irqnr < 16) {
287			writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
288#ifdef CONFIG_SMP
289			handle_IPI(irqnr, regs);
290#endif
291			continue;
292		}
293		break;
294	} while (1);
295}
296
297static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
298{
299	struct gic_chip_data *chip_data = irq_get_handler_data(irq);
300	struct irq_chip *chip = irq_get_chip(irq);
301	unsigned int cascade_irq, gic_irq;
302	unsigned long status;
303
304	chained_irq_enter(chip, desc);
305
306	raw_spin_lock(&irq_controller_lock);
307	status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK);
308	raw_spin_unlock(&irq_controller_lock);
309
310	gic_irq = (status & 0x3ff);
311	if (gic_irq == 1023)
312		goto out;
313
314	cascade_irq = irq_find_mapping(chip_data->domain, gic_irq);
315	if (unlikely(gic_irq < 32 || gic_irq > 1020))
316		do_bad_IRQ(cascade_irq, desc);
317	else
318		generic_handle_irq(cascade_irq);
319
320 out:
321	chained_irq_exit(chip, desc);
322}
323
324static struct irq_chip gic_chip = {
325	.name			= "GIC",
326	.irq_mask		= gic_mask_irq,
327	.irq_unmask		= gic_unmask_irq,
328	.irq_eoi		= gic_eoi_irq,
329	.irq_set_type		= gic_set_type,
330	.irq_retrigger		= gic_retrigger,
331#ifdef CONFIG_SMP
332	.irq_set_affinity	= gic_set_affinity,
333#endif
334	.irq_set_wake		= gic_set_wake,
335};
336
337void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
338{
339	if (gic_nr >= MAX_GIC_NR)
340		BUG();
341	if (irq_set_handler_data(irq, &gic_data[gic_nr]) != 0)
342		BUG();
343	irq_set_chained_handler(irq, gic_handle_cascade_irq);
344}
345
346static void __init gic_dist_init(struct gic_chip_data *gic)
347{
348	unsigned int i;
349	u32 cpumask;
350	unsigned int gic_irqs = gic->gic_irqs;
351	void __iomem *base = gic_data_dist_base(gic);
352	u32 cpu = cpu_logical_map(smp_processor_id());
353
354	cpumask = 1 << cpu;
355	cpumask |= cpumask << 8;
356	cpumask |= cpumask << 16;
357
358	writel_relaxed(0, base + GIC_DIST_CTRL);
359
360	/*
361	 * Set all global interrupts to be level triggered, active low.
362	 */
363	for (i = 32; i < gic_irqs; i += 16)
364		writel_relaxed(0, base + GIC_DIST_CONFIG + i * 4 / 16);
365
366	/*
367	 * Set all global interrupts to this CPU only.
368	 */
369	for (i = 32; i < gic_irqs; i += 4)
370		writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
371
372	/*
373	 * Set priority on all global interrupts.
374	 */
375	for (i = 32; i < gic_irqs; i += 4)
376		writel_relaxed(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4);
377
378	/*
379	 * Disable all interrupts.  Leave the PPI and SGIs alone
380	 * as these enables are banked registers.
381	 */
382	for (i = 32; i < gic_irqs; i += 32)
383		writel_relaxed(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);
384
385	writel_relaxed(1, base + GIC_DIST_CTRL);
386}
387
388static void __cpuinit gic_cpu_init(struct gic_chip_data *gic)
389{
390	void __iomem *dist_base = gic_data_dist_base(gic);
391	void __iomem *base = gic_data_cpu_base(gic);
392	int i;
393
394	/*
395	 * Deal with the banked PPI and SGI interrupts - disable all
396	 * PPI interrupts, ensure all SGI interrupts are enabled.
397	 */
398	writel_relaxed(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR);
399	writel_relaxed(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET);
400
401	/*
402	 * Set priority on PPI and SGI interrupts
403	 */
404	for (i = 0; i < 32; i += 4)
405		writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4);
406
407	writel_relaxed(0xf0, base + GIC_CPU_PRIMASK);
408	writel_relaxed(1, base + GIC_CPU_CTRL);
409}
410
411#ifdef CONFIG_CPU_PM
412/*
413 * Saves the GIC distributor registers during suspend or idle.  Must be called
414 * with interrupts disabled but before powering down the GIC.  After calling
415 * this function, no interrupts will be delivered by the GIC, and another
416 * platform-specific wakeup source must be enabled.
417 */
418static void gic_dist_save(unsigned int gic_nr)
419{
420	unsigned int gic_irqs;
421	void __iomem *dist_base;
422	int i;
423
424	if (gic_nr >= MAX_GIC_NR)
425		BUG();
426
427	gic_irqs = gic_data[gic_nr].gic_irqs;
428	dist_base = gic_data_dist_base(&gic_data[gic_nr]);
429
430	if (!dist_base)
431		return;
432
433	for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
434		gic_data[gic_nr].saved_spi_conf[i] =
435			readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
436
437	for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
438		gic_data[gic_nr].saved_spi_target[i] =
439			readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
440
441	for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
442		gic_data[gic_nr].saved_spi_enable[i] =
443			readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
444}
445
446/*
447 * Restores the GIC distributor registers during resume or when coming out of
448 * idle.  Must be called before enabling interrupts.  If a level interrupt
449 * that occured while the GIC was suspended is still present, it will be
450 * handled normally, but any edge interrupts that occured will not be seen by
451 * the GIC and need to be handled by the platform-specific wakeup source.
452 */
453static void gic_dist_restore(unsigned int gic_nr)
454{
455	unsigned int gic_irqs;
456	unsigned int i;
457	void __iomem *dist_base;
458
459	if (gic_nr >= MAX_GIC_NR)
460		BUG();
461
462	gic_irqs = gic_data[gic_nr].gic_irqs;
463	dist_base = gic_data_dist_base(&gic_data[gic_nr]);
464
465	if (!dist_base)
466		return;
467
468	writel_relaxed(0, dist_base + GIC_DIST_CTRL);
469
470	for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
471		writel_relaxed(gic_data[gic_nr].saved_spi_conf[i],
472			dist_base + GIC_DIST_CONFIG + i * 4);
473
474	for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
475		writel_relaxed(0xa0a0a0a0,
476			dist_base + GIC_DIST_PRI + i * 4);
477
478	for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
479		writel_relaxed(gic_data[gic_nr].saved_spi_target[i],
480			dist_base + GIC_DIST_TARGET + i * 4);
481
482	for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
483		writel_relaxed(gic_data[gic_nr].saved_spi_enable[i],
484			dist_base + GIC_DIST_ENABLE_SET + i * 4);
485
486	writel_relaxed(1, dist_base + GIC_DIST_CTRL);
487}
488
489static void gic_cpu_save(unsigned int gic_nr)
490{
491	int i;
492	u32 *ptr;
493	void __iomem *dist_base;
494	void __iomem *cpu_base;
495
496	if (gic_nr >= MAX_GIC_NR)
497		BUG();
498
499	dist_base = gic_data_dist_base(&gic_data[gic_nr]);
500	cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
501
502	if (!dist_base || !cpu_base)
503		return;
504
505	ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_enable);
506	for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
507		ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
508
509	ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_conf);
510	for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
511		ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
512
513}
514
515static void gic_cpu_restore(unsigned int gic_nr)
516{
517	int i;
518	u32 *ptr;
519	void __iomem *dist_base;
520	void __iomem *cpu_base;
521
522	if (gic_nr >= MAX_GIC_NR)
523		BUG();
524
525	dist_base = gic_data_dist_base(&gic_data[gic_nr]);
526	cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
527
528	if (!dist_base || !cpu_base)
529		return;
530
531	ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_enable);
532	for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
533		writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4);
534
535	ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_conf);
536	for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
537		writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4);
538
539	for (i = 0; i < DIV_ROUND_UP(32, 4); i++)
540		writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4);
541
542	writel_relaxed(0xf0, cpu_base + GIC_CPU_PRIMASK);
543	writel_relaxed(1, cpu_base + GIC_CPU_CTRL);
544}
545
546static int gic_notifier(struct notifier_block *self, unsigned long cmd,	void *v)
547{
548	int i;
549
550	for (i = 0; i < MAX_GIC_NR; i++) {
551#ifdef CONFIG_GIC_NON_BANKED
552		/* Skip over unused GICs */
553		if (!gic_data[i].get_base)
554			continue;
555#endif
556		switch (cmd) {
557		case CPU_PM_ENTER:
558			gic_cpu_save(i);
559			break;
560		case CPU_PM_ENTER_FAILED:
561		case CPU_PM_EXIT:
562			gic_cpu_restore(i);
563			break;
564		case CPU_CLUSTER_PM_ENTER:
565			gic_dist_save(i);
566			break;
567		case CPU_CLUSTER_PM_ENTER_FAILED:
568		case CPU_CLUSTER_PM_EXIT:
569			gic_dist_restore(i);
570			break;
571		}
572	}
573
574	return NOTIFY_OK;
575}
576
577static struct notifier_block gic_notifier_block = {
578	.notifier_call = gic_notifier,
579};
580
581static void __init gic_pm_init(struct gic_chip_data *gic)
582{
583	gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
584		sizeof(u32));
585	BUG_ON(!gic->saved_ppi_enable);
586
587	gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4,
588		sizeof(u32));
589	BUG_ON(!gic->saved_ppi_conf);
590
591	if (gic == &gic_data[0])
592		cpu_pm_register_notifier(&gic_notifier_block);
593}
594#else
595static void __init gic_pm_init(struct gic_chip_data *gic)
596{
597}
598#endif
599
600static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
601				irq_hw_number_t hw)
602{
603	if (hw < 32) {
604		irq_set_percpu_devid(irq);
605		irq_set_chip_and_handler(irq, &gic_chip,
606					 handle_percpu_devid_irq);
607		set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN);
608	} else {
609		irq_set_chip_and_handler(irq, &gic_chip,
610					 handle_fasteoi_irq);
611		set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
612	}
613	irq_set_chip_data(irq, d->host_data);
614	return 0;
615}
616
617static int gic_irq_domain_xlate(struct irq_domain *d,
618				struct device_node *controller,
619				const u32 *intspec, unsigned int intsize,
620				unsigned long *out_hwirq, unsigned int *out_type)
621{
622	if (d->of_node != controller)
623		return -EINVAL;
624	if (intsize < 3)
625		return -EINVAL;
626
627	/* Get the interrupt number and add 16 to skip over SGIs */
628	*out_hwirq = intspec[1] + 16;
629
630	/* For SPIs, we need to add 16 more to get the GIC irq ID number */
631	if (!intspec[0])
632		*out_hwirq += 16;
633
634	*out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
635	return 0;
636}
637
638const struct irq_domain_ops gic_irq_domain_ops = {
639	.map = gic_irq_domain_map,
640	.xlate = gic_irq_domain_xlate,
641};
642
643void __init gic_init_bases(unsigned int gic_nr, int irq_start,
644			   void __iomem *dist_base, void __iomem *cpu_base,
645			   u32 percpu_offset, struct device_node *node)
646{
647	irq_hw_number_t hwirq_base;
648	struct gic_chip_data *gic;
649	int gic_irqs, irq_base;
650
651	BUG_ON(gic_nr >= MAX_GIC_NR);
652
653	gic = &gic_data[gic_nr];
654#ifdef CONFIG_GIC_NON_BANKED
655	if (percpu_offset) { /* Frankein-GIC without banked registers... */
656		unsigned int cpu;
657
658		gic->dist_base.percpu_base = alloc_percpu(void __iomem *);
659		gic->cpu_base.percpu_base = alloc_percpu(void __iomem *);
660		if (WARN_ON(!gic->dist_base.percpu_base ||
661			    !gic->cpu_base.percpu_base)) {
662			free_percpu(gic->dist_base.percpu_base);
663			free_percpu(gic->cpu_base.percpu_base);
664			return;
665		}
666
667		for_each_possible_cpu(cpu) {
668			unsigned long offset = percpu_offset * cpu_logical_map(cpu);
669			*per_cpu_ptr(gic->dist_base.percpu_base, cpu) = dist_base + offset;
670			*per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = cpu_base + offset;
671		}
672
673		gic_set_base_accessor(gic, gic_get_percpu_base);
674	} else
675#endif
676	{			/* Normal, sane GIC... */
677		WARN(percpu_offset,
678		     "GIC_NON_BANKED not enabled, ignoring %08x offset!",
679		     percpu_offset);
680		gic->dist_base.common_base = dist_base;
681		gic->cpu_base.common_base = cpu_base;
682		gic_set_base_accessor(gic, gic_get_common_base);
683	}
684
685	/*
686	 * For primary GICs, skip over SGIs.
687	 * For secondary GICs, skip over PPIs, too.
688	 */
689	if (gic_nr == 0 && (irq_start & 31) > 0) {
690		hwirq_base = 16;
691		if (irq_start != -1)
692			irq_start = (irq_start & ~31) + 16;
693	} else {
694		hwirq_base = 32;
695	}
696
697	/*
698	 * Find out how many interrupts are supported.
699	 * The GIC only supports up to 1020 interrupt sources.
700	 */
701	gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f;
702	gic_irqs = (gic_irqs + 1) * 32;
703	if (gic_irqs > 1020)
704		gic_irqs = 1020;
705	gic->gic_irqs = gic_irqs;
706
707	gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */
708	irq_base = irq_alloc_descs(irq_start, 16, gic_irqs, numa_node_id());
709	if (IS_ERR_VALUE(irq_base)) {
710		WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n",
711		     irq_start);
712		irq_base = irq_start;
713	}
714	gic->domain = irq_domain_add_legacy(node, gic_irqs, irq_base,
715				    hwirq_base, &gic_irq_domain_ops, gic);
716	if (WARN_ON(!gic->domain))
717		return;
718
719	gic_chip.flags |= gic_arch_extn.flags;
720	gic_dist_init(gic);
721	gic_cpu_init(gic);
722	gic_pm_init(gic);
723}
724
725void __cpuinit gic_secondary_init(unsigned int gic_nr)
726{
727	BUG_ON(gic_nr >= MAX_GIC_NR);
728
729	gic_cpu_init(&gic_data[gic_nr]);
730}
731
732#ifdef CONFIG_SMP
733void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
734{
735	int cpu;
736	unsigned long map = 0;
737
738	/* Convert our logical CPU mask into a physical one. */
739	for_each_cpu(cpu, mask)
740		map |= 1 << cpu_logical_map(cpu);
741
742	/*
743	 * Ensure that stores to Normal memory are visible to the
744	 * other CPUs before issuing the IPI.
745	 */
746	dsb();
747
748	/* this always happens on GIC0 */
749	writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
750}
751#endif
752
753#ifdef CONFIG_OF
754static int gic_cnt __initdata = 0;
755
756int __init gic_of_init(struct device_node *node, struct device_node *parent)
757{
758	void __iomem *cpu_base;
759	void __iomem *dist_base;
760	u32 percpu_offset;
761	int irq;
762
763	if (WARN_ON(!node))
764		return -ENODEV;
765
766	dist_base = of_iomap(node, 0);
767	WARN(!dist_base, "unable to map gic dist registers\n");
768
769	cpu_base = of_iomap(node, 1);
770	WARN(!cpu_base, "unable to map gic cpu registers\n");
771
772	if (of_property_read_u32(node, "cpu-offset", &percpu_offset))
773		percpu_offset = 0;
774
775	gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset, node);
776
777	if (parent) {
778		irq = irq_of_parse_and_map(node, 0);
779		gic_cascade_irq(gic_cnt, irq);
780	}
781	gic_cnt++;
782	return 0;
783}
784#endif