1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Samsung's Exynos4412 SoC device tree source
  4 *
  5 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
  6 *		http://www.samsung.com
  7 *
  8 * Samsung's Exynos4412 SoC device nodes are listed in this file. Exynos4412
  9 * based board files can include this file and provide values for board specific
 10 * bindings.
 11 *
 12 * Note: This file does not include device nodes for all the controllers in
 13 * Exynos4412 SoC. As device tree coverage for Exynos4412 increases, additional
 14 * nodes can be added to this file.
 15 */
 16
 17#include "exynos4x12.dtsi"
 18
 19/ {
 20	compatible = "samsung,exynos4412", "samsung,exynos4";
 21
 22	cpus {
 23		#address-cells = <1>;
 24		#size-cells = <0>;
 25
 26		cpu-map {
 27			cluster0 {
 28				core0 {
 29					cpu = <&cpu0>;
 30				};
 31				core1 {
 32					cpu = <&cpu1>;
 33				};
 34				core2 {
 35					cpu = <&cpu2>;
 36				};
 37				core3 {
 38					cpu = <&cpu3>;
 39				};
 40			};
 41		};
 42
 43		cpu0: cpu@a00 {
 44			device_type = "cpu";
 45			compatible = "arm,cortex-a9";
 46			reg = <0xa00>;
 47			clocks = <&clock CLK_ARM_CLK>;
 48			clock-names = "cpu";
 49			operating-points-v2 = <&cpu0_opp_table>;
 50			#cooling-cells = <2>; /* min followed by max */
 51		};
 52
 53		cpu1: cpu@a01 {
 54			device_type = "cpu";
 55			compatible = "arm,cortex-a9";
 56			reg = <0xa01>;
 57			clocks = <&clock CLK_ARM_CLK>;
 58			clock-names = "cpu";
 59			operating-points-v2 = <&cpu0_opp_table>;
 60			#cooling-cells = <2>; /* min followed by max */
 61		};
 62
 63		cpu2: cpu@a02 {
 64			device_type = "cpu";
 65			compatible = "arm,cortex-a9";
 66			reg = <0xa02>;
 67			clocks = <&clock CLK_ARM_CLK>;
 68			clock-names = "cpu";
 69			operating-points-v2 = <&cpu0_opp_table>;
 70			#cooling-cells = <2>; /* min followed by max */
 71		};
 72
 73		cpu3: cpu@a03 {
 74			device_type = "cpu";
 75			compatible = "arm,cortex-a9";
 76			reg = <0xa03>;
 77			clocks = <&clock CLK_ARM_CLK>;
 78			clock-names = "cpu";
 79			operating-points-v2 = <&cpu0_opp_table>;
 80			#cooling-cells = <2>; /* min followed by max */
 81		};
 82	};
 83
 84	cpu0_opp_table: opp-table-0 {
 85		compatible = "operating-points-v2";
 86		opp-shared;
 87
 88		opp-200000000 {
 89			opp-hz = /bits/ 64 <200000000>;
 90			opp-microvolt = <900000>;
 91			clock-latency-ns = <200000>;
 92		};
 93		opp-300000000 {
 94			opp-hz = /bits/ 64 <300000000>;
 95			opp-microvolt = <900000>;
 96			clock-latency-ns = <200000>;
 97		};
 98		opp-400000000 {
 99			opp-hz = /bits/ 64 <400000000>;
100			opp-microvolt = <925000>;
101			clock-latency-ns = <200000>;
102		};
103		opp-500000000 {
104			opp-hz = /bits/ 64 <500000000>;
105			opp-microvolt = <950000>;
106			clock-latency-ns = <200000>;
107		};
108		opp-600000000 {
109			opp-hz = /bits/ 64 <600000000>;
110			opp-microvolt = <975000>;
111			clock-latency-ns = <200000>;
112		};
113		opp-700000000 {
114			opp-hz = /bits/ 64 <700000000>;
115			opp-microvolt = <987500>;
116			clock-latency-ns = <200000>;
117		};
118		opp-800000000 {
119			opp-hz = /bits/ 64 <800000000>;
120			opp-microvolt = <1000000>;
121			clock-latency-ns = <200000>;
122			opp-suspend;
123		};
124		opp-900000000 {
125			opp-hz = /bits/ 64 <900000000>;
126			opp-microvolt = <1037500>;
127			clock-latency-ns = <200000>;
128		};
129		opp-1000000000 {
130			opp-hz = /bits/ 64 <1000000000>;
131			opp-microvolt = <1087500>;
132			clock-latency-ns = <200000>;
133		};
134		opp-1100000000 {
135			opp-hz = /bits/ 64 <1100000000>;
136			opp-microvolt = <1137500>;
137			clock-latency-ns = <200000>;
138		};
139		opp-1200000000 {
140			opp-hz = /bits/ 64 <1200000000>;
141			opp-microvolt = <1187500>;
142			clock-latency-ns = <200000>;
143		};
144		opp-1300000000 {
145			opp-hz = /bits/ 64 <1300000000>;
146			opp-microvolt = <1250000>;
147			clock-latency-ns = <200000>;
148		};
149		opp-1400000000 {
150			opp-hz = /bits/ 64 <1400000000>;
151			opp-microvolt = <1287500>;
152			clock-latency-ns = <200000>;
153		};
154		cpu0_opp_1500: opp-1500000000 {
155			opp-hz = /bits/ 64 <1500000000>;
156			opp-microvolt = <1350000>;
157			clock-latency-ns = <200000>;
158			turbo-mode;
159		};
160	};
161};
162
163&clock {
164	compatible = "samsung,exynos4412-clock";
165};
166
167&combiner {
168	samsung,combiner-nr = <20>;
169};
170
171&gic {
172	cpu-offset = <0x4000>;
173};
174
175&pmu {
176	interrupts = <2 2>, <3 2>, <18 2>, <19 2>;
177	interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
178	status = "okay";
179};
180
181&pmu_system_controller {
182	compatible = "samsung,exynos4412-pmu", "simple-mfd", "syscon";
183};