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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Socionext SPI flash controller F_OSPI driver
4 * Copyright (C) 2021 Socionext Inc.
5 */
6
7#include <linux/bitfield.h>
8#include <linux/clk.h>
9#include <linux/io.h>
10#include <linux/iopoll.h>
11#include <linux/module.h>
12#include <linux/mutex.h>
13#include <linux/of.h>
14#include <linux/platform_device.h>
15#include <linux/spi/spi.h>
16#include <linux/spi/spi-mem.h>
17
18/* Registers */
19#define OSPI_PROT_CTL_INDIR 0x00
20#define OSPI_PROT_MODE_DATA_MASK GENMASK(31, 30)
21#define OSPI_PROT_MODE_ALT_MASK GENMASK(29, 28)
22#define OSPI_PROT_MODE_ADDR_MASK GENMASK(27, 26)
23#define OSPI_PROT_MODE_CODE_MASK GENMASK(25, 24)
24#define OSPI_PROT_MODE_SINGLE 0
25#define OSPI_PROT_MODE_DUAL 1
26#define OSPI_PROT_MODE_QUAD 2
27#define OSPI_PROT_MODE_OCTAL 3
28#define OSPI_PROT_DATA_RATE_DATA BIT(23)
29#define OSPI_PROT_DATA_RATE_ALT BIT(22)
30#define OSPI_PROT_DATA_RATE_ADDR BIT(21)
31#define OSPI_PROT_DATA_RATE_CODE BIT(20)
32#define OSPI_PROT_SDR 0
33#define OSPI_PROT_DDR 1
34#define OSPI_PROT_BIT_POS_DATA BIT(19)
35#define OSPI_PROT_BIT_POS_ALT BIT(18)
36#define OSPI_PROT_BIT_POS_ADDR BIT(17)
37#define OSPI_PROT_BIT_POS_CODE BIT(16)
38#define OSPI_PROT_SAMP_EDGE BIT(12)
39#define OSPI_PROT_DATA_UNIT_MASK GENMASK(11, 10)
40#define OSPI_PROT_DATA_UNIT_1B 0
41#define OSPI_PROT_DATA_UNIT_2B 1
42#define OSPI_PROT_DATA_UNIT_4B 3
43#define OSPI_PROT_TRANS_DIR_WRITE BIT(9)
44#define OSPI_PROT_DATA_EN BIT(8)
45#define OSPI_PROT_ALT_SIZE_MASK GENMASK(7, 5)
46#define OSPI_PROT_ADDR_SIZE_MASK GENMASK(4, 2)
47#define OSPI_PROT_CODE_SIZE_MASK GENMASK(1, 0)
48
49#define OSPI_CLK_CTL 0x10
50#define OSPI_CLK_CTL_BOOT_INT_CLK_EN BIT(16)
51#define OSPI_CLK_CTL_PHA BIT(12)
52#define OSPI_CLK_CTL_PHA_180 0
53#define OSPI_CLK_CTL_PHA_90 1
54#define OSPI_CLK_CTL_DIV GENMASK(9, 8)
55#define OSPI_CLK_CTL_DIV_1 0
56#define OSPI_CLK_CTL_DIV_2 1
57#define OSPI_CLK_CTL_DIV_4 2
58#define OSPI_CLK_CTL_DIV_8 3
59#define OSPI_CLK_CTL_INT_CLK_EN BIT(0)
60
61#define OSPI_CS_CTL1 0x14
62#define OSPI_CS_CTL2 0x18
63#define OSPI_SSEL 0x20
64#define OSPI_CMD_IDX_INDIR 0x40
65#define OSPI_ADDR 0x50
66#define OSPI_ALT_INDIR 0x60
67#define OSPI_DMY_INDIR 0x70
68#define OSPI_DAT 0x80
69#define OSPI_DAT_SWP_INDIR 0x90
70
71#define OSPI_DAT_SIZE_INDIR 0xA0
72#define OSPI_DAT_SIZE_EN BIT(15)
73#define OSPI_DAT_SIZE_MASK GENMASK(10, 0)
74#define OSPI_DAT_SIZE_MAX (OSPI_DAT_SIZE_MASK + 1)
75
76#define OSPI_TRANS_CTL 0xC0
77#define OSPI_TRANS_CTL_STOP_REQ BIT(1) /* RW1AC */
78#define OSPI_TRANS_CTL_START_REQ BIT(0) /* RW1AC */
79
80#define OSPI_ACC_MODE 0xC4
81#define OSPI_ACC_MODE_BOOT_DISABLE BIT(0)
82
83#define OSPI_SWRST 0xD0
84#define OSPI_SWRST_INDIR_WRITE_FIFO BIT(9) /* RW1AC */
85#define OSPI_SWRST_INDIR_READ_FIFO BIT(8) /* RW1AC */
86
87#define OSPI_STAT 0xE0
88#define OSPI_STAT_IS_AXI_WRITING BIT(10)
89#define OSPI_STAT_IS_AXI_READING BIT(9)
90#define OSPI_STAT_IS_SPI_INT_CLK_STOP BIT(4)
91#define OSPI_STAT_IS_SPI_IDLE BIT(3)
92
93#define OSPI_IRQ 0xF0
94#define OSPI_IRQ_CS_DEASSERT BIT(8)
95#define OSPI_IRQ_WRITE_BUF_READY BIT(2)
96#define OSPI_IRQ_READ_BUF_READY BIT(1)
97#define OSPI_IRQ_CS_TRANS_COMP BIT(0)
98#define OSPI_IRQ_ALL \
99 (OSPI_IRQ_CS_DEASSERT | OSPI_IRQ_WRITE_BUF_READY \
100 | OSPI_IRQ_READ_BUF_READY | OSPI_IRQ_CS_TRANS_COMP)
101
102#define OSPI_IRQ_STAT_EN 0xF4
103#define OSPI_IRQ_SIG_EN 0xF8
104
105/* Parameters */
106#define OSPI_NUM_CS 4
107#define OSPI_DUMMY_CYCLE_MAX 255
108#define OSPI_WAIT_MAX_MSEC 100
109
110struct f_ospi {
111 void __iomem *base;
112 struct device *dev;
113 struct clk *clk;
114 struct mutex mlock;
115};
116
117static u32 f_ospi_get_dummy_cycle(const struct spi_mem_op *op)
118{
119 if (!op->dummy.nbytes)
120 return 0;
121
122 return (op->dummy.nbytes * 8) / op->dummy.buswidth;
123}
124
125static void f_ospi_clear_irq(struct f_ospi *ospi)
126{
127 writel(OSPI_IRQ_CS_DEASSERT | OSPI_IRQ_CS_TRANS_COMP,
128 ospi->base + OSPI_IRQ);
129}
130
131static void f_ospi_enable_irq_status(struct f_ospi *ospi, u32 irq_bits)
132{
133 u32 val;
134
135 val = readl(ospi->base + OSPI_IRQ_STAT_EN);
136 val |= irq_bits;
137 writel(val, ospi->base + OSPI_IRQ_STAT_EN);
138}
139
140static void f_ospi_disable_irq_status(struct f_ospi *ospi, u32 irq_bits)
141{
142 u32 val;
143
144 val = readl(ospi->base + OSPI_IRQ_STAT_EN);
145 val &= ~irq_bits;
146 writel(val, ospi->base + OSPI_IRQ_STAT_EN);
147}
148
149static void f_ospi_disable_irq_output(struct f_ospi *ospi, u32 irq_bits)
150{
151 u32 val;
152
153 val = readl(ospi->base + OSPI_IRQ_SIG_EN);
154 val &= ~irq_bits;
155 writel(val, ospi->base + OSPI_IRQ_SIG_EN);
156}
157
158static int f_ospi_prepare_config(struct f_ospi *ospi)
159{
160 u32 val, stat0, stat1;
161
162 /* G4: Disable internal clock */
163 val = readl(ospi->base + OSPI_CLK_CTL);
164 val &= ~(OSPI_CLK_CTL_BOOT_INT_CLK_EN | OSPI_CLK_CTL_INT_CLK_EN);
165 writel(val, ospi->base + OSPI_CLK_CTL);
166
167 /* G5: Wait for stop */
168 stat0 = OSPI_STAT_IS_AXI_WRITING | OSPI_STAT_IS_AXI_READING;
169 stat1 = OSPI_STAT_IS_SPI_IDLE | OSPI_STAT_IS_SPI_INT_CLK_STOP;
170
171 return readl_poll_timeout(ospi->base + OSPI_STAT,
172 val, (val & (stat0 | stat1)) == stat1,
173 0, OSPI_WAIT_MAX_MSEC);
174}
175
176static int f_ospi_unprepare_config(struct f_ospi *ospi)
177{
178 u32 val;
179
180 /* G11: Enable internal clock */
181 val = readl(ospi->base + OSPI_CLK_CTL);
182 val |= OSPI_CLK_CTL_BOOT_INT_CLK_EN | OSPI_CLK_CTL_INT_CLK_EN;
183 writel(val, ospi->base + OSPI_CLK_CTL);
184
185 /* G12: Wait for clock to start */
186 return readl_poll_timeout(ospi->base + OSPI_STAT,
187 val, !(val & OSPI_STAT_IS_SPI_INT_CLK_STOP),
188 0, OSPI_WAIT_MAX_MSEC);
189}
190
191static void f_ospi_config_clk(struct f_ospi *ospi, u32 device_hz)
192{
193 long rate_hz = clk_get_rate(ospi->clk);
194 u32 div = DIV_ROUND_UP(rate_hz, device_hz);
195 u32 div_reg;
196 u32 val;
197
198 if (rate_hz < device_hz) {
199 dev_warn(ospi->dev, "Device frequency too large: %d\n",
200 device_hz);
201 div_reg = OSPI_CLK_CTL_DIV_1;
202 } else {
203 if (div == 1) {
204 div_reg = OSPI_CLK_CTL_DIV_1;
205 } else if (div == 2) {
206 div_reg = OSPI_CLK_CTL_DIV_2;
207 } else if (div <= 4) {
208 div_reg = OSPI_CLK_CTL_DIV_4;
209 } else if (div <= 8) {
210 div_reg = OSPI_CLK_CTL_DIV_8;
211 } else {
212 dev_warn(ospi->dev, "Device frequency too small: %d\n",
213 device_hz);
214 div_reg = OSPI_CLK_CTL_DIV_8;
215 }
216 }
217
218 /*
219 * G7: Set clock mode
220 * clock phase is fixed at 180 degrees and configure edge direction
221 * instead.
222 */
223 val = readl(ospi->base + OSPI_CLK_CTL);
224
225 val &= ~(OSPI_CLK_CTL_PHA | OSPI_CLK_CTL_DIV);
226 val |= FIELD_PREP(OSPI_CLK_CTL_PHA, OSPI_CLK_CTL_PHA_180)
227 | FIELD_PREP(OSPI_CLK_CTL_DIV, div_reg);
228
229 writel(val, ospi->base + OSPI_CLK_CTL);
230}
231
232static void f_ospi_config_dll(struct f_ospi *ospi)
233{
234 /* G8: Configure DLL, nothing */
235}
236
237static u8 f_ospi_get_mode(struct f_ospi *ospi, int width, int data_size)
238{
239 u8 mode = OSPI_PROT_MODE_SINGLE;
240
241 switch (width) {
242 case 1:
243 mode = OSPI_PROT_MODE_SINGLE;
244 break;
245 case 2:
246 mode = OSPI_PROT_MODE_DUAL;
247 break;
248 case 4:
249 mode = OSPI_PROT_MODE_QUAD;
250 break;
251 case 8:
252 mode = OSPI_PROT_MODE_OCTAL;
253 break;
254 default:
255 if (data_size)
256 dev_err(ospi->dev, "Invalid buswidth: %d\n", width);
257 break;
258 }
259
260 return mode;
261}
262
263static void f_ospi_config_indir_protocol(struct f_ospi *ospi,
264 struct spi_mem *mem,
265 const struct spi_mem_op *op)
266{
267 struct spi_device *spi = mem->spi;
268 u8 mode;
269 u32 prot = 0, val;
270 int unit;
271
272 /* Set one chip select */
273 writel(BIT(spi_get_chipselect(spi, 0)), ospi->base + OSPI_SSEL);
274
275 mode = f_ospi_get_mode(ospi, op->cmd.buswidth, 1);
276 prot |= FIELD_PREP(OSPI_PROT_MODE_CODE_MASK, mode);
277
278 mode = f_ospi_get_mode(ospi, op->addr.buswidth, op->addr.nbytes);
279 prot |= FIELD_PREP(OSPI_PROT_MODE_ADDR_MASK, mode);
280
281 mode = f_ospi_get_mode(ospi, op->data.buswidth, op->data.nbytes);
282 prot |= FIELD_PREP(OSPI_PROT_MODE_DATA_MASK, mode);
283
284 prot |= FIELD_PREP(OSPI_PROT_DATA_RATE_DATA, OSPI_PROT_SDR);
285 prot |= FIELD_PREP(OSPI_PROT_DATA_RATE_ALT, OSPI_PROT_SDR);
286 prot |= FIELD_PREP(OSPI_PROT_DATA_RATE_ADDR, OSPI_PROT_SDR);
287 prot |= FIELD_PREP(OSPI_PROT_DATA_RATE_CODE, OSPI_PROT_SDR);
288
289 if (spi->mode & SPI_LSB_FIRST)
290 prot |= OSPI_PROT_BIT_POS_DATA | OSPI_PROT_BIT_POS_ALT
291 | OSPI_PROT_BIT_POS_ADDR | OSPI_PROT_BIT_POS_CODE;
292
293 if (spi->mode & SPI_CPHA)
294 prot |= OSPI_PROT_SAMP_EDGE;
295
296 /* Examine nbytes % 4 */
297 switch (op->data.nbytes & 0x3) {
298 case 0:
299 unit = OSPI_PROT_DATA_UNIT_4B;
300 val = 0;
301 break;
302 case 2:
303 unit = OSPI_PROT_DATA_UNIT_2B;
304 val = OSPI_DAT_SIZE_EN | (op->data.nbytes - 1);
305 break;
306 default:
307 unit = OSPI_PROT_DATA_UNIT_1B;
308 val = OSPI_DAT_SIZE_EN | (op->data.nbytes - 1);
309 break;
310 }
311 prot |= FIELD_PREP(OSPI_PROT_DATA_UNIT_MASK, unit);
312
313 switch (op->data.dir) {
314 case SPI_MEM_DATA_IN:
315 prot |= OSPI_PROT_DATA_EN;
316 break;
317
318 case SPI_MEM_DATA_OUT:
319 prot |= OSPI_PROT_TRANS_DIR_WRITE | OSPI_PROT_DATA_EN;
320 break;
321
322 case SPI_MEM_NO_DATA:
323 prot |= OSPI_PROT_TRANS_DIR_WRITE;
324 break;
325
326 default:
327 dev_warn(ospi->dev, "Unsupported direction");
328 break;
329 }
330
331 prot |= FIELD_PREP(OSPI_PROT_ADDR_SIZE_MASK, op->addr.nbytes);
332 prot |= FIELD_PREP(OSPI_PROT_CODE_SIZE_MASK, 1); /* 1byte */
333
334 writel(prot, ospi->base + OSPI_PROT_CTL_INDIR);
335 writel(val, ospi->base + OSPI_DAT_SIZE_INDIR);
336}
337
338static int f_ospi_indir_prepare_op(struct f_ospi *ospi, struct spi_mem *mem,
339 const struct spi_mem_op *op)
340{
341 struct spi_device *spi = mem->spi;
342 u32 irq_stat_en;
343 int ret;
344
345 ret = f_ospi_prepare_config(ospi);
346 if (ret)
347 return ret;
348
349 f_ospi_config_clk(ospi, spi->max_speed_hz);
350
351 f_ospi_config_indir_protocol(ospi, mem, op);
352
353 writel(f_ospi_get_dummy_cycle(op), ospi->base + OSPI_DMY_INDIR);
354 writel(op->addr.val, ospi->base + OSPI_ADDR);
355 writel(op->cmd.opcode, ospi->base + OSPI_CMD_IDX_INDIR);
356
357 f_ospi_clear_irq(ospi);
358
359 switch (op->data.dir) {
360 case SPI_MEM_DATA_IN:
361 irq_stat_en = OSPI_IRQ_READ_BUF_READY | OSPI_IRQ_CS_TRANS_COMP;
362 break;
363
364 case SPI_MEM_DATA_OUT:
365 irq_stat_en = OSPI_IRQ_WRITE_BUF_READY | OSPI_IRQ_CS_TRANS_COMP;
366 break;
367
368 case SPI_MEM_NO_DATA:
369 irq_stat_en = OSPI_IRQ_CS_TRANS_COMP;
370 break;
371
372 default:
373 dev_warn(ospi->dev, "Unsupported direction");
374 irq_stat_en = 0;
375 }
376
377 f_ospi_disable_irq_status(ospi, ~irq_stat_en);
378 f_ospi_enable_irq_status(ospi, irq_stat_en);
379
380 return f_ospi_unprepare_config(ospi);
381}
382
383static void f_ospi_indir_start_xfer(struct f_ospi *ospi)
384{
385 /* Write only 1, auto cleared */
386 writel(OSPI_TRANS_CTL_START_REQ, ospi->base + OSPI_TRANS_CTL);
387}
388
389static void f_ospi_indir_stop_xfer(struct f_ospi *ospi)
390{
391 /* Write only 1, auto cleared */
392 writel(OSPI_TRANS_CTL_STOP_REQ, ospi->base + OSPI_TRANS_CTL);
393}
394
395static int f_ospi_indir_wait_xfer_complete(struct f_ospi *ospi)
396{
397 u32 val;
398
399 return readl_poll_timeout(ospi->base + OSPI_IRQ, val,
400 val & OSPI_IRQ_CS_TRANS_COMP,
401 0, OSPI_WAIT_MAX_MSEC);
402}
403
404static int f_ospi_indir_read(struct f_ospi *ospi, struct spi_mem *mem,
405 const struct spi_mem_op *op)
406{
407 u8 *buf = op->data.buf.in;
408 u32 val;
409 int i, ret;
410
411 mutex_lock(&ospi->mlock);
412
413 /* E1-2: Prepare transfer operation */
414 ret = f_ospi_indir_prepare_op(ospi, mem, op);
415 if (ret)
416 goto out;
417
418 f_ospi_indir_start_xfer(ospi);
419
420 /* E3-4: Wait for ready and read data */
421 for (i = 0; i < op->data.nbytes; i++) {
422 ret = readl_poll_timeout(ospi->base + OSPI_IRQ, val,
423 val & OSPI_IRQ_READ_BUF_READY,
424 0, OSPI_WAIT_MAX_MSEC);
425 if (ret)
426 goto out;
427
428 buf[i] = readl(ospi->base + OSPI_DAT) & 0xFF;
429 }
430
431 /* E5-6: Stop transfer if data size is nothing */
432 if (!(readl(ospi->base + OSPI_DAT_SIZE_INDIR) & OSPI_DAT_SIZE_EN))
433 f_ospi_indir_stop_xfer(ospi);
434
435 /* E7-8: Wait for completion and clear */
436 ret = f_ospi_indir_wait_xfer_complete(ospi);
437 if (ret)
438 goto out;
439
440 writel(OSPI_IRQ_CS_TRANS_COMP, ospi->base + OSPI_IRQ);
441
442 /* E9: Do nothing if data size is valid */
443 if (readl(ospi->base + OSPI_DAT_SIZE_INDIR) & OSPI_DAT_SIZE_EN)
444 goto out;
445
446 /* E10-11: Reset and check read fifo */
447 writel(OSPI_SWRST_INDIR_READ_FIFO, ospi->base + OSPI_SWRST);
448
449 ret = readl_poll_timeout(ospi->base + OSPI_SWRST, val,
450 !(val & OSPI_SWRST_INDIR_READ_FIFO),
451 0, OSPI_WAIT_MAX_MSEC);
452out:
453 mutex_unlock(&ospi->mlock);
454
455 return ret;
456}
457
458static int f_ospi_indir_write(struct f_ospi *ospi, struct spi_mem *mem,
459 const struct spi_mem_op *op)
460{
461 u8 *buf = (u8 *)op->data.buf.out;
462 u32 val;
463 int i, ret;
464
465 mutex_lock(&ospi->mlock);
466
467 /* F1-3: Prepare transfer operation */
468 ret = f_ospi_indir_prepare_op(ospi, mem, op);
469 if (ret)
470 goto out;
471
472 f_ospi_indir_start_xfer(ospi);
473
474 if (!(readl(ospi->base + OSPI_PROT_CTL_INDIR) & OSPI_PROT_DATA_EN))
475 goto nodata;
476
477 /* F4-5: Wait for buffer ready and write data */
478 for (i = 0; i < op->data.nbytes; i++) {
479 ret = readl_poll_timeout(ospi->base + OSPI_IRQ, val,
480 val & OSPI_IRQ_WRITE_BUF_READY,
481 0, OSPI_WAIT_MAX_MSEC);
482 if (ret)
483 goto out;
484
485 writel(buf[i], ospi->base + OSPI_DAT);
486 }
487
488 /* F6-7: Stop transfer if data size is nothing */
489 if (!(readl(ospi->base + OSPI_DAT_SIZE_INDIR) & OSPI_DAT_SIZE_EN))
490 f_ospi_indir_stop_xfer(ospi);
491
492nodata:
493 /* F8-9: Wait for completion and clear */
494 ret = f_ospi_indir_wait_xfer_complete(ospi);
495 if (ret)
496 goto out;
497
498 writel(OSPI_IRQ_CS_TRANS_COMP, ospi->base + OSPI_IRQ);
499out:
500 mutex_unlock(&ospi->mlock);
501
502 return ret;
503}
504
505static int f_ospi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
506{
507 struct f_ospi *ospi = spi_controller_get_devdata(mem->spi->controller);
508 int err = 0;
509
510 switch (op->data.dir) {
511 case SPI_MEM_DATA_IN:
512 err = f_ospi_indir_read(ospi, mem, op);
513 break;
514
515 case SPI_MEM_DATA_OUT:
516 fallthrough;
517 case SPI_MEM_NO_DATA:
518 err = f_ospi_indir_write(ospi, mem, op);
519 break;
520
521 default:
522 dev_warn(ospi->dev, "Unsupported direction");
523 err = -EOPNOTSUPP;
524 }
525
526 return err;
527}
528
529static bool f_ospi_supports_op_width(struct spi_mem *mem,
530 const struct spi_mem_op *op)
531{
532 static const u8 width_available[] = { 0, 1, 2, 4, 8 };
533 u8 width_op[] = { op->cmd.buswidth, op->addr.buswidth,
534 op->dummy.buswidth, op->data.buswidth };
535 bool is_match_found;
536 int i, j;
537
538 for (i = 0; i < ARRAY_SIZE(width_op); i++) {
539 is_match_found = false;
540
541 for (j = 0; j < ARRAY_SIZE(width_available); j++) {
542 if (width_op[i] == width_available[j]) {
543 is_match_found = true;
544 break;
545 }
546 }
547
548 if (!is_match_found)
549 return false;
550 }
551
552 return true;
553}
554
555static bool f_ospi_supports_op(struct spi_mem *mem,
556 const struct spi_mem_op *op)
557{
558 if (f_ospi_get_dummy_cycle(op) > OSPI_DUMMY_CYCLE_MAX)
559 return false;
560
561 if (op->addr.nbytes > 4)
562 return false;
563
564 if (!f_ospi_supports_op_width(mem, op))
565 return false;
566
567 return spi_mem_default_supports_op(mem, op);
568}
569
570static int f_ospi_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op)
571{
572 op->data.nbytes = min_t(int, op->data.nbytes, OSPI_DAT_SIZE_MAX);
573
574 return 0;
575}
576
577static const struct spi_controller_mem_ops f_ospi_mem_ops = {
578 .adjust_op_size = f_ospi_adjust_op_size,
579 .supports_op = f_ospi_supports_op,
580 .exec_op = f_ospi_exec_op,
581};
582
583static int f_ospi_init(struct f_ospi *ospi)
584{
585 int ret;
586
587 ret = f_ospi_prepare_config(ospi);
588 if (ret)
589 return ret;
590
591 /* Disable boot signal */
592 writel(OSPI_ACC_MODE_BOOT_DISABLE, ospi->base + OSPI_ACC_MODE);
593
594 f_ospi_config_dll(ospi);
595
596 /* Disable IRQ */
597 f_ospi_clear_irq(ospi);
598 f_ospi_disable_irq_status(ospi, OSPI_IRQ_ALL);
599 f_ospi_disable_irq_output(ospi, OSPI_IRQ_ALL);
600
601 return f_ospi_unprepare_config(ospi);
602}
603
604static int f_ospi_probe(struct platform_device *pdev)
605{
606 struct spi_controller *ctlr;
607 struct device *dev = &pdev->dev;
608 struct f_ospi *ospi;
609 u32 num_cs = OSPI_NUM_CS;
610 int ret;
611
612 ctlr = spi_alloc_host(dev, sizeof(*ospi));
613 if (!ctlr)
614 return -ENOMEM;
615
616 ctlr->mode_bits = SPI_TX_DUAL | SPI_TX_QUAD | SPI_TX_OCTAL
617 | SPI_RX_DUAL | SPI_RX_QUAD | SPI_RX_OCTAL
618 | SPI_MODE_0 | SPI_MODE_1 | SPI_LSB_FIRST;
619 ctlr->mem_ops = &f_ospi_mem_ops;
620 ctlr->bus_num = -1;
621 of_property_read_u32(dev->of_node, "num-cs", &num_cs);
622 if (num_cs > OSPI_NUM_CS) {
623 dev_err(dev, "num-cs too large: %d\n", num_cs);
624 return -ENOMEM;
625 }
626 ctlr->num_chipselect = num_cs;
627 ctlr->dev.of_node = dev->of_node;
628
629 ospi = spi_controller_get_devdata(ctlr);
630 ospi->dev = dev;
631
632 platform_set_drvdata(pdev, ospi);
633
634 ospi->base = devm_platform_ioremap_resource(pdev, 0);
635 if (IS_ERR(ospi->base)) {
636 ret = PTR_ERR(ospi->base);
637 goto err_put_ctlr;
638 }
639
640 ospi->clk = devm_clk_get_enabled(dev, NULL);
641 if (IS_ERR(ospi->clk)) {
642 ret = PTR_ERR(ospi->clk);
643 goto err_put_ctlr;
644 }
645
646 mutex_init(&ospi->mlock);
647
648 ret = f_ospi_init(ospi);
649 if (ret)
650 goto err_destroy_mutex;
651
652 ret = devm_spi_register_controller(dev, ctlr);
653 if (ret)
654 goto err_destroy_mutex;
655
656 return 0;
657
658err_destroy_mutex:
659 mutex_destroy(&ospi->mlock);
660
661err_put_ctlr:
662 spi_controller_put(ctlr);
663
664 return ret;
665}
666
667static void f_ospi_remove(struct platform_device *pdev)
668{
669 struct f_ospi *ospi = platform_get_drvdata(pdev);
670
671 mutex_destroy(&ospi->mlock);
672}
673
674static const struct of_device_id f_ospi_dt_ids[] = {
675 { .compatible = "socionext,f-ospi" },
676 {}
677};
678MODULE_DEVICE_TABLE(of, f_ospi_dt_ids);
679
680static struct platform_driver f_ospi_driver = {
681 .driver = {
682 .name = "socionext,f-ospi",
683 .of_match_table = f_ospi_dt_ids,
684 },
685 .probe = f_ospi_probe,
686 .remove = f_ospi_remove,
687};
688module_platform_driver(f_ospi_driver);
689
690MODULE_DESCRIPTION("Socionext F_OSPI controller driver");
691MODULE_AUTHOR("Socionext Inc.");
692MODULE_AUTHOR("Kunihiko Hayashi <hayashi.kunihiko@socionext.com>");
693MODULE_LICENSE("GPL");