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1/*
2 * AMD 10Gb Ethernet driver
3 *
4 * This file is available to you under your choice of the following two
5 * licenses:
6 *
7 * License 1: GPLv2
8 *
9 * Copyright (c) 2016 Advanced Micro Devices, Inc.
10 *
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 *
24 * This file incorporates work covered by the following copyright and
25 * permission notice:
26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28 * Inc. unless otherwise expressly agreed to in writing between Synopsys
29 * and you.
30 *
31 * The Software IS NOT an item of Licensed Software or Licensed Product
32 * under any End User Software License Agreement or Agreement for Licensed
33 * Product with Synopsys or any supplement thereto. Permission is hereby
34 * granted, free of charge, to any person obtaining a copy of this software
35 * annotated with this license and the Software, to deal in the Software
36 * without restriction, including without limitation the rights to use,
37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38 * of the Software, and to permit persons to whom the Software is furnished
39 * to do so, subject to the following conditions:
40 *
41 * The above copyright notice and this permission notice shall be included
42 * in all copies or substantial portions of the Software.
43 *
44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54 * THE POSSIBILITY OF SUCH DAMAGE.
55 *
56 *
57 * License 2: Modified BSD
58 *
59 * Copyright (c) 2016 Advanced Micro Devices, Inc.
60 * All rights reserved.
61 *
62 * Redistribution and use in source and binary forms, with or without
63 * modification, are permitted provided that the following conditions are met:
64 * * Redistributions of source code must retain the above copyright
65 * notice, this list of conditions and the following disclaimer.
66 * * Redistributions in binary form must reproduce the above copyright
67 * notice, this list of conditions and the following disclaimer in the
68 * documentation and/or other materials provided with the distribution.
69 * * Neither the name of Advanced Micro Devices, Inc. nor the
70 * names of its contributors may be used to endorse or promote products
71 * derived from this software without specific prior written permission.
72 *
73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
83 *
84 * This file incorporates work covered by the following copyright and
85 * permission notice:
86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
88 * Inc. unless otherwise expressly agreed to in writing between Synopsys
89 * and you.
90 *
91 * The Software IS NOT an item of Licensed Software or Licensed Product
92 * under any End User Software License Agreement or Agreement for Licensed
93 * Product with Synopsys or any supplement thereto. Permission is hereby
94 * granted, free of charge, to any person obtaining a copy of this software
95 * annotated with this license and the Software, to deal in the Software
96 * without restriction, including without limitation the rights to use,
97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
98 * of the Software, and to permit persons to whom the Software is furnished
99 * to do so, subject to the following conditions:
100 *
101 * The above copyright notice and this permission notice shall be included
102 * in all copies or substantial portions of the Software.
103 *
104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
114 * THE POSSIBILITY OF SUCH DAMAGE.
115 */
116
117#include <linux/module.h>
118#include <linux/device.h>
119#include <linux/kmod.h>
120#include <linux/mdio.h>
121#include <linux/phy.h>
122#include <linux/ethtool.h>
123
124#include "xgbe.h"
125#include "xgbe-common.h"
126
127#define XGBE_PHY_PORT_SPEED_10 BIT(0)
128#define XGBE_PHY_PORT_SPEED_100 BIT(1)
129#define XGBE_PHY_PORT_SPEED_1000 BIT(2)
130#define XGBE_PHY_PORT_SPEED_2500 BIT(3)
131#define XGBE_PHY_PORT_SPEED_10000 BIT(4)
132
133#define XGBE_MUTEX_RELEASE 0x80000000
134
135#define XGBE_SFP_DIRECT 7
136
137/* I2C target addresses */
138#define XGBE_SFP_SERIAL_ID_ADDRESS 0x50
139#define XGBE_SFP_DIAG_INFO_ADDRESS 0x51
140#define XGBE_SFP_PHY_ADDRESS 0x56
141#define XGBE_GPIO_ADDRESS_PCA9555 0x20
142
143/* SFP sideband signal indicators */
144#define XGBE_GPIO_NO_TX_FAULT BIT(0)
145#define XGBE_GPIO_NO_RATE_SELECT BIT(1)
146#define XGBE_GPIO_NO_MOD_ABSENT BIT(2)
147#define XGBE_GPIO_NO_RX_LOS BIT(3)
148
149/* Rate-change complete wait/retry count */
150#define XGBE_RATECHANGE_COUNT 500
151
152/* CDR delay values for KR support (in usec) */
153#define XGBE_CDR_DELAY_INIT 10000
154#define XGBE_CDR_DELAY_INC 10000
155#define XGBE_CDR_DELAY_MAX 100000
156
157/* RRC frequency during link status check */
158#define XGBE_RRC_FREQUENCY 10
159
160enum xgbe_port_mode {
161 XGBE_PORT_MODE_RSVD = 0,
162 XGBE_PORT_MODE_BACKPLANE,
163 XGBE_PORT_MODE_BACKPLANE_2500,
164 XGBE_PORT_MODE_1000BASE_T,
165 XGBE_PORT_MODE_1000BASE_X,
166 XGBE_PORT_MODE_NBASE_T,
167 XGBE_PORT_MODE_10GBASE_T,
168 XGBE_PORT_MODE_10GBASE_R,
169 XGBE_PORT_MODE_SFP,
170 XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG,
171 XGBE_PORT_MODE_MAX,
172};
173
174enum xgbe_conn_type {
175 XGBE_CONN_TYPE_NONE = 0,
176 XGBE_CONN_TYPE_SFP,
177 XGBE_CONN_TYPE_MDIO,
178 XGBE_CONN_TYPE_RSVD1,
179 XGBE_CONN_TYPE_BACKPLANE,
180 XGBE_CONN_TYPE_MAX,
181};
182
183/* SFP/SFP+ related definitions */
184enum xgbe_sfp_comm {
185 XGBE_SFP_COMM_DIRECT = 0,
186 XGBE_SFP_COMM_PCA9545,
187};
188
189enum xgbe_sfp_cable {
190 XGBE_SFP_CABLE_UNKNOWN = 0,
191 XGBE_SFP_CABLE_ACTIVE,
192 XGBE_SFP_CABLE_PASSIVE,
193 XGBE_SFP_CABLE_FIBER,
194};
195
196enum xgbe_sfp_base {
197 XGBE_SFP_BASE_UNKNOWN = 0,
198 XGBE_SFP_BASE_1000_T,
199 XGBE_SFP_BASE_1000_SX,
200 XGBE_SFP_BASE_1000_LX,
201 XGBE_SFP_BASE_1000_CX,
202 XGBE_SFP_BASE_10000_SR,
203 XGBE_SFP_BASE_10000_LR,
204 XGBE_SFP_BASE_10000_LRM,
205 XGBE_SFP_BASE_10000_ER,
206 XGBE_SFP_BASE_10000_CR,
207};
208
209enum xgbe_sfp_speed {
210 XGBE_SFP_SPEED_UNKNOWN = 0,
211 XGBE_SFP_SPEED_100_1000,
212 XGBE_SFP_SPEED_1000,
213 XGBE_SFP_SPEED_10000,
214};
215
216/* SFP Serial ID Base ID values relative to an offset of 0 */
217#define XGBE_SFP_BASE_ID 0
218#define XGBE_SFP_ID_SFP 0x03
219
220#define XGBE_SFP_BASE_EXT_ID 1
221#define XGBE_SFP_EXT_ID_SFP 0x04
222
223#define XGBE_SFP_BASE_10GBE_CC 3
224#define XGBE_SFP_BASE_10GBE_CC_SR BIT(4)
225#define XGBE_SFP_BASE_10GBE_CC_LR BIT(5)
226#define XGBE_SFP_BASE_10GBE_CC_LRM BIT(6)
227#define XGBE_SFP_BASE_10GBE_CC_ER BIT(7)
228
229#define XGBE_SFP_BASE_1GBE_CC 6
230#define XGBE_SFP_BASE_1GBE_CC_SX BIT(0)
231#define XGBE_SFP_BASE_1GBE_CC_LX BIT(1)
232#define XGBE_SFP_BASE_1GBE_CC_CX BIT(2)
233#define XGBE_SFP_BASE_1GBE_CC_T BIT(3)
234
235#define XGBE_SFP_BASE_CABLE 8
236#define XGBE_SFP_BASE_CABLE_PASSIVE BIT(2)
237#define XGBE_SFP_BASE_CABLE_ACTIVE BIT(3)
238
239#define XGBE_SFP_BASE_BR 12
240#define XGBE_SFP_BASE_BR_1GBE_MIN 0x0a
241#define XGBE_SFP_BASE_BR_10GBE_MIN 0x64
242
243#define XGBE_SFP_BASE_CU_CABLE_LEN 18
244
245#define XGBE_SFP_BASE_VENDOR_NAME 20
246#define XGBE_SFP_BASE_VENDOR_NAME_LEN 16
247#define XGBE_SFP_BASE_VENDOR_PN 40
248#define XGBE_SFP_BASE_VENDOR_PN_LEN 16
249#define XGBE_SFP_BASE_VENDOR_REV 56
250#define XGBE_SFP_BASE_VENDOR_REV_LEN 4
251
252#define XGBE_SFP_BASE_CC 63
253
254/* SFP Serial ID Extended ID values relative to an offset of 64 */
255#define XGBE_SFP_BASE_VENDOR_SN 4
256#define XGBE_SFP_BASE_VENDOR_SN_LEN 16
257
258#define XGBE_SFP_EXTD_OPT1 1
259#define XGBE_SFP_EXTD_OPT1_RX_LOS BIT(1)
260#define XGBE_SFP_EXTD_OPT1_TX_FAULT BIT(3)
261
262#define XGBE_SFP_EXTD_DIAG 28
263#define XGBE_SFP_EXTD_DIAG_ADDR_CHANGE BIT(2)
264
265#define XGBE_SFP_EXTD_SFF_8472 30
266
267#define XGBE_SFP_EXTD_CC 31
268
269struct xgbe_sfp_eeprom {
270 u8 base[64];
271 u8 extd[32];
272 u8 vendor[32];
273};
274
275#define XGBE_SFP_DIAGS_SUPPORTED(_x) \
276 ((_x)->extd[XGBE_SFP_EXTD_SFF_8472] && \
277 !((_x)->extd[XGBE_SFP_EXTD_DIAG] & XGBE_SFP_EXTD_DIAG_ADDR_CHANGE))
278
279#define XGBE_SFP_EEPROM_BASE_LEN 256
280#define XGBE_SFP_EEPROM_DIAG_LEN 256
281#define XGBE_SFP_EEPROM_MAX (XGBE_SFP_EEPROM_BASE_LEN + \
282 XGBE_SFP_EEPROM_DIAG_LEN)
283
284#define XGBE_BEL_FUSE_VENDOR "BEL-FUSE "
285#define XGBE_BEL_FUSE_PARTNO "1GBT-SFP06 "
286
287#define XGBE_MOLEX_VENDOR "Molex Inc. "
288
289struct xgbe_sfp_ascii {
290 union {
291 char vendor[XGBE_SFP_BASE_VENDOR_NAME_LEN + 1];
292 char partno[XGBE_SFP_BASE_VENDOR_PN_LEN + 1];
293 char rev[XGBE_SFP_BASE_VENDOR_REV_LEN + 1];
294 char serno[XGBE_SFP_BASE_VENDOR_SN_LEN + 1];
295 } u;
296};
297
298/* MDIO PHY reset types */
299enum xgbe_mdio_reset {
300 XGBE_MDIO_RESET_NONE = 0,
301 XGBE_MDIO_RESET_I2C_GPIO,
302 XGBE_MDIO_RESET_INT_GPIO,
303 XGBE_MDIO_RESET_MAX,
304};
305
306/* Re-driver related definitions */
307enum xgbe_phy_redrv_if {
308 XGBE_PHY_REDRV_IF_MDIO = 0,
309 XGBE_PHY_REDRV_IF_I2C,
310 XGBE_PHY_REDRV_IF_MAX,
311};
312
313enum xgbe_phy_redrv_model {
314 XGBE_PHY_REDRV_MODEL_4223 = 0,
315 XGBE_PHY_REDRV_MODEL_4227,
316 XGBE_PHY_REDRV_MODEL_MAX,
317};
318
319enum xgbe_phy_redrv_mode {
320 XGBE_PHY_REDRV_MODE_CX = 5,
321 XGBE_PHY_REDRV_MODE_SR = 9,
322};
323
324#define XGBE_PHY_REDRV_MODE_REG 0x12b0
325
326/* PHY related configuration information */
327struct xgbe_phy_data {
328 enum xgbe_port_mode port_mode;
329
330 unsigned int port_id;
331
332 unsigned int port_speeds;
333
334 enum xgbe_conn_type conn_type;
335
336 enum xgbe_mode cur_mode;
337 enum xgbe_mode start_mode;
338
339 unsigned int rrc_count;
340
341 unsigned int mdio_addr;
342
343 /* SFP Support */
344 enum xgbe_sfp_comm sfp_comm;
345 unsigned int sfp_mux_address;
346 unsigned int sfp_mux_channel;
347
348 unsigned int sfp_gpio_address;
349 unsigned int sfp_gpio_mask;
350 unsigned int sfp_gpio_inputs;
351 unsigned int sfp_gpio_rx_los;
352 unsigned int sfp_gpio_tx_fault;
353 unsigned int sfp_gpio_mod_absent;
354 unsigned int sfp_gpio_rate_select;
355
356 unsigned int sfp_rx_los;
357 unsigned int sfp_tx_fault;
358 unsigned int sfp_mod_absent;
359 unsigned int sfp_changed;
360 unsigned int sfp_phy_avail;
361 unsigned int sfp_cable_len;
362 enum xgbe_sfp_base sfp_base;
363 enum xgbe_sfp_cable sfp_cable;
364 enum xgbe_sfp_speed sfp_speed;
365 struct xgbe_sfp_eeprom sfp_eeprom;
366
367 /* External PHY support */
368 enum xgbe_mdio_mode phydev_mode;
369 struct mii_bus *mii;
370 struct phy_device *phydev;
371 enum xgbe_mdio_reset mdio_reset;
372 unsigned int mdio_reset_addr;
373 unsigned int mdio_reset_gpio;
374
375 /* Re-driver support */
376 unsigned int redrv;
377 unsigned int redrv_if;
378 unsigned int redrv_addr;
379 unsigned int redrv_lane;
380 unsigned int redrv_model;
381
382 /* KR AN support */
383 unsigned int phy_cdr_notrack;
384 unsigned int phy_cdr_delay;
385};
386
387/* I2C, MDIO and GPIO lines are muxed, so only one device at a time */
388static DEFINE_MUTEX(xgbe_phy_comm_lock);
389
390static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata);
391static void xgbe_phy_rrc(struct xgbe_prv_data *pdata);
392static void xgbe_phy_perform_ratechange(struct xgbe_prv_data *pdata,
393 enum xgbe_mb_cmd cmd,
394 enum xgbe_mb_subcmd sub_cmd);
395
396static int xgbe_phy_i2c_xfer(struct xgbe_prv_data *pdata,
397 struct xgbe_i2c_op *i2c_op)
398{
399 return pdata->i2c_if.i2c_xfer(pdata, i2c_op);
400}
401
402static int xgbe_phy_redrv_write(struct xgbe_prv_data *pdata, unsigned int reg,
403 unsigned int val)
404{
405 struct xgbe_phy_data *phy_data = pdata->phy_data;
406 struct xgbe_i2c_op i2c_op;
407 __be16 *redrv_val;
408 u8 redrv_data[5], csum;
409 unsigned int i, retry;
410 int ret;
411
412 /* High byte of register contains read/write indicator */
413 redrv_data[0] = ((reg >> 8) & 0xff) << 1;
414 redrv_data[1] = reg & 0xff;
415 redrv_val = (__be16 *)&redrv_data[2];
416 *redrv_val = cpu_to_be16(val);
417
418 /* Calculate 1 byte checksum */
419 csum = 0;
420 for (i = 0; i < 4; i++) {
421 csum += redrv_data[i];
422 if (redrv_data[i] > csum)
423 csum++;
424 }
425 redrv_data[4] = ~csum;
426
427 retry = 1;
428again1:
429 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
430 i2c_op.target = phy_data->redrv_addr;
431 i2c_op.len = sizeof(redrv_data);
432 i2c_op.buf = redrv_data;
433 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
434 if (ret) {
435 if ((ret == -EAGAIN) && retry--)
436 goto again1;
437
438 return ret;
439 }
440
441 retry = 1;
442again2:
443 i2c_op.cmd = XGBE_I2C_CMD_READ;
444 i2c_op.target = phy_data->redrv_addr;
445 i2c_op.len = 1;
446 i2c_op.buf = redrv_data;
447 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
448 if (ret) {
449 if ((ret == -EAGAIN) && retry--)
450 goto again2;
451
452 return ret;
453 }
454
455 if (redrv_data[0] != 0xff) {
456 netif_dbg(pdata, drv, pdata->netdev,
457 "Redriver write checksum error\n");
458 ret = -EIO;
459 }
460
461 return ret;
462}
463
464static int xgbe_phy_i2c_write(struct xgbe_prv_data *pdata, unsigned int target,
465 void *val, unsigned int val_len)
466{
467 struct xgbe_i2c_op i2c_op;
468 int retry, ret;
469
470 retry = 1;
471again:
472 /* Write the specfied register */
473 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
474 i2c_op.target = target;
475 i2c_op.len = val_len;
476 i2c_op.buf = val;
477 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
478 if ((ret == -EAGAIN) && retry--)
479 goto again;
480
481 return ret;
482}
483
484static int xgbe_phy_i2c_read(struct xgbe_prv_data *pdata, unsigned int target,
485 void *reg, unsigned int reg_len,
486 void *val, unsigned int val_len)
487{
488 struct xgbe_i2c_op i2c_op;
489 int retry, ret;
490
491 retry = 1;
492again1:
493 /* Set the specified register to read */
494 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
495 i2c_op.target = target;
496 i2c_op.len = reg_len;
497 i2c_op.buf = reg;
498 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
499 if (ret) {
500 if ((ret == -EAGAIN) && retry--)
501 goto again1;
502
503 return ret;
504 }
505
506 retry = 1;
507again2:
508 /* Read the specfied register */
509 i2c_op.cmd = XGBE_I2C_CMD_READ;
510 i2c_op.target = target;
511 i2c_op.len = val_len;
512 i2c_op.buf = val;
513 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
514 if ((ret == -EAGAIN) && retry--)
515 goto again2;
516
517 return ret;
518}
519
520static int xgbe_phy_sfp_put_mux(struct xgbe_prv_data *pdata)
521{
522 struct xgbe_phy_data *phy_data = pdata->phy_data;
523 struct xgbe_i2c_op i2c_op;
524 u8 mux_channel;
525
526 if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT)
527 return 0;
528
529 /* Select no mux channels */
530 mux_channel = 0;
531 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
532 i2c_op.target = phy_data->sfp_mux_address;
533 i2c_op.len = sizeof(mux_channel);
534 i2c_op.buf = &mux_channel;
535
536 return xgbe_phy_i2c_xfer(pdata, &i2c_op);
537}
538
539static int xgbe_phy_sfp_get_mux(struct xgbe_prv_data *pdata)
540{
541 struct xgbe_phy_data *phy_data = pdata->phy_data;
542 struct xgbe_i2c_op i2c_op;
543 u8 mux_channel;
544
545 if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT)
546 return 0;
547
548 /* Select desired mux channel */
549 mux_channel = 1 << phy_data->sfp_mux_channel;
550 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
551 i2c_op.target = phy_data->sfp_mux_address;
552 i2c_op.len = sizeof(mux_channel);
553 i2c_op.buf = &mux_channel;
554
555 return xgbe_phy_i2c_xfer(pdata, &i2c_op);
556}
557
558static void xgbe_phy_put_comm_ownership(struct xgbe_prv_data *pdata)
559{
560 mutex_unlock(&xgbe_phy_comm_lock);
561}
562
563static int xgbe_phy_get_comm_ownership(struct xgbe_prv_data *pdata)
564{
565 struct xgbe_phy_data *phy_data = pdata->phy_data;
566 unsigned long timeout;
567 unsigned int mutex_id;
568
569 /* The I2C and MDIO/GPIO bus is multiplexed between multiple devices,
570 * the driver needs to take the software mutex and then the hardware
571 * mutexes before being able to use the busses.
572 */
573 mutex_lock(&xgbe_phy_comm_lock);
574
575 /* Clear the mutexes */
576 XP_IOWRITE(pdata, XP_I2C_MUTEX, XGBE_MUTEX_RELEASE);
577 XP_IOWRITE(pdata, XP_MDIO_MUTEX, XGBE_MUTEX_RELEASE);
578
579 /* Mutex formats are the same for I2C and MDIO/GPIO */
580 mutex_id = 0;
581 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ID, phy_data->port_id);
582 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ACTIVE, 1);
583
584 timeout = jiffies + (5 * HZ);
585 while (time_before(jiffies, timeout)) {
586 /* Must be all zeroes in order to obtain the mutex */
587 if (XP_IOREAD(pdata, XP_I2C_MUTEX) ||
588 XP_IOREAD(pdata, XP_MDIO_MUTEX)) {
589 usleep_range(100, 200);
590 continue;
591 }
592
593 /* Obtain the mutex */
594 XP_IOWRITE(pdata, XP_I2C_MUTEX, mutex_id);
595 XP_IOWRITE(pdata, XP_MDIO_MUTEX, mutex_id);
596
597 return 0;
598 }
599
600 mutex_unlock(&xgbe_phy_comm_lock);
601
602 netdev_err(pdata->netdev, "unable to obtain hardware mutexes\n");
603
604 return -ETIMEDOUT;
605}
606
607static int xgbe_phy_mdio_mii_write_c22(struct xgbe_prv_data *pdata, int addr,
608 int reg, u16 val)
609{
610 struct xgbe_phy_data *phy_data = pdata->phy_data;
611
612 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22)
613 return -EOPNOTSUPP;
614
615 return pdata->hw_if.write_ext_mii_regs_c22(pdata, addr, reg, val);
616}
617
618static int xgbe_phy_mdio_mii_write_c45(struct xgbe_prv_data *pdata, int addr,
619 int devad, int reg, u16 val)
620{
621 struct xgbe_phy_data *phy_data = pdata->phy_data;
622
623 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45)
624 return -EOPNOTSUPP;
625
626 return pdata->hw_if.write_ext_mii_regs_c45(pdata, addr, devad,
627 reg, val);
628}
629
630static int xgbe_phy_i2c_mii_write(struct xgbe_prv_data *pdata, int reg, u16 val)
631{
632 __be16 *mii_val;
633 u8 mii_data[3];
634 int ret;
635
636 ret = xgbe_phy_sfp_get_mux(pdata);
637 if (ret)
638 return ret;
639
640 mii_data[0] = reg & 0xff;
641 mii_val = (__be16 *)&mii_data[1];
642 *mii_val = cpu_to_be16(val);
643
644 ret = xgbe_phy_i2c_write(pdata, XGBE_SFP_PHY_ADDRESS,
645 mii_data, sizeof(mii_data));
646
647 xgbe_phy_sfp_put_mux(pdata);
648
649 return ret;
650}
651
652static int xgbe_phy_mii_write_c22(struct mii_bus *mii, int addr, int reg,
653 u16 val)
654{
655 struct xgbe_prv_data *pdata = mii->priv;
656 struct xgbe_phy_data *phy_data = pdata->phy_data;
657 int ret;
658
659 ret = xgbe_phy_get_comm_ownership(pdata);
660 if (ret)
661 return ret;
662
663 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
664 ret = xgbe_phy_i2c_mii_write(pdata, reg, val);
665 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO)
666 ret = xgbe_phy_mdio_mii_write_c22(pdata, addr, reg, val);
667 else
668 ret = -EOPNOTSUPP;
669
670 xgbe_phy_put_comm_ownership(pdata);
671
672 return ret;
673}
674
675static int xgbe_phy_mii_write_c45(struct mii_bus *mii, int addr, int devad,
676 int reg, u16 val)
677{
678 struct xgbe_prv_data *pdata = mii->priv;
679 struct xgbe_phy_data *phy_data = pdata->phy_data;
680 int ret;
681
682 ret = xgbe_phy_get_comm_ownership(pdata);
683 if (ret)
684 return ret;
685
686 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
687 ret = -EOPNOTSUPP;
688 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO)
689 ret = xgbe_phy_mdio_mii_write_c45(pdata, addr, devad, reg, val);
690 else
691 ret = -EOPNOTSUPP;
692
693 xgbe_phy_put_comm_ownership(pdata);
694
695 return ret;
696}
697
698static int xgbe_phy_mdio_mii_read_c22(struct xgbe_prv_data *pdata, int addr,
699 int reg)
700{
701 struct xgbe_phy_data *phy_data = pdata->phy_data;
702
703 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22)
704 return -EOPNOTSUPP;
705
706 return pdata->hw_if.read_ext_mii_regs_c22(pdata, addr, reg);
707}
708
709static int xgbe_phy_mdio_mii_read_c45(struct xgbe_prv_data *pdata, int addr,
710 int devad, int reg)
711{
712 struct xgbe_phy_data *phy_data = pdata->phy_data;
713
714 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45)
715 return -EOPNOTSUPP;
716
717 return pdata->hw_if.read_ext_mii_regs_c45(pdata, addr, devad, reg);
718}
719
720static int xgbe_phy_i2c_mii_read(struct xgbe_prv_data *pdata, int reg)
721{
722 __be16 mii_val;
723 u8 mii_reg;
724 int ret;
725
726 ret = xgbe_phy_sfp_get_mux(pdata);
727 if (ret)
728 return ret;
729
730 mii_reg = reg;
731 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_PHY_ADDRESS,
732 &mii_reg, sizeof(mii_reg),
733 &mii_val, sizeof(mii_val));
734 if (!ret)
735 ret = be16_to_cpu(mii_val);
736
737 xgbe_phy_sfp_put_mux(pdata);
738
739 return ret;
740}
741
742static int xgbe_phy_mii_read_c22(struct mii_bus *mii, int addr, int reg)
743{
744 struct xgbe_prv_data *pdata = mii->priv;
745 struct xgbe_phy_data *phy_data = pdata->phy_data;
746 int ret;
747
748 ret = xgbe_phy_get_comm_ownership(pdata);
749 if (ret)
750 return ret;
751
752 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
753 ret = xgbe_phy_i2c_mii_read(pdata, reg);
754 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO)
755 ret = xgbe_phy_mdio_mii_read_c22(pdata, addr, reg);
756 else
757 ret = -EOPNOTSUPP;
758
759 xgbe_phy_put_comm_ownership(pdata);
760
761 return ret;
762}
763
764static int xgbe_phy_mii_read_c45(struct mii_bus *mii, int addr, int devad,
765 int reg)
766{
767 struct xgbe_prv_data *pdata = mii->priv;
768 struct xgbe_phy_data *phy_data = pdata->phy_data;
769 int ret;
770
771 ret = xgbe_phy_get_comm_ownership(pdata);
772 if (ret)
773 return ret;
774
775 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
776 ret = -EOPNOTSUPP;
777 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO)
778 ret = xgbe_phy_mdio_mii_read_c45(pdata, addr, devad, reg);
779 else
780 ret = -ENOTSUPP;
781
782 xgbe_phy_put_comm_ownership(pdata);
783
784 return ret;
785}
786
787static void xgbe_phy_sfp_phy_settings(struct xgbe_prv_data *pdata)
788{
789 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
790 struct xgbe_phy_data *phy_data = pdata->phy_data;
791
792 if (!phy_data->sfp_mod_absent && !phy_data->sfp_changed)
793 return;
794
795 XGBE_ZERO_SUP(lks);
796
797 if (phy_data->sfp_mod_absent) {
798 pdata->phy.speed = SPEED_UNKNOWN;
799 pdata->phy.duplex = DUPLEX_UNKNOWN;
800 pdata->phy.autoneg = AUTONEG_ENABLE;
801 pdata->phy.pause_autoneg = AUTONEG_ENABLE;
802
803 XGBE_SET_SUP(lks, Autoneg);
804 XGBE_SET_SUP(lks, Pause);
805 XGBE_SET_SUP(lks, Asym_Pause);
806 XGBE_SET_SUP(lks, TP);
807 XGBE_SET_SUP(lks, FIBRE);
808
809 XGBE_LM_COPY(lks, advertising, lks, supported);
810
811 return;
812 }
813
814 switch (phy_data->sfp_base) {
815 case XGBE_SFP_BASE_1000_T:
816 case XGBE_SFP_BASE_1000_SX:
817 case XGBE_SFP_BASE_1000_LX:
818 case XGBE_SFP_BASE_1000_CX:
819 pdata->phy.speed = SPEED_UNKNOWN;
820 pdata->phy.duplex = DUPLEX_UNKNOWN;
821 pdata->phy.autoneg = AUTONEG_ENABLE;
822 pdata->phy.pause_autoneg = AUTONEG_ENABLE;
823 XGBE_SET_SUP(lks, Autoneg);
824 XGBE_SET_SUP(lks, Pause);
825 XGBE_SET_SUP(lks, Asym_Pause);
826 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T) {
827 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10)
828 XGBE_SET_SUP(lks, 10baseT_Full);
829 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100)
830 XGBE_SET_SUP(lks, 100baseT_Full);
831 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
832 XGBE_SET_SUP(lks, 1000baseT_Full);
833 } else {
834 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
835 XGBE_SET_SUP(lks, 1000baseX_Full);
836 }
837 break;
838 case XGBE_SFP_BASE_10000_SR:
839 case XGBE_SFP_BASE_10000_LR:
840 case XGBE_SFP_BASE_10000_LRM:
841 case XGBE_SFP_BASE_10000_ER:
842 case XGBE_SFP_BASE_10000_CR:
843 pdata->phy.speed = SPEED_10000;
844 pdata->phy.duplex = DUPLEX_FULL;
845 pdata->phy.autoneg = AUTONEG_DISABLE;
846 pdata->phy.pause_autoneg = AUTONEG_DISABLE;
847 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
848 switch (phy_data->sfp_base) {
849 case XGBE_SFP_BASE_10000_SR:
850 XGBE_SET_SUP(lks, 10000baseSR_Full);
851 break;
852 case XGBE_SFP_BASE_10000_LR:
853 XGBE_SET_SUP(lks, 10000baseLR_Full);
854 break;
855 case XGBE_SFP_BASE_10000_LRM:
856 XGBE_SET_SUP(lks, 10000baseLRM_Full);
857 break;
858 case XGBE_SFP_BASE_10000_ER:
859 XGBE_SET_SUP(lks, 10000baseER_Full);
860 break;
861 case XGBE_SFP_BASE_10000_CR:
862 XGBE_SET_SUP(lks, 10000baseCR_Full);
863 break;
864 default:
865 break;
866 }
867 }
868 break;
869 default:
870 pdata->phy.speed = SPEED_UNKNOWN;
871 pdata->phy.duplex = DUPLEX_UNKNOWN;
872 pdata->phy.autoneg = AUTONEG_DISABLE;
873 pdata->phy.pause_autoneg = AUTONEG_DISABLE;
874 break;
875 }
876
877 switch (phy_data->sfp_base) {
878 case XGBE_SFP_BASE_1000_T:
879 case XGBE_SFP_BASE_1000_CX:
880 case XGBE_SFP_BASE_10000_CR:
881 XGBE_SET_SUP(lks, TP);
882 break;
883 default:
884 XGBE_SET_SUP(lks, FIBRE);
885 break;
886 }
887
888 XGBE_LM_COPY(lks, advertising, lks, supported);
889}
890
891static bool xgbe_phy_sfp_bit_rate(struct xgbe_sfp_eeprom *sfp_eeprom,
892 enum xgbe_sfp_speed sfp_speed)
893{
894 u8 *sfp_base, min;
895
896 sfp_base = sfp_eeprom->base;
897
898 switch (sfp_speed) {
899 case XGBE_SFP_SPEED_1000:
900 min = XGBE_SFP_BASE_BR_1GBE_MIN;
901 break;
902 case XGBE_SFP_SPEED_10000:
903 min = XGBE_SFP_BASE_BR_10GBE_MIN;
904 break;
905 default:
906 return false;
907 }
908
909 return sfp_base[XGBE_SFP_BASE_BR] >= min;
910}
911
912static void xgbe_phy_free_phy_device(struct xgbe_prv_data *pdata)
913{
914 struct xgbe_phy_data *phy_data = pdata->phy_data;
915
916 if (phy_data->phydev) {
917 phy_detach(phy_data->phydev);
918 phy_device_remove(phy_data->phydev);
919 phy_device_free(phy_data->phydev);
920 phy_data->phydev = NULL;
921 }
922}
923
924static bool xgbe_phy_finisar_phy_quirks(struct xgbe_prv_data *pdata)
925{
926 struct xgbe_phy_data *phy_data = pdata->phy_data;
927 unsigned int phy_id = phy_data->phydev->phy_id;
928
929 if (phy_data->port_mode != XGBE_PORT_MODE_SFP)
930 return false;
931
932 if ((phy_id & 0xfffffff0) != 0x01ff0cc0)
933 return false;
934
935 /* Enable Base-T AN */
936 phy_write(phy_data->phydev, 0x16, 0x0001);
937 phy_write(phy_data->phydev, 0x00, 0x9140);
938 phy_write(phy_data->phydev, 0x16, 0x0000);
939
940 /* Enable SGMII at 100Base-T/1000Base-T Full Duplex */
941 phy_write(phy_data->phydev, 0x1b, 0x9084);
942 phy_write(phy_data->phydev, 0x09, 0x0e00);
943 phy_write(phy_data->phydev, 0x00, 0x8140);
944 phy_write(phy_data->phydev, 0x04, 0x0d01);
945 phy_write(phy_data->phydev, 0x00, 0x9140);
946
947 linkmode_copy(phy_data->phydev->supported, PHY_GBIT_FEATURES);
948
949 phy_support_asym_pause(phy_data->phydev);
950
951 netif_dbg(pdata, drv, pdata->netdev,
952 "Finisar PHY quirk in place\n");
953
954 return true;
955}
956
957static bool xgbe_phy_belfuse_phy_quirks(struct xgbe_prv_data *pdata)
958{
959 struct xgbe_phy_data *phy_data = pdata->phy_data;
960 struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom;
961 unsigned int phy_id = phy_data->phydev->phy_id;
962 int reg;
963
964 if (phy_data->port_mode != XGBE_PORT_MODE_SFP)
965 return false;
966
967 if (memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME],
968 XGBE_BEL_FUSE_VENDOR, XGBE_SFP_BASE_VENDOR_NAME_LEN))
969 return false;
970
971 /* For Bel-Fuse, use the extra AN flag */
972 pdata->an_again = 1;
973
974 if (memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN],
975 XGBE_BEL_FUSE_PARTNO, XGBE_SFP_BASE_VENDOR_PN_LEN))
976 return false;
977
978 if ((phy_id & 0xfffffff0) != 0x03625d10)
979 return false;
980
981 /* Reset PHY - wait for self-clearing reset bit to clear */
982 genphy_soft_reset(phy_data->phydev);
983
984 /* Disable RGMII mode */
985 phy_write(phy_data->phydev, 0x18, 0x7007);
986 reg = phy_read(phy_data->phydev, 0x18);
987 phy_write(phy_data->phydev, 0x18, reg & ~0x0080);
988
989 /* Enable fiber register bank */
990 phy_write(phy_data->phydev, 0x1c, 0x7c00);
991 reg = phy_read(phy_data->phydev, 0x1c);
992 reg &= 0x03ff;
993 reg &= ~0x0001;
994 phy_write(phy_data->phydev, 0x1c, 0x8000 | 0x7c00 | reg | 0x0001);
995
996 /* Power down SerDes */
997 reg = phy_read(phy_data->phydev, 0x00);
998 phy_write(phy_data->phydev, 0x00, reg | 0x00800);
999
1000 /* Configure SGMII-to-Copper mode */
1001 phy_write(phy_data->phydev, 0x1c, 0x7c00);
1002 reg = phy_read(phy_data->phydev, 0x1c);
1003 reg &= 0x03ff;
1004 reg &= ~0x0006;
1005 phy_write(phy_data->phydev, 0x1c, 0x8000 | 0x7c00 | reg | 0x0004);
1006
1007 /* Power up SerDes */
1008 reg = phy_read(phy_data->phydev, 0x00);
1009 phy_write(phy_data->phydev, 0x00, reg & ~0x00800);
1010
1011 /* Enable copper register bank */
1012 phy_write(phy_data->phydev, 0x1c, 0x7c00);
1013 reg = phy_read(phy_data->phydev, 0x1c);
1014 reg &= 0x03ff;
1015 reg &= ~0x0001;
1016 phy_write(phy_data->phydev, 0x1c, 0x8000 | 0x7c00 | reg);
1017
1018 /* Power up SerDes */
1019 reg = phy_read(phy_data->phydev, 0x00);
1020 phy_write(phy_data->phydev, 0x00, reg & ~0x00800);
1021
1022 linkmode_copy(phy_data->phydev->supported, PHY_GBIT_FEATURES);
1023 phy_support_asym_pause(phy_data->phydev);
1024
1025 netif_dbg(pdata, drv, pdata->netdev,
1026 "BelFuse PHY quirk in place\n");
1027
1028 return true;
1029}
1030
1031static void xgbe_phy_external_phy_quirks(struct xgbe_prv_data *pdata)
1032{
1033 if (xgbe_phy_belfuse_phy_quirks(pdata))
1034 return;
1035
1036 if (xgbe_phy_finisar_phy_quirks(pdata))
1037 return;
1038}
1039
1040static int xgbe_phy_find_phy_device(struct xgbe_prv_data *pdata)
1041{
1042 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1043 struct xgbe_phy_data *phy_data = pdata->phy_data;
1044 struct phy_device *phydev;
1045 int ret;
1046
1047 /* If we already have a PHY, just return */
1048 if (phy_data->phydev)
1049 return 0;
1050
1051 /* Clear the extra AN flag */
1052 pdata->an_again = 0;
1053
1054 /* Check for the use of an external PHY */
1055 if (phy_data->phydev_mode == XGBE_MDIO_MODE_NONE)
1056 return 0;
1057
1058 /* For SFP, only use an external PHY if available */
1059 if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) &&
1060 !phy_data->sfp_phy_avail)
1061 return 0;
1062
1063 /* Set the proper MDIO mode for the PHY */
1064 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr,
1065 phy_data->phydev_mode);
1066 if (ret) {
1067 netdev_err(pdata->netdev,
1068 "mdio port/clause not compatible (%u/%u)\n",
1069 phy_data->mdio_addr, phy_data->phydev_mode);
1070 return ret;
1071 }
1072
1073 /* Create and connect to the PHY device */
1074 phydev = get_phy_device(phy_data->mii, phy_data->mdio_addr,
1075 (phy_data->phydev_mode == XGBE_MDIO_MODE_CL45));
1076 if (IS_ERR(phydev)) {
1077 netdev_err(pdata->netdev, "get_phy_device failed\n");
1078 return -ENODEV;
1079 }
1080 netif_dbg(pdata, drv, pdata->netdev, "external PHY id is %#010x\n",
1081 phydev->phy_id);
1082
1083 /*TODO: If c45, add request_module based on one of the MMD ids? */
1084
1085 ret = phy_device_register(phydev);
1086 if (ret) {
1087 netdev_err(pdata->netdev, "phy_device_register failed\n");
1088 phy_device_free(phydev);
1089 return ret;
1090 }
1091
1092 ret = phy_attach_direct(pdata->netdev, phydev, phydev->dev_flags,
1093 PHY_INTERFACE_MODE_SGMII);
1094 if (ret) {
1095 netdev_err(pdata->netdev, "phy_attach_direct failed\n");
1096 phy_device_remove(phydev);
1097 phy_device_free(phydev);
1098 return ret;
1099 }
1100 phy_data->phydev = phydev;
1101
1102 xgbe_phy_external_phy_quirks(pdata);
1103
1104 linkmode_and(phydev->advertising, phydev->advertising,
1105 lks->link_modes.advertising);
1106
1107 phy_start_aneg(phy_data->phydev);
1108
1109 return 0;
1110}
1111
1112static void xgbe_phy_sfp_external_phy(struct xgbe_prv_data *pdata)
1113{
1114 struct xgbe_phy_data *phy_data = pdata->phy_data;
1115 int ret;
1116
1117 if (!phy_data->sfp_changed)
1118 return;
1119
1120 phy_data->sfp_phy_avail = 0;
1121
1122 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
1123 return;
1124
1125 /* Check access to the PHY by reading CTRL1 */
1126 ret = xgbe_phy_i2c_mii_read(pdata, MII_BMCR);
1127 if (ret < 0)
1128 return;
1129
1130 /* Successfully accessed the PHY */
1131 phy_data->sfp_phy_avail = 1;
1132}
1133
1134static bool xgbe_phy_check_sfp_rx_los(struct xgbe_phy_data *phy_data)
1135{
1136 u8 *sfp_extd = phy_data->sfp_eeprom.extd;
1137
1138 if (!(sfp_extd[XGBE_SFP_EXTD_OPT1] & XGBE_SFP_EXTD_OPT1_RX_LOS))
1139 return false;
1140
1141 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_RX_LOS)
1142 return false;
1143
1144 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_rx_los))
1145 return true;
1146
1147 return false;
1148}
1149
1150static bool xgbe_phy_check_sfp_tx_fault(struct xgbe_phy_data *phy_data)
1151{
1152 u8 *sfp_extd = phy_data->sfp_eeprom.extd;
1153
1154 if (!(sfp_extd[XGBE_SFP_EXTD_OPT1] & XGBE_SFP_EXTD_OPT1_TX_FAULT))
1155 return false;
1156
1157 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_TX_FAULT)
1158 return false;
1159
1160 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_tx_fault))
1161 return true;
1162
1163 return false;
1164}
1165
1166static bool xgbe_phy_check_sfp_mod_absent(struct xgbe_phy_data *phy_data)
1167{
1168 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_MOD_ABSENT)
1169 return false;
1170
1171 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_mod_absent))
1172 return true;
1173
1174 return false;
1175}
1176
1177static void xgbe_phy_sfp_parse_eeprom(struct xgbe_prv_data *pdata)
1178{
1179 struct xgbe_phy_data *phy_data = pdata->phy_data;
1180 struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom;
1181 u8 *sfp_base;
1182
1183 sfp_base = sfp_eeprom->base;
1184
1185 if (sfp_base[XGBE_SFP_BASE_ID] != XGBE_SFP_ID_SFP)
1186 return;
1187
1188 if (sfp_base[XGBE_SFP_BASE_EXT_ID] != XGBE_SFP_EXT_ID_SFP)
1189 return;
1190
1191 /* Update transceiver signals (eeprom extd/options) */
1192 phy_data->sfp_tx_fault = xgbe_phy_check_sfp_tx_fault(phy_data);
1193 phy_data->sfp_rx_los = xgbe_phy_check_sfp_rx_los(phy_data);
1194
1195 /* Assume FIBER cable unless told otherwise */
1196 if (sfp_base[XGBE_SFP_BASE_CABLE] & XGBE_SFP_BASE_CABLE_PASSIVE) {
1197 phy_data->sfp_cable = XGBE_SFP_CABLE_PASSIVE;
1198 phy_data->sfp_cable_len = sfp_base[XGBE_SFP_BASE_CU_CABLE_LEN];
1199 } else if (sfp_base[XGBE_SFP_BASE_CABLE] & XGBE_SFP_BASE_CABLE_ACTIVE) {
1200 phy_data->sfp_cable = XGBE_SFP_CABLE_ACTIVE;
1201 } else {
1202 phy_data->sfp_cable = XGBE_SFP_CABLE_FIBER;
1203 }
1204
1205 /* Determine the type of SFP */
1206 if (phy_data->sfp_cable != XGBE_SFP_CABLE_FIBER &&
1207 xgbe_phy_sfp_bit_rate(sfp_eeprom, XGBE_SFP_SPEED_10000))
1208 phy_data->sfp_base = XGBE_SFP_BASE_10000_CR;
1209 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_SR)
1210 phy_data->sfp_base = XGBE_SFP_BASE_10000_SR;
1211 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LR)
1212 phy_data->sfp_base = XGBE_SFP_BASE_10000_LR;
1213 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LRM)
1214 phy_data->sfp_base = XGBE_SFP_BASE_10000_LRM;
1215 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_ER)
1216 phy_data->sfp_base = XGBE_SFP_BASE_10000_ER;
1217 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_SX)
1218 phy_data->sfp_base = XGBE_SFP_BASE_1000_SX;
1219 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_LX)
1220 phy_data->sfp_base = XGBE_SFP_BASE_1000_LX;
1221 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_CX)
1222 phy_data->sfp_base = XGBE_SFP_BASE_1000_CX;
1223 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_T)
1224 phy_data->sfp_base = XGBE_SFP_BASE_1000_T;
1225
1226 switch (phy_data->sfp_base) {
1227 case XGBE_SFP_BASE_1000_T:
1228 phy_data->sfp_speed = XGBE_SFP_SPEED_100_1000;
1229 break;
1230 case XGBE_SFP_BASE_1000_SX:
1231 case XGBE_SFP_BASE_1000_LX:
1232 case XGBE_SFP_BASE_1000_CX:
1233 phy_data->sfp_speed = XGBE_SFP_SPEED_1000;
1234 break;
1235 case XGBE_SFP_BASE_10000_SR:
1236 case XGBE_SFP_BASE_10000_LR:
1237 case XGBE_SFP_BASE_10000_LRM:
1238 case XGBE_SFP_BASE_10000_ER:
1239 case XGBE_SFP_BASE_10000_CR:
1240 phy_data->sfp_speed = XGBE_SFP_SPEED_10000;
1241 break;
1242 default:
1243 break;
1244 }
1245}
1246
1247static void xgbe_phy_sfp_eeprom_info(struct xgbe_prv_data *pdata,
1248 struct xgbe_sfp_eeprom *sfp_eeprom)
1249{
1250 struct xgbe_sfp_ascii sfp_ascii;
1251 char *sfp_data = (char *)&sfp_ascii;
1252
1253 netif_dbg(pdata, drv, pdata->netdev, "SFP detected:\n");
1254 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME],
1255 XGBE_SFP_BASE_VENDOR_NAME_LEN);
1256 sfp_data[XGBE_SFP_BASE_VENDOR_NAME_LEN] = '\0';
1257 netif_dbg(pdata, drv, pdata->netdev, " vendor: %s\n",
1258 sfp_data);
1259
1260 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN],
1261 XGBE_SFP_BASE_VENDOR_PN_LEN);
1262 sfp_data[XGBE_SFP_BASE_VENDOR_PN_LEN] = '\0';
1263 netif_dbg(pdata, drv, pdata->netdev, " part number: %s\n",
1264 sfp_data);
1265
1266 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_REV],
1267 XGBE_SFP_BASE_VENDOR_REV_LEN);
1268 sfp_data[XGBE_SFP_BASE_VENDOR_REV_LEN] = '\0';
1269 netif_dbg(pdata, drv, pdata->netdev, " revision level: %s\n",
1270 sfp_data);
1271
1272 memcpy(sfp_data, &sfp_eeprom->extd[XGBE_SFP_BASE_VENDOR_SN],
1273 XGBE_SFP_BASE_VENDOR_SN_LEN);
1274 sfp_data[XGBE_SFP_BASE_VENDOR_SN_LEN] = '\0';
1275 netif_dbg(pdata, drv, pdata->netdev, " serial number: %s\n",
1276 sfp_data);
1277}
1278
1279static bool xgbe_phy_sfp_verify_eeprom(u8 cc_in, u8 *buf, unsigned int len)
1280{
1281 u8 cc;
1282
1283 for (cc = 0; len; buf++, len--)
1284 cc += *buf;
1285
1286 return cc == cc_in;
1287}
1288
1289static int xgbe_phy_sfp_read_eeprom(struct xgbe_prv_data *pdata)
1290{
1291 struct xgbe_phy_data *phy_data = pdata->phy_data;
1292 struct xgbe_sfp_eeprom sfp_eeprom;
1293 u8 eeprom_addr;
1294 int ret;
1295
1296 ret = xgbe_phy_sfp_get_mux(pdata);
1297 if (ret) {
1298 dev_err_once(pdata->dev, "%s: I2C error setting SFP MUX\n",
1299 netdev_name(pdata->netdev));
1300 return ret;
1301 }
1302
1303 /* Read the SFP serial ID eeprom */
1304 eeprom_addr = 0;
1305 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_SERIAL_ID_ADDRESS,
1306 &eeprom_addr, sizeof(eeprom_addr),
1307 &sfp_eeprom, sizeof(sfp_eeprom));
1308 if (ret) {
1309 dev_err_once(pdata->dev, "%s: I2C error reading SFP EEPROM\n",
1310 netdev_name(pdata->netdev));
1311 goto put;
1312 }
1313
1314 /* Validate the contents read */
1315 if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.base[XGBE_SFP_BASE_CC],
1316 sfp_eeprom.base,
1317 sizeof(sfp_eeprom.base) - 1)) {
1318 ret = -EINVAL;
1319 goto put;
1320 }
1321
1322 if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.extd[XGBE_SFP_EXTD_CC],
1323 sfp_eeprom.extd,
1324 sizeof(sfp_eeprom.extd) - 1)) {
1325 ret = -EINVAL;
1326 goto put;
1327 }
1328
1329 /* Check for an added or changed SFP */
1330 if (memcmp(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom))) {
1331 phy_data->sfp_changed = 1;
1332
1333 if (netif_msg_drv(pdata))
1334 xgbe_phy_sfp_eeprom_info(pdata, &sfp_eeprom);
1335
1336 memcpy(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom));
1337
1338 xgbe_phy_free_phy_device(pdata);
1339 } else {
1340 phy_data->sfp_changed = 0;
1341 }
1342
1343put:
1344 xgbe_phy_sfp_put_mux(pdata);
1345
1346 return ret;
1347}
1348
1349static void xgbe_phy_sfp_signals(struct xgbe_prv_data *pdata)
1350{
1351 struct xgbe_phy_data *phy_data = pdata->phy_data;
1352 u8 gpio_reg, gpio_ports[2];
1353 int ret;
1354
1355 /* Read the input port registers */
1356 gpio_reg = 0;
1357 ret = xgbe_phy_i2c_read(pdata, phy_data->sfp_gpio_address,
1358 &gpio_reg, sizeof(gpio_reg),
1359 gpio_ports, sizeof(gpio_ports));
1360 if (ret) {
1361 dev_err_once(pdata->dev, "%s: I2C error reading SFP GPIOs\n",
1362 netdev_name(pdata->netdev));
1363 return;
1364 }
1365
1366 phy_data->sfp_gpio_inputs = (gpio_ports[1] << 8) | gpio_ports[0];
1367
1368 phy_data->sfp_mod_absent = xgbe_phy_check_sfp_mod_absent(phy_data);
1369}
1370
1371static void xgbe_phy_sfp_mod_absent(struct xgbe_prv_data *pdata)
1372{
1373 struct xgbe_phy_data *phy_data = pdata->phy_data;
1374
1375 xgbe_phy_free_phy_device(pdata);
1376
1377 phy_data->sfp_mod_absent = 1;
1378 phy_data->sfp_phy_avail = 0;
1379 memset(&phy_data->sfp_eeprom, 0, sizeof(phy_data->sfp_eeprom));
1380}
1381
1382static void xgbe_phy_sfp_reset(struct xgbe_phy_data *phy_data)
1383{
1384 phy_data->sfp_rx_los = 0;
1385 phy_data->sfp_tx_fault = 0;
1386 phy_data->sfp_mod_absent = 1;
1387 phy_data->sfp_base = XGBE_SFP_BASE_UNKNOWN;
1388 phy_data->sfp_cable = XGBE_SFP_CABLE_UNKNOWN;
1389 phy_data->sfp_speed = XGBE_SFP_SPEED_UNKNOWN;
1390}
1391
1392static void xgbe_phy_sfp_detect(struct xgbe_prv_data *pdata)
1393{
1394 struct xgbe_phy_data *phy_data = pdata->phy_data;
1395 int ret;
1396
1397 /* Reset the SFP signals and info */
1398 xgbe_phy_sfp_reset(phy_data);
1399
1400 ret = xgbe_phy_get_comm_ownership(pdata);
1401 if (ret)
1402 return;
1403
1404 /* Read the SFP signals and check for module presence */
1405 xgbe_phy_sfp_signals(pdata);
1406 if (phy_data->sfp_mod_absent) {
1407 xgbe_phy_sfp_mod_absent(pdata);
1408 goto put;
1409 }
1410
1411 ret = xgbe_phy_sfp_read_eeprom(pdata);
1412 if (ret) {
1413 /* Treat any error as if there isn't an SFP plugged in */
1414 xgbe_phy_sfp_reset(phy_data);
1415 xgbe_phy_sfp_mod_absent(pdata);
1416 goto put;
1417 }
1418
1419 xgbe_phy_sfp_parse_eeprom(pdata);
1420
1421 xgbe_phy_sfp_external_phy(pdata);
1422
1423put:
1424 xgbe_phy_sfp_phy_settings(pdata);
1425
1426 xgbe_phy_put_comm_ownership(pdata);
1427}
1428
1429static int xgbe_phy_module_eeprom(struct xgbe_prv_data *pdata,
1430 struct ethtool_eeprom *eeprom, u8 *data)
1431{
1432 struct xgbe_phy_data *phy_data = pdata->phy_data;
1433 u8 eeprom_addr, eeprom_data[XGBE_SFP_EEPROM_MAX];
1434 struct xgbe_sfp_eeprom *sfp_eeprom;
1435 unsigned int i, j, rem;
1436 int ret;
1437
1438 rem = eeprom->len;
1439
1440 if (!eeprom->len) {
1441 ret = -EINVAL;
1442 goto done;
1443 }
1444
1445 if ((eeprom->offset + eeprom->len) > XGBE_SFP_EEPROM_MAX) {
1446 ret = -EINVAL;
1447 goto done;
1448 }
1449
1450 if (phy_data->port_mode != XGBE_PORT_MODE_SFP) {
1451 ret = -ENXIO;
1452 goto done;
1453 }
1454
1455 if (!netif_running(pdata->netdev)) {
1456 ret = -EIO;
1457 goto done;
1458 }
1459
1460 if (phy_data->sfp_mod_absent) {
1461 ret = -EIO;
1462 goto done;
1463 }
1464
1465 ret = xgbe_phy_get_comm_ownership(pdata);
1466 if (ret) {
1467 ret = -EIO;
1468 goto done;
1469 }
1470
1471 ret = xgbe_phy_sfp_get_mux(pdata);
1472 if (ret) {
1473 netdev_err(pdata->netdev, "I2C error setting SFP MUX\n");
1474 ret = -EIO;
1475 goto put_own;
1476 }
1477
1478 /* Read the SFP serial ID eeprom */
1479 eeprom_addr = 0;
1480 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_SERIAL_ID_ADDRESS,
1481 &eeprom_addr, sizeof(eeprom_addr),
1482 eeprom_data, XGBE_SFP_EEPROM_BASE_LEN);
1483 if (ret) {
1484 netdev_err(pdata->netdev,
1485 "I2C error reading SFP EEPROM\n");
1486 ret = -EIO;
1487 goto put_mux;
1488 }
1489
1490 sfp_eeprom = (struct xgbe_sfp_eeprom *)eeprom_data;
1491
1492 if (XGBE_SFP_DIAGS_SUPPORTED(sfp_eeprom)) {
1493 /* Read the SFP diagnostic eeprom */
1494 eeprom_addr = 0;
1495 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_DIAG_INFO_ADDRESS,
1496 &eeprom_addr, sizeof(eeprom_addr),
1497 eeprom_data + XGBE_SFP_EEPROM_BASE_LEN,
1498 XGBE_SFP_EEPROM_DIAG_LEN);
1499 if (ret) {
1500 netdev_err(pdata->netdev,
1501 "I2C error reading SFP DIAGS\n");
1502 ret = -EIO;
1503 goto put_mux;
1504 }
1505 }
1506
1507 for (i = 0, j = eeprom->offset; i < eeprom->len; i++, j++) {
1508 if ((j >= XGBE_SFP_EEPROM_BASE_LEN) &&
1509 !XGBE_SFP_DIAGS_SUPPORTED(sfp_eeprom))
1510 break;
1511
1512 data[i] = eeprom_data[j];
1513 rem--;
1514 }
1515
1516put_mux:
1517 xgbe_phy_sfp_put_mux(pdata);
1518
1519put_own:
1520 xgbe_phy_put_comm_ownership(pdata);
1521
1522done:
1523 eeprom->len -= rem;
1524
1525 return ret;
1526}
1527
1528static int xgbe_phy_module_info(struct xgbe_prv_data *pdata,
1529 struct ethtool_modinfo *modinfo)
1530{
1531 struct xgbe_phy_data *phy_data = pdata->phy_data;
1532
1533 if (phy_data->port_mode != XGBE_PORT_MODE_SFP)
1534 return -ENXIO;
1535
1536 if (!netif_running(pdata->netdev))
1537 return -EIO;
1538
1539 if (phy_data->sfp_mod_absent)
1540 return -EIO;
1541
1542 if (XGBE_SFP_DIAGS_SUPPORTED(&phy_data->sfp_eeprom)) {
1543 modinfo->type = ETH_MODULE_SFF_8472;
1544 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1545 } else {
1546 modinfo->type = ETH_MODULE_SFF_8079;
1547 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
1548 }
1549
1550 return 0;
1551}
1552
1553static void xgbe_phy_phydev_flowctrl(struct xgbe_prv_data *pdata)
1554{
1555 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1556 struct xgbe_phy_data *phy_data = pdata->phy_data;
1557 u16 lcl_adv = 0, rmt_adv = 0;
1558 u8 fc;
1559
1560 pdata->phy.tx_pause = 0;
1561 pdata->phy.rx_pause = 0;
1562
1563 if (!phy_data->phydev)
1564 return;
1565
1566 lcl_adv = linkmode_adv_to_lcl_adv_t(phy_data->phydev->advertising);
1567
1568 if (phy_data->phydev->pause) {
1569 XGBE_SET_LP_ADV(lks, Pause);
1570 rmt_adv |= LPA_PAUSE_CAP;
1571 }
1572 if (phy_data->phydev->asym_pause) {
1573 XGBE_SET_LP_ADV(lks, Asym_Pause);
1574 rmt_adv |= LPA_PAUSE_ASYM;
1575 }
1576
1577 fc = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
1578 if (fc & FLOW_CTRL_TX)
1579 pdata->phy.tx_pause = 1;
1580 if (fc & FLOW_CTRL_RX)
1581 pdata->phy.rx_pause = 1;
1582}
1583
1584static enum xgbe_mode xgbe_phy_an37_sgmii_outcome(struct xgbe_prv_data *pdata)
1585{
1586 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1587 enum xgbe_mode mode;
1588
1589 XGBE_SET_LP_ADV(lks, Autoneg);
1590 XGBE_SET_LP_ADV(lks, TP);
1591
1592 /* Use external PHY to determine flow control */
1593 if (pdata->phy.pause_autoneg)
1594 xgbe_phy_phydev_flowctrl(pdata);
1595
1596 switch (pdata->an_status & XGBE_SGMII_AN_LINK_SPEED) {
1597 case XGBE_SGMII_AN_LINK_SPEED_10:
1598 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) {
1599 XGBE_SET_LP_ADV(lks, 10baseT_Full);
1600 mode = XGBE_MODE_SGMII_10;
1601 } else {
1602 /* Half-duplex not supported */
1603 XGBE_SET_LP_ADV(lks, 10baseT_Half);
1604 mode = XGBE_MODE_UNKNOWN;
1605 }
1606 break;
1607 case XGBE_SGMII_AN_LINK_SPEED_100:
1608 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) {
1609 XGBE_SET_LP_ADV(lks, 100baseT_Full);
1610 mode = XGBE_MODE_SGMII_100;
1611 } else {
1612 /* Half-duplex not supported */
1613 XGBE_SET_LP_ADV(lks, 100baseT_Half);
1614 mode = XGBE_MODE_UNKNOWN;
1615 }
1616 break;
1617 case XGBE_SGMII_AN_LINK_SPEED_1000:
1618 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) {
1619 XGBE_SET_LP_ADV(lks, 1000baseT_Full);
1620 mode = XGBE_MODE_SGMII_1000;
1621 } else {
1622 /* Half-duplex not supported */
1623 XGBE_SET_LP_ADV(lks, 1000baseT_Half);
1624 mode = XGBE_MODE_UNKNOWN;
1625 }
1626 break;
1627 default:
1628 mode = XGBE_MODE_UNKNOWN;
1629 }
1630
1631 return mode;
1632}
1633
1634static enum xgbe_mode xgbe_phy_an37_outcome(struct xgbe_prv_data *pdata)
1635{
1636 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1637 enum xgbe_mode mode;
1638 unsigned int ad_reg, lp_reg;
1639
1640 XGBE_SET_LP_ADV(lks, Autoneg);
1641 XGBE_SET_LP_ADV(lks, FIBRE);
1642
1643 /* Compare Advertisement and Link Partner register */
1644 ad_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE);
1645 lp_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_LP_ABILITY);
1646 if (lp_reg & 0x100)
1647 XGBE_SET_LP_ADV(lks, Pause);
1648 if (lp_reg & 0x80)
1649 XGBE_SET_LP_ADV(lks, Asym_Pause);
1650
1651 if (pdata->phy.pause_autoneg) {
1652 /* Set flow control based on auto-negotiation result */
1653 pdata->phy.tx_pause = 0;
1654 pdata->phy.rx_pause = 0;
1655
1656 if (ad_reg & lp_reg & 0x100) {
1657 pdata->phy.tx_pause = 1;
1658 pdata->phy.rx_pause = 1;
1659 } else if (ad_reg & lp_reg & 0x80) {
1660 if (ad_reg & 0x100)
1661 pdata->phy.rx_pause = 1;
1662 else if (lp_reg & 0x100)
1663 pdata->phy.tx_pause = 1;
1664 }
1665 }
1666
1667 if (lp_reg & 0x20)
1668 XGBE_SET_LP_ADV(lks, 1000baseX_Full);
1669
1670 /* Half duplex is not supported */
1671 ad_reg &= lp_reg;
1672 mode = (ad_reg & 0x20) ? XGBE_MODE_X : XGBE_MODE_UNKNOWN;
1673
1674 return mode;
1675}
1676
1677static enum xgbe_mode xgbe_phy_an73_redrv_outcome(struct xgbe_prv_data *pdata)
1678{
1679 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1680 struct xgbe_phy_data *phy_data = pdata->phy_data;
1681 enum xgbe_mode mode;
1682 unsigned int ad_reg, lp_reg;
1683
1684 XGBE_SET_LP_ADV(lks, Autoneg);
1685 XGBE_SET_LP_ADV(lks, Backplane);
1686
1687 /* Use external PHY to determine flow control */
1688 if (pdata->phy.pause_autoneg)
1689 xgbe_phy_phydev_flowctrl(pdata);
1690
1691 /* Compare Advertisement and Link Partner register 2 */
1692 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
1693 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
1694 if (lp_reg & 0x80)
1695 XGBE_SET_LP_ADV(lks, 10000baseKR_Full);
1696 if (lp_reg & 0x20)
1697 XGBE_SET_LP_ADV(lks, 1000baseKX_Full);
1698
1699 ad_reg &= lp_reg;
1700 if (ad_reg & 0x80) {
1701 switch (phy_data->port_mode) {
1702 case XGBE_PORT_MODE_BACKPLANE:
1703 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
1704 mode = XGBE_MODE_KR;
1705 break;
1706 default:
1707 mode = XGBE_MODE_SFI;
1708 break;
1709 }
1710 } else if (ad_reg & 0x20) {
1711 switch (phy_data->port_mode) {
1712 case XGBE_PORT_MODE_BACKPLANE:
1713 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
1714 mode = XGBE_MODE_KX_1000;
1715 break;
1716 case XGBE_PORT_MODE_1000BASE_X:
1717 mode = XGBE_MODE_X;
1718 break;
1719 case XGBE_PORT_MODE_SFP:
1720 switch (phy_data->sfp_base) {
1721 case XGBE_SFP_BASE_1000_T:
1722 if (phy_data->phydev &&
1723 (phy_data->phydev->speed == SPEED_10))
1724 mode = XGBE_MODE_SGMII_10;
1725 else if (phy_data->phydev &&
1726 (phy_data->phydev->speed == SPEED_100))
1727 mode = XGBE_MODE_SGMII_100;
1728 else
1729 mode = XGBE_MODE_SGMII_1000;
1730 break;
1731 case XGBE_SFP_BASE_1000_SX:
1732 case XGBE_SFP_BASE_1000_LX:
1733 case XGBE_SFP_BASE_1000_CX:
1734 default:
1735 mode = XGBE_MODE_X;
1736 break;
1737 }
1738 break;
1739 default:
1740 if (phy_data->phydev &&
1741 (phy_data->phydev->speed == SPEED_10))
1742 mode = XGBE_MODE_SGMII_10;
1743 else if (phy_data->phydev &&
1744 (phy_data->phydev->speed == SPEED_100))
1745 mode = XGBE_MODE_SGMII_100;
1746 else
1747 mode = XGBE_MODE_SGMII_1000;
1748 break;
1749 }
1750 } else {
1751 mode = XGBE_MODE_UNKNOWN;
1752 }
1753
1754 /* Compare Advertisement and Link Partner register 3 */
1755 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
1756 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
1757 if (lp_reg & 0xc000)
1758 XGBE_SET_LP_ADV(lks, 10000baseR_FEC);
1759
1760 return mode;
1761}
1762
1763static enum xgbe_mode xgbe_phy_an73_outcome(struct xgbe_prv_data *pdata)
1764{
1765 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1766 enum xgbe_mode mode;
1767 unsigned int ad_reg, lp_reg;
1768
1769 XGBE_SET_LP_ADV(lks, Autoneg);
1770 XGBE_SET_LP_ADV(lks, Backplane);
1771
1772 /* Compare Advertisement and Link Partner register 1 */
1773 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
1774 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA);
1775 if (lp_reg & 0x400)
1776 XGBE_SET_LP_ADV(lks, Pause);
1777 if (lp_reg & 0x800)
1778 XGBE_SET_LP_ADV(lks, Asym_Pause);
1779
1780 if (pdata->phy.pause_autoneg) {
1781 /* Set flow control based on auto-negotiation result */
1782 pdata->phy.tx_pause = 0;
1783 pdata->phy.rx_pause = 0;
1784
1785 if (ad_reg & lp_reg & 0x400) {
1786 pdata->phy.tx_pause = 1;
1787 pdata->phy.rx_pause = 1;
1788 } else if (ad_reg & lp_reg & 0x800) {
1789 if (ad_reg & 0x400)
1790 pdata->phy.rx_pause = 1;
1791 else if (lp_reg & 0x400)
1792 pdata->phy.tx_pause = 1;
1793 }
1794 }
1795
1796 /* Compare Advertisement and Link Partner register 2 */
1797 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
1798 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
1799 if (lp_reg & 0x80)
1800 XGBE_SET_LP_ADV(lks, 10000baseKR_Full);
1801 if (lp_reg & 0x20)
1802 XGBE_SET_LP_ADV(lks, 1000baseKX_Full);
1803
1804 ad_reg &= lp_reg;
1805 if (ad_reg & 0x80)
1806 mode = XGBE_MODE_KR;
1807 else if (ad_reg & 0x20)
1808 mode = XGBE_MODE_KX_1000;
1809 else
1810 mode = XGBE_MODE_UNKNOWN;
1811
1812 /* Compare Advertisement and Link Partner register 3 */
1813 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
1814 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
1815 if (lp_reg & 0xc000)
1816 XGBE_SET_LP_ADV(lks, 10000baseR_FEC);
1817
1818 return mode;
1819}
1820
1821static enum xgbe_mode xgbe_phy_an_outcome(struct xgbe_prv_data *pdata)
1822{
1823 switch (pdata->an_mode) {
1824 case XGBE_AN_MODE_CL73:
1825 return xgbe_phy_an73_outcome(pdata);
1826 case XGBE_AN_MODE_CL73_REDRV:
1827 return xgbe_phy_an73_redrv_outcome(pdata);
1828 case XGBE_AN_MODE_CL37:
1829 return xgbe_phy_an37_outcome(pdata);
1830 case XGBE_AN_MODE_CL37_SGMII:
1831 return xgbe_phy_an37_sgmii_outcome(pdata);
1832 default:
1833 return XGBE_MODE_UNKNOWN;
1834 }
1835}
1836
1837static void xgbe_phy_an_advertising(struct xgbe_prv_data *pdata,
1838 struct ethtool_link_ksettings *dlks)
1839{
1840 struct ethtool_link_ksettings *slks = &pdata->phy.lks;
1841 struct xgbe_phy_data *phy_data = pdata->phy_data;
1842
1843 XGBE_LM_COPY(dlks, advertising, slks, advertising);
1844
1845 /* Without a re-driver, just return current advertising */
1846 if (!phy_data->redrv)
1847 return;
1848
1849 /* With the KR re-driver we need to advertise a single speed */
1850 XGBE_CLR_ADV(dlks, 1000baseKX_Full);
1851 XGBE_CLR_ADV(dlks, 10000baseKR_Full);
1852
1853 /* Advertise FEC support is present */
1854 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
1855 XGBE_SET_ADV(dlks, 10000baseR_FEC);
1856
1857 switch (phy_data->port_mode) {
1858 case XGBE_PORT_MODE_BACKPLANE:
1859 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
1860 XGBE_SET_ADV(dlks, 10000baseKR_Full);
1861 break;
1862 case XGBE_PORT_MODE_BACKPLANE_2500:
1863 XGBE_SET_ADV(dlks, 1000baseKX_Full);
1864 break;
1865 case XGBE_PORT_MODE_1000BASE_T:
1866 case XGBE_PORT_MODE_1000BASE_X:
1867 case XGBE_PORT_MODE_NBASE_T:
1868 XGBE_SET_ADV(dlks, 1000baseKX_Full);
1869 break;
1870 case XGBE_PORT_MODE_10GBASE_T:
1871 if (phy_data->phydev &&
1872 (phy_data->phydev->speed == SPEED_10000))
1873 XGBE_SET_ADV(dlks, 10000baseKR_Full);
1874 else if (phy_data->phydev &&
1875 (phy_data->phydev->speed == SPEED_2500))
1876 XGBE_SET_ADV(dlks, 2500baseX_Full);
1877 else
1878 XGBE_SET_ADV(dlks, 1000baseKX_Full);
1879 break;
1880 case XGBE_PORT_MODE_10GBASE_R:
1881 XGBE_SET_ADV(dlks, 10000baseKR_Full);
1882 break;
1883 case XGBE_PORT_MODE_SFP:
1884 switch (phy_data->sfp_base) {
1885 case XGBE_SFP_BASE_1000_T:
1886 case XGBE_SFP_BASE_1000_SX:
1887 case XGBE_SFP_BASE_1000_LX:
1888 case XGBE_SFP_BASE_1000_CX:
1889 XGBE_SET_ADV(dlks, 1000baseKX_Full);
1890 break;
1891 default:
1892 XGBE_SET_ADV(dlks, 10000baseKR_Full);
1893 break;
1894 }
1895 break;
1896 default:
1897 XGBE_SET_ADV(dlks, 10000baseKR_Full);
1898 break;
1899 }
1900}
1901
1902static int xgbe_phy_an_config(struct xgbe_prv_data *pdata)
1903{
1904 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1905 struct xgbe_phy_data *phy_data = pdata->phy_data;
1906 int ret;
1907
1908 ret = xgbe_phy_find_phy_device(pdata);
1909 if (ret)
1910 return ret;
1911
1912 if (!phy_data->phydev)
1913 return 0;
1914
1915 phy_data->phydev->autoneg = pdata->phy.autoneg;
1916 linkmode_and(phy_data->phydev->advertising,
1917 phy_data->phydev->supported,
1918 lks->link_modes.advertising);
1919
1920 if (pdata->phy.autoneg != AUTONEG_ENABLE) {
1921 phy_data->phydev->speed = pdata->phy.speed;
1922 phy_data->phydev->duplex = pdata->phy.duplex;
1923 }
1924
1925 ret = phy_start_aneg(phy_data->phydev);
1926
1927 return ret;
1928}
1929
1930static enum xgbe_an_mode xgbe_phy_an_sfp_mode(struct xgbe_phy_data *phy_data)
1931{
1932 switch (phy_data->sfp_base) {
1933 case XGBE_SFP_BASE_1000_T:
1934 return XGBE_AN_MODE_CL37_SGMII;
1935 case XGBE_SFP_BASE_1000_SX:
1936 case XGBE_SFP_BASE_1000_LX:
1937 case XGBE_SFP_BASE_1000_CX:
1938 return XGBE_AN_MODE_CL37;
1939 default:
1940 return XGBE_AN_MODE_NONE;
1941 }
1942}
1943
1944static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata)
1945{
1946 struct xgbe_phy_data *phy_data = pdata->phy_data;
1947
1948 /* A KR re-driver will always require CL73 AN */
1949 if (phy_data->redrv)
1950 return XGBE_AN_MODE_CL73_REDRV;
1951
1952 switch (phy_data->port_mode) {
1953 case XGBE_PORT_MODE_BACKPLANE:
1954 return XGBE_AN_MODE_CL73;
1955 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
1956 case XGBE_PORT_MODE_BACKPLANE_2500:
1957 return XGBE_AN_MODE_NONE;
1958 case XGBE_PORT_MODE_1000BASE_T:
1959 return XGBE_AN_MODE_CL37_SGMII;
1960 case XGBE_PORT_MODE_1000BASE_X:
1961 return XGBE_AN_MODE_CL37;
1962 case XGBE_PORT_MODE_NBASE_T:
1963 return XGBE_AN_MODE_CL37_SGMII;
1964 case XGBE_PORT_MODE_10GBASE_T:
1965 return XGBE_AN_MODE_CL73;
1966 case XGBE_PORT_MODE_10GBASE_R:
1967 return XGBE_AN_MODE_NONE;
1968 case XGBE_PORT_MODE_SFP:
1969 return xgbe_phy_an_sfp_mode(phy_data);
1970 default:
1971 return XGBE_AN_MODE_NONE;
1972 }
1973}
1974
1975static int xgbe_phy_set_redrv_mode_mdio(struct xgbe_prv_data *pdata,
1976 enum xgbe_phy_redrv_mode mode)
1977{
1978 struct xgbe_phy_data *phy_data = pdata->phy_data;
1979 u16 redrv_reg, redrv_val;
1980
1981 redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000);
1982 redrv_val = (u16)mode;
1983
1984 return pdata->hw_if.write_ext_mii_regs_c22(pdata, phy_data->redrv_addr,
1985 redrv_reg, redrv_val);
1986}
1987
1988static int xgbe_phy_set_redrv_mode_i2c(struct xgbe_prv_data *pdata,
1989 enum xgbe_phy_redrv_mode mode)
1990{
1991 struct xgbe_phy_data *phy_data = pdata->phy_data;
1992 unsigned int redrv_reg;
1993 int ret;
1994
1995 /* Calculate the register to write */
1996 redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000);
1997
1998 ret = xgbe_phy_redrv_write(pdata, redrv_reg, mode);
1999
2000 return ret;
2001}
2002
2003static void xgbe_phy_set_redrv_mode(struct xgbe_prv_data *pdata)
2004{
2005 struct xgbe_phy_data *phy_data = pdata->phy_data;
2006 enum xgbe_phy_redrv_mode mode;
2007 int ret;
2008
2009 if (!phy_data->redrv)
2010 return;
2011
2012 mode = XGBE_PHY_REDRV_MODE_CX;
2013 if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) &&
2014 (phy_data->sfp_base != XGBE_SFP_BASE_1000_CX) &&
2015 (phy_data->sfp_base != XGBE_SFP_BASE_10000_CR))
2016 mode = XGBE_PHY_REDRV_MODE_SR;
2017
2018 ret = xgbe_phy_get_comm_ownership(pdata);
2019 if (ret)
2020 return;
2021
2022 if (phy_data->redrv_if)
2023 xgbe_phy_set_redrv_mode_i2c(pdata, mode);
2024 else
2025 xgbe_phy_set_redrv_mode_mdio(pdata, mode);
2026
2027 xgbe_phy_put_comm_ownership(pdata);
2028}
2029
2030#define MAX_RX_ADAPT_RETRIES 1
2031#define XGBE_PMA_RX_VAL_SIG_MASK (XGBE_PMA_RX_SIG_DET_0_MASK | \
2032 XGBE_PMA_RX_VALID_0_MASK)
2033
2034static void xgbe_set_rx_adap_mode(struct xgbe_prv_data *pdata,
2035 enum xgbe_mode mode)
2036{
2037 if (pdata->rx_adapt_retries++ >= MAX_RX_ADAPT_RETRIES) {
2038 pdata->rx_adapt_retries = 0;
2039 return;
2040 }
2041
2042 xgbe_phy_perform_ratechange(pdata,
2043 mode == XGBE_MODE_KR ?
2044 XGBE_MB_CMD_SET_10G_KR :
2045 XGBE_MB_CMD_SET_10G_SFI,
2046 XGBE_MB_SUBCMD_RX_ADAP);
2047}
2048
2049static void xgbe_rx_adaptation(struct xgbe_prv_data *pdata)
2050{
2051 struct xgbe_phy_data *phy_data = pdata->phy_data;
2052 unsigned int reg;
2053
2054 /* step 2: force PCS to send RX_ADAPT Req to PHY */
2055 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_EQ_CTRL4,
2056 XGBE_PMA_RX_AD_REQ_MASK, XGBE_PMA_RX_AD_REQ_ENABLE);
2057
2058 /* Step 3: Wait for RX_ADAPT ACK from the PHY */
2059 msleep(200);
2060
2061 /* Software polls for coefficient update command (given by local PHY) */
2062 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_PHY_RX_EQ_CEU);
2063
2064 /* Clear the RX_AD_REQ bit */
2065 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_EQ_CTRL4,
2066 XGBE_PMA_RX_AD_REQ_MASK, XGBE_PMA_RX_AD_REQ_DISABLE);
2067
2068 /* Check if coefficient update command is set */
2069 if ((reg & XGBE_PMA_CFF_UPDT_MASK) != XGBE_PMA_CFF_UPDT_MASK)
2070 goto set_mode;
2071
2072 /* Step 4: Check for Block lock */
2073
2074 /* Link status is latched low, so read once to clear
2075 * and then read again to get current state
2076 */
2077 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
2078 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
2079 if (reg & MDIO_STAT1_LSTATUS) {
2080 /* If the block lock is found, update the helpers
2081 * and declare the link up
2082 */
2083 netif_dbg(pdata, link, pdata->netdev, "Block_lock done");
2084 pdata->rx_adapt_done = true;
2085 pdata->mode_set = false;
2086 return;
2087 }
2088
2089set_mode:
2090 xgbe_set_rx_adap_mode(pdata, phy_data->cur_mode);
2091}
2092
2093static void xgbe_phy_rx_adaptation(struct xgbe_prv_data *pdata)
2094{
2095 unsigned int reg;
2096
2097rx_adapt_reinit:
2098 reg = XMDIO_READ_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_LSTS,
2099 XGBE_PMA_RX_VAL_SIG_MASK);
2100
2101 /* step 1: Check for RX_VALID && LF_SIGDET */
2102 if ((reg & XGBE_PMA_RX_VAL_SIG_MASK) != XGBE_PMA_RX_VAL_SIG_MASK) {
2103 netif_dbg(pdata, link, pdata->netdev,
2104 "RX_VALID or LF_SIGDET is unset, issue rrc");
2105 xgbe_phy_rrc(pdata);
2106 if (pdata->rx_adapt_retries++ >= MAX_RX_ADAPT_RETRIES) {
2107 pdata->rx_adapt_retries = 0;
2108 return;
2109 }
2110 goto rx_adapt_reinit;
2111 }
2112
2113 /* perform rx adaptation */
2114 xgbe_rx_adaptation(pdata);
2115}
2116
2117static void xgbe_phy_rx_reset(struct xgbe_prv_data *pdata)
2118{
2119 int reg;
2120
2121 reg = XMDIO_READ_BITS(pdata, MDIO_MMD_PCS, MDIO_PCS_DIGITAL_STAT,
2122 XGBE_PCS_PSEQ_STATE_MASK);
2123 if (reg == XGBE_PCS_PSEQ_STATE_POWER_GOOD) {
2124 /* Mailbox command timed out, reset of RX block is required.
2125 * This can be done by asseting the reset bit and wait for
2126 * its compeletion.
2127 */
2128 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_CTRL1,
2129 XGBE_PMA_RX_RST_0_MASK, XGBE_PMA_RX_RST_0_RESET_ON);
2130 ndelay(20);
2131 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_CTRL1,
2132 XGBE_PMA_RX_RST_0_MASK, XGBE_PMA_RX_RST_0_RESET_OFF);
2133 usleep_range(40, 50);
2134 netif_err(pdata, link, pdata->netdev, "firmware mailbox reset performed\n");
2135 }
2136}
2137
2138static void xgbe_phy_pll_ctrl(struct xgbe_prv_data *pdata, bool enable)
2139{
2140 /* PLL_CTRL feature needs to be enabled for fixed PHY modes (Non-Autoneg) only */
2141 if (pdata->phy.autoneg != AUTONEG_DISABLE)
2142 return;
2143
2144 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_MISC_CTRL0,
2145 XGBE_PMA_PLL_CTRL_MASK,
2146 enable ? XGBE_PMA_PLL_CTRL_ENABLE
2147 : XGBE_PMA_PLL_CTRL_DISABLE);
2148
2149 /* Wait for command to complete */
2150 usleep_range(100, 200);
2151}
2152
2153static void xgbe_phy_perform_ratechange(struct xgbe_prv_data *pdata,
2154 enum xgbe_mb_cmd cmd, enum xgbe_mb_subcmd sub_cmd)
2155{
2156 unsigned int s0 = 0;
2157 unsigned int wait;
2158
2159 /* Disable PLL re-initialization during FW command processing */
2160 xgbe_phy_pll_ctrl(pdata, false);
2161
2162 /* Log if a previous command did not complete */
2163 if (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) {
2164 netif_dbg(pdata, link, pdata->netdev,
2165 "firmware mailbox not ready for command\n");
2166 xgbe_phy_rx_reset(pdata);
2167 }
2168
2169 /* Construct the command */
2170 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, cmd);
2171 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, sub_cmd);
2172
2173 /* Issue the command */
2174 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
2175 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
2176 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
2177
2178 /* Wait for command to complete */
2179 wait = XGBE_RATECHANGE_COUNT;
2180 while (wait--) {
2181 if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS))
2182 goto do_rx_adaptation;
2183
2184 usleep_range(1000, 2000);
2185 }
2186
2187 netif_dbg(pdata, link, pdata->netdev,
2188 "firmware mailbox command did not complete\n");
2189
2190 /* Reset on error */
2191 xgbe_phy_rx_reset(pdata);
2192 goto reenable_pll;
2193
2194do_rx_adaptation:
2195 if (pdata->en_rx_adap && sub_cmd == XGBE_MB_SUBCMD_RX_ADAP &&
2196 (cmd == XGBE_MB_CMD_SET_10G_KR || cmd == XGBE_MB_CMD_SET_10G_SFI)) {
2197 netif_dbg(pdata, link, pdata->netdev,
2198 "Enabling RX adaptation\n");
2199 pdata->mode_set = true;
2200 xgbe_phy_rx_adaptation(pdata);
2201 /* return from here to avoid enabling PLL ctrl
2202 * during adaptation phase
2203 */
2204 return;
2205 }
2206
2207reenable_pll:
2208 /* Enable PLL re-initialization, not needed for PHY Power Off and RRC cmds */
2209 if (cmd != XGBE_MB_CMD_POWER_OFF &&
2210 cmd != XGBE_MB_CMD_RRC)
2211 xgbe_phy_pll_ctrl(pdata, true);
2212}
2213
2214static void xgbe_phy_rrc(struct xgbe_prv_data *pdata)
2215{
2216 /* Receiver Reset Cycle */
2217 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_RRC, XGBE_MB_SUBCMD_NONE);
2218
2219 netif_dbg(pdata, link, pdata->netdev, "receiver reset complete\n");
2220}
2221
2222static void xgbe_phy_power_off(struct xgbe_prv_data *pdata)
2223{
2224 struct xgbe_phy_data *phy_data = pdata->phy_data;
2225
2226 /* Power off */
2227 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_POWER_OFF, XGBE_MB_SUBCMD_NONE);
2228
2229 phy_data->cur_mode = XGBE_MODE_UNKNOWN;
2230
2231 netif_dbg(pdata, link, pdata->netdev, "phy powered off\n");
2232}
2233
2234static bool enable_rx_adap(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2235{
2236 struct xgbe_phy_data *phy_data = pdata->phy_data;
2237 unsigned int ver;
2238
2239 /* Rx-Adaptation is not supported on older platforms(< 0x30H) */
2240 ver = XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER);
2241 if (ver < 0x30)
2242 return false;
2243
2244 /* Re-driver models 4223 && 4227 do not support Rx-Adaptation */
2245 if (phy_data->redrv &&
2246 (phy_data->redrv_model == XGBE_PHY_REDRV_MODEL_4223 ||
2247 phy_data->redrv_model == XGBE_PHY_REDRV_MODEL_4227))
2248 return false;
2249
2250 /* 10G KR mode with AN does not support Rx-Adaptation */
2251 if (mode == XGBE_MODE_KR &&
2252 phy_data->port_mode != XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG)
2253 return false;
2254
2255 pdata->en_rx_adap = 1;
2256 return true;
2257}
2258
2259static void xgbe_phy_sfi_mode(struct xgbe_prv_data *pdata)
2260{
2261 struct xgbe_phy_data *phy_data = pdata->phy_data;
2262
2263 xgbe_phy_set_redrv_mode(pdata);
2264
2265 /* 10G/SFI */
2266 if (phy_data->sfp_cable != XGBE_SFP_CABLE_PASSIVE) {
2267 pdata->en_rx_adap = 0;
2268 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_10G_SFI, XGBE_MB_SUBCMD_ACTIVE);
2269 } else if ((phy_data->sfp_cable == XGBE_SFP_CABLE_PASSIVE) &&
2270 (enable_rx_adap(pdata, XGBE_MODE_SFI))) {
2271 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_10G_SFI,
2272 XGBE_MB_SUBCMD_RX_ADAP);
2273 } else {
2274 if (phy_data->sfp_cable_len <= 1)
2275 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_10G_SFI,
2276 XGBE_MB_SUBCMD_PASSIVE_1M);
2277 else if (phy_data->sfp_cable_len <= 3)
2278 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_10G_SFI,
2279 XGBE_MB_SUBCMD_PASSIVE_3M);
2280 else
2281 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_10G_SFI,
2282 XGBE_MB_SUBCMD_PASSIVE_OTHER);
2283 }
2284
2285 phy_data->cur_mode = XGBE_MODE_SFI;
2286
2287 netif_dbg(pdata, link, pdata->netdev, "10GbE SFI mode set\n");
2288}
2289
2290static void xgbe_phy_x_mode(struct xgbe_prv_data *pdata)
2291{
2292 struct xgbe_phy_data *phy_data = pdata->phy_data;
2293
2294 xgbe_phy_set_redrv_mode(pdata);
2295
2296 /* 1G/X */
2297 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_1G, XGBE_MB_SUBCMD_1G_KX);
2298
2299 phy_data->cur_mode = XGBE_MODE_X;
2300
2301 netif_dbg(pdata, link, pdata->netdev, "1GbE X mode set\n");
2302}
2303
2304static void xgbe_phy_sgmii_1000_mode(struct xgbe_prv_data *pdata)
2305{
2306 struct xgbe_phy_data *phy_data = pdata->phy_data;
2307
2308 xgbe_phy_set_redrv_mode(pdata);
2309
2310 /* 1G/SGMII */
2311 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_1G, XGBE_MB_SUBCMD_1G_SGMII);
2312
2313 phy_data->cur_mode = XGBE_MODE_SGMII_1000;
2314
2315 netif_dbg(pdata, link, pdata->netdev, "1GbE SGMII mode set\n");
2316}
2317
2318static void xgbe_phy_sgmii_100_mode(struct xgbe_prv_data *pdata)
2319{
2320 struct xgbe_phy_data *phy_data = pdata->phy_data;
2321
2322 xgbe_phy_set_redrv_mode(pdata);
2323
2324 /* 100M/SGMII */
2325 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_1G, XGBE_MB_SUBCMD_100MBITS);
2326
2327 phy_data->cur_mode = XGBE_MODE_SGMII_100;
2328
2329 netif_dbg(pdata, link, pdata->netdev, "100MbE SGMII mode set\n");
2330}
2331
2332static void xgbe_phy_sgmii_10_mode(struct xgbe_prv_data *pdata)
2333{
2334 struct xgbe_phy_data *phy_data = pdata->phy_data;
2335
2336 xgbe_phy_set_redrv_mode(pdata);
2337
2338 /* 10M/SGMII */
2339 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_1G, XGBE_MB_SUBCMD_10MBITS);
2340
2341 phy_data->cur_mode = XGBE_MODE_SGMII_10;
2342
2343 netif_dbg(pdata, link, pdata->netdev, "10MbE SGMII mode set\n");
2344}
2345
2346static void xgbe_phy_kr_mode(struct xgbe_prv_data *pdata)
2347{
2348 struct xgbe_phy_data *phy_data = pdata->phy_data;
2349
2350 xgbe_phy_set_redrv_mode(pdata);
2351
2352 /* 10G/KR */
2353 if (enable_rx_adap(pdata, XGBE_MODE_KR))
2354 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_10G_KR,
2355 XGBE_MB_SUBCMD_RX_ADAP);
2356 else
2357 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_10G_KR,
2358 XGBE_MB_SUBCMD_NONE);
2359
2360 phy_data->cur_mode = XGBE_MODE_KR;
2361
2362 netif_dbg(pdata, link, pdata->netdev, "10GbE KR mode set\n");
2363}
2364
2365static void xgbe_phy_kx_2500_mode(struct xgbe_prv_data *pdata)
2366{
2367 struct xgbe_phy_data *phy_data = pdata->phy_data;
2368
2369 xgbe_phy_set_redrv_mode(pdata);
2370
2371 /* 2.5G/KX */
2372 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_2_5G, XGBE_MB_SUBCMD_NONE);
2373
2374 phy_data->cur_mode = XGBE_MODE_KX_2500;
2375
2376 netif_dbg(pdata, link, pdata->netdev, "2.5GbE KX mode set\n");
2377}
2378
2379static void xgbe_phy_kx_1000_mode(struct xgbe_prv_data *pdata)
2380{
2381 struct xgbe_phy_data *phy_data = pdata->phy_data;
2382
2383 xgbe_phy_set_redrv_mode(pdata);
2384
2385 /* 1G/KX */
2386 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_1G, XGBE_MB_SUBCMD_1G_KX);
2387
2388 phy_data->cur_mode = XGBE_MODE_KX_1000;
2389
2390 netif_dbg(pdata, link, pdata->netdev, "1GbE KX mode set\n");
2391}
2392
2393static enum xgbe_mode xgbe_phy_cur_mode(struct xgbe_prv_data *pdata)
2394{
2395 struct xgbe_phy_data *phy_data = pdata->phy_data;
2396
2397 return phy_data->cur_mode;
2398}
2399
2400static enum xgbe_mode xgbe_phy_switch_baset_mode(struct xgbe_prv_data *pdata)
2401{
2402 struct xgbe_phy_data *phy_data = pdata->phy_data;
2403
2404 /* No switching if not 10GBase-T */
2405 if (phy_data->port_mode != XGBE_PORT_MODE_10GBASE_T)
2406 return xgbe_phy_cur_mode(pdata);
2407
2408 switch (xgbe_phy_cur_mode(pdata)) {
2409 case XGBE_MODE_SGMII_10:
2410 case XGBE_MODE_SGMII_100:
2411 case XGBE_MODE_SGMII_1000:
2412 return XGBE_MODE_KR;
2413 case XGBE_MODE_KX_2500:
2414 return XGBE_MODE_SGMII_1000;
2415 case XGBE_MODE_KR:
2416 default:
2417 return XGBE_MODE_KX_2500;
2418 }
2419}
2420
2421static enum xgbe_mode xgbe_phy_switch_bp_2500_mode(struct xgbe_prv_data *pdata)
2422{
2423 return XGBE_MODE_KX_2500;
2424}
2425
2426static enum xgbe_mode xgbe_phy_switch_bp_mode(struct xgbe_prv_data *pdata)
2427{
2428 /* If we are in KR switch to KX, and vice-versa */
2429 switch (xgbe_phy_cur_mode(pdata)) {
2430 case XGBE_MODE_KX_1000:
2431 return XGBE_MODE_KR;
2432 case XGBE_MODE_KR:
2433 default:
2434 return XGBE_MODE_KX_1000;
2435 }
2436}
2437
2438static enum xgbe_mode xgbe_phy_switch_mode(struct xgbe_prv_data *pdata)
2439{
2440 struct xgbe_phy_data *phy_data = pdata->phy_data;
2441
2442 switch (phy_data->port_mode) {
2443 case XGBE_PORT_MODE_BACKPLANE:
2444 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
2445 return xgbe_phy_switch_bp_mode(pdata);
2446 case XGBE_PORT_MODE_BACKPLANE_2500:
2447 return xgbe_phy_switch_bp_2500_mode(pdata);
2448 case XGBE_PORT_MODE_1000BASE_T:
2449 case XGBE_PORT_MODE_NBASE_T:
2450 case XGBE_PORT_MODE_10GBASE_T:
2451 return xgbe_phy_switch_baset_mode(pdata);
2452 case XGBE_PORT_MODE_1000BASE_X:
2453 case XGBE_PORT_MODE_10GBASE_R:
2454 case XGBE_PORT_MODE_SFP:
2455 /* No switching, so just return current mode */
2456 return xgbe_phy_cur_mode(pdata);
2457 default:
2458 return XGBE_MODE_UNKNOWN;
2459 }
2460}
2461
2462static enum xgbe_mode xgbe_phy_get_basex_mode(struct xgbe_phy_data *phy_data,
2463 int speed)
2464{
2465 switch (speed) {
2466 case SPEED_1000:
2467 return XGBE_MODE_X;
2468 case SPEED_10000:
2469 return XGBE_MODE_KR;
2470 default:
2471 return XGBE_MODE_UNKNOWN;
2472 }
2473}
2474
2475static enum xgbe_mode xgbe_phy_get_baset_mode(struct xgbe_phy_data *phy_data,
2476 int speed)
2477{
2478 switch (speed) {
2479 case SPEED_10:
2480 return XGBE_MODE_SGMII_10;
2481 case SPEED_100:
2482 return XGBE_MODE_SGMII_100;
2483 case SPEED_1000:
2484 return XGBE_MODE_SGMII_1000;
2485 case SPEED_2500:
2486 return XGBE_MODE_KX_2500;
2487 case SPEED_10000:
2488 return XGBE_MODE_KR;
2489 default:
2490 return XGBE_MODE_UNKNOWN;
2491 }
2492}
2493
2494static enum xgbe_mode xgbe_phy_get_sfp_mode(struct xgbe_phy_data *phy_data,
2495 int speed)
2496{
2497 switch (speed) {
2498 case SPEED_10:
2499 return XGBE_MODE_SGMII_10;
2500 case SPEED_100:
2501 return XGBE_MODE_SGMII_100;
2502 case SPEED_1000:
2503 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T)
2504 return XGBE_MODE_SGMII_1000;
2505 else
2506 return XGBE_MODE_X;
2507 case SPEED_10000:
2508 case SPEED_UNKNOWN:
2509 return XGBE_MODE_SFI;
2510 default:
2511 return XGBE_MODE_UNKNOWN;
2512 }
2513}
2514
2515static enum xgbe_mode xgbe_phy_get_bp_2500_mode(int speed)
2516{
2517 switch (speed) {
2518 case SPEED_2500:
2519 return XGBE_MODE_KX_2500;
2520 default:
2521 return XGBE_MODE_UNKNOWN;
2522 }
2523}
2524
2525static enum xgbe_mode xgbe_phy_get_bp_mode(int speed)
2526{
2527 switch (speed) {
2528 case SPEED_1000:
2529 return XGBE_MODE_KX_1000;
2530 case SPEED_10000:
2531 return XGBE_MODE_KR;
2532 default:
2533 return XGBE_MODE_UNKNOWN;
2534 }
2535}
2536
2537static enum xgbe_mode xgbe_phy_get_mode(struct xgbe_prv_data *pdata,
2538 int speed)
2539{
2540 struct xgbe_phy_data *phy_data = pdata->phy_data;
2541
2542 switch (phy_data->port_mode) {
2543 case XGBE_PORT_MODE_BACKPLANE:
2544 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
2545 return xgbe_phy_get_bp_mode(speed);
2546 case XGBE_PORT_MODE_BACKPLANE_2500:
2547 return xgbe_phy_get_bp_2500_mode(speed);
2548 case XGBE_PORT_MODE_1000BASE_T:
2549 case XGBE_PORT_MODE_NBASE_T:
2550 case XGBE_PORT_MODE_10GBASE_T:
2551 return xgbe_phy_get_baset_mode(phy_data, speed);
2552 case XGBE_PORT_MODE_1000BASE_X:
2553 case XGBE_PORT_MODE_10GBASE_R:
2554 return xgbe_phy_get_basex_mode(phy_data, speed);
2555 case XGBE_PORT_MODE_SFP:
2556 return xgbe_phy_get_sfp_mode(phy_data, speed);
2557 default:
2558 return XGBE_MODE_UNKNOWN;
2559 }
2560}
2561
2562static void xgbe_phy_set_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2563{
2564 switch (mode) {
2565 case XGBE_MODE_KX_1000:
2566 xgbe_phy_kx_1000_mode(pdata);
2567 break;
2568 case XGBE_MODE_KX_2500:
2569 xgbe_phy_kx_2500_mode(pdata);
2570 break;
2571 case XGBE_MODE_KR:
2572 xgbe_phy_kr_mode(pdata);
2573 break;
2574 case XGBE_MODE_SGMII_10:
2575 xgbe_phy_sgmii_10_mode(pdata);
2576 break;
2577 case XGBE_MODE_SGMII_100:
2578 xgbe_phy_sgmii_100_mode(pdata);
2579 break;
2580 case XGBE_MODE_SGMII_1000:
2581 xgbe_phy_sgmii_1000_mode(pdata);
2582 break;
2583 case XGBE_MODE_X:
2584 xgbe_phy_x_mode(pdata);
2585 break;
2586 case XGBE_MODE_SFI:
2587 xgbe_phy_sfi_mode(pdata);
2588 break;
2589 default:
2590 break;
2591 }
2592}
2593
2594static bool xgbe_phy_check_mode(struct xgbe_prv_data *pdata,
2595 enum xgbe_mode mode, bool advert)
2596{
2597 if (pdata->phy.autoneg == AUTONEG_ENABLE) {
2598 return advert;
2599 } else {
2600 enum xgbe_mode cur_mode;
2601
2602 cur_mode = xgbe_phy_get_mode(pdata, pdata->phy.speed);
2603 if (cur_mode == mode)
2604 return true;
2605 }
2606
2607 return false;
2608}
2609
2610static bool xgbe_phy_use_basex_mode(struct xgbe_prv_data *pdata,
2611 enum xgbe_mode mode)
2612{
2613 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2614
2615 switch (mode) {
2616 case XGBE_MODE_X:
2617 return xgbe_phy_check_mode(pdata, mode,
2618 XGBE_ADV(lks, 1000baseX_Full));
2619 case XGBE_MODE_KR:
2620 return xgbe_phy_check_mode(pdata, mode,
2621 XGBE_ADV(lks, 10000baseKR_Full));
2622 default:
2623 return false;
2624 }
2625}
2626
2627static bool xgbe_phy_use_baset_mode(struct xgbe_prv_data *pdata,
2628 enum xgbe_mode mode)
2629{
2630 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2631
2632 switch (mode) {
2633 case XGBE_MODE_SGMII_10:
2634 return xgbe_phy_check_mode(pdata, mode,
2635 XGBE_ADV(lks, 10baseT_Full));
2636 case XGBE_MODE_SGMII_100:
2637 return xgbe_phy_check_mode(pdata, mode,
2638 XGBE_ADV(lks, 100baseT_Full));
2639 case XGBE_MODE_SGMII_1000:
2640 return xgbe_phy_check_mode(pdata, mode,
2641 XGBE_ADV(lks, 1000baseT_Full));
2642 case XGBE_MODE_KX_2500:
2643 return xgbe_phy_check_mode(pdata, mode,
2644 XGBE_ADV(lks, 2500baseT_Full));
2645 case XGBE_MODE_KR:
2646 return xgbe_phy_check_mode(pdata, mode,
2647 XGBE_ADV(lks, 10000baseT_Full));
2648 default:
2649 return false;
2650 }
2651}
2652
2653static bool xgbe_phy_use_sfp_mode(struct xgbe_prv_data *pdata,
2654 enum xgbe_mode mode)
2655{
2656 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2657 struct xgbe_phy_data *phy_data = pdata->phy_data;
2658
2659 switch (mode) {
2660 case XGBE_MODE_X:
2661 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T)
2662 return false;
2663 return xgbe_phy_check_mode(pdata, mode,
2664 XGBE_ADV(lks, 1000baseX_Full));
2665 case XGBE_MODE_SGMII_10:
2666 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
2667 return false;
2668 return xgbe_phy_check_mode(pdata, mode,
2669 XGBE_ADV(lks, 10baseT_Full));
2670 case XGBE_MODE_SGMII_100:
2671 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
2672 return false;
2673 return xgbe_phy_check_mode(pdata, mode,
2674 XGBE_ADV(lks, 100baseT_Full));
2675 case XGBE_MODE_SGMII_1000:
2676 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
2677 return false;
2678 return xgbe_phy_check_mode(pdata, mode,
2679 XGBE_ADV(lks, 1000baseT_Full));
2680 case XGBE_MODE_SFI:
2681 if (phy_data->sfp_mod_absent)
2682 return true;
2683 return xgbe_phy_check_mode(pdata, mode,
2684 XGBE_ADV(lks, 10000baseSR_Full) ||
2685 XGBE_ADV(lks, 10000baseLR_Full) ||
2686 XGBE_ADV(lks, 10000baseLRM_Full) ||
2687 XGBE_ADV(lks, 10000baseER_Full) ||
2688 XGBE_ADV(lks, 10000baseCR_Full));
2689 default:
2690 return false;
2691 }
2692}
2693
2694static bool xgbe_phy_use_bp_2500_mode(struct xgbe_prv_data *pdata,
2695 enum xgbe_mode mode)
2696{
2697 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2698
2699 switch (mode) {
2700 case XGBE_MODE_KX_2500:
2701 return xgbe_phy_check_mode(pdata, mode,
2702 XGBE_ADV(lks, 2500baseX_Full));
2703 default:
2704 return false;
2705 }
2706}
2707
2708static bool xgbe_phy_use_bp_mode(struct xgbe_prv_data *pdata,
2709 enum xgbe_mode mode)
2710{
2711 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2712
2713 switch (mode) {
2714 case XGBE_MODE_KX_1000:
2715 return xgbe_phy_check_mode(pdata, mode,
2716 XGBE_ADV(lks, 1000baseKX_Full));
2717 case XGBE_MODE_KR:
2718 return xgbe_phy_check_mode(pdata, mode,
2719 XGBE_ADV(lks, 10000baseKR_Full));
2720 default:
2721 return false;
2722 }
2723}
2724
2725static bool xgbe_phy_use_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2726{
2727 struct xgbe_phy_data *phy_data = pdata->phy_data;
2728
2729 switch (phy_data->port_mode) {
2730 case XGBE_PORT_MODE_BACKPLANE:
2731 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
2732 return xgbe_phy_use_bp_mode(pdata, mode);
2733 case XGBE_PORT_MODE_BACKPLANE_2500:
2734 return xgbe_phy_use_bp_2500_mode(pdata, mode);
2735 case XGBE_PORT_MODE_1000BASE_T:
2736 case XGBE_PORT_MODE_NBASE_T:
2737 case XGBE_PORT_MODE_10GBASE_T:
2738 return xgbe_phy_use_baset_mode(pdata, mode);
2739 case XGBE_PORT_MODE_1000BASE_X:
2740 case XGBE_PORT_MODE_10GBASE_R:
2741 return xgbe_phy_use_basex_mode(pdata, mode);
2742 case XGBE_PORT_MODE_SFP:
2743 return xgbe_phy_use_sfp_mode(pdata, mode);
2744 default:
2745 return false;
2746 }
2747}
2748
2749static bool xgbe_phy_valid_speed_basex_mode(struct xgbe_phy_data *phy_data,
2750 int speed)
2751{
2752 switch (speed) {
2753 case SPEED_1000:
2754 return (phy_data->port_mode == XGBE_PORT_MODE_1000BASE_X);
2755 case SPEED_10000:
2756 return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_R);
2757 default:
2758 return false;
2759 }
2760}
2761
2762static bool xgbe_phy_valid_speed_baset_mode(struct xgbe_prv_data *pdata,
2763 int speed)
2764{
2765 struct xgbe_phy_data *phy_data = pdata->phy_data;
2766 unsigned int ver;
2767
2768 switch (speed) {
2769 case SPEED_10:
2770 /* Supported in ver 21H and ver >= 30H */
2771 ver = XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER);
2772 return (ver == 0x21 || ver >= 0x30);
2773 case SPEED_100:
2774 case SPEED_1000:
2775 return true;
2776 case SPEED_2500:
2777 return ((phy_data->port_mode == XGBE_PORT_MODE_10GBASE_T) ||
2778 (phy_data->port_mode == XGBE_PORT_MODE_NBASE_T));
2779 case SPEED_10000:
2780 return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_T);
2781 default:
2782 return false;
2783 }
2784}
2785
2786static bool xgbe_phy_valid_speed_sfp_mode(struct xgbe_prv_data *pdata,
2787 int speed)
2788{
2789 struct xgbe_phy_data *phy_data = pdata->phy_data;
2790 unsigned int ver;
2791
2792 switch (speed) {
2793 case SPEED_10:
2794 /* Supported in ver 21H and ver >= 30H */
2795 ver = XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER);
2796 return ((ver == 0x21 || ver >= 0x30) &&
2797 (phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000));
2798 case SPEED_100:
2799 return (phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000);
2800 case SPEED_1000:
2801 return ((phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000) ||
2802 (phy_data->sfp_speed == XGBE_SFP_SPEED_1000));
2803 case SPEED_10000:
2804 return (phy_data->sfp_speed == XGBE_SFP_SPEED_10000);
2805 default:
2806 return false;
2807 }
2808}
2809
2810static bool xgbe_phy_valid_speed_bp_2500_mode(int speed)
2811{
2812 switch (speed) {
2813 case SPEED_2500:
2814 return true;
2815 default:
2816 return false;
2817 }
2818}
2819
2820static bool xgbe_phy_valid_speed_bp_mode(int speed)
2821{
2822 switch (speed) {
2823 case SPEED_1000:
2824 case SPEED_10000:
2825 return true;
2826 default:
2827 return false;
2828 }
2829}
2830
2831static bool xgbe_phy_valid_speed(struct xgbe_prv_data *pdata, int speed)
2832{
2833 struct xgbe_phy_data *phy_data = pdata->phy_data;
2834
2835 switch (phy_data->port_mode) {
2836 case XGBE_PORT_MODE_BACKPLANE:
2837 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
2838 return xgbe_phy_valid_speed_bp_mode(speed);
2839 case XGBE_PORT_MODE_BACKPLANE_2500:
2840 return xgbe_phy_valid_speed_bp_2500_mode(speed);
2841 case XGBE_PORT_MODE_1000BASE_T:
2842 case XGBE_PORT_MODE_NBASE_T:
2843 case XGBE_PORT_MODE_10GBASE_T:
2844 return xgbe_phy_valid_speed_baset_mode(pdata, speed);
2845 case XGBE_PORT_MODE_1000BASE_X:
2846 case XGBE_PORT_MODE_10GBASE_R:
2847 return xgbe_phy_valid_speed_basex_mode(phy_data, speed);
2848 case XGBE_PORT_MODE_SFP:
2849 return xgbe_phy_valid_speed_sfp_mode(pdata, speed);
2850 default:
2851 return false;
2852 }
2853}
2854
2855static int xgbe_phy_link_status(struct xgbe_prv_data *pdata, int *an_restart)
2856{
2857 struct xgbe_phy_data *phy_data = pdata->phy_data;
2858 unsigned int reg;
2859 int ret;
2860
2861 *an_restart = 0;
2862
2863 if (phy_data->port_mode == XGBE_PORT_MODE_SFP) {
2864 /* Check SFP signals */
2865 xgbe_phy_sfp_detect(pdata);
2866
2867 if (phy_data->sfp_changed) {
2868 *an_restart = 1;
2869 return 0;
2870 }
2871
2872 if (phy_data->sfp_mod_absent || phy_data->sfp_rx_los) {
2873 if (pdata->en_rx_adap)
2874 pdata->rx_adapt_done = false;
2875 return 0;
2876 }
2877 }
2878
2879 if (phy_data->phydev) {
2880 /* Check external PHY */
2881 ret = phy_read_status(phy_data->phydev);
2882 if (ret < 0)
2883 return 0;
2884
2885 if ((pdata->phy.autoneg == AUTONEG_ENABLE) &&
2886 !phy_aneg_done(phy_data->phydev))
2887 return 0;
2888
2889 if (!phy_data->phydev->link)
2890 return 0;
2891 }
2892
2893 /* Link status is latched low, so read once to clear
2894 * and then read again to get current state
2895 */
2896 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
2897 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
2898
2899 if (pdata->en_rx_adap) {
2900 /* if the link is available and adaptation is done,
2901 * declare link up
2902 */
2903 if ((reg & MDIO_STAT1_LSTATUS) && pdata->rx_adapt_done)
2904 return 1;
2905 /* If either link is not available or adaptation is not done,
2906 * retrigger the adaptation logic. (if the mode is not set,
2907 * then issue mailbox command first)
2908 */
2909 if (pdata->mode_set) {
2910 xgbe_phy_rx_adaptation(pdata);
2911 } else {
2912 pdata->rx_adapt_done = false;
2913 xgbe_phy_set_mode(pdata, phy_data->cur_mode);
2914 }
2915
2916 /* check again for the link and adaptation status */
2917 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
2918 if ((reg & MDIO_STAT1_LSTATUS) && pdata->rx_adapt_done)
2919 return 1;
2920 } else if (reg & MDIO_STAT1_LSTATUS)
2921 return 1;
2922
2923 if (pdata->phy.autoneg == AUTONEG_ENABLE &&
2924 phy_data->port_mode == XGBE_PORT_MODE_BACKPLANE) {
2925 if (!test_bit(XGBE_LINK_INIT, &pdata->dev_state)) {
2926 netif_carrier_off(pdata->netdev);
2927 *an_restart = 1;
2928 }
2929 }
2930
2931 /* No link, attempt a receiver reset cycle */
2932 if (pdata->vdata->enable_rrc && phy_data->rrc_count++ > XGBE_RRC_FREQUENCY) {
2933 phy_data->rrc_count = 0;
2934 xgbe_phy_rrc(pdata);
2935 }
2936
2937 return 0;
2938}
2939
2940static void xgbe_phy_sfp_gpio_setup(struct xgbe_prv_data *pdata)
2941{
2942 struct xgbe_phy_data *phy_data = pdata->phy_data;
2943
2944 phy_data->sfp_gpio_address = XGBE_GPIO_ADDRESS_PCA9555 +
2945 XP_GET_BITS(pdata->pp3, XP_PROP_3,
2946 GPIO_ADDR);
2947
2948 phy_data->sfp_gpio_mask = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2949 GPIO_MASK);
2950
2951 phy_data->sfp_gpio_rx_los = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2952 GPIO_RX_LOS);
2953 phy_data->sfp_gpio_tx_fault = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2954 GPIO_TX_FAULT);
2955 phy_data->sfp_gpio_mod_absent = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2956 GPIO_MOD_ABS);
2957 phy_data->sfp_gpio_rate_select = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2958 GPIO_RATE_SELECT);
2959
2960 if (netif_msg_probe(pdata)) {
2961 dev_dbg(pdata->dev, "SFP: gpio_address=%#x\n",
2962 phy_data->sfp_gpio_address);
2963 dev_dbg(pdata->dev, "SFP: gpio_mask=%#x\n",
2964 phy_data->sfp_gpio_mask);
2965 dev_dbg(pdata->dev, "SFP: gpio_rx_los=%u\n",
2966 phy_data->sfp_gpio_rx_los);
2967 dev_dbg(pdata->dev, "SFP: gpio_tx_fault=%u\n",
2968 phy_data->sfp_gpio_tx_fault);
2969 dev_dbg(pdata->dev, "SFP: gpio_mod_absent=%u\n",
2970 phy_data->sfp_gpio_mod_absent);
2971 dev_dbg(pdata->dev, "SFP: gpio_rate_select=%u\n",
2972 phy_data->sfp_gpio_rate_select);
2973 }
2974}
2975
2976static void xgbe_phy_sfp_comm_setup(struct xgbe_prv_data *pdata)
2977{
2978 struct xgbe_phy_data *phy_data = pdata->phy_data;
2979 unsigned int mux_addr_hi, mux_addr_lo;
2980
2981 mux_addr_hi = XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_ADDR_HI);
2982 mux_addr_lo = XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_ADDR_LO);
2983 if (mux_addr_lo == XGBE_SFP_DIRECT)
2984 return;
2985
2986 phy_data->sfp_comm = XGBE_SFP_COMM_PCA9545;
2987 phy_data->sfp_mux_address = (mux_addr_hi << 2) + mux_addr_lo;
2988 phy_data->sfp_mux_channel = XP_GET_BITS(pdata->pp4, XP_PROP_4,
2989 MUX_CHAN);
2990
2991 if (netif_msg_probe(pdata)) {
2992 dev_dbg(pdata->dev, "SFP: mux_address=%#x\n",
2993 phy_data->sfp_mux_address);
2994 dev_dbg(pdata->dev, "SFP: mux_channel=%u\n",
2995 phy_data->sfp_mux_channel);
2996 }
2997}
2998
2999static void xgbe_phy_sfp_setup(struct xgbe_prv_data *pdata)
3000{
3001 xgbe_phy_sfp_comm_setup(pdata);
3002 xgbe_phy_sfp_gpio_setup(pdata);
3003}
3004
3005static int xgbe_phy_int_mdio_reset(struct xgbe_prv_data *pdata)
3006{
3007 struct xgbe_phy_data *phy_data = pdata->phy_data;
3008 unsigned int ret;
3009
3010 ret = pdata->hw_if.set_gpio(pdata, phy_data->mdio_reset_gpio);
3011 if (ret)
3012 return ret;
3013
3014 ret = pdata->hw_if.clr_gpio(pdata, phy_data->mdio_reset_gpio);
3015
3016 return ret;
3017}
3018
3019static int xgbe_phy_i2c_mdio_reset(struct xgbe_prv_data *pdata)
3020{
3021 struct xgbe_phy_data *phy_data = pdata->phy_data;
3022 u8 gpio_reg, gpio_ports[2], gpio_data[3];
3023 int ret;
3024
3025 /* Read the output port registers */
3026 gpio_reg = 2;
3027 ret = xgbe_phy_i2c_read(pdata, phy_data->mdio_reset_addr,
3028 &gpio_reg, sizeof(gpio_reg),
3029 gpio_ports, sizeof(gpio_ports));
3030 if (ret)
3031 return ret;
3032
3033 /* Prepare to write the GPIO data */
3034 gpio_data[0] = 2;
3035 gpio_data[1] = gpio_ports[0];
3036 gpio_data[2] = gpio_ports[1];
3037
3038 /* Set the GPIO pin */
3039 if (phy_data->mdio_reset_gpio < 8)
3040 gpio_data[1] |= (1 << (phy_data->mdio_reset_gpio % 8));
3041 else
3042 gpio_data[2] |= (1 << (phy_data->mdio_reset_gpio % 8));
3043
3044 /* Write the output port registers */
3045 ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr,
3046 gpio_data, sizeof(gpio_data));
3047 if (ret)
3048 return ret;
3049
3050 /* Clear the GPIO pin */
3051 if (phy_data->mdio_reset_gpio < 8)
3052 gpio_data[1] &= ~(1 << (phy_data->mdio_reset_gpio % 8));
3053 else
3054 gpio_data[2] &= ~(1 << (phy_data->mdio_reset_gpio % 8));
3055
3056 /* Write the output port registers */
3057 ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr,
3058 gpio_data, sizeof(gpio_data));
3059
3060 return ret;
3061}
3062
3063static int xgbe_phy_mdio_reset(struct xgbe_prv_data *pdata)
3064{
3065 struct xgbe_phy_data *phy_data = pdata->phy_data;
3066 int ret;
3067
3068 if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO)
3069 return 0;
3070
3071 ret = xgbe_phy_get_comm_ownership(pdata);
3072 if (ret)
3073 return ret;
3074
3075 if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO)
3076 ret = xgbe_phy_i2c_mdio_reset(pdata);
3077 else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO)
3078 ret = xgbe_phy_int_mdio_reset(pdata);
3079
3080 xgbe_phy_put_comm_ownership(pdata);
3081
3082 return ret;
3083}
3084
3085static bool xgbe_phy_redrv_error(struct xgbe_phy_data *phy_data)
3086{
3087 if (!phy_data->redrv)
3088 return false;
3089
3090 if (phy_data->redrv_if >= XGBE_PHY_REDRV_IF_MAX)
3091 return true;
3092
3093 switch (phy_data->redrv_model) {
3094 case XGBE_PHY_REDRV_MODEL_4223:
3095 if (phy_data->redrv_lane > 3)
3096 return true;
3097 break;
3098 case XGBE_PHY_REDRV_MODEL_4227:
3099 if (phy_data->redrv_lane > 1)
3100 return true;
3101 break;
3102 default:
3103 return true;
3104 }
3105
3106 return false;
3107}
3108
3109static int xgbe_phy_mdio_reset_setup(struct xgbe_prv_data *pdata)
3110{
3111 struct xgbe_phy_data *phy_data = pdata->phy_data;
3112
3113 if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO)
3114 return 0;
3115
3116 phy_data->mdio_reset = XP_GET_BITS(pdata->pp3, XP_PROP_3, MDIO_RESET);
3117 switch (phy_data->mdio_reset) {
3118 case XGBE_MDIO_RESET_NONE:
3119 case XGBE_MDIO_RESET_I2C_GPIO:
3120 case XGBE_MDIO_RESET_INT_GPIO:
3121 break;
3122 default:
3123 dev_err(pdata->dev, "unsupported MDIO reset (%#x)\n",
3124 phy_data->mdio_reset);
3125 return -EINVAL;
3126 }
3127
3128 if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO) {
3129 phy_data->mdio_reset_addr = XGBE_GPIO_ADDRESS_PCA9555 +
3130 XP_GET_BITS(pdata->pp3, XP_PROP_3,
3131 MDIO_RESET_I2C_ADDR);
3132 phy_data->mdio_reset_gpio = XP_GET_BITS(pdata->pp3, XP_PROP_3,
3133 MDIO_RESET_I2C_GPIO);
3134 } else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO) {
3135 phy_data->mdio_reset_gpio = XP_GET_BITS(pdata->pp3, XP_PROP_3,
3136 MDIO_RESET_INT_GPIO);
3137 }
3138
3139 return 0;
3140}
3141
3142static bool xgbe_phy_port_mode_mismatch(struct xgbe_prv_data *pdata)
3143{
3144 struct xgbe_phy_data *phy_data = pdata->phy_data;
3145 unsigned int ver;
3146
3147 /* 10 Mbps speed is supported in ver 21H and ver >= 30H */
3148 ver = XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER);
3149 if ((ver < 0x30 && ver != 0x21) && (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10))
3150 return true;
3151
3152 switch (phy_data->port_mode) {
3153 case XGBE_PORT_MODE_BACKPLANE:
3154 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
3155 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
3156 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
3157 return false;
3158 break;
3159 case XGBE_PORT_MODE_BACKPLANE_2500:
3160 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500)
3161 return false;
3162 break;
3163 case XGBE_PORT_MODE_1000BASE_T:
3164 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10) ||
3165 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
3166 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000))
3167 return false;
3168 break;
3169 case XGBE_PORT_MODE_1000BASE_X:
3170 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
3171 return false;
3172 break;
3173 case XGBE_PORT_MODE_NBASE_T:
3174 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10) ||
3175 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
3176 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
3177 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500))
3178 return false;
3179 break;
3180 case XGBE_PORT_MODE_10GBASE_T:
3181 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10) ||
3182 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
3183 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
3184 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500) ||
3185 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
3186 return false;
3187 break;
3188 case XGBE_PORT_MODE_10GBASE_R:
3189 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)
3190 return false;
3191 break;
3192 case XGBE_PORT_MODE_SFP:
3193 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10) ||
3194 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
3195 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
3196 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
3197 return false;
3198 break;
3199 default:
3200 break;
3201 }
3202
3203 return true;
3204}
3205
3206static bool xgbe_phy_conn_type_mismatch(struct xgbe_prv_data *pdata)
3207{
3208 struct xgbe_phy_data *phy_data = pdata->phy_data;
3209
3210 switch (phy_data->port_mode) {
3211 case XGBE_PORT_MODE_BACKPLANE:
3212 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
3213 case XGBE_PORT_MODE_BACKPLANE_2500:
3214 if (phy_data->conn_type == XGBE_CONN_TYPE_BACKPLANE)
3215 return false;
3216 break;
3217 case XGBE_PORT_MODE_1000BASE_T:
3218 case XGBE_PORT_MODE_1000BASE_X:
3219 case XGBE_PORT_MODE_NBASE_T:
3220 case XGBE_PORT_MODE_10GBASE_T:
3221 case XGBE_PORT_MODE_10GBASE_R:
3222 if (phy_data->conn_type == XGBE_CONN_TYPE_MDIO)
3223 return false;
3224 break;
3225 case XGBE_PORT_MODE_SFP:
3226 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
3227 return false;
3228 break;
3229 default:
3230 break;
3231 }
3232
3233 return true;
3234}
3235
3236static bool xgbe_phy_port_enabled(struct xgbe_prv_data *pdata)
3237{
3238 if (!XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_SPEEDS))
3239 return false;
3240 if (!XP_GET_BITS(pdata->pp0, XP_PROP_0, CONN_TYPE))
3241 return false;
3242
3243 return true;
3244}
3245
3246static void xgbe_phy_cdr_track(struct xgbe_prv_data *pdata)
3247{
3248 struct xgbe_phy_data *phy_data = pdata->phy_data;
3249
3250 if (!pdata->debugfs_an_cdr_workaround)
3251 return;
3252
3253 if (!phy_data->phy_cdr_notrack)
3254 return;
3255
3256 usleep_range(phy_data->phy_cdr_delay,
3257 phy_data->phy_cdr_delay + 500);
3258
3259 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL,
3260 XGBE_PMA_CDR_TRACK_EN_MASK,
3261 XGBE_PMA_CDR_TRACK_EN_ON);
3262
3263 phy_data->phy_cdr_notrack = 0;
3264}
3265
3266static void xgbe_phy_cdr_notrack(struct xgbe_prv_data *pdata)
3267{
3268 struct xgbe_phy_data *phy_data = pdata->phy_data;
3269
3270 if (!pdata->debugfs_an_cdr_workaround)
3271 return;
3272
3273 if (phy_data->phy_cdr_notrack)
3274 return;
3275
3276 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL,
3277 XGBE_PMA_CDR_TRACK_EN_MASK,
3278 XGBE_PMA_CDR_TRACK_EN_OFF);
3279
3280 xgbe_phy_rrc(pdata);
3281
3282 phy_data->phy_cdr_notrack = 1;
3283}
3284
3285static void xgbe_phy_kr_training_post(struct xgbe_prv_data *pdata)
3286{
3287 if (!pdata->debugfs_an_cdr_track_early)
3288 xgbe_phy_cdr_track(pdata);
3289}
3290
3291static void xgbe_phy_kr_training_pre(struct xgbe_prv_data *pdata)
3292{
3293 if (pdata->debugfs_an_cdr_track_early)
3294 xgbe_phy_cdr_track(pdata);
3295}
3296
3297static void xgbe_phy_an_post(struct xgbe_prv_data *pdata)
3298{
3299 struct xgbe_phy_data *phy_data = pdata->phy_data;
3300
3301 switch (pdata->an_mode) {
3302 case XGBE_AN_MODE_CL73:
3303 case XGBE_AN_MODE_CL73_REDRV:
3304 if (phy_data->cur_mode != XGBE_MODE_KR)
3305 break;
3306
3307 xgbe_phy_cdr_track(pdata);
3308
3309 switch (pdata->an_result) {
3310 case XGBE_AN_READY:
3311 case XGBE_AN_COMPLETE:
3312 break;
3313 default:
3314 if (phy_data->phy_cdr_delay < XGBE_CDR_DELAY_MAX)
3315 phy_data->phy_cdr_delay += XGBE_CDR_DELAY_INC;
3316 else
3317 phy_data->phy_cdr_delay = XGBE_CDR_DELAY_INIT;
3318 break;
3319 }
3320 break;
3321 default:
3322 break;
3323 }
3324}
3325
3326static void xgbe_phy_an_pre(struct xgbe_prv_data *pdata)
3327{
3328 struct xgbe_phy_data *phy_data = pdata->phy_data;
3329
3330 switch (pdata->an_mode) {
3331 case XGBE_AN_MODE_CL73:
3332 case XGBE_AN_MODE_CL73_REDRV:
3333 if (phy_data->cur_mode != XGBE_MODE_KR)
3334 break;
3335
3336 xgbe_phy_cdr_notrack(pdata);
3337 break;
3338 default:
3339 break;
3340 }
3341}
3342
3343static void xgbe_phy_stop(struct xgbe_prv_data *pdata)
3344{
3345 struct xgbe_phy_data *phy_data = pdata->phy_data;
3346
3347 /* If we have an external PHY, free it */
3348 xgbe_phy_free_phy_device(pdata);
3349
3350 /* Reset SFP data */
3351 xgbe_phy_sfp_reset(phy_data);
3352 xgbe_phy_sfp_mod_absent(pdata);
3353
3354 /* Reset CDR support */
3355 xgbe_phy_cdr_track(pdata);
3356
3357 /* Power off the PHY */
3358 xgbe_phy_power_off(pdata);
3359
3360 /* Stop the I2C controller */
3361 pdata->i2c_if.i2c_stop(pdata);
3362}
3363
3364static int xgbe_phy_start(struct xgbe_prv_data *pdata)
3365{
3366 struct xgbe_phy_data *phy_data = pdata->phy_data;
3367 int ret;
3368
3369 /* Start the I2C controller */
3370 ret = pdata->i2c_if.i2c_start(pdata);
3371 if (ret)
3372 return ret;
3373
3374 /* Set the proper MDIO mode for the re-driver */
3375 if (phy_data->redrv && !phy_data->redrv_if) {
3376 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr,
3377 XGBE_MDIO_MODE_CL22);
3378 if (ret) {
3379 netdev_err(pdata->netdev,
3380 "redriver mdio port not compatible (%u)\n",
3381 phy_data->redrv_addr);
3382 return ret;
3383 }
3384 }
3385
3386 /* Start in highest supported mode */
3387 xgbe_phy_set_mode(pdata, phy_data->start_mode);
3388
3389 /* Reset CDR support */
3390 xgbe_phy_cdr_track(pdata);
3391
3392 /* After starting the I2C controller, we can check for an SFP */
3393 switch (phy_data->port_mode) {
3394 case XGBE_PORT_MODE_SFP:
3395 xgbe_phy_sfp_detect(pdata);
3396 break;
3397 default:
3398 break;
3399 }
3400
3401 /* If we have an external PHY, start it */
3402 ret = xgbe_phy_find_phy_device(pdata);
3403 if (ret)
3404 goto err_i2c;
3405
3406 return 0;
3407
3408err_i2c:
3409 pdata->i2c_if.i2c_stop(pdata);
3410
3411 return ret;
3412}
3413
3414static int xgbe_phy_reset(struct xgbe_prv_data *pdata)
3415{
3416 struct xgbe_phy_data *phy_data = pdata->phy_data;
3417 enum xgbe_mode cur_mode;
3418 int ret;
3419
3420 /* Reset by power cycling the PHY */
3421 cur_mode = phy_data->cur_mode;
3422 xgbe_phy_power_off(pdata);
3423 xgbe_phy_set_mode(pdata, cur_mode);
3424
3425 if (!phy_data->phydev)
3426 return 0;
3427
3428 /* Reset the external PHY */
3429 ret = xgbe_phy_mdio_reset(pdata);
3430 if (ret)
3431 return ret;
3432
3433 return phy_init_hw(phy_data->phydev);
3434}
3435
3436static void xgbe_phy_exit(struct xgbe_prv_data *pdata)
3437{
3438 struct xgbe_phy_data *phy_data = pdata->phy_data;
3439
3440 /* Unregister for driving external PHYs */
3441 mdiobus_unregister(phy_data->mii);
3442}
3443
3444static int xgbe_phy_init(struct xgbe_prv_data *pdata)
3445{
3446 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
3447 struct xgbe_phy_data *phy_data;
3448 struct mii_bus *mii;
3449 int ret;
3450
3451 /* Check if enabled */
3452 if (!xgbe_phy_port_enabled(pdata)) {
3453 dev_info(pdata->dev, "device is not enabled\n");
3454 return -ENODEV;
3455 }
3456
3457 /* Initialize the I2C controller */
3458 ret = pdata->i2c_if.i2c_init(pdata);
3459 if (ret)
3460 return ret;
3461
3462 phy_data = devm_kzalloc(pdata->dev, sizeof(*phy_data), GFP_KERNEL);
3463 if (!phy_data)
3464 return -ENOMEM;
3465 pdata->phy_data = phy_data;
3466
3467 phy_data->port_mode = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_MODE);
3468 phy_data->port_id = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_ID);
3469 phy_data->port_speeds = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_SPEEDS);
3470 phy_data->conn_type = XP_GET_BITS(pdata->pp0, XP_PROP_0, CONN_TYPE);
3471 phy_data->mdio_addr = XP_GET_BITS(pdata->pp0, XP_PROP_0, MDIO_ADDR);
3472 if (netif_msg_probe(pdata)) {
3473 dev_dbg(pdata->dev, "port mode=%u\n", phy_data->port_mode);
3474 dev_dbg(pdata->dev, "port id=%u\n", phy_data->port_id);
3475 dev_dbg(pdata->dev, "port speeds=%#x\n", phy_data->port_speeds);
3476 dev_dbg(pdata->dev, "conn type=%u\n", phy_data->conn_type);
3477 dev_dbg(pdata->dev, "mdio addr=%u\n", phy_data->mdio_addr);
3478 }
3479
3480 phy_data->redrv = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_PRESENT);
3481 phy_data->redrv_if = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_IF);
3482 phy_data->redrv_addr = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_ADDR);
3483 phy_data->redrv_lane = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_LANE);
3484 phy_data->redrv_model = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_MODEL);
3485 if (phy_data->redrv && netif_msg_probe(pdata)) {
3486 dev_dbg(pdata->dev, "redrv present\n");
3487 dev_dbg(pdata->dev, "redrv i/f=%u\n", phy_data->redrv_if);
3488 dev_dbg(pdata->dev, "redrv addr=%#x\n", phy_data->redrv_addr);
3489 dev_dbg(pdata->dev, "redrv lane=%u\n", phy_data->redrv_lane);
3490 dev_dbg(pdata->dev, "redrv model=%u\n", phy_data->redrv_model);
3491 }
3492
3493 /* Validate the connection requested */
3494 if (xgbe_phy_conn_type_mismatch(pdata)) {
3495 dev_err(pdata->dev, "phy mode/connection mismatch (%#x/%#x)\n",
3496 phy_data->port_mode, phy_data->conn_type);
3497 return -EINVAL;
3498 }
3499
3500 /* Validate the mode requested */
3501 if (xgbe_phy_port_mode_mismatch(pdata)) {
3502 dev_err(pdata->dev, "phy mode/speed mismatch (%#x/%#x)\n",
3503 phy_data->port_mode, phy_data->port_speeds);
3504 return -EINVAL;
3505 }
3506
3507 /* Check for and validate MDIO reset support */
3508 ret = xgbe_phy_mdio_reset_setup(pdata);
3509 if (ret)
3510 return ret;
3511
3512 /* Validate the re-driver information */
3513 if (xgbe_phy_redrv_error(phy_data)) {
3514 dev_err(pdata->dev, "phy re-driver settings error\n");
3515 return -EINVAL;
3516 }
3517 pdata->kr_redrv = phy_data->redrv;
3518
3519 /* Indicate current mode is unknown */
3520 phy_data->cur_mode = XGBE_MODE_UNKNOWN;
3521
3522 /* Initialize supported features */
3523 XGBE_ZERO_SUP(lks);
3524
3525 switch (phy_data->port_mode) {
3526 /* Backplane support */
3527 case XGBE_PORT_MODE_BACKPLANE:
3528 XGBE_SET_SUP(lks, Autoneg);
3529 fallthrough;
3530 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
3531 XGBE_SET_SUP(lks, Pause);
3532 XGBE_SET_SUP(lks, Asym_Pause);
3533 XGBE_SET_SUP(lks, Backplane);
3534 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3535 XGBE_SET_SUP(lks, 1000baseKX_Full);
3536 phy_data->start_mode = XGBE_MODE_KX_1000;
3537 }
3538 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
3539 XGBE_SET_SUP(lks, 10000baseKR_Full);
3540 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
3541 XGBE_SET_SUP(lks, 10000baseR_FEC);
3542 phy_data->start_mode = XGBE_MODE_KR;
3543 }
3544
3545 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
3546 break;
3547 case XGBE_PORT_MODE_BACKPLANE_2500:
3548 XGBE_SET_SUP(lks, Pause);
3549 XGBE_SET_SUP(lks, Asym_Pause);
3550 XGBE_SET_SUP(lks, Backplane);
3551 XGBE_SET_SUP(lks, 2500baseX_Full);
3552 phy_data->start_mode = XGBE_MODE_KX_2500;
3553
3554 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
3555 break;
3556
3557 /* MDIO 1GBase-T support */
3558 case XGBE_PORT_MODE_1000BASE_T:
3559 XGBE_SET_SUP(lks, Autoneg);
3560 XGBE_SET_SUP(lks, Pause);
3561 XGBE_SET_SUP(lks, Asym_Pause);
3562 XGBE_SET_SUP(lks, TP);
3563 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10) {
3564 XGBE_SET_SUP(lks, 10baseT_Full);
3565 phy_data->start_mode = XGBE_MODE_SGMII_10;
3566 }
3567 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
3568 XGBE_SET_SUP(lks, 100baseT_Full);
3569 phy_data->start_mode = XGBE_MODE_SGMII_100;
3570 }
3571 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3572 XGBE_SET_SUP(lks, 1000baseT_Full);
3573 phy_data->start_mode = XGBE_MODE_SGMII_1000;
3574 }
3575
3576 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
3577 break;
3578
3579 /* MDIO Base-X support */
3580 case XGBE_PORT_MODE_1000BASE_X:
3581 XGBE_SET_SUP(lks, Autoneg);
3582 XGBE_SET_SUP(lks, Pause);
3583 XGBE_SET_SUP(lks, Asym_Pause);
3584 XGBE_SET_SUP(lks, FIBRE);
3585 XGBE_SET_SUP(lks, 1000baseX_Full);
3586 phy_data->start_mode = XGBE_MODE_X;
3587
3588 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
3589 break;
3590
3591 /* MDIO NBase-T support */
3592 case XGBE_PORT_MODE_NBASE_T:
3593 XGBE_SET_SUP(lks, Autoneg);
3594 XGBE_SET_SUP(lks, Pause);
3595 XGBE_SET_SUP(lks, Asym_Pause);
3596 XGBE_SET_SUP(lks, TP);
3597 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10) {
3598 XGBE_SET_SUP(lks, 10baseT_Full);
3599 phy_data->start_mode = XGBE_MODE_SGMII_10;
3600 }
3601 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
3602 XGBE_SET_SUP(lks, 100baseT_Full);
3603 phy_data->start_mode = XGBE_MODE_SGMII_100;
3604 }
3605 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3606 XGBE_SET_SUP(lks, 1000baseT_Full);
3607 phy_data->start_mode = XGBE_MODE_SGMII_1000;
3608 }
3609 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500) {
3610 XGBE_SET_SUP(lks, 2500baseT_Full);
3611 phy_data->start_mode = XGBE_MODE_KX_2500;
3612 }
3613
3614 phy_data->phydev_mode = XGBE_MDIO_MODE_CL45;
3615 break;
3616
3617 /* 10GBase-T support */
3618 case XGBE_PORT_MODE_10GBASE_T:
3619 XGBE_SET_SUP(lks, Autoneg);
3620 XGBE_SET_SUP(lks, Pause);
3621 XGBE_SET_SUP(lks, Asym_Pause);
3622 XGBE_SET_SUP(lks, TP);
3623 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10) {
3624 XGBE_SET_SUP(lks, 10baseT_Full);
3625 phy_data->start_mode = XGBE_MODE_SGMII_10;
3626 }
3627 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
3628 XGBE_SET_SUP(lks, 100baseT_Full);
3629 phy_data->start_mode = XGBE_MODE_SGMII_100;
3630 }
3631 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3632 XGBE_SET_SUP(lks, 1000baseT_Full);
3633 phy_data->start_mode = XGBE_MODE_SGMII_1000;
3634 }
3635 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500) {
3636 XGBE_SET_SUP(lks, 2500baseT_Full);
3637 phy_data->start_mode = XGBE_MODE_KX_2500;
3638 }
3639 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
3640 XGBE_SET_SUP(lks, 10000baseT_Full);
3641 phy_data->start_mode = XGBE_MODE_KR;
3642 }
3643
3644 phy_data->phydev_mode = XGBE_MDIO_MODE_CL45;
3645 break;
3646
3647 /* 10GBase-R support */
3648 case XGBE_PORT_MODE_10GBASE_R:
3649 XGBE_SET_SUP(lks, Autoneg);
3650 XGBE_SET_SUP(lks, Pause);
3651 XGBE_SET_SUP(lks, Asym_Pause);
3652 XGBE_SET_SUP(lks, FIBRE);
3653 XGBE_SET_SUP(lks, 10000baseSR_Full);
3654 XGBE_SET_SUP(lks, 10000baseLR_Full);
3655 XGBE_SET_SUP(lks, 10000baseLRM_Full);
3656 XGBE_SET_SUP(lks, 10000baseER_Full);
3657 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
3658 XGBE_SET_SUP(lks, 10000baseR_FEC);
3659 phy_data->start_mode = XGBE_MODE_SFI;
3660
3661 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
3662 break;
3663
3664 /* SFP support */
3665 case XGBE_PORT_MODE_SFP:
3666 XGBE_SET_SUP(lks, Autoneg);
3667 XGBE_SET_SUP(lks, Pause);
3668 XGBE_SET_SUP(lks, Asym_Pause);
3669 XGBE_SET_SUP(lks, TP);
3670 XGBE_SET_SUP(lks, FIBRE);
3671 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10)
3672 phy_data->start_mode = XGBE_MODE_SGMII_10;
3673 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100)
3674 phy_data->start_mode = XGBE_MODE_SGMII_100;
3675 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
3676 phy_data->start_mode = XGBE_MODE_SGMII_1000;
3677 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)
3678 phy_data->start_mode = XGBE_MODE_SFI;
3679
3680 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
3681
3682 xgbe_phy_sfp_setup(pdata);
3683 break;
3684 default:
3685 return -EINVAL;
3686 }
3687
3688 if (netif_msg_probe(pdata))
3689 dev_dbg(pdata->dev, "phy supported=0x%*pb\n",
3690 __ETHTOOL_LINK_MODE_MASK_NBITS,
3691 lks->link_modes.supported);
3692
3693 if ((phy_data->conn_type & XGBE_CONN_TYPE_MDIO) &&
3694 (phy_data->phydev_mode != XGBE_MDIO_MODE_NONE)) {
3695 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr,
3696 phy_data->phydev_mode);
3697 if (ret) {
3698 dev_err(pdata->dev,
3699 "mdio port/clause not compatible (%d/%u)\n",
3700 phy_data->mdio_addr, phy_data->phydev_mode);
3701 return -EINVAL;
3702 }
3703 }
3704
3705 if (phy_data->redrv && !phy_data->redrv_if) {
3706 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr,
3707 XGBE_MDIO_MODE_CL22);
3708 if (ret) {
3709 dev_err(pdata->dev,
3710 "redriver mdio port not compatible (%u)\n",
3711 phy_data->redrv_addr);
3712 return -EINVAL;
3713 }
3714 }
3715
3716 phy_data->phy_cdr_delay = XGBE_CDR_DELAY_INIT;
3717
3718 /* Register for driving external PHYs */
3719 mii = devm_mdiobus_alloc(pdata->dev);
3720 if (!mii) {
3721 dev_err(pdata->dev, "mdiobus_alloc failed\n");
3722 return -ENOMEM;
3723 }
3724
3725 mii->priv = pdata;
3726 mii->name = "amd-xgbe-mii";
3727 mii->read = xgbe_phy_mii_read_c22;
3728 mii->write = xgbe_phy_mii_write_c22;
3729 mii->read_c45 = xgbe_phy_mii_read_c45;
3730 mii->write_c45 = xgbe_phy_mii_write_c45;
3731 mii->parent = pdata->dev;
3732 mii->phy_mask = ~0;
3733 snprintf(mii->id, sizeof(mii->id), "%s", dev_name(pdata->dev));
3734 ret = mdiobus_register(mii);
3735 if (ret) {
3736 dev_err(pdata->dev, "mdiobus_register failed\n");
3737 return ret;
3738 }
3739 phy_data->mii = mii;
3740
3741 return 0;
3742}
3743
3744void xgbe_init_function_ptrs_phy_v2(struct xgbe_phy_if *phy_if)
3745{
3746 struct xgbe_phy_impl_if *phy_impl = &phy_if->phy_impl;
3747
3748 phy_impl->init = xgbe_phy_init;
3749 phy_impl->exit = xgbe_phy_exit;
3750
3751 phy_impl->reset = xgbe_phy_reset;
3752 phy_impl->start = xgbe_phy_start;
3753 phy_impl->stop = xgbe_phy_stop;
3754
3755 phy_impl->link_status = xgbe_phy_link_status;
3756
3757 phy_impl->valid_speed = xgbe_phy_valid_speed;
3758
3759 phy_impl->use_mode = xgbe_phy_use_mode;
3760 phy_impl->set_mode = xgbe_phy_set_mode;
3761 phy_impl->get_mode = xgbe_phy_get_mode;
3762 phy_impl->switch_mode = xgbe_phy_switch_mode;
3763 phy_impl->cur_mode = xgbe_phy_cur_mode;
3764
3765 phy_impl->an_mode = xgbe_phy_an_mode;
3766
3767 phy_impl->an_config = xgbe_phy_an_config;
3768
3769 phy_impl->an_advertising = xgbe_phy_an_advertising;
3770
3771 phy_impl->an_outcome = xgbe_phy_an_outcome;
3772
3773 phy_impl->an_pre = xgbe_phy_an_pre;
3774 phy_impl->an_post = xgbe_phy_an_post;
3775
3776 phy_impl->kr_training_pre = xgbe_phy_kr_training_pre;
3777 phy_impl->kr_training_post = xgbe_phy_kr_training_post;
3778
3779 phy_impl->module_info = xgbe_phy_module_info;
3780 phy_impl->module_eeprom = xgbe_phy_module_eeprom;
3781}