Loading...
1// SPDX-License-Identifier: GPL-2.0+
2//
3// MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
4// Copyright 2008 Juergen Beisert, kernel@pengutronix.de
5//
6// Based on code from Freescale Semiconductor,
7// Authors: Daniel Mack, Juergen Beisert.
8// Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
9
10#include <linux/clk.h>
11#include <linux/err.h>
12#include <linux/init.h>
13#include <linux/interrupt.h>
14#include <linux/io.h>
15#include <linux/irq.h>
16#include <linux/irqdomain.h>
17#include <linux/irqchip/chained_irq.h>
18#include <linux/module.h>
19#include <linux/platform_device.h>
20#include <linux/pm_runtime.h>
21#include <linux/slab.h>
22#include <linux/spinlock.h>
23#include <linux/syscore_ops.h>
24#include <linux/gpio/driver.h>
25#include <linux/of.h>
26#include <linux/bug.h>
27
28#define IMX_SCU_WAKEUP_OFF 0
29#define IMX_SCU_WAKEUP_LOW_LVL 4
30#define IMX_SCU_WAKEUP_FALL_EDGE 5
31#define IMX_SCU_WAKEUP_RISE_EDGE 6
32#define IMX_SCU_WAKEUP_HIGH_LVL 7
33
34/* device type dependent stuff */
35struct mxc_gpio_hwdata {
36 unsigned dr_reg;
37 unsigned gdir_reg;
38 unsigned psr_reg;
39 unsigned icr1_reg;
40 unsigned icr2_reg;
41 unsigned imr_reg;
42 unsigned isr_reg;
43 int edge_sel_reg;
44 unsigned low_level;
45 unsigned high_level;
46 unsigned rise_edge;
47 unsigned fall_edge;
48};
49
50struct mxc_gpio_reg_saved {
51 u32 icr1;
52 u32 icr2;
53 u32 imr;
54 u32 gdir;
55 u32 edge_sel;
56 u32 dr;
57};
58
59struct mxc_gpio_port {
60 struct list_head node;
61 void __iomem *base;
62 struct clk *clk;
63 int irq;
64 int irq_high;
65 void (*mx_irq_handler)(struct irq_desc *desc);
66 struct irq_domain *domain;
67 struct gpio_chip gc;
68 struct device *dev;
69 u32 both_edges;
70 struct mxc_gpio_reg_saved gpio_saved_reg;
71 bool power_off;
72 u32 wakeup_pads;
73 bool is_pad_wakeup;
74 u32 pad_type[32];
75 const struct mxc_gpio_hwdata *hwdata;
76};
77
78static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata = {
79 .dr_reg = 0x1c,
80 .gdir_reg = 0x00,
81 .psr_reg = 0x24,
82 .icr1_reg = 0x28,
83 .icr2_reg = 0x2c,
84 .imr_reg = 0x30,
85 .isr_reg = 0x34,
86 .edge_sel_reg = -EINVAL,
87 .low_level = 0x03,
88 .high_level = 0x02,
89 .rise_edge = 0x00,
90 .fall_edge = 0x01,
91};
92
93static struct mxc_gpio_hwdata imx31_gpio_hwdata = {
94 .dr_reg = 0x00,
95 .gdir_reg = 0x04,
96 .psr_reg = 0x08,
97 .icr1_reg = 0x0c,
98 .icr2_reg = 0x10,
99 .imr_reg = 0x14,
100 .isr_reg = 0x18,
101 .edge_sel_reg = -EINVAL,
102 .low_level = 0x00,
103 .high_level = 0x01,
104 .rise_edge = 0x02,
105 .fall_edge = 0x03,
106};
107
108static struct mxc_gpio_hwdata imx35_gpio_hwdata = {
109 .dr_reg = 0x00,
110 .gdir_reg = 0x04,
111 .psr_reg = 0x08,
112 .icr1_reg = 0x0c,
113 .icr2_reg = 0x10,
114 .imr_reg = 0x14,
115 .isr_reg = 0x18,
116 .edge_sel_reg = 0x1c,
117 .low_level = 0x00,
118 .high_level = 0x01,
119 .rise_edge = 0x02,
120 .fall_edge = 0x03,
121};
122
123#define GPIO_DR (port->hwdata->dr_reg)
124#define GPIO_GDIR (port->hwdata->gdir_reg)
125#define GPIO_PSR (port->hwdata->psr_reg)
126#define GPIO_ICR1 (port->hwdata->icr1_reg)
127#define GPIO_ICR2 (port->hwdata->icr2_reg)
128#define GPIO_IMR (port->hwdata->imr_reg)
129#define GPIO_ISR (port->hwdata->isr_reg)
130#define GPIO_EDGE_SEL (port->hwdata->edge_sel_reg)
131
132#define GPIO_INT_LOW_LEV (port->hwdata->low_level)
133#define GPIO_INT_HIGH_LEV (port->hwdata->high_level)
134#define GPIO_INT_RISE_EDGE (port->hwdata->rise_edge)
135#define GPIO_INT_FALL_EDGE (port->hwdata->fall_edge)
136#define GPIO_INT_BOTH_EDGES 0x4
137
138static const struct of_device_id mxc_gpio_dt_ids[] = {
139 { .compatible = "fsl,imx1-gpio", .data = &imx1_imx21_gpio_hwdata },
140 { .compatible = "fsl,imx21-gpio", .data = &imx1_imx21_gpio_hwdata },
141 { .compatible = "fsl,imx31-gpio", .data = &imx31_gpio_hwdata },
142 { .compatible = "fsl,imx35-gpio", .data = &imx35_gpio_hwdata },
143 { .compatible = "fsl,imx7d-gpio", .data = &imx35_gpio_hwdata },
144 { .compatible = "fsl,imx8dxl-gpio", .data = &imx35_gpio_hwdata },
145 { .compatible = "fsl,imx8qm-gpio", .data = &imx35_gpio_hwdata },
146 { .compatible = "fsl,imx8qxp-gpio", .data = &imx35_gpio_hwdata },
147 { /* sentinel */ }
148};
149MODULE_DEVICE_TABLE(of, mxc_gpio_dt_ids);
150
151/*
152 * MX2 has one interrupt *for all* gpio ports. The list is used
153 * to save the references to all ports, so that mx2_gpio_irq_handler
154 * can walk through all interrupt status registers.
155 */
156static LIST_HEAD(mxc_gpio_ports);
157
158/* Note: This driver assumes 32 GPIOs are handled in one register */
159
160static int gpio_set_irq_type(struct irq_data *d, u32 type)
161{
162 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
163 struct mxc_gpio_port *port = gc->private;
164 unsigned long flags;
165 u32 bit, val;
166 u32 gpio_idx = d->hwirq;
167 int edge;
168 void __iomem *reg = port->base;
169
170 port->both_edges &= ~(1 << gpio_idx);
171 switch (type) {
172 case IRQ_TYPE_EDGE_RISING:
173 edge = GPIO_INT_RISE_EDGE;
174 break;
175 case IRQ_TYPE_EDGE_FALLING:
176 edge = GPIO_INT_FALL_EDGE;
177 break;
178 case IRQ_TYPE_EDGE_BOTH:
179 if (GPIO_EDGE_SEL >= 0) {
180 edge = GPIO_INT_BOTH_EDGES;
181 } else {
182 val = port->gc.get(&port->gc, gpio_idx);
183 if (val) {
184 edge = GPIO_INT_LOW_LEV;
185 pr_debug("mxc: set GPIO %d to low trigger\n", gpio_idx);
186 } else {
187 edge = GPIO_INT_HIGH_LEV;
188 pr_debug("mxc: set GPIO %d to high trigger\n", gpio_idx);
189 }
190 port->both_edges |= 1 << gpio_idx;
191 }
192 break;
193 case IRQ_TYPE_LEVEL_LOW:
194 edge = GPIO_INT_LOW_LEV;
195 break;
196 case IRQ_TYPE_LEVEL_HIGH:
197 edge = GPIO_INT_HIGH_LEV;
198 break;
199 default:
200 return -EINVAL;
201 }
202
203 raw_spin_lock_irqsave(&port->gc.bgpio_lock, flags);
204
205 if (GPIO_EDGE_SEL >= 0) {
206 val = readl(port->base + GPIO_EDGE_SEL);
207 if (edge == GPIO_INT_BOTH_EDGES)
208 writel(val | (1 << gpio_idx),
209 port->base + GPIO_EDGE_SEL);
210 else
211 writel(val & ~(1 << gpio_idx),
212 port->base + GPIO_EDGE_SEL);
213 }
214
215 if (edge != GPIO_INT_BOTH_EDGES) {
216 reg += GPIO_ICR1 + ((gpio_idx & 0x10) >> 2); /* lower or upper register */
217 bit = gpio_idx & 0xf;
218 val = readl(reg) & ~(0x3 << (bit << 1));
219 writel(val | (edge << (bit << 1)), reg);
220 }
221
222 writel(1 << gpio_idx, port->base + GPIO_ISR);
223 port->pad_type[gpio_idx] = type;
224
225 raw_spin_unlock_irqrestore(&port->gc.bgpio_lock, flags);
226
227 return port->gc.direction_input(&port->gc, gpio_idx);
228}
229
230static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
231{
232 void __iomem *reg = port->base;
233 unsigned long flags;
234 u32 bit, val;
235 int edge;
236
237 raw_spin_lock_irqsave(&port->gc.bgpio_lock, flags);
238
239 reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
240 bit = gpio & 0xf;
241 val = readl(reg);
242 edge = (val >> (bit << 1)) & 3;
243 val &= ~(0x3 << (bit << 1));
244 if (edge == GPIO_INT_HIGH_LEV) {
245 edge = GPIO_INT_LOW_LEV;
246 pr_debug("mxc: switch GPIO %d to low trigger\n", gpio);
247 } else if (edge == GPIO_INT_LOW_LEV) {
248 edge = GPIO_INT_HIGH_LEV;
249 pr_debug("mxc: switch GPIO %d to high trigger\n", gpio);
250 } else {
251 pr_err("mxc: invalid configuration for GPIO %d: %x\n",
252 gpio, edge);
253 goto unlock;
254 }
255 writel(val | (edge << (bit << 1)), reg);
256
257unlock:
258 raw_spin_unlock_irqrestore(&port->gc.bgpio_lock, flags);
259}
260
261/* handle 32 interrupts in one status register */
262static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
263{
264 while (irq_stat != 0) {
265 int irqoffset = fls(irq_stat) - 1;
266
267 if (port->both_edges & (1 << irqoffset))
268 mxc_flip_edge(port, irqoffset);
269
270 generic_handle_domain_irq(port->domain, irqoffset);
271
272 irq_stat &= ~(1 << irqoffset);
273 }
274}
275
276/* MX1 and MX3 has one interrupt *per* gpio port */
277static void mx3_gpio_irq_handler(struct irq_desc *desc)
278{
279 u32 irq_stat;
280 struct mxc_gpio_port *port = irq_desc_get_handler_data(desc);
281 struct irq_chip *chip = irq_desc_get_chip(desc);
282
283 if (port->is_pad_wakeup)
284 return;
285
286 chained_irq_enter(chip, desc);
287
288 irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR);
289
290 mxc_gpio_irq_handler(port, irq_stat);
291
292 chained_irq_exit(chip, desc);
293}
294
295/* MX2 has one interrupt *for all* gpio ports */
296static void mx2_gpio_irq_handler(struct irq_desc *desc)
297{
298 u32 irq_msk, irq_stat;
299 struct mxc_gpio_port *port;
300 struct irq_chip *chip = irq_desc_get_chip(desc);
301
302 chained_irq_enter(chip, desc);
303
304 /* walk through all interrupt status registers */
305 list_for_each_entry(port, &mxc_gpio_ports, node) {
306 irq_msk = readl(port->base + GPIO_IMR);
307 if (!irq_msk)
308 continue;
309
310 irq_stat = readl(port->base + GPIO_ISR) & irq_msk;
311 if (irq_stat)
312 mxc_gpio_irq_handler(port, irq_stat);
313 }
314 chained_irq_exit(chip, desc);
315}
316
317/*
318 * Set interrupt number "irq" in the GPIO as a wake-up source.
319 * While system is running, all registered GPIO interrupts need to have
320 * wake-up enabled. When system is suspended, only selected GPIO interrupts
321 * need to have wake-up enabled.
322 * @param irq interrupt source number
323 * @param enable enable as wake-up if equal to non-zero
324 * @return This function returns 0 on success.
325 */
326static int gpio_set_wake_irq(struct irq_data *d, u32 enable)
327{
328 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
329 struct mxc_gpio_port *port = gc->private;
330 u32 gpio_idx = d->hwirq;
331 int ret;
332
333 if (enable) {
334 if (port->irq_high && (gpio_idx >= 16))
335 ret = enable_irq_wake(port->irq_high);
336 else
337 ret = enable_irq_wake(port->irq);
338 port->wakeup_pads |= (1 << gpio_idx);
339 } else {
340 if (port->irq_high && (gpio_idx >= 16))
341 ret = disable_irq_wake(port->irq_high);
342 else
343 ret = disable_irq_wake(port->irq);
344 port->wakeup_pads &= ~(1 << gpio_idx);
345 }
346
347 return ret;
348}
349
350static int mxc_gpio_init_gc(struct mxc_gpio_port *port, int irq_base)
351{
352 struct irq_chip_generic *gc;
353 struct irq_chip_type *ct;
354 int rv;
355
356 gc = devm_irq_alloc_generic_chip(port->dev, "gpio-mxc", 1, irq_base,
357 port->base, handle_level_irq);
358 if (!gc)
359 return -ENOMEM;
360 gc->private = port;
361
362 ct = gc->chip_types;
363 ct->chip.irq_ack = irq_gc_ack_set_bit;
364 ct->chip.irq_mask = irq_gc_mask_clr_bit;
365 ct->chip.irq_unmask = irq_gc_mask_set_bit;
366 ct->chip.irq_set_type = gpio_set_irq_type;
367 ct->chip.irq_set_wake = gpio_set_wake_irq;
368 ct->chip.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND;
369 ct->regs.ack = GPIO_ISR;
370 ct->regs.mask = GPIO_IMR;
371
372 rv = devm_irq_setup_generic_chip(port->dev, gc, IRQ_MSK(32),
373 IRQ_GC_INIT_NESTED_LOCK,
374 IRQ_NOREQUEST, 0);
375
376 return rv;
377}
378
379static int mxc_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
380{
381 struct mxc_gpio_port *port = gpiochip_get_data(gc);
382
383 return irq_find_mapping(port->domain, offset);
384}
385
386static int mxc_gpio_request(struct gpio_chip *chip, unsigned int offset)
387{
388 int ret;
389
390 ret = gpiochip_generic_request(chip, offset);
391 if (ret)
392 return ret;
393
394 return pm_runtime_resume_and_get(chip->parent);
395}
396
397static void mxc_gpio_free(struct gpio_chip *chip, unsigned int offset)
398{
399 gpiochip_generic_free(chip, offset);
400 pm_runtime_put(chip->parent);
401}
402
403static void mxc_update_irq_chained_handler(struct mxc_gpio_port *port, bool enable)
404{
405 if (enable)
406 irq_set_chained_handler_and_data(port->irq, port->mx_irq_handler, port);
407 else
408 irq_set_chained_handler_and_data(port->irq, NULL, NULL);
409
410 /* setup handler for GPIO 16 to 31 */
411 if (port->irq_high > 0) {
412 if (enable)
413 irq_set_chained_handler_and_data(port->irq_high,
414 port->mx_irq_handler,
415 port);
416 else
417 irq_set_chained_handler_and_data(port->irq_high, NULL, NULL);
418 }
419}
420
421static int mxc_gpio_probe(struct platform_device *pdev)
422{
423 struct device_node *np = pdev->dev.of_node;
424 struct mxc_gpio_port *port;
425 int irq_count;
426 int irq_base;
427 int err;
428
429 port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
430 if (!port)
431 return -ENOMEM;
432
433 port->dev = &pdev->dev;
434 port->hwdata = device_get_match_data(&pdev->dev);
435
436 port->base = devm_platform_ioremap_resource(pdev, 0);
437 if (IS_ERR(port->base))
438 return PTR_ERR(port->base);
439
440 irq_count = platform_irq_count(pdev);
441 if (irq_count < 0)
442 return irq_count;
443
444 if (irq_count > 1) {
445 port->irq_high = platform_get_irq(pdev, 1);
446 if (port->irq_high < 0)
447 port->irq_high = 0;
448 }
449
450 port->irq = platform_get_irq(pdev, 0);
451 if (port->irq < 0)
452 return port->irq;
453
454 /* the controller clock is optional */
455 port->clk = devm_clk_get_optional_enabled(&pdev->dev, NULL);
456 if (IS_ERR(port->clk))
457 return PTR_ERR(port->clk);
458
459 if (of_device_is_compatible(np, "fsl,imx7d-gpio"))
460 port->power_off = true;
461
462 pm_runtime_get_noresume(&pdev->dev);
463 pm_runtime_set_active(&pdev->dev);
464 pm_runtime_enable(&pdev->dev);
465
466 /* disable the interrupt and clear the status */
467 writel(0, port->base + GPIO_IMR);
468 writel(~0, port->base + GPIO_ISR);
469
470 if (of_device_is_compatible(np, "fsl,imx21-gpio")) {
471 /*
472 * Setup one handler for all GPIO interrupts. Actually setting
473 * the handler is needed only once, but doing it for every port
474 * is more robust and easier.
475 */
476 port->irq_high = -1;
477 port->mx_irq_handler = mx2_gpio_irq_handler;
478 } else
479 port->mx_irq_handler = mx3_gpio_irq_handler;
480
481 mxc_update_irq_chained_handler(port, true);
482 err = bgpio_init(&port->gc, &pdev->dev, 4,
483 port->base + GPIO_PSR,
484 port->base + GPIO_DR, NULL,
485 port->base + GPIO_GDIR, NULL,
486 BGPIOF_READ_OUTPUT_REG_SET);
487 if (err)
488 goto out_bgio;
489
490 port->gc.request = mxc_gpio_request;
491 port->gc.free = mxc_gpio_free;
492 port->gc.to_irq = mxc_gpio_to_irq;
493 port->gc.base = of_alias_get_id(np, "gpio") * 32;
494
495 err = devm_gpiochip_add_data(&pdev->dev, &port->gc, port);
496 if (err)
497 goto out_bgio;
498
499 irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, 32, numa_node_id());
500 if (irq_base < 0) {
501 err = irq_base;
502 goto out_bgio;
503 }
504
505 port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
506 &irq_domain_simple_ops, NULL);
507 if (!port->domain) {
508 err = -ENODEV;
509 goto out_bgio;
510 }
511
512 irq_domain_set_pm_device(port->domain, &pdev->dev);
513
514 /* gpio-mxc can be a generic irq chip */
515 err = mxc_gpio_init_gc(port, irq_base);
516 if (err < 0)
517 goto out_irqdomain_remove;
518
519 list_add_tail(&port->node, &mxc_gpio_ports);
520
521 platform_set_drvdata(pdev, port);
522 pm_runtime_put_autosuspend(&pdev->dev);
523
524 return 0;
525
526out_irqdomain_remove:
527 irq_domain_remove(port->domain);
528out_bgio:
529 pm_runtime_disable(&pdev->dev);
530 pm_runtime_put_noidle(&pdev->dev);
531 dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err);
532 return err;
533}
534
535static void mxc_gpio_save_regs(struct mxc_gpio_port *port)
536{
537 if (!port->power_off)
538 return;
539
540 port->gpio_saved_reg.icr1 = readl(port->base + GPIO_ICR1);
541 port->gpio_saved_reg.icr2 = readl(port->base + GPIO_ICR2);
542 port->gpio_saved_reg.imr = readl(port->base + GPIO_IMR);
543 port->gpio_saved_reg.gdir = readl(port->base + GPIO_GDIR);
544 port->gpio_saved_reg.edge_sel = readl(port->base + GPIO_EDGE_SEL);
545 port->gpio_saved_reg.dr = readl(port->base + GPIO_DR);
546}
547
548static void mxc_gpio_restore_regs(struct mxc_gpio_port *port)
549{
550 if (!port->power_off)
551 return;
552
553 writel(port->gpio_saved_reg.icr1, port->base + GPIO_ICR1);
554 writel(port->gpio_saved_reg.icr2, port->base + GPIO_ICR2);
555 writel(port->gpio_saved_reg.imr, port->base + GPIO_IMR);
556 writel(port->gpio_saved_reg.gdir, port->base + GPIO_GDIR);
557 writel(port->gpio_saved_reg.edge_sel, port->base + GPIO_EDGE_SEL);
558 writel(port->gpio_saved_reg.dr, port->base + GPIO_DR);
559}
560
561static bool mxc_gpio_generic_config(struct mxc_gpio_port *port,
562 unsigned int offset, unsigned long conf)
563{
564 struct device_node *np = port->dev->of_node;
565
566 if (of_device_is_compatible(np, "fsl,imx8dxl-gpio") ||
567 of_device_is_compatible(np, "fsl,imx8qxp-gpio") ||
568 of_device_is_compatible(np, "fsl,imx8qm-gpio"))
569 return (gpiochip_generic_config(&port->gc, offset, conf) == 0);
570
571 return false;
572}
573
574static bool mxc_gpio_set_pad_wakeup(struct mxc_gpio_port *port, bool enable)
575{
576 unsigned long config;
577 bool ret = false;
578 int i, type;
579
580 static const u32 pad_type_map[] = {
581 IMX_SCU_WAKEUP_OFF, /* 0 */
582 IMX_SCU_WAKEUP_RISE_EDGE, /* IRQ_TYPE_EDGE_RISING */
583 IMX_SCU_WAKEUP_FALL_EDGE, /* IRQ_TYPE_EDGE_FALLING */
584 IMX_SCU_WAKEUP_FALL_EDGE, /* IRQ_TYPE_EDGE_BOTH */
585 IMX_SCU_WAKEUP_HIGH_LVL, /* IRQ_TYPE_LEVEL_HIGH */
586 IMX_SCU_WAKEUP_OFF, /* 5 */
587 IMX_SCU_WAKEUP_OFF, /* 6 */
588 IMX_SCU_WAKEUP_OFF, /* 7 */
589 IMX_SCU_WAKEUP_LOW_LVL, /* IRQ_TYPE_LEVEL_LOW */
590 };
591
592 for (i = 0; i < 32; i++) {
593 if ((port->wakeup_pads & (1 << i))) {
594 type = port->pad_type[i];
595 if (enable)
596 config = pad_type_map[type];
597 else
598 config = IMX_SCU_WAKEUP_OFF;
599 ret |= mxc_gpio_generic_config(port, i, config);
600 }
601 }
602
603 return ret;
604}
605
606static int mxc_gpio_runtime_suspend(struct device *dev)
607{
608 struct mxc_gpio_port *port = dev_get_drvdata(dev);
609
610 mxc_gpio_save_regs(port);
611 clk_disable_unprepare(port->clk);
612 mxc_update_irq_chained_handler(port, false);
613
614 return 0;
615}
616
617static int mxc_gpio_runtime_resume(struct device *dev)
618{
619 struct mxc_gpio_port *port = dev_get_drvdata(dev);
620 int ret;
621
622 mxc_update_irq_chained_handler(port, true);
623 ret = clk_prepare_enable(port->clk);
624 if (ret) {
625 mxc_update_irq_chained_handler(port, false);
626 return ret;
627 }
628
629 mxc_gpio_restore_regs(port);
630
631 return 0;
632}
633
634static int mxc_gpio_noirq_suspend(struct device *dev)
635{
636 struct platform_device *pdev = to_platform_device(dev);
637 struct mxc_gpio_port *port = platform_get_drvdata(pdev);
638
639 if (port->wakeup_pads > 0)
640 port->is_pad_wakeup = mxc_gpio_set_pad_wakeup(port, true);
641
642 return 0;
643}
644
645static int mxc_gpio_noirq_resume(struct device *dev)
646{
647 struct platform_device *pdev = to_platform_device(dev);
648 struct mxc_gpio_port *port = platform_get_drvdata(pdev);
649
650 if (port->wakeup_pads > 0)
651 mxc_gpio_set_pad_wakeup(port, false);
652 port->is_pad_wakeup = false;
653
654 return 0;
655}
656
657static const struct dev_pm_ops mxc_gpio_dev_pm_ops = {
658 NOIRQ_SYSTEM_SLEEP_PM_OPS(mxc_gpio_noirq_suspend, mxc_gpio_noirq_resume)
659 RUNTIME_PM_OPS(mxc_gpio_runtime_suspend, mxc_gpio_runtime_resume, NULL)
660};
661
662static int mxc_gpio_syscore_suspend(void)
663{
664 struct mxc_gpio_port *port;
665 int ret;
666
667 /* walk through all ports */
668 list_for_each_entry(port, &mxc_gpio_ports, node) {
669 ret = clk_prepare_enable(port->clk);
670 if (ret)
671 return ret;
672 mxc_gpio_save_regs(port);
673 clk_disable_unprepare(port->clk);
674 }
675
676 return 0;
677}
678
679static void mxc_gpio_syscore_resume(void)
680{
681 struct mxc_gpio_port *port;
682 int ret;
683
684 /* walk through all ports */
685 list_for_each_entry(port, &mxc_gpio_ports, node) {
686 ret = clk_prepare_enable(port->clk);
687 if (ret) {
688 pr_err("mxc: failed to enable gpio clock %d\n", ret);
689 return;
690 }
691 mxc_gpio_restore_regs(port);
692 clk_disable_unprepare(port->clk);
693 }
694}
695
696static struct syscore_ops mxc_gpio_syscore_ops = {
697 .suspend = mxc_gpio_syscore_suspend,
698 .resume = mxc_gpio_syscore_resume,
699};
700
701static struct platform_driver mxc_gpio_driver = {
702 .driver = {
703 .name = "gpio-mxc",
704 .of_match_table = mxc_gpio_dt_ids,
705 .suppress_bind_attrs = true,
706 .pm = pm_ptr(&mxc_gpio_dev_pm_ops),
707 },
708 .probe = mxc_gpio_probe,
709};
710
711static int __init gpio_mxc_init(void)
712{
713 register_syscore_ops(&mxc_gpio_syscore_ops);
714
715 return platform_driver_register(&mxc_gpio_driver);
716}
717subsys_initcall(gpio_mxc_init);
718
719MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
720MODULE_DESCRIPTION("i.MX GPIO Driver");
721MODULE_LICENSE("GPL");
1/*
2 * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 *
5 * Based on code from Freescale,
6 * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
20 */
21
22#include <linux/init.h>
23#include <linux/interrupt.h>
24#include <linux/io.h>
25#include <linux/irq.h>
26#include <linux/gpio.h>
27#include <linux/platform_device.h>
28#include <linux/slab.h>
29#include <linux/basic_mmio_gpio.h>
30#include <linux/of.h>
31#include <linux/of_device.h>
32#include <linux/module.h>
33#include <asm-generic/bug.h>
34#include <asm/mach/irq.h>
35
36#define irq_to_gpio(irq) ((irq) - MXC_GPIO_IRQ_START)
37
38enum mxc_gpio_hwtype {
39 IMX1_GPIO, /* runs on i.mx1 */
40 IMX21_GPIO, /* runs on i.mx21 and i.mx27 */
41 IMX31_GPIO, /* runs on all other i.mx */
42};
43
44/* device type dependent stuff */
45struct mxc_gpio_hwdata {
46 unsigned dr_reg;
47 unsigned gdir_reg;
48 unsigned psr_reg;
49 unsigned icr1_reg;
50 unsigned icr2_reg;
51 unsigned imr_reg;
52 unsigned isr_reg;
53 unsigned low_level;
54 unsigned high_level;
55 unsigned rise_edge;
56 unsigned fall_edge;
57};
58
59struct mxc_gpio_port {
60 struct list_head node;
61 void __iomem *base;
62 int irq;
63 int irq_high;
64 int virtual_irq_start;
65 struct bgpio_chip bgc;
66 u32 both_edges;
67};
68
69static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata = {
70 .dr_reg = 0x1c,
71 .gdir_reg = 0x00,
72 .psr_reg = 0x24,
73 .icr1_reg = 0x28,
74 .icr2_reg = 0x2c,
75 .imr_reg = 0x30,
76 .isr_reg = 0x34,
77 .low_level = 0x03,
78 .high_level = 0x02,
79 .rise_edge = 0x00,
80 .fall_edge = 0x01,
81};
82
83static struct mxc_gpio_hwdata imx31_gpio_hwdata = {
84 .dr_reg = 0x00,
85 .gdir_reg = 0x04,
86 .psr_reg = 0x08,
87 .icr1_reg = 0x0c,
88 .icr2_reg = 0x10,
89 .imr_reg = 0x14,
90 .isr_reg = 0x18,
91 .low_level = 0x00,
92 .high_level = 0x01,
93 .rise_edge = 0x02,
94 .fall_edge = 0x03,
95};
96
97static enum mxc_gpio_hwtype mxc_gpio_hwtype;
98static struct mxc_gpio_hwdata *mxc_gpio_hwdata;
99
100#define GPIO_DR (mxc_gpio_hwdata->dr_reg)
101#define GPIO_GDIR (mxc_gpio_hwdata->gdir_reg)
102#define GPIO_PSR (mxc_gpio_hwdata->psr_reg)
103#define GPIO_ICR1 (mxc_gpio_hwdata->icr1_reg)
104#define GPIO_ICR2 (mxc_gpio_hwdata->icr2_reg)
105#define GPIO_IMR (mxc_gpio_hwdata->imr_reg)
106#define GPIO_ISR (mxc_gpio_hwdata->isr_reg)
107
108#define GPIO_INT_LOW_LEV (mxc_gpio_hwdata->low_level)
109#define GPIO_INT_HIGH_LEV (mxc_gpio_hwdata->high_level)
110#define GPIO_INT_RISE_EDGE (mxc_gpio_hwdata->rise_edge)
111#define GPIO_INT_FALL_EDGE (mxc_gpio_hwdata->fall_edge)
112#define GPIO_INT_NONE 0x4
113
114static struct platform_device_id mxc_gpio_devtype[] = {
115 {
116 .name = "imx1-gpio",
117 .driver_data = IMX1_GPIO,
118 }, {
119 .name = "imx21-gpio",
120 .driver_data = IMX21_GPIO,
121 }, {
122 .name = "imx31-gpio",
123 .driver_data = IMX31_GPIO,
124 }, {
125 /* sentinel */
126 }
127};
128
129static const struct of_device_id mxc_gpio_dt_ids[] = {
130 { .compatible = "fsl,imx1-gpio", .data = &mxc_gpio_devtype[IMX1_GPIO], },
131 { .compatible = "fsl,imx21-gpio", .data = &mxc_gpio_devtype[IMX21_GPIO], },
132 { .compatible = "fsl,imx31-gpio", .data = &mxc_gpio_devtype[IMX31_GPIO], },
133 { /* sentinel */ }
134};
135
136/*
137 * MX2 has one interrupt *for all* gpio ports. The list is used
138 * to save the references to all ports, so that mx2_gpio_irq_handler
139 * can walk through all interrupt status registers.
140 */
141static LIST_HEAD(mxc_gpio_ports);
142
143/* Note: This driver assumes 32 GPIOs are handled in one register */
144
145static int gpio_set_irq_type(struct irq_data *d, u32 type)
146{
147 u32 gpio = irq_to_gpio(d->irq);
148 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
149 struct mxc_gpio_port *port = gc->private;
150 u32 bit, val;
151 int edge;
152 void __iomem *reg = port->base;
153
154 port->both_edges &= ~(1 << (gpio & 31));
155 switch (type) {
156 case IRQ_TYPE_EDGE_RISING:
157 edge = GPIO_INT_RISE_EDGE;
158 break;
159 case IRQ_TYPE_EDGE_FALLING:
160 edge = GPIO_INT_FALL_EDGE;
161 break;
162 case IRQ_TYPE_EDGE_BOTH:
163 val = gpio_get_value(gpio);
164 if (val) {
165 edge = GPIO_INT_LOW_LEV;
166 pr_debug("mxc: set GPIO %d to low trigger\n", gpio);
167 } else {
168 edge = GPIO_INT_HIGH_LEV;
169 pr_debug("mxc: set GPIO %d to high trigger\n", gpio);
170 }
171 port->both_edges |= 1 << (gpio & 31);
172 break;
173 case IRQ_TYPE_LEVEL_LOW:
174 edge = GPIO_INT_LOW_LEV;
175 break;
176 case IRQ_TYPE_LEVEL_HIGH:
177 edge = GPIO_INT_HIGH_LEV;
178 break;
179 default:
180 return -EINVAL;
181 }
182
183 reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
184 bit = gpio & 0xf;
185 val = readl(reg) & ~(0x3 << (bit << 1));
186 writel(val | (edge << (bit << 1)), reg);
187 writel(1 << (gpio & 0x1f), port->base + GPIO_ISR);
188
189 return 0;
190}
191
192static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
193{
194 void __iomem *reg = port->base;
195 u32 bit, val;
196 int edge;
197
198 reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
199 bit = gpio & 0xf;
200 val = readl(reg);
201 edge = (val >> (bit << 1)) & 3;
202 val &= ~(0x3 << (bit << 1));
203 if (edge == GPIO_INT_HIGH_LEV) {
204 edge = GPIO_INT_LOW_LEV;
205 pr_debug("mxc: switch GPIO %d to low trigger\n", gpio);
206 } else if (edge == GPIO_INT_LOW_LEV) {
207 edge = GPIO_INT_HIGH_LEV;
208 pr_debug("mxc: switch GPIO %d to high trigger\n", gpio);
209 } else {
210 pr_err("mxc: invalid configuration for GPIO %d: %x\n",
211 gpio, edge);
212 return;
213 }
214 writel(val | (edge << (bit << 1)), reg);
215}
216
217/* handle 32 interrupts in one status register */
218static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
219{
220 u32 gpio_irq_no_base = port->virtual_irq_start;
221
222 while (irq_stat != 0) {
223 int irqoffset = fls(irq_stat) - 1;
224
225 if (port->both_edges & (1 << irqoffset))
226 mxc_flip_edge(port, irqoffset);
227
228 generic_handle_irq(gpio_irq_no_base + irqoffset);
229
230 irq_stat &= ~(1 << irqoffset);
231 }
232}
233
234/* MX1 and MX3 has one interrupt *per* gpio port */
235static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
236{
237 u32 irq_stat;
238 struct mxc_gpio_port *port = irq_get_handler_data(irq);
239 struct irq_chip *chip = irq_get_chip(irq);
240
241 chained_irq_enter(chip, desc);
242
243 irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR);
244
245 mxc_gpio_irq_handler(port, irq_stat);
246
247 chained_irq_exit(chip, desc);
248}
249
250/* MX2 has one interrupt *for all* gpio ports */
251static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
252{
253 u32 irq_msk, irq_stat;
254 struct mxc_gpio_port *port;
255
256 /* walk through all interrupt status registers */
257 list_for_each_entry(port, &mxc_gpio_ports, node) {
258 irq_msk = readl(port->base + GPIO_IMR);
259 if (!irq_msk)
260 continue;
261
262 irq_stat = readl(port->base + GPIO_ISR) & irq_msk;
263 if (irq_stat)
264 mxc_gpio_irq_handler(port, irq_stat);
265 }
266}
267
268/*
269 * Set interrupt number "irq" in the GPIO as a wake-up source.
270 * While system is running, all registered GPIO interrupts need to have
271 * wake-up enabled. When system is suspended, only selected GPIO interrupts
272 * need to have wake-up enabled.
273 * @param irq interrupt source number
274 * @param enable enable as wake-up if equal to non-zero
275 * @return This function returns 0 on success.
276 */
277static int gpio_set_wake_irq(struct irq_data *d, u32 enable)
278{
279 u32 gpio = irq_to_gpio(d->irq);
280 u32 gpio_idx = gpio & 0x1F;
281 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
282 struct mxc_gpio_port *port = gc->private;
283
284 if (enable) {
285 if (port->irq_high && (gpio_idx >= 16))
286 enable_irq_wake(port->irq_high);
287 else
288 enable_irq_wake(port->irq);
289 } else {
290 if (port->irq_high && (gpio_idx >= 16))
291 disable_irq_wake(port->irq_high);
292 else
293 disable_irq_wake(port->irq);
294 }
295
296 return 0;
297}
298
299static void __init mxc_gpio_init_gc(struct mxc_gpio_port *port)
300{
301 struct irq_chip_generic *gc;
302 struct irq_chip_type *ct;
303
304 gc = irq_alloc_generic_chip("gpio-mxc", 1, port->virtual_irq_start,
305 port->base, handle_level_irq);
306 gc->private = port;
307
308 ct = gc->chip_types;
309 ct->chip.irq_ack = irq_gc_ack_set_bit;
310 ct->chip.irq_mask = irq_gc_mask_clr_bit;
311 ct->chip.irq_unmask = irq_gc_mask_set_bit;
312 ct->chip.irq_set_type = gpio_set_irq_type;
313 ct->chip.irq_set_wake = gpio_set_wake_irq;
314 ct->regs.ack = GPIO_ISR;
315 ct->regs.mask = GPIO_IMR;
316
317 irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_NESTED_LOCK,
318 IRQ_NOREQUEST, 0);
319}
320
321static void __devinit mxc_gpio_get_hw(struct platform_device *pdev)
322{
323 const struct of_device_id *of_id =
324 of_match_device(mxc_gpio_dt_ids, &pdev->dev);
325 enum mxc_gpio_hwtype hwtype;
326
327 if (of_id)
328 pdev->id_entry = of_id->data;
329 hwtype = pdev->id_entry->driver_data;
330
331 if (mxc_gpio_hwtype) {
332 /*
333 * The driver works with a reasonable presupposition,
334 * that is all gpio ports must be the same type when
335 * running on one soc.
336 */
337 BUG_ON(mxc_gpio_hwtype != hwtype);
338 return;
339 }
340
341 if (hwtype == IMX31_GPIO)
342 mxc_gpio_hwdata = &imx31_gpio_hwdata;
343 else
344 mxc_gpio_hwdata = &imx1_imx21_gpio_hwdata;
345
346 mxc_gpio_hwtype = hwtype;
347}
348
349static int mxc_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
350{
351 struct bgpio_chip *bgc = to_bgpio_chip(gc);
352 struct mxc_gpio_port *port =
353 container_of(bgc, struct mxc_gpio_port, bgc);
354
355 return port->virtual_irq_start + offset;
356}
357
358static int __devinit mxc_gpio_probe(struct platform_device *pdev)
359{
360 struct device_node *np = pdev->dev.of_node;
361 struct mxc_gpio_port *port;
362 struct resource *iores;
363 int err;
364
365 mxc_gpio_get_hw(pdev);
366
367 port = kzalloc(sizeof(struct mxc_gpio_port), GFP_KERNEL);
368 if (!port)
369 return -ENOMEM;
370
371 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
372 if (!iores) {
373 err = -ENODEV;
374 goto out_kfree;
375 }
376
377 if (!request_mem_region(iores->start, resource_size(iores),
378 pdev->name)) {
379 err = -EBUSY;
380 goto out_kfree;
381 }
382
383 port->base = ioremap(iores->start, resource_size(iores));
384 if (!port->base) {
385 err = -ENOMEM;
386 goto out_release_mem;
387 }
388
389 port->irq_high = platform_get_irq(pdev, 1);
390 port->irq = platform_get_irq(pdev, 0);
391 if (port->irq < 0) {
392 err = -EINVAL;
393 goto out_iounmap;
394 }
395
396 /* disable the interrupt and clear the status */
397 writel(0, port->base + GPIO_IMR);
398 writel(~0, port->base + GPIO_ISR);
399
400 if (mxc_gpio_hwtype == IMX21_GPIO) {
401 /*
402 * Setup one handler for all GPIO interrupts. Actually setting
403 * the handler is needed only once, but doing it for every port
404 * is more robust and easier.
405 */
406 irq_set_chained_handler(port->irq, mx2_gpio_irq_handler);
407 } else {
408 /* setup one handler for each entry */
409 irq_set_chained_handler(port->irq, mx3_gpio_irq_handler);
410 irq_set_handler_data(port->irq, port);
411 if (port->irq_high > 0) {
412 /* setup handler for GPIO 16 to 31 */
413 irq_set_chained_handler(port->irq_high,
414 mx3_gpio_irq_handler);
415 irq_set_handler_data(port->irq_high, port);
416 }
417 }
418
419 err = bgpio_init(&port->bgc, &pdev->dev, 4,
420 port->base + GPIO_PSR,
421 port->base + GPIO_DR, NULL,
422 port->base + GPIO_GDIR, NULL, 0);
423 if (err)
424 goto out_iounmap;
425
426 port->bgc.gc.to_irq = mxc_gpio_to_irq;
427 port->bgc.gc.base = pdev->id * 32;
428 port->bgc.dir = port->bgc.read_reg(port->bgc.reg_dir);
429 port->bgc.data = port->bgc.read_reg(port->bgc.reg_set);
430
431 err = gpiochip_add(&port->bgc.gc);
432 if (err)
433 goto out_bgpio_remove;
434
435 /*
436 * In dt case, we use gpio number range dynamically
437 * allocated by gpio core.
438 */
439 port->virtual_irq_start = MXC_GPIO_IRQ_START + (np ? port->bgc.gc.base :
440 pdev->id * 32);
441
442 /* gpio-mxc can be a generic irq chip */
443 mxc_gpio_init_gc(port);
444
445 list_add_tail(&port->node, &mxc_gpio_ports);
446
447 return 0;
448
449out_bgpio_remove:
450 bgpio_remove(&port->bgc);
451out_iounmap:
452 iounmap(port->base);
453out_release_mem:
454 release_mem_region(iores->start, resource_size(iores));
455out_kfree:
456 kfree(port);
457 dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err);
458 return err;
459}
460
461static struct platform_driver mxc_gpio_driver = {
462 .driver = {
463 .name = "gpio-mxc",
464 .owner = THIS_MODULE,
465 .of_match_table = mxc_gpio_dt_ids,
466 },
467 .probe = mxc_gpio_probe,
468 .id_table = mxc_gpio_devtype,
469};
470
471static int __init gpio_mxc_init(void)
472{
473 return platform_driver_register(&mxc_gpio_driver);
474}
475postcore_initcall(gpio_mxc_init);
476
477MODULE_AUTHOR("Freescale Semiconductor, "
478 "Daniel Mack <danielncaiaq.de>, "
479 "Juergen Beisert <kernel@pengutronix.de>");
480MODULE_DESCRIPTION("Freescale MXC GPIO");
481MODULE_LICENSE("GPL");