1/*
  2 * amd8131_edac.h, EDAC defs for AMD8131 hypertransport chip
  3 *
  4 * Copyright (c) 2008 Wind River Systems, Inc.
  5 *
  6 * Authors:	Cao Qingtao <qingtao.cao@windriver.com>
  7 * 		Benjamin Walsh <benjamin.walsh@windriver.com>
  8 * 		Hu Yongqi <yongqi.hu@windriver.com>
  9 *
 10 * This program is free software; you can redistribute it and/or modify
 11 * it under the terms of the GNU General Public License version 2 as
 12 * published by the Free Software Foundation.
 13 *
 14 * This program is distributed in the hope that it will be useful,
 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 17 * See the GNU General Public License for more details.
 18 *
 19 * You should have received a copy of the GNU General Public License
 20 * along with this program; if not, write to the Free Software
 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 22 */
 23
 24#ifndef _AMD8131_EDAC_H_
 25#define _AMD8131_EDAC_H_
 26
 27#define DEVFN_PCIX_BRIDGE_NORTH_A	8
 28#define DEVFN_PCIX_BRIDGE_NORTH_B	16
 29#define DEVFN_PCIX_BRIDGE_SOUTH_A	24
 30#define DEVFN_PCIX_BRIDGE_SOUTH_B	32
 31
 32/************************************************************
 33 *	PCI-X Bridge Status and Command Register, DevA:0x04
 34 ************************************************************/
 35#define REG_STS_CMD	0x04
 36enum sts_cmd_bits {
 37	STS_CMD_SSE	= BIT(30),
 38	STS_CMD_SERREN	= BIT(8)
 39};
 40
 41/************************************************************
 42 *	PCI-X Bridge Interrupt and Bridge Control Register,
 43 ************************************************************/
 44#define REG_INT_CTLR	0x3c
 45enum int_ctlr_bits {
 46	INT_CTLR_DTSE	= BIT(27),
 47	INT_CTLR_DTS	= BIT(26),
 48	INT_CTLR_SERR	= BIT(17),
 49	INT_CTLR_PERR	= BIT(16)
 50};
 51
 52/************************************************************
 53 *	PCI-X Bridge Memory Base-Limit Register, DevA:0x1C
 54 ************************************************************/
 55#define REG_MEM_LIM	0x1c
 56enum mem_limit_bits {
 57	MEM_LIMIT_DPE 	= BIT(31),
 58	MEM_LIMIT_RSE 	= BIT(30),
 59	MEM_LIMIT_RMA 	= BIT(29),
 60	MEM_LIMIT_RTA 	= BIT(28),
 61	MEM_LIMIT_STA	= BIT(27),
 62	MEM_LIMIT_MDPE	= BIT(24),
 63	MEM_LIMIT_MASK	= MEM_LIMIT_DPE|MEM_LIMIT_RSE|MEM_LIMIT_RMA|
 64				MEM_LIMIT_RTA|MEM_LIMIT_STA|MEM_LIMIT_MDPE
 65};
 66
 67/************************************************************
 68 *	Link Configuration And Control Register, side A
 69 ************************************************************/
 70#define REG_LNK_CTRL_A	0xc4
 71
 72/************************************************************
 73 *	Link Configuration And Control Register, side B
 74 ************************************************************/
 75#define REG_LNK_CTRL_B  0xc8
 76
 77enum lnk_ctrl_bits {
 78	LNK_CTRL_CRCERR_A	= BIT(9),
 79	LNK_CTRL_CRCERR_B	= BIT(8),
 80	LNK_CTRL_CRCFEN		= BIT(1)
 81};
 82
 83enum pcix_bridge_inst {
 84	NORTH_A = 0,
 85	NORTH_B = 1,
 86	SOUTH_A = 2,
 87	SOUTH_B = 3,
 88	NO_BRIDGE = 4
 89};
 90
 91struct amd8131_dev_info {
 92	int devfn;
 93	enum pcix_bridge_inst inst;
 94	struct pci_dev *dev;
 95	int edac_idx;	/* pci device index */
 96	char *ctl_name;
 97	struct edac_pci_ctl_info *edac_dev;
 98};
 99
100/*
101 * AMD8131 chipset has two pairs of PCIX Bridge and related IOAPIC
102 * Controller, and ATCA-6101 has two AMD8131 chipsets, so there are
103 * four PCIX Bridges on ATCA-6101 altogether.
104 *
105 * These PCIX Bridges share the same PCI Device ID and are all of
106 * Function Zero, they could be discrimated by their pci_dev->devfn.
107 * They share the same set of init/check/exit methods, and their
108 * private structures are collected in the devices[] array.
109 */
110struct amd8131_info {
111	u16 err_dev;	/* PCI Device ID for AMD8131 APIC*/
112	struct amd8131_dev_info *devices;
113	void (*init)(struct amd8131_dev_info *dev_info);
114	void (*exit)(struct amd8131_dev_info *dev_info);
115	void (*check)(struct edac_pci_ctl_info *edac_dev);
116};
117
118#endif /* _AMD8131_EDAC_H_ */
119