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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Cryptographic API.
4 *
5 * Glue code for the SHA1 Secure Hash Algorithm assembler implementations
6 * using SSSE3, AVX, AVX2, and SHA-NI instructions.
7 *
8 * This file is based on sha1_generic.c
9 *
10 * Copyright (c) Alan Smithee.
11 * Copyright (c) Andrew McDonald <andrew@mcdonald.org.uk>
12 * Copyright (c) Jean-Francois Dive <jef@linuxbe.org>
13 * Copyright (c) Mathias Krause <minipli@googlemail.com>
14 * Copyright (c) Chandramouli Narayanan <mouli@linux.intel.com>
15 */
16
17#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
18
19#include <crypto/internal/hash.h>
20#include <crypto/internal/simd.h>
21#include <linux/init.h>
22#include <linux/module.h>
23#include <linux/mm.h>
24#include <linux/types.h>
25#include <crypto/sha1.h>
26#include <crypto/sha1_base.h>
27#include <asm/cpu_device_id.h>
28#include <asm/simd.h>
29
30static const struct x86_cpu_id module_cpu_ids[] = {
31#ifdef CONFIG_AS_SHA1_NI
32 X86_MATCH_FEATURE(X86_FEATURE_SHA_NI, NULL),
33#endif
34 X86_MATCH_FEATURE(X86_FEATURE_AVX2, NULL),
35 X86_MATCH_FEATURE(X86_FEATURE_AVX, NULL),
36 X86_MATCH_FEATURE(X86_FEATURE_SSSE3, NULL),
37 {}
38};
39MODULE_DEVICE_TABLE(x86cpu, module_cpu_ids);
40
41static int sha1_update(struct shash_desc *desc, const u8 *data,
42 unsigned int len, sha1_block_fn *sha1_xform)
43{
44 struct sha1_state *sctx = shash_desc_ctx(desc);
45
46 if (!crypto_simd_usable() ||
47 (sctx->count % SHA1_BLOCK_SIZE) + len < SHA1_BLOCK_SIZE)
48 return crypto_sha1_update(desc, data, len);
49
50 /*
51 * Make sure struct sha1_state begins directly with the SHA1
52 * 160-bit internal state, as this is what the asm functions expect.
53 */
54 BUILD_BUG_ON(offsetof(struct sha1_state, state) != 0);
55
56 kernel_fpu_begin();
57 sha1_base_do_update(desc, data, len, sha1_xform);
58 kernel_fpu_end();
59
60 return 0;
61}
62
63static int sha1_finup(struct shash_desc *desc, const u8 *data,
64 unsigned int len, u8 *out, sha1_block_fn *sha1_xform)
65{
66 if (!crypto_simd_usable())
67 return crypto_sha1_finup(desc, data, len, out);
68
69 kernel_fpu_begin();
70 if (len)
71 sha1_base_do_update(desc, data, len, sha1_xform);
72 sha1_base_do_finalize(desc, sha1_xform);
73 kernel_fpu_end();
74
75 return sha1_base_finish(desc, out);
76}
77
78asmlinkage void sha1_transform_ssse3(struct sha1_state *state,
79 const u8 *data, int blocks);
80
81static int sha1_ssse3_update(struct shash_desc *desc, const u8 *data,
82 unsigned int len)
83{
84 return sha1_update(desc, data, len, sha1_transform_ssse3);
85}
86
87static int sha1_ssse3_finup(struct shash_desc *desc, const u8 *data,
88 unsigned int len, u8 *out)
89{
90 return sha1_finup(desc, data, len, out, sha1_transform_ssse3);
91}
92
93/* Add padding and return the message digest. */
94static int sha1_ssse3_final(struct shash_desc *desc, u8 *out)
95{
96 return sha1_ssse3_finup(desc, NULL, 0, out);
97}
98
99static struct shash_alg sha1_ssse3_alg = {
100 .digestsize = SHA1_DIGEST_SIZE,
101 .init = sha1_base_init,
102 .update = sha1_ssse3_update,
103 .final = sha1_ssse3_final,
104 .finup = sha1_ssse3_finup,
105 .descsize = sizeof(struct sha1_state),
106 .base = {
107 .cra_name = "sha1",
108 .cra_driver_name = "sha1-ssse3",
109 .cra_priority = 150,
110 .cra_blocksize = SHA1_BLOCK_SIZE,
111 .cra_module = THIS_MODULE,
112 }
113};
114
115static int register_sha1_ssse3(void)
116{
117 if (boot_cpu_has(X86_FEATURE_SSSE3))
118 return crypto_register_shash(&sha1_ssse3_alg);
119 return 0;
120}
121
122static void unregister_sha1_ssse3(void)
123{
124 if (boot_cpu_has(X86_FEATURE_SSSE3))
125 crypto_unregister_shash(&sha1_ssse3_alg);
126}
127
128asmlinkage void sha1_transform_avx(struct sha1_state *state,
129 const u8 *data, int blocks);
130
131static int sha1_avx_update(struct shash_desc *desc, const u8 *data,
132 unsigned int len)
133{
134 return sha1_update(desc, data, len, sha1_transform_avx);
135}
136
137static int sha1_avx_finup(struct shash_desc *desc, const u8 *data,
138 unsigned int len, u8 *out)
139{
140 return sha1_finup(desc, data, len, out, sha1_transform_avx);
141}
142
143static int sha1_avx_final(struct shash_desc *desc, u8 *out)
144{
145 return sha1_avx_finup(desc, NULL, 0, out);
146}
147
148static struct shash_alg sha1_avx_alg = {
149 .digestsize = SHA1_DIGEST_SIZE,
150 .init = sha1_base_init,
151 .update = sha1_avx_update,
152 .final = sha1_avx_final,
153 .finup = sha1_avx_finup,
154 .descsize = sizeof(struct sha1_state),
155 .base = {
156 .cra_name = "sha1",
157 .cra_driver_name = "sha1-avx",
158 .cra_priority = 160,
159 .cra_blocksize = SHA1_BLOCK_SIZE,
160 .cra_module = THIS_MODULE,
161 }
162};
163
164static bool avx_usable(void)
165{
166 if (!cpu_has_xfeatures(XFEATURE_MASK_SSE | XFEATURE_MASK_YMM, NULL)) {
167 if (boot_cpu_has(X86_FEATURE_AVX))
168 pr_info("AVX detected but unusable.\n");
169 return false;
170 }
171
172 return true;
173}
174
175static int register_sha1_avx(void)
176{
177 if (avx_usable())
178 return crypto_register_shash(&sha1_avx_alg);
179 return 0;
180}
181
182static void unregister_sha1_avx(void)
183{
184 if (avx_usable())
185 crypto_unregister_shash(&sha1_avx_alg);
186}
187
188#define SHA1_AVX2_BLOCK_OPTSIZE 4 /* optimal 4*64 bytes of SHA1 blocks */
189
190asmlinkage void sha1_transform_avx2(struct sha1_state *state,
191 const u8 *data, int blocks);
192
193static bool avx2_usable(void)
194{
195 if (avx_usable() && boot_cpu_has(X86_FEATURE_AVX2)
196 && boot_cpu_has(X86_FEATURE_BMI1)
197 && boot_cpu_has(X86_FEATURE_BMI2))
198 return true;
199
200 return false;
201}
202
203static void sha1_apply_transform_avx2(struct sha1_state *state,
204 const u8 *data, int blocks)
205{
206 /* Select the optimal transform based on data block size */
207 if (blocks >= SHA1_AVX2_BLOCK_OPTSIZE)
208 sha1_transform_avx2(state, data, blocks);
209 else
210 sha1_transform_avx(state, data, blocks);
211}
212
213static int sha1_avx2_update(struct shash_desc *desc, const u8 *data,
214 unsigned int len)
215{
216 return sha1_update(desc, data, len, sha1_apply_transform_avx2);
217}
218
219static int sha1_avx2_finup(struct shash_desc *desc, const u8 *data,
220 unsigned int len, u8 *out)
221{
222 return sha1_finup(desc, data, len, out, sha1_apply_transform_avx2);
223}
224
225static int sha1_avx2_final(struct shash_desc *desc, u8 *out)
226{
227 return sha1_avx2_finup(desc, NULL, 0, out);
228}
229
230static struct shash_alg sha1_avx2_alg = {
231 .digestsize = SHA1_DIGEST_SIZE,
232 .init = sha1_base_init,
233 .update = sha1_avx2_update,
234 .final = sha1_avx2_final,
235 .finup = sha1_avx2_finup,
236 .descsize = sizeof(struct sha1_state),
237 .base = {
238 .cra_name = "sha1",
239 .cra_driver_name = "sha1-avx2",
240 .cra_priority = 170,
241 .cra_blocksize = SHA1_BLOCK_SIZE,
242 .cra_module = THIS_MODULE,
243 }
244};
245
246static int register_sha1_avx2(void)
247{
248 if (avx2_usable())
249 return crypto_register_shash(&sha1_avx2_alg);
250 return 0;
251}
252
253static void unregister_sha1_avx2(void)
254{
255 if (avx2_usable())
256 crypto_unregister_shash(&sha1_avx2_alg);
257}
258
259#ifdef CONFIG_AS_SHA1_NI
260asmlinkage void sha1_ni_transform(struct sha1_state *digest, const u8 *data,
261 int rounds);
262
263static int sha1_ni_update(struct shash_desc *desc, const u8 *data,
264 unsigned int len)
265{
266 return sha1_update(desc, data, len, sha1_ni_transform);
267}
268
269static int sha1_ni_finup(struct shash_desc *desc, const u8 *data,
270 unsigned int len, u8 *out)
271{
272 return sha1_finup(desc, data, len, out, sha1_ni_transform);
273}
274
275static int sha1_ni_final(struct shash_desc *desc, u8 *out)
276{
277 return sha1_ni_finup(desc, NULL, 0, out);
278}
279
280static struct shash_alg sha1_ni_alg = {
281 .digestsize = SHA1_DIGEST_SIZE,
282 .init = sha1_base_init,
283 .update = sha1_ni_update,
284 .final = sha1_ni_final,
285 .finup = sha1_ni_finup,
286 .descsize = sizeof(struct sha1_state),
287 .base = {
288 .cra_name = "sha1",
289 .cra_driver_name = "sha1-ni",
290 .cra_priority = 250,
291 .cra_blocksize = SHA1_BLOCK_SIZE,
292 .cra_module = THIS_MODULE,
293 }
294};
295
296static int register_sha1_ni(void)
297{
298 if (boot_cpu_has(X86_FEATURE_SHA_NI))
299 return crypto_register_shash(&sha1_ni_alg);
300 return 0;
301}
302
303static void unregister_sha1_ni(void)
304{
305 if (boot_cpu_has(X86_FEATURE_SHA_NI))
306 crypto_unregister_shash(&sha1_ni_alg);
307}
308
309#else
310static inline int register_sha1_ni(void) { return 0; }
311static inline void unregister_sha1_ni(void) { }
312#endif
313
314static int __init sha1_ssse3_mod_init(void)
315{
316 if (!x86_match_cpu(module_cpu_ids))
317 return -ENODEV;
318
319 if (register_sha1_ssse3())
320 goto fail;
321
322 if (register_sha1_avx()) {
323 unregister_sha1_ssse3();
324 goto fail;
325 }
326
327 if (register_sha1_avx2()) {
328 unregister_sha1_avx();
329 unregister_sha1_ssse3();
330 goto fail;
331 }
332
333 if (register_sha1_ni()) {
334 unregister_sha1_avx2();
335 unregister_sha1_avx();
336 unregister_sha1_ssse3();
337 goto fail;
338 }
339
340 return 0;
341fail:
342 return -ENODEV;
343}
344
345static void __exit sha1_ssse3_mod_fini(void)
346{
347 unregister_sha1_ni();
348 unregister_sha1_avx2();
349 unregister_sha1_avx();
350 unregister_sha1_ssse3();
351}
352
353module_init(sha1_ssse3_mod_init);
354module_exit(sha1_ssse3_mod_fini);
355
356MODULE_LICENSE("GPL");
357MODULE_DESCRIPTION("SHA1 Secure Hash Algorithm, Supplemental SSE3 accelerated");
358
359MODULE_ALIAS_CRYPTO("sha1");
360MODULE_ALIAS_CRYPTO("sha1-ssse3");
361MODULE_ALIAS_CRYPTO("sha1-avx");
362MODULE_ALIAS_CRYPTO("sha1-avx2");
363#ifdef CONFIG_AS_SHA1_NI
364MODULE_ALIAS_CRYPTO("sha1-ni");
365#endif
1/*
2 * Cryptographic API.
3 *
4 * Glue code for the SHA1 Secure Hash Algorithm assembler implementation using
5 * Supplemental SSE3 instructions.
6 *
7 * This file is based on sha1_generic.c
8 *
9 * Copyright (c) Alan Smithee.
10 * Copyright (c) Andrew McDonald <andrew@mcdonald.org.uk>
11 * Copyright (c) Jean-Francois Dive <jef@linuxbe.org>
12 * Copyright (c) Mathias Krause <minipli@googlemail.com>
13 *
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License as published by the Free
16 * Software Foundation; either version 2 of the License, or (at your option)
17 * any later version.
18 *
19 */
20
21#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
22
23#include <crypto/internal/hash.h>
24#include <linux/init.h>
25#include <linux/module.h>
26#include <linux/mm.h>
27#include <linux/cryptohash.h>
28#include <linux/types.h>
29#include <crypto/sha.h>
30#include <asm/byteorder.h>
31#include <asm/i387.h>
32#include <asm/xcr.h>
33#include <asm/xsave.h>
34
35
36asmlinkage void sha1_transform_ssse3(u32 *digest, const char *data,
37 unsigned int rounds);
38#ifdef SHA1_ENABLE_AVX_SUPPORT
39asmlinkage void sha1_transform_avx(u32 *digest, const char *data,
40 unsigned int rounds);
41#endif
42
43static asmlinkage void (*sha1_transform_asm)(u32 *, const char *, unsigned int);
44
45
46static int sha1_ssse3_init(struct shash_desc *desc)
47{
48 struct sha1_state *sctx = shash_desc_ctx(desc);
49
50 *sctx = (struct sha1_state){
51 .state = { SHA1_H0, SHA1_H1, SHA1_H2, SHA1_H3, SHA1_H4 },
52 };
53
54 return 0;
55}
56
57static int __sha1_ssse3_update(struct shash_desc *desc, const u8 *data,
58 unsigned int len, unsigned int partial)
59{
60 struct sha1_state *sctx = shash_desc_ctx(desc);
61 unsigned int done = 0;
62
63 sctx->count += len;
64
65 if (partial) {
66 done = SHA1_BLOCK_SIZE - partial;
67 memcpy(sctx->buffer + partial, data, done);
68 sha1_transform_asm(sctx->state, sctx->buffer, 1);
69 }
70
71 if (len - done >= SHA1_BLOCK_SIZE) {
72 const unsigned int rounds = (len - done) / SHA1_BLOCK_SIZE;
73
74 sha1_transform_asm(sctx->state, data + done, rounds);
75 done += rounds * SHA1_BLOCK_SIZE;
76 }
77
78 memcpy(sctx->buffer, data + done, len - done);
79
80 return 0;
81}
82
83static int sha1_ssse3_update(struct shash_desc *desc, const u8 *data,
84 unsigned int len)
85{
86 struct sha1_state *sctx = shash_desc_ctx(desc);
87 unsigned int partial = sctx->count % SHA1_BLOCK_SIZE;
88 int res;
89
90 /* Handle the fast case right here */
91 if (partial + len < SHA1_BLOCK_SIZE) {
92 sctx->count += len;
93 memcpy(sctx->buffer + partial, data, len);
94
95 return 0;
96 }
97
98 if (!irq_fpu_usable()) {
99 res = crypto_sha1_update(desc, data, len);
100 } else {
101 kernel_fpu_begin();
102 res = __sha1_ssse3_update(desc, data, len, partial);
103 kernel_fpu_end();
104 }
105
106 return res;
107}
108
109
110/* Add padding and return the message digest. */
111static int sha1_ssse3_final(struct shash_desc *desc, u8 *out)
112{
113 struct sha1_state *sctx = shash_desc_ctx(desc);
114 unsigned int i, index, padlen;
115 __be32 *dst = (__be32 *)out;
116 __be64 bits;
117 static const u8 padding[SHA1_BLOCK_SIZE] = { 0x80, };
118
119 bits = cpu_to_be64(sctx->count << 3);
120
121 /* Pad out to 56 mod 64 and append length */
122 index = sctx->count % SHA1_BLOCK_SIZE;
123 padlen = (index < 56) ? (56 - index) : ((SHA1_BLOCK_SIZE+56) - index);
124 if (!irq_fpu_usable()) {
125 crypto_sha1_update(desc, padding, padlen);
126 crypto_sha1_update(desc, (const u8 *)&bits, sizeof(bits));
127 } else {
128 kernel_fpu_begin();
129 /* We need to fill a whole block for __sha1_ssse3_update() */
130 if (padlen <= 56) {
131 sctx->count += padlen;
132 memcpy(sctx->buffer + index, padding, padlen);
133 } else {
134 __sha1_ssse3_update(desc, padding, padlen, index);
135 }
136 __sha1_ssse3_update(desc, (const u8 *)&bits, sizeof(bits), 56);
137 kernel_fpu_end();
138 }
139
140 /* Store state in digest */
141 for (i = 0; i < 5; i++)
142 dst[i] = cpu_to_be32(sctx->state[i]);
143
144 /* Wipe context */
145 memset(sctx, 0, sizeof(*sctx));
146
147 return 0;
148}
149
150static int sha1_ssse3_export(struct shash_desc *desc, void *out)
151{
152 struct sha1_state *sctx = shash_desc_ctx(desc);
153
154 memcpy(out, sctx, sizeof(*sctx));
155
156 return 0;
157}
158
159static int sha1_ssse3_import(struct shash_desc *desc, const void *in)
160{
161 struct sha1_state *sctx = shash_desc_ctx(desc);
162
163 memcpy(sctx, in, sizeof(*sctx));
164
165 return 0;
166}
167
168static struct shash_alg alg = {
169 .digestsize = SHA1_DIGEST_SIZE,
170 .init = sha1_ssse3_init,
171 .update = sha1_ssse3_update,
172 .final = sha1_ssse3_final,
173 .export = sha1_ssse3_export,
174 .import = sha1_ssse3_import,
175 .descsize = sizeof(struct sha1_state),
176 .statesize = sizeof(struct sha1_state),
177 .base = {
178 .cra_name = "sha1",
179 .cra_driver_name= "sha1-ssse3",
180 .cra_priority = 150,
181 .cra_flags = CRYPTO_ALG_TYPE_SHASH,
182 .cra_blocksize = SHA1_BLOCK_SIZE,
183 .cra_module = THIS_MODULE,
184 }
185};
186
187#ifdef SHA1_ENABLE_AVX_SUPPORT
188static bool __init avx_usable(void)
189{
190 u64 xcr0;
191
192 if (!cpu_has_avx || !cpu_has_osxsave)
193 return false;
194
195 xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
196 if ((xcr0 & (XSTATE_SSE | XSTATE_YMM)) != (XSTATE_SSE | XSTATE_YMM)) {
197 pr_info("AVX detected but unusable.\n");
198
199 return false;
200 }
201
202 return true;
203}
204#endif
205
206static int __init sha1_ssse3_mod_init(void)
207{
208 /* test for SSSE3 first */
209 if (cpu_has_ssse3)
210 sha1_transform_asm = sha1_transform_ssse3;
211
212#ifdef SHA1_ENABLE_AVX_SUPPORT
213 /* allow AVX to override SSSE3, it's a little faster */
214 if (avx_usable())
215 sha1_transform_asm = sha1_transform_avx;
216#endif
217
218 if (sha1_transform_asm) {
219 pr_info("Using %s optimized SHA-1 implementation\n",
220 sha1_transform_asm == sha1_transform_ssse3 ? "SSSE3"
221 : "AVX");
222 return crypto_register_shash(&alg);
223 }
224 pr_info("Neither AVX nor SSSE3 is available/usable.\n");
225
226 return -ENODEV;
227}
228
229static void __exit sha1_ssse3_mod_fini(void)
230{
231 crypto_unregister_shash(&alg);
232}
233
234module_init(sha1_ssse3_mod_init);
235module_exit(sha1_ssse3_mod_fini);
236
237MODULE_LICENSE("GPL");
238MODULE_DESCRIPTION("SHA1 Secure Hash Algorithm, Supplemental SSE3 accelerated");
239
240MODULE_ALIAS("sha1");