1/*
  2 * ARM Ltd. Versatile Express
  3 *
  4 * CoreTile Express A9x4
  5 * Cortex-A9 MPCore (V2P-CA9)
  6 *
  7 * HBI-0191B
  8 */
  9
 10/dts-v1/;
 11
 12/ {
 13	model = "V2P-CA9";
 14	arm,hbi = <0x191>;
 15	compatible = "arm,vexpress,v2p-ca9", "arm,vexpress";
 16	interrupt-parent = <&gic>;
 17	#address-cells = <1>;
 18	#size-cells = <1>;
 19
 20	chosen { };
 21
 22	aliases {
 23		serial0 = &v2m_serial0;
 24		serial1 = &v2m_serial1;
 25		serial2 = &v2m_serial2;
 26		serial3 = &v2m_serial3;
 27		i2c0 = &v2m_i2c_dvi;
 28		i2c1 = &v2m_i2c_pcie;
 29	};
 30
 31	cpus {
 32		#address-cells = <1>;
 33		#size-cells = <0>;
 34
 35		cpu@0 {
 36			device_type = "cpu";
 37			compatible = "arm,cortex-a9";
 38			reg = <0>;
 39			next-level-cache = <&L2>;
 40		};
 41
 42		cpu@1 {
 43			device_type = "cpu";
 44			compatible = "arm,cortex-a9";
 45			reg = <1>;
 46			next-level-cache = <&L2>;
 47		};
 48
 49		cpu@2 {
 50			device_type = "cpu";
 51			compatible = "arm,cortex-a9";
 52			reg = <2>;
 53			next-level-cache = <&L2>;
 54		};
 55
 56		cpu@3 {
 57			device_type = "cpu";
 58			compatible = "arm,cortex-a9";
 59			reg = <3>;
 60			next-level-cache = <&L2>;
 61		};
 62	};
 63
 64	memory@60000000 {
 65		device_type = "memory";
 66		reg = <0x60000000 0x40000000>;
 67	};
 68
 69	clcd@10020000 {
 70		compatible = "arm,pl111", "arm,primecell";
 71		reg = <0x10020000 0x1000>;
 72		interrupts = <0 44 4>;
 73	};
 74
 75	memory-controller@100e0000 {
 76		compatible = "arm,pl341", "arm,primecell";
 77		reg = <0x100e0000 0x1000>;
 78	};
 79
 80	memory-controller@100e1000 {
 81		compatible = "arm,pl354", "arm,primecell";
 82		reg = <0x100e1000 0x1000>;
 83		interrupts = <0 45 4>,
 84			     <0 46 4>;
 85	};
 86
 87	timer@100e4000 {
 88		compatible = "arm,sp804", "arm,primecell";
 89		reg = <0x100e4000 0x1000>;
 90		interrupts = <0 48 4>,
 91			     <0 49 4>;
 92	};
 93
 94	watchdog@100e5000 {
 95		compatible = "arm,sp805", "arm,primecell";
 96		reg = <0x100e5000 0x1000>;
 97		interrupts = <0 51 4>;
 98	};
 99
100	scu@1e000000 {
101		compatible = "arm,cortex-a9-scu";
102		reg = <0x1e000000 0x58>;
103	};
104
105	timer@1e000600 {
106		compatible = "arm,cortex-a9-twd-timer";
107		reg = <0x1e000600 0x20>;
108		interrupts = <1 13 0xf04>;
109	};
110
111	watchdog@1e000620 {
112		compatible = "arm,cortex-a9-twd-wdt";
113		reg = <0x1e000620 0x20>;
114		interrupts = <1 14 0xf04>;
115	};
116
117	gic: interrupt-controller@1e001000 {
118		compatible = "arm,cortex-a9-gic";
119		#interrupt-cells = <3>;
120		#address-cells = <0>;
121		interrupt-controller;
122		reg = <0x1e001000 0x1000>,
123		      <0x1e000100 0x100>;
124	};
125
126	L2: cache-controller@1e00a000 {
127		compatible = "arm,pl310-cache";
128		reg = <0x1e00a000 0x1000>;
129		interrupts = <0 43 4>;
130		cache-level = <2>;
131		arm,data-latency = <1 1 1>;
132		arm,tag-latency = <1 1 1>;
133	};
134
135	pmu {
136		compatible = "arm,cortex-a9-pmu";
137		interrupts = <0 60 4>,
138			     <0 61 4>,
139			     <0 62 4>,
140			     <0 63 4>;
141	};
142
143	motherboard {
144		ranges = <0 0 0x40000000 0x04000000>,
145			 <1 0 0x44000000 0x04000000>,
146			 <2 0 0x48000000 0x04000000>,
147			 <3 0 0x4c000000 0x04000000>,
148			 <7 0 0x10000000 0x00020000>;
149
150		interrupt-map-mask = <0 0 63>;
151		interrupt-map = <0 0  0 &gic 0  0 4>,
152				<0 0  1 &gic 0  1 4>,
153				<0 0  2 &gic 0  2 4>,
154				<0 0  3 &gic 0  3 4>,
155				<0 0  4 &gic 0  4 4>,
156				<0 0  5 &gic 0  5 4>,
157				<0 0  6 &gic 0  6 4>,
158				<0 0  7 &gic 0  7 4>,
159				<0 0  8 &gic 0  8 4>,
160				<0 0  9 &gic 0  9 4>,
161				<0 0 10 &gic 0 10 4>,
162				<0 0 11 &gic 0 11 4>,
163				<0 0 12 &gic 0 12 4>,
164				<0 0 13 &gic 0 13 4>,
165				<0 0 14 &gic 0 14 4>,
166				<0 0 15 &gic 0 15 4>,
167				<0 0 16 &gic 0 16 4>,
168				<0 0 17 &gic 0 17 4>,
169				<0 0 18 &gic 0 18 4>,
170				<0 0 19 &gic 0 19 4>,
171				<0 0 20 &gic 0 20 4>,
172				<0 0 21 &gic 0 21 4>,
173				<0 0 22 &gic 0 22 4>,
174				<0 0 23 &gic 0 23 4>,
175				<0 0 24 &gic 0 24 4>,
176				<0 0 25 &gic 0 25 4>,
177				<0 0 26 &gic 0 26 4>,
178				<0 0 27 &gic 0 27 4>,
179				<0 0 28 &gic 0 28 4>,
180				<0 0 29 &gic 0 29 4>,
181				<0 0 30 &gic 0 30 4>,
182				<0 0 31 &gic 0 31 4>,
183				<0 0 32 &gic 0 32 4>,
184				<0 0 33 &gic 0 33 4>,
185				<0 0 34 &gic 0 34 4>,
186				<0 0 35 &gic 0 35 4>,
187				<0 0 36 &gic 0 36 4>,
188				<0 0 37 &gic 0 37 4>,
189				<0 0 38 &gic 0 38 4>,
190				<0 0 39 &gic 0 39 4>,
191				<0 0 40 &gic 0 40 4>,
192				<0 0 41 &gic 0 41 4>,
193				<0 0 42 &gic 0 42 4>;
194	};
195};
196
197/include/ "vexpress-v2m.dtsi"