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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * max98090.h -- MAX98090 ALSA SoC Audio driver
4 *
5 * Copyright 2011-2012 Maxim Integrated Products
6 */
7
8#ifndef _MAX98090_H
9#define _MAX98090_H
10
11/*
12 * The default operating frequency for a DMIC attached to the codec.
13 * This can be overridden by a device tree property.
14 */
15#define MAX98090_DEFAULT_DMIC_FREQ 2500000
16
17/*
18 * MAX98090 Register Definitions
19 */
20
21#define M98090_REG_SOFTWARE_RESET 0x00
22#define M98090_REG_DEVICE_STATUS 0x01
23#define M98090_REG_JACK_STATUS 0x02
24#define M98090_REG_INTERRUPT_S 0x03
25#define M98090_REG_QUICK_SYSTEM_CLOCK 0x04
26#define M98090_REG_QUICK_SAMPLE_RATE 0x05
27#define M98090_REG_DAI_INTERFACE 0x06
28#define M98090_REG_DAC_PATH 0x07
29#define M98090_REG_MIC_DIRECT_TO_ADC 0x08
30#define M98090_REG_LINE_TO_ADC 0x09
31#define M98090_REG_ANALOG_MIC_LOOP 0x0A
32#define M98090_REG_ANALOG_LINE_LOOP 0x0B
33#define M98090_REG_RESERVED 0x0C
34#define M98090_REG_LINE_INPUT_CONFIG 0x0D
35#define M98090_REG_LINE_INPUT_LEVEL 0x0E
36#define M98090_REG_INPUT_MODE 0x0F
37#define M98090_REG_MIC1_INPUT_LEVEL 0x10
38#define M98090_REG_MIC2_INPUT_LEVEL 0x11
39#define M98090_REG_MIC_BIAS_VOLTAGE 0x12
40#define M98090_REG_DIGITAL_MIC_ENABLE 0x13
41#define M98090_REG_DIGITAL_MIC_CONFIG 0x14
42#define M98090_REG_LEFT_ADC_MIXER 0x15
43#define M98090_REG_RIGHT_ADC_MIXER 0x16
44#define M98090_REG_LEFT_ADC_LEVEL 0x17
45#define M98090_REG_RIGHT_ADC_LEVEL 0x18
46#define M98090_REG_ADC_BIQUAD_LEVEL 0x19
47#define M98090_REG_ADC_SIDETONE 0x1A
48#define M98090_REG_SYSTEM_CLOCK 0x1B
49#define M98090_REG_CLOCK_MODE 0x1C
50#define M98090_REG_CLOCK_RATIO_NI_MSB 0x1D
51#define M98090_REG_CLOCK_RATIO_NI_LSB 0x1E
52#define M98090_REG_CLOCK_RATIO_MI_MSB 0x1F
53#define M98090_REG_CLOCK_RATIO_MI_LSB 0x20
54#define M98090_REG_MASTER_MODE 0x21
55#define M98090_REG_INTERFACE_FORMAT 0x22
56#define M98090_REG_TDM_CONTROL 0x23
57#define M98090_REG_TDM_FORMAT 0x24
58#define M98090_REG_IO_CONFIGURATION 0x25
59#define M98090_REG_FILTER_CONFIG 0x26
60#define M98090_REG_DAI_PLAYBACK_LEVEL 0x27
61#define M98090_REG_DAI_PLAYBACK_LEVEL_EQ 0x28
62#define M98090_REG_LEFT_HP_MIXER 0x29
63#define M98090_REG_RIGHT_HP_MIXER 0x2A
64#define M98090_REG_HP_CONTROL 0x2B
65#define M98090_REG_LEFT_HP_VOLUME 0x2C
66#define M98090_REG_RIGHT_HP_VOLUME 0x2D
67#define M98090_REG_LEFT_SPK_MIXER 0x2E
68#define M98090_REG_RIGHT_SPK_MIXER 0x2F
69#define M98090_REG_SPK_CONTROL 0x30
70#define M98090_REG_LEFT_SPK_VOLUME 0x31
71#define M98090_REG_RIGHT_SPK_VOLUME 0x32
72#define M98090_REG_DRC_TIMING 0x33
73#define M98090_REG_DRC_COMPRESSOR 0x34
74#define M98090_REG_DRC_EXPANDER 0x35
75#define M98090_REG_DRC_GAIN 0x36
76#define M98090_REG_RCV_LOUTL_MIXER 0x37
77#define M98090_REG_RCV_LOUTL_CONTROL 0x38
78#define M98090_REG_RCV_LOUTL_VOLUME 0x39
79#define M98090_REG_LOUTR_MIXER 0x3A
80#define M98090_REG_LOUTR_CONTROL 0x3B
81#define M98090_REG_LOUTR_VOLUME 0x3C
82#define M98090_REG_JACK_DETECT 0x3D
83#define M98090_REG_INPUT_ENABLE 0x3E
84#define M98090_REG_OUTPUT_ENABLE 0x3F
85#define M98090_REG_LEVEL_CONTROL 0x40
86#define M98090_REG_DSP_FILTER_ENABLE 0x41
87#define M98090_REG_BIAS_CONTROL 0x42
88#define M98090_REG_DAC_CONTROL 0x43
89#define M98090_REG_ADC_CONTROL 0x44
90#define M98090_REG_DEVICE_SHUTDOWN 0x45
91#define M98090_REG_EQUALIZER_BASE 0x46
92#define M98090_REG_RECORD_BIQUAD_BASE 0xAF
93#define M98090_REG_DMIC3_VOLUME 0xBE
94#define M98090_REG_DMIC4_VOLUME 0xBF
95#define M98090_REG_DMIC34_BQ_PREATTEN 0xC0
96#define M98090_REG_RECORD_TDM_SLOT 0xC1
97#define M98090_REG_SAMPLE_RATE 0xC2
98#define M98090_REG_DMIC34_BIQUAD_BASE 0xC3
99#define M98090_REG_REVISION_ID 0xFF
100
101#define M98090_REG_CNT (0xFF+1)
102#define MAX98090_MAX_REGISTER 0xFF
103
104/* MAX98090 Register Bit Fields */
105
106/*
107 * M98090_REG_SOFTWARE_RESET
108 */
109#define M98090_SWRESET_MASK (1<<7)
110#define M98090_SWRESET_SHIFT 7
111#define M98090_SWRESET_WIDTH 1
112
113/*
114 * M98090_REG_DEVICE_STATUS
115 */
116#define M98090_CLD_MASK (1<<7)
117#define M98090_CLD_SHIFT 7
118#define M98090_CLD_WIDTH 1
119#define M98090_SLD_MASK (1<<6)
120#define M98090_SLD_SHIFT 6
121#define M98090_SLD_WIDTH 1
122#define M98090_ULK_MASK (1<<5)
123#define M98090_ULK_SHIFT 5
124#define M98090_ULK_WIDTH 1
125#define M98090_JDET_MASK (1<<2)
126#define M98090_JDET_SHIFT 2
127#define M98090_JDET_WIDTH 1
128#define M98090_DRCACT_MASK (1<<1)
129#define M98090_DRCACT_SHIFT 1
130#define M98090_DRCACT_WIDTH 1
131#define M98090_DRCCLP_MASK (1<<0)
132#define M98090_DRCCLP_SHIFT 0
133#define M98090_DRCCLP_WIDTH 1
134
135/*
136 * M98090_REG_JACK_STATUS
137 */
138#define M98090_LSNS_MASK (1<<2)
139#define M98090_LSNS_SHIFT 2
140#define M98090_LSNS_WIDTH 1
141#define M98090_JKSNS_MASK (1<<1)
142#define M98090_JKSNS_SHIFT 1
143#define M98090_JKSNS_WIDTH 1
144
145/*
146 * M98090_REG_INTERRUPT_S
147 */
148#define M98090_ICLD_MASK (1<<7)
149#define M98090_ICLD_SHIFT 7
150#define M98090_ICLD_WIDTH 1
151#define M98090_ISLD_MASK (1<<6)
152#define M98090_ISLD_SHIFT 6
153#define M98090_ISLD_WIDTH 1
154#define M98090_IULK_MASK (1<<5)
155#define M98090_IULK_SHIFT 5
156#define M98090_IULK_WIDTH 1
157#define M98090_IJDET_MASK (1<<2)
158#define M98090_IJDET_SHIFT 2
159#define M98090_IJDET_WIDTH 1
160#define M98090_IDRCACT_MASK (1<<1)
161#define M98090_IDRCACT_SHIFT 1
162#define M98090_IDRCACT_WIDTH 1
163#define M98090_IDRCCLP_MASK (1<<0)
164#define M98090_IDRCCLP_SHIFT 0
165#define M98090_IDRCCLP_WIDTH 1
166
167/*
168 * M98090_REG_QUICK_SYSTEM_CLOCK
169 */
170#define M98090_26M_MASK (1<<7)
171#define M98090_26M_SHIFT 7
172#define M98090_26M_WIDTH 1
173#define M98090_19P2M_MASK (1<<6)
174#define M98090_19P2M_SHIFT 6
175#define M98090_19P2M_WIDTH 1
176#define M98090_13M_MASK (1<<5)
177#define M98090_13M_SHIFT 5
178#define M98090_13M_WIDTH 1
179#define M98090_12P288M_MASK (1<<4)
180#define M98090_12P288M_SHIFT 4
181#define M98090_12P288M_WIDTH 1
182#define M98090_12M_MASK (1<<3)
183#define M98090_12M_SHIFT 3
184#define M98090_12M_WIDTH 1
185#define M98090_11P2896M_MASK (1<<2)
186#define M98090_11P2896M_SHIFT 2
187#define M98090_11P2896M_WIDTH 1
188#define M98090_256FS_MASK (1<<0)
189#define M98090_256FS_SHIFT 0
190#define M98090_256FS_WIDTH 1
191#define M98090_CLK_ALL_SHIFT 0
192#define M98090_CLK_ALL_WIDTH 8
193#define M98090_CLK_ALL_NUM (1<<M98090_CLK_ALL_WIDTH)
194
195/*
196 * M98090_REG_QUICK_SAMPLE_RATE
197 */
198#define M98090_SR_96K_MASK (1<<5)
199#define M98090_SR_96K_SHIFT 5
200#define M98090_SR_96K_WIDTH 1
201#define M98090_SR_32K_MASK (1<<4)
202#define M98090_SR_32K_SHIFT 4
203#define M98090_SR_32K_WIDTH 1
204#define M98090_SR_48K_MASK (1<<3)
205#define M98090_SR_48K_SHIFT 3
206#define M98090_SR_48K_WIDTH 1
207#define M98090_SR_44K1_MASK (1<<2)
208#define M98090_SR_44K1_SHIFT 2
209#define M98090_SR_44K1_WIDTH 1
210#define M98090_SR_16K_MASK (1<<1)
211#define M98090_SR_16K_SHIFT 1
212#define M98090_SR_16K_WIDTH 1
213#define M98090_SR_8K_MASK (1<<0)
214#define M98090_SR_8K_SHIFT 0
215#define M98090_SR_8K_WIDTH 1
216#define M98090_SR_MASK 0x3F
217#define M98090_SR_ALL_SHIFT 0
218#define M98090_SR_ALL_WIDTH 8
219#define M98090_SR_ALL_NUM (1<<M98090_SR_ALL_WIDTH)
220
221/*
222 * M98090_REG_DAI_INTERFACE
223 */
224#define M98090_RJ_M_MASK (1<<5)
225#define M98090_RJ_M_SHIFT 5
226#define M98090_RJ_M_WIDTH 1
227#define M98090_RJ_S_MASK (1<<4)
228#define M98090_RJ_S_SHIFT 4
229#define M98090_RJ_S_WIDTH 1
230#define M98090_LJ_M_MASK (1<<3)
231#define M98090_LJ_M_SHIFT 3
232#define M98090_LJ_M_WIDTH 1
233#define M98090_LJ_S_MASK (1<<2)
234#define M98090_LJ_S_SHIFT 2
235#define M98090_LJ_S_WIDTH 1
236#define M98090_I2S_M_MASK (1<<1)
237#define M98090_I2S_M_SHIFT 1
238#define M98090_I2S_M_WIDTH 1
239#define M98090_I2S_S_MASK (1<<0)
240#define M98090_I2S_S_SHIFT 0
241#define M98090_I2S_S_WIDTH 1
242#define M98090_DAI_ALL_SHIFT 0
243#define M98090_DAI_ALL_WIDTH 8
244#define M98090_DAI_ALL_NUM (1<<M98090_DAI_ALL_WIDTH)
245
246/*
247 * M98090_REG_DAC_PATH
248 */
249#define M98090_DIG2_HP_MASK (1<<7)
250#define M98090_DIG2_HP_SHIFT 7
251#define M98090_DIG2_HP_WIDTH 1
252#define M98090_DIG2_EAR_MASK (1<<6)
253#define M98090_DIG2_EAR_SHIFT 6
254#define M98090_DIG2_EAR_WIDTH 1
255#define M98090_DIG2_SPK_MASK (1<<5)
256#define M98090_DIG2_SPK_SHIFT 5
257#define M98090_DIG2_SPK_WIDTH 1
258#define M98090_DIG2_LOUT_MASK (1<<4)
259#define M98090_DIG2_LOUT_SHIFT 4
260#define M98090_DIG2_LOUT_WIDTH 1
261#define M98090_DIG2_ALL_SHIFT 0
262#define M98090_DIG2_ALL_WIDTH 8
263#define M98090_DIG2_ALL_NUM (1<<M98090_DIG2_ALL_WIDTH)
264
265/*
266 * M98090_REG_MIC_DIRECT_TO_ADC
267 */
268#define M98090_IN12_MIC1_MASK (1<<7)
269#define M98090_IN12_MIC1_SHIFT 7
270#define M98090_IN12_MIC1_WIDTH 1
271#define M98090_IN34_MIC2_MASK (1<<6)
272#define M98090_IN34_MIC2_SHIFT 6
273#define M98090_IN34_MIC2_WIDTH 1
274#define M98090_IN56_MIC1_MASK (1<<5)
275#define M98090_IN56_MIC1_SHIFT 5
276#define M98090_IN56_MIC1_WIDTH 1
277#define M98090_IN56_MIC2_MASK (1<<4)
278#define M98090_IN56_MIC2_SHIFT 4
279#define M98090_IN56_MIC2_WIDTH 1
280#define M98090_IN12_DADC_MASK (1<<3)
281#define M98090_IN12_DADC_SHIFT 3
282#define M98090_IN12_DADC_WIDTH 1
283#define M98090_IN34_DADC_MASK (1<<2)
284#define M98090_IN34_DADC_SHIFT 2
285#define M98090_IN34_DADC_WIDTH 1
286#define M98090_IN56_DADC_MASK (1<<1)
287#define M98090_IN56_DADC_SHIFT 1
288#define M98090_IN56_DADC_WIDTH 1
289#define M98090_MIC_ALL_SHIFT 0
290#define M98090_MIC_ALL_WIDTH 8
291#define M98090_MIC_ALL_NUM (1<<M98090_MIC_ALL_WIDTH)
292
293/*
294 * M98090_REG_LINE_TO_ADC
295 */
296#define M98090_IN12S_AB_MASK (1<<7)
297#define M98090_IN12S_AB_SHIFT 7
298#define M98090_IN12S_AB_WIDTH 1
299#define M98090_IN34S_AB_MASK (1<<6)
300#define M98090_IN34S_AB_SHIFT 6
301#define M98090_IN34S_AB_WIDTH 1
302#define M98090_IN56S_AB_MASK (1<<5)
303#define M98090_IN56S_AB_SHIFT 5
304#define M98090_IN56S_AB_WIDTH 1
305#define M98090_IN34D_A_MASK (1<<4)
306#define M98090_IN34D_A_SHIFT 4
307#define M98090_IN34D_A_WIDTH 1
308#define M98090_IN56D_B_MASK (1<<3)
309#define M98090_IN56D_B_SHIFT 3
310#define M98090_IN56D_B_WIDTH 1
311#define M98090_LINE_ALL_SHIFT 0
312#define M98090_LINE_ALL_WIDTH 8
313#define M98090_LINE_ALL_NUM (1<<M98090_LINE_ALL_WIDTH)
314
315/*
316 * M98090_REG_ANALOG_MIC_LOOP
317 */
318#define M98090_IN12_M1HPL_MASK (1<<7)
319#define M98090_IN12_M1HPL_SHIFT 7
320#define M98090_IN12_M1HPL_WIDTH 1
321#define M98090_IN12_M1SPKL_MASK (1<<6)
322#define M98090_IN12_M1SPKL_SHIFT 6
323#define M98090_IN12_M1SPKL_WIDTH 1
324#define M98090_IN12_M1EAR_MASK (1<<5)
325#define M98090_IN12_M1EAR_SHIFT 5
326#define M98090_IN12_M1EAR_WIDTH 1
327#define M98090_IN12_M1LOUTL_MASK (1<<4)
328#define M98090_IN12_M1LOUTL_SHIFT 4
329#define M98090_IN12_M1LOUTL_WIDTH 1
330#define M98090_IN34_M2HPR_MASK (1<<3)
331#define M98090_IN34_M2HPR_SHIFT 3
332#define M98090_IN34_M2HPR_WIDTH 1
333#define M98090_IN34_M2SPKR_MASK (1<<2)
334#define M98090_IN34_M2SPKR_SHIFT 2
335#define M98090_IN34_M2SPKR_WIDTH 1
336#define M98090_IN34_M2EAR_MASK (1<<1)
337#define M98090_IN34_M2EAR_SHIFT 1
338#define M98090_IN34_M2EAR_WIDTH 1
339#define M98090_IN34_M2LOUTR_MASK (1<<0)
340#define M98090_IN34_M2LOUTR_SHIFT 0
341#define M98090_IN34_M2LOUTR_WIDTH 1
342#define M98090_AMIC_ALL_SHIFT 0
343#define M98090_AMIC_ALL_WIDTH 8
344#define M98090_AMIC_ALL_NUM (1<<M98090_AMIC_ALL_WIDTH)
345
346/*
347 * M98090_REG_ANALOG_LINE_LOOP
348 */
349#define M98090_IN12S_ABHP_MASK (1<<7)
350#define M98090_IN12S_ABHP_SHIFT 7
351#define M98090_IN12S_ABHP_WIDTH 1
352#define M98090_IN34D_ASPKL_MASK (1<<6)
353#define M98090_IN34D_ASPKL_SHIFT 6
354#define M98090_IN34D_ASPKL_WIDTH 1
355#define M98090_IN34D_AEAR_MASK (1<<5)
356#define M98090_IN34D_AEAR_SHIFT 5
357#define M98090_IN34D_AEAR_WIDTH 1
358#define M98090_IN12S_ABLOUT_MASK (1<<4)
359#define M98090_IN12S_ABLOUT_SHIFT 4
360#define M98090_IN12S_ABLOUT_WIDTH 1
361#define M98090_IN34S_ABHP_MASK (1<<3)
362#define M98090_IN34S_ABHP_SHIFT 3
363#define M98090_IN34S_ABHP_WIDTH 1
364#define M98090_IN56D_BSPKR_MASK (1<<2)
365#define M98090_IN56D_BSPKR_SHIFT 2
366#define M98090_IN56D_BSPKR_WIDTH 1
367#define M98090_IN56D_BEAR_MASK (1<<1)
368#define M98090_IN56D_BEAR_SHIFT 1
369#define M98090_IN56D_BEAR_WIDTH 1
370#define M98090_IN34S_ABLOUT_MASK (1<<0)
371#define M98090_IN34S_ABLOUT_SHIFT 0
372#define M98090_IN34S_ABLOUT_WIDTH 1
373#define M98090_ALIN_ALL_SHIFT 0
374#define M98090_ALIN_ALL_WIDTH 8
375#define M98090_ALIN_ALL_NUM (1<<M98090_ALIN_ALL_WIDTH)
376
377/*
378 * M98090_REG_RESERVED
379 */
380
381/*
382 * M98090_REG_LINE_INPUT_CONFIG
383 */
384#define M98090_IN34DIFF_MASK (1<<7)
385#define M98090_IN34DIFF_SHIFT 7
386#define M98090_IN34DIFF_WIDTH 1
387#define M98090_IN56DIFF_MASK (1<<6)
388#define M98090_IN56DIFF_SHIFT 6
389#define M98090_IN56DIFF_WIDTH 1
390#define M98090_IN1SEEN_MASK (1<<5)
391#define M98090_IN1SEEN_SHIFT 5
392#define M98090_IN1SEEN_WIDTH 1
393#define M98090_IN2SEEN_MASK (1<<4)
394#define M98090_IN2SEEN_SHIFT 4
395#define M98090_IN2SEEN_WIDTH 1
396#define M98090_IN3SEEN_MASK (1<<3)
397#define M98090_IN3SEEN_SHIFT 3
398#define M98090_IN3SEEN_WIDTH 1
399#define M98090_IN4SEEN_MASK (1<<2)
400#define M98090_IN4SEEN_SHIFT 2
401#define M98090_IN4SEEN_WIDTH 1
402#define M98090_IN5SEEN_MASK (1<<1)
403#define M98090_IN5SEEN_SHIFT 1
404#define M98090_IN5SEEN_WIDTH 1
405#define M98090_IN6SEEN_MASK (1<<0)
406#define M98090_IN6SEEN_SHIFT 0
407#define M98090_IN6SEEN_WIDTH 1
408
409/*
410 * M98090_REG_LINE_INPUT_LEVEL
411 */
412#define M98090_MIXG135_MASK (1<<7)
413#define M98090_MIXG135_SHIFT 7
414#define M98090_MIXG135_WIDTH 1
415#define M98090_MIXG135_NUM (1<<M98090_MIXG135_WIDTH)
416#define M98090_MIXG246_MASK (1<<6)
417#define M98090_MIXG246_SHIFT 6
418#define M98090_MIXG246_WIDTH 1
419#define M98090_MIXG246_NUM (1<<M98090_MIXG246_WIDTH)
420#define M98090_LINAPGA_MASK (7<<3)
421#define M98090_LINAPGA_SHIFT 3
422#define M98090_LINAPGA_WIDTH 3
423#define M98090_LINAPGA_NUM 6
424#define M98090_LINBPGA_MASK (7<<0)
425#define M98090_LINBPGA_SHIFT 0
426#define M98090_LINBPGA_WIDTH 3
427#define M98090_LINBPGA_NUM 6
428
429/*
430 * M98090_REG_INPUT_MODE
431 */
432#define M98090_EXTBUFA_MASK (1<<7)
433#define M98090_EXTBUFA_SHIFT 7
434#define M98090_EXTBUFA_WIDTH 1
435#define M98090_EXTBUFA_NUM (1<<M98090_EXTBUFA_WIDTH)
436#define M98090_EXTBUFB_MASK (1<<6)
437#define M98090_EXTBUFB_SHIFT 6
438#define M98090_EXTBUFB_WIDTH 1
439#define M98090_EXTBUFB_NUM (1<<M98090_EXTBUFB_WIDTH)
440#define M98090_EXTMIC_MASK (3<<0)
441#define M98090_EXTMIC_SHIFT 0
442#define M98090_EXTMIC1_SHIFT 0
443#define M98090_EXTMIC2_SHIFT 1
444#define M98090_EXTMIC_WIDTH 2
445#define M98090_EXTMIC_NONE (0<<0)
446#define M98090_EXTMIC_MIC1 (1<<0)
447#define M98090_EXTMIC_MIC2 (2<<0)
448
449/*
450 * M98090_REG_MIC1_INPUT_LEVEL
451 */
452#define M98090_MIC_PA1EN_MASK (3<<5)
453#define M98090_MIC_PA1EN_SHIFT 5
454#define M98090_MIC_PA1EN_WIDTH 2
455#define M98090_MIC_PA1EN_NUM 3
456#define M98090_MIC_PGAM1_MASK (31<<0)
457#define M98090_MIC_PGAM1_SHIFT 0
458#define M98090_MIC_PGAM1_WIDTH 5
459#define M98090_MIC_PGAM1_NUM 21
460
461/*
462 * M98090_REG_MIC2_INPUT_LEVEL
463 */
464#define M98090_MIC_PA2EN_MASK (3<<5)
465#define M98090_MIC_PA2EN_SHIFT 5
466#define M98090_MIC_PA2EN_WIDTH 2
467#define M98090_MIC_PA2EN_NUM 3
468#define M98090_MIC_PGAM2_MASK (31<<0)
469#define M98090_MIC_PGAM2_SHIFT 0
470#define M98090_MIC_PGAM2_WIDTH 5
471#define M98090_MIC_PGAM2_NUM 21
472
473/*
474 * M98090_REG_MIC_BIAS_VOLTAGE
475 */
476#define M98090_MBVSEL_MASK (3<<0)
477#define M98090_MBVSEL_SHIFT 0
478#define M98090_MBVSEL_WIDTH 2
479#define M98090_MBVSEL_2V8 (3<<0)
480#define M98090_MBVSEL_2V55 (2<<0)
481#define M98090_MBVSEL_2V4 (1<<0)
482#define M98090_MBVSEL_2V2 (0<<0)
483
484/*
485 * M98090_REG_DIGITAL_MIC_ENABLE
486 */
487#define M98090_MICCLK_MASK (7<<4)
488#define M98090_MICCLK_SHIFT 4
489#define M98090_MICCLK_WIDTH 3
490#define M98090_DIGMIC4_MASK (1<<3)
491#define M98090_DIGMIC4_SHIFT 3
492#define M98090_DIGMIC4_WIDTH 1
493#define M98090_DIGMIC4_NUM (1<<M98090_DIGMIC4_WIDTH)
494#define M98090_DIGMIC3_MASK (1<<2)
495#define M98090_DIGMIC3_SHIFT 2
496#define M98090_DIGMIC3_WIDTH 1
497#define M98090_DIGMIC3_NUM (1<<M98090_DIGMIC3_WIDTH)
498#define M98090_DIGMICR_MASK (1<<1)
499#define M98090_DIGMICR_SHIFT 1
500#define M98090_DIGMICR_WIDTH 1
501#define M98090_DIGMICR_NUM (1<<M98090_DIGMICR_WIDTH)
502#define M98090_DIGMICL_MASK (1<<0)
503#define M98090_DIGMICL_SHIFT 0
504#define M98090_DIGMICL_WIDTH 1
505#define M98090_DIGMICL_NUM (1<<M98090_DIGMICL_WIDTH)
506
507/*
508 * M98090_REG_DIGITAL_MIC_CONFIG
509 */
510#define M98090_DMIC_COMP_MASK (15<<4)
511#define M98090_DMIC_COMP_SHIFT 4
512#define M98090_DMIC_COMP_WIDTH 4
513#define M98090_DMIC_COMP_NUM (1<<M98090_DMIC_COMP_WIDTH)
514#define M98090_DMIC_FREQ_MASK (3<<0)
515#define M98090_DMIC_FREQ_SHIFT 0
516#define M98090_DMIC_FREQ_WIDTH 2
517
518/*
519 * M98090_REG_LEFT_ADC_MIXER
520 */
521#define M98090_MIXADL_MIC2_MASK (1<<6)
522#define M98090_MIXADL_MIC2_SHIFT 6
523#define M98090_MIXADL_MIC2_WIDTH 1
524#define M98090_MIXADL_MIC1_MASK (1<<5)
525#define M98090_MIXADL_MIC1_SHIFT 5
526#define M98090_MIXADL_MIC1_WIDTH 1
527#define M98090_MIXADL_LINEB_MASK (1<<4)
528#define M98090_MIXADL_LINEB_SHIFT 4
529#define M98090_MIXADL_LINEB_WIDTH 1
530#define M98090_MIXADL_LINEA_MASK (1<<3)
531#define M98090_MIXADL_LINEA_SHIFT 3
532#define M98090_MIXADL_LINEA_WIDTH 1
533#define M98090_MIXADL_IN65DIFF_MASK (1<<2)
534#define M98090_MIXADL_IN65DIFF_SHIFT 2
535#define M98090_MIXADL_IN65DIFF_WIDTH 1
536#define M98090_MIXADL_IN34DIFF_MASK (1<<1)
537#define M98090_MIXADL_IN34DIFF_SHIFT 1
538#define M98090_MIXADL_IN34DIFF_WIDTH 1
539#define M98090_MIXADL_IN12DIFF_MASK (1<<0)
540#define M98090_MIXADL_IN12DIFF_SHIFT 0
541#define M98090_MIXADL_IN12DIFF_WIDTH 1
542#define M98090_MIXADL_MASK (255<<0)
543#define M98090_MIXADL_SHIFT 0
544#define M98090_MIXADL_WIDTH 8
545
546/*
547 * M98090_REG_RIGHT_ADC_MIXER
548 */
549#define M98090_MIXADR_MIC2_MASK (1<<6)
550#define M98090_MIXADR_MIC2_SHIFT 6
551#define M98090_MIXADR_MIC2_WIDTH 1
552#define M98090_MIXADR_MIC1_MASK (1<<5)
553#define M98090_MIXADR_MIC1_SHIFT 5
554#define M98090_MIXADR_MIC1_WIDTH 1
555#define M98090_MIXADR_LINEB_MASK (1<<4)
556#define M98090_MIXADR_LINEB_SHIFT 4
557#define M98090_MIXADR_LINEB_WIDTH 1
558#define M98090_MIXADR_LINEA_MASK (1<<3)
559#define M98090_MIXADR_LINEA_SHIFT 3
560#define M98090_MIXADR_LINEA_WIDTH 1
561#define M98090_MIXADR_IN65DIFF_MASK (1<<2)
562#define M98090_MIXADR_IN65DIFF_SHIFT 2
563#define M98090_MIXADR_IN65DIFF_WIDTH 1
564#define M98090_MIXADR_IN34DIFF_MASK (1<<1)
565#define M98090_MIXADR_IN34DIFF_SHIFT 1
566#define M98090_MIXADR_IN34DIFF_WIDTH 1
567#define M98090_MIXADR_IN12DIFF_MASK (1<<0)
568#define M98090_MIXADR_IN12DIFF_SHIFT 0
569#define M98090_MIXADR_IN12DIFF_WIDTH 1
570#define M98090_MIXADR_MASK (255<<0)
571#define M98090_MIXADR_SHIFT 0
572#define M98090_MIXADR_WIDTH 8
573
574/*
575 * M98090_REG_LEFT_ADC_LEVEL
576 */
577#define M98090_AVLG_MASK (7<<4)
578#define M98090_AVLG_SHIFT 4
579#define M98090_AVLG_WIDTH 3
580#define M98090_AVLG_NUM (1<<M98090_AVLG_WIDTH)
581#define M98090_AVL_MASK (15<<0)
582#define M98090_AVL_SHIFT 0
583#define M98090_AVL_WIDTH 4
584#define M98090_AVL_NUM (1<<M98090_AVL_WIDTH)
585
586/*
587 * M98090_REG_RIGHT_ADC_LEVEL
588 */
589#define M98090_AVRG_MASK (7<<4)
590#define M98090_AVRG_SHIFT 4
591#define M98090_AVRG_WIDTH 3
592#define M98090_AVRG_NUM (1<<M98090_AVRG_WIDTH)
593#define M98090_AVR_MASK (15<<0)
594#define M98090_AVR_SHIFT 0
595#define M98090_AVR_WIDTH 4
596#define M98090_AVR_NUM (1<<M98090_AVR_WIDTH)
597
598/*
599 * M98090_REG_ADC_BIQUAD_LEVEL
600 */
601#define M98090_AVBQ_MASK (15<<0)
602#define M98090_AVBQ_SHIFT 0
603#define M98090_AVBQ_WIDTH 4
604#define M98090_AVBQ_NUM (1<<M98090_AVBQ_WIDTH)
605
606/*
607 * M98090_REG_ADC_SIDETONE
608 */
609#define M98090_DSTSR_MASK (1<<7)
610#define M98090_DSTSR_SHIFT 7
611#define M98090_DSTSR_WIDTH 1
612#define M98090_DSTSL_MASK (1<<6)
613#define M98090_DSTSL_SHIFT 6
614#define M98090_DSTSL_WIDTH 1
615#define M98090_DVST_MASK (31<<0)
616#define M98090_DVST_SHIFT 0
617#define M98090_DVST_WIDTH 5
618#define M98090_DVST_NUM 31
619
620/*
621 * M98090_REG_SYSTEM_CLOCK
622 */
623#define M98090_PSCLK_MASK (3<<4)
624#define M98090_PSCLK_SHIFT 4
625#define M98090_PSCLK_WIDTH 2
626#define M98090_PSCLK_DISABLED (0<<4)
627#define M98090_PSCLK_DIV1 (1<<4)
628#define M98090_PSCLK_DIV2 (2<<4)
629#define M98090_PSCLK_DIV4 (3<<4)
630
631/*
632 * M98090_REG_CLOCK_MODE
633 */
634#define M98090_FREQ_MASK (15<<4)
635#define M98090_FREQ_SHIFT 4
636#define M98090_FREQ_WIDTH 4
637#define M98090_USE_M1_MASK (1<<0)
638#define M98090_USE_M1_SHIFT 0
639#define M98090_USE_M1_WIDTH 1
640#define M98090_USE_M1_NUM (1<<M98090_USE_M1_WIDTH)
641
642/*
643 * M98090_REG_CLOCK_RATIO_NI_MSB
644 */
645#define M98090_NI_HI_MASK (127<<0)
646#define M98090_NI_HI_SHIFT 0
647#define M98090_NI_HI_WIDTH 7
648#define M98090_NI_HI_NUM (1<<M98090_NI_HI_WIDTH)
649
650/*
651 * M98090_REG_CLOCK_RATIO_NI_LSB
652 */
653#define M98090_NI_LO_MASK (255<<0)
654#define M98090_NI_LO_SHIFT 0
655#define M98090_NI_LO_WIDTH 8
656#define M98090_NI_LO_NUM (1<<M98090_NI_LO_WIDTH)
657
658/*
659 * M98090_REG_CLOCK_RATIO_MI_MSB
660 */
661#define M98090_MI_HI_MASK (255<<0)
662#define M98090_MI_HI_SHIFT 0
663#define M98090_MI_HI_WIDTH 8
664#define M98090_MI_HI_NUM (1<<M98090_MI_HI_WIDTH)
665
666/*
667 * M98090_REG_CLOCK_RATIO_MI_LSB
668 */
669#define M98090_MI_LO_MASK (255<<0)
670#define M98090_MI_LO_SHIFT 0
671#define M98090_MI_LO_WIDTH 8
672#define M98090_MI_LO_NUM (1<<M98090_MI_LO_WIDTH)
673
674/*
675 * M98090_REG_MASTER_MODE
676 */
677#define M98090_MAS_MASK (1<<7)
678#define M98090_MAS_SHIFT 7
679#define M98090_MAS_WIDTH 1
680#define M98090_BSEL_MASK (1<<0)
681#define M98090_BSEL_SHIFT 0
682#define M98090_BSEL_WIDTH 1
683#define M98090_BSEL_32 (1<<0)
684#define M98090_BSEL_48 (2<<0)
685#define M98090_BSEL_64 (3<<0)
686
687/*
688 * M98090_REG_INTERFACE_FORMAT
689 */
690#define M98090_RJ_MASK (1<<5)
691#define M98090_RJ_SHIFT 5
692#define M98090_RJ_WIDTH 1
693#define M98090_WCI_MASK (1<<4)
694#define M98090_WCI_SHIFT 4
695#define M98090_WCI_WIDTH 1
696#define M98090_BCI_MASK (1<<3)
697#define M98090_BCI_SHIFT 3
698#define M98090_BCI_WIDTH 1
699#define M98090_DLY_MASK (1<<2)
700#define M98090_DLY_SHIFT 2
701#define M98090_DLY_WIDTH 1
702#define M98090_WS_MASK (3<<0)
703#define M98090_WS_SHIFT 0
704#define M98090_WS_WIDTH 2
705#define M98090_WS_NUM (1<<M98090_WS_WIDTH)
706
707/*
708 * M98090_REG_TDM_CONTROL
709 */
710#define M98090_FSW_MASK (1<<1)
711#define M98090_FSW_SHIFT 1
712#define M98090_FSW_WIDTH 1
713#define M98090_TDM_MASK (1<<0)
714#define M98090_TDM_SHIFT 0
715#define M98090_TDM_WIDTH 1
716#define M98090_TDM_NUM (1<<M98090_TDM_WIDTH)
717
718/*
719 * M98090_REG_TDM_FORMAT
720 */
721#define M98090_TDM_SLOTL_MASK (3<<6)
722#define M98090_TDM_SLOTL_SHIFT 6
723#define M98090_TDM_SLOTL_WIDTH 2
724#define M98090_TDM_SLOTL_NUM (1<<M98090_TDM_SLOTL_WIDTH)
725#define M98090_TDM_SLOTR_MASK (3<<4)
726#define M98090_TDM_SLOTR_SHIFT 4
727#define M98090_TDM_SLOTR_WIDTH 2
728#define M98090_TDM_SLOTR_NUM (1<<M98090_TDM_SLOTR_WIDTH)
729#define M98090_TDM_SLOTDLY_MASK (15<<0)
730#define M98090_TDM_SLOTDLY_SHIFT 0
731#define M98090_TDM_SLOTDLY_WIDTH 4
732#define M98090_TDM_SLOTDLY_NUM (1<<M98090_TDM_SLOTDLY_WIDTH)
733
734/*
735 * M98090_REG_IO_CONFIGURATION
736 */
737#define M98090_LTEN_MASK (1<<5)
738#define M98090_LTEN_SHIFT 5
739#define M98090_LTEN_WIDTH 1
740#define M98090_LTEN_NUM (1<<M98090_LTEN_WIDTH)
741#define M98090_LBEN_MASK (1<<4)
742#define M98090_LBEN_SHIFT 4
743#define M98090_LBEN_WIDTH 1
744#define M98090_LBEN_NUM (1<<M98090_LBEN_WIDTH)
745#define M98090_DMONO_MASK (1<<3)
746#define M98090_DMONO_SHIFT 3
747#define M98090_DMONO_WIDTH 1
748#define M98090_DMONO_NUM (1<<M98090_DMONO_WIDTH)
749#define M98090_HIZOFF_MASK (1<<2)
750#define M98090_HIZOFF_SHIFT 2
751#define M98090_HIZOFF_WIDTH 1
752#define M98090_HIZOFF_NUM (1<<M98090_HIZOFF_WIDTH)
753#define M98090_SDOEN_MASK (1<<1)
754#define M98090_SDOEN_SHIFT 1
755#define M98090_SDOEN_WIDTH 1
756#define M98090_SDOEN_NUM (1<<M98090_SDOEN_WIDTH)
757#define M98090_SDIEN_MASK (1<<0)
758#define M98090_SDIEN_SHIFT 0
759#define M98090_SDIEN_WIDTH 1
760#define M98090_SDIEN_NUM (1<<M98090_SDIEN_WIDTH)
761
762/*
763 * M98090_REG_FILTER_CONFIG
764 */
765#define M98090_MODE_MASK (1<<7)
766#define M98090_MODE_SHIFT 7
767#define M98090_MODE_WIDTH 1
768#define M98090_AHPF_MASK (1<<6)
769#define M98090_AHPF_SHIFT 6
770#define M98090_AHPF_WIDTH 1
771#define M98090_AHPF_NUM (1<<M98090_AHPF_WIDTH)
772#define M98090_DHPF_MASK (1<<5)
773#define M98090_DHPF_SHIFT 5
774#define M98090_DHPF_WIDTH 1
775#define M98090_DHPF_NUM (1<<M98090_DHPF_WIDTH)
776#define M98090_DHF_MASK (1<<4)
777#define M98090_DHF_SHIFT 4
778#define M98090_DHF_WIDTH 1
779#define M98090_FLT_DMIC34MODE_MASK (1<<3)
780#define M98090_FLT_DMIC34MODE_SHIFT 3
781#define M98090_FLT_DMIC34MODE_WIDTH 1
782#define M98090_FLT_DMIC34HPF_MASK (1<<2)
783#define M98090_FLT_DMIC34HPF_SHIFT 2
784#define M98090_FLT_DMIC34HPF_WIDTH 1
785#define M98090_FLT_DMIC34HPF_NUM (1<<M98090_FLT_DMIC34HPF_WIDTH)
786
787/*
788 * M98090_REG_DAI_PLAYBACK_LEVEL
789 */
790#define M98090_DVM_MASK (1<<7)
791#define M98090_DVM_SHIFT 7
792#define M98090_DVM_WIDTH 1
793#define M98090_DVG_MASK (3<<4)
794#define M98090_DVG_SHIFT 4
795#define M98090_DVG_WIDTH 2
796#define M98090_DVG_NUM (1<<M98090_DVG_WIDTH)
797#define M98090_DV_MASK (15<<0)
798#define M98090_DV_SHIFT 0
799#define M98090_DV_WIDTH 4
800#define M98090_DV_NUM (1<<M98090_DV_WIDTH)
801
802/*
803 * M98090_REG_DAI_PLAYBACK_LEVEL_EQ
804 */
805#define M98090_EQCLPN_MASK (1<<4)
806#define M98090_EQCLPN_SHIFT 4
807#define M98090_EQCLPN_WIDTH 1
808#define M98090_EQCLPN_NUM (1<<M98090_EQCLPN_WIDTH)
809#define M98090_DVEQ_MASK (15<<0)
810#define M98090_DVEQ_SHIFT 0
811#define M98090_DVEQ_WIDTH 4
812#define M98090_DVEQ_NUM (1<<M98090_DVEQ_WIDTH)
813
814/*
815 * M98090_REG_LEFT_HP_MIXER
816 */
817#define M98090_MIXHPL_MIC2_MASK (1<<5)
818#define M98090_MIXHPL_MIC2_SHIFT 5
819#define M98090_MIXHPL_MIC2_WIDTH 1
820#define M98090_MIXHPL_MIC1_MASK (1<<4)
821#define M98090_MIXHPL_MIC1_SHIFT 4
822#define M98090_MIXHPL_MIC1_WIDTH 1
823#define M98090_MIXHPL_LINEB_MASK (1<<3)
824#define M98090_MIXHPL_LINEB_SHIFT 3
825#define M98090_MIXHPL_LINEB_WIDTH 1
826#define M98090_MIXHPL_LINEA_MASK (1<<2)
827#define M98090_MIXHPL_LINEA_SHIFT 2
828#define M98090_MIXHPL_LINEA_WIDTH 1
829#define M98090_MIXHPL_DACR_MASK (1<<1)
830#define M98090_MIXHPL_DACR_SHIFT 1
831#define M98090_MIXHPL_DACR_WIDTH 1
832#define M98090_MIXHPL_DACL_MASK (1<<0)
833#define M98090_MIXHPL_DACL_SHIFT 0
834#define M98090_MIXHPL_DACL_WIDTH 1
835#define M98090_MIXHPL_MASK (63<<0)
836#define M98090_MIXHPL_SHIFT 0
837#define M98090_MIXHPL_WIDTH 6
838
839/*
840 * M98090_REG_RIGHT_HP_MIXER
841 */
842#define M98090_MIXHPR_MIC2_MASK (1<<5)
843#define M98090_MIXHPR_MIC2_SHIFT 5
844#define M98090_MIXHPR_MIC2_WIDTH 1
845#define M98090_MIXHPR_MIC1_MASK (1<<4)
846#define M98090_MIXHPR_MIC1_SHIFT 4
847#define M98090_MIXHPR_MIC1_WIDTH 1
848#define M98090_MIXHPR_LINEB_MASK (1<<3)
849#define M98090_MIXHPR_LINEB_SHIFT 3
850#define M98090_MIXHPR_LINEB_WIDTH 1
851#define M98090_MIXHPR_LINEA_MASK (1<<2)
852#define M98090_MIXHPR_LINEA_SHIFT 2
853#define M98090_MIXHPR_LINEA_WIDTH 1
854#define M98090_MIXHPR_DACR_MASK (1<<1)
855#define M98090_MIXHPR_DACR_SHIFT 1
856#define M98090_MIXHPR_DACR_WIDTH 1
857#define M98090_MIXHPR_DACL_MASK (1<<0)
858#define M98090_MIXHPR_DACL_SHIFT 0
859#define M98090_MIXHPR_DACL_WIDTH 1
860#define M98090_MIXHPR_MASK (63<<0)
861#define M98090_MIXHPR_SHIFT 0
862#define M98090_MIXHPR_WIDTH 6
863
864/*
865 * M98090_REG_HP_CONTROL
866 */
867#define M98090_MIXHPRSEL_MASK (1<<5)
868#define M98090_MIXHPRSEL_SHIFT 5
869#define M98090_MIXHPRSEL_WIDTH 1
870#define M98090_MIXHPLSEL_MASK (1<<4)
871#define M98090_MIXHPLSEL_SHIFT 4
872#define M98090_MIXHPLSEL_WIDTH 1
873#define M98090_MIXHPRG_MASK (3<<2)
874#define M98090_MIXHPRG_SHIFT 2
875#define M98090_MIXHPRG_WIDTH 2
876#define M98090_MIXHPRG_NUM (1<<M98090_MIXHPRG_WIDTH)
877#define M98090_MIXHPLG_MASK (3<<0)
878#define M98090_MIXHPLG_SHIFT 0
879#define M98090_MIXHPLG_WIDTH 2
880#define M98090_MIXHPLG_NUM (1<<M98090_MIXHPLG_WIDTH)
881
882/*
883 * M98090_REG_LEFT_HP_VOLUME
884 */
885#define M98090_HPLM_MASK (1<<7)
886#define M98090_HPLM_SHIFT 7
887#define M98090_HPLM_WIDTH 1
888#define M98090_HPVOLL_MASK (31<<0)
889#define M98090_HPVOLL_SHIFT 0
890#define M98090_HPVOLL_WIDTH 5
891#define M98090_HPVOLL_NUM (1<<M98090_HPVOLL_WIDTH)
892
893/*
894 * M98090_REG_RIGHT_HP_VOLUME
895 */
896#define M98090_HPRM_MASK (1<<7)
897#define M98090_HPRM_SHIFT 7
898#define M98090_HPRM_WIDTH 1
899#define M98090_HPVOLR_MASK (31<<0)
900#define M98090_HPVOLR_SHIFT 0
901#define M98090_HPVOLR_WIDTH 5
902#define M98090_HPVOLR_NUM (1<<M98090_HPVOLR_WIDTH)
903
904/*
905 * M98090_REG_LEFT_SPK_MIXER
906 */
907#define M98090_MIXSPL_MIC2_MASK (1<<5)
908#define M98090_MIXSPL_MIC2_SHIFT 5
909#define M98090_MIXSPL_MIC2_WIDTH 1
910#define M98090_MIXSPL_MIC1_MASK (1<<4)
911#define M98090_MIXSPL_MIC1_SHIFT 4
912#define M98090_MIXSPL_MIC1_WIDTH 1
913#define M98090_MIXSPL_LINEB_MASK (1<<3)
914#define M98090_MIXSPL_LINEB_SHIFT 3
915#define M98090_MIXSPL_LINEB_WIDTH 1
916#define M98090_MIXSPL_LINEA_MASK (1<<2)
917#define M98090_MIXSPL_LINEA_SHIFT 2
918#define M98090_MIXSPL_LINEA_WIDTH 1
919#define M98090_MIXSPL_DACR_MASK (1<<1)
920#define M98090_MIXSPL_DACR_SHIFT 1
921#define M98090_MIXSPL_DACR_WIDTH 1
922#define M98090_MIXSPL_DACL_MASK (1<<0)
923#define M98090_MIXSPL_DACL_SHIFT 0
924#define M98090_MIXSPL_DACL_WIDTH 1
925#define M98090_MIXSPL_MASK (63<<0)
926#define M98090_MIXSPL_SHIFT 0
927#define M98090_MIXSPL_WIDTH 6
928#define M98090_MIXSPR_DACR_MASK (1<<1)
929#define M98090_MIXSPR_DACR_SHIFT 1
930#define M98090_MIXSPR_DACR_WIDTH 1
931
932
933/*
934 * M98090_REG_RIGHT_SPK_MIXER
935 */
936#define M98090_SPK_SLAVE_MASK (1<<6)
937#define M98090_SPK_SLAVE_SHIFT 6
938#define M98090_SPK_SLAVE_WIDTH 1
939#define M98090_MIXSPR_MIC2_MASK (1<<5)
940#define M98090_MIXSPR_MIC2_SHIFT 5
941#define M98090_MIXSPR_MIC2_WIDTH 1
942#define M98090_MIXSPR_MIC1_MASK (1<<4)
943#define M98090_MIXSPR_MIC1_SHIFT 4
944#define M98090_MIXSPR_MIC1_WIDTH 1
945#define M98090_MIXSPR_LINEB_MASK (1<<3)
946#define M98090_MIXSPR_LINEB_SHIFT 3
947#define M98090_MIXSPR_LINEB_WIDTH 1
948#define M98090_MIXSPR_LINEA_MASK (1<<2)
949#define M98090_MIXSPR_LINEA_SHIFT 2
950#define M98090_MIXSPR_LINEA_WIDTH 1
951#define M98090_MIXSPR_DACR_MASK (1<<1)
952#define M98090_MIXSPR_DACR_SHIFT 1
953#define M98090_MIXSPR_DACR_WIDTH 1
954#define M98090_MIXSPR_DACL_MASK (1<<0)
955#define M98090_MIXSPR_DACL_SHIFT 0
956#define M98090_MIXSPR_DACL_WIDTH 1
957#define M98090_MIXSPR_MASK (63<<0)
958#define M98090_MIXSPR_SHIFT 0
959#define M98090_MIXSPR_WIDTH 6
960
961/*
962 * M98090_REG_SPK_CONTROL
963 */
964#define M98090_MIXSPRG_MASK (3<<2)
965#define M98090_MIXSPRG_SHIFT 2
966#define M98090_MIXSPRG_WIDTH 2
967#define M98090_MIXSPRG_NUM (1<<M98090_MIXSPRG_WIDTH)
968#define M98090_MIXSPLG_MASK (3<<0)
969#define M98090_MIXSPLG_SHIFT 0
970#define M98090_MIXSPLG_WIDTH 2
971#define M98090_MIXSPLG_NUM (1<<M98090_MIXSPLG_WIDTH)
972
973/*
974 * M98090_REG_LEFT_SPK_VOLUME
975 */
976#define M98090_SPLM_MASK (1<<7)
977#define M98090_SPLM_SHIFT 7
978#define M98090_SPLM_WIDTH 1
979#define M98090_SPVOLL_MASK (63<<0)
980#define M98090_SPVOLL_SHIFT 0
981#define M98090_SPVOLL_WIDTH 6
982#define M98090_SPVOLL_NUM 40
983
984/*
985 * M98090_REG_RIGHT_SPK_VOLUME
986 */
987#define M98090_SPRM_MASK (1<<7)
988#define M98090_SPRM_SHIFT 7
989#define M98090_SPRM_WIDTH 1
990#define M98090_SPVOLR_MASK (63<<0)
991#define M98090_SPVOLR_SHIFT 0
992#define M98090_SPVOLR_WIDTH 6
993#define M98090_SPVOLR_NUM 40
994
995/*
996 * M98090_REG_DRC_TIMING
997 */
998#define M98090_DRCEN_MASK (1<<7)
999#define M98090_DRCEN_SHIFT 7
1000#define M98090_DRCEN_WIDTH 1
1001#define M98090_DRCEN_NUM (1<<M98090_DRCEN_WIDTH)
1002#define M98090_DRCRLS_MASK (7<<4)
1003#define M98090_DRCRLS_SHIFT 4
1004#define M98090_DRCRLS_WIDTH 3
1005#define M98090_DRCATK_MASK (7<<0)
1006#define M98090_DRCATK_SHIFT 0
1007#define M98090_DRCATK_WIDTH 3
1008
1009/*
1010 * M98090_REG_DRC_COMPRESSOR
1011 */
1012#define M98090_DRCCMP_MASK (7<<5)
1013#define M98090_DRCCMP_SHIFT 5
1014#define M98090_DRCCMP_WIDTH 3
1015#define M98090_DRCTHC_MASK (31<<0)
1016#define M98090_DRCTHC_SHIFT 0
1017#define M98090_DRCTHC_WIDTH 5
1018#define M98090_DRCTHC_NUM (1<<M98090_DRCTHC_WIDTH)
1019
1020/*
1021 * M98090_REG_DRC_EXPANDER
1022 */
1023#define M98090_DRCEXP_MASK (7<<5)
1024#define M98090_DRCEXP_SHIFT 5
1025#define M98090_DRCEXP_WIDTH 3
1026#define M98090_DRCTHE_MASK (31<<0)
1027#define M98090_DRCTHE_SHIFT 0
1028#define M98090_DRCTHE_WIDTH 5
1029#define M98090_DRCTHE_NUM (1<<M98090_DRCTHE_WIDTH)
1030
1031/*
1032 * M98090_REG_DRC_GAIN
1033 */
1034#define M98090_DRCG_MASK (31<<0)
1035#define M98090_DRCG_SHIFT 0
1036#define M98090_DRCG_WIDTH 5
1037#define M98090_DRCG_NUM 13
1038
1039/*
1040 * M98090_REG_RCV_LOUTL_MIXER
1041 */
1042#define M98090_MIXRCVL_MIC2_MASK (1<<5)
1043#define M98090_MIXRCVL_MIC2_SHIFT 5
1044#define M98090_MIXRCVL_MIC2_WIDTH 1
1045#define M98090_MIXRCVL_MIC1_MASK (1<<4)
1046#define M98090_MIXRCVL_MIC1_SHIFT 4
1047#define M98090_MIXRCVL_MIC1_WIDTH 1
1048#define M98090_MIXRCVL_LINEB_MASK (1<<3)
1049#define M98090_MIXRCVL_LINEB_SHIFT 3
1050#define M98090_MIXRCVL_LINEB_WIDTH 1
1051#define M98090_MIXRCVL_LINEA_MASK (1<<2)
1052#define M98090_MIXRCVL_LINEA_SHIFT 2
1053#define M98090_MIXRCVL_LINEA_WIDTH 1
1054#define M98090_MIXRCVL_DACR_MASK (1<<1)
1055#define M98090_MIXRCVL_DACR_SHIFT 1
1056#define M98090_MIXRCVL_DACR_WIDTH 1
1057#define M98090_MIXRCVL_DACL_MASK (1<<0)
1058#define M98090_MIXRCVL_DACL_SHIFT 0
1059#define M98090_MIXRCVL_DACL_WIDTH 1
1060#define M98090_MIXRCVL_MASK (63<<0)
1061#define M98090_MIXRCVL_SHIFT 0
1062#define M98090_MIXRCVL_WIDTH 6
1063
1064/*
1065 * M98090_REG_RCV_LOUTL_CONTROL
1066 */
1067#define M98090_MIXRCVLG_MASK (3<<0)
1068#define M98090_MIXRCVLG_SHIFT 0
1069#define M98090_MIXRCVLG_WIDTH 2
1070#define M98090_MIXRCVLG_NUM (1<<M98090_MIXRCVLG_WIDTH)
1071
1072/*
1073 * M98090_REG_RCV_LOUTL_VOLUME
1074 */
1075#define M98090_RCVLM_MASK (1<<7)
1076#define M98090_RCVLM_SHIFT 7
1077#define M98090_RCVLM_WIDTH 1
1078#define M98090_RCVLVOL_MASK (31<<0)
1079#define M98090_RCVLVOL_SHIFT 0
1080#define M98090_RCVLVOL_WIDTH 5
1081#define M98090_RCVLVOL_NUM (1<<M98090_RCVLVOL_WIDTH)
1082
1083/*
1084 * M98090_REG_LOUTR_MIXER
1085 */
1086#define M98090_LINMOD_MASK (1<<7)
1087#define M98090_LINMOD_SHIFT 7
1088#define M98090_LINMOD_WIDTH 1
1089#define M98090_MIXRCVR_MIC2_MASK (1<<5)
1090#define M98090_MIXRCVR_MIC2_SHIFT 5
1091#define M98090_MIXRCVR_MIC2_WIDTH 1
1092#define M98090_MIXRCVR_MIC1_MASK (1<<4)
1093#define M98090_MIXRCVR_MIC1_SHIFT 4
1094#define M98090_MIXRCVR_MIC1_WIDTH 1
1095#define M98090_MIXRCVR_LINEB_MASK (1<<3)
1096#define M98090_MIXRCVR_LINEB_SHIFT 3
1097#define M98090_MIXRCVR_LINEB_WIDTH 1
1098#define M98090_MIXRCVR_LINEA_MASK (1<<2)
1099#define M98090_MIXRCVR_LINEA_SHIFT 2
1100#define M98090_MIXRCVR_LINEA_WIDTH 1
1101#define M98090_MIXRCVR_DACR_MASK (1<<1)
1102#define M98090_MIXRCVR_DACR_SHIFT 1
1103#define M98090_MIXRCVR_DACR_WIDTH 1
1104#define M98090_MIXRCVR_DACL_MASK (1<<0)
1105#define M98090_MIXRCVR_DACL_SHIFT 0
1106#define M98090_MIXRCVR_DACL_WIDTH 1
1107#define M98090_MIXRCVR_MASK (63<<0)
1108#define M98090_MIXRCVR_SHIFT 0
1109#define M98090_MIXRCVR_WIDTH 6
1110
1111/*
1112 * M98090_REG_LOUTR_CONTROL
1113 */
1114#define M98090_MIXRCVRG_MASK (3<<0)
1115#define M98090_MIXRCVRG_SHIFT 0
1116#define M98090_MIXRCVRG_WIDTH 2
1117#define M98090_MIXRCVRG_NUM (1<<M98090_MIXRCVRG_WIDTH)
1118
1119/*
1120 * M98090_REG_LOUTR_VOLUME
1121 */
1122#define M98090_RCVRM_MASK (1<<7)
1123#define M98090_RCVRM_SHIFT 7
1124#define M98090_RCVRM_WIDTH 1
1125#define M98090_RCVRVOL_MASK (31<<0)
1126#define M98090_RCVRVOL_SHIFT 0
1127#define M98090_RCVRVOL_WIDTH 5
1128#define M98090_RCVRVOL_NUM (1<<M98090_RCVRVOL_WIDTH)
1129
1130/*
1131 * M98090_REG_JACK_DETECT
1132 */
1133#define M98090_JDETEN_MASK (1<<7)
1134#define M98090_JDETEN_SHIFT 7
1135#define M98090_JDETEN_WIDTH 1
1136#define M98090_JDWK_MASK (1<<6)
1137#define M98090_JDWK_SHIFT 6
1138#define M98090_JDWK_WIDTH 1
1139#define M98090_JDEB_MASK (3<<0)
1140#define M98090_JDEB_SHIFT 0
1141#define M98090_JDEB_WIDTH 2
1142#define M98090_JDEB_25MS (0<<0)
1143#define M98090_JDEB_50MS (1<<0)
1144#define M98090_JDEB_100MS (2<<0)
1145#define M98090_JDEB_200MS (3<<0)
1146
1147/*
1148 * M98090_REG_INPUT_ENABLE
1149 */
1150#define M98090_MBEN_MASK (1<<4)
1151#define M98090_MBEN_SHIFT 4
1152#define M98090_MBEN_WIDTH 1
1153#define M98090_LINEAEN_MASK (1<<3)
1154#define M98090_LINEAEN_SHIFT 3
1155#define M98090_LINEAEN_WIDTH 1
1156#define M98090_LINEBEN_MASK (1<<2)
1157#define M98090_LINEBEN_SHIFT 2
1158#define M98090_LINEBEN_WIDTH 1
1159#define M98090_ADREN_MASK (1<<1)
1160#define M98090_ADREN_SHIFT 1
1161#define M98090_ADREN_WIDTH 1
1162#define M98090_ADLEN_MASK (1<<0)
1163#define M98090_ADLEN_SHIFT 0
1164#define M98090_ADLEN_WIDTH 1
1165
1166/*
1167 * M98090_REG_OUTPUT_ENABLE
1168 */
1169#define M98090_HPREN_MASK (1<<7)
1170#define M98090_HPREN_SHIFT 7
1171#define M98090_HPREN_WIDTH 1
1172#define M98090_HPLEN_MASK (1<<6)
1173#define M98090_HPLEN_SHIFT 6
1174#define M98090_HPLEN_WIDTH 1
1175#define M98090_SPREN_MASK (1<<5)
1176#define M98090_SPREN_SHIFT 5
1177#define M98090_SPREN_WIDTH 1
1178#define M98090_SPLEN_MASK (1<<4)
1179#define M98090_SPLEN_SHIFT 4
1180#define M98090_SPLEN_WIDTH 1
1181#define M98090_RCVLEN_MASK (1<<3)
1182#define M98090_RCVLEN_SHIFT 3
1183#define M98090_RCVLEN_WIDTH 1
1184#define M98090_RCVREN_MASK (1<<2)
1185#define M98090_RCVREN_SHIFT 2
1186#define M98090_RCVREN_WIDTH 1
1187#define M98090_DAREN_MASK (1<<1)
1188#define M98090_DAREN_SHIFT 1
1189#define M98090_DAREN_WIDTH 1
1190#define M98090_DALEN_MASK (1<<0)
1191#define M98090_DALEN_SHIFT 0
1192#define M98090_DALEN_WIDTH 1
1193
1194/*
1195 * M98090_REG_LEVEL_CONTROL
1196 */
1197#define M98090_ZDENN_MASK (1<<2)
1198#define M98090_ZDENN_SHIFT 2
1199#define M98090_ZDENN_WIDTH 1
1200#define M98090_ZDENN_NUM (1<<M98090_ZDENN_WIDTH)
1201#define M98090_VS2ENN_MASK (1<<1)
1202#define M98090_VS2ENN_SHIFT 1
1203#define M98090_VS2ENN_WIDTH 1
1204#define M98090_VS2ENN_NUM (1<<M98090_VS2ENN_WIDTH)
1205#define M98090_VSENN_MASK (1<<0)
1206#define M98090_VSENN_SHIFT 0
1207#define M98090_VSENN_WIDTH 1
1208#define M98090_VSENN_NUM (1<<M98090_VSENN_WIDTH)
1209
1210/*
1211 * M98090_REG_DSP_FILTER_ENABLE
1212 */
1213#define M98090_DMIC34BQEN_MASK (1<<4)
1214#define M98090_DMIC34BQEN_SHIFT 4
1215#define M98090_DMIC34BQEN_WIDTH 1
1216#define M98090_DMIC34BQEN_NUM (1<<M98090_DMIC34BQEN_WIDTH)
1217#define M98090_ADCBQEN_MASK (1<<3)
1218#define M98090_ADCBQEN_SHIFT 3
1219#define M98090_ADCBQEN_WIDTH 1
1220#define M98090_ADCBQEN_NUM (1<<M98090_ADCBQEN_WIDTH)
1221#define M98090_EQ3BANDEN_MASK (1<<2)
1222#define M98090_EQ3BANDEN_SHIFT 2
1223#define M98090_EQ3BANDEN_WIDTH 1
1224#define M98090_EQ3BANDEN_NUM (1<<M98090_EQ3BANDEN_WIDTH)
1225#define M98090_EQ5BANDEN_MASK (1<<1)
1226#define M98090_EQ5BANDEN_SHIFT 1
1227#define M98090_EQ5BANDEN_WIDTH 1
1228#define M98090_EQ5BANDEN_NUM (1<<M98090_EQ5BANDEN_WIDTH)
1229#define M98090_EQ7BANDEN_MASK (1<<0)
1230#define M98090_EQ7BANDEN_SHIFT 0
1231#define M98090_EQ7BANDEN_WIDTH 1
1232#define M98090_EQ7BANDEN_NUM (1<<M98090_EQ7BANDEN_WIDTH)
1233
1234/*
1235 * M98090_REG_BIAS_CONTROL
1236 */
1237#define M98090_VCM_MODE_MASK (1<<0)
1238#define M98090_VCM_MODE_SHIFT 0
1239#define M98090_VCM_MODE_WIDTH 1
1240#define M98090_VCM_MODE_NUM (1<<M98090_VCM_MODE_WIDTH)
1241
1242/*
1243 * M98090_REG_DAC_CONTROL
1244 */
1245#define M98090_PERFMODE_MASK (1<<1)
1246#define M98090_PERFMODE_SHIFT 1
1247#define M98090_PERFMODE_WIDTH 1
1248#define M98090_PERFMODE_NUM (1<<M98090_PERFMODE_WIDTH)
1249#define M98090_DACHP_MASK (1<<0)
1250#define M98090_DACHP_SHIFT 0
1251#define M98090_DACHP_WIDTH 1
1252#define M98090_DACHP_NUM (1<<M98090_DACHP_WIDTH)
1253
1254/*
1255 * M98090_REG_ADC_CONTROL
1256 */
1257#define M98090_OSR128_MASK (1<<2)
1258#define M98090_OSR128_SHIFT 2
1259#define M98090_OSR128_WIDTH 1
1260#define M98090_ADCDITHER_MASK (1<<1)
1261#define M98090_ADCDITHER_SHIFT 1
1262#define M98090_ADCDITHER_WIDTH 1
1263#define M98090_ADCDITHER_NUM (1<<M98090_ADCDITHER_WIDTH)
1264#define M98090_ADCHP_MASK (1<<0)
1265#define M98090_ADCHP_SHIFT 0
1266#define M98090_ADCHP_WIDTH 1
1267#define M98090_ADCHP_NUM (1<<M98090_ADCHP_WIDTH)
1268
1269/*
1270 * M98090_REG_DEVICE_SHUTDOWN
1271 */
1272#define M98090_SHDNN_MASK (1<<7)
1273#define M98090_SHDNN_SHIFT 7
1274#define M98090_SHDNN_WIDTH 1
1275
1276/*
1277 * M98090_REG_EQUALIZER_BASE
1278 */
1279#define M98090_B0_1_HI_MASK (255<<0)
1280#define M98090_B0_1_HI_SHIFT 0
1281#define M98090_B0_1_HI_WIDTH 8
1282#define M98090_B0_1_MID_MASK (255<<0)
1283#define M98090_B0_1_MID_SHIFT 0
1284#define M98090_B0_1_MID_WIDTH 8
1285#define M98090_B0_1_LO_MASK (255<<0)
1286#define M98090_B0_1_LO_SHIFT 0
1287#define M98090_B0_1_LO_WIDTH 8
1288#define M98090_B1_1_HI_MASK (255<<0)
1289#define M98090_B1_1_HI_SHIFT 0
1290#define M98090_B1_1_HI_WIDTH 8
1291#define M98090_B1_1_MID_MASK (255<<0)
1292#define M98090_B1_1_MID_SHIFT 0
1293#define M98090_B1_1_MID_WIDTH 8
1294#define M98090_B1_1_LO_MASK (255<<0)
1295#define M98090_B1_1_LO_SHIFT 0
1296#define M98090_B1_1_LO_WIDTH 8
1297#define M98090_B2_1_HI_MASK (255<<0)
1298#define M98090_B2_1_HI_SHIFT 0
1299#define M98090_B2_1_HI_WIDTH 8
1300#define M98090_B2_1_MID_MASK (255<<0)
1301#define M98090_B2_1_MID_SHIFT 0
1302#define M98090_B2_1_MID_WIDTH 8
1303#define M98090_B2_1_LO_MASK (255<<0)
1304#define M98090_B2_1_LO_SHIFT 0
1305#define M98090_B2_1_LO_WIDTH 8
1306#define M98090_A1_1_HI_MASK (255<<0)
1307#define M98090_A1_1_HI_SHIFT 0
1308#define M98090_A1_1_HI_WIDTH 8
1309#define M98090_A1_1_MID_MASK (255<<0)
1310#define M98090_A1_1_MID_SHIFT 0
1311#define M98090_A1_1_MID_WIDTH 8
1312#define M98090_A1_1_LO_MASK (255<<0)
1313#define M98090_A1_1_LO_SHIFT 0
1314#define M98090_A1_1_LO_WIDTH 8
1315#define M98090_A2_1_HI_MASK (255<<0)
1316#define M98090_A2_1_HI_SHIFT 0
1317#define M98090_A2_1_HI_WIDTH 8
1318#define M98090_A2_1_MID_MASK (255<<0)
1319#define M98090_A2_1_MID_SHIFT 0
1320#define M98090_A2_1_MID_WIDTH 8
1321#define M98090_A2_1_LO_MASK (255<<0)
1322#define M98090_A2_1_LO_SHIFT 0
1323#define M98090_A2_1_LO_WIDTH 8
1324
1325#define M98090_COEFS_PER_BAND 5
1326#define M98090_COEFS_BLK_SZ (M98090_COEFS_PER_BAND * 3)
1327#define M98090_COEFS_MAX_SZ (M98090_COEFS_BLK_SZ * 7)
1328
1329/*
1330 * M98090_REG_RECORD_BIQUAD_BASE
1331 */
1332#define M98090_REC_B0_HI_MASK (255<<0)
1333#define M98090_REC_B0_HI_SHIFT 0
1334#define M98090_REC_B0_HI_WIDTH 8
1335#define M98090_REC_B0_MID_MASK (255<<0)
1336#define M98090_REC_B0_MID_SHIFT 0
1337#define M98090_REC_B0_MID_WIDTH 8
1338#define M98090_REC_B0_LO_MASK (255<<0)
1339#define M98090_REC_B0_LO_SHIFT 0
1340#define M98090_REC_B0_LO_WIDTH 8
1341#define M98090_REC_B1_HI_MASK (255<<0)
1342#define M98090_REC_B1_HI_SHIFT 0
1343#define M98090_REC_B1_HI_WIDTH 8
1344#define M98090_REC_B1_MID_MASK (255<<0)
1345#define M98090_REC_B1_MID_SHIFT 0
1346#define M98090_REC_B1_MID_WIDTH 8
1347#define M98090_REC_B1_LO_MASK (255<<0)
1348#define M98090_REC_B1_LO_SHIFT 0
1349#define M98090_REC_B1_LO_WIDTH 8
1350#define M98090_REC_B2_HI_MASK (255<<0)
1351#define M98090_REC_B2_HI_SHIFT 0
1352#define M98090_REC_B2_HI_WIDTH 8
1353#define M98090_REC_B2_MID_MASK (255<<0)
1354#define M98090_REC_B2_MID_SHIFT 0
1355#define M98090_REC_B2_MID_WIDTH 8
1356#define M98090_REC_B2_LO_MASK (255<<0)
1357#define M98090_REC_B2_LO_SHIFT 0
1358#define M98090_REC_B2_LO_WIDTH 8
1359#define M98090_REC_A1_HI_MASK (255<<0)
1360#define M98090_REC_A1_HI_SHIFT 0
1361#define M98090_REC_A1_HI_WIDTH 8
1362#define M98090_REC_A1_MID_MASK (255<<0)
1363#define M98090_REC_A1_MID_SHIFT 0
1364#define M98090_REC_A1_MID_WIDTH 8
1365#define M98090_REC_A1_LO_MASK (255<<0)
1366#define M98090_REC_A1_LO_SHIFT 0
1367#define M98090_REC_A1_LO_WIDTH 8
1368#define M98090_REC_A2_HI_MASK (255<<0)
1369#define M98090_REC_A2_HI_SHIFT 0
1370#define M98090_REC_A2_HI_WIDTH 8
1371#define M98090_REC_A2_MID_MASK (255<<0)
1372#define M98090_REC_A2_MID_SHIFT 0
1373#define M98090_REC_A2_MID_WIDTH 8
1374#define M98090_REC_A2_LO_MASK (255<<0)
1375#define M98090_REC_A2_LO_SHIFT 0
1376#define M98090_REC_A2_LO_WIDTH 8
1377
1378/*
1379 * M98090_REG_DMIC3_VOLUME
1380 */
1381#define M98090_DMIC_AV3G_MASK (7<<4)
1382#define M98090_DMIC_AV3G_SHIFT 4
1383#define M98090_DMIC_AV3G_WIDTH 3
1384#define M98090_DMIC_AV3G_NUM (1<<M98090_DMIC_AV3G_WIDTH)
1385#define M98090_DMIC_AV3_MASK (15<<0)
1386#define M98090_DMIC_AV3_SHIFT 0
1387#define M98090_DMIC_AV3_WIDTH 4
1388#define M98090_DMIC_AV3_NUM (1<<M98090_DMIC_AV3_WIDTH)
1389
1390/*
1391 * M98090_REG_DMIC4_VOLUME
1392 */
1393#define M98090_DMIC_AV4G_MASK (7<<4)
1394#define M98090_DMIC_AV4G_SHIFT 4
1395#define M98090_DMIC_AV4G_WIDTH 3
1396#define M98090_DMIC_AV4G_NUM (1<<M98090_DMIC_AV4G_WIDTH)
1397#define M98090_DMIC_AV4_MASK (15<<0)
1398#define M98090_DMIC_AV4_SHIFT 0
1399#define M98090_DMIC_AV4_WIDTH 4
1400#define M98090_DMIC_AV4_NUM (1<<M98090_DMIC_AV4_WIDTH)
1401
1402/*
1403 * M98090_REG_DMIC34_BQ_PREATTEN
1404 */
1405#define M98090_AV34BQ_MASK (15<<0)
1406#define M98090_AV34BQ_SHIFT 0
1407#define M98090_AV34BQ_WIDTH 4
1408#define M98090_AV34BQ_NUM (1<<M98090_AV34BQ_WIDTH)
1409
1410/*
1411 * M98090_REG_RECORD_TDM_SLOT
1412 */
1413#define M98090_TDM_SLOTADCL_MASK (3<<6)
1414#define M98090_TDM_SLOTADCL_SHIFT 6
1415#define M98090_TDM_SLOTADCL_WIDTH 2
1416#define M98090_TDM_SLOTADCL_NUM (1<<M98090_TDM_SLOTADCL_WIDTH)
1417#define M98090_TDM_SLOTADCR_MASK (3<<4)
1418#define M98090_TDM_SLOTADCR_SHIFT 4
1419#define M98090_TDM_SLOTADCR_WIDTH 2
1420#define M98090_TDM_SLOTADCR_NUM (1<<M98090_TDM_SLOTADCR_WIDTH)
1421#define M98090_TDM_SLOTDMIC3_MASK (3<<2)
1422#define M98090_TDM_SLOTDMIC3_SHIFT 2
1423#define M98090_TDM_SLOTDMIC3_WIDTH 2
1424#define M98090_TDM_SLOTDMIC3_NUM (1<<M98090_TDM_SLOTDMIC3_WIDTH)
1425#define M98090_TDM_SLOTDMIC4_MASK (3<<0)
1426#define M98090_TDM_SLOTDMIC4_SHIFT 0
1427#define M98090_TDM_SLOTDMIC4_WIDTH 2
1428#define M98090_TDM_SLOTDMIC4_NUM (1<<M98090_TDM_SLOTDMIC4_WIDTH)
1429
1430/*
1431 * M98090_REG_SAMPLE_RATE
1432 */
1433#define M98090_DMIC34_ZEROPAD_MASK (1<<4)
1434#define M98090_DMIC34_ZEROPAD_SHIFT 4
1435#define M98090_DMIC34_ZEROPAD_WIDTH 1
1436#define M98090_DMIC34_ZEROPAD_NUM (1<<M98090_DIGMIC4_WIDTH)
1437#define M98090_DMIC34_SRDIV_MASK (7<<0)
1438#define M98090_DMIC34_SRDIV_SHIFT 0
1439#define M98090_DMIC34_SRDIV_WIDTH 3
1440
1441/*
1442 * M98090_REG_DMIC34_BIQUAD_BASE
1443 */
1444#define M98090_DMIC34_B0_HI_MASK (255<<0)
1445#define M98090_DMIC34_B0_HI_SHIFT 0
1446#define M98090_DMIC34_B0_HI_WIDTH 8
1447#define M98090_DMIC34_B0_MID_MASK (255<<0)
1448#define M98090_DMIC34_B0_MID_SHIFT 0
1449#define M98090_DMIC34_B0_MID_WIDTH 8
1450#define M98090_DMIC34_B0_LO_MASK (255<<0)
1451#define M98090_DMIC34_B0_LO_SHIFT 0
1452#define M98090_DMIC34_B0_LO_WIDTH 8
1453#define M98090_DMIC34_B1_HI_MASK (255<<0)
1454#define M98090_DMIC34_B1_HI_SHIFT 0
1455#define M98090_DMIC34_B1_HI_WIDTH 8
1456#define M98090_DMIC34_B1_MID_MASK (255<<0)
1457#define M98090_DMIC34_B1_MID_SHIFT 0
1458#define M98090_DMIC34_B1_MID_WIDTH 8
1459#define M98090_DMIC34_B1_LO_MASK (255<<0)
1460#define M98090_DMIC34_B1_LO_SHIFT 0
1461#define M98090_DMIC34_B1_LO_WIDTH 8
1462#define M98090_DMIC34_B2_HI_MASK (255<<0)
1463#define M98090_DMIC34_B2_HI_SHIFT 0
1464#define M98090_DMIC34_B2_HI_WIDTH 8
1465#define M98090_DMIC34_B2_MID_MASK (255<<0)
1466#define M98090_DMIC34_B2_MID_SHIFT 0
1467#define M98090_DMIC34_B2_MID_WIDTH 8
1468#define M98090_DMIC34_B2_LO_MASK (255<<0)
1469#define M98090_DMIC34_B2_LO_SHIFT 0
1470#define M98090_DMIC34_B2_LO_WIDTH 8
1471#define M98090_DMIC34_A1_HI_MASK (255<<0)
1472#define M98090_DMIC34_A1_HI_SHIFT 0
1473#define M98090_DMIC34_A1_HI_WIDTH 8
1474#define M98090_DMIC34_A1_MID_MASK (255<<0)
1475#define M98090_DMIC34_A1_MID_SHIFT 0
1476#define M98090_DMIC34_A1_MID_WIDTH 8
1477#define M98090_DMIC34_A1_LO_MASK (255<<0)
1478#define M98090_DMIC34_A1_LO_SHIFT 0
1479#define M98090_DMIC34_A1_LO_WIDTH 8
1480#define M98090_DMIC34_A2_HI_MASK (255<<0)
1481#define M98090_DMIC34_A2_HI_SHIFT 0
1482#define M98090_DMIC34_A2_HI_WIDTH 8
1483#define M98090_DMIC34_A2_MID_MASK (255<<0)
1484#define M98090_DMIC34_A2_MID_SHIFT 0
1485#define M98090_DMIC34_A2_MID_WIDTH 8
1486#define M98090_DMIC34_A2_LO_MASK (255<<0)
1487#define M98090_DMIC34_A2_LO_SHIFT 0
1488#define M98090_DMIC34_A2_LO_WIDTH 8
1489
1490#define M98090_JACK_STATE_NO_HEADSET 0
1491#define M98090_JACK_STATE_NO_HEADSET_2 1
1492#define M98090_JACK_STATE_HEADPHONE 2
1493#define M98090_JACK_STATE_HEADSET 3
1494
1495/*
1496 * M98090_REG_REVISION_ID
1497 */
1498#define M98090_REVID_MASK (255<<0)
1499#define M98090_REVID_SHIFT 0
1500#define M98090_REVID_WIDTH 8
1501#define M98090_REVID_NUM (1<<M98090_REVID_WIDTH)
1502
1503/* Silicon revision number */
1504#define M98090_REVA 0x40
1505#define M98091_REVA 0x50
1506
1507enum max98090_type {
1508 MAX98090,
1509 MAX98091,
1510};
1511
1512struct max98090_cdata {
1513 unsigned int rate;
1514 unsigned int fmt;
1515};
1516
1517struct max98090_priv {
1518 struct regmap *regmap;
1519 struct snd_soc_component *component;
1520 enum max98090_type devtype;
1521 struct max98090_pdata *pdata;
1522 struct clk *mclk;
1523 unsigned int sysclk;
1524 unsigned int pclk;
1525 unsigned int bclk;
1526 unsigned int lrclk;
1527 u32 dmic_freq;
1528 struct max98090_cdata dai[1];
1529 int jack_state;
1530 struct delayed_work jack_work;
1531 struct delayed_work pll_det_enable_work;
1532 struct work_struct pll_det_disable_work;
1533 struct snd_soc_jack *jack;
1534 unsigned int dai_fmt;
1535 int tdm_slots;
1536 int tdm_lslot;
1537 int tdm_rslot;
1538 u8 lin_state;
1539 unsigned int pa1en;
1540 unsigned int pa2en;
1541 unsigned int sidetone;
1542 bool master;
1543 bool shdn_pending;
1544};
1545
1546int max98090_mic_detect(struct snd_soc_component *component,
1547 struct snd_soc_jack *jack);
1548
1549#endif
1/*
2 * max98090.h -- MAX98090 ALSA SoC Audio driver
3 *
4 * Copyright 2011-2012 Maxim Integrated Products
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef _MAX98090_H
12#define _MAX98090_H
13
14#include <linux/version.h>
15
16/* One can override the Linux version here with an explicit version number */
17#define M98090_LINUX_VERSION LINUX_VERSION_CODE
18
19/*
20 * MAX98090 Register Definitions
21 */
22
23#define M98090_REG_SOFTWARE_RESET 0x00
24#define M98090_REG_DEVICE_STATUS 0x01
25#define M98090_REG_JACK_STATUS 0x02
26#define M98090_REG_INTERRUPT_S 0x03
27#define M98090_REG_QUICK_SYSTEM_CLOCK 0x04
28#define M98090_REG_QUICK_SAMPLE_RATE 0x05
29#define M98090_REG_DAI_INTERFACE 0x06
30#define M98090_REG_DAC_PATH 0x07
31#define M98090_REG_MIC_DIRECT_TO_ADC 0x08
32#define M98090_REG_LINE_TO_ADC 0x09
33#define M98090_REG_ANALOG_MIC_LOOP 0x0A
34#define M98090_REG_ANALOG_LINE_LOOP 0x0B
35#define M98090_REG_RESERVED 0x0C
36#define M98090_REG_LINE_INPUT_CONFIG 0x0D
37#define M98090_REG_LINE_INPUT_LEVEL 0x0E
38#define M98090_REG_INPUT_MODE 0x0F
39#define M98090_REG_MIC1_INPUT_LEVEL 0x10
40#define M98090_REG_MIC2_INPUT_LEVEL 0x11
41#define M98090_REG_MIC_BIAS_VOLTAGE 0x12
42#define M98090_REG_DIGITAL_MIC_ENABLE 0x13
43#define M98090_REG_DIGITAL_MIC_CONFIG 0x14
44#define M98090_REG_LEFT_ADC_MIXER 0x15
45#define M98090_REG_RIGHT_ADC_MIXER 0x16
46#define M98090_REG_LEFT_ADC_LEVEL 0x17
47#define M98090_REG_RIGHT_ADC_LEVEL 0x18
48#define M98090_REG_ADC_BIQUAD_LEVEL 0x19
49#define M98090_REG_ADC_SIDETONE 0x1A
50#define M98090_REG_SYSTEM_CLOCK 0x1B
51#define M98090_REG_CLOCK_MODE 0x1C
52#define M98090_REG_CLOCK_RATIO_NI_MSB 0x1D
53#define M98090_REG_CLOCK_RATIO_NI_LSB 0x1E
54#define M98090_REG_CLOCK_RATIO_MI_MSB 0x1F
55#define M98090_REG_CLOCK_RATIO_MI_LSB 0x20
56#define M98090_REG_MASTER_MODE 0x21
57#define M98090_REG_INTERFACE_FORMAT 0x22
58#define M98090_REG_TDM_CONTROL 0x23
59#define M98090_REG_TDM_FORMAT 0x24
60#define M98090_REG_IO_CONFIGURATION 0x25
61#define M98090_REG_FILTER_CONFIG 0x26
62#define M98090_REG_DAI_PLAYBACK_LEVEL 0x27
63#define M98090_REG_DAI_PLAYBACK_LEVEL_EQ 0x28
64#define M98090_REG_LEFT_HP_MIXER 0x29
65#define M98090_REG_RIGHT_HP_MIXER 0x2A
66#define M98090_REG_HP_CONTROL 0x2B
67#define M98090_REG_LEFT_HP_VOLUME 0x2C
68#define M98090_REG_RIGHT_HP_VOLUME 0x2D
69#define M98090_REG_LEFT_SPK_MIXER 0x2E
70#define M98090_REG_RIGHT_SPK_MIXER 0x2F
71#define M98090_REG_SPK_CONTROL 0x30
72#define M98090_REG_LEFT_SPK_VOLUME 0x31
73#define M98090_REG_RIGHT_SPK_VOLUME 0x32
74#define M98090_REG_DRC_TIMING 0x33
75#define M98090_REG_DRC_COMPRESSOR 0x34
76#define M98090_REG_DRC_EXPANDER 0x35
77#define M98090_REG_DRC_GAIN 0x36
78#define M98090_REG_RCV_LOUTL_MIXER 0x37
79#define M98090_REG_RCV_LOUTL_CONTROL 0x38
80#define M98090_REG_RCV_LOUTL_VOLUME 0x39
81#define M98090_REG_LOUTR_MIXER 0x3A
82#define M98090_REG_LOUTR_CONTROL 0x3B
83#define M98090_REG_LOUTR_VOLUME 0x3C
84#define M98090_REG_JACK_DETECT 0x3D
85#define M98090_REG_INPUT_ENABLE 0x3E
86#define M98090_REG_OUTPUT_ENABLE 0x3F
87#define M98090_REG_LEVEL_CONTROL 0x40
88#define M98090_REG_DSP_FILTER_ENABLE 0x41
89#define M98090_REG_BIAS_CONTROL 0x42
90#define M98090_REG_DAC_CONTROL 0x43
91#define M98090_REG_ADC_CONTROL 0x44
92#define M98090_REG_DEVICE_SHUTDOWN 0x45
93#define M98090_REG_EQUALIZER_BASE 0x46
94#define M98090_REG_RECORD_BIQUAD_BASE 0xAF
95#define M98090_REG_DMIC3_VOLUME 0xBE
96#define M98090_REG_DMIC4_VOLUME 0xBF
97#define M98090_REG_DMIC34_BQ_PREATTEN 0xC0
98#define M98090_REG_RECORD_TDM_SLOT 0xC1
99#define M98090_REG_SAMPLE_RATE 0xC2
100#define M98090_REG_DMIC34_BIQUAD_BASE 0xC3
101#define M98090_REG_REVISION_ID 0xFF
102
103#define M98090_REG_CNT (0xFF+1)
104#define MAX98090_MAX_REGISTER 0xFF
105
106/* MAX98090 Register Bit Fields */
107
108/*
109 * M98090_REG_SOFTWARE_RESET
110 */
111#define M98090_SWRESET_MASK (1<<7)
112#define M98090_SWRESET_SHIFT 7
113#define M98090_SWRESET_WIDTH 1
114
115/*
116 * M98090_REG_DEVICE_STATUS
117 */
118#define M98090_CLD_MASK (1<<7)
119#define M98090_CLD_SHIFT 7
120#define M98090_CLD_WIDTH 1
121#define M98090_SLD_MASK (1<<6)
122#define M98090_SLD_SHIFT 6
123#define M98090_SLD_WIDTH 1
124#define M98090_ULK_MASK (1<<5)
125#define M98090_ULK_SHIFT 5
126#define M98090_ULK_WIDTH 1
127#define M98090_JDET_MASK (1<<2)
128#define M98090_JDET_SHIFT 2
129#define M98090_JDET_WIDTH 1
130#define M98090_DRCACT_MASK (1<<1)
131#define M98090_DRCACT_SHIFT 1
132#define M98090_DRCACT_WIDTH 1
133#define M98090_DRCCLP_MASK (1<<0)
134#define M98090_DRCCLP_SHIFT 0
135#define M98090_DRCCLP_WIDTH 1
136
137/*
138 * M98090_REG_JACK_STATUS
139 */
140#define M98090_LSNS_MASK (1<<2)
141#define M98090_LSNS_SHIFT 2
142#define M98090_LSNS_WIDTH 1
143#define M98090_JKSNS_MASK (1<<1)
144#define M98090_JKSNS_SHIFT 1
145#define M98090_JKSNS_WIDTH 1
146
147/*
148 * M98090_REG_INTERRUPT_S
149 */
150#define M98090_ICLD_MASK (1<<7)
151#define M98090_ICLD_SHIFT 7
152#define M98090_ICLD_WIDTH 1
153#define M98090_ISLD_MASK (1<<6)
154#define M98090_ISLD_SHIFT 6
155#define M98090_ISLD_WIDTH 1
156#define M98090_IULK_MASK (1<<5)
157#define M98090_IULK_SHIFT 5
158#define M98090_IULK_WIDTH 1
159#define M98090_IJDET_MASK (1<<2)
160#define M98090_IJDET_SHIFT 2
161#define M98090_IJDET_WIDTH 1
162#define M98090_IDRCACT_MASK (1<<1)
163#define M98090_IDRCACT_SHIFT 1
164#define M98090_IDRCACT_WIDTH 1
165#define M98090_IDRCCLP_MASK (1<<0)
166#define M98090_IDRCCLP_SHIFT 0
167#define M98090_IDRCCLP_WIDTH 1
168
169/*
170 * M98090_REG_QUICK_SYSTEM_CLOCK
171 */
172#define M98090_26M_MASK (1<<7)
173#define M98090_26M_SHIFT 7
174#define M98090_26M_WIDTH 1
175#define M98090_19P2M_MASK (1<<6)
176#define M98090_19P2M_SHIFT 6
177#define M98090_19P2M_WIDTH 1
178#define M98090_13M_MASK (1<<5)
179#define M98090_13M_SHIFT 5
180#define M98090_13M_WIDTH 1
181#define M98090_12P288M_MASK (1<<4)
182#define M98090_12P288M_SHIFT 4
183#define M98090_12P288M_WIDTH 1
184#define M98090_12M_MASK (1<<3)
185#define M98090_12M_SHIFT 3
186#define M98090_12M_WIDTH 1
187#define M98090_11P2896M_MASK (1<<2)
188#define M98090_11P2896M_SHIFT 2
189#define M98090_11P2896M_WIDTH 1
190#define M98090_256FS_MASK (1<<0)
191#define M98090_256FS_SHIFT 0
192#define M98090_256FS_WIDTH 1
193#define M98090_CLK_ALL_SHIFT 0
194#define M98090_CLK_ALL_WIDTH 8
195#define M98090_CLK_ALL_NUM (1<<M98090_CLK_ALL_WIDTH)
196
197/*
198 * M98090_REG_QUICK_SAMPLE_RATE
199 */
200#define M98090_SR_96K_MASK (1<<5)
201#define M98090_SR_96K_SHIFT 5
202#define M98090_SR_96K_WIDTH 1
203#define M98090_SR_32K_MASK (1<<4)
204#define M98090_SR_32K_SHIFT 4
205#define M98090_SR_32K_WIDTH 1
206#define M98090_SR_48K_MASK (1<<3)
207#define M98090_SR_48K_SHIFT 3
208#define M98090_SR_48K_WIDTH 1
209#define M98090_SR_44K1_MASK (1<<2)
210#define M98090_SR_44K1_SHIFT 2
211#define M98090_SR_44K1_WIDTH 1
212#define M98090_SR_16K_MASK (1<<1)
213#define M98090_SR_16K_SHIFT 1
214#define M98090_SR_16K_WIDTH 1
215#define M98090_SR_8K_MASK (1<<0)
216#define M98090_SR_8K_SHIFT 0
217#define M98090_SR_8K_WIDTH 1
218#define M98090_SR_MASK 0x3F
219#define M98090_SR_ALL_SHIFT 0
220#define M98090_SR_ALL_WIDTH 8
221#define M98090_SR_ALL_NUM (1<<M98090_SR_ALL_WIDTH)
222
223/*
224 * M98090_REG_DAI_INTERFACE
225 */
226#define M98090_RJ_M_MASK (1<<5)
227#define M98090_RJ_M_SHIFT 5
228#define M98090_RJ_M_WIDTH 1
229#define M98090_RJ_S_MASK (1<<4)
230#define M98090_RJ_S_SHIFT 4
231#define M98090_RJ_S_WIDTH 1
232#define M98090_LJ_M_MASK (1<<3)
233#define M98090_LJ_M_SHIFT 3
234#define M98090_LJ_M_WIDTH 1
235#define M98090_LJ_S_MASK (1<<2)
236#define M98090_LJ_S_SHIFT 2
237#define M98090_LJ_S_WIDTH 1
238#define M98090_I2S_M_MASK (1<<1)
239#define M98090_I2S_M_SHIFT 1
240#define M98090_I2S_M_WIDTH 1
241#define M98090_I2S_S_MASK (1<<0)
242#define M98090_I2S_S_SHIFT 0
243#define M98090_I2S_S_WIDTH 1
244#define M98090_DAI_ALL_SHIFT 0
245#define M98090_DAI_ALL_WIDTH 8
246#define M98090_DAI_ALL_NUM (1<<M98090_DAI_ALL_WIDTH)
247
248/*
249 * M98090_REG_DAC_PATH
250 */
251#define M98090_DIG2_HP_MASK (1<<7)
252#define M98090_DIG2_HP_SHIFT 7
253#define M98090_DIG2_HP_WIDTH 1
254#define M98090_DIG2_EAR_MASK (1<<6)
255#define M98090_DIG2_EAR_SHIFT 6
256#define M98090_DIG2_EAR_WIDTH 1
257#define M98090_DIG2_SPK_MASK (1<<5)
258#define M98090_DIG2_SPK_SHIFT 5
259#define M98090_DIG2_SPK_WIDTH 1
260#define M98090_DIG2_LOUT_MASK (1<<4)
261#define M98090_DIG2_LOUT_SHIFT 4
262#define M98090_DIG2_LOUT_WIDTH 1
263#define M98090_DIG2_ALL_SHIFT 0
264#define M98090_DIG2_ALL_WIDTH 8
265#define M98090_DIG2_ALL_NUM (1<<M98090_DIG2_ALL_WIDTH)
266
267/*
268 * M98090_REG_MIC_DIRECT_TO_ADC
269 */
270#define M98090_IN12_MIC1_MASK (1<<7)
271#define M98090_IN12_MIC1_SHIFT 7
272#define M98090_IN12_MIC1_WIDTH 1
273#define M98090_IN34_MIC2_MASK (1<<6)
274#define M98090_IN34_MIC2_SHIFT 6
275#define M98090_IN34_MIC2_WIDTH 1
276#define M98090_IN56_MIC1_MASK (1<<5)
277#define M98090_IN56_MIC1_SHIFT 5
278#define M98090_IN56_MIC1_WIDTH 1
279#define M98090_IN56_MIC2_MASK (1<<4)
280#define M98090_IN56_MIC2_SHIFT 4
281#define M98090_IN56_MIC2_WIDTH 1
282#define M98090_IN12_DADC_MASK (1<<3)
283#define M98090_IN12_DADC_SHIFT 3
284#define M98090_IN12_DADC_WIDTH 1
285#define M98090_IN34_DADC_MASK (1<<2)
286#define M98090_IN34_DADC_SHIFT 2
287#define M98090_IN34_DADC_WIDTH 1
288#define M98090_IN56_DADC_MASK (1<<1)
289#define M98090_IN56_DADC_SHIFT 1
290#define M98090_IN56_DADC_WIDTH 1
291#define M98090_MIC_ALL_SHIFT 0
292#define M98090_MIC_ALL_WIDTH 8
293#define M98090_MIC_ALL_NUM (1<<M98090_MIC_ALL_WIDTH)
294
295/*
296 * M98090_REG_LINE_TO_ADC
297 */
298#define M98090_IN12S_AB_MASK (1<<7)
299#define M98090_IN12S_AB_SHIFT 7
300#define M98090_IN12S_AB_WIDTH 1
301#define M98090_IN34S_AB_MASK (1<<6)
302#define M98090_IN34S_AB_SHIFT 6
303#define M98090_IN34S_AB_WIDTH 1
304#define M98090_IN56S_AB_MASK (1<<5)
305#define M98090_IN56S_AB_SHIFT 5
306#define M98090_IN56S_AB_WIDTH 1
307#define M98090_IN34D_A_MASK (1<<4)
308#define M98090_IN34D_A_SHIFT 4
309#define M98090_IN34D_A_WIDTH 1
310#define M98090_IN56D_B_MASK (1<<3)
311#define M98090_IN56D_B_SHIFT 3
312#define M98090_IN56D_B_WIDTH 1
313#define M98090_LINE_ALL_SHIFT 0
314#define M98090_LINE_ALL_WIDTH 8
315#define M98090_LINE_ALL_NUM (1<<M98090_LINE_ALL_WIDTH)
316
317/*
318 * M98090_REG_ANALOG_MIC_LOOP
319 */
320#define M98090_IN12_M1HPL_MASK (1<<7)
321#define M98090_IN12_M1HPL_SHIFT 7
322#define M98090_IN12_M1HPL_WIDTH 1
323#define M98090_IN12_M1SPKL_MASK (1<<6)
324#define M98090_IN12_M1SPKL_SHIFT 6
325#define M98090_IN12_M1SPKL_WIDTH 1
326#define M98090_IN12_M1EAR_MASK (1<<5)
327#define M98090_IN12_M1EAR_SHIFT 5
328#define M98090_IN12_M1EAR_WIDTH 1
329#define M98090_IN12_M1LOUTL_MASK (1<<4)
330#define M98090_IN12_M1LOUTL_SHIFT 4
331#define M98090_IN12_M1LOUTL_WIDTH 1
332#define M98090_IN34_M2HPR_MASK (1<<3)
333#define M98090_IN34_M2HPR_SHIFT 3
334#define M98090_IN34_M2HPR_WIDTH 1
335#define M98090_IN34_M2SPKR_MASK (1<<2)
336#define M98090_IN34_M2SPKR_SHIFT 2
337#define M98090_IN34_M2SPKR_WIDTH 1
338#define M98090_IN34_M2EAR_MASK (1<<1)
339#define M98090_IN34_M2EAR_SHIFT 1
340#define M98090_IN34_M2EAR_WIDTH 1
341#define M98090_IN34_M2LOUTR_MASK (1<<0)
342#define M98090_IN34_M2LOUTR_SHIFT 0
343#define M98090_IN34_M2LOUTR_WIDTH 1
344#define M98090_AMIC_ALL_SHIFT 0
345#define M98090_AMIC_ALL_WIDTH 8
346#define M98090_AMIC_ALL_NUM (1<<M98090_AMIC_ALL_WIDTH)
347
348/*
349 * M98090_REG_ANALOG_LINE_LOOP
350 */
351#define M98090_IN12S_ABHP_MASK (1<<7)
352#define M98090_IN12S_ABHP_SHIFT 7
353#define M98090_IN12S_ABHP_WIDTH 1
354#define M98090_IN34D_ASPKL_MASK (1<<6)
355#define M98090_IN34D_ASPKL_SHIFT 6
356#define M98090_IN34D_ASPKL_WIDTH 1
357#define M98090_IN34D_AEAR_MASK (1<<5)
358#define M98090_IN34D_AEAR_SHIFT 5
359#define M98090_IN34D_AEAR_WIDTH 1
360#define M98090_IN12S_ABLOUT_MASK (1<<4)
361#define M98090_IN12S_ABLOUT_SHIFT 4
362#define M98090_IN12S_ABLOUT_WIDTH 1
363#define M98090_IN34S_ABHP_MASK (1<<3)
364#define M98090_IN34S_ABHP_SHIFT 3
365#define M98090_IN34S_ABHP_WIDTH 1
366#define M98090_IN56D_BSPKR_MASK (1<<2)
367#define M98090_IN56D_BSPKR_SHIFT 2
368#define M98090_IN56D_BSPKR_WIDTH 1
369#define M98090_IN56D_BEAR_MASK (1<<1)
370#define M98090_IN56D_BEAR_SHIFT 1
371#define M98090_IN56D_BEAR_WIDTH 1
372#define M98090_IN34S_ABLOUT_MASK (1<<0)
373#define M98090_IN34S_ABLOUT_SHIFT 0
374#define M98090_IN34S_ABLOUT_WIDTH 1
375#define M98090_ALIN_ALL_SHIFT 0
376#define M98090_ALIN_ALL_WIDTH 8
377#define M98090_ALIN_ALL_NUM (1<<M98090_ALIN_ALL_WIDTH)
378
379/*
380 * M98090_REG_RESERVED
381 */
382
383/*
384 * M98090_REG_LINE_INPUT_CONFIG
385 */
386#define M98090_IN34DIFF_MASK (1<<7)
387#define M98090_IN34DIFF_SHIFT 7
388#define M98090_IN34DIFF_WIDTH 1
389#define M98090_IN56DIFF_MASK (1<<6)
390#define M98090_IN56DIFF_SHIFT 6
391#define M98090_IN56DIFF_WIDTH 1
392#define M98090_IN1SEEN_MASK (1<<5)
393#define M98090_IN1SEEN_SHIFT 5
394#define M98090_IN1SEEN_WIDTH 1
395#define M98090_IN2SEEN_MASK (1<<4)
396#define M98090_IN2SEEN_SHIFT 4
397#define M98090_IN2SEEN_WIDTH 1
398#define M98090_IN3SEEN_MASK (1<<3)
399#define M98090_IN3SEEN_SHIFT 3
400#define M98090_IN3SEEN_WIDTH 1
401#define M98090_IN4SEEN_MASK (1<<2)
402#define M98090_IN4SEEN_SHIFT 2
403#define M98090_IN4SEEN_WIDTH 1
404#define M98090_IN5SEEN_MASK (1<<1)
405#define M98090_IN5SEEN_SHIFT 1
406#define M98090_IN5SEEN_WIDTH 1
407#define M98090_IN6SEEN_MASK (1<<0)
408#define M98090_IN6SEEN_SHIFT 0
409#define M98090_IN6SEEN_WIDTH 1
410
411/*
412 * M98090_REG_LINE_INPUT_LEVEL
413 */
414#define M98090_MIXG135_MASK (1<<7)
415#define M98090_MIXG135_SHIFT 7
416#define M98090_MIXG135_WIDTH 1
417#define M98090_MIXG135_NUM (1<<M98090_MIXG135_WIDTH)
418#define M98090_MIXG246_MASK (1<<6)
419#define M98090_MIXG246_SHIFT 6
420#define M98090_MIXG246_WIDTH 1
421#define M98090_MIXG246_NUM (1<<M98090_MIXG246_WIDTH)
422#define M98090_LINAPGA_MASK (7<<3)
423#define M98090_LINAPGA_SHIFT 3
424#define M98090_LINAPGA_WIDTH 3
425#define M98090_LINAPGA_NUM 6
426#define M98090_LINBPGA_MASK (7<<0)
427#define M98090_LINBPGA_SHIFT 0
428#define M98090_LINBPGA_WIDTH 3
429#define M98090_LINBPGA_NUM 6
430
431/*
432 * M98090_REG_INPUT_MODE
433 */
434#define M98090_EXTBUFA_MASK (1<<7)
435#define M98090_EXTBUFA_SHIFT 7
436#define M98090_EXTBUFA_WIDTH 1
437#define M98090_EXTBUFA_NUM (1<<M98090_EXTBUFA_WIDTH)
438#define M98090_EXTBUFB_MASK (1<<6)
439#define M98090_EXTBUFB_SHIFT 6
440#define M98090_EXTBUFB_WIDTH 1
441#define M98090_EXTBUFB_NUM (1<<M98090_EXTBUFB_WIDTH)
442#define M98090_EXTMIC_MASK (3<<0)
443#define M98090_EXTMIC_SHIFT 0
444#define M98090_EXTMIC1_SHIFT 0
445#define M98090_EXTMIC2_SHIFT 1
446#define M98090_EXTMIC_WIDTH 2
447#define M98090_EXTMIC_NONE (0<<0)
448#define M98090_EXTMIC_MIC1 (1<<0)
449#define M98090_EXTMIC_MIC2 (2<<0)
450
451/*
452 * M98090_REG_MIC1_INPUT_LEVEL
453 */
454#define M98090_MIC_PA1EN_MASK (3<<5)
455#define M98090_MIC_PA1EN_SHIFT 5
456#define M98090_MIC_PA1EN_WIDTH 2
457#define M98090_MIC_PA1EN_NUM 3
458#define M98090_MIC_PGAM1_MASK (31<<0)
459#define M98090_MIC_PGAM1_SHIFT 0
460#define M98090_MIC_PGAM1_WIDTH 5
461#define M98090_MIC_PGAM1_NUM 21
462
463/*
464 * M98090_REG_MIC2_INPUT_LEVEL
465 */
466#define M98090_MIC_PA2EN_MASK (3<<5)
467#define M98090_MIC_PA2EN_SHIFT 5
468#define M98090_MIC_PA2EN_WIDTH 2
469#define M98090_MIC_PA2EN_NUM 3
470#define M98090_MIC_PGAM2_MASK (31<<0)
471#define M98090_MIC_PGAM2_SHIFT 0
472#define M98090_MIC_PGAM2_WIDTH 5
473#define M98090_MIC_PGAM2_NUM 21
474
475/*
476 * M98090_REG_MIC_BIAS_VOLTAGE
477 */
478#define M98090_MBVSEL_MASK (3<<0)
479#define M98090_MBVSEL_SHIFT 0
480#define M98090_MBVSEL_WIDTH 2
481#define M98090_MBVSEL_2V8 (3<<0)
482#define M98090_MBVSEL_2V55 (2<<0)
483#define M98090_MBVSEL_2V4 (1<<0)
484#define M98090_MBVSEL_2V2 (0<<0)
485
486/*
487 * M98090_REG_DIGITAL_MIC_ENABLE
488 */
489#define M98090_MICCLK_MASK (7<<4)
490#define M98090_MICCLK_SHIFT 4
491#define M98090_MICCLK_WIDTH 3
492#define M98090_DIGMIC4_MASK (1<<3)
493#define M98090_DIGMIC4_SHIFT 3
494#define M98090_DIGMIC4_WIDTH 1
495#define M98090_DIGMIC4_NUM (1<<M98090_DIGMIC4_WIDTH)
496#define M98090_DIGMIC3_MASK (1<<2)
497#define M98090_DIGMIC3_SHIFT 2
498#define M98090_DIGMIC3_WIDTH 1
499#define M98090_DIGMIC3_NUM (1<<M98090_DIGMIC3_WIDTH)
500#define M98090_DIGMICR_MASK (1<<1)
501#define M98090_DIGMICR_SHIFT 1
502#define M98090_DIGMICR_WIDTH 1
503#define M98090_DIGMICR_NUM (1<<M98090_DIGMICR_WIDTH)
504#define M98090_DIGMICL_MASK (1<<0)
505#define M98090_DIGMICL_SHIFT 0
506#define M98090_DIGMICL_WIDTH 1
507#define M98090_DIGMICL_NUM (1<<M98090_DIGMICL_WIDTH)
508
509/*
510 * M98090_REG_DIGITAL_MIC_CONFIG
511 */
512#define M98090_DMIC_COMP_MASK (15<<4)
513#define M98090_DMIC_COMP_SHIFT 4
514#define M98090_DMIC_COMP_WIDTH 4
515#define M98090_DMIC_COMP_NUM (1<<M98090_DMIC_COMP_WIDTH)
516#define M98090_DMIC_FREQ_MASK (3<<0)
517#define M98090_DMIC_FREQ_SHIFT 0
518#define M98090_DMIC_FREQ_WIDTH 2
519
520/*
521 * M98090_REG_LEFT_ADC_MIXER
522 */
523#define M98090_MIXADL_MIC2_MASK (1<<6)
524#define M98090_MIXADL_MIC2_SHIFT 6
525#define M98090_MIXADL_MIC2_WIDTH 1
526#define M98090_MIXADL_MIC1_MASK (1<<5)
527#define M98090_MIXADL_MIC1_SHIFT 5
528#define M98090_MIXADL_MIC1_WIDTH 1
529#define M98090_MIXADL_LINEB_MASK (1<<4)
530#define M98090_MIXADL_LINEB_SHIFT 4
531#define M98090_MIXADL_LINEB_WIDTH 1
532#define M98090_MIXADL_LINEA_MASK (1<<3)
533#define M98090_MIXADL_LINEA_SHIFT 3
534#define M98090_MIXADL_LINEA_WIDTH 1
535#define M98090_MIXADL_IN65DIFF_MASK (1<<2)
536#define M98090_MIXADL_IN65DIFF_SHIFT 2
537#define M98090_MIXADL_IN65DIFF_WIDTH 1
538#define M98090_MIXADL_IN34DIFF_MASK (1<<1)
539#define M98090_MIXADL_IN34DIFF_SHIFT 1
540#define M98090_MIXADL_IN34DIFF_WIDTH 1
541#define M98090_MIXADL_IN12DIFF_MASK (1<<0)
542#define M98090_MIXADL_IN12DIFF_SHIFT 0
543#define M98090_MIXADL_IN12DIFF_WIDTH 1
544#define M98090_MIXADL_MASK (255<<0)
545#define M98090_MIXADL_SHIFT 0
546#define M98090_MIXADL_WIDTH 8
547
548/*
549 * M98090_REG_RIGHT_ADC_MIXER
550 */
551#define M98090_MIXADR_MIC2_MASK (1<<6)
552#define M98090_MIXADR_MIC2_SHIFT 6
553#define M98090_MIXADR_MIC2_WIDTH 1
554#define M98090_MIXADR_MIC1_MASK (1<<5)
555#define M98090_MIXADR_MIC1_SHIFT 5
556#define M98090_MIXADR_MIC1_WIDTH 1
557#define M98090_MIXADR_LINEB_MASK (1<<4)
558#define M98090_MIXADR_LINEB_SHIFT 4
559#define M98090_MIXADR_LINEB_WIDTH 1
560#define M98090_MIXADR_LINEA_MASK (1<<3)
561#define M98090_MIXADR_LINEA_SHIFT 3
562#define M98090_MIXADR_LINEA_WIDTH 1
563#define M98090_MIXADR_IN65DIFF_MASK (1<<2)
564#define M98090_MIXADR_IN65DIFF_SHIFT 2
565#define M98090_MIXADR_IN65DIFF_WIDTH 1
566#define M98090_MIXADR_IN34DIFF_MASK (1<<1)
567#define M98090_MIXADR_IN34DIFF_SHIFT 1
568#define M98090_MIXADR_IN34DIFF_WIDTH 1
569#define M98090_MIXADR_IN12DIFF_MASK (1<<0)
570#define M98090_MIXADR_IN12DIFF_SHIFT 0
571#define M98090_MIXADR_IN12DIFF_WIDTH 1
572#define M98090_MIXADR_MASK (255<<0)
573#define M98090_MIXADR_SHIFT 0
574#define M98090_MIXADR_WIDTH 8
575
576/*
577 * M98090_REG_LEFT_ADC_LEVEL
578 */
579#define M98090_AVLG_MASK (7<<4)
580#define M98090_AVLG_SHIFT 4
581#define M98090_AVLG_WIDTH 3
582#define M98090_AVLG_NUM (1<<M98090_AVLG_WIDTH)
583#define M98090_AVL_MASK (15<<0)
584#define M98090_AVL_SHIFT 0
585#define M98090_AVL_WIDTH 4
586#define M98090_AVL_NUM (1<<M98090_AVL_WIDTH)
587
588/*
589 * M98090_REG_RIGHT_ADC_LEVEL
590 */
591#define M98090_AVRG_MASK (7<<4)
592#define M98090_AVRG_SHIFT 4
593#define M98090_AVRG_WIDTH 3
594#define M98090_AVRG_NUM (1<<M98090_AVRG_WIDTH)
595#define M98090_AVR_MASK (15<<0)
596#define M98090_AVR_SHIFT 0
597#define M98090_AVR_WIDTH 4
598#define M98090_AVR_NUM (1<<M98090_AVR_WIDTH)
599
600/*
601 * M98090_REG_ADC_BIQUAD_LEVEL
602 */
603#define M98090_AVBQ_MASK (15<<0)
604#define M98090_AVBQ_SHIFT 0
605#define M98090_AVBQ_WIDTH 4
606#define M98090_AVBQ_NUM (1<<M98090_AVBQ_WIDTH)
607
608/*
609 * M98090_REG_ADC_SIDETONE
610 */
611#define M98090_DSTSR_MASK (1<<7)
612#define M98090_DSTSR_SHIFT 7
613#define M98090_DSTSR_WIDTH 1
614#define M98090_DSTSL_MASK (1<<6)
615#define M98090_DSTSL_SHIFT 6
616#define M98090_DSTSL_WIDTH 1
617#define M98090_DVST_MASK (31<<0)
618#define M98090_DVST_SHIFT 0
619#define M98090_DVST_WIDTH 5
620#define M98090_DVST_NUM 31
621
622/*
623 * M98090_REG_SYSTEM_CLOCK
624 */
625#define M98090_PSCLK_MASK (3<<4)
626#define M98090_PSCLK_SHIFT 4
627#define M98090_PSCLK_WIDTH 2
628#define M98090_PSCLK_DISABLED (0<<4)
629#define M98090_PSCLK_DIV1 (1<<4)
630#define M98090_PSCLK_DIV2 (2<<4)
631#define M98090_PSCLK_DIV4 (3<<4)
632
633/*
634 * M98090_REG_CLOCK_MODE
635 */
636#define M98090_FREQ_MASK (15<<4)
637#define M98090_FREQ_SHIFT 4
638#define M98090_FREQ_WIDTH 4
639#define M98090_USE_M1_MASK (1<<0)
640#define M98090_USE_M1_SHIFT 0
641#define M98090_USE_M1_WIDTH 1
642#define M98090_USE_M1_NUM (1<<M98090_USE_M1_WIDTH)
643
644/*
645 * M98090_REG_CLOCK_RATIO_NI_MSB
646 */
647#define M98090_NI_HI_MASK (127<<0)
648#define M98090_NI_HI_SHIFT 0
649#define M98090_NI_HI_WIDTH 7
650#define M98090_NI_HI_NUM (1<<M98090_NI_HI_WIDTH)
651
652/*
653 * M98090_REG_CLOCK_RATIO_NI_LSB
654 */
655#define M98090_NI_LO_MASK (255<<0)
656#define M98090_NI_LO_SHIFT 0
657#define M98090_NI_LO_WIDTH 8
658#define M98090_NI_LO_NUM (1<<M98090_NI_LO_WIDTH)
659
660/*
661 * M98090_REG_CLOCK_RATIO_MI_MSB
662 */
663#define M98090_MI_HI_MASK (255<<0)
664#define M98090_MI_HI_SHIFT 0
665#define M98090_MI_HI_WIDTH 8
666#define M98090_MI_HI_NUM (1<<M98090_MI_HI_WIDTH)
667
668/*
669 * M98090_REG_CLOCK_RATIO_MI_LSB
670 */
671#define M98090_MI_LO_MASK (255<<0)
672#define M98090_MI_LO_SHIFT 0
673#define M98090_MI_LO_WIDTH 8
674#define M98090_MI_LO_NUM (1<<M98090_MI_LO_WIDTH)
675
676/*
677 * M98090_REG_MASTER_MODE
678 */
679#define M98090_MAS_MASK (1<<7)
680#define M98090_MAS_SHIFT 7
681#define M98090_MAS_WIDTH 1
682#define M98090_BSEL_MASK (1<<0)
683#define M98090_BSEL_SHIFT 0
684#define M98090_BSEL_WIDTH 1
685#define M98090_BSEL_32 (1<<0)
686#define M98090_BSEL_48 (2<<0)
687#define M98090_BSEL_64 (3<<0)
688
689/*
690 * M98090_REG_INTERFACE_FORMAT
691 */
692#define M98090_RJ_MASK (1<<5)
693#define M98090_RJ_SHIFT 5
694#define M98090_RJ_WIDTH 1
695#define M98090_WCI_MASK (1<<4)
696#define M98090_WCI_SHIFT 4
697#define M98090_WCI_WIDTH 1
698#define M98090_BCI_MASK (1<<3)
699#define M98090_BCI_SHIFT 3
700#define M98090_BCI_WIDTH 1
701#define M98090_DLY_MASK (1<<2)
702#define M98090_DLY_SHIFT 2
703#define M98090_DLY_WIDTH 1
704#define M98090_WS_MASK (3<<0)
705#define M98090_WS_SHIFT 0
706#define M98090_WS_WIDTH 2
707#define M98090_WS_NUM (1<<M98090_WS_WIDTH)
708
709/*
710 * M98090_REG_TDM_CONTROL
711 */
712#define M98090_FSW_MASK (1<<1)
713#define M98090_FSW_SHIFT 1
714#define M98090_FSW_WIDTH 1
715#define M98090_TDM_MASK (1<<0)
716#define M98090_TDM_SHIFT 0
717#define M98090_TDM_WIDTH 1
718#define M98090_TDM_NUM (1<<M98090_TDM_WIDTH)
719
720/*
721 * M98090_REG_TDM_FORMAT
722 */
723#define M98090_TDM_SLOTL_MASK (3<<6)
724#define M98090_TDM_SLOTL_SHIFT 6
725#define M98090_TDM_SLOTL_WIDTH 2
726#define M98090_TDM_SLOTL_NUM (1<<M98090_TDM_SLOTL_WIDTH)
727#define M98090_TDM_SLOTR_MASK (3<<4)
728#define M98090_TDM_SLOTR_SHIFT 4
729#define M98090_TDM_SLOTR_WIDTH 2
730#define M98090_TDM_SLOTR_NUM (1<<M98090_TDM_SLOTR_WIDTH)
731#define M98090_TDM_SLOTDLY_MASK (15<<0)
732#define M98090_TDM_SLOTDLY_SHIFT 0
733#define M98090_TDM_SLOTDLY_WIDTH 4
734#define M98090_TDM_SLOTDLY_NUM (1<<M98090_TDM_SLOTDLY_WIDTH)
735
736/*
737 * M98090_REG_IO_CONFIGURATION
738 */
739#define M98090_LTEN_MASK (1<<5)
740#define M98090_LTEN_SHIFT 5
741#define M98090_LTEN_WIDTH 1
742#define M98090_LTEN_NUM (1<<M98090_LTEN_WIDTH)
743#define M98090_LBEN_MASK (1<<4)
744#define M98090_LBEN_SHIFT 4
745#define M98090_LBEN_WIDTH 1
746#define M98090_LBEN_NUM (1<<M98090_LBEN_WIDTH)
747#define M98090_DMONO_MASK (1<<3)
748#define M98090_DMONO_SHIFT 3
749#define M98090_DMONO_WIDTH 1
750#define M98090_DMONO_NUM (1<<M98090_DMONO_WIDTH)
751#define M98090_HIZOFF_MASK (1<<2)
752#define M98090_HIZOFF_SHIFT 2
753#define M98090_HIZOFF_WIDTH 1
754#define M98090_HIZOFF_NUM (1<<M98090_HIZOFF_WIDTH)
755#define M98090_SDOEN_MASK (1<<1)
756#define M98090_SDOEN_SHIFT 1
757#define M98090_SDOEN_WIDTH 1
758#define M98090_SDOEN_NUM (1<<M98090_SDOEN_WIDTH)
759#define M98090_SDIEN_MASK (1<<0)
760#define M98090_SDIEN_SHIFT 0
761#define M98090_SDIEN_WIDTH 1
762#define M98090_SDIEN_NUM (1<<M98090_SDIEN_WIDTH)
763
764/*
765 * M98090_REG_FILTER_CONFIG
766 */
767#define M98090_MODE_MASK (1<<7)
768#define M98090_MODE_SHIFT 7
769#define M98090_MODE_WIDTH 1
770#define M98090_AHPF_MASK (1<<6)
771#define M98090_AHPF_SHIFT 6
772#define M98090_AHPF_WIDTH 1
773#define M98090_AHPF_NUM (1<<M98090_AHPF_WIDTH)
774#define M98090_DHPF_MASK (1<<5)
775#define M98090_DHPF_SHIFT 5
776#define M98090_DHPF_WIDTH 1
777#define M98090_DHPF_NUM (1<<M98090_DHPF_WIDTH)
778#define M98090_DHF_MASK (1<<4)
779#define M98090_DHF_SHIFT 4
780#define M98090_DHF_WIDTH 1
781#define M98090_FLT_DMIC34MODE_MASK (1<<3)
782#define M98090_FLT_DMIC34MODE_SHIFT 3
783#define M98090_FLT_DMIC34MODE_WIDTH 1
784#define M98090_FLT_DMIC34HPF_MASK (1<<2)
785#define M98090_FLT_DMIC34HPF_SHIFT 2
786#define M98090_FLT_DMIC34HPF_WIDTH 1
787#define M98090_FLT_DMIC34HPF_NUM (1<<M98090_FLT_DMIC34HPF_WIDTH)
788
789/*
790 * M98090_REG_DAI_PLAYBACK_LEVEL
791 */
792#define M98090_DVM_MASK (1<<7)
793#define M98090_DVM_SHIFT 7
794#define M98090_DVM_WIDTH 1
795#define M98090_DVG_MASK (3<<4)
796#define M98090_DVG_SHIFT 4
797#define M98090_DVG_WIDTH 2
798#define M98090_DVG_NUM (1<<M98090_DVG_WIDTH)
799#define M98090_DV_MASK (15<<0)
800#define M98090_DV_SHIFT 0
801#define M98090_DV_WIDTH 4
802#define M98090_DV_NUM (1<<M98090_DV_WIDTH)
803
804/*
805 * M98090_REG_DAI_PLAYBACK_LEVEL_EQ
806 */
807#define M98090_EQCLPN_MASK (1<<4)
808#define M98090_EQCLPN_SHIFT 4
809#define M98090_EQCLPN_WIDTH 1
810#define M98090_EQCLPN_NUM (1<<M98090_EQCLPN_WIDTH)
811#define M98090_DVEQ_MASK (15<<0)
812#define M98090_DVEQ_SHIFT 0
813#define M98090_DVEQ_WIDTH 4
814#define M98090_DVEQ_NUM (1<<M98090_DVEQ_WIDTH)
815
816/*
817 * M98090_REG_LEFT_HP_MIXER
818 */
819#define M98090_MIXHPL_MIC2_MASK (1<<5)
820#define M98090_MIXHPL_MIC2_SHIFT 5
821#define M98090_MIXHPL_MIC2_WIDTH 1
822#define M98090_MIXHPL_MIC1_MASK (1<<4)
823#define M98090_MIXHPL_MIC1_SHIFT 4
824#define M98090_MIXHPL_MIC1_WIDTH 1
825#define M98090_MIXHPL_LINEB_MASK (1<<3)
826#define M98090_MIXHPL_LINEB_SHIFT 3
827#define M98090_MIXHPL_LINEB_WIDTH 1
828#define M98090_MIXHPL_LINEA_MASK (1<<2)
829#define M98090_MIXHPL_LINEA_SHIFT 2
830#define M98090_MIXHPL_LINEA_WIDTH 1
831#define M98090_MIXHPL_DACR_MASK (1<<1)
832#define M98090_MIXHPL_DACR_SHIFT 1
833#define M98090_MIXHPL_DACR_WIDTH 1
834#define M98090_MIXHPL_DACL_MASK (1<<0)
835#define M98090_MIXHPL_DACL_SHIFT 0
836#define M98090_MIXHPL_DACL_WIDTH 1
837#define M98090_MIXHPL_MASK (63<<0)
838#define M98090_MIXHPL_SHIFT 0
839#define M98090_MIXHPL_WIDTH 6
840
841/*
842 * M98090_REG_RIGHT_HP_MIXER
843 */
844#define M98090_MIXHPR_MIC2_MASK (1<<5)
845#define M98090_MIXHPR_MIC2_SHIFT 5
846#define M98090_MIXHPR_MIC2_WIDTH 1
847#define M98090_MIXHPR_MIC1_MASK (1<<4)
848#define M98090_MIXHPR_MIC1_SHIFT 4
849#define M98090_MIXHPR_MIC1_WIDTH 1
850#define M98090_MIXHPR_LINEB_MASK (1<<3)
851#define M98090_MIXHPR_LINEB_SHIFT 3
852#define M98090_MIXHPR_LINEB_WIDTH 1
853#define M98090_MIXHPR_LINEA_MASK (1<<2)
854#define M98090_MIXHPR_LINEA_SHIFT 2
855#define M98090_MIXHPR_LINEA_WIDTH 1
856#define M98090_MIXHPR_DACR_MASK (1<<1)
857#define M98090_MIXHPR_DACR_SHIFT 1
858#define M98090_MIXHPR_DACR_WIDTH 1
859#define M98090_MIXHPR_DACL_MASK (1<<0)
860#define M98090_MIXHPR_DACL_SHIFT 0
861#define M98090_MIXHPR_DACL_WIDTH 1
862#define M98090_MIXHPR_MASK (63<<0)
863#define M98090_MIXHPR_SHIFT 0
864#define M98090_MIXHPR_WIDTH 6
865
866/*
867 * M98090_REG_HP_CONTROL
868 */
869#define M98090_MIXHPRSEL_MASK (1<<5)
870#define M98090_MIXHPRSEL_SHIFT 5
871#define M98090_MIXHPRSEL_WIDTH 1
872#define M98090_MIXHPLSEL_MASK (1<<4)
873#define M98090_MIXHPLSEL_SHIFT 4
874#define M98090_MIXHPLSEL_WIDTH 1
875#define M98090_MIXHPRG_MASK (3<<2)
876#define M98090_MIXHPRG_SHIFT 2
877#define M98090_MIXHPRG_WIDTH 2
878#define M98090_MIXHPRG_NUM (1<<M98090_MIXHPRG_WIDTH)
879#define M98090_MIXHPLG_MASK (3<<0)
880#define M98090_MIXHPLG_SHIFT 0
881#define M98090_MIXHPLG_WIDTH 2
882#define M98090_MIXHPLG_NUM (1<<M98090_MIXHPLG_WIDTH)
883
884/*
885 * M98090_REG_LEFT_HP_VOLUME
886 */
887#define M98090_HPLM_MASK (1<<7)
888#define M98090_HPLM_SHIFT 7
889#define M98090_HPLM_WIDTH 1
890#define M98090_HPVOLL_MASK (31<<0)
891#define M98090_HPVOLL_SHIFT 0
892#define M98090_HPVOLL_WIDTH 5
893#define M98090_HPVOLL_NUM (1<<M98090_HPVOLL_WIDTH)
894
895/*
896 * M98090_REG_RIGHT_HP_VOLUME
897 */
898#define M98090_HPRM_MASK (1<<7)
899#define M98090_HPRM_SHIFT 7
900#define M98090_HPRM_WIDTH 1
901#define M98090_HPVOLR_MASK (31<<0)
902#define M98090_HPVOLR_SHIFT 0
903#define M98090_HPVOLR_WIDTH 5
904#define M98090_HPVOLR_NUM (1<<M98090_HPVOLR_WIDTH)
905
906/*
907 * M98090_REG_LEFT_SPK_MIXER
908 */
909#define M98090_MIXSPL_MIC2_MASK (1<<5)
910#define M98090_MIXSPL_MIC2_SHIFT 5
911#define M98090_MIXSPL_MIC2_WIDTH 1
912#define M98090_MIXSPL_MIC1_MASK (1<<4)
913#define M98090_MIXSPL_MIC1_SHIFT 4
914#define M98090_MIXSPL_MIC1_WIDTH 1
915#define M98090_MIXSPL_LINEB_MASK (1<<3)
916#define M98090_MIXSPL_LINEB_SHIFT 3
917#define M98090_MIXSPL_LINEB_WIDTH 1
918#define M98090_MIXSPL_LINEA_MASK (1<<2)
919#define M98090_MIXSPL_LINEA_SHIFT 2
920#define M98090_MIXSPL_LINEA_WIDTH 1
921#define M98090_MIXSPL_DACR_MASK (1<<1)
922#define M98090_MIXSPL_DACR_SHIFT 1
923#define M98090_MIXSPL_DACR_WIDTH 1
924#define M98090_MIXSPL_DACL_MASK (1<<0)
925#define M98090_MIXSPL_DACL_SHIFT 0
926#define M98090_MIXSPL_DACL_WIDTH 1
927#define M98090_MIXSPL_MASK (63<<0)
928#define M98090_MIXSPL_SHIFT 0
929#define M98090_MIXSPL_WIDTH 6
930#define M98090_MIXSPR_DACR_MASK (1<<1)
931#define M98090_MIXSPR_DACR_SHIFT 1
932#define M98090_MIXSPR_DACR_WIDTH 1
933
934
935/*
936 * M98090_REG_RIGHT_SPK_MIXER
937 */
938#define M98090_SPK_SLAVE_MASK (1<<6)
939#define M98090_SPK_SLAVE_SHIFT 6
940#define M98090_SPK_SLAVE_WIDTH 1
941#define M98090_MIXSPR_MIC2_MASK (1<<5)
942#define M98090_MIXSPR_MIC2_SHIFT 5
943#define M98090_MIXSPR_MIC2_WIDTH 1
944#define M98090_MIXSPR_MIC1_MASK (1<<4)
945#define M98090_MIXSPR_MIC1_SHIFT 4
946#define M98090_MIXSPR_MIC1_WIDTH 1
947#define M98090_MIXSPR_LINEB_MASK (1<<3)
948#define M98090_MIXSPR_LINEB_SHIFT 3
949#define M98090_MIXSPR_LINEB_WIDTH 1
950#define M98090_MIXSPR_LINEA_MASK (1<<2)
951#define M98090_MIXSPR_LINEA_SHIFT 2
952#define M98090_MIXSPR_LINEA_WIDTH 1
953#define M98090_MIXSPR_DACR_MASK (1<<1)
954#define M98090_MIXSPR_DACR_SHIFT 1
955#define M98090_MIXSPR_DACR_WIDTH 1
956#define M98090_MIXSPR_DACL_MASK (1<<0)
957#define M98090_MIXSPR_DACL_SHIFT 0
958#define M98090_MIXSPR_DACL_WIDTH 1
959#define M98090_MIXSPR_MASK (63<<0)
960#define M98090_MIXSPR_SHIFT 0
961#define M98090_MIXSPR_WIDTH 6
962
963/*
964 * M98090_REG_SPK_CONTROL
965 */
966#define M98090_MIXSPRG_MASK (3<<2)
967#define M98090_MIXSPRG_SHIFT 2
968#define M98090_MIXSPRG_WIDTH 2
969#define M98090_MIXSPRG_NUM (1<<M98090_MIXSPRG_WIDTH)
970#define M98090_MIXSPLG_MASK (3<<0)
971#define M98090_MIXSPLG_SHIFT 0
972#define M98090_MIXSPLG_WIDTH 2
973#define M98090_MIXSPLG_NUM (1<<M98090_MIXSPLG_WIDTH)
974
975/*
976 * M98090_REG_LEFT_SPK_VOLUME
977 */
978#define M98090_SPLM_MASK (1<<7)
979#define M98090_SPLM_SHIFT 7
980#define M98090_SPLM_WIDTH 1
981#define M98090_SPVOLL_MASK (63<<0)
982#define M98090_SPVOLL_SHIFT 0
983#define M98090_SPVOLL_WIDTH 6
984#define M98090_SPVOLL_NUM 40
985
986/*
987 * M98090_REG_RIGHT_SPK_VOLUME
988 */
989#define M98090_SPRM_MASK (1<<7)
990#define M98090_SPRM_SHIFT 7
991#define M98090_SPRM_WIDTH 1
992#define M98090_SPVOLR_MASK (63<<0)
993#define M98090_SPVOLR_SHIFT 0
994#define M98090_SPVOLR_WIDTH 6
995#define M98090_SPVOLR_NUM 40
996
997/*
998 * M98090_REG_DRC_TIMING
999 */
1000#define M98090_DRCEN_MASK (1<<7)
1001#define M98090_DRCEN_SHIFT 7
1002#define M98090_DRCEN_WIDTH 1
1003#define M98090_DRCEN_NUM (1<<M98090_DRCEN_WIDTH)
1004#define M98090_DRCRLS_MASK (7<<4)
1005#define M98090_DRCRLS_SHIFT 4
1006#define M98090_DRCRLS_WIDTH 3
1007#define M98090_DRCATK_MASK (7<<0)
1008#define M98090_DRCATK_SHIFT 0
1009#define M98090_DRCATK_WIDTH 3
1010
1011/*
1012 * M98090_REG_DRC_COMPRESSOR
1013 */
1014#define M98090_DRCCMP_MASK (7<<5)
1015#define M98090_DRCCMP_SHIFT 5
1016#define M98090_DRCCMP_WIDTH 3
1017#define M98090_DRCTHC_MASK (31<<0)
1018#define M98090_DRCTHC_SHIFT 0
1019#define M98090_DRCTHC_WIDTH 5
1020#define M98090_DRCTHC_NUM (1<<M98090_DRCTHC_WIDTH)
1021
1022/*
1023 * M98090_REG_DRC_EXPANDER
1024 */
1025#define M98090_DRCEXP_MASK (7<<5)
1026#define M98090_DRCEXP_SHIFT 5
1027#define M98090_DRCEXP_WIDTH 3
1028#define M98090_DRCTHE_MASK (31<<0)
1029#define M98090_DRCTHE_SHIFT 0
1030#define M98090_DRCTHE_WIDTH 5
1031#define M98090_DRCTHE_NUM (1<<M98090_DRCTHE_WIDTH)
1032
1033/*
1034 * M98090_REG_DRC_GAIN
1035 */
1036#define M98090_DRCG_MASK (31<<0)
1037#define M98090_DRCG_SHIFT 0
1038#define M98090_DRCG_WIDTH 5
1039#define M98090_DRCG_NUM 13
1040
1041/*
1042 * M98090_REG_RCV_LOUTL_MIXER
1043 */
1044#define M98090_MIXRCVL_MIC2_MASK (1<<5)
1045#define M98090_MIXRCVL_MIC2_SHIFT 5
1046#define M98090_MIXRCVL_MIC2_WIDTH 1
1047#define M98090_MIXRCVL_MIC1_MASK (1<<4)
1048#define M98090_MIXRCVL_MIC1_SHIFT 4
1049#define M98090_MIXRCVL_MIC1_WIDTH 1
1050#define M98090_MIXRCVL_LINEB_MASK (1<<3)
1051#define M98090_MIXRCVL_LINEB_SHIFT 3
1052#define M98090_MIXRCVL_LINEB_WIDTH 1
1053#define M98090_MIXRCVL_LINEA_MASK (1<<2)
1054#define M98090_MIXRCVL_LINEA_SHIFT 2
1055#define M98090_MIXRCVL_LINEA_WIDTH 1
1056#define M98090_MIXRCVL_DACR_MASK (1<<1)
1057#define M98090_MIXRCVL_DACR_SHIFT 1
1058#define M98090_MIXRCVL_DACR_WIDTH 1
1059#define M98090_MIXRCVL_DACL_MASK (1<<0)
1060#define M98090_MIXRCVL_DACL_SHIFT 0
1061#define M98090_MIXRCVL_DACL_WIDTH 1
1062#define M98090_MIXRCVL_MASK (63<<0)
1063#define M98090_MIXRCVL_SHIFT 0
1064#define M98090_MIXRCVL_WIDTH 6
1065
1066/*
1067 * M98090_REG_RCV_LOUTL_CONTROL
1068 */
1069#define M98090_MIXRCVLG_MASK (3<<0)
1070#define M98090_MIXRCVLG_SHIFT 0
1071#define M98090_MIXRCVLG_WIDTH 2
1072#define M98090_MIXRCVLG_NUM (1<<M98090_MIXRCVLG_WIDTH)
1073
1074/*
1075 * M98090_REG_RCV_LOUTL_VOLUME
1076 */
1077#define M98090_RCVLM_MASK (1<<7)
1078#define M98090_RCVLM_SHIFT 7
1079#define M98090_RCVLM_WIDTH 1
1080#define M98090_RCVLVOL_MASK (31<<0)
1081#define M98090_RCVLVOL_SHIFT 0
1082#define M98090_RCVLVOL_WIDTH 5
1083#define M98090_RCVLVOL_NUM (1<<M98090_RCVLVOL_WIDTH)
1084
1085/*
1086 * M98090_REG_LOUTR_MIXER
1087 */
1088#define M98090_LINMOD_MASK (1<<7)
1089#define M98090_LINMOD_SHIFT 7
1090#define M98090_LINMOD_WIDTH 1
1091#define M98090_MIXRCVR_MIC2_MASK (1<<5)
1092#define M98090_MIXRCVR_MIC2_SHIFT 5
1093#define M98090_MIXRCVR_MIC2_WIDTH 1
1094#define M98090_MIXRCVR_MIC1_MASK (1<<4)
1095#define M98090_MIXRCVR_MIC1_SHIFT 4
1096#define M98090_MIXRCVR_MIC1_WIDTH 1
1097#define M98090_MIXRCVR_LINEB_MASK (1<<3)
1098#define M98090_MIXRCVR_LINEB_SHIFT 3
1099#define M98090_MIXRCVR_LINEB_WIDTH 1
1100#define M98090_MIXRCVR_LINEA_MASK (1<<2)
1101#define M98090_MIXRCVR_LINEA_SHIFT 2
1102#define M98090_MIXRCVR_LINEA_WIDTH 1
1103#define M98090_MIXRCVR_DACR_MASK (1<<1)
1104#define M98090_MIXRCVR_DACR_SHIFT 1
1105#define M98090_MIXRCVR_DACR_WIDTH 1
1106#define M98090_MIXRCVR_DACL_MASK (1<<0)
1107#define M98090_MIXRCVR_DACL_SHIFT 0
1108#define M98090_MIXRCVR_DACL_WIDTH 1
1109#define M98090_MIXRCVR_MASK (63<<0)
1110#define M98090_MIXRCVR_SHIFT 0
1111#define M98090_MIXRCVR_WIDTH 6
1112
1113/*
1114 * M98090_REG_LOUTR_CONTROL
1115 */
1116#define M98090_MIXRCVRG_MASK (3<<0)
1117#define M98090_MIXRCVRG_SHIFT 0
1118#define M98090_MIXRCVRG_WIDTH 2
1119#define M98090_MIXRCVRG_NUM (1<<M98090_MIXRCVRG_WIDTH)
1120
1121/*
1122 * M98090_REG_LOUTR_VOLUME
1123 */
1124#define M98090_RCVRM_MASK (1<<7)
1125#define M98090_RCVRM_SHIFT 7
1126#define M98090_RCVRM_WIDTH 1
1127#define M98090_RCVRVOL_MASK (31<<0)
1128#define M98090_RCVRVOL_SHIFT 0
1129#define M98090_RCVRVOL_WIDTH 5
1130#define M98090_RCVRVOL_NUM (1<<M98090_RCVRVOL_WIDTH)
1131
1132/*
1133 * M98090_REG_JACK_DETECT
1134 */
1135#define M98090_JDETEN_MASK (1<<7)
1136#define M98090_JDETEN_SHIFT 7
1137#define M98090_JDETEN_WIDTH 1
1138#define M98090_JDWK_MASK (1<<6)
1139#define M98090_JDWK_SHIFT 6
1140#define M98090_JDWK_WIDTH 1
1141#define M98090_JDEB_MASK (3<<0)
1142#define M98090_JDEB_SHIFT 0
1143#define M98090_JDEB_WIDTH 2
1144#define M98090_JDEB_25MS (0<<0)
1145#define M98090_JDEB_50MS (1<<0)
1146#define M98090_JDEB_100MS (2<<0)
1147#define M98090_JDEB_200MS (3<<0)
1148
1149/*
1150 * M98090_REG_INPUT_ENABLE
1151 */
1152#define M98090_MBEN_MASK (1<<4)
1153#define M98090_MBEN_SHIFT 4
1154#define M98090_MBEN_WIDTH 1
1155#define M98090_LINEAEN_MASK (1<<3)
1156#define M98090_LINEAEN_SHIFT 3
1157#define M98090_LINEAEN_WIDTH 1
1158#define M98090_LINEBEN_MASK (1<<2)
1159#define M98090_LINEBEN_SHIFT 2
1160#define M98090_LINEBEN_WIDTH 1
1161#define M98090_ADREN_MASK (1<<1)
1162#define M98090_ADREN_SHIFT 1
1163#define M98090_ADREN_WIDTH 1
1164#define M98090_ADLEN_MASK (1<<0)
1165#define M98090_ADLEN_SHIFT 0
1166#define M98090_ADLEN_WIDTH 1
1167
1168/*
1169 * M98090_REG_OUTPUT_ENABLE
1170 */
1171#define M98090_HPREN_MASK (1<<7)
1172#define M98090_HPREN_SHIFT 7
1173#define M98090_HPREN_WIDTH 1
1174#define M98090_HPLEN_MASK (1<<6)
1175#define M98090_HPLEN_SHIFT 6
1176#define M98090_HPLEN_WIDTH 1
1177#define M98090_SPREN_MASK (1<<5)
1178#define M98090_SPREN_SHIFT 5
1179#define M98090_SPREN_WIDTH 1
1180#define M98090_SPLEN_MASK (1<<4)
1181#define M98090_SPLEN_SHIFT 4
1182#define M98090_SPLEN_WIDTH 1
1183#define M98090_RCVLEN_MASK (1<<3)
1184#define M98090_RCVLEN_SHIFT 3
1185#define M98090_RCVLEN_WIDTH 1
1186#define M98090_RCVREN_MASK (1<<2)
1187#define M98090_RCVREN_SHIFT 2
1188#define M98090_RCVREN_WIDTH 1
1189#define M98090_DAREN_MASK (1<<1)
1190#define M98090_DAREN_SHIFT 1
1191#define M98090_DAREN_WIDTH 1
1192#define M98090_DALEN_MASK (1<<0)
1193#define M98090_DALEN_SHIFT 0
1194#define M98090_DALEN_WIDTH 1
1195
1196/*
1197 * M98090_REG_LEVEL_CONTROL
1198 */
1199#define M98090_ZDENN_MASK (1<<2)
1200#define M98090_ZDENN_SHIFT 2
1201#define M98090_ZDENN_WIDTH 1
1202#define M98090_ZDENN_NUM (1<<M98090_ZDENN_WIDTH)
1203#define M98090_VS2ENN_MASK (1<<1)
1204#define M98090_VS2ENN_SHIFT 1
1205#define M98090_VS2ENN_WIDTH 1
1206#define M98090_VS2ENN_NUM (1<<M98090_VS2ENN_WIDTH)
1207#define M98090_VSENN_MASK (1<<0)
1208#define M98090_VSENN_SHIFT 0
1209#define M98090_VSENN_WIDTH 1
1210#define M98090_VSENN_NUM (1<<M98090_VSENN_WIDTH)
1211
1212/*
1213 * M98090_REG_DSP_FILTER_ENABLE
1214 */
1215#define M98090_DMIC34BQEN_MASK (1<<4)
1216#define M98090_DMIC34BQEN_SHIFT 4
1217#define M98090_DMIC34BQEN_WIDTH 1
1218#define M98090_DMIC34BQEN_NUM (1<<M98090_DMIC34BQEN_WIDTH)
1219#define M98090_ADCBQEN_MASK (1<<3)
1220#define M98090_ADCBQEN_SHIFT 3
1221#define M98090_ADCBQEN_WIDTH 1
1222#define M98090_ADCBQEN_NUM (1<<M98090_ADCBQEN_WIDTH)
1223#define M98090_EQ3BANDEN_MASK (1<<2)
1224#define M98090_EQ3BANDEN_SHIFT 2
1225#define M98090_EQ3BANDEN_WIDTH 1
1226#define M98090_EQ3BANDEN_NUM (1<<M98090_EQ3BANDEN_WIDTH)
1227#define M98090_EQ5BANDEN_MASK (1<<1)
1228#define M98090_EQ5BANDEN_SHIFT 1
1229#define M98090_EQ5BANDEN_WIDTH 1
1230#define M98090_EQ5BANDEN_NUM (1<<M98090_EQ5BANDEN_WIDTH)
1231#define M98090_EQ7BANDEN_MASK (1<<0)
1232#define M98090_EQ7BANDEN_SHIFT 0
1233#define M98090_EQ7BANDEN_WIDTH 1
1234#define M98090_EQ7BANDEN_NUM (1<<M98090_EQ7BANDEN_WIDTH)
1235
1236/*
1237 * M98090_REG_BIAS_CONTROL
1238 */
1239#define M98090_VCM_MODE_MASK (1<<0)
1240#define M98090_VCM_MODE_SHIFT 0
1241#define M98090_VCM_MODE_WIDTH 1
1242#define M98090_VCM_MODE_NUM (1<<M98090_VCM_MODE_WIDTH)
1243
1244/*
1245 * M98090_REG_DAC_CONTROL
1246 */
1247#define M98090_PERFMODE_MASK (1<<1)
1248#define M98090_PERFMODE_SHIFT 1
1249#define M98090_PERFMODE_WIDTH 1
1250#define M98090_PERFMODE_NUM (1<<M98090_PERFMODE_WIDTH)
1251#define M98090_DACHP_MASK (1<<0)
1252#define M98090_DACHP_SHIFT 0
1253#define M98090_DACHP_WIDTH 1
1254#define M98090_DACHP_NUM (1<<M98090_DACHP_WIDTH)
1255
1256/*
1257 * M98090_REG_ADC_CONTROL
1258 */
1259#define M98090_OSR128_MASK (1<<2)
1260#define M98090_OSR128_SHIFT 2
1261#define M98090_OSR128_WIDTH 1
1262#define M98090_ADCDITHER_MASK (1<<1)
1263#define M98090_ADCDITHER_SHIFT 1
1264#define M98090_ADCDITHER_WIDTH 1
1265#define M98090_ADCDITHER_NUM (1<<M98090_ADCDITHER_WIDTH)
1266#define M98090_ADCHP_MASK (1<<0)
1267#define M98090_ADCHP_SHIFT 0
1268#define M98090_ADCHP_WIDTH 1
1269#define M98090_ADCHP_NUM (1<<M98090_ADCHP_WIDTH)
1270
1271/*
1272 * M98090_REG_DEVICE_SHUTDOWN
1273 */
1274#define M98090_SHDNN_MASK (1<<7)
1275#define M98090_SHDNN_SHIFT 7
1276#define M98090_SHDNN_WIDTH 1
1277
1278/*
1279 * M98090_REG_EQUALIZER_BASE
1280 */
1281#define M98090_B0_1_HI_MASK (255<<0)
1282#define M98090_B0_1_HI_SHIFT 0
1283#define M98090_B0_1_HI_WIDTH 8
1284#define M98090_B0_1_MID_MASK (255<<0)
1285#define M98090_B0_1_MID_SHIFT 0
1286#define M98090_B0_1_MID_WIDTH 8
1287#define M98090_B0_1_LO_MASK (255<<0)
1288#define M98090_B0_1_LO_SHIFT 0
1289#define M98090_B0_1_LO_WIDTH 8
1290#define M98090_B1_1_HI_MASK (255<<0)
1291#define M98090_B1_1_HI_SHIFT 0
1292#define M98090_B1_1_HI_WIDTH 8
1293#define M98090_B1_1_MID_MASK (255<<0)
1294#define M98090_B1_1_MID_SHIFT 0
1295#define M98090_B1_1_MID_WIDTH 8
1296#define M98090_B1_1_LO_MASK (255<<0)
1297#define M98090_B1_1_LO_SHIFT 0
1298#define M98090_B1_1_LO_WIDTH 8
1299#define M98090_B2_1_HI_MASK (255<<0)
1300#define M98090_B2_1_HI_SHIFT 0
1301#define M98090_B2_1_HI_WIDTH 8
1302#define M98090_B2_1_MID_MASK (255<<0)
1303#define M98090_B2_1_MID_SHIFT 0
1304#define M98090_B2_1_MID_WIDTH 8
1305#define M98090_B2_1_LO_MASK (255<<0)
1306#define M98090_B2_1_LO_SHIFT 0
1307#define M98090_B2_1_LO_WIDTH 8
1308#define M98090_A1_1_HI_MASK (255<<0)
1309#define M98090_A1_1_HI_SHIFT 0
1310#define M98090_A1_1_HI_WIDTH 8
1311#define M98090_A1_1_MID_MASK (255<<0)
1312#define M98090_A1_1_MID_SHIFT 0
1313#define M98090_A1_1_MID_WIDTH 8
1314#define M98090_A1_1_LO_MASK (255<<0)
1315#define M98090_A1_1_LO_SHIFT 0
1316#define M98090_A1_1_LO_WIDTH 8
1317#define M98090_A2_1_HI_MASK (255<<0)
1318#define M98090_A2_1_HI_SHIFT 0
1319#define M98090_A2_1_HI_WIDTH 8
1320#define M98090_A2_1_MID_MASK (255<<0)
1321#define M98090_A2_1_MID_SHIFT 0
1322#define M98090_A2_1_MID_WIDTH 8
1323#define M98090_A2_1_LO_MASK (255<<0)
1324#define M98090_A2_1_LO_SHIFT 0
1325#define M98090_A2_1_LO_WIDTH 8
1326
1327#define M98090_COEFS_PER_BAND 5
1328#define M98090_COEFS_BLK_SZ (M98090_COEFS_PER_BAND * 3)
1329#define M98090_COEFS_MAX_SZ (M98090_COEFS_BLK_SZ * 7)
1330
1331/*
1332 * M98090_REG_RECORD_BIQUAD_BASE
1333 */
1334#define M98090_REC_B0_HI_MASK (255<<0)
1335#define M98090_REC_B0_HI_SHIFT 0
1336#define M98090_REC_B0_HI_WIDTH 8
1337#define M98090_REC_B0_MID_MASK (255<<0)
1338#define M98090_REC_B0_MID_SHIFT 0
1339#define M98090_REC_B0_MID_WIDTH 8
1340#define M98090_REC_B0_LO_MASK (255<<0)
1341#define M98090_REC_B0_LO_SHIFT 0
1342#define M98090_REC_B0_LO_WIDTH 8
1343#define M98090_REC_B1_HI_MASK (255<<0)
1344#define M98090_REC_B1_HI_SHIFT 0
1345#define M98090_REC_B1_HI_WIDTH 8
1346#define M98090_REC_B1_MID_MASK (255<<0)
1347#define M98090_REC_B1_MID_SHIFT 0
1348#define M98090_REC_B1_MID_WIDTH 8
1349#define M98090_REC_B1_LO_MASK (255<<0)
1350#define M98090_REC_B1_LO_SHIFT 0
1351#define M98090_REC_B1_LO_WIDTH 8
1352#define M98090_REC_B2_HI_MASK (255<<0)
1353#define M98090_REC_B2_HI_SHIFT 0
1354#define M98090_REC_B2_HI_WIDTH 8
1355#define M98090_REC_B2_MID_MASK (255<<0)
1356#define M98090_REC_B2_MID_SHIFT 0
1357#define M98090_REC_B2_MID_WIDTH 8
1358#define M98090_REC_B2_LO_MASK (255<<0)
1359#define M98090_REC_B2_LO_SHIFT 0
1360#define M98090_REC_B2_LO_WIDTH 8
1361#define M98090_REC_A1_HI_MASK (255<<0)
1362#define M98090_REC_A1_HI_SHIFT 0
1363#define M98090_REC_A1_HI_WIDTH 8
1364#define M98090_REC_A1_MID_MASK (255<<0)
1365#define M98090_REC_A1_MID_SHIFT 0
1366#define M98090_REC_A1_MID_WIDTH 8
1367#define M98090_REC_A1_LO_MASK (255<<0)
1368#define M98090_REC_A1_LO_SHIFT 0
1369#define M98090_REC_A1_LO_WIDTH 8
1370#define M98090_REC_A2_HI_MASK (255<<0)
1371#define M98090_REC_A2_HI_SHIFT 0
1372#define M98090_REC_A2_HI_WIDTH 8
1373#define M98090_REC_A2_MID_MASK (255<<0)
1374#define M98090_REC_A2_MID_SHIFT 0
1375#define M98090_REC_A2_MID_WIDTH 8
1376#define M98090_REC_A2_LO_MASK (255<<0)
1377#define M98090_REC_A2_LO_SHIFT 0
1378#define M98090_REC_A2_LO_WIDTH 8
1379
1380/*
1381 * M98090_REG_DMIC3_VOLUME
1382 */
1383#define M98090_DMIC_AV3G_MASK (7<<4)
1384#define M98090_DMIC_AV3G_SHIFT 4
1385#define M98090_DMIC_AV3G_WIDTH 3
1386#define M98090_DMIC_AV3G_NUM (1<<M98090_DMIC_AV3G_WIDTH)
1387#define M98090_DMIC_AV3_MASK (15<<0)
1388#define M98090_DMIC_AV3_SHIFT 0
1389#define M98090_DMIC_AV3_WIDTH 4
1390#define M98090_DMIC_AV3_NUM (1<<M98090_DMIC_AV3_WIDTH)
1391
1392/*
1393 * M98090_REG_DMIC4_VOLUME
1394 */
1395#define M98090_DMIC_AV4G_MASK (7<<4)
1396#define M98090_DMIC_AV4G_SHIFT 4
1397#define M98090_DMIC_AV4G_WIDTH 3
1398#define M98090_DMIC_AV4G_NUM (1<<M98090_DMIC_AV4G_WIDTH)
1399#define M98090_DMIC_AV4_MASK (15<<0)
1400#define M98090_DMIC_AV4_SHIFT 0
1401#define M98090_DMIC_AV4_WIDTH 4
1402#define M98090_DMIC_AV4_NUM (1<<M98090_DMIC_AV4_WIDTH)
1403
1404/*
1405 * M98090_REG_DMIC34_BQ_PREATTEN
1406 */
1407#define M98090_AV34BQ_MASK (15<<0)
1408#define M98090_AV34BQ_SHIFT 0
1409#define M98090_AV34BQ_WIDTH 4
1410#define M98090_AV34BQ_NUM (1<<M98090_AV34BQ_WIDTH)
1411
1412/*
1413 * M98090_REG_RECORD_TDM_SLOT
1414 */
1415#define M98090_TDM_SLOTADCL_MASK (3<<6)
1416#define M98090_TDM_SLOTADCL_SHIFT 6
1417#define M98090_TDM_SLOTADCL_WIDTH 2
1418#define M98090_TDM_SLOTADCL_NUM (1<<M98090_TDM_SLOTADCL_WIDTH)
1419#define M98090_TDM_SLOTADCR_MASK (3<<4)
1420#define M98090_TDM_SLOTADCR_SHIFT 4
1421#define M98090_TDM_SLOTADCR_WIDTH 2
1422#define M98090_TDM_SLOTADCR_NUM (1<<M98090_TDM_SLOTADCR_WIDTH)
1423#define M98090_TDM_SLOTDMIC3_MASK (3<<2)
1424#define M98090_TDM_SLOTDMIC3_SHIFT 2
1425#define M98090_TDM_SLOTDMIC3_WIDTH 2
1426#define M98090_TDM_SLOTDMIC3_NUM (1<<M98090_TDM_SLOTDMIC3_WIDTH)
1427#define M98090_TDM_SLOTDMIC4_MASK (3<<0)
1428#define M98090_TDM_SLOTDMIC4_SHIFT 0
1429#define M98090_TDM_SLOTDMIC4_WIDTH 2
1430#define M98090_TDM_SLOTDMIC4_NUM (1<<M98090_TDM_SLOTDMIC4_WIDTH)
1431
1432/*
1433 * M98090_REG_SAMPLE_RATE
1434 */
1435#define M98090_DMIC34_ZEROPAD_MASK (1<<4)
1436#define M98090_DMIC34_ZEROPAD_SHIFT 4
1437#define M98090_DMIC34_ZEROPAD_WIDTH 1
1438#define M98090_DMIC34_ZEROPAD_NUM (1<<M98090_DIGMIC4_WIDTH)
1439#define M98090_DMIC34_SRDIV_MASK (7<<0)
1440#define M98090_DMIC34_SRDIV_SHIFT 0
1441#define M98090_DMIC34_SRDIV_WIDTH 3
1442
1443/*
1444 * M98090_REG_DMIC34_BIQUAD_BASE
1445 */
1446#define M98090_DMIC34_B0_HI_MASK (255<<0)
1447#define M98090_DMIC34_B0_HI_SHIFT 0
1448#define M98090_DMIC34_B0_HI_WIDTH 8
1449#define M98090_DMIC34_B0_MID_MASK (255<<0)
1450#define M98090_DMIC34_B0_MID_SHIFT 0
1451#define M98090_DMIC34_B0_MID_WIDTH 8
1452#define M98090_DMIC34_B0_LO_MASK (255<<0)
1453#define M98090_DMIC34_B0_LO_SHIFT 0
1454#define M98090_DMIC34_B0_LO_WIDTH 8
1455#define M98090_DMIC34_B1_HI_MASK (255<<0)
1456#define M98090_DMIC34_B1_HI_SHIFT 0
1457#define M98090_DMIC34_B1_HI_WIDTH 8
1458#define M98090_DMIC34_B1_MID_MASK (255<<0)
1459#define M98090_DMIC34_B1_MID_SHIFT 0
1460#define M98090_DMIC34_B1_MID_WIDTH 8
1461#define M98090_DMIC34_B1_LO_MASK (255<<0)
1462#define M98090_DMIC34_B1_LO_SHIFT 0
1463#define M98090_DMIC34_B1_LO_WIDTH 8
1464#define M98090_DMIC34_B2_HI_MASK (255<<0)
1465#define M98090_DMIC34_B2_HI_SHIFT 0
1466#define M98090_DMIC34_B2_HI_WIDTH 8
1467#define M98090_DMIC34_B2_MID_MASK (255<<0)
1468#define M98090_DMIC34_B2_MID_SHIFT 0
1469#define M98090_DMIC34_B2_MID_WIDTH 8
1470#define M98090_DMIC34_B2_LO_MASK (255<<0)
1471#define M98090_DMIC34_B2_LO_SHIFT 0
1472#define M98090_DMIC34_B2_LO_WIDTH 8
1473#define M98090_DMIC34_A1_HI_MASK (255<<0)
1474#define M98090_DMIC34_A1_HI_SHIFT 0
1475#define M98090_DMIC34_A1_HI_WIDTH 8
1476#define M98090_DMIC34_A1_MID_MASK (255<<0)
1477#define M98090_DMIC34_A1_MID_SHIFT 0
1478#define M98090_DMIC34_A1_MID_WIDTH 8
1479#define M98090_DMIC34_A1_LO_MASK (255<<0)
1480#define M98090_DMIC34_A1_LO_SHIFT 0
1481#define M98090_DMIC34_A1_LO_WIDTH 8
1482#define M98090_DMIC34_A2_HI_MASK (255<<0)
1483#define M98090_DMIC34_A2_HI_SHIFT 0
1484#define M98090_DMIC34_A2_HI_WIDTH 8
1485#define M98090_DMIC34_A2_MID_MASK (255<<0)
1486#define M98090_DMIC34_A2_MID_SHIFT 0
1487#define M98090_DMIC34_A2_MID_WIDTH 8
1488#define M98090_DMIC34_A2_LO_MASK (255<<0)
1489#define M98090_DMIC34_A2_LO_SHIFT 0
1490#define M98090_DMIC34_A2_LO_WIDTH 8
1491
1492#define M98090_JACK_STATE_NO_HEADSET 0
1493#define M98090_JACK_STATE_NO_HEADSET_2 1
1494#define M98090_JACK_STATE_HEADPHONE 2
1495#define M98090_JACK_STATE_HEADSET 3
1496
1497/*
1498 * M98090_REG_REVISION_ID
1499 */
1500#define M98090_REVID_MASK (255<<0)
1501#define M98090_REVID_SHIFT 0
1502#define M98090_REVID_WIDTH 8
1503#define M98090_REVID_NUM (1<<M98090_REVID_WIDTH)
1504
1505#define M98090_BYTE1(w) ((w >> 8) & 0xff)
1506#define M98090_BYTE0(w) (w & 0xff)
1507
1508/* Silicon revision number */
1509#define M98090_REVA 0x40
1510#define M98091_REVA 0x50
1511
1512enum max98090_type {
1513 MAX98090,
1514 MAX98091,
1515};
1516
1517struct max98090_cdata {
1518 unsigned int rate;
1519 unsigned int fmt;
1520};
1521
1522struct max98090_priv {
1523 struct regmap *regmap;
1524 struct snd_soc_codec *codec;
1525 enum max98090_type devtype;
1526 struct max98090_pdata *pdata;
1527 unsigned int sysclk;
1528 unsigned int bclk;
1529 unsigned int lrclk;
1530 struct max98090_cdata dai[1];
1531 int irq;
1532 int jack_state;
1533 struct delayed_work jack_work;
1534 struct snd_soc_jack *jack;
1535 unsigned int dai_fmt;
1536 int tdm_slots;
1537 int tdm_width;
1538 u8 lin_state;
1539 unsigned int pa1en;
1540 unsigned int pa2en;
1541 unsigned int extmic_mux;
1542 unsigned int sidetone;
1543};
1544
1545int max98090_mic_detect(struct snd_soc_codec *codec,
1546 struct snd_soc_jack *jack);
1547
1548#endif