1/*
  2 * adv7604 - Analog Devices ADV7604 video decoder driver
  3 *
  4 * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
  5 *
  6 * This program is free software; you may redistribute it and/or modify
  7 * it under the terms of the GNU General Public License as published by
  8 * the Free Software Foundation; version 2 of the License.
  9 *
 10 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 11 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 12 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 13 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 14 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 15 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 16 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 17 * SOFTWARE.
 18 *
 19 */
 20
 21#ifndef _ADV7604_
 22#define _ADV7604_
 23
 24/* Analog input muxing modes (AFE register 0x02, [2:0]) */
 25enum adv7604_ain_sel {
 26	ADV7604_AIN1_2_3_NC_SYNC_1_2 = 0,
 27	ADV7604_AIN4_5_6_NC_SYNC_2_1 = 1,
 28	ADV7604_AIN7_8_9_NC_SYNC_3_1 = 2,
 29	ADV7604_AIN10_11_12_NC_SYNC_4_1 = 3,
 30	ADV7604_AIN9_4_5_6_SYNC_2_1 = 4,
 31};
 32
 33/* Bus rotation and reordering (IO register 0x04, [7:5]) */
 34enum adv7604_op_ch_sel {
 35	ADV7604_OP_CH_SEL_GBR = 0,
 36	ADV7604_OP_CH_SEL_GRB = 1,
 37	ADV7604_OP_CH_SEL_BGR = 2,
 38	ADV7604_OP_CH_SEL_RGB = 3,
 39	ADV7604_OP_CH_SEL_BRG = 4,
 40	ADV7604_OP_CH_SEL_RBG = 5,
 41};
 42
 43/* Input Color Space (IO register 0x02, [7:4]) */
 44enum adv7604_inp_color_space {
 45	ADV7604_INP_COLOR_SPACE_LIM_RGB = 0,
 46	ADV7604_INP_COLOR_SPACE_FULL_RGB = 1,
 47	ADV7604_INP_COLOR_SPACE_LIM_YCbCr_601 = 2,
 48	ADV7604_INP_COLOR_SPACE_LIM_YCbCr_709 = 3,
 49	ADV7604_INP_COLOR_SPACE_XVYCC_601 = 4,
 50	ADV7604_INP_COLOR_SPACE_XVYCC_709 = 5,
 51	ADV7604_INP_COLOR_SPACE_FULL_YCbCr_601 = 6,
 52	ADV7604_INP_COLOR_SPACE_FULL_YCbCr_709 = 7,
 53	ADV7604_INP_COLOR_SPACE_AUTO = 0xf,
 54};
 55
 56/* Select output format (IO register 0x03, [7:0]) */
 57enum adv7604_op_format_sel {
 58	ADV7604_OP_FORMAT_SEL_SDR_ITU656_8 = 0x00,
 59	ADV7604_OP_FORMAT_SEL_SDR_ITU656_10 = 0x01,
 60	ADV7604_OP_FORMAT_SEL_SDR_ITU656_12_MODE0 = 0x02,
 61	ADV7604_OP_FORMAT_SEL_SDR_ITU656_12_MODE1 = 0x06,
 62	ADV7604_OP_FORMAT_SEL_SDR_ITU656_12_MODE2 = 0x0a,
 63	ADV7604_OP_FORMAT_SEL_DDR_422_8 = 0x20,
 64	ADV7604_OP_FORMAT_SEL_DDR_422_10 = 0x21,
 65	ADV7604_OP_FORMAT_SEL_DDR_422_12_MODE0 = 0x22,
 66	ADV7604_OP_FORMAT_SEL_DDR_422_12_MODE1 = 0x23,
 67	ADV7604_OP_FORMAT_SEL_DDR_422_12_MODE2 = 0x24,
 68	ADV7604_OP_FORMAT_SEL_SDR_444_24 = 0x40,
 69	ADV7604_OP_FORMAT_SEL_SDR_444_30 = 0x41,
 70	ADV7604_OP_FORMAT_SEL_SDR_444_36_MODE0 = 0x42,
 71	ADV7604_OP_FORMAT_SEL_DDR_444_24 = 0x60,
 72	ADV7604_OP_FORMAT_SEL_DDR_444_30 = 0x61,
 73	ADV7604_OP_FORMAT_SEL_DDR_444_36 = 0x62,
 74	ADV7604_OP_FORMAT_SEL_SDR_ITU656_16 = 0x80,
 75	ADV7604_OP_FORMAT_SEL_SDR_ITU656_20 = 0x81,
 76	ADV7604_OP_FORMAT_SEL_SDR_ITU656_24_MODE0 = 0x82,
 77	ADV7604_OP_FORMAT_SEL_SDR_ITU656_24_MODE1 = 0x86,
 78	ADV7604_OP_FORMAT_SEL_SDR_ITU656_24_MODE2 = 0x8a,
 79};
 80
 81enum adv7604_drive_strength {
 82	ADV7604_DR_STR_MEDIUM_LOW = 1,
 83	ADV7604_DR_STR_MEDIUM_HIGH = 2,
 84	ADV7604_DR_STR_HIGH = 3,
 85};
 86
 87/* Platform dependent definition */
 88struct adv7604_platform_data {
 89	/* DIS_PWRDNB: 1 if the PWRDNB pin is unused and unconnected */
 90	unsigned disable_pwrdnb:1;
 91
 92	/* DIS_CABLE_DET_RST: 1 if the 5V pins are unused and unconnected */
 93	unsigned disable_cable_det_rst:1;
 94
 95	/* Analog input muxing mode */
 96	enum adv7604_ain_sel ain_sel;
 97
 98	/* Bus rotation and reordering */
 99	enum adv7604_op_ch_sel op_ch_sel;
100
101	/* Select output format */
102	enum adv7604_op_format_sel op_format_sel;
103
104	/* IO register 0x02 */
105	unsigned alt_gamma:1;
106	unsigned op_656_range:1;
107	unsigned rgb_out:1;
108	unsigned alt_data_sat:1;
109
110	/* IO register 0x05 */
111	unsigned blank_data:1;
112	unsigned insert_av_codes:1;
113	unsigned replicate_av_codes:1;
114	unsigned invert_cbcr:1;
115
116	/* IO register 0x06 */
117	unsigned inv_vs_pol:1;
118	unsigned inv_hs_pol:1;
119
120	/* IO register 0x14 */
121	enum adv7604_drive_strength dr_str_data;
122	enum adv7604_drive_strength dr_str_clk;
123	enum adv7604_drive_strength dr_str_sync;
124
125	/* IO register 0x30 */
126	unsigned output_bus_lsb_to_msb:1;
127
128	/* Free run */
129	unsigned hdmi_free_run_mode;
130
131	/* i2c addresses: 0 == use default */
132	u8 i2c_avlink;
133	u8 i2c_cec;
134	u8 i2c_infoframe;
135	u8 i2c_esdp;
136	u8 i2c_dpp;
137	u8 i2c_afe;
138	u8 i2c_repeater;
139	u8 i2c_edid;
140	u8 i2c_hdmi;
141	u8 i2c_test;
142	u8 i2c_cp;
143	u8 i2c_vdp;
144};
145
146enum adv7604_input_port {
147	ADV7604_INPUT_HDMI_PORT_A,
148	ADV7604_INPUT_HDMI_PORT_B,
149	ADV7604_INPUT_HDMI_PORT_C,
150	ADV7604_INPUT_HDMI_PORT_D,
151	ADV7604_INPUT_VGA_RGB,
152	ADV7604_INPUT_VGA_COMP,
153};
154
155#define ADV7604_EDID_PORT_A 0
156#define ADV7604_EDID_PORT_B 1
157#define ADV7604_EDID_PORT_C 2
158#define ADV7604_EDID_PORT_D 3
159
160#define V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE	(V4L2_CID_DV_CLASS_BASE + 0x1000)
161#define V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL	(V4L2_CID_DV_CLASS_BASE + 0x1001)
162#define V4L2_CID_ADV_RX_FREE_RUN_COLOR		(V4L2_CID_DV_CLASS_BASE + 0x1002)
163
164/* notify events */
165#define ADV7604_HOTPLUG		1
166#define ADV7604_FMT_CHANGE	2
167
168#endif