1/* vi: ts=8 sw=8
  2 *
  3 * TI 3410/5052 USB Serial Driver Header
  4 *
  5 * Copyright (C) 2004 Texas Instruments
  6 *
  7 * This driver is based on the Linux io_ti driver, which is
  8 *   Copyright (C) 2000-2002 Inside Out Networks
  9 *   Copyright (C) 2001-2002 Greg Kroah-Hartman
 10 *
 11 * This program is free software; you can redistribute it and/or modify
 12 * it under the terms of the GNU General Public License as published by
 13 * the Free Software Foundation; either version 2 of the License, or
 14 * (at your option) any later version.
 15 *
 16 * For questions or problems with this driver, contact Texas Instruments
 17 * technical support, or Al Borchers <alborchers@steinerpoint.com>, or
 18 * Peter Berger <pberger@brimson.com>.
 19 */
 20
 21#ifndef _TI_3410_5052_H_
 22#define _TI_3410_5052_H_
 23
 24/* Configuration ids */
 25#define TI_BOOT_CONFIG			1
 26#define TI_ACTIVE_CONFIG		2
 27
 28/* Vendor and product ids */
 29#define TI_VENDOR_ID			0x0451
 30#define IBM_VENDOR_ID			0x04b3
 31#define TI_3410_PRODUCT_ID		0x3410
 32#define IBM_4543_PRODUCT_ID		0x4543
 33#define IBM_454B_PRODUCT_ID		0x454b
 34#define IBM_454C_PRODUCT_ID		0x454c
 35#define TI_3410_EZ430_ID		0xF430  /* TI ez430 development tool */
 36#define TI_5052_BOOT_PRODUCT_ID		0x5052	/* no EEPROM, no firmware */
 37#define TI_5152_BOOT_PRODUCT_ID		0x5152	/* no EEPROM, no firmware */
 38#define TI_5052_EEPROM_PRODUCT_ID	0x505A	/* EEPROM, no firmware */
 39#define TI_5052_FIRMWARE_PRODUCT_ID	0x505F	/* firmware is running */
 40#define FRI2_PRODUCT_ID			0x5053  /* Fish River Island II */
 41
 42/* Multi-Tech vendor and product ids */
 43#define MTS_VENDOR_ID			0x06E0
 44#define MTS_GSM_NO_FW_PRODUCT_ID	0xF108
 45#define MTS_CDMA_NO_FW_PRODUCT_ID	0xF109
 46#define MTS_CDMA_PRODUCT_ID		0xF110
 47#define MTS_GSM_PRODUCT_ID		0xF111
 48#define MTS_EDGE_PRODUCT_ID		0xF112
 49#define MTS_MT9234MU_PRODUCT_ID		0xF114
 50#define MTS_MT9234ZBA_PRODUCT_ID	0xF115
 51#define MTS_MT9234ZBAOLD_PRODUCT_ID	0x0319
 52
 53/* Abbott Diabetics vendor and product ids */
 54#define ABBOTT_VENDOR_ID		0x1a61
 55#define ABBOTT_STEREO_PLUG_ID		0x3410
 56#define ABBOTT_PRODUCT_ID		ABBOTT_STEREO_PLUG_ID
 57#define ABBOTT_STRIP_PORT_ID		0x3420
 58
 59/* Commands */
 60#define TI_GET_VERSION			0x01
 61#define TI_GET_PORT_STATUS		0x02
 62#define TI_GET_PORT_DEV_INFO		0x03
 63#define TI_GET_CONFIG			0x04
 64#define TI_SET_CONFIG			0x05
 65#define TI_OPEN_PORT			0x06
 66#define TI_CLOSE_PORT			0x07
 67#define TI_START_PORT			0x08
 68#define TI_STOP_PORT			0x09
 69#define TI_TEST_PORT			0x0A
 70#define TI_PURGE_PORT			0x0B
 71#define TI_RESET_EXT_DEVICE		0x0C
 72#define TI_WRITE_DATA			0x80
 73#define TI_READ_DATA			0x81
 74#define TI_REQ_TYPE_CLASS		0x82
 75
 76/* Module identifiers */
 77#define TI_I2C_PORT			0x01
 78#define TI_IEEE1284_PORT		0x02
 79#define TI_UART1_PORT			0x03
 80#define TI_UART2_PORT			0x04
 81#define TI_RAM_PORT			0x05
 82
 83/* Modem status */
 84#define TI_MSR_DELTA_CTS		0x01
 85#define TI_MSR_DELTA_DSR		0x02
 86#define TI_MSR_DELTA_RI			0x04
 87#define TI_MSR_DELTA_CD			0x08
 88#define TI_MSR_CTS			0x10
 89#define TI_MSR_DSR			0x20
 90#define TI_MSR_RI			0x40
 91#define TI_MSR_CD			0x80
 92#define TI_MSR_DELTA_MASK		0x0F
 93#define TI_MSR_MASK			0xF0
 94
 95/* Line status */
 96#define TI_LSR_OVERRUN_ERROR		0x01
 97#define TI_LSR_PARITY_ERROR		0x02
 98#define TI_LSR_FRAMING_ERROR		0x04
 99#define TI_LSR_BREAK			0x08
100#define TI_LSR_ERROR			0x0F
101#define TI_LSR_RX_FULL			0x10
102#define TI_LSR_TX_EMPTY			0x20
103
104/* Line control */
105#define TI_LCR_BREAK			0x40
106
107/* Modem control */
108#define TI_MCR_LOOP			0x04
109#define TI_MCR_DTR			0x10
110#define TI_MCR_RTS			0x20
111
112/* Mask settings */
113#define TI_UART_ENABLE_RTS_IN		0x0001
114#define TI_UART_DISABLE_RTS		0x0002
115#define TI_UART_ENABLE_PARITY_CHECKING	0x0008
116#define TI_UART_ENABLE_DSR_OUT		0x0010
117#define TI_UART_ENABLE_CTS_OUT		0x0020
118#define TI_UART_ENABLE_X_OUT		0x0040
119#define TI_UART_ENABLE_XA_OUT		0x0080
120#define TI_UART_ENABLE_X_IN		0x0100
121#define TI_UART_ENABLE_DTR_IN		0x0800
122#define TI_UART_DISABLE_DTR		0x1000
123#define TI_UART_ENABLE_MS_INTS		0x2000
124#define TI_UART_ENABLE_AUTO_START_DMA	0x4000
125
126/* Parity */
127#define TI_UART_NO_PARITY		0x00
128#define TI_UART_ODD_PARITY		0x01
129#define TI_UART_EVEN_PARITY		0x02
130#define TI_UART_MARK_PARITY		0x03
131#define TI_UART_SPACE_PARITY		0x04
132
133/* Stop bits */
134#define TI_UART_1_STOP_BITS		0x00
135#define TI_UART_1_5_STOP_BITS		0x01
136#define TI_UART_2_STOP_BITS		0x02
137
138/* Bits per character */
139#define TI_UART_5_DATA_BITS		0x00
140#define TI_UART_6_DATA_BITS		0x01
141#define TI_UART_7_DATA_BITS		0x02
142#define TI_UART_8_DATA_BITS		0x03
143
144/* 232/485 modes */
145#define TI_UART_232			0x00
146#define TI_UART_485_RECEIVER_DISABLED	0x01
147#define TI_UART_485_RECEIVER_ENABLED	0x02
148
149/* Pipe transfer mode and timeout */
150#define TI_PIPE_MODE_CONTINOUS		0x01
151#define TI_PIPE_MODE_MASK		0x03
152#define TI_PIPE_TIMEOUT_MASK		0x7C
153#define TI_PIPE_TIMEOUT_ENABLE		0x80
154
155/* Config struct */
156struct ti_uart_config {
157	__u16	wBaudRate;
158	__u16	wFlags;
159	__u8	bDataBits;
160	__u8	bParity;
161	__u8	bStopBits;
162	char	cXon;
163	char	cXoff;
164	__u8	bUartMode;
165} __attribute__((packed));
166
167/* Get port status */
168struct ti_port_status {
169	__u8	bCmdCode;
170	__u8	bModuleId;
171	__u8	bErrorCode;
172	__u8	bMSR;
173	__u8	bLSR;
174} __attribute__((packed));
175
176/* Purge modes */
177#define TI_PURGE_OUTPUT			0x00
178#define TI_PURGE_INPUT			0x80
179
180/* Read/Write data */
181#define TI_RW_DATA_ADDR_SFR		0x10
182#define TI_RW_DATA_ADDR_IDATA		0x20
183#define TI_RW_DATA_ADDR_XDATA		0x30
184#define TI_RW_DATA_ADDR_CODE		0x40
185#define TI_RW_DATA_ADDR_GPIO		0x50
186#define TI_RW_DATA_ADDR_I2C		0x60
187#define TI_RW_DATA_ADDR_FLASH		0x70
188#define TI_RW_DATA_ADDR_DSP		0x80
189
190#define TI_RW_DATA_UNSPECIFIED		0x00
191#define TI_RW_DATA_BYTE			0x01
192#define TI_RW_DATA_WORD			0x02
193#define TI_RW_DATA_DOUBLE_WORD		0x04
194
195struct ti_write_data_bytes {
196	__u8	bAddrType;
197	__u8	bDataType;
198	__u8	bDataCounter;
199	__be16	wBaseAddrHi;
200	__be16	wBaseAddrLo;
201	__u8	bData[0];
202} __attribute__((packed));
203
204struct ti_read_data_request {
205	__u8	bAddrType;
206	__u8	bDataType;
207	__u8	bDataCounter;
208	__be16	wBaseAddrHi;
209	__be16	wBaseAddrLo;
210} __attribute__((packed));
211
212struct ti_read_data_bytes {
213	__u8	bCmdCode;
214	__u8	bModuleId;
215	__u8	bErrorCode;
216	__u8	bData[0];
217} __attribute__((packed));
218
219/* Interrupt struct */
220struct ti_interrupt {
221	__u8	bICode;
222	__u8	bIInfo;
223} __attribute__((packed));
224
225/* Interrupt codes */
226#define TI_GET_PORT_FROM_CODE(c)	(((c) >> 4) - 3)
227#define TI_GET_FUNC_FROM_CODE(c)	((c) & 0x0f)
228#define TI_CODE_HARDWARE_ERROR		0xFF
229#define TI_CODE_DATA_ERROR		0x03
230#define TI_CODE_MODEM_STATUS		0x04
231
232/* Download firmware max packet size */
233#define TI_DOWNLOAD_MAX_PACKET_SIZE	64
234
235/* Firmware image header */
236struct ti_firmware_header {
237	__le16	wLength;
238	__u8	bCheckSum;
239} __attribute__((packed));
240
241/* UART addresses */
242#define TI_UART1_BASE_ADDR		0xFFA0	/* UART 1 base address */
243#define TI_UART2_BASE_ADDR		0xFFB0	/* UART 2 base address */
244#define TI_UART_OFFSET_LCR		0x0002	/* UART MCR register offset */
245#define TI_UART_OFFSET_MCR		0x0004	/* UART MCR register offset */
246
247#endif /* _TI_3410_5052_H_ */