1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Rockchip Generic Register Files setup
  4 *
  5 * Copyright (c) 2016 Heiko Stuebner <heiko@sntech.de>
  6 */
  7
  8#include <linux/err.h>
  9#include <linux/mfd/syscon.h>
 10#include <linux/of.h>
 11#include <linux/platform_device.h>
 12#include <linux/regmap.h>
 13
 14#define HIWORD_UPDATE(val, mask, shift) \
 15		((val) << (shift) | (mask) << ((shift) + 16))
 16
 17struct rockchip_grf_value {
 18	const char *desc;
 19	u32 reg;
 20	u32 val;
 21};
 22
 23struct rockchip_grf_info {
 24	const struct rockchip_grf_value *values;
 25	int num_values;
 26};
 27
 28#define RK3036_GRF_SOC_CON0		0x140
 29
 30static const struct rockchip_grf_value rk3036_defaults[] __initconst = {
 31	/*
 32	 * Disable auto jtag/sdmmc switching that causes issues with the
 33	 * clock-framework and the mmc controllers making them unreliable.
 34	 */
 35	{ "jtag switching", RK3036_GRF_SOC_CON0, HIWORD_UPDATE(0, 1, 11) },
 36};
 37
 38static const struct rockchip_grf_info rk3036_grf __initconst = {
 39	.values = rk3036_defaults,
 40	.num_values = ARRAY_SIZE(rk3036_defaults),
 41};
 42
 43#define RK3128_GRF_SOC_CON0		0x140
 44#define RK3128_GRF_SOC_CON1		0x144
 45
 46static const struct rockchip_grf_value rk3128_defaults[] __initconst = {
 47	{ "jtag switching", RK3128_GRF_SOC_CON0, HIWORD_UPDATE(0, 1, 8) },
 48	{ "vpu main clock", RK3128_GRF_SOC_CON1, HIWORD_UPDATE(0, 1, 10) },
 49};
 50
 51static const struct rockchip_grf_info rk3128_grf __initconst = {
 52	.values = rk3128_defaults,
 53	.num_values = ARRAY_SIZE(rk3128_defaults),
 54};
 55
 56#define RK3228_GRF_SOC_CON6		0x418
 57
 58static const struct rockchip_grf_value rk3228_defaults[] __initconst = {
 59	{ "jtag switching", RK3228_GRF_SOC_CON6, HIWORD_UPDATE(0, 1, 8) },
 60};
 61
 62static const struct rockchip_grf_info rk3228_grf __initconst = {
 63	.values = rk3228_defaults,
 64	.num_values = ARRAY_SIZE(rk3228_defaults),
 65};
 66
 67#define RK3288_GRF_SOC_CON0		0x244
 68#define RK3288_GRF_SOC_CON2		0x24c
 69
 70static const struct rockchip_grf_value rk3288_defaults[] __initconst = {
 71	{ "jtag switching", RK3288_GRF_SOC_CON0, HIWORD_UPDATE(0, 1, 12) },
 72	{ "pwm select", RK3288_GRF_SOC_CON2, HIWORD_UPDATE(1, 1, 0) },
 73};
 74
 75static const struct rockchip_grf_info rk3288_grf __initconst = {
 76	.values = rk3288_defaults,
 77	.num_values = ARRAY_SIZE(rk3288_defaults),
 78};
 79
 80#define RK3328_GRF_SOC_CON4		0x410
 81
 82static const struct rockchip_grf_value rk3328_defaults[] __initconst = {
 83	{ "jtag switching", RK3328_GRF_SOC_CON4, HIWORD_UPDATE(0, 1, 12) },
 84};
 85
 86static const struct rockchip_grf_info rk3328_grf __initconst = {
 87	.values = rk3328_defaults,
 88	.num_values = ARRAY_SIZE(rk3328_defaults),
 89};
 90
 91#define RK3368_GRF_SOC_CON15		0x43c
 92
 93static const struct rockchip_grf_value rk3368_defaults[] __initconst = {
 94	{ "jtag switching", RK3368_GRF_SOC_CON15, HIWORD_UPDATE(0, 1, 13) },
 95};
 96
 97static const struct rockchip_grf_info rk3368_grf __initconst = {
 98	.values = rk3368_defaults,
 99	.num_values = ARRAY_SIZE(rk3368_defaults),
100};
101
102#define RK3399_GRF_SOC_CON7		0xe21c
103
104static const struct rockchip_grf_value rk3399_defaults[] __initconst = {
105	{ "jtag switching", RK3399_GRF_SOC_CON7, HIWORD_UPDATE(0, 1, 12) },
106};
107
108static const struct rockchip_grf_info rk3399_grf __initconst = {
109	.values = rk3399_defaults,
110	.num_values = ARRAY_SIZE(rk3399_defaults),
111};
112
113#define RK3566_GRF_USB3OTG0_CON1	0x0104
114
115static const struct rockchip_grf_value rk3566_defaults[] __initconst = {
116	{ "usb3otg port switch", RK3566_GRF_USB3OTG0_CON1, HIWORD_UPDATE(0, 1, 12) },
117	{ "usb3otg clock switch", RK3566_GRF_USB3OTG0_CON1, HIWORD_UPDATE(1, 1, 7) },
118	{ "usb3otg disable usb3", RK3566_GRF_USB3OTG0_CON1, HIWORD_UPDATE(1, 1, 0) },
119};
120
121static const struct rockchip_grf_info rk3566_pipegrf __initconst = {
122	.values = rk3566_defaults,
123	.num_values = ARRAY_SIZE(rk3566_defaults),
124};
125
126#define RK3576_SYSGRF_SOC_CON1		0x0004
127
128static const struct rockchip_grf_value rk3576_defaults_sys_grf[] __initconst = {
129	{ "i3c0 weakpull", RK3576_SYSGRF_SOC_CON1, HIWORD_UPDATE(3, 3, 6) },
130	{ "i3c1 weakpull", RK3576_SYSGRF_SOC_CON1, HIWORD_UPDATE(3, 3, 8) },
131};
132
133static const struct rockchip_grf_info rk3576_sysgrf __initconst = {
134	.values = rk3576_defaults_sys_grf,
135	.num_values = ARRAY_SIZE(rk3576_defaults_sys_grf),
136};
137
138#define RK3576_IOCGRF_MISC_CON		0x04F0
139
140static const struct rockchip_grf_value rk3576_defaults_ioc_grf[] __initconst = {
141	{ "jtag switching", RK3576_IOCGRF_MISC_CON, HIWORD_UPDATE(0, 1, 1) },
142};
143
144static const struct rockchip_grf_info rk3576_iocgrf __initconst = {
145	.values = rk3576_defaults_ioc_grf,
146	.num_values = ARRAY_SIZE(rk3576_defaults_ioc_grf),
147};
148
149#define RK3588_GRF_SOC_CON6		0x0318
150
151static const struct rockchip_grf_value rk3588_defaults[] __initconst = {
152	{ "jtag switching", RK3588_GRF_SOC_CON6, HIWORD_UPDATE(0, 1, 14) },
153};
154
155static const struct rockchip_grf_info rk3588_sysgrf __initconst = {
156	.values = rk3588_defaults,
157	.num_values = ARRAY_SIZE(rk3588_defaults),
158};
159
160static const struct of_device_id rockchip_grf_dt_match[] __initconst = {
161	{
162		.compatible = "rockchip,rk3036-grf",
163		.data = (void *)&rk3036_grf,
164	}, {
165		.compatible = "rockchip,rk3128-grf",
166		.data = (void *)&rk3128_grf,
167	}, {
168		.compatible = "rockchip,rk3228-grf",
169		.data = (void *)&rk3228_grf,
170	}, {
171		.compatible = "rockchip,rk3288-grf",
172		.data = (void *)&rk3288_grf,
173	}, {
174		.compatible = "rockchip,rk3328-grf",
175		.data = (void *)&rk3328_grf,
176	}, {
177		.compatible = "rockchip,rk3368-grf",
178		.data = (void *)&rk3368_grf,
179	}, {
180		.compatible = "rockchip,rk3399-grf",
181		.data = (void *)&rk3399_grf,
182	}, {
183		.compatible = "rockchip,rk3566-pipe-grf",
184		.data = (void *)&rk3566_pipegrf,
185	}, {
186		.compatible = "rockchip,rk3576-sys-grf",
187		.data = (void *)&rk3576_sysgrf,
188	}, {
189		.compatible = "rockchip,rk3576-ioc-grf",
190		.data = (void *)&rk3576_iocgrf,
191	}, {
192		.compatible = "rockchip,rk3588-sys-grf",
193		.data = (void *)&rk3588_sysgrf,
194	},
195	{ /* sentinel */ },
196};
197
198static int __init rockchip_grf_init(void)
199{
200	const struct rockchip_grf_info *grf_info;
201	const struct of_device_id *match;
202	struct device_node *np;
203	struct regmap *grf;
204	int ret, i;
205
206	np = of_find_matching_node_and_match(NULL, rockchip_grf_dt_match,
207					     &match);
208	if (!np)
209		return -ENODEV;
210	if (!match || !match->data) {
211		pr_err("%s: missing grf data\n", __func__);
212		of_node_put(np);
213		return -EINVAL;
214	}
215
216	grf_info = match->data;
217
218	grf = syscon_node_to_regmap(np);
219	of_node_put(np);
220	if (IS_ERR(grf)) {
221		pr_err("%s: could not get grf syscon\n", __func__);
222		return PTR_ERR(grf);
223	}
224
225	for (i = 0; i < grf_info->num_values; i++) {
226		const struct rockchip_grf_value *val = &grf_info->values[i];
227
228		pr_debug("%s: adjusting %s in %#6x to %#10x\n", __func__,
229			val->desc, val->reg, val->val);
230		ret = regmap_write(grf, val->reg, val->val);
231		if (ret < 0)
232			pr_err("%s: write to %#6x failed with %d\n",
233			       __func__, val->reg, ret);
234	}
235
236	return 0;
237}
238postcore_initcall(rockchip_grf_init);