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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Driver for the Intel SCU IPC mechanism
4 *
5 * (C) Copyright 2008-2010,2015 Intel Corporation
6 * Author: Sreedhara DS (sreedhara.ds@intel.com)
7 *
8 * SCU running in ARC processor communicates with other entity running in IA
9 * core through IPC mechanism which in turn messaging between IA core ad SCU.
10 * SCU has two IPC mechanism IPC-1 and IPC-2. IPC-1 is used between IA32 and
11 * SCU where IPC-2 is used between P-Unit and SCU. This driver delas with
12 * IPC-1 Driver provides an API for power control unit registers (e.g. MSIC)
13 * along with other APIs.
14 */
15
16#include <linux/cleanup.h>
17#include <linux/delay.h>
18#include <linux/device.h>
19#include <linux/errno.h>
20#include <linux/init.h>
21#include <linux/interrupt.h>
22#include <linux/io.h>
23#include <linux/iopoll.h>
24#include <linux/module.h>
25#include <linux/slab.h>
26
27#include <linux/platform_data/x86/intel_scu_ipc.h>
28
29/* IPC defines the following message types */
30#define IPCMSG_PCNTRL 0xff /* Power controller unit read/write */
31
32/* Command id associated with message IPCMSG_PCNTRL */
33#define IPC_CMD_PCNTRL_W 0 /* Register write */
34#define IPC_CMD_PCNTRL_R 1 /* Register read */
35#define IPC_CMD_PCNTRL_M 2 /* Register read-modify-write */
36
37/*
38 * IPC register summary
39 *
40 * IPC register blocks are memory mapped at fixed address of PCI BAR 0.
41 * To read or write information to the SCU, driver writes to IPC-1 memory
42 * mapped registers. The following is the IPC mechanism
43 *
44 * 1. IA core cDMI interface claims this transaction and converts it to a
45 * Transaction Layer Packet (TLP) message which is sent across the cDMI.
46 *
47 * 2. South Complex cDMI block receives this message and writes it to
48 * the IPC-1 register block, causing an interrupt to the SCU
49 *
50 * 3. SCU firmware decodes this interrupt and IPC message and the appropriate
51 * message handler is called within firmware.
52 */
53
54#define IPC_WWBUF_SIZE 20 /* IPC Write buffer Size */
55#define IPC_RWBUF_SIZE 20 /* IPC Read buffer Size */
56#define IPC_IOC 0x100 /* IPC command register IOC bit */
57
58struct intel_scu_ipc_dev {
59 struct device dev;
60 struct module *owner;
61 void __iomem *ipc_base;
62 struct completion cmd_complete;
63
64 struct intel_scu_ipc_data data;
65};
66
67#define IPC_STATUS 0x04
68#define IPC_STATUS_IRQ BIT(2)
69#define IPC_STATUS_ERR BIT(1)
70#define IPC_STATUS_BUSY BIT(0)
71
72/*
73 * IPC Write/Read Buffers:
74 * 16 byte buffer for sending and receiving data to and from SCU.
75 */
76#define IPC_WRITE_BUFFER 0x80
77#define IPC_READ_BUFFER 0x90
78
79/* Timeout in jiffies */
80#define IPC_TIMEOUT (10 * HZ)
81
82static struct intel_scu_ipc_dev *ipcdev; /* Only one for now */
83static DEFINE_MUTEX(ipclock); /* lock used to prevent multiple call to SCU */
84
85static struct class intel_scu_ipc_class = {
86 .name = "intel_scu_ipc",
87};
88
89/**
90 * intel_scu_ipc_dev_get() - Get SCU IPC instance
91 *
92 * The recommended new API takes SCU IPC instance as parameter and this
93 * function can be called by driver to get the instance. This also makes
94 * sure the driver providing the IPC functionality cannot be unloaded
95 * while the caller has the instance.
96 *
97 * Call intel_scu_ipc_dev_put() to release the instance.
98 *
99 * Returns %NULL if SCU IPC is not currently available.
100 */
101struct intel_scu_ipc_dev *intel_scu_ipc_dev_get(void)
102{
103 guard(mutex)(&ipclock);
104
105 if (ipcdev) {
106 get_device(&ipcdev->dev);
107 /*
108 * Prevent the IPC provider from being unloaded while it
109 * is being used.
110 */
111 if (try_module_get(ipcdev->owner))
112 return ipcdev;
113
114 put_device(&ipcdev->dev);
115 }
116
117 return NULL;
118}
119EXPORT_SYMBOL_GPL(intel_scu_ipc_dev_get);
120
121/**
122 * intel_scu_ipc_dev_put() - Put SCU IPC instance
123 * @scu: SCU IPC instance
124 *
125 * This function releases the SCU IPC instance retrieved from
126 * intel_scu_ipc_dev_get() and allows the driver providing IPC to be
127 * unloaded.
128 */
129void intel_scu_ipc_dev_put(struct intel_scu_ipc_dev *scu)
130{
131 if (scu) {
132 module_put(scu->owner);
133 put_device(&scu->dev);
134 }
135}
136EXPORT_SYMBOL_GPL(intel_scu_ipc_dev_put);
137
138struct intel_scu_ipc_devres {
139 struct intel_scu_ipc_dev *scu;
140};
141
142static void devm_intel_scu_ipc_dev_release(struct device *dev, void *res)
143{
144 struct intel_scu_ipc_devres *dr = res;
145 struct intel_scu_ipc_dev *scu = dr->scu;
146
147 intel_scu_ipc_dev_put(scu);
148}
149
150/**
151 * devm_intel_scu_ipc_dev_get() - Allocate managed SCU IPC device
152 * @dev: Device requesting the SCU IPC device
153 *
154 * The recommended new API takes SCU IPC instance as parameter and this
155 * function can be called by driver to get the instance. This also makes
156 * sure the driver providing the IPC functionality cannot be unloaded
157 * while the caller has the instance.
158 *
159 * Returns %NULL if SCU IPC is not currently available.
160 */
161struct intel_scu_ipc_dev *devm_intel_scu_ipc_dev_get(struct device *dev)
162{
163 struct intel_scu_ipc_devres *dr;
164 struct intel_scu_ipc_dev *scu;
165
166 dr = devres_alloc(devm_intel_scu_ipc_dev_release, sizeof(*dr), GFP_KERNEL);
167 if (!dr)
168 return NULL;
169
170 scu = intel_scu_ipc_dev_get();
171 if (!scu) {
172 devres_free(dr);
173 return NULL;
174 }
175
176 dr->scu = scu;
177 devres_add(dev, dr);
178
179 return scu;
180}
181EXPORT_SYMBOL_GPL(devm_intel_scu_ipc_dev_get);
182
183/*
184 * Send ipc command
185 * Command Register (Write Only):
186 * A write to this register results in an interrupt to the SCU core processor
187 * Format:
188 * |rfu2(8) | size(8) | command id(4) | rfu1(3) | ioc(1) | command(8)|
189 */
190static inline void ipc_command(struct intel_scu_ipc_dev *scu, u32 cmd)
191{
192 reinit_completion(&scu->cmd_complete);
193 writel(cmd | IPC_IOC, scu->ipc_base);
194}
195
196/*
197 * Write ipc data
198 * IPC Write Buffer (Write Only):
199 * 16-byte buffer for sending data associated with IPC command to
200 * SCU. Size of the data is specified in the IPC_COMMAND_REG register
201 */
202static inline void ipc_data_writel(struct intel_scu_ipc_dev *scu, u32 data, u32 offset)
203{
204 writel(data, scu->ipc_base + IPC_WRITE_BUFFER + offset);
205}
206
207/*
208 * Status Register (Read Only):
209 * Driver will read this register to get the ready/busy status of the IPC
210 * block and error status of the IPC command that was just processed by SCU
211 * Format:
212 * |rfu3(8)|error code(8)|initiator id(8)|cmd id(4)|rfu1(2)|error(1)|busy(1)|
213 */
214static inline u8 ipc_read_status(struct intel_scu_ipc_dev *scu)
215{
216 return __raw_readl(scu->ipc_base + IPC_STATUS);
217}
218
219/* Read ipc u32 data */
220static inline u32 ipc_data_readl(struct intel_scu_ipc_dev *scu, u32 offset)
221{
222 return readl(scu->ipc_base + IPC_READ_BUFFER + offset);
223}
224
225/* Wait till scu status is busy */
226static inline int busy_loop(struct intel_scu_ipc_dev *scu)
227{
228 u8 status;
229 int err;
230
231 err = readx_poll_timeout(ipc_read_status, scu, status, !(status & IPC_STATUS_BUSY),
232 100, jiffies_to_usecs(IPC_TIMEOUT));
233 if (err)
234 return err;
235
236 return (status & IPC_STATUS_ERR) ? -EIO : 0;
237}
238
239/* Wait till ipc ioc interrupt is received or timeout in 10 HZ */
240static inline int ipc_wait_for_interrupt(struct intel_scu_ipc_dev *scu)
241{
242 int status;
243
244 wait_for_completion_timeout(&scu->cmd_complete, IPC_TIMEOUT);
245
246 status = ipc_read_status(scu);
247 if (status & IPC_STATUS_BUSY)
248 return -ETIMEDOUT;
249
250 if (status & IPC_STATUS_ERR)
251 return -EIO;
252
253 return 0;
254}
255
256static int intel_scu_ipc_check_status(struct intel_scu_ipc_dev *scu)
257{
258 return scu->data.irq > 0 ? ipc_wait_for_interrupt(scu) : busy_loop(scu);
259}
260
261static struct intel_scu_ipc_dev *intel_scu_ipc_get(struct intel_scu_ipc_dev *scu)
262{
263 u8 status;
264
265 if (!scu)
266 scu = ipcdev;
267 if (!scu)
268 return ERR_PTR(-ENODEV);
269
270 status = ipc_read_status(scu);
271 if (status & IPC_STATUS_BUSY) {
272 dev_dbg(&scu->dev, "device is busy\n");
273 return ERR_PTR(-EBUSY);
274 }
275
276 return scu;
277}
278
279/* Read/Write power control(PMIC in Langwell, MSIC in PenWell) registers */
280static int pwr_reg_rdwr(struct intel_scu_ipc_dev *scu, u16 *addr, u8 *data,
281 u32 count, u32 op, u32 id)
282{
283 int nc;
284 u32 offset = 0;
285 int err;
286 u8 cbuf[IPC_WWBUF_SIZE];
287 u32 *wbuf = (u32 *)&cbuf;
288
289 memset(cbuf, 0, sizeof(cbuf));
290
291 guard(mutex)(&ipclock);
292
293 scu = intel_scu_ipc_get(scu);
294 if (IS_ERR(scu))
295 return PTR_ERR(scu);
296
297 for (nc = 0; nc < count; nc++, offset += 2) {
298 cbuf[offset] = addr[nc];
299 cbuf[offset + 1] = addr[nc] >> 8;
300 }
301
302 if (id == IPC_CMD_PCNTRL_R) {
303 for (nc = 0, offset = 0; nc < count; nc++, offset += 4)
304 ipc_data_writel(scu, wbuf[nc], offset);
305 ipc_command(scu, (count * 2) << 16 | id << 12 | 0 << 8 | op);
306 } else if (id == IPC_CMD_PCNTRL_W) {
307 for (nc = 0; nc < count; nc++, offset += 1)
308 cbuf[offset] = data[nc];
309 for (nc = 0, offset = 0; nc < count; nc++, offset += 4)
310 ipc_data_writel(scu, wbuf[nc], offset);
311 ipc_command(scu, (count * 3) << 16 | id << 12 | 0 << 8 | op);
312 } else if (id == IPC_CMD_PCNTRL_M) {
313 cbuf[offset] = data[0];
314 cbuf[offset + 1] = data[1];
315 ipc_data_writel(scu, wbuf[0], 0); /* Write wbuff */
316 ipc_command(scu, 4 << 16 | id << 12 | 0 << 8 | op);
317 }
318
319 err = intel_scu_ipc_check_status(scu);
320 if (err)
321 return err;
322
323 /* Read rbuf */
324 for (nc = 0, offset = 0; nc < 4; nc++, offset += 4)
325 wbuf[nc] = ipc_data_readl(scu, offset);
326 memcpy(data, wbuf, count);
327
328 return 0;
329}
330
331/**
332 * intel_scu_ipc_dev_ioread8() - Read a byte via the SCU
333 * @scu: Optional SCU IPC instance
334 * @addr: Register on SCU
335 * @data: Return pointer for read byte
336 *
337 * Read a single register. Returns %0 on success or an error code. All
338 * locking between SCU accesses is handled for the caller.
339 *
340 * This function may sleep.
341 */
342int intel_scu_ipc_dev_ioread8(struct intel_scu_ipc_dev *scu, u16 addr, u8 *data)
343{
344 return pwr_reg_rdwr(scu, &addr, data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
345}
346EXPORT_SYMBOL(intel_scu_ipc_dev_ioread8);
347
348/**
349 * intel_scu_ipc_dev_iowrite8() - Write a byte via the SCU
350 * @scu: Optional SCU IPC instance
351 * @addr: Register on SCU
352 * @data: Byte to write
353 *
354 * Write a single register. Returns %0 on success or an error code. All
355 * locking between SCU accesses is handled for the caller.
356 *
357 * This function may sleep.
358 */
359int intel_scu_ipc_dev_iowrite8(struct intel_scu_ipc_dev *scu, u16 addr, u8 data)
360{
361 return pwr_reg_rdwr(scu, &addr, &data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
362}
363EXPORT_SYMBOL(intel_scu_ipc_dev_iowrite8);
364
365/**
366 * intel_scu_ipc_dev_readv() - Read a set of registers
367 * @scu: Optional SCU IPC instance
368 * @addr: Register list
369 * @data: Bytes to return
370 * @len: Length of array
371 *
372 * Read registers. Returns %0 on success or an error code. All locking
373 * between SCU accesses is handled for the caller.
374 *
375 * The largest array length permitted by the hardware is 5 items.
376 *
377 * This function may sleep.
378 */
379int intel_scu_ipc_dev_readv(struct intel_scu_ipc_dev *scu, u16 *addr, u8 *data,
380 size_t len)
381{
382 return pwr_reg_rdwr(scu, addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
383}
384EXPORT_SYMBOL(intel_scu_ipc_dev_readv);
385
386/**
387 * intel_scu_ipc_dev_writev() - Write a set of registers
388 * @scu: Optional SCU IPC instance
389 * @addr: Register list
390 * @data: Bytes to write
391 * @len: Length of array
392 *
393 * Write registers. Returns %0 on success or an error code. All locking
394 * between SCU accesses is handled for the caller.
395 *
396 * The largest array length permitted by the hardware is 5 items.
397 *
398 * This function may sleep.
399 */
400int intel_scu_ipc_dev_writev(struct intel_scu_ipc_dev *scu, u16 *addr, u8 *data,
401 size_t len)
402{
403 return pwr_reg_rdwr(scu, addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
404}
405EXPORT_SYMBOL(intel_scu_ipc_dev_writev);
406
407/**
408 * intel_scu_ipc_dev_update() - Update a register
409 * @scu: Optional SCU IPC instance
410 * @addr: Register address
411 * @data: Bits to update
412 * @mask: Mask of bits to update
413 *
414 * Read-modify-write power control unit register. The first data argument
415 * must be register value and second is mask value mask is a bitmap that
416 * indicates which bits to update. %0 = masked. Don't modify this bit, %1 =
417 * modify this bit. returns %0 on success or an error code.
418 *
419 * This function may sleep. Locking between SCU accesses is handled
420 * for the caller.
421 */
422int intel_scu_ipc_dev_update(struct intel_scu_ipc_dev *scu, u16 addr, u8 data,
423 u8 mask)
424{
425 u8 tmp[2] = { data, mask };
426 return pwr_reg_rdwr(scu, &addr, tmp, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_M);
427}
428EXPORT_SYMBOL(intel_scu_ipc_dev_update);
429
430/**
431 * intel_scu_ipc_dev_simple_command() - Send a simple command
432 * @scu: Optional SCU IPC instance
433 * @cmd: Command
434 * @sub: Sub type
435 *
436 * Issue a simple command to the SCU. Do not use this interface if you must
437 * then access data as any data values may be overwritten by another SCU
438 * access by the time this function returns.
439 *
440 * This function may sleep. Locking for SCU accesses is handled for the
441 * caller.
442 */
443int intel_scu_ipc_dev_simple_command(struct intel_scu_ipc_dev *scu, int cmd,
444 int sub)
445{
446 u32 cmdval;
447 int err;
448
449 guard(mutex)(&ipclock);
450
451 scu = intel_scu_ipc_get(scu);
452 if (IS_ERR(scu))
453 return PTR_ERR(scu);
454
455 cmdval = sub << 12 | cmd;
456 ipc_command(scu, cmdval);
457 err = intel_scu_ipc_check_status(scu);
458 if (err)
459 dev_err(&scu->dev, "IPC command %#x failed with %d\n", cmdval, err);
460 return err;
461}
462EXPORT_SYMBOL(intel_scu_ipc_dev_simple_command);
463
464/**
465 * intel_scu_ipc_dev_command_with_size() - Command with data
466 * @scu: Optional SCU IPC instance
467 * @cmd: Command
468 * @sub: Sub type
469 * @in: Input data
470 * @inlen: Input length in bytes
471 * @size: Input size written to the IPC command register in whatever
472 * units (dword, byte) the particular firmware requires. Normally
473 * should be the same as @inlen.
474 * @out: Output data
475 * @outlen: Output length in bytes
476 *
477 * Issue a command to the SCU which involves data transfers. Do the
478 * data copies under the lock but leave it for the caller to interpret.
479 */
480int intel_scu_ipc_dev_command_with_size(struct intel_scu_ipc_dev *scu, int cmd,
481 int sub, const void *in, size_t inlen,
482 size_t size, void *out, size_t outlen)
483{
484 size_t outbuflen = DIV_ROUND_UP(outlen, sizeof(u32));
485 size_t inbuflen = DIV_ROUND_UP(inlen, sizeof(u32));
486 u32 cmdval, inbuf[4] = {}, outbuf[4] = {};
487 int i, err;
488
489 if (inbuflen > 4 || outbuflen > 4)
490 return -EINVAL;
491
492 guard(mutex)(&ipclock);
493
494 scu = intel_scu_ipc_get(scu);
495 if (IS_ERR(scu))
496 return PTR_ERR(scu);
497
498 memcpy(inbuf, in, inlen);
499 for (i = 0; i < inbuflen; i++)
500 ipc_data_writel(scu, inbuf[i], 4 * i);
501
502 cmdval = (size << 16) | (sub << 12) | cmd;
503 ipc_command(scu, cmdval);
504 err = intel_scu_ipc_check_status(scu);
505 if (err) {
506 dev_err(&scu->dev, "IPC command %#x failed with %d\n", cmdval, err);
507 return err;
508 }
509
510 for (i = 0; i < outbuflen; i++)
511 outbuf[i] = ipc_data_readl(scu, 4 * i);
512
513 memcpy(out, outbuf, outlen);
514
515 return 0;
516}
517EXPORT_SYMBOL(intel_scu_ipc_dev_command_with_size);
518
519/*
520 * Interrupt handler gets called when ioc bit of IPC_COMMAND_REG set to 1
521 * When ioc bit is set to 1, caller api must wait for interrupt handler called
522 * which in turn unlocks the caller api. Currently this is not used
523 *
524 * This is edge triggered so we need take no action to clear anything
525 */
526static irqreturn_t ioc(int irq, void *dev_id)
527{
528 struct intel_scu_ipc_dev *scu = dev_id;
529 int status = ipc_read_status(scu);
530
531 writel(status | IPC_STATUS_IRQ, scu->ipc_base + IPC_STATUS);
532 complete(&scu->cmd_complete);
533
534 return IRQ_HANDLED;
535}
536
537static void intel_scu_ipc_release(struct device *dev)
538{
539 struct intel_scu_ipc_dev *scu = container_of(dev, struct intel_scu_ipc_dev, dev);
540 struct intel_scu_ipc_data *data = &scu->data;
541
542 if (data->irq > 0)
543 free_irq(data->irq, scu);
544 iounmap(scu->ipc_base);
545 release_mem_region(data->mem.start, resource_size(&data->mem));
546 kfree(scu);
547}
548
549/**
550 * __intel_scu_ipc_register() - Register SCU IPC device
551 * @parent: Parent device
552 * @scu_data: Data used to configure SCU IPC
553 * @owner: Module registering the SCU IPC device
554 *
555 * Call this function to register SCU IPC mechanism under @parent.
556 * Returns pointer to the new SCU IPC device or ERR_PTR() in case of
557 * failure. The caller may use the returned instance if it needs to do
558 * SCU IPC calls itself.
559 */
560struct intel_scu_ipc_dev *
561__intel_scu_ipc_register(struct device *parent,
562 const struct intel_scu_ipc_data *scu_data,
563 struct module *owner)
564{
565 int err;
566 struct intel_scu_ipc_data *data;
567 struct intel_scu_ipc_dev *scu;
568 void __iomem *ipc_base;
569
570 guard(mutex)(&ipclock);
571
572 /* We support only one IPC */
573 if (ipcdev)
574 return ERR_PTR(-EBUSY);
575
576 scu = kzalloc(sizeof(*scu), GFP_KERNEL);
577 if (!scu)
578 return ERR_PTR(-ENOMEM);
579
580 scu->owner = owner;
581 scu->dev.parent = parent;
582 scu->dev.class = &intel_scu_ipc_class;
583 scu->dev.release = intel_scu_ipc_release;
584
585 memcpy(&scu->data, scu_data, sizeof(scu->data));
586 data = &scu->data;
587
588 if (!request_mem_region(data->mem.start, resource_size(&data->mem), "intel_scu_ipc")) {
589 err = -EBUSY;
590 goto err_free;
591 }
592
593 ipc_base = ioremap(data->mem.start, resource_size(&data->mem));
594 if (!ipc_base) {
595 err = -ENOMEM;
596 goto err_release;
597 }
598
599 scu->ipc_base = ipc_base;
600 init_completion(&scu->cmd_complete);
601
602 if (data->irq > 0) {
603 err = request_irq(data->irq, ioc, 0, "intel_scu_ipc", scu);
604 if (err)
605 goto err_unmap;
606 }
607
608 /*
609 * After this point intel_scu_ipc_release() takes care of
610 * releasing the SCU IPC resources once refcount drops to zero.
611 */
612 dev_set_name(&scu->dev, "intel_scu_ipc");
613 err = device_register(&scu->dev);
614 if (err) {
615 put_device(&scu->dev);
616 return ERR_PTR(err);
617 }
618
619 /* Assign device at last */
620 ipcdev = scu;
621 return scu;
622
623err_unmap:
624 iounmap(ipc_base);
625err_release:
626 release_mem_region(data->mem.start, resource_size(&data->mem));
627err_free:
628 kfree(scu);
629 return ERR_PTR(err);
630}
631EXPORT_SYMBOL_GPL(__intel_scu_ipc_register);
632
633/**
634 * intel_scu_ipc_unregister() - Unregister SCU IPC
635 * @scu: SCU IPC handle
636 *
637 * This unregisters the SCU IPC device and releases the acquired
638 * resources once the refcount goes to zero.
639 */
640void intel_scu_ipc_unregister(struct intel_scu_ipc_dev *scu)
641{
642 guard(mutex)(&ipclock);
643
644 if (!WARN_ON(!ipcdev)) {
645 ipcdev = NULL;
646 device_unregister(&scu->dev);
647 }
648}
649EXPORT_SYMBOL_GPL(intel_scu_ipc_unregister);
650
651static void devm_intel_scu_ipc_unregister(struct device *dev, void *res)
652{
653 struct intel_scu_ipc_devres *dr = res;
654 struct intel_scu_ipc_dev *scu = dr->scu;
655
656 intel_scu_ipc_unregister(scu);
657}
658
659/**
660 * __devm_intel_scu_ipc_register() - Register managed SCU IPC device
661 * @parent: Parent device
662 * @scu_data: Data used to configure SCU IPC
663 * @owner: Module registering the SCU IPC device
664 *
665 * Call this function to register managed SCU IPC mechanism under
666 * @parent. Returns pointer to the new SCU IPC device or ERR_PTR() in
667 * case of failure. The caller may use the returned instance if it needs
668 * to do SCU IPC calls itself.
669 */
670struct intel_scu_ipc_dev *
671__devm_intel_scu_ipc_register(struct device *parent,
672 const struct intel_scu_ipc_data *scu_data,
673 struct module *owner)
674{
675 struct intel_scu_ipc_devres *dr;
676 struct intel_scu_ipc_dev *scu;
677
678 dr = devres_alloc(devm_intel_scu_ipc_unregister, sizeof(*dr), GFP_KERNEL);
679 if (!dr)
680 return NULL;
681
682 scu = __intel_scu_ipc_register(parent, scu_data, owner);
683 if (IS_ERR(scu)) {
684 devres_free(dr);
685 return scu;
686 }
687
688 dr->scu = scu;
689 devres_add(parent, dr);
690
691 return scu;
692}
693EXPORT_SYMBOL_GPL(__devm_intel_scu_ipc_register);
694
695static int __init intel_scu_ipc_init(void)
696{
697 return class_register(&intel_scu_ipc_class);
698}
699subsys_initcall(intel_scu_ipc_init);
700
701static void __exit intel_scu_ipc_exit(void)
702{
703 class_unregister(&intel_scu_ipc_class);
704}
705module_exit(intel_scu_ipc_exit);
1/*
2 * intel_scu_ipc.c: Driver for the Intel SCU IPC mechanism
3 *
4 * (C) Copyright 2008-2010 Intel Corporation
5 * Author: Sreedhara DS (sreedhara.ds@intel.com)
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2
10 * of the License.
11 *
12 * SCU running in ARC processor communicates with other entity running in IA
13 * core through IPC mechanism which in turn messaging between IA core ad SCU.
14 * SCU has two IPC mechanism IPC-1 and IPC-2. IPC-1 is used between IA32 and
15 * SCU where IPC-2 is used between P-Unit and SCU. This driver delas with
16 * IPC-1 Driver provides an API for power control unit registers (e.g. MSIC)
17 * along with other APIs.
18 */
19#include <linux/delay.h>
20#include <linux/errno.h>
21#include <linux/init.h>
22#include <linux/device.h>
23#include <linux/pm.h>
24#include <linux/pci.h>
25#include <linux/interrupt.h>
26#include <linux/sfi.h>
27#include <linux/module.h>
28#include <asm/intel-mid.h>
29#include <asm/intel_scu_ipc.h>
30
31/* IPC defines the following message types */
32#define IPCMSG_WATCHDOG_TIMER 0xF8 /* Set Kernel Watchdog Threshold */
33#define IPCMSG_BATTERY 0xEF /* Coulomb Counter Accumulator */
34#define IPCMSG_FW_UPDATE 0xFE /* Firmware update */
35#define IPCMSG_PCNTRL 0xFF /* Power controller unit read/write */
36#define IPCMSG_FW_REVISION 0xF4 /* Get firmware revision */
37
38/* Command id associated with message IPCMSG_PCNTRL */
39#define IPC_CMD_PCNTRL_W 0 /* Register write */
40#define IPC_CMD_PCNTRL_R 1 /* Register read */
41#define IPC_CMD_PCNTRL_M 2 /* Register read-modify-write */
42
43/*
44 * IPC register summary
45 *
46 * IPC register blocks are memory mapped at fixed address of 0xFF11C000
47 * To read or write information to the SCU, driver writes to IPC-1 memory
48 * mapped registers (base address 0xFF11C000). The following is the IPC
49 * mechanism
50 *
51 * 1. IA core cDMI interface claims this transaction and converts it to a
52 * Transaction Layer Packet (TLP) message which is sent across the cDMI.
53 *
54 * 2. South Complex cDMI block receives this message and writes it to
55 * the IPC-1 register block, causing an interrupt to the SCU
56 *
57 * 3. SCU firmware decodes this interrupt and IPC message and the appropriate
58 * message handler is called within firmware.
59 */
60
61#define IPC_WWBUF_SIZE 20 /* IPC Write buffer Size */
62#define IPC_RWBUF_SIZE 20 /* IPC Read buffer Size */
63#define IPC_IOC 0x100 /* IPC command register IOC bit */
64
65#define PCI_DEVICE_ID_LINCROFT 0x082a
66#define PCI_DEVICE_ID_PENWELL 0x080e
67#define PCI_DEVICE_ID_CLOVERVIEW 0x08ea
68#define PCI_DEVICE_ID_TANGIER 0x11a0
69
70/* intel scu ipc driver data*/
71struct intel_scu_ipc_pdata_t {
72 u32 ipc_base;
73 u32 i2c_base;
74 u32 ipc_len;
75 u32 i2c_len;
76 u8 irq_mode;
77};
78
79static struct intel_scu_ipc_pdata_t intel_scu_ipc_lincroft_pdata = {
80 .ipc_base = 0xff11c000,
81 .i2c_base = 0xff12b000,
82 .ipc_len = 0x100,
83 .i2c_len = 0x10,
84 .irq_mode = 0,
85};
86
87/* Penwell and Cloverview */
88static struct intel_scu_ipc_pdata_t intel_scu_ipc_penwell_pdata = {
89 .ipc_base = 0xff11c000,
90 .i2c_base = 0xff12b000,
91 .ipc_len = 0x100,
92 .i2c_len = 0x10,
93 .irq_mode = 1,
94};
95
96static struct intel_scu_ipc_pdata_t intel_scu_ipc_tangier_pdata = {
97 .ipc_base = 0xff009000,
98 .i2c_base = 0xff00d000,
99 .ipc_len = 0x100,
100 .i2c_len = 0x10,
101 .irq_mode = 0,
102};
103
104static int ipc_probe(struct pci_dev *dev, const struct pci_device_id *id);
105static void ipc_remove(struct pci_dev *pdev);
106
107struct intel_scu_ipc_dev {
108 struct pci_dev *pdev;
109 void __iomem *ipc_base;
110 void __iomem *i2c_base;
111 struct completion cmd_complete;
112 u8 irq_mode;
113};
114
115static struct intel_scu_ipc_dev ipcdev; /* Only one for now */
116
117static int platform; /* Platform type */
118
119/*
120 * IPC Read Buffer (Read Only):
121 * 16 byte buffer for receiving data from SCU, if IPC command
122 * processing results in response data
123 */
124#define IPC_READ_BUFFER 0x90
125
126#define IPC_I2C_CNTRL_ADDR 0
127#define I2C_DATA_ADDR 0x04
128
129static DEFINE_MUTEX(ipclock); /* lock used to prevent multiple call to SCU */
130
131/*
132 * Command Register (Write Only):
133 * A write to this register results in an interrupt to the SCU core processor
134 * Format:
135 * |rfu2(8) | size(8) | command id(4) | rfu1(3) | ioc(1) | command(8)|
136 */
137static inline void ipc_command(u32 cmd) /* Send ipc command */
138{
139 if (ipcdev.irq_mode) {
140 reinit_completion(&ipcdev.cmd_complete);
141 writel(cmd | IPC_IOC, ipcdev.ipc_base);
142 }
143 writel(cmd, ipcdev.ipc_base);
144}
145
146/*
147 * IPC Write Buffer (Write Only):
148 * 16-byte buffer for sending data associated with IPC command to
149 * SCU. Size of the data is specified in the IPC_COMMAND_REG register
150 */
151static inline void ipc_data_writel(u32 data, u32 offset) /* Write ipc data */
152{
153 writel(data, ipcdev.ipc_base + 0x80 + offset);
154}
155
156/*
157 * Status Register (Read Only):
158 * Driver will read this register to get the ready/busy status of the IPC
159 * block and error status of the IPC command that was just processed by SCU
160 * Format:
161 * |rfu3(8)|error code(8)|initiator id(8)|cmd id(4)|rfu1(2)|error(1)|busy(1)|
162 */
163
164static inline u8 ipc_read_status(void)
165{
166 return __raw_readl(ipcdev.ipc_base + 0x04);
167}
168
169static inline u8 ipc_data_readb(u32 offset) /* Read ipc byte data */
170{
171 return readb(ipcdev.ipc_base + IPC_READ_BUFFER + offset);
172}
173
174static inline u32 ipc_data_readl(u32 offset) /* Read ipc u32 data */
175{
176 return readl(ipcdev.ipc_base + IPC_READ_BUFFER + offset);
177}
178
179static inline int busy_loop(void) /* Wait till scu status is busy */
180{
181 u32 status = 0;
182 u32 loop_count = 0;
183
184 status = ipc_read_status();
185 while (status & 1) {
186 udelay(1); /* scu processing time is in few u secods */
187 status = ipc_read_status();
188 loop_count++;
189 /* break if scu doesn't reset busy bit after huge retry */
190 if (loop_count > 100000) {
191 dev_err(&ipcdev.pdev->dev, "IPC timed out");
192 return -ETIMEDOUT;
193 }
194 }
195 if ((status >> 1) & 1)
196 return -EIO;
197
198 return 0;
199}
200
201/* Wait till ipc ioc interrupt is received or timeout in 3 HZ */
202static inline int ipc_wait_for_interrupt(void)
203{
204 int status;
205
206 if (!wait_for_completion_timeout(&ipcdev.cmd_complete, 3 * HZ)) {
207 struct device *dev = &ipcdev.pdev->dev;
208 dev_err(dev, "IPC timed out\n");
209 return -ETIMEDOUT;
210 }
211
212 status = ipc_read_status();
213
214 if ((status >> 1) & 1)
215 return -EIO;
216
217 return 0;
218}
219
220int intel_scu_ipc_check_status(void)
221{
222 return ipcdev.irq_mode ? ipc_wait_for_interrupt() : busy_loop();
223}
224
225/* Read/Write power control(PMIC in Langwell, MSIC in PenWell) registers */
226static int pwr_reg_rdwr(u16 *addr, u8 *data, u32 count, u32 op, u32 id)
227{
228 int nc;
229 u32 offset = 0;
230 int err;
231 u8 cbuf[IPC_WWBUF_SIZE] = { };
232 u32 *wbuf = (u32 *)&cbuf;
233
234 mutex_lock(&ipclock);
235
236 memset(cbuf, 0, sizeof(cbuf));
237
238 if (ipcdev.pdev == NULL) {
239 mutex_unlock(&ipclock);
240 return -ENODEV;
241 }
242
243 for (nc = 0; nc < count; nc++, offset += 2) {
244 cbuf[offset] = addr[nc];
245 cbuf[offset + 1] = addr[nc] >> 8;
246 }
247
248 if (id == IPC_CMD_PCNTRL_R) {
249 for (nc = 0, offset = 0; nc < count; nc++, offset += 4)
250 ipc_data_writel(wbuf[nc], offset);
251 ipc_command((count*2) << 16 | id << 12 | 0 << 8 | op);
252 } else if (id == IPC_CMD_PCNTRL_W) {
253 for (nc = 0; nc < count; nc++, offset += 1)
254 cbuf[offset] = data[nc];
255 for (nc = 0, offset = 0; nc < count; nc++, offset += 4)
256 ipc_data_writel(wbuf[nc], offset);
257 ipc_command((count*3) << 16 | id << 12 | 0 << 8 | op);
258 } else if (id == IPC_CMD_PCNTRL_M) {
259 cbuf[offset] = data[0];
260 cbuf[offset + 1] = data[1];
261 ipc_data_writel(wbuf[0], 0); /* Write wbuff */
262 ipc_command(4 << 16 | id << 12 | 0 << 8 | op);
263 }
264
265 err = intel_scu_ipc_check_status();
266 if (!err && id == IPC_CMD_PCNTRL_R) { /* Read rbuf */
267 /* Workaround: values are read as 0 without memcpy_fromio */
268 memcpy_fromio(cbuf, ipcdev.ipc_base + 0x90, 16);
269 for (nc = 0; nc < count; nc++)
270 data[nc] = ipc_data_readb(nc);
271 }
272 mutex_unlock(&ipclock);
273 return err;
274}
275
276/**
277 * intel_scu_ipc_ioread8 - read a word via the SCU
278 * @addr: register on SCU
279 * @data: return pointer for read byte
280 *
281 * Read a single register. Returns 0 on success or an error code. All
282 * locking between SCU accesses is handled for the caller.
283 *
284 * This function may sleep.
285 */
286int intel_scu_ipc_ioread8(u16 addr, u8 *data)
287{
288 return pwr_reg_rdwr(&addr, data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
289}
290EXPORT_SYMBOL(intel_scu_ipc_ioread8);
291
292/**
293 * intel_scu_ipc_ioread16 - read a word via the SCU
294 * @addr: register on SCU
295 * @data: return pointer for read word
296 *
297 * Read a register pair. Returns 0 on success or an error code. All
298 * locking between SCU accesses is handled for the caller.
299 *
300 * This function may sleep.
301 */
302int intel_scu_ipc_ioread16(u16 addr, u16 *data)
303{
304 u16 x[2] = {addr, addr + 1 };
305 return pwr_reg_rdwr(x, (u8 *)data, 2, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
306}
307EXPORT_SYMBOL(intel_scu_ipc_ioread16);
308
309/**
310 * intel_scu_ipc_ioread32 - read a dword via the SCU
311 * @addr: register on SCU
312 * @data: return pointer for read dword
313 *
314 * Read four registers. Returns 0 on success or an error code. All
315 * locking between SCU accesses is handled for the caller.
316 *
317 * This function may sleep.
318 */
319int intel_scu_ipc_ioread32(u16 addr, u32 *data)
320{
321 u16 x[4] = {addr, addr + 1, addr + 2, addr + 3};
322 return pwr_reg_rdwr(x, (u8 *)data, 4, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
323}
324EXPORT_SYMBOL(intel_scu_ipc_ioread32);
325
326/**
327 * intel_scu_ipc_iowrite8 - write a byte via the SCU
328 * @addr: register on SCU
329 * @data: byte to write
330 *
331 * Write a single register. Returns 0 on success or an error code. All
332 * locking between SCU accesses is handled for the caller.
333 *
334 * This function may sleep.
335 */
336int intel_scu_ipc_iowrite8(u16 addr, u8 data)
337{
338 return pwr_reg_rdwr(&addr, &data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
339}
340EXPORT_SYMBOL(intel_scu_ipc_iowrite8);
341
342/**
343 * intel_scu_ipc_iowrite16 - write a word via the SCU
344 * @addr: register on SCU
345 * @data: word to write
346 *
347 * Write two registers. Returns 0 on success or an error code. All
348 * locking between SCU accesses is handled for the caller.
349 *
350 * This function may sleep.
351 */
352int intel_scu_ipc_iowrite16(u16 addr, u16 data)
353{
354 u16 x[2] = {addr, addr + 1 };
355 return pwr_reg_rdwr(x, (u8 *)&data, 2, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
356}
357EXPORT_SYMBOL(intel_scu_ipc_iowrite16);
358
359/**
360 * intel_scu_ipc_iowrite32 - write a dword via the SCU
361 * @addr: register on SCU
362 * @data: dword to write
363 *
364 * Write four registers. Returns 0 on success or an error code. All
365 * locking between SCU accesses is handled for the caller.
366 *
367 * This function may sleep.
368 */
369int intel_scu_ipc_iowrite32(u16 addr, u32 data)
370{
371 u16 x[4] = {addr, addr + 1, addr + 2, addr + 3};
372 return pwr_reg_rdwr(x, (u8 *)&data, 4, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
373}
374EXPORT_SYMBOL(intel_scu_ipc_iowrite32);
375
376/**
377 * intel_scu_ipc_readvv - read a set of registers
378 * @addr: register list
379 * @data: bytes to return
380 * @len: length of array
381 *
382 * Read registers. Returns 0 on success or an error code. All
383 * locking between SCU accesses is handled for the caller.
384 *
385 * The largest array length permitted by the hardware is 5 items.
386 *
387 * This function may sleep.
388 */
389int intel_scu_ipc_readv(u16 *addr, u8 *data, int len)
390{
391 return pwr_reg_rdwr(addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
392}
393EXPORT_SYMBOL(intel_scu_ipc_readv);
394
395/**
396 * intel_scu_ipc_writev - write a set of registers
397 * @addr: register list
398 * @data: bytes to write
399 * @len: length of array
400 *
401 * Write registers. Returns 0 on success or an error code. All
402 * locking between SCU accesses is handled for the caller.
403 *
404 * The largest array length permitted by the hardware is 5 items.
405 *
406 * This function may sleep.
407 *
408 */
409int intel_scu_ipc_writev(u16 *addr, u8 *data, int len)
410{
411 return pwr_reg_rdwr(addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
412}
413EXPORT_SYMBOL(intel_scu_ipc_writev);
414
415
416/**
417 * intel_scu_ipc_update_register - r/m/w a register
418 * @addr: register address
419 * @bits: bits to update
420 * @mask: mask of bits to update
421 *
422 * Read-modify-write power control unit register. The first data argument
423 * must be register value and second is mask value
424 * mask is a bitmap that indicates which bits to update.
425 * 0 = masked. Don't modify this bit, 1 = modify this bit.
426 * returns 0 on success or an error code.
427 *
428 * This function may sleep. Locking between SCU accesses is handled
429 * for the caller.
430 */
431int intel_scu_ipc_update_register(u16 addr, u8 bits, u8 mask)
432{
433 u8 data[2] = { bits, mask };
434 return pwr_reg_rdwr(&addr, data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_M);
435}
436EXPORT_SYMBOL(intel_scu_ipc_update_register);
437
438/**
439 * intel_scu_ipc_simple_command - send a simple command
440 * @cmd: command
441 * @sub: sub type
442 *
443 * Issue a simple command to the SCU. Do not use this interface if
444 * you must then access data as any data values may be overwritten
445 * by another SCU access by the time this function returns.
446 *
447 * This function may sleep. Locking for SCU accesses is handled for
448 * the caller.
449 */
450int intel_scu_ipc_simple_command(int cmd, int sub)
451{
452 int err;
453
454 mutex_lock(&ipclock);
455 if (ipcdev.pdev == NULL) {
456 mutex_unlock(&ipclock);
457 return -ENODEV;
458 }
459 ipc_command(sub << 12 | cmd);
460 err = intel_scu_ipc_check_status();
461 mutex_unlock(&ipclock);
462 return err;
463}
464EXPORT_SYMBOL(intel_scu_ipc_simple_command);
465
466/**
467 * intel_scu_ipc_command - command with data
468 * @cmd: command
469 * @sub: sub type
470 * @in: input data
471 * @inlen: input length in dwords
472 * @out: output data
473 * @outlein: output length in dwords
474 *
475 * Issue a command to the SCU which involves data transfers. Do the
476 * data copies under the lock but leave it for the caller to interpret
477 */
478
479int intel_scu_ipc_command(int cmd, int sub, u32 *in, int inlen,
480 u32 *out, int outlen)
481{
482 int i, err;
483
484 mutex_lock(&ipclock);
485 if (ipcdev.pdev == NULL) {
486 mutex_unlock(&ipclock);
487 return -ENODEV;
488 }
489
490 for (i = 0; i < inlen; i++)
491 ipc_data_writel(*in++, 4 * i);
492
493 ipc_command((inlen << 16) | (sub << 12) | cmd);
494 err = intel_scu_ipc_check_status();
495
496 if (!err) {
497 for (i = 0; i < outlen; i++)
498 *out++ = ipc_data_readl(4 * i);
499 }
500
501 mutex_unlock(&ipclock);
502 return err;
503}
504EXPORT_SYMBOL(intel_scu_ipc_command);
505
506/*I2C commands */
507#define IPC_I2C_WRITE 1 /* I2C Write command */
508#define IPC_I2C_READ 2 /* I2C Read command */
509
510/**
511 * intel_scu_ipc_i2c_cntrl - I2C read/write operations
512 * @addr: I2C address + command bits
513 * @data: data to read/write
514 *
515 * Perform an an I2C read/write operation via the SCU. All locking is
516 * handled for the caller. This function may sleep.
517 *
518 * Returns an error code or 0 on success.
519 *
520 * This has to be in the IPC driver for the locking.
521 */
522int intel_scu_ipc_i2c_cntrl(u32 addr, u32 *data)
523{
524 u32 cmd = 0;
525
526 mutex_lock(&ipclock);
527 if (ipcdev.pdev == NULL) {
528 mutex_unlock(&ipclock);
529 return -ENODEV;
530 }
531 cmd = (addr >> 24) & 0xFF;
532 if (cmd == IPC_I2C_READ) {
533 writel(addr, ipcdev.i2c_base + IPC_I2C_CNTRL_ADDR);
534 /* Write not getting updated without delay */
535 mdelay(1);
536 *data = readl(ipcdev.i2c_base + I2C_DATA_ADDR);
537 } else if (cmd == IPC_I2C_WRITE) {
538 writel(*data, ipcdev.i2c_base + I2C_DATA_ADDR);
539 mdelay(1);
540 writel(addr, ipcdev.i2c_base + IPC_I2C_CNTRL_ADDR);
541 } else {
542 dev_err(&ipcdev.pdev->dev,
543 "intel_scu_ipc: I2C INVALID_CMD = 0x%x\n", cmd);
544
545 mutex_unlock(&ipclock);
546 return -EIO;
547 }
548 mutex_unlock(&ipclock);
549 return 0;
550}
551EXPORT_SYMBOL(intel_scu_ipc_i2c_cntrl);
552
553/*
554 * Interrupt handler gets called when ioc bit of IPC_COMMAND_REG set to 1
555 * When ioc bit is set to 1, caller api must wait for interrupt handler called
556 * which in turn unlocks the caller api. Currently this is not used
557 *
558 * This is edge triggered so we need take no action to clear anything
559 */
560static irqreturn_t ioc(int irq, void *dev_id)
561{
562 if (ipcdev.irq_mode)
563 complete(&ipcdev.cmd_complete);
564
565 return IRQ_HANDLED;
566}
567
568/**
569 * ipc_probe - probe an Intel SCU IPC
570 * @dev: the PCI device matching
571 * @id: entry in the match table
572 *
573 * Enable and install an intel SCU IPC. This appears in the PCI space
574 * but uses some hard coded addresses as well.
575 */
576static int ipc_probe(struct pci_dev *dev, const struct pci_device_id *id)
577{
578 int err;
579 struct intel_scu_ipc_pdata_t *pdata;
580 resource_size_t pci_resource;
581
582 if (ipcdev.pdev) /* We support only one SCU */
583 return -EBUSY;
584
585 pdata = (struct intel_scu_ipc_pdata_t *)id->driver_data;
586
587 ipcdev.pdev = pci_dev_get(dev);
588 ipcdev.irq_mode = pdata->irq_mode;
589
590 err = pci_enable_device(dev);
591 if (err)
592 return err;
593
594 err = pci_request_regions(dev, "intel_scu_ipc");
595 if (err)
596 return err;
597
598 pci_resource = pci_resource_start(dev, 0);
599 if (!pci_resource)
600 return -ENOMEM;
601
602 init_completion(&ipcdev.cmd_complete);
603
604 if (request_irq(dev->irq, ioc, 0, "intel_scu_ipc", &ipcdev))
605 return -EBUSY;
606
607 ipcdev.ipc_base = ioremap_nocache(pdata->ipc_base, pdata->ipc_len);
608 if (!ipcdev.ipc_base)
609 return -ENOMEM;
610
611 ipcdev.i2c_base = ioremap_nocache(pdata->i2c_base, pdata->i2c_len);
612 if (!ipcdev.i2c_base) {
613 iounmap(ipcdev.ipc_base);
614 return -ENOMEM;
615 }
616
617 intel_scu_devices_create();
618
619 return 0;
620}
621
622/**
623 * ipc_remove - remove a bound IPC device
624 * @pdev: PCI device
625 *
626 * In practice the SCU is not removable but this function is also
627 * called for each device on a module unload or cleanup which is the
628 * path that will get used.
629 *
630 * Free up the mappings and release the PCI resources
631 */
632static void ipc_remove(struct pci_dev *pdev)
633{
634 free_irq(pdev->irq, &ipcdev);
635 pci_release_regions(pdev);
636 pci_dev_put(ipcdev.pdev);
637 iounmap(ipcdev.ipc_base);
638 iounmap(ipcdev.i2c_base);
639 ipcdev.pdev = NULL;
640 intel_scu_devices_destroy();
641}
642
643static DEFINE_PCI_DEVICE_TABLE(pci_ids) = {
644 {
645 PCI_VDEVICE(INTEL, PCI_DEVICE_ID_LINCROFT),
646 (kernel_ulong_t)&intel_scu_ipc_lincroft_pdata,
647 }, {
648 PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PENWELL),
649 (kernel_ulong_t)&intel_scu_ipc_penwell_pdata,
650 }, {
651 PCI_VDEVICE(INTEL, PCI_DEVICE_ID_CLOVERVIEW),
652 (kernel_ulong_t)&intel_scu_ipc_penwell_pdata,
653 }, {
654 PCI_VDEVICE(INTEL, PCI_DEVICE_ID_TANGIER),
655 (kernel_ulong_t)&intel_scu_ipc_tangier_pdata,
656 }, {
657 0,
658 }
659};
660MODULE_DEVICE_TABLE(pci, pci_ids);
661
662static struct pci_driver ipc_driver = {
663 .name = "intel_scu_ipc",
664 .id_table = pci_ids,
665 .probe = ipc_probe,
666 .remove = ipc_remove,
667};
668
669
670static int __init intel_scu_ipc_init(void)
671{
672 platform = intel_mid_identify_cpu();
673 if (platform == 0)
674 return -ENODEV;
675 return pci_register_driver(&ipc_driver);
676}
677
678static void __exit intel_scu_ipc_exit(void)
679{
680 pci_unregister_driver(&ipc_driver);
681}
682
683MODULE_AUTHOR("Sreedhara DS <sreedhara.ds@intel.com>");
684MODULE_DESCRIPTION("Intel SCU IPC driver");
685MODULE_LICENSE("GPL");
686
687module_init(intel_scu_ipc_init);
688module_exit(intel_scu_ipc_exit);