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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Microchip ENC28J60 ethernet driver (MAC + PHY)
4 *
5 * Copyright (C) 2007 Eurek srl
6 * Author: Claudio Lanconelli <lanconelli.claudio@eptar.com>
7 * based on enc28j60.c written by David Anders for 2.4 kernel version
8 *
9 * $Id: enc28j60.c,v 1.22 2007/12/20 10:47:01 claudio Exp $
10 */
11
12#include <linux/module.h>
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/fcntl.h>
16#include <linux/interrupt.h>
17#include <linux/property.h>
18#include <linux/string.h>
19#include <linux/errno.h>
20#include <linux/netdevice.h>
21#include <linux/etherdevice.h>
22#include <linux/ethtool.h>
23#include <linux/tcp.h>
24#include <linux/skbuff.h>
25#include <linux/delay.h>
26#include <linux/spi/spi.h>
27
28#include "enc28j60_hw.h"
29
30#define DRV_NAME "enc28j60"
31#define DRV_VERSION "1.02"
32
33#define SPI_OPLEN 1
34
35#define ENC28J60_MSG_DEFAULT \
36 (NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN | NETIF_MSG_LINK)
37
38/* Buffer size required for the largest SPI transfer (i.e., reading a
39 * frame).
40 */
41#define SPI_TRANSFER_BUF_LEN (4 + MAX_FRAMELEN)
42
43#define TX_TIMEOUT (4 * HZ)
44
45/* Max TX retries in case of collision as suggested by errata datasheet */
46#define MAX_TX_RETRYCOUNT 16
47
48enum {
49 RXFILTER_NORMAL,
50 RXFILTER_MULTI,
51 RXFILTER_PROMISC
52};
53
54/* Driver local data */
55struct enc28j60_net {
56 struct net_device *netdev;
57 struct spi_device *spi;
58 struct mutex lock;
59 struct sk_buff *tx_skb;
60 struct work_struct tx_work;
61 struct work_struct setrx_work;
62 struct work_struct restart_work;
63 u8 bank; /* current register bank selected */
64 u16 next_pk_ptr; /* next packet pointer within FIFO */
65 u16 max_pk_counter; /* statistics: max packet counter */
66 u16 tx_retry_count;
67 bool hw_enable;
68 bool full_duplex;
69 int rxfilter;
70 u32 msg_enable;
71 u8 spi_transfer_buf[SPI_TRANSFER_BUF_LEN];
72};
73
74/* use ethtool to change the level for any given device */
75static struct {
76 u32 msg_enable;
77} debug = { -1 };
78
79/*
80 * SPI read buffer
81 * Wait for the SPI transfer and copy received data to destination.
82 */
83static int
84spi_read_buf(struct enc28j60_net *priv, int len, u8 *data)
85{
86 struct device *dev = &priv->spi->dev;
87 u8 *rx_buf = priv->spi_transfer_buf + 4;
88 u8 *tx_buf = priv->spi_transfer_buf;
89 struct spi_transfer tx = {
90 .tx_buf = tx_buf,
91 .len = SPI_OPLEN,
92 };
93 struct spi_transfer rx = {
94 .rx_buf = rx_buf,
95 .len = len,
96 };
97 struct spi_message msg;
98 int ret;
99
100 tx_buf[0] = ENC28J60_READ_BUF_MEM;
101
102 spi_message_init(&msg);
103 spi_message_add_tail(&tx, &msg);
104 spi_message_add_tail(&rx, &msg);
105
106 ret = spi_sync(priv->spi, &msg);
107 if (ret == 0) {
108 memcpy(data, rx_buf, len);
109 ret = msg.status;
110 }
111 if (ret && netif_msg_drv(priv))
112 dev_printk(KERN_DEBUG, dev, "%s() failed: ret = %d\n",
113 __func__, ret);
114
115 return ret;
116}
117
118/*
119 * SPI write buffer
120 */
121static int spi_write_buf(struct enc28j60_net *priv, int len, const u8 *data)
122{
123 struct device *dev = &priv->spi->dev;
124 int ret;
125
126 if (len > SPI_TRANSFER_BUF_LEN - 1 || len <= 0)
127 ret = -EINVAL;
128 else {
129 priv->spi_transfer_buf[0] = ENC28J60_WRITE_BUF_MEM;
130 memcpy(&priv->spi_transfer_buf[1], data, len);
131 ret = spi_write(priv->spi, priv->spi_transfer_buf, len + 1);
132 if (ret && netif_msg_drv(priv))
133 dev_printk(KERN_DEBUG, dev, "%s() failed: ret = %d\n",
134 __func__, ret);
135 }
136 return ret;
137}
138
139/*
140 * basic SPI read operation
141 */
142static u8 spi_read_op(struct enc28j60_net *priv, u8 op, u8 addr)
143{
144 struct device *dev = &priv->spi->dev;
145 u8 tx_buf[2];
146 u8 rx_buf[4];
147 u8 val = 0;
148 int ret;
149 int slen = SPI_OPLEN;
150
151 /* do dummy read if needed */
152 if (addr & SPRD_MASK)
153 slen++;
154
155 tx_buf[0] = op | (addr & ADDR_MASK);
156 ret = spi_write_then_read(priv->spi, tx_buf, 1, rx_buf, slen);
157 if (ret)
158 dev_printk(KERN_DEBUG, dev, "%s() failed: ret = %d\n",
159 __func__, ret);
160 else
161 val = rx_buf[slen - 1];
162
163 return val;
164}
165
166/*
167 * basic SPI write operation
168 */
169static int spi_write_op(struct enc28j60_net *priv, u8 op, u8 addr, u8 val)
170{
171 struct device *dev = &priv->spi->dev;
172 int ret;
173
174 priv->spi_transfer_buf[0] = op | (addr & ADDR_MASK);
175 priv->spi_transfer_buf[1] = val;
176 ret = spi_write(priv->spi, priv->spi_transfer_buf, 2);
177 if (ret && netif_msg_drv(priv))
178 dev_printk(KERN_DEBUG, dev, "%s() failed: ret = %d\n",
179 __func__, ret);
180 return ret;
181}
182
183static void enc28j60_soft_reset(struct enc28j60_net *priv)
184{
185 spi_write_op(priv, ENC28J60_SOFT_RESET, 0, ENC28J60_SOFT_RESET);
186 /* Errata workaround #1, CLKRDY check is unreliable,
187 * delay at least 1 ms instead */
188 udelay(2000);
189}
190
191/*
192 * select the current register bank if necessary
193 */
194static void enc28j60_set_bank(struct enc28j60_net *priv, u8 addr)
195{
196 u8 b = (addr & BANK_MASK) >> 5;
197
198 /* These registers (EIE, EIR, ESTAT, ECON2, ECON1)
199 * are present in all banks, no need to switch bank.
200 */
201 if (addr >= EIE && addr <= ECON1)
202 return;
203
204 /* Clear or set each bank selection bit as needed */
205 if ((b & ECON1_BSEL0) != (priv->bank & ECON1_BSEL0)) {
206 if (b & ECON1_BSEL0)
207 spi_write_op(priv, ENC28J60_BIT_FIELD_SET, ECON1,
208 ECON1_BSEL0);
209 else
210 spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, ECON1,
211 ECON1_BSEL0);
212 }
213 if ((b & ECON1_BSEL1) != (priv->bank & ECON1_BSEL1)) {
214 if (b & ECON1_BSEL1)
215 spi_write_op(priv, ENC28J60_BIT_FIELD_SET, ECON1,
216 ECON1_BSEL1);
217 else
218 spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, ECON1,
219 ECON1_BSEL1);
220 }
221 priv->bank = b;
222}
223
224/*
225 * Register access routines through the SPI bus.
226 * Every register access comes in two flavours:
227 * - nolock_xxx: caller needs to invoke mutex_lock, usually to access
228 * atomically more than one register
229 * - locked_xxx: caller doesn't need to invoke mutex_lock, single access
230 *
231 * Some registers can be accessed through the bit field clear and
232 * bit field set to avoid a read modify write cycle.
233 */
234
235/*
236 * Register bit field Set
237 */
238static void nolock_reg_bfset(struct enc28j60_net *priv, u8 addr, u8 mask)
239{
240 enc28j60_set_bank(priv, addr);
241 spi_write_op(priv, ENC28J60_BIT_FIELD_SET, addr, mask);
242}
243
244static void locked_reg_bfset(struct enc28j60_net *priv, u8 addr, u8 mask)
245{
246 mutex_lock(&priv->lock);
247 nolock_reg_bfset(priv, addr, mask);
248 mutex_unlock(&priv->lock);
249}
250
251/*
252 * Register bit field Clear
253 */
254static void nolock_reg_bfclr(struct enc28j60_net *priv, u8 addr, u8 mask)
255{
256 enc28j60_set_bank(priv, addr);
257 spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, addr, mask);
258}
259
260static void locked_reg_bfclr(struct enc28j60_net *priv, u8 addr, u8 mask)
261{
262 mutex_lock(&priv->lock);
263 nolock_reg_bfclr(priv, addr, mask);
264 mutex_unlock(&priv->lock);
265}
266
267/*
268 * Register byte read
269 */
270static int nolock_regb_read(struct enc28j60_net *priv, u8 address)
271{
272 enc28j60_set_bank(priv, address);
273 return spi_read_op(priv, ENC28J60_READ_CTRL_REG, address);
274}
275
276static int locked_regb_read(struct enc28j60_net *priv, u8 address)
277{
278 int ret;
279
280 mutex_lock(&priv->lock);
281 ret = nolock_regb_read(priv, address);
282 mutex_unlock(&priv->lock);
283
284 return ret;
285}
286
287/*
288 * Register word read
289 */
290static int nolock_regw_read(struct enc28j60_net *priv, u8 address)
291{
292 int rl, rh;
293
294 enc28j60_set_bank(priv, address);
295 rl = spi_read_op(priv, ENC28J60_READ_CTRL_REG, address);
296 rh = spi_read_op(priv, ENC28J60_READ_CTRL_REG, address + 1);
297
298 return (rh << 8) | rl;
299}
300
301static int locked_regw_read(struct enc28j60_net *priv, u8 address)
302{
303 int ret;
304
305 mutex_lock(&priv->lock);
306 ret = nolock_regw_read(priv, address);
307 mutex_unlock(&priv->lock);
308
309 return ret;
310}
311
312/*
313 * Register byte write
314 */
315static void nolock_regb_write(struct enc28j60_net *priv, u8 address, u8 data)
316{
317 enc28j60_set_bank(priv, address);
318 spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, address, data);
319}
320
321static void locked_regb_write(struct enc28j60_net *priv, u8 address, u8 data)
322{
323 mutex_lock(&priv->lock);
324 nolock_regb_write(priv, address, data);
325 mutex_unlock(&priv->lock);
326}
327
328/*
329 * Register word write
330 */
331static void nolock_regw_write(struct enc28j60_net *priv, u8 address, u16 data)
332{
333 enc28j60_set_bank(priv, address);
334 spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, address, (u8) data);
335 spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, address + 1,
336 (u8) (data >> 8));
337}
338
339static void locked_regw_write(struct enc28j60_net *priv, u8 address, u16 data)
340{
341 mutex_lock(&priv->lock);
342 nolock_regw_write(priv, address, data);
343 mutex_unlock(&priv->lock);
344}
345
346/*
347 * Buffer memory read
348 * Select the starting address and execute a SPI buffer read.
349 */
350static void enc28j60_mem_read(struct enc28j60_net *priv, u16 addr, int len,
351 u8 *data)
352{
353 mutex_lock(&priv->lock);
354 nolock_regw_write(priv, ERDPTL, addr);
355#ifdef CONFIG_ENC28J60_WRITEVERIFY
356 if (netif_msg_drv(priv)) {
357 struct device *dev = &priv->spi->dev;
358 u16 reg;
359
360 reg = nolock_regw_read(priv, ERDPTL);
361 if (reg != addr)
362 dev_printk(KERN_DEBUG, dev,
363 "%s() error writing ERDPT (0x%04x - 0x%04x)\n",
364 __func__, reg, addr);
365 }
366#endif
367 spi_read_buf(priv, len, data);
368 mutex_unlock(&priv->lock);
369}
370
371/*
372 * Write packet to enc28j60 TX buffer memory
373 */
374static void
375enc28j60_packet_write(struct enc28j60_net *priv, int len, const u8 *data)
376{
377 struct device *dev = &priv->spi->dev;
378
379 mutex_lock(&priv->lock);
380 /* Set the write pointer to start of transmit buffer area */
381 nolock_regw_write(priv, EWRPTL, TXSTART_INIT);
382#ifdef CONFIG_ENC28J60_WRITEVERIFY
383 if (netif_msg_drv(priv)) {
384 u16 reg;
385 reg = nolock_regw_read(priv, EWRPTL);
386 if (reg != TXSTART_INIT)
387 dev_printk(KERN_DEBUG, dev,
388 "%s() ERWPT:0x%04x != 0x%04x\n",
389 __func__, reg, TXSTART_INIT);
390 }
391#endif
392 /* Set the TXND pointer to correspond to the packet size given */
393 nolock_regw_write(priv, ETXNDL, TXSTART_INIT + len);
394 /* write per-packet control byte */
395 spi_write_op(priv, ENC28J60_WRITE_BUF_MEM, 0, 0x00);
396 if (netif_msg_hw(priv))
397 dev_printk(KERN_DEBUG, dev,
398 "%s() after control byte ERWPT:0x%04x\n",
399 __func__, nolock_regw_read(priv, EWRPTL));
400 /* copy the packet into the transmit buffer */
401 spi_write_buf(priv, len, data);
402 if (netif_msg_hw(priv))
403 dev_printk(KERN_DEBUG, dev,
404 "%s() after write packet ERWPT:0x%04x, len=%d\n",
405 __func__, nolock_regw_read(priv, EWRPTL), len);
406 mutex_unlock(&priv->lock);
407}
408
409static int poll_ready(struct enc28j60_net *priv, u8 reg, u8 mask, u8 val)
410{
411 struct device *dev = &priv->spi->dev;
412 unsigned long timeout = jiffies + msecs_to_jiffies(20);
413
414 /* 20 msec timeout read */
415 while ((nolock_regb_read(priv, reg) & mask) != val) {
416 if (time_after(jiffies, timeout)) {
417 if (netif_msg_drv(priv))
418 dev_dbg(dev, "reg %02x ready timeout!\n", reg);
419 return -ETIMEDOUT;
420 }
421 cpu_relax();
422 }
423 return 0;
424}
425
426/*
427 * Wait until the PHY operation is complete.
428 */
429static int wait_phy_ready(struct enc28j60_net *priv)
430{
431 return poll_ready(priv, MISTAT, MISTAT_BUSY, 0) ? 0 : 1;
432}
433
434/*
435 * PHY register read
436 * PHY registers are not accessed directly, but through the MII.
437 */
438static u16 enc28j60_phy_read(struct enc28j60_net *priv, u8 address)
439{
440 u16 ret;
441
442 mutex_lock(&priv->lock);
443 /* set the PHY register address */
444 nolock_regb_write(priv, MIREGADR, address);
445 /* start the register read operation */
446 nolock_regb_write(priv, MICMD, MICMD_MIIRD);
447 /* wait until the PHY read completes */
448 wait_phy_ready(priv);
449 /* quit reading */
450 nolock_regb_write(priv, MICMD, 0x00);
451 /* return the data */
452 ret = nolock_regw_read(priv, MIRDL);
453 mutex_unlock(&priv->lock);
454
455 return ret;
456}
457
458static int enc28j60_phy_write(struct enc28j60_net *priv, u8 address, u16 data)
459{
460 int ret;
461
462 mutex_lock(&priv->lock);
463 /* set the PHY register address */
464 nolock_regb_write(priv, MIREGADR, address);
465 /* write the PHY data */
466 nolock_regw_write(priv, MIWRL, data);
467 /* wait until the PHY write completes and return */
468 ret = wait_phy_ready(priv);
469 mutex_unlock(&priv->lock);
470
471 return ret;
472}
473
474/*
475 * Program the hardware MAC address from dev->dev_addr.
476 */
477static int enc28j60_set_hw_macaddr(struct net_device *ndev)
478{
479 int ret;
480 struct enc28j60_net *priv = netdev_priv(ndev);
481 struct device *dev = &priv->spi->dev;
482
483 mutex_lock(&priv->lock);
484 if (!priv->hw_enable) {
485 if (netif_msg_drv(priv))
486 dev_info(dev, "%s: Setting MAC address to %pM\n",
487 ndev->name, ndev->dev_addr);
488 /* NOTE: MAC address in ENC28J60 is byte-backward */
489 nolock_regb_write(priv, MAADR5, ndev->dev_addr[0]);
490 nolock_regb_write(priv, MAADR4, ndev->dev_addr[1]);
491 nolock_regb_write(priv, MAADR3, ndev->dev_addr[2]);
492 nolock_regb_write(priv, MAADR2, ndev->dev_addr[3]);
493 nolock_regb_write(priv, MAADR1, ndev->dev_addr[4]);
494 nolock_regb_write(priv, MAADR0, ndev->dev_addr[5]);
495 ret = 0;
496 } else {
497 if (netif_msg_drv(priv))
498 dev_printk(KERN_DEBUG, dev,
499 "%s() Hardware must be disabled to set Mac address\n",
500 __func__);
501 ret = -EBUSY;
502 }
503 mutex_unlock(&priv->lock);
504 return ret;
505}
506
507/*
508 * Store the new hardware address in dev->dev_addr, and update the MAC.
509 */
510static int enc28j60_set_mac_address(struct net_device *dev, void *addr)
511{
512 struct sockaddr *address = addr;
513
514 if (netif_running(dev))
515 return -EBUSY;
516 if (!is_valid_ether_addr(address->sa_data))
517 return -EADDRNOTAVAIL;
518
519 eth_hw_addr_set(dev, address->sa_data);
520 return enc28j60_set_hw_macaddr(dev);
521}
522
523/*
524 * Debug routine to dump useful register contents
525 */
526static void enc28j60_dump_regs(struct enc28j60_net *priv, const char *msg)
527{
528 struct device *dev = &priv->spi->dev;
529
530 mutex_lock(&priv->lock);
531 dev_printk(KERN_DEBUG, dev,
532 " %s\n"
533 "HwRevID: 0x%02x\n"
534 "Cntrl: ECON1 ECON2 ESTAT EIR EIE\n"
535 " 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x\n"
536 "MAC : MACON1 MACON3 MACON4\n"
537 " 0x%02x 0x%02x 0x%02x\n"
538 "Rx : ERXST ERXND ERXWRPT ERXRDPT ERXFCON EPKTCNT MAMXFL\n"
539 " 0x%04x 0x%04x 0x%04x 0x%04x "
540 "0x%02x 0x%02x 0x%04x\n"
541 "Tx : ETXST ETXND MACLCON1 MACLCON2 MAPHSUP\n"
542 " 0x%04x 0x%04x 0x%02x 0x%02x 0x%02x\n",
543 msg, nolock_regb_read(priv, EREVID),
544 nolock_regb_read(priv, ECON1), nolock_regb_read(priv, ECON2),
545 nolock_regb_read(priv, ESTAT), nolock_regb_read(priv, EIR),
546 nolock_regb_read(priv, EIE), nolock_regb_read(priv, MACON1),
547 nolock_regb_read(priv, MACON3), nolock_regb_read(priv, MACON4),
548 nolock_regw_read(priv, ERXSTL), nolock_regw_read(priv, ERXNDL),
549 nolock_regw_read(priv, ERXWRPTL),
550 nolock_regw_read(priv, ERXRDPTL),
551 nolock_regb_read(priv, ERXFCON),
552 nolock_regb_read(priv, EPKTCNT),
553 nolock_regw_read(priv, MAMXFLL), nolock_regw_read(priv, ETXSTL),
554 nolock_regw_read(priv, ETXNDL),
555 nolock_regb_read(priv, MACLCON1),
556 nolock_regb_read(priv, MACLCON2),
557 nolock_regb_read(priv, MAPHSUP));
558 mutex_unlock(&priv->lock);
559}
560
561/*
562 * ERXRDPT need to be set always at odd addresses, refer to errata datasheet
563 */
564static u16 erxrdpt_workaround(u16 next_packet_ptr, u16 start, u16 end)
565{
566 u16 erxrdpt;
567
568 if ((next_packet_ptr - 1 < start) || (next_packet_ptr - 1 > end))
569 erxrdpt = end;
570 else
571 erxrdpt = next_packet_ptr - 1;
572
573 return erxrdpt;
574}
575
576/*
577 * Calculate wrap around when reading beyond the end of the RX buffer
578 */
579static u16 rx_packet_start(u16 ptr)
580{
581 if (ptr + RSV_SIZE > RXEND_INIT)
582 return (ptr + RSV_SIZE) - (RXEND_INIT - RXSTART_INIT + 1);
583 else
584 return ptr + RSV_SIZE;
585}
586
587static void nolock_rxfifo_init(struct enc28j60_net *priv, u16 start, u16 end)
588{
589 struct device *dev = &priv->spi->dev;
590 u16 erxrdpt;
591
592 if (start > 0x1FFF || end > 0x1FFF || start > end) {
593 if (netif_msg_drv(priv))
594 dev_err(dev, "%s(%d, %d) RXFIFO bad parameters!\n",
595 __func__, start, end);
596 return;
597 }
598 /* set receive buffer start + end */
599 priv->next_pk_ptr = start;
600 nolock_regw_write(priv, ERXSTL, start);
601 erxrdpt = erxrdpt_workaround(priv->next_pk_ptr, start, end);
602 nolock_regw_write(priv, ERXRDPTL, erxrdpt);
603 nolock_regw_write(priv, ERXNDL, end);
604}
605
606static void nolock_txfifo_init(struct enc28j60_net *priv, u16 start, u16 end)
607{
608 struct device *dev = &priv->spi->dev;
609
610 if (start > 0x1FFF || end > 0x1FFF || start > end) {
611 if (netif_msg_drv(priv))
612 dev_err(dev, "%s(%d, %d) TXFIFO bad parameters!\n",
613 __func__, start, end);
614 return;
615 }
616 /* set transmit buffer start + end */
617 nolock_regw_write(priv, ETXSTL, start);
618 nolock_regw_write(priv, ETXNDL, end);
619}
620
621/*
622 * Low power mode shrinks power consumption about 100x, so we'd like
623 * the chip to be in that mode whenever it's inactive. (However, we
624 * can't stay in low power mode during suspend with WOL active.)
625 */
626static void enc28j60_lowpower(struct enc28j60_net *priv, bool is_low)
627{
628 struct device *dev = &priv->spi->dev;
629
630 if (netif_msg_drv(priv))
631 dev_dbg(dev, "%s power...\n", is_low ? "low" : "high");
632
633 mutex_lock(&priv->lock);
634 if (is_low) {
635 nolock_reg_bfclr(priv, ECON1, ECON1_RXEN);
636 poll_ready(priv, ESTAT, ESTAT_RXBUSY, 0);
637 poll_ready(priv, ECON1, ECON1_TXRTS, 0);
638 /* ECON2_VRPS was set during initialization */
639 nolock_reg_bfset(priv, ECON2, ECON2_PWRSV);
640 } else {
641 nolock_reg_bfclr(priv, ECON2, ECON2_PWRSV);
642 poll_ready(priv, ESTAT, ESTAT_CLKRDY, ESTAT_CLKRDY);
643 /* caller sets ECON1_RXEN */
644 }
645 mutex_unlock(&priv->lock);
646}
647
648static int enc28j60_hw_init(struct enc28j60_net *priv)
649{
650 struct device *dev = &priv->spi->dev;
651 u8 reg;
652
653 if (netif_msg_drv(priv))
654 dev_printk(KERN_DEBUG, dev, "%s() - %s\n", __func__,
655 priv->full_duplex ? "FullDuplex" : "HalfDuplex");
656
657 mutex_lock(&priv->lock);
658 /* first reset the chip */
659 enc28j60_soft_reset(priv);
660 /* Clear ECON1 */
661 spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, ECON1, 0x00);
662 priv->bank = 0;
663 priv->hw_enable = false;
664 priv->tx_retry_count = 0;
665 priv->max_pk_counter = 0;
666 priv->rxfilter = RXFILTER_NORMAL;
667 /* enable address auto increment and voltage regulator powersave */
668 nolock_regb_write(priv, ECON2, ECON2_AUTOINC | ECON2_VRPS);
669
670 nolock_rxfifo_init(priv, RXSTART_INIT, RXEND_INIT);
671 nolock_txfifo_init(priv, TXSTART_INIT, TXEND_INIT);
672 mutex_unlock(&priv->lock);
673
674 /*
675 * Check the RevID.
676 * If it's 0x00 or 0xFF probably the enc28j60 is not mounted or
677 * damaged.
678 */
679 reg = locked_regb_read(priv, EREVID);
680 if (netif_msg_drv(priv))
681 dev_info(dev, "chip RevID: 0x%02x\n", reg);
682 if (reg == 0x00 || reg == 0xff) {
683 if (netif_msg_drv(priv))
684 dev_printk(KERN_DEBUG, dev, "%s() Invalid RevId %d\n",
685 __func__, reg);
686 return 0;
687 }
688
689 /* default filter mode: (unicast OR broadcast) AND crc valid */
690 locked_regb_write(priv, ERXFCON,
691 ERXFCON_UCEN | ERXFCON_CRCEN | ERXFCON_BCEN);
692
693 /* enable MAC receive */
694 locked_regb_write(priv, MACON1,
695 MACON1_MARXEN | MACON1_TXPAUS | MACON1_RXPAUS);
696 /* enable automatic padding and CRC operations */
697 if (priv->full_duplex) {
698 locked_regb_write(priv, MACON3,
699 MACON3_PADCFG0 | MACON3_TXCRCEN |
700 MACON3_FRMLNEN | MACON3_FULDPX);
701 /* set inter-frame gap (non-back-to-back) */
702 locked_regb_write(priv, MAIPGL, 0x12);
703 /* set inter-frame gap (back-to-back) */
704 locked_regb_write(priv, MABBIPG, 0x15);
705 } else {
706 locked_regb_write(priv, MACON3,
707 MACON3_PADCFG0 | MACON3_TXCRCEN |
708 MACON3_FRMLNEN);
709 locked_regb_write(priv, MACON4, 1 << 6); /* DEFER bit */
710 /* set inter-frame gap (non-back-to-back) */
711 locked_regw_write(priv, MAIPGL, 0x0C12);
712 /* set inter-frame gap (back-to-back) */
713 locked_regb_write(priv, MABBIPG, 0x12);
714 }
715 /*
716 * MACLCON1 (default)
717 * MACLCON2 (default)
718 * Set the maximum packet size which the controller will accept.
719 */
720 locked_regw_write(priv, MAMXFLL, MAX_FRAMELEN);
721
722 /* Configure LEDs */
723 if (!enc28j60_phy_write(priv, PHLCON, ENC28J60_LAMPS_MODE))
724 return 0;
725
726 if (priv->full_duplex) {
727 if (!enc28j60_phy_write(priv, PHCON1, PHCON1_PDPXMD))
728 return 0;
729 if (!enc28j60_phy_write(priv, PHCON2, 0x00))
730 return 0;
731 } else {
732 if (!enc28j60_phy_write(priv, PHCON1, 0x00))
733 return 0;
734 if (!enc28j60_phy_write(priv, PHCON2, PHCON2_HDLDIS))
735 return 0;
736 }
737 if (netif_msg_hw(priv))
738 enc28j60_dump_regs(priv, "Hw initialized.");
739
740 return 1;
741}
742
743static void enc28j60_hw_enable(struct enc28j60_net *priv)
744{
745 struct device *dev = &priv->spi->dev;
746
747 /* enable interrupts */
748 if (netif_msg_hw(priv))
749 dev_printk(KERN_DEBUG, dev, "%s() enabling interrupts.\n",
750 __func__);
751
752 enc28j60_phy_write(priv, PHIE, PHIE_PGEIE | PHIE_PLNKIE);
753
754 mutex_lock(&priv->lock);
755 nolock_reg_bfclr(priv, EIR, EIR_DMAIF | EIR_LINKIF |
756 EIR_TXIF | EIR_TXERIF | EIR_RXERIF | EIR_PKTIF);
757 nolock_regb_write(priv, EIE, EIE_INTIE | EIE_PKTIE | EIE_LINKIE |
758 EIE_TXIE | EIE_TXERIE | EIE_RXERIE);
759
760 /* enable receive logic */
761 nolock_reg_bfset(priv, ECON1, ECON1_RXEN);
762 priv->hw_enable = true;
763 mutex_unlock(&priv->lock);
764}
765
766static void enc28j60_hw_disable(struct enc28j60_net *priv)
767{
768 mutex_lock(&priv->lock);
769 /* disable interrupts and packet reception */
770 nolock_regb_write(priv, EIE, 0x00);
771 nolock_reg_bfclr(priv, ECON1, ECON1_RXEN);
772 priv->hw_enable = false;
773 mutex_unlock(&priv->lock);
774}
775
776static int
777enc28j60_setlink(struct net_device *ndev, u8 autoneg, u16 speed, u8 duplex)
778{
779 struct enc28j60_net *priv = netdev_priv(ndev);
780 int ret = 0;
781
782 if (!priv->hw_enable) {
783 /* link is in low power mode now; duplex setting
784 * will take effect on next enc28j60_hw_init().
785 */
786 if (autoneg == AUTONEG_DISABLE && speed == SPEED_10)
787 priv->full_duplex = (duplex == DUPLEX_FULL);
788 else {
789 if (netif_msg_link(priv))
790 netdev_warn(ndev, "unsupported link setting\n");
791 ret = -EOPNOTSUPP;
792 }
793 } else {
794 if (netif_msg_link(priv))
795 netdev_warn(ndev, "Warning: hw must be disabled to set link mode\n");
796 ret = -EBUSY;
797 }
798 return ret;
799}
800
801/*
802 * Read the Transmit Status Vector
803 */
804static void enc28j60_read_tsv(struct enc28j60_net *priv, u8 tsv[TSV_SIZE])
805{
806 struct device *dev = &priv->spi->dev;
807 int endptr;
808
809 endptr = locked_regw_read(priv, ETXNDL);
810 if (netif_msg_hw(priv))
811 dev_printk(KERN_DEBUG, dev, "reading TSV at addr:0x%04x\n",
812 endptr + 1);
813 enc28j60_mem_read(priv, endptr + 1, TSV_SIZE, tsv);
814}
815
816static void enc28j60_dump_tsv(struct enc28j60_net *priv, const char *msg,
817 u8 tsv[TSV_SIZE])
818{
819 struct device *dev = &priv->spi->dev;
820 u16 tmp1, tmp2;
821
822 dev_printk(KERN_DEBUG, dev, "%s - TSV:\n", msg);
823 tmp1 = tsv[1];
824 tmp1 <<= 8;
825 tmp1 |= tsv[0];
826
827 tmp2 = tsv[5];
828 tmp2 <<= 8;
829 tmp2 |= tsv[4];
830
831 dev_printk(KERN_DEBUG, dev,
832 "ByteCount: %d, CollisionCount: %d, TotByteOnWire: %d\n",
833 tmp1, tsv[2] & 0x0f, tmp2);
834 dev_printk(KERN_DEBUG, dev,
835 "TxDone: %d, CRCErr:%d, LenChkErr: %d, LenOutOfRange: %d\n",
836 TSV_GETBIT(tsv, TSV_TXDONE),
837 TSV_GETBIT(tsv, TSV_TXCRCERROR),
838 TSV_GETBIT(tsv, TSV_TXLENCHKERROR),
839 TSV_GETBIT(tsv, TSV_TXLENOUTOFRANGE));
840 dev_printk(KERN_DEBUG, dev,
841 "Multicast: %d, Broadcast: %d, PacketDefer: %d, ExDefer: %d\n",
842 TSV_GETBIT(tsv, TSV_TXMULTICAST),
843 TSV_GETBIT(tsv, TSV_TXBROADCAST),
844 TSV_GETBIT(tsv, TSV_TXPACKETDEFER),
845 TSV_GETBIT(tsv, TSV_TXEXDEFER));
846 dev_printk(KERN_DEBUG, dev,
847 "ExCollision: %d, LateCollision: %d, Giant: %d, Underrun: %d\n",
848 TSV_GETBIT(tsv, TSV_TXEXCOLLISION),
849 TSV_GETBIT(tsv, TSV_TXLATECOLLISION),
850 TSV_GETBIT(tsv, TSV_TXGIANT), TSV_GETBIT(tsv, TSV_TXUNDERRUN));
851 dev_printk(KERN_DEBUG, dev,
852 "ControlFrame: %d, PauseFrame: %d, BackPressApp: %d, VLanTagFrame: %d\n",
853 TSV_GETBIT(tsv, TSV_TXCONTROLFRAME),
854 TSV_GETBIT(tsv, TSV_TXPAUSEFRAME),
855 TSV_GETBIT(tsv, TSV_BACKPRESSUREAPP),
856 TSV_GETBIT(tsv, TSV_TXVLANTAGFRAME));
857}
858
859/*
860 * Receive Status vector
861 */
862static void enc28j60_dump_rsv(struct enc28j60_net *priv, const char *msg,
863 u16 pk_ptr, int len, u16 sts)
864{
865 struct device *dev = &priv->spi->dev;
866
867 dev_printk(KERN_DEBUG, dev, "%s - NextPk: 0x%04x - RSV:\n", msg, pk_ptr);
868 dev_printk(KERN_DEBUG, dev, "ByteCount: %d, DribbleNibble: %d\n",
869 len, RSV_GETBIT(sts, RSV_DRIBBLENIBBLE));
870 dev_printk(KERN_DEBUG, dev,
871 "RxOK: %d, CRCErr:%d, LenChkErr: %d, LenOutOfRange: %d\n",
872 RSV_GETBIT(sts, RSV_RXOK),
873 RSV_GETBIT(sts, RSV_CRCERROR),
874 RSV_GETBIT(sts, RSV_LENCHECKERR),
875 RSV_GETBIT(sts, RSV_LENOUTOFRANGE));
876 dev_printk(KERN_DEBUG, dev,
877 "Multicast: %d, Broadcast: %d, LongDropEvent: %d, CarrierEvent: %d\n",
878 RSV_GETBIT(sts, RSV_RXMULTICAST),
879 RSV_GETBIT(sts, RSV_RXBROADCAST),
880 RSV_GETBIT(sts, RSV_RXLONGEVDROPEV),
881 RSV_GETBIT(sts, RSV_CARRIEREV));
882 dev_printk(KERN_DEBUG, dev,
883 "ControlFrame: %d, PauseFrame: %d, UnknownOp: %d, VLanTagFrame: %d\n",
884 RSV_GETBIT(sts, RSV_RXCONTROLFRAME),
885 RSV_GETBIT(sts, RSV_RXPAUSEFRAME),
886 RSV_GETBIT(sts, RSV_RXUNKNOWNOPCODE),
887 RSV_GETBIT(sts, RSV_RXTYPEVLAN));
888}
889
890static void dump_packet(const char *msg, int len, const char *data)
891{
892 printk(KERN_DEBUG DRV_NAME ": %s - packet len:%d\n", msg, len);
893 print_hex_dump(KERN_DEBUG, "pk data: ", DUMP_PREFIX_OFFSET, 16, 1,
894 data, len, true);
895}
896
897/*
898 * Hardware receive function.
899 * Read the buffer memory, update the FIFO pointer to free the buffer,
900 * check the status vector and decrement the packet counter.
901 */
902static void enc28j60_hw_rx(struct net_device *ndev)
903{
904 struct enc28j60_net *priv = netdev_priv(ndev);
905 struct device *dev = &priv->spi->dev;
906 struct sk_buff *skb = NULL;
907 u16 erxrdpt, next_packet, rxstat;
908 u8 rsv[RSV_SIZE];
909 int len;
910
911 if (netif_msg_rx_status(priv))
912 netdev_printk(KERN_DEBUG, ndev, "RX pk_addr:0x%04x\n",
913 priv->next_pk_ptr);
914
915 if (unlikely(priv->next_pk_ptr > RXEND_INIT)) {
916 if (netif_msg_rx_err(priv))
917 netdev_err(ndev, "%s() Invalid packet address!! 0x%04x\n",
918 __func__, priv->next_pk_ptr);
919 /* packet address corrupted: reset RX logic */
920 mutex_lock(&priv->lock);
921 nolock_reg_bfclr(priv, ECON1, ECON1_RXEN);
922 nolock_reg_bfset(priv, ECON1, ECON1_RXRST);
923 nolock_reg_bfclr(priv, ECON1, ECON1_RXRST);
924 nolock_rxfifo_init(priv, RXSTART_INIT, RXEND_INIT);
925 nolock_reg_bfclr(priv, EIR, EIR_RXERIF);
926 nolock_reg_bfset(priv, ECON1, ECON1_RXEN);
927 mutex_unlock(&priv->lock);
928 ndev->stats.rx_errors++;
929 return;
930 }
931 /* Read next packet pointer and rx status vector */
932 enc28j60_mem_read(priv, priv->next_pk_ptr, sizeof(rsv), rsv);
933
934 next_packet = rsv[1];
935 next_packet <<= 8;
936 next_packet |= rsv[0];
937
938 len = rsv[3];
939 len <<= 8;
940 len |= rsv[2];
941
942 rxstat = rsv[5];
943 rxstat <<= 8;
944 rxstat |= rsv[4];
945
946 if (netif_msg_rx_status(priv))
947 enc28j60_dump_rsv(priv, __func__, next_packet, len, rxstat);
948
949 if (!RSV_GETBIT(rxstat, RSV_RXOK) || len > MAX_FRAMELEN) {
950 if (netif_msg_rx_err(priv))
951 netdev_err(ndev, "Rx Error (%04x)\n", rxstat);
952 ndev->stats.rx_errors++;
953 if (RSV_GETBIT(rxstat, RSV_CRCERROR))
954 ndev->stats.rx_crc_errors++;
955 if (RSV_GETBIT(rxstat, RSV_LENCHECKERR))
956 ndev->stats.rx_frame_errors++;
957 if (len > MAX_FRAMELEN)
958 ndev->stats.rx_over_errors++;
959 } else {
960 skb = netdev_alloc_skb(ndev, len + NET_IP_ALIGN);
961 if (!skb) {
962 if (netif_msg_rx_err(priv))
963 netdev_err(ndev, "out of memory for Rx'd frame\n");
964 ndev->stats.rx_dropped++;
965 } else {
966 skb_reserve(skb, NET_IP_ALIGN);
967 /* copy the packet from the receive buffer */
968 enc28j60_mem_read(priv,
969 rx_packet_start(priv->next_pk_ptr),
970 len, skb_put(skb, len));
971 if (netif_msg_pktdata(priv))
972 dump_packet(__func__, skb->len, skb->data);
973 skb->protocol = eth_type_trans(skb, ndev);
974 /* update statistics */
975 ndev->stats.rx_packets++;
976 ndev->stats.rx_bytes += len;
977 netif_rx(skb);
978 }
979 }
980 /*
981 * Move the RX read pointer to the start of the next
982 * received packet.
983 * This frees the memory we just read out.
984 */
985 erxrdpt = erxrdpt_workaround(next_packet, RXSTART_INIT, RXEND_INIT);
986 if (netif_msg_hw(priv))
987 dev_printk(KERN_DEBUG, dev, "%s() ERXRDPT:0x%04x\n",
988 __func__, erxrdpt);
989
990 mutex_lock(&priv->lock);
991 nolock_regw_write(priv, ERXRDPTL, erxrdpt);
992#ifdef CONFIG_ENC28J60_WRITEVERIFY
993 if (netif_msg_drv(priv)) {
994 u16 reg;
995 reg = nolock_regw_read(priv, ERXRDPTL);
996 if (reg != erxrdpt)
997 dev_printk(KERN_DEBUG, dev,
998 "%s() ERXRDPT verify error (0x%04x - 0x%04x)\n",
999 __func__, reg, erxrdpt);
1000 }
1001#endif
1002 priv->next_pk_ptr = next_packet;
1003 /* we are done with this packet, decrement the packet counter */
1004 nolock_reg_bfset(priv, ECON2, ECON2_PKTDEC);
1005 mutex_unlock(&priv->lock);
1006}
1007
1008/*
1009 * Calculate free space in RxFIFO
1010 */
1011static int enc28j60_get_free_rxfifo(struct enc28j60_net *priv)
1012{
1013 struct net_device *ndev = priv->netdev;
1014 int epkcnt, erxst, erxnd, erxwr, erxrd;
1015 int free_space;
1016
1017 mutex_lock(&priv->lock);
1018 epkcnt = nolock_regb_read(priv, EPKTCNT);
1019 if (epkcnt >= 255)
1020 free_space = -1;
1021 else {
1022 erxst = nolock_regw_read(priv, ERXSTL);
1023 erxnd = nolock_regw_read(priv, ERXNDL);
1024 erxwr = nolock_regw_read(priv, ERXWRPTL);
1025 erxrd = nolock_regw_read(priv, ERXRDPTL);
1026
1027 if (erxwr > erxrd)
1028 free_space = (erxnd - erxst) - (erxwr - erxrd);
1029 else if (erxwr == erxrd)
1030 free_space = (erxnd - erxst);
1031 else
1032 free_space = erxrd - erxwr - 1;
1033 }
1034 mutex_unlock(&priv->lock);
1035 if (netif_msg_rx_status(priv))
1036 netdev_printk(KERN_DEBUG, ndev, "%s() free_space = %d\n",
1037 __func__, free_space);
1038 return free_space;
1039}
1040
1041/*
1042 * Access the PHY to determine link status
1043 */
1044static void enc28j60_check_link_status(struct net_device *ndev)
1045{
1046 struct enc28j60_net *priv = netdev_priv(ndev);
1047 struct device *dev = &priv->spi->dev;
1048 u16 reg;
1049 int duplex;
1050
1051 reg = enc28j60_phy_read(priv, PHSTAT2);
1052 if (netif_msg_hw(priv))
1053 dev_printk(KERN_DEBUG, dev,
1054 "%s() PHSTAT1: %04x, PHSTAT2: %04x\n", __func__,
1055 enc28j60_phy_read(priv, PHSTAT1), reg);
1056 duplex = reg & PHSTAT2_DPXSTAT;
1057
1058 if (reg & PHSTAT2_LSTAT) {
1059 netif_carrier_on(ndev);
1060 if (netif_msg_ifup(priv))
1061 netdev_info(ndev, "link up - %s\n",
1062 duplex ? "Full duplex" : "Half duplex");
1063 } else {
1064 if (netif_msg_ifdown(priv))
1065 netdev_info(ndev, "link down\n");
1066 netif_carrier_off(ndev);
1067 }
1068}
1069
1070static void enc28j60_tx_clear(struct net_device *ndev, bool err)
1071{
1072 struct enc28j60_net *priv = netdev_priv(ndev);
1073
1074 if (err)
1075 ndev->stats.tx_errors++;
1076 else
1077 ndev->stats.tx_packets++;
1078
1079 if (priv->tx_skb) {
1080 if (!err)
1081 ndev->stats.tx_bytes += priv->tx_skb->len;
1082 dev_kfree_skb(priv->tx_skb);
1083 priv->tx_skb = NULL;
1084 }
1085 locked_reg_bfclr(priv, ECON1, ECON1_TXRTS);
1086 netif_wake_queue(ndev);
1087}
1088
1089/*
1090 * RX handler
1091 * Ignore PKTIF because is unreliable! (Look at the errata datasheet)
1092 * Check EPKTCNT is the suggested workaround.
1093 * We don't need to clear interrupt flag, automatically done when
1094 * enc28j60_hw_rx() decrements the packet counter.
1095 * Returns how many packet processed.
1096 */
1097static int enc28j60_rx_interrupt(struct net_device *ndev)
1098{
1099 struct enc28j60_net *priv = netdev_priv(ndev);
1100 int pk_counter, ret;
1101
1102 pk_counter = locked_regb_read(priv, EPKTCNT);
1103 if (pk_counter && netif_msg_intr(priv))
1104 netdev_printk(KERN_DEBUG, ndev, "intRX, pk_cnt: %d\n",
1105 pk_counter);
1106 if (pk_counter > priv->max_pk_counter) {
1107 /* update statistics */
1108 priv->max_pk_counter = pk_counter;
1109 if (netif_msg_rx_status(priv) && priv->max_pk_counter > 1)
1110 netdev_printk(KERN_DEBUG, ndev, "RX max_pk_cnt: %d\n",
1111 priv->max_pk_counter);
1112 }
1113 ret = pk_counter;
1114 while (pk_counter-- > 0)
1115 enc28j60_hw_rx(ndev);
1116
1117 return ret;
1118}
1119
1120static irqreturn_t enc28j60_irq(int irq, void *dev_id)
1121{
1122 struct enc28j60_net *priv = dev_id;
1123 struct net_device *ndev = priv->netdev;
1124 int intflags, loop;
1125
1126 /* disable further interrupts */
1127 locked_reg_bfclr(priv, EIE, EIE_INTIE);
1128
1129 do {
1130 loop = 0;
1131 intflags = locked_regb_read(priv, EIR);
1132 /* DMA interrupt handler (not currently used) */
1133 if ((intflags & EIR_DMAIF) != 0) {
1134 loop++;
1135 if (netif_msg_intr(priv))
1136 netdev_printk(KERN_DEBUG, ndev, "intDMA(%d)\n",
1137 loop);
1138 locked_reg_bfclr(priv, EIR, EIR_DMAIF);
1139 }
1140 /* LINK changed handler */
1141 if ((intflags & EIR_LINKIF) != 0) {
1142 loop++;
1143 if (netif_msg_intr(priv))
1144 netdev_printk(KERN_DEBUG, ndev, "intLINK(%d)\n",
1145 loop);
1146 enc28j60_check_link_status(ndev);
1147 /* read PHIR to clear the flag */
1148 enc28j60_phy_read(priv, PHIR);
1149 }
1150 /* TX complete handler */
1151 if (((intflags & EIR_TXIF) != 0) &&
1152 ((intflags & EIR_TXERIF) == 0)) {
1153 bool err = false;
1154 loop++;
1155 if (netif_msg_intr(priv))
1156 netdev_printk(KERN_DEBUG, ndev, "intTX(%d)\n",
1157 loop);
1158 priv->tx_retry_count = 0;
1159 if (locked_regb_read(priv, ESTAT) & ESTAT_TXABRT) {
1160 if (netif_msg_tx_err(priv))
1161 netdev_err(ndev, "Tx Error (aborted)\n");
1162 err = true;
1163 }
1164 if (netif_msg_tx_done(priv)) {
1165 u8 tsv[TSV_SIZE];
1166 enc28j60_read_tsv(priv, tsv);
1167 enc28j60_dump_tsv(priv, "Tx Done", tsv);
1168 }
1169 enc28j60_tx_clear(ndev, err);
1170 locked_reg_bfclr(priv, EIR, EIR_TXIF);
1171 }
1172 /* TX Error handler */
1173 if ((intflags & EIR_TXERIF) != 0) {
1174 u8 tsv[TSV_SIZE];
1175
1176 loop++;
1177 if (netif_msg_intr(priv))
1178 netdev_printk(KERN_DEBUG, ndev, "intTXErr(%d)\n",
1179 loop);
1180 locked_reg_bfclr(priv, ECON1, ECON1_TXRTS);
1181 enc28j60_read_tsv(priv, tsv);
1182 if (netif_msg_tx_err(priv))
1183 enc28j60_dump_tsv(priv, "Tx Error", tsv);
1184 /* Reset TX logic */
1185 mutex_lock(&priv->lock);
1186 nolock_reg_bfset(priv, ECON1, ECON1_TXRST);
1187 nolock_reg_bfclr(priv, ECON1, ECON1_TXRST);
1188 nolock_txfifo_init(priv, TXSTART_INIT, TXEND_INIT);
1189 mutex_unlock(&priv->lock);
1190 /* Transmit Late collision check for retransmit */
1191 if (TSV_GETBIT(tsv, TSV_TXLATECOLLISION)) {
1192 if (netif_msg_tx_err(priv))
1193 netdev_printk(KERN_DEBUG, ndev,
1194 "LateCollision TXErr (%d)\n",
1195 priv->tx_retry_count);
1196 if (priv->tx_retry_count++ < MAX_TX_RETRYCOUNT)
1197 locked_reg_bfset(priv, ECON1,
1198 ECON1_TXRTS);
1199 else
1200 enc28j60_tx_clear(ndev, true);
1201 } else
1202 enc28j60_tx_clear(ndev, true);
1203 locked_reg_bfclr(priv, EIR, EIR_TXERIF | EIR_TXIF);
1204 }
1205 /* RX Error handler */
1206 if ((intflags & EIR_RXERIF) != 0) {
1207 loop++;
1208 if (netif_msg_intr(priv))
1209 netdev_printk(KERN_DEBUG, ndev, "intRXErr(%d)\n",
1210 loop);
1211 /* Check free FIFO space to flag RX overrun */
1212 if (enc28j60_get_free_rxfifo(priv) <= 0) {
1213 if (netif_msg_rx_err(priv))
1214 netdev_printk(KERN_DEBUG, ndev, "RX Overrun\n");
1215 ndev->stats.rx_dropped++;
1216 }
1217 locked_reg_bfclr(priv, EIR, EIR_RXERIF);
1218 }
1219 /* RX handler */
1220 if (enc28j60_rx_interrupt(ndev))
1221 loop++;
1222 } while (loop);
1223
1224 /* re-enable interrupts */
1225 locked_reg_bfset(priv, EIE, EIE_INTIE);
1226
1227 return IRQ_HANDLED;
1228}
1229
1230/*
1231 * Hardware transmit function.
1232 * Fill the buffer memory and send the contents of the transmit buffer
1233 * onto the network
1234 */
1235static void enc28j60_hw_tx(struct enc28j60_net *priv)
1236{
1237 struct net_device *ndev = priv->netdev;
1238
1239 BUG_ON(!priv->tx_skb);
1240
1241 if (netif_msg_tx_queued(priv))
1242 netdev_printk(KERN_DEBUG, ndev, "Tx Packet Len:%d\n",
1243 priv->tx_skb->len);
1244
1245 if (netif_msg_pktdata(priv))
1246 dump_packet(__func__,
1247 priv->tx_skb->len, priv->tx_skb->data);
1248 enc28j60_packet_write(priv, priv->tx_skb->len, priv->tx_skb->data);
1249
1250#ifdef CONFIG_ENC28J60_WRITEVERIFY
1251 /* readback and verify written data */
1252 if (netif_msg_drv(priv)) {
1253 struct device *dev = &priv->spi->dev;
1254 int test_len, k;
1255 u8 test_buf[64]; /* limit the test to the first 64 bytes */
1256 int okflag;
1257
1258 test_len = priv->tx_skb->len;
1259 if (test_len > sizeof(test_buf))
1260 test_len = sizeof(test_buf);
1261
1262 /* + 1 to skip control byte */
1263 enc28j60_mem_read(priv, TXSTART_INIT + 1, test_len, test_buf);
1264 okflag = 1;
1265 for (k = 0; k < test_len; k++) {
1266 if (priv->tx_skb->data[k] != test_buf[k]) {
1267 dev_printk(KERN_DEBUG, dev,
1268 "Error, %d location differ: 0x%02x-0x%02x\n",
1269 k, priv->tx_skb->data[k], test_buf[k]);
1270 okflag = 0;
1271 }
1272 }
1273 if (!okflag)
1274 dev_printk(KERN_DEBUG, dev, "Tx write buffer, verify ERROR!\n");
1275 }
1276#endif
1277 /* set TX request flag */
1278 locked_reg_bfset(priv, ECON1, ECON1_TXRTS);
1279}
1280
1281static netdev_tx_t enc28j60_send_packet(struct sk_buff *skb,
1282 struct net_device *dev)
1283{
1284 struct enc28j60_net *priv = netdev_priv(dev);
1285
1286 /* If some error occurs while trying to transmit this
1287 * packet, you should return '1' from this function.
1288 * In such a case you _may not_ do anything to the
1289 * SKB, it is still owned by the network queueing
1290 * layer when an error is returned. This means you
1291 * may not modify any SKB fields, you may not free
1292 * the SKB, etc.
1293 */
1294 netif_stop_queue(dev);
1295
1296 /* Remember the skb for deferred processing */
1297 priv->tx_skb = skb;
1298 schedule_work(&priv->tx_work);
1299
1300 return NETDEV_TX_OK;
1301}
1302
1303static void enc28j60_tx_work_handler(struct work_struct *work)
1304{
1305 struct enc28j60_net *priv =
1306 container_of(work, struct enc28j60_net, tx_work);
1307
1308 /* actual delivery of data */
1309 enc28j60_hw_tx(priv);
1310}
1311
1312static void enc28j60_tx_timeout(struct net_device *ndev, unsigned int txqueue)
1313{
1314 struct enc28j60_net *priv = netdev_priv(ndev);
1315
1316 if (netif_msg_timer(priv))
1317 netdev_err(ndev, "tx timeout\n");
1318
1319 ndev->stats.tx_errors++;
1320 /* can't restart safely under softirq */
1321 schedule_work(&priv->restart_work);
1322}
1323
1324/*
1325 * Open/initialize the board. This is called (in the current kernel)
1326 * sometime after booting when the 'ifconfig' program is run.
1327 *
1328 * This routine should set everything up anew at each open, even
1329 * registers that "should" only need to be set once at boot, so that
1330 * there is non-reboot way to recover if something goes wrong.
1331 */
1332static int enc28j60_net_open(struct net_device *dev)
1333{
1334 struct enc28j60_net *priv = netdev_priv(dev);
1335
1336 if (!is_valid_ether_addr(dev->dev_addr)) {
1337 if (netif_msg_ifup(priv))
1338 netdev_err(dev, "invalid MAC address %pM\n", dev->dev_addr);
1339 return -EADDRNOTAVAIL;
1340 }
1341 /* Reset the hardware here (and take it out of low power mode) */
1342 enc28j60_lowpower(priv, false);
1343 enc28j60_hw_disable(priv);
1344 if (!enc28j60_hw_init(priv)) {
1345 if (netif_msg_ifup(priv))
1346 netdev_err(dev, "hw_reset() failed\n");
1347 return -EINVAL;
1348 }
1349 /* Update the MAC address (in case user has changed it) */
1350 enc28j60_set_hw_macaddr(dev);
1351 /* Enable interrupts */
1352 enc28j60_hw_enable(priv);
1353 /* check link status */
1354 enc28j60_check_link_status(dev);
1355 /* We are now ready to accept transmit requests from
1356 * the queueing layer of the networking.
1357 */
1358 netif_start_queue(dev);
1359
1360 return 0;
1361}
1362
1363/* The inverse routine to net_open(). */
1364static int enc28j60_net_close(struct net_device *dev)
1365{
1366 struct enc28j60_net *priv = netdev_priv(dev);
1367
1368 enc28j60_hw_disable(priv);
1369 enc28j60_lowpower(priv, true);
1370 netif_stop_queue(dev);
1371
1372 return 0;
1373}
1374
1375/*
1376 * Set or clear the multicast filter for this adapter
1377 * num_addrs == -1 Promiscuous mode, receive all packets
1378 * num_addrs == 0 Normal mode, filter out multicast packets
1379 * num_addrs > 0 Multicast mode, receive normal and MC packets
1380 */
1381static void enc28j60_set_multicast_list(struct net_device *dev)
1382{
1383 struct enc28j60_net *priv = netdev_priv(dev);
1384 int oldfilter = priv->rxfilter;
1385
1386 if (dev->flags & IFF_PROMISC) {
1387 if (netif_msg_link(priv))
1388 netdev_info(dev, "promiscuous mode\n");
1389 priv->rxfilter = RXFILTER_PROMISC;
1390 } else if ((dev->flags & IFF_ALLMULTI) || !netdev_mc_empty(dev)) {
1391 if (netif_msg_link(priv))
1392 netdev_info(dev, "%smulticast mode\n",
1393 (dev->flags & IFF_ALLMULTI) ? "all-" : "");
1394 priv->rxfilter = RXFILTER_MULTI;
1395 } else {
1396 if (netif_msg_link(priv))
1397 netdev_info(dev, "normal mode\n");
1398 priv->rxfilter = RXFILTER_NORMAL;
1399 }
1400
1401 if (oldfilter != priv->rxfilter)
1402 schedule_work(&priv->setrx_work);
1403}
1404
1405static void enc28j60_setrx_work_handler(struct work_struct *work)
1406{
1407 struct enc28j60_net *priv =
1408 container_of(work, struct enc28j60_net, setrx_work);
1409 struct device *dev = &priv->spi->dev;
1410
1411 if (priv->rxfilter == RXFILTER_PROMISC) {
1412 if (netif_msg_drv(priv))
1413 dev_printk(KERN_DEBUG, dev, "promiscuous mode\n");
1414 locked_regb_write(priv, ERXFCON, 0x00);
1415 } else if (priv->rxfilter == RXFILTER_MULTI) {
1416 if (netif_msg_drv(priv))
1417 dev_printk(KERN_DEBUG, dev, "multicast mode\n");
1418 locked_regb_write(priv, ERXFCON,
1419 ERXFCON_UCEN | ERXFCON_CRCEN |
1420 ERXFCON_BCEN | ERXFCON_MCEN);
1421 } else {
1422 if (netif_msg_drv(priv))
1423 dev_printk(KERN_DEBUG, dev, "normal mode\n");
1424 locked_regb_write(priv, ERXFCON,
1425 ERXFCON_UCEN | ERXFCON_CRCEN |
1426 ERXFCON_BCEN);
1427 }
1428}
1429
1430static void enc28j60_restart_work_handler(struct work_struct *work)
1431{
1432 struct enc28j60_net *priv =
1433 container_of(work, struct enc28j60_net, restart_work);
1434 struct net_device *ndev = priv->netdev;
1435 int ret;
1436
1437 rtnl_lock();
1438 if (netif_running(ndev)) {
1439 enc28j60_net_close(ndev);
1440 ret = enc28j60_net_open(ndev);
1441 if (unlikely(ret)) {
1442 netdev_info(ndev, "could not restart %d\n", ret);
1443 dev_close(ndev);
1444 }
1445 }
1446 rtnl_unlock();
1447}
1448
1449/* ......................... ETHTOOL SUPPORT ........................... */
1450
1451static void
1452enc28j60_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1453{
1454 strscpy(info->driver, DRV_NAME, sizeof(info->driver));
1455 strscpy(info->version, DRV_VERSION, sizeof(info->version));
1456 strscpy(info->bus_info,
1457 dev_name(dev->dev.parent), sizeof(info->bus_info));
1458}
1459
1460static int
1461enc28j60_get_link_ksettings(struct net_device *dev,
1462 struct ethtool_link_ksettings *cmd)
1463{
1464 struct enc28j60_net *priv = netdev_priv(dev);
1465
1466 ethtool_link_ksettings_zero_link_mode(cmd, supported);
1467 ethtool_link_ksettings_add_link_mode(cmd, supported, 10baseT_Half);
1468 ethtool_link_ksettings_add_link_mode(cmd, supported, 10baseT_Full);
1469 ethtool_link_ksettings_add_link_mode(cmd, supported, TP);
1470
1471 cmd->base.speed = SPEED_10;
1472 cmd->base.duplex = priv->full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
1473 cmd->base.port = PORT_TP;
1474 cmd->base.autoneg = AUTONEG_DISABLE;
1475
1476 return 0;
1477}
1478
1479static int
1480enc28j60_set_link_ksettings(struct net_device *dev,
1481 const struct ethtool_link_ksettings *cmd)
1482{
1483 return enc28j60_setlink(dev, cmd->base.autoneg,
1484 cmd->base.speed, cmd->base.duplex);
1485}
1486
1487static u32 enc28j60_get_msglevel(struct net_device *dev)
1488{
1489 struct enc28j60_net *priv = netdev_priv(dev);
1490 return priv->msg_enable;
1491}
1492
1493static void enc28j60_set_msglevel(struct net_device *dev, u32 val)
1494{
1495 struct enc28j60_net *priv = netdev_priv(dev);
1496 priv->msg_enable = val;
1497}
1498
1499static const struct ethtool_ops enc28j60_ethtool_ops = {
1500 .get_drvinfo = enc28j60_get_drvinfo,
1501 .get_msglevel = enc28j60_get_msglevel,
1502 .set_msglevel = enc28j60_set_msglevel,
1503 .get_link_ksettings = enc28j60_get_link_ksettings,
1504 .set_link_ksettings = enc28j60_set_link_ksettings,
1505};
1506
1507static int enc28j60_chipset_init(struct net_device *dev)
1508{
1509 struct enc28j60_net *priv = netdev_priv(dev);
1510
1511 return enc28j60_hw_init(priv);
1512}
1513
1514static const struct net_device_ops enc28j60_netdev_ops = {
1515 .ndo_open = enc28j60_net_open,
1516 .ndo_stop = enc28j60_net_close,
1517 .ndo_start_xmit = enc28j60_send_packet,
1518 .ndo_set_rx_mode = enc28j60_set_multicast_list,
1519 .ndo_set_mac_address = enc28j60_set_mac_address,
1520 .ndo_tx_timeout = enc28j60_tx_timeout,
1521 .ndo_validate_addr = eth_validate_addr,
1522};
1523
1524static int enc28j60_probe(struct spi_device *spi)
1525{
1526 struct net_device *dev;
1527 struct enc28j60_net *priv;
1528 int ret = 0;
1529
1530 if (netif_msg_drv(&debug))
1531 dev_info(&spi->dev, "Ethernet driver %s loaded\n", DRV_VERSION);
1532
1533 dev = alloc_etherdev(sizeof(struct enc28j60_net));
1534 if (!dev) {
1535 ret = -ENOMEM;
1536 goto error_alloc;
1537 }
1538 priv = netdev_priv(dev);
1539
1540 priv->netdev = dev; /* priv to netdev reference */
1541 priv->spi = spi; /* priv to spi reference */
1542 priv->msg_enable = netif_msg_init(debug.msg_enable, ENC28J60_MSG_DEFAULT);
1543 mutex_init(&priv->lock);
1544 INIT_WORK(&priv->tx_work, enc28j60_tx_work_handler);
1545 INIT_WORK(&priv->setrx_work, enc28j60_setrx_work_handler);
1546 INIT_WORK(&priv->restart_work, enc28j60_restart_work_handler);
1547 spi_set_drvdata(spi, priv); /* spi to priv reference */
1548 SET_NETDEV_DEV(dev, &spi->dev);
1549
1550 if (!enc28j60_chipset_init(dev)) {
1551 if (netif_msg_probe(priv))
1552 dev_info(&spi->dev, "chip not found\n");
1553 ret = -EIO;
1554 goto error_irq;
1555 }
1556
1557 if (device_get_ethdev_address(&spi->dev, dev))
1558 eth_hw_addr_random(dev);
1559 enc28j60_set_hw_macaddr(dev);
1560
1561 /* Board setup must set the relevant edge trigger type;
1562 * level triggers won't currently work.
1563 */
1564 ret = request_threaded_irq(spi->irq, NULL, enc28j60_irq, IRQF_ONESHOT,
1565 DRV_NAME, priv);
1566 if (ret < 0) {
1567 if (netif_msg_probe(priv))
1568 dev_err(&spi->dev, "request irq %d failed (ret = %d)\n",
1569 spi->irq, ret);
1570 goto error_irq;
1571 }
1572
1573 dev->if_port = IF_PORT_10BASET;
1574 dev->irq = spi->irq;
1575 dev->netdev_ops = &enc28j60_netdev_ops;
1576 dev->watchdog_timeo = TX_TIMEOUT;
1577 dev->ethtool_ops = &enc28j60_ethtool_ops;
1578
1579 enc28j60_lowpower(priv, true);
1580
1581 ret = register_netdev(dev);
1582 if (ret) {
1583 if (netif_msg_probe(priv))
1584 dev_err(&spi->dev, "register netdev failed (ret = %d)\n",
1585 ret);
1586 goto error_register;
1587 }
1588
1589 return 0;
1590
1591error_register:
1592 free_irq(spi->irq, priv);
1593error_irq:
1594 free_netdev(dev);
1595error_alloc:
1596 return ret;
1597}
1598
1599static void enc28j60_remove(struct spi_device *spi)
1600{
1601 struct enc28j60_net *priv = spi_get_drvdata(spi);
1602
1603 unregister_netdev(priv->netdev);
1604 free_irq(spi->irq, priv);
1605 free_netdev(priv->netdev);
1606}
1607
1608static const struct of_device_id enc28j60_dt_ids[] = {
1609 { .compatible = "microchip,enc28j60" },
1610 { /* sentinel */ }
1611};
1612MODULE_DEVICE_TABLE(of, enc28j60_dt_ids);
1613
1614static struct spi_driver enc28j60_driver = {
1615 .driver = {
1616 .name = DRV_NAME,
1617 .of_match_table = enc28j60_dt_ids,
1618 },
1619 .probe = enc28j60_probe,
1620 .remove = enc28j60_remove,
1621};
1622module_spi_driver(enc28j60_driver);
1623
1624MODULE_DESCRIPTION(DRV_NAME " ethernet driver");
1625MODULE_AUTHOR("Claudio Lanconelli <lanconelli.claudio@eptar.com>");
1626MODULE_LICENSE("GPL");
1627module_param_named(debug, debug.msg_enable, int, 0);
1628MODULE_PARM_DESC(debug, "Debug verbosity level in amount of bits set (0=none, ..., 31=all)");
1629MODULE_ALIAS("spi:" DRV_NAME);
1/*
2 * Microchip ENC28J60 ethernet driver (MAC + PHY)
3 *
4 * Copyright (C) 2007 Eurek srl
5 * Author: Claudio Lanconelli <lanconelli.claudio@eptar.com>
6 * based on enc28j60.c written by David Anders for 2.4 kernel version
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * $Id: enc28j60.c,v 1.22 2007/12/20 10:47:01 claudio Exp $
14 */
15
16#include <linux/module.h>
17#include <linux/kernel.h>
18#include <linux/types.h>
19#include <linux/fcntl.h>
20#include <linux/interrupt.h>
21#include <linux/string.h>
22#include <linux/errno.h>
23#include <linux/init.h>
24#include <linux/netdevice.h>
25#include <linux/etherdevice.h>
26#include <linux/ethtool.h>
27#include <linux/tcp.h>
28#include <linux/skbuff.h>
29#include <linux/delay.h>
30#include <linux/spi/spi.h>
31
32#include "enc28j60_hw.h"
33
34#define DRV_NAME "enc28j60"
35#define DRV_VERSION "1.01"
36
37#define SPI_OPLEN 1
38
39#define ENC28J60_MSG_DEFAULT \
40 (NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN | NETIF_MSG_LINK)
41
42/* Buffer size required for the largest SPI transfer (i.e., reading a
43 * frame). */
44#define SPI_TRANSFER_BUF_LEN (4 + MAX_FRAMELEN)
45
46#define TX_TIMEOUT (4 * HZ)
47
48/* Max TX retries in case of collision as suggested by errata datasheet */
49#define MAX_TX_RETRYCOUNT 16
50
51enum {
52 RXFILTER_NORMAL,
53 RXFILTER_MULTI,
54 RXFILTER_PROMISC
55};
56
57/* Driver local data */
58struct enc28j60_net {
59 struct net_device *netdev;
60 struct spi_device *spi;
61 struct mutex lock;
62 struct sk_buff *tx_skb;
63 struct work_struct tx_work;
64 struct work_struct irq_work;
65 struct work_struct setrx_work;
66 struct work_struct restart_work;
67 u8 bank; /* current register bank selected */
68 u16 next_pk_ptr; /* next packet pointer within FIFO */
69 u16 max_pk_counter; /* statistics: max packet counter */
70 u16 tx_retry_count;
71 bool hw_enable;
72 bool full_duplex;
73 int rxfilter;
74 u32 msg_enable;
75 u8 spi_transfer_buf[SPI_TRANSFER_BUF_LEN];
76};
77
78/* use ethtool to change the level for any given device */
79static struct {
80 u32 msg_enable;
81} debug = { -1 };
82
83/*
84 * SPI read buffer
85 * wait for the SPI transfer and copy received data to destination
86 */
87static int
88spi_read_buf(struct enc28j60_net *priv, int len, u8 *data)
89{
90 u8 *rx_buf = priv->spi_transfer_buf + 4;
91 u8 *tx_buf = priv->spi_transfer_buf;
92 struct spi_transfer t = {
93 .tx_buf = tx_buf,
94 .rx_buf = rx_buf,
95 .len = SPI_OPLEN + len,
96 };
97 struct spi_message msg;
98 int ret;
99
100 tx_buf[0] = ENC28J60_READ_BUF_MEM;
101 tx_buf[1] = tx_buf[2] = tx_buf[3] = 0; /* don't care */
102
103 spi_message_init(&msg);
104 spi_message_add_tail(&t, &msg);
105 ret = spi_sync(priv->spi, &msg);
106 if (ret == 0) {
107 memcpy(data, &rx_buf[SPI_OPLEN], len);
108 ret = msg.status;
109 }
110 if (ret && netif_msg_drv(priv))
111 printk(KERN_DEBUG DRV_NAME ": %s() failed: ret = %d\n",
112 __func__, ret);
113
114 return ret;
115}
116
117/*
118 * SPI write buffer
119 */
120static int spi_write_buf(struct enc28j60_net *priv, int len,
121 const u8 *data)
122{
123 int ret;
124
125 if (len > SPI_TRANSFER_BUF_LEN - 1 || len <= 0)
126 ret = -EINVAL;
127 else {
128 priv->spi_transfer_buf[0] = ENC28J60_WRITE_BUF_MEM;
129 memcpy(&priv->spi_transfer_buf[1], data, len);
130 ret = spi_write(priv->spi, priv->spi_transfer_buf, len + 1);
131 if (ret && netif_msg_drv(priv))
132 printk(KERN_DEBUG DRV_NAME ": %s() failed: ret = %d\n",
133 __func__, ret);
134 }
135 return ret;
136}
137
138/*
139 * basic SPI read operation
140 */
141static u8 spi_read_op(struct enc28j60_net *priv, u8 op,
142 u8 addr)
143{
144 u8 tx_buf[2];
145 u8 rx_buf[4];
146 u8 val = 0;
147 int ret;
148 int slen = SPI_OPLEN;
149
150 /* do dummy read if needed */
151 if (addr & SPRD_MASK)
152 slen++;
153
154 tx_buf[0] = op | (addr & ADDR_MASK);
155 ret = spi_write_then_read(priv->spi, tx_buf, 1, rx_buf, slen);
156 if (ret)
157 printk(KERN_DEBUG DRV_NAME ": %s() failed: ret = %d\n",
158 __func__, ret);
159 else
160 val = rx_buf[slen - 1];
161
162 return val;
163}
164
165/*
166 * basic SPI write operation
167 */
168static int spi_write_op(struct enc28j60_net *priv, u8 op,
169 u8 addr, u8 val)
170{
171 int ret;
172
173 priv->spi_transfer_buf[0] = op | (addr & ADDR_MASK);
174 priv->spi_transfer_buf[1] = val;
175 ret = spi_write(priv->spi, priv->spi_transfer_buf, 2);
176 if (ret && netif_msg_drv(priv))
177 printk(KERN_DEBUG DRV_NAME ": %s() failed: ret = %d\n",
178 __func__, ret);
179 return ret;
180}
181
182static void enc28j60_soft_reset(struct enc28j60_net *priv)
183{
184 if (netif_msg_hw(priv))
185 printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __func__);
186
187 spi_write_op(priv, ENC28J60_SOFT_RESET, 0, ENC28J60_SOFT_RESET);
188 /* Errata workaround #1, CLKRDY check is unreliable,
189 * delay at least 1 mS instead */
190 udelay(2000);
191}
192
193/*
194 * select the current register bank if necessary
195 */
196static void enc28j60_set_bank(struct enc28j60_net *priv, u8 addr)
197{
198 u8 b = (addr & BANK_MASK) >> 5;
199
200 /* These registers (EIE, EIR, ESTAT, ECON2, ECON1)
201 * are present in all banks, no need to switch bank
202 */
203 if (addr >= EIE && addr <= ECON1)
204 return;
205
206 /* Clear or set each bank selection bit as needed */
207 if ((b & ECON1_BSEL0) != (priv->bank & ECON1_BSEL0)) {
208 if (b & ECON1_BSEL0)
209 spi_write_op(priv, ENC28J60_BIT_FIELD_SET, ECON1,
210 ECON1_BSEL0);
211 else
212 spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, ECON1,
213 ECON1_BSEL0);
214 }
215 if ((b & ECON1_BSEL1) != (priv->bank & ECON1_BSEL1)) {
216 if (b & ECON1_BSEL1)
217 spi_write_op(priv, ENC28J60_BIT_FIELD_SET, ECON1,
218 ECON1_BSEL1);
219 else
220 spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, ECON1,
221 ECON1_BSEL1);
222 }
223 priv->bank = b;
224}
225
226/*
227 * Register access routines through the SPI bus.
228 * Every register access comes in two flavours:
229 * - nolock_xxx: caller needs to invoke mutex_lock, usually to access
230 * atomically more than one register
231 * - locked_xxx: caller doesn't need to invoke mutex_lock, single access
232 *
233 * Some registers can be accessed through the bit field clear and
234 * bit field set to avoid a read modify write cycle.
235 */
236
237/*
238 * Register bit field Set
239 */
240static void nolock_reg_bfset(struct enc28j60_net *priv,
241 u8 addr, u8 mask)
242{
243 enc28j60_set_bank(priv, addr);
244 spi_write_op(priv, ENC28J60_BIT_FIELD_SET, addr, mask);
245}
246
247static void locked_reg_bfset(struct enc28j60_net *priv,
248 u8 addr, u8 mask)
249{
250 mutex_lock(&priv->lock);
251 nolock_reg_bfset(priv, addr, mask);
252 mutex_unlock(&priv->lock);
253}
254
255/*
256 * Register bit field Clear
257 */
258static void nolock_reg_bfclr(struct enc28j60_net *priv,
259 u8 addr, u8 mask)
260{
261 enc28j60_set_bank(priv, addr);
262 spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, addr, mask);
263}
264
265static void locked_reg_bfclr(struct enc28j60_net *priv,
266 u8 addr, u8 mask)
267{
268 mutex_lock(&priv->lock);
269 nolock_reg_bfclr(priv, addr, mask);
270 mutex_unlock(&priv->lock);
271}
272
273/*
274 * Register byte read
275 */
276static int nolock_regb_read(struct enc28j60_net *priv,
277 u8 address)
278{
279 enc28j60_set_bank(priv, address);
280 return spi_read_op(priv, ENC28J60_READ_CTRL_REG, address);
281}
282
283static int locked_regb_read(struct enc28j60_net *priv,
284 u8 address)
285{
286 int ret;
287
288 mutex_lock(&priv->lock);
289 ret = nolock_regb_read(priv, address);
290 mutex_unlock(&priv->lock);
291
292 return ret;
293}
294
295/*
296 * Register word read
297 */
298static int nolock_regw_read(struct enc28j60_net *priv,
299 u8 address)
300{
301 int rl, rh;
302
303 enc28j60_set_bank(priv, address);
304 rl = spi_read_op(priv, ENC28J60_READ_CTRL_REG, address);
305 rh = spi_read_op(priv, ENC28J60_READ_CTRL_REG, address + 1);
306
307 return (rh << 8) | rl;
308}
309
310static int locked_regw_read(struct enc28j60_net *priv,
311 u8 address)
312{
313 int ret;
314
315 mutex_lock(&priv->lock);
316 ret = nolock_regw_read(priv, address);
317 mutex_unlock(&priv->lock);
318
319 return ret;
320}
321
322/*
323 * Register byte write
324 */
325static void nolock_regb_write(struct enc28j60_net *priv,
326 u8 address, u8 data)
327{
328 enc28j60_set_bank(priv, address);
329 spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, address, data);
330}
331
332static void locked_regb_write(struct enc28j60_net *priv,
333 u8 address, u8 data)
334{
335 mutex_lock(&priv->lock);
336 nolock_regb_write(priv, address, data);
337 mutex_unlock(&priv->lock);
338}
339
340/*
341 * Register word write
342 */
343static void nolock_regw_write(struct enc28j60_net *priv,
344 u8 address, u16 data)
345{
346 enc28j60_set_bank(priv, address);
347 spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, address, (u8) data);
348 spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, address + 1,
349 (u8) (data >> 8));
350}
351
352static void locked_regw_write(struct enc28j60_net *priv,
353 u8 address, u16 data)
354{
355 mutex_lock(&priv->lock);
356 nolock_regw_write(priv, address, data);
357 mutex_unlock(&priv->lock);
358}
359
360/*
361 * Buffer memory read
362 * Select the starting address and execute a SPI buffer read
363 */
364static void enc28j60_mem_read(struct enc28j60_net *priv,
365 u16 addr, int len, u8 *data)
366{
367 mutex_lock(&priv->lock);
368 nolock_regw_write(priv, ERDPTL, addr);
369#ifdef CONFIG_ENC28J60_WRITEVERIFY
370 if (netif_msg_drv(priv)) {
371 u16 reg;
372 reg = nolock_regw_read(priv, ERDPTL);
373 if (reg != addr)
374 printk(KERN_DEBUG DRV_NAME ": %s() error writing ERDPT "
375 "(0x%04x - 0x%04x)\n", __func__, reg, addr);
376 }
377#endif
378 spi_read_buf(priv, len, data);
379 mutex_unlock(&priv->lock);
380}
381
382/*
383 * Write packet to enc28j60 TX buffer memory
384 */
385static void
386enc28j60_packet_write(struct enc28j60_net *priv, int len, const u8 *data)
387{
388 mutex_lock(&priv->lock);
389 /* Set the write pointer to start of transmit buffer area */
390 nolock_regw_write(priv, EWRPTL, TXSTART_INIT);
391#ifdef CONFIG_ENC28J60_WRITEVERIFY
392 if (netif_msg_drv(priv)) {
393 u16 reg;
394 reg = nolock_regw_read(priv, EWRPTL);
395 if (reg != TXSTART_INIT)
396 printk(KERN_DEBUG DRV_NAME
397 ": %s() ERWPT:0x%04x != 0x%04x\n",
398 __func__, reg, TXSTART_INIT);
399 }
400#endif
401 /* Set the TXND pointer to correspond to the packet size given */
402 nolock_regw_write(priv, ETXNDL, TXSTART_INIT + len);
403 /* write per-packet control byte */
404 spi_write_op(priv, ENC28J60_WRITE_BUF_MEM, 0, 0x00);
405 if (netif_msg_hw(priv))
406 printk(KERN_DEBUG DRV_NAME
407 ": %s() after control byte ERWPT:0x%04x\n",
408 __func__, nolock_regw_read(priv, EWRPTL));
409 /* copy the packet into the transmit buffer */
410 spi_write_buf(priv, len, data);
411 if (netif_msg_hw(priv))
412 printk(KERN_DEBUG DRV_NAME
413 ": %s() after write packet ERWPT:0x%04x, len=%d\n",
414 __func__, nolock_regw_read(priv, EWRPTL), len);
415 mutex_unlock(&priv->lock);
416}
417
418static unsigned long msec20_to_jiffies;
419
420static int poll_ready(struct enc28j60_net *priv, u8 reg, u8 mask, u8 val)
421{
422 unsigned long timeout = jiffies + msec20_to_jiffies;
423
424 /* 20 msec timeout read */
425 while ((nolock_regb_read(priv, reg) & mask) != val) {
426 if (time_after(jiffies, timeout)) {
427 if (netif_msg_drv(priv))
428 dev_dbg(&priv->spi->dev,
429 "reg %02x ready timeout!\n", reg);
430 return -ETIMEDOUT;
431 }
432 cpu_relax();
433 }
434 return 0;
435}
436
437/*
438 * Wait until the PHY operation is complete.
439 */
440static int wait_phy_ready(struct enc28j60_net *priv)
441{
442 return poll_ready(priv, MISTAT, MISTAT_BUSY, 0) ? 0 : 1;
443}
444
445/*
446 * PHY register read
447 * PHY registers are not accessed directly, but through the MII
448 */
449static u16 enc28j60_phy_read(struct enc28j60_net *priv, u8 address)
450{
451 u16 ret;
452
453 mutex_lock(&priv->lock);
454 /* set the PHY register address */
455 nolock_regb_write(priv, MIREGADR, address);
456 /* start the register read operation */
457 nolock_regb_write(priv, MICMD, MICMD_MIIRD);
458 /* wait until the PHY read completes */
459 wait_phy_ready(priv);
460 /* quit reading */
461 nolock_regb_write(priv, MICMD, 0x00);
462 /* return the data */
463 ret = nolock_regw_read(priv, MIRDL);
464 mutex_unlock(&priv->lock);
465
466 return ret;
467}
468
469static int enc28j60_phy_write(struct enc28j60_net *priv, u8 address, u16 data)
470{
471 int ret;
472
473 mutex_lock(&priv->lock);
474 /* set the PHY register address */
475 nolock_regb_write(priv, MIREGADR, address);
476 /* write the PHY data */
477 nolock_regw_write(priv, MIWRL, data);
478 /* wait until the PHY write completes and return */
479 ret = wait_phy_ready(priv);
480 mutex_unlock(&priv->lock);
481
482 return ret;
483}
484
485/*
486 * Program the hardware MAC address from dev->dev_addr.
487 */
488static int enc28j60_set_hw_macaddr(struct net_device *ndev)
489{
490 int ret;
491 struct enc28j60_net *priv = netdev_priv(ndev);
492
493 mutex_lock(&priv->lock);
494 if (!priv->hw_enable) {
495 if (netif_msg_drv(priv))
496 printk(KERN_INFO DRV_NAME
497 ": %s: Setting MAC address to %pM\n",
498 ndev->name, ndev->dev_addr);
499 /* NOTE: MAC address in ENC28J60 is byte-backward */
500 nolock_regb_write(priv, MAADR5, ndev->dev_addr[0]);
501 nolock_regb_write(priv, MAADR4, ndev->dev_addr[1]);
502 nolock_regb_write(priv, MAADR3, ndev->dev_addr[2]);
503 nolock_regb_write(priv, MAADR2, ndev->dev_addr[3]);
504 nolock_regb_write(priv, MAADR1, ndev->dev_addr[4]);
505 nolock_regb_write(priv, MAADR0, ndev->dev_addr[5]);
506 ret = 0;
507 } else {
508 if (netif_msg_drv(priv))
509 printk(KERN_DEBUG DRV_NAME
510 ": %s() Hardware must be disabled to set "
511 "Mac address\n", __func__);
512 ret = -EBUSY;
513 }
514 mutex_unlock(&priv->lock);
515 return ret;
516}
517
518/*
519 * Store the new hardware address in dev->dev_addr, and update the MAC.
520 */
521static int enc28j60_set_mac_address(struct net_device *dev, void *addr)
522{
523 struct sockaddr *address = addr;
524
525 if (netif_running(dev))
526 return -EBUSY;
527 if (!is_valid_ether_addr(address->sa_data))
528 return -EADDRNOTAVAIL;
529
530 memcpy(dev->dev_addr, address->sa_data, dev->addr_len);
531 return enc28j60_set_hw_macaddr(dev);
532}
533
534/*
535 * Debug routine to dump useful register contents
536 */
537static void enc28j60_dump_regs(struct enc28j60_net *priv, const char *msg)
538{
539 mutex_lock(&priv->lock);
540 printk(KERN_DEBUG DRV_NAME " %s\n"
541 "HwRevID: 0x%02x\n"
542 "Cntrl: ECON1 ECON2 ESTAT EIR EIE\n"
543 " 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x\n"
544 "MAC : MACON1 MACON3 MACON4\n"
545 " 0x%02x 0x%02x 0x%02x\n"
546 "Rx : ERXST ERXND ERXWRPT ERXRDPT ERXFCON EPKTCNT MAMXFL\n"
547 " 0x%04x 0x%04x 0x%04x 0x%04x "
548 "0x%02x 0x%02x 0x%04x\n"
549 "Tx : ETXST ETXND MACLCON1 MACLCON2 MAPHSUP\n"
550 " 0x%04x 0x%04x 0x%02x 0x%02x 0x%02x\n",
551 msg, nolock_regb_read(priv, EREVID),
552 nolock_regb_read(priv, ECON1), nolock_regb_read(priv, ECON2),
553 nolock_regb_read(priv, ESTAT), nolock_regb_read(priv, EIR),
554 nolock_regb_read(priv, EIE), nolock_regb_read(priv, MACON1),
555 nolock_regb_read(priv, MACON3), nolock_regb_read(priv, MACON4),
556 nolock_regw_read(priv, ERXSTL), nolock_regw_read(priv, ERXNDL),
557 nolock_regw_read(priv, ERXWRPTL),
558 nolock_regw_read(priv, ERXRDPTL),
559 nolock_regb_read(priv, ERXFCON),
560 nolock_regb_read(priv, EPKTCNT),
561 nolock_regw_read(priv, MAMXFLL), nolock_regw_read(priv, ETXSTL),
562 nolock_regw_read(priv, ETXNDL),
563 nolock_regb_read(priv, MACLCON1),
564 nolock_regb_read(priv, MACLCON2),
565 nolock_regb_read(priv, MAPHSUP));
566 mutex_unlock(&priv->lock);
567}
568
569/*
570 * ERXRDPT need to be set always at odd addresses, refer to errata datasheet
571 */
572static u16 erxrdpt_workaround(u16 next_packet_ptr, u16 start, u16 end)
573{
574 u16 erxrdpt;
575
576 if ((next_packet_ptr - 1 < start) || (next_packet_ptr - 1 > end))
577 erxrdpt = end;
578 else
579 erxrdpt = next_packet_ptr - 1;
580
581 return erxrdpt;
582}
583
584/*
585 * Calculate wrap around when reading beyond the end of the RX buffer
586 */
587static u16 rx_packet_start(u16 ptr)
588{
589 if (ptr + RSV_SIZE > RXEND_INIT)
590 return (ptr + RSV_SIZE) - (RXEND_INIT - RXSTART_INIT + 1);
591 else
592 return ptr + RSV_SIZE;
593}
594
595static void nolock_rxfifo_init(struct enc28j60_net *priv, u16 start, u16 end)
596{
597 u16 erxrdpt;
598
599 if (start > 0x1FFF || end > 0x1FFF || start > end) {
600 if (netif_msg_drv(priv))
601 printk(KERN_ERR DRV_NAME ": %s(%d, %d) RXFIFO "
602 "bad parameters!\n", __func__, start, end);
603 return;
604 }
605 /* set receive buffer start + end */
606 priv->next_pk_ptr = start;
607 nolock_regw_write(priv, ERXSTL, start);
608 erxrdpt = erxrdpt_workaround(priv->next_pk_ptr, start, end);
609 nolock_regw_write(priv, ERXRDPTL, erxrdpt);
610 nolock_regw_write(priv, ERXNDL, end);
611}
612
613static void nolock_txfifo_init(struct enc28j60_net *priv, u16 start, u16 end)
614{
615 if (start > 0x1FFF || end > 0x1FFF || start > end) {
616 if (netif_msg_drv(priv))
617 printk(KERN_ERR DRV_NAME ": %s(%d, %d) TXFIFO "
618 "bad parameters!\n", __func__, start, end);
619 return;
620 }
621 /* set transmit buffer start + end */
622 nolock_regw_write(priv, ETXSTL, start);
623 nolock_regw_write(priv, ETXNDL, end);
624}
625
626/*
627 * Low power mode shrinks power consumption about 100x, so we'd like
628 * the chip to be in that mode whenever it's inactive. (However, we
629 * can't stay in lowpower mode during suspend with WOL active.)
630 */
631static void enc28j60_lowpower(struct enc28j60_net *priv, bool is_low)
632{
633 if (netif_msg_drv(priv))
634 dev_dbg(&priv->spi->dev, "%s power...\n",
635 is_low ? "low" : "high");
636
637 mutex_lock(&priv->lock);
638 if (is_low) {
639 nolock_reg_bfclr(priv, ECON1, ECON1_RXEN);
640 poll_ready(priv, ESTAT, ESTAT_RXBUSY, 0);
641 poll_ready(priv, ECON1, ECON1_TXRTS, 0);
642 /* ECON2_VRPS was set during initialization */
643 nolock_reg_bfset(priv, ECON2, ECON2_PWRSV);
644 } else {
645 nolock_reg_bfclr(priv, ECON2, ECON2_PWRSV);
646 poll_ready(priv, ESTAT, ESTAT_CLKRDY, ESTAT_CLKRDY);
647 /* caller sets ECON1_RXEN */
648 }
649 mutex_unlock(&priv->lock);
650}
651
652static int enc28j60_hw_init(struct enc28j60_net *priv)
653{
654 u8 reg;
655
656 if (netif_msg_drv(priv))
657 printk(KERN_DEBUG DRV_NAME ": %s() - %s\n", __func__,
658 priv->full_duplex ? "FullDuplex" : "HalfDuplex");
659
660 mutex_lock(&priv->lock);
661 /* first reset the chip */
662 enc28j60_soft_reset(priv);
663 /* Clear ECON1 */
664 spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, ECON1, 0x00);
665 priv->bank = 0;
666 priv->hw_enable = false;
667 priv->tx_retry_count = 0;
668 priv->max_pk_counter = 0;
669 priv->rxfilter = RXFILTER_NORMAL;
670 /* enable address auto increment and voltage regulator powersave */
671 nolock_regb_write(priv, ECON2, ECON2_AUTOINC | ECON2_VRPS);
672
673 nolock_rxfifo_init(priv, RXSTART_INIT, RXEND_INIT);
674 nolock_txfifo_init(priv, TXSTART_INIT, TXEND_INIT);
675 mutex_unlock(&priv->lock);
676
677 /*
678 * Check the RevID.
679 * If it's 0x00 or 0xFF probably the enc28j60 is not mounted or
680 * damaged
681 */
682 reg = locked_regb_read(priv, EREVID);
683 if (netif_msg_drv(priv))
684 printk(KERN_INFO DRV_NAME ": chip RevID: 0x%02x\n", reg);
685 if (reg == 0x00 || reg == 0xff) {
686 if (netif_msg_drv(priv))
687 printk(KERN_DEBUG DRV_NAME ": %s() Invalid RevId %d\n",
688 __func__, reg);
689 return 0;
690 }
691
692 /* default filter mode: (unicast OR broadcast) AND crc valid */
693 locked_regb_write(priv, ERXFCON,
694 ERXFCON_UCEN | ERXFCON_CRCEN | ERXFCON_BCEN);
695
696 /* enable MAC receive */
697 locked_regb_write(priv, MACON1,
698 MACON1_MARXEN | MACON1_TXPAUS | MACON1_RXPAUS);
699 /* enable automatic padding and CRC operations */
700 if (priv->full_duplex) {
701 locked_regb_write(priv, MACON3,
702 MACON3_PADCFG0 | MACON3_TXCRCEN |
703 MACON3_FRMLNEN | MACON3_FULDPX);
704 /* set inter-frame gap (non-back-to-back) */
705 locked_regb_write(priv, MAIPGL, 0x12);
706 /* set inter-frame gap (back-to-back) */
707 locked_regb_write(priv, MABBIPG, 0x15);
708 } else {
709 locked_regb_write(priv, MACON3,
710 MACON3_PADCFG0 | MACON3_TXCRCEN |
711 MACON3_FRMLNEN);
712 locked_regb_write(priv, MACON4, 1 << 6); /* DEFER bit */
713 /* set inter-frame gap (non-back-to-back) */
714 locked_regw_write(priv, MAIPGL, 0x0C12);
715 /* set inter-frame gap (back-to-back) */
716 locked_regb_write(priv, MABBIPG, 0x12);
717 }
718 /*
719 * MACLCON1 (default)
720 * MACLCON2 (default)
721 * Set the maximum packet size which the controller will accept
722 */
723 locked_regw_write(priv, MAMXFLL, MAX_FRAMELEN);
724
725 /* Configure LEDs */
726 if (!enc28j60_phy_write(priv, PHLCON, ENC28J60_LAMPS_MODE))
727 return 0;
728
729 if (priv->full_duplex) {
730 if (!enc28j60_phy_write(priv, PHCON1, PHCON1_PDPXMD))
731 return 0;
732 if (!enc28j60_phy_write(priv, PHCON2, 0x00))
733 return 0;
734 } else {
735 if (!enc28j60_phy_write(priv, PHCON1, 0x00))
736 return 0;
737 if (!enc28j60_phy_write(priv, PHCON2, PHCON2_HDLDIS))
738 return 0;
739 }
740 if (netif_msg_hw(priv))
741 enc28j60_dump_regs(priv, "Hw initialized.");
742
743 return 1;
744}
745
746static void enc28j60_hw_enable(struct enc28j60_net *priv)
747{
748 /* enable interrupts */
749 if (netif_msg_hw(priv))
750 printk(KERN_DEBUG DRV_NAME ": %s() enabling interrupts.\n",
751 __func__);
752
753 enc28j60_phy_write(priv, PHIE, PHIE_PGEIE | PHIE_PLNKIE);
754
755 mutex_lock(&priv->lock);
756 nolock_reg_bfclr(priv, EIR, EIR_DMAIF | EIR_LINKIF |
757 EIR_TXIF | EIR_TXERIF | EIR_RXERIF | EIR_PKTIF);
758 nolock_regb_write(priv, EIE, EIE_INTIE | EIE_PKTIE | EIE_LINKIE |
759 EIE_TXIE | EIE_TXERIE | EIE_RXERIE);
760
761 /* enable receive logic */
762 nolock_reg_bfset(priv, ECON1, ECON1_RXEN);
763 priv->hw_enable = true;
764 mutex_unlock(&priv->lock);
765}
766
767static void enc28j60_hw_disable(struct enc28j60_net *priv)
768{
769 mutex_lock(&priv->lock);
770 /* disable interrutps and packet reception */
771 nolock_regb_write(priv, EIE, 0x00);
772 nolock_reg_bfclr(priv, ECON1, ECON1_RXEN);
773 priv->hw_enable = false;
774 mutex_unlock(&priv->lock);
775}
776
777static int
778enc28j60_setlink(struct net_device *ndev, u8 autoneg, u16 speed, u8 duplex)
779{
780 struct enc28j60_net *priv = netdev_priv(ndev);
781 int ret = 0;
782
783 if (!priv->hw_enable) {
784 /* link is in low power mode now; duplex setting
785 * will take effect on next enc28j60_hw_init().
786 */
787 if (autoneg == AUTONEG_DISABLE && speed == SPEED_10)
788 priv->full_duplex = (duplex == DUPLEX_FULL);
789 else {
790 if (netif_msg_link(priv))
791 dev_warn(&ndev->dev,
792 "unsupported link setting\n");
793 ret = -EOPNOTSUPP;
794 }
795 } else {
796 if (netif_msg_link(priv))
797 dev_warn(&ndev->dev, "Warning: hw must be disabled "
798 "to set link mode\n");
799 ret = -EBUSY;
800 }
801 return ret;
802}
803
804/*
805 * Read the Transmit Status Vector
806 */
807static void enc28j60_read_tsv(struct enc28j60_net *priv, u8 tsv[TSV_SIZE])
808{
809 int endptr;
810
811 endptr = locked_regw_read(priv, ETXNDL);
812 if (netif_msg_hw(priv))
813 printk(KERN_DEBUG DRV_NAME ": reading TSV at addr:0x%04x\n",
814 endptr + 1);
815 enc28j60_mem_read(priv, endptr + 1, TSV_SIZE, tsv);
816}
817
818static void enc28j60_dump_tsv(struct enc28j60_net *priv, const char *msg,
819 u8 tsv[TSV_SIZE])
820{
821 u16 tmp1, tmp2;
822
823 printk(KERN_DEBUG DRV_NAME ": %s - TSV:\n", msg);
824 tmp1 = tsv[1];
825 tmp1 <<= 8;
826 tmp1 |= tsv[0];
827
828 tmp2 = tsv[5];
829 tmp2 <<= 8;
830 tmp2 |= tsv[4];
831
832 printk(KERN_DEBUG DRV_NAME ": ByteCount: %d, CollisionCount: %d,"
833 " TotByteOnWire: %d\n", tmp1, tsv[2] & 0x0f, tmp2);
834 printk(KERN_DEBUG DRV_NAME ": TxDone: %d, CRCErr:%d, LenChkErr: %d,"
835 " LenOutOfRange: %d\n", TSV_GETBIT(tsv, TSV_TXDONE),
836 TSV_GETBIT(tsv, TSV_TXCRCERROR),
837 TSV_GETBIT(tsv, TSV_TXLENCHKERROR),
838 TSV_GETBIT(tsv, TSV_TXLENOUTOFRANGE));
839 printk(KERN_DEBUG DRV_NAME ": Multicast: %d, Broadcast: %d, "
840 "PacketDefer: %d, ExDefer: %d\n",
841 TSV_GETBIT(tsv, TSV_TXMULTICAST),
842 TSV_GETBIT(tsv, TSV_TXBROADCAST),
843 TSV_GETBIT(tsv, TSV_TXPACKETDEFER),
844 TSV_GETBIT(tsv, TSV_TXEXDEFER));
845 printk(KERN_DEBUG DRV_NAME ": ExCollision: %d, LateCollision: %d, "
846 "Giant: %d, Underrun: %d\n",
847 TSV_GETBIT(tsv, TSV_TXEXCOLLISION),
848 TSV_GETBIT(tsv, TSV_TXLATECOLLISION),
849 TSV_GETBIT(tsv, TSV_TXGIANT), TSV_GETBIT(tsv, TSV_TXUNDERRUN));
850 printk(KERN_DEBUG DRV_NAME ": ControlFrame: %d, PauseFrame: %d, "
851 "BackPressApp: %d, VLanTagFrame: %d\n",
852 TSV_GETBIT(tsv, TSV_TXCONTROLFRAME),
853 TSV_GETBIT(tsv, TSV_TXPAUSEFRAME),
854 TSV_GETBIT(tsv, TSV_BACKPRESSUREAPP),
855 TSV_GETBIT(tsv, TSV_TXVLANTAGFRAME));
856}
857
858/*
859 * Receive Status vector
860 */
861static void enc28j60_dump_rsv(struct enc28j60_net *priv, const char *msg,
862 u16 pk_ptr, int len, u16 sts)
863{
864 printk(KERN_DEBUG DRV_NAME ": %s - NextPk: 0x%04x - RSV:\n",
865 msg, pk_ptr);
866 printk(KERN_DEBUG DRV_NAME ": ByteCount: %d, DribbleNibble: %d\n", len,
867 RSV_GETBIT(sts, RSV_DRIBBLENIBBLE));
868 printk(KERN_DEBUG DRV_NAME ": RxOK: %d, CRCErr:%d, LenChkErr: %d,"
869 " LenOutOfRange: %d\n", RSV_GETBIT(sts, RSV_RXOK),
870 RSV_GETBIT(sts, RSV_CRCERROR),
871 RSV_GETBIT(sts, RSV_LENCHECKERR),
872 RSV_GETBIT(sts, RSV_LENOUTOFRANGE));
873 printk(KERN_DEBUG DRV_NAME ": Multicast: %d, Broadcast: %d, "
874 "LongDropEvent: %d, CarrierEvent: %d\n",
875 RSV_GETBIT(sts, RSV_RXMULTICAST),
876 RSV_GETBIT(sts, RSV_RXBROADCAST),
877 RSV_GETBIT(sts, RSV_RXLONGEVDROPEV),
878 RSV_GETBIT(sts, RSV_CARRIEREV));
879 printk(KERN_DEBUG DRV_NAME ": ControlFrame: %d, PauseFrame: %d,"
880 " UnknownOp: %d, VLanTagFrame: %d\n",
881 RSV_GETBIT(sts, RSV_RXCONTROLFRAME),
882 RSV_GETBIT(sts, RSV_RXPAUSEFRAME),
883 RSV_GETBIT(sts, RSV_RXUNKNOWNOPCODE),
884 RSV_GETBIT(sts, RSV_RXTYPEVLAN));
885}
886
887static void dump_packet(const char *msg, int len, const char *data)
888{
889 printk(KERN_DEBUG DRV_NAME ": %s - packet len:%d\n", msg, len);
890 print_hex_dump(KERN_DEBUG, "pk data: ", DUMP_PREFIX_OFFSET, 16, 1,
891 data, len, true);
892}
893
894/*
895 * Hardware receive function.
896 * Read the buffer memory, update the FIFO pointer to free the buffer,
897 * check the status vector and decrement the packet counter.
898 */
899static void enc28j60_hw_rx(struct net_device *ndev)
900{
901 struct enc28j60_net *priv = netdev_priv(ndev);
902 struct sk_buff *skb = NULL;
903 u16 erxrdpt, next_packet, rxstat;
904 u8 rsv[RSV_SIZE];
905 int len;
906
907 if (netif_msg_rx_status(priv))
908 printk(KERN_DEBUG DRV_NAME ": RX pk_addr:0x%04x\n",
909 priv->next_pk_ptr);
910
911 if (unlikely(priv->next_pk_ptr > RXEND_INIT)) {
912 if (netif_msg_rx_err(priv))
913 dev_err(&ndev->dev,
914 "%s() Invalid packet address!! 0x%04x\n",
915 __func__, priv->next_pk_ptr);
916 /* packet address corrupted: reset RX logic */
917 mutex_lock(&priv->lock);
918 nolock_reg_bfclr(priv, ECON1, ECON1_RXEN);
919 nolock_reg_bfset(priv, ECON1, ECON1_RXRST);
920 nolock_reg_bfclr(priv, ECON1, ECON1_RXRST);
921 nolock_rxfifo_init(priv, RXSTART_INIT, RXEND_INIT);
922 nolock_reg_bfclr(priv, EIR, EIR_RXERIF);
923 nolock_reg_bfset(priv, ECON1, ECON1_RXEN);
924 mutex_unlock(&priv->lock);
925 ndev->stats.rx_errors++;
926 return;
927 }
928 /* Read next packet pointer and rx status vector */
929 enc28j60_mem_read(priv, priv->next_pk_ptr, sizeof(rsv), rsv);
930
931 next_packet = rsv[1];
932 next_packet <<= 8;
933 next_packet |= rsv[0];
934
935 len = rsv[3];
936 len <<= 8;
937 len |= rsv[2];
938
939 rxstat = rsv[5];
940 rxstat <<= 8;
941 rxstat |= rsv[4];
942
943 if (netif_msg_rx_status(priv))
944 enc28j60_dump_rsv(priv, __func__, next_packet, len, rxstat);
945
946 if (!RSV_GETBIT(rxstat, RSV_RXOK) || len > MAX_FRAMELEN) {
947 if (netif_msg_rx_err(priv))
948 dev_err(&ndev->dev, "Rx Error (%04x)\n", rxstat);
949 ndev->stats.rx_errors++;
950 if (RSV_GETBIT(rxstat, RSV_CRCERROR))
951 ndev->stats.rx_crc_errors++;
952 if (RSV_GETBIT(rxstat, RSV_LENCHECKERR))
953 ndev->stats.rx_frame_errors++;
954 if (len > MAX_FRAMELEN)
955 ndev->stats.rx_over_errors++;
956 } else {
957 skb = netdev_alloc_skb(ndev, len + NET_IP_ALIGN);
958 if (!skb) {
959 if (netif_msg_rx_err(priv))
960 dev_err(&ndev->dev,
961 "out of memory for Rx'd frame\n");
962 ndev->stats.rx_dropped++;
963 } else {
964 skb_reserve(skb, NET_IP_ALIGN);
965 /* copy the packet from the receive buffer */
966 enc28j60_mem_read(priv,
967 rx_packet_start(priv->next_pk_ptr),
968 len, skb_put(skb, len));
969 if (netif_msg_pktdata(priv))
970 dump_packet(__func__, skb->len, skb->data);
971 skb->protocol = eth_type_trans(skb, ndev);
972 /* update statistics */
973 ndev->stats.rx_packets++;
974 ndev->stats.rx_bytes += len;
975 netif_rx_ni(skb);
976 }
977 }
978 /*
979 * Move the RX read pointer to the start of the next
980 * received packet.
981 * This frees the memory we just read out
982 */
983 erxrdpt = erxrdpt_workaround(next_packet, RXSTART_INIT, RXEND_INIT);
984 if (netif_msg_hw(priv))
985 printk(KERN_DEBUG DRV_NAME ": %s() ERXRDPT:0x%04x\n",
986 __func__, erxrdpt);
987
988 mutex_lock(&priv->lock);
989 nolock_regw_write(priv, ERXRDPTL, erxrdpt);
990#ifdef CONFIG_ENC28J60_WRITEVERIFY
991 if (netif_msg_drv(priv)) {
992 u16 reg;
993 reg = nolock_regw_read(priv, ERXRDPTL);
994 if (reg != erxrdpt)
995 printk(KERN_DEBUG DRV_NAME ": %s() ERXRDPT verify "
996 "error (0x%04x - 0x%04x)\n", __func__,
997 reg, erxrdpt);
998 }
999#endif
1000 priv->next_pk_ptr = next_packet;
1001 /* we are done with this packet, decrement the packet counter */
1002 nolock_reg_bfset(priv, ECON2, ECON2_PKTDEC);
1003 mutex_unlock(&priv->lock);
1004}
1005
1006/*
1007 * Calculate free space in RxFIFO
1008 */
1009static int enc28j60_get_free_rxfifo(struct enc28j60_net *priv)
1010{
1011 int epkcnt, erxst, erxnd, erxwr, erxrd;
1012 int free_space;
1013
1014 mutex_lock(&priv->lock);
1015 epkcnt = nolock_regb_read(priv, EPKTCNT);
1016 if (epkcnt >= 255)
1017 free_space = -1;
1018 else {
1019 erxst = nolock_regw_read(priv, ERXSTL);
1020 erxnd = nolock_regw_read(priv, ERXNDL);
1021 erxwr = nolock_regw_read(priv, ERXWRPTL);
1022 erxrd = nolock_regw_read(priv, ERXRDPTL);
1023
1024 if (erxwr > erxrd)
1025 free_space = (erxnd - erxst) - (erxwr - erxrd);
1026 else if (erxwr == erxrd)
1027 free_space = (erxnd - erxst);
1028 else
1029 free_space = erxrd - erxwr - 1;
1030 }
1031 mutex_unlock(&priv->lock);
1032 if (netif_msg_rx_status(priv))
1033 printk(KERN_DEBUG DRV_NAME ": %s() free_space = %d\n",
1034 __func__, free_space);
1035 return free_space;
1036}
1037
1038/*
1039 * Access the PHY to determine link status
1040 */
1041static void enc28j60_check_link_status(struct net_device *ndev)
1042{
1043 struct enc28j60_net *priv = netdev_priv(ndev);
1044 u16 reg;
1045 int duplex;
1046
1047 reg = enc28j60_phy_read(priv, PHSTAT2);
1048 if (netif_msg_hw(priv))
1049 printk(KERN_DEBUG DRV_NAME ": %s() PHSTAT1: %04x, "
1050 "PHSTAT2: %04x\n", __func__,
1051 enc28j60_phy_read(priv, PHSTAT1), reg);
1052 duplex = reg & PHSTAT2_DPXSTAT;
1053
1054 if (reg & PHSTAT2_LSTAT) {
1055 netif_carrier_on(ndev);
1056 if (netif_msg_ifup(priv))
1057 dev_info(&ndev->dev, "link up - %s\n",
1058 duplex ? "Full duplex" : "Half duplex");
1059 } else {
1060 if (netif_msg_ifdown(priv))
1061 dev_info(&ndev->dev, "link down\n");
1062 netif_carrier_off(ndev);
1063 }
1064}
1065
1066static void enc28j60_tx_clear(struct net_device *ndev, bool err)
1067{
1068 struct enc28j60_net *priv = netdev_priv(ndev);
1069
1070 if (err)
1071 ndev->stats.tx_errors++;
1072 else
1073 ndev->stats.tx_packets++;
1074
1075 if (priv->tx_skb) {
1076 if (!err)
1077 ndev->stats.tx_bytes += priv->tx_skb->len;
1078 dev_kfree_skb(priv->tx_skb);
1079 priv->tx_skb = NULL;
1080 }
1081 locked_reg_bfclr(priv, ECON1, ECON1_TXRTS);
1082 netif_wake_queue(ndev);
1083}
1084
1085/*
1086 * RX handler
1087 * ignore PKTIF because is unreliable! (look at the errata datasheet)
1088 * check EPKTCNT is the suggested workaround.
1089 * We don't need to clear interrupt flag, automatically done when
1090 * enc28j60_hw_rx() decrements the packet counter.
1091 * Returns how many packet processed.
1092 */
1093static int enc28j60_rx_interrupt(struct net_device *ndev)
1094{
1095 struct enc28j60_net *priv = netdev_priv(ndev);
1096 int pk_counter, ret;
1097
1098 pk_counter = locked_regb_read(priv, EPKTCNT);
1099 if (pk_counter && netif_msg_intr(priv))
1100 printk(KERN_DEBUG DRV_NAME ": intRX, pk_cnt: %d\n", pk_counter);
1101 if (pk_counter > priv->max_pk_counter) {
1102 /* update statistics */
1103 priv->max_pk_counter = pk_counter;
1104 if (netif_msg_rx_status(priv) && priv->max_pk_counter > 1)
1105 printk(KERN_DEBUG DRV_NAME ": RX max_pk_cnt: %d\n",
1106 priv->max_pk_counter);
1107 }
1108 ret = pk_counter;
1109 while (pk_counter-- > 0)
1110 enc28j60_hw_rx(ndev);
1111
1112 return ret;
1113}
1114
1115static void enc28j60_irq_work_handler(struct work_struct *work)
1116{
1117 struct enc28j60_net *priv =
1118 container_of(work, struct enc28j60_net, irq_work);
1119 struct net_device *ndev = priv->netdev;
1120 int intflags, loop;
1121
1122 if (netif_msg_intr(priv))
1123 printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __func__);
1124 /* disable further interrupts */
1125 locked_reg_bfclr(priv, EIE, EIE_INTIE);
1126
1127 do {
1128 loop = 0;
1129 intflags = locked_regb_read(priv, EIR);
1130 /* DMA interrupt handler (not currently used) */
1131 if ((intflags & EIR_DMAIF) != 0) {
1132 loop++;
1133 if (netif_msg_intr(priv))
1134 printk(KERN_DEBUG DRV_NAME
1135 ": intDMA(%d)\n", loop);
1136 locked_reg_bfclr(priv, EIR, EIR_DMAIF);
1137 }
1138 /* LINK changed handler */
1139 if ((intflags & EIR_LINKIF) != 0) {
1140 loop++;
1141 if (netif_msg_intr(priv))
1142 printk(KERN_DEBUG DRV_NAME
1143 ": intLINK(%d)\n", loop);
1144 enc28j60_check_link_status(ndev);
1145 /* read PHIR to clear the flag */
1146 enc28j60_phy_read(priv, PHIR);
1147 }
1148 /* TX complete handler */
1149 if ((intflags & EIR_TXIF) != 0) {
1150 bool err = false;
1151 loop++;
1152 if (netif_msg_intr(priv))
1153 printk(KERN_DEBUG DRV_NAME
1154 ": intTX(%d)\n", loop);
1155 priv->tx_retry_count = 0;
1156 if (locked_regb_read(priv, ESTAT) & ESTAT_TXABRT) {
1157 if (netif_msg_tx_err(priv))
1158 dev_err(&ndev->dev,
1159 "Tx Error (aborted)\n");
1160 err = true;
1161 }
1162 if (netif_msg_tx_done(priv)) {
1163 u8 tsv[TSV_SIZE];
1164 enc28j60_read_tsv(priv, tsv);
1165 enc28j60_dump_tsv(priv, "Tx Done", tsv);
1166 }
1167 enc28j60_tx_clear(ndev, err);
1168 locked_reg_bfclr(priv, EIR, EIR_TXIF);
1169 }
1170 /* TX Error handler */
1171 if ((intflags & EIR_TXERIF) != 0) {
1172 u8 tsv[TSV_SIZE];
1173
1174 loop++;
1175 if (netif_msg_intr(priv))
1176 printk(KERN_DEBUG DRV_NAME
1177 ": intTXErr(%d)\n", loop);
1178 locked_reg_bfclr(priv, ECON1, ECON1_TXRTS);
1179 enc28j60_read_tsv(priv, tsv);
1180 if (netif_msg_tx_err(priv))
1181 enc28j60_dump_tsv(priv, "Tx Error", tsv);
1182 /* Reset TX logic */
1183 mutex_lock(&priv->lock);
1184 nolock_reg_bfset(priv, ECON1, ECON1_TXRST);
1185 nolock_reg_bfclr(priv, ECON1, ECON1_TXRST);
1186 nolock_txfifo_init(priv, TXSTART_INIT, TXEND_INIT);
1187 mutex_unlock(&priv->lock);
1188 /* Transmit Late collision check for retransmit */
1189 if (TSV_GETBIT(tsv, TSV_TXLATECOLLISION)) {
1190 if (netif_msg_tx_err(priv))
1191 printk(KERN_DEBUG DRV_NAME
1192 ": LateCollision TXErr (%d)\n",
1193 priv->tx_retry_count);
1194 if (priv->tx_retry_count++ < MAX_TX_RETRYCOUNT)
1195 locked_reg_bfset(priv, ECON1,
1196 ECON1_TXRTS);
1197 else
1198 enc28j60_tx_clear(ndev, true);
1199 } else
1200 enc28j60_tx_clear(ndev, true);
1201 locked_reg_bfclr(priv, EIR, EIR_TXERIF);
1202 }
1203 /* RX Error handler */
1204 if ((intflags & EIR_RXERIF) != 0) {
1205 loop++;
1206 if (netif_msg_intr(priv))
1207 printk(KERN_DEBUG DRV_NAME
1208 ": intRXErr(%d)\n", loop);
1209 /* Check free FIFO space to flag RX overrun */
1210 if (enc28j60_get_free_rxfifo(priv) <= 0) {
1211 if (netif_msg_rx_err(priv))
1212 printk(KERN_DEBUG DRV_NAME
1213 ": RX Overrun\n");
1214 ndev->stats.rx_dropped++;
1215 }
1216 locked_reg_bfclr(priv, EIR, EIR_RXERIF);
1217 }
1218 /* RX handler */
1219 if (enc28j60_rx_interrupt(ndev))
1220 loop++;
1221 } while (loop);
1222
1223 /* re-enable interrupts */
1224 locked_reg_bfset(priv, EIE, EIE_INTIE);
1225 if (netif_msg_intr(priv))
1226 printk(KERN_DEBUG DRV_NAME ": %s() exit\n", __func__);
1227}
1228
1229/*
1230 * Hardware transmit function.
1231 * Fill the buffer memory and send the contents of the transmit buffer
1232 * onto the network
1233 */
1234static void enc28j60_hw_tx(struct enc28j60_net *priv)
1235{
1236 if (netif_msg_tx_queued(priv))
1237 printk(KERN_DEBUG DRV_NAME
1238 ": Tx Packet Len:%d\n", priv->tx_skb->len);
1239
1240 if (netif_msg_pktdata(priv))
1241 dump_packet(__func__,
1242 priv->tx_skb->len, priv->tx_skb->data);
1243 enc28j60_packet_write(priv, priv->tx_skb->len, priv->tx_skb->data);
1244
1245#ifdef CONFIG_ENC28J60_WRITEVERIFY
1246 /* readback and verify written data */
1247 if (netif_msg_drv(priv)) {
1248 int test_len, k;
1249 u8 test_buf[64]; /* limit the test to the first 64 bytes */
1250 int okflag;
1251
1252 test_len = priv->tx_skb->len;
1253 if (test_len > sizeof(test_buf))
1254 test_len = sizeof(test_buf);
1255
1256 /* + 1 to skip control byte */
1257 enc28j60_mem_read(priv, TXSTART_INIT + 1, test_len, test_buf);
1258 okflag = 1;
1259 for (k = 0; k < test_len; k++) {
1260 if (priv->tx_skb->data[k] != test_buf[k]) {
1261 printk(KERN_DEBUG DRV_NAME
1262 ": Error, %d location differ: "
1263 "0x%02x-0x%02x\n", k,
1264 priv->tx_skb->data[k], test_buf[k]);
1265 okflag = 0;
1266 }
1267 }
1268 if (!okflag)
1269 printk(KERN_DEBUG DRV_NAME ": Tx write buffer, "
1270 "verify ERROR!\n");
1271 }
1272#endif
1273 /* set TX request flag */
1274 locked_reg_bfset(priv, ECON1, ECON1_TXRTS);
1275}
1276
1277static netdev_tx_t enc28j60_send_packet(struct sk_buff *skb,
1278 struct net_device *dev)
1279{
1280 struct enc28j60_net *priv = netdev_priv(dev);
1281
1282 if (netif_msg_tx_queued(priv))
1283 printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __func__);
1284
1285 /* If some error occurs while trying to transmit this
1286 * packet, you should return '1' from this function.
1287 * In such a case you _may not_ do anything to the
1288 * SKB, it is still owned by the network queueing
1289 * layer when an error is returned. This means you
1290 * may not modify any SKB fields, you may not free
1291 * the SKB, etc.
1292 */
1293 netif_stop_queue(dev);
1294
1295 /* Remember the skb for deferred processing */
1296 priv->tx_skb = skb;
1297 schedule_work(&priv->tx_work);
1298
1299 return NETDEV_TX_OK;
1300}
1301
1302static void enc28j60_tx_work_handler(struct work_struct *work)
1303{
1304 struct enc28j60_net *priv =
1305 container_of(work, struct enc28j60_net, tx_work);
1306
1307 /* actual delivery of data */
1308 enc28j60_hw_tx(priv);
1309}
1310
1311static irqreturn_t enc28j60_irq(int irq, void *dev_id)
1312{
1313 struct enc28j60_net *priv = dev_id;
1314
1315 /*
1316 * Can't do anything in interrupt context because we need to
1317 * block (spi_sync() is blocking) so fire of the interrupt
1318 * handling workqueue.
1319 * Remember that we access enc28j60 registers through SPI bus
1320 * via spi_sync() call.
1321 */
1322 schedule_work(&priv->irq_work);
1323
1324 return IRQ_HANDLED;
1325}
1326
1327static void enc28j60_tx_timeout(struct net_device *ndev)
1328{
1329 struct enc28j60_net *priv = netdev_priv(ndev);
1330
1331 if (netif_msg_timer(priv))
1332 dev_err(&ndev->dev, DRV_NAME " tx timeout\n");
1333
1334 ndev->stats.tx_errors++;
1335 /* can't restart safely under softirq */
1336 schedule_work(&priv->restart_work);
1337}
1338
1339/*
1340 * Open/initialize the board. This is called (in the current kernel)
1341 * sometime after booting when the 'ifconfig' program is run.
1342 *
1343 * This routine should set everything up anew at each open, even
1344 * registers that "should" only need to be set once at boot, so that
1345 * there is non-reboot way to recover if something goes wrong.
1346 */
1347static int enc28j60_net_open(struct net_device *dev)
1348{
1349 struct enc28j60_net *priv = netdev_priv(dev);
1350
1351 if (netif_msg_drv(priv))
1352 printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __func__);
1353
1354 if (!is_valid_ether_addr(dev->dev_addr)) {
1355 if (netif_msg_ifup(priv))
1356 dev_err(&dev->dev, "invalid MAC address %pM\n",
1357 dev->dev_addr);
1358 return -EADDRNOTAVAIL;
1359 }
1360 /* Reset the hardware here (and take it out of low power mode) */
1361 enc28j60_lowpower(priv, false);
1362 enc28j60_hw_disable(priv);
1363 if (!enc28j60_hw_init(priv)) {
1364 if (netif_msg_ifup(priv))
1365 dev_err(&dev->dev, "hw_reset() failed\n");
1366 return -EINVAL;
1367 }
1368 /* Update the MAC address (in case user has changed it) */
1369 enc28j60_set_hw_macaddr(dev);
1370 /* Enable interrupts */
1371 enc28j60_hw_enable(priv);
1372 /* check link status */
1373 enc28j60_check_link_status(dev);
1374 /* We are now ready to accept transmit requests from
1375 * the queueing layer of the networking.
1376 */
1377 netif_start_queue(dev);
1378
1379 return 0;
1380}
1381
1382/* The inverse routine to net_open(). */
1383static int enc28j60_net_close(struct net_device *dev)
1384{
1385 struct enc28j60_net *priv = netdev_priv(dev);
1386
1387 if (netif_msg_drv(priv))
1388 printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __func__);
1389
1390 enc28j60_hw_disable(priv);
1391 enc28j60_lowpower(priv, true);
1392 netif_stop_queue(dev);
1393
1394 return 0;
1395}
1396
1397/*
1398 * Set or clear the multicast filter for this adapter
1399 * num_addrs == -1 Promiscuous mode, receive all packets
1400 * num_addrs == 0 Normal mode, filter out multicast packets
1401 * num_addrs > 0 Multicast mode, receive normal and MC packets
1402 */
1403static void enc28j60_set_multicast_list(struct net_device *dev)
1404{
1405 struct enc28j60_net *priv = netdev_priv(dev);
1406 int oldfilter = priv->rxfilter;
1407
1408 if (dev->flags & IFF_PROMISC) {
1409 if (netif_msg_link(priv))
1410 dev_info(&dev->dev, "promiscuous mode\n");
1411 priv->rxfilter = RXFILTER_PROMISC;
1412 } else if ((dev->flags & IFF_ALLMULTI) || !netdev_mc_empty(dev)) {
1413 if (netif_msg_link(priv))
1414 dev_info(&dev->dev, "%smulticast mode\n",
1415 (dev->flags & IFF_ALLMULTI) ? "all-" : "");
1416 priv->rxfilter = RXFILTER_MULTI;
1417 } else {
1418 if (netif_msg_link(priv))
1419 dev_info(&dev->dev, "normal mode\n");
1420 priv->rxfilter = RXFILTER_NORMAL;
1421 }
1422
1423 if (oldfilter != priv->rxfilter)
1424 schedule_work(&priv->setrx_work);
1425}
1426
1427static void enc28j60_setrx_work_handler(struct work_struct *work)
1428{
1429 struct enc28j60_net *priv =
1430 container_of(work, struct enc28j60_net, setrx_work);
1431
1432 if (priv->rxfilter == RXFILTER_PROMISC) {
1433 if (netif_msg_drv(priv))
1434 printk(KERN_DEBUG DRV_NAME ": promiscuous mode\n");
1435 locked_regb_write(priv, ERXFCON, 0x00);
1436 } else if (priv->rxfilter == RXFILTER_MULTI) {
1437 if (netif_msg_drv(priv))
1438 printk(KERN_DEBUG DRV_NAME ": multicast mode\n");
1439 locked_regb_write(priv, ERXFCON,
1440 ERXFCON_UCEN | ERXFCON_CRCEN |
1441 ERXFCON_BCEN | ERXFCON_MCEN);
1442 } else {
1443 if (netif_msg_drv(priv))
1444 printk(KERN_DEBUG DRV_NAME ": normal mode\n");
1445 locked_regb_write(priv, ERXFCON,
1446 ERXFCON_UCEN | ERXFCON_CRCEN |
1447 ERXFCON_BCEN);
1448 }
1449}
1450
1451static void enc28j60_restart_work_handler(struct work_struct *work)
1452{
1453 struct enc28j60_net *priv =
1454 container_of(work, struct enc28j60_net, restart_work);
1455 struct net_device *ndev = priv->netdev;
1456 int ret;
1457
1458 rtnl_lock();
1459 if (netif_running(ndev)) {
1460 enc28j60_net_close(ndev);
1461 ret = enc28j60_net_open(ndev);
1462 if (unlikely(ret)) {
1463 dev_info(&ndev->dev, " could not restart %d\n", ret);
1464 dev_close(ndev);
1465 }
1466 }
1467 rtnl_unlock();
1468}
1469
1470/* ......................... ETHTOOL SUPPORT ........................... */
1471
1472static void
1473enc28j60_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1474{
1475 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
1476 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1477 strlcpy(info->bus_info,
1478 dev_name(dev->dev.parent), sizeof(info->bus_info));
1479}
1480
1481static int
1482enc28j60_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1483{
1484 struct enc28j60_net *priv = netdev_priv(dev);
1485
1486 cmd->transceiver = XCVR_INTERNAL;
1487 cmd->supported = SUPPORTED_10baseT_Half
1488 | SUPPORTED_10baseT_Full
1489 | SUPPORTED_TP;
1490 ethtool_cmd_speed_set(cmd, SPEED_10);
1491 cmd->duplex = priv->full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
1492 cmd->port = PORT_TP;
1493 cmd->autoneg = AUTONEG_DISABLE;
1494
1495 return 0;
1496}
1497
1498static int
1499enc28j60_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1500{
1501 return enc28j60_setlink(dev, cmd->autoneg,
1502 ethtool_cmd_speed(cmd), cmd->duplex);
1503}
1504
1505static u32 enc28j60_get_msglevel(struct net_device *dev)
1506{
1507 struct enc28j60_net *priv = netdev_priv(dev);
1508 return priv->msg_enable;
1509}
1510
1511static void enc28j60_set_msglevel(struct net_device *dev, u32 val)
1512{
1513 struct enc28j60_net *priv = netdev_priv(dev);
1514 priv->msg_enable = val;
1515}
1516
1517static const struct ethtool_ops enc28j60_ethtool_ops = {
1518 .get_settings = enc28j60_get_settings,
1519 .set_settings = enc28j60_set_settings,
1520 .get_drvinfo = enc28j60_get_drvinfo,
1521 .get_msglevel = enc28j60_get_msglevel,
1522 .set_msglevel = enc28j60_set_msglevel,
1523};
1524
1525static int enc28j60_chipset_init(struct net_device *dev)
1526{
1527 struct enc28j60_net *priv = netdev_priv(dev);
1528
1529 return enc28j60_hw_init(priv);
1530}
1531
1532static const struct net_device_ops enc28j60_netdev_ops = {
1533 .ndo_open = enc28j60_net_open,
1534 .ndo_stop = enc28j60_net_close,
1535 .ndo_start_xmit = enc28j60_send_packet,
1536 .ndo_set_rx_mode = enc28j60_set_multicast_list,
1537 .ndo_set_mac_address = enc28j60_set_mac_address,
1538 .ndo_tx_timeout = enc28j60_tx_timeout,
1539 .ndo_change_mtu = eth_change_mtu,
1540 .ndo_validate_addr = eth_validate_addr,
1541};
1542
1543static int enc28j60_probe(struct spi_device *spi)
1544{
1545 struct net_device *dev;
1546 struct enc28j60_net *priv;
1547 int ret = 0;
1548
1549 if (netif_msg_drv(&debug))
1550 dev_info(&spi->dev, DRV_NAME " Ethernet driver %s loaded\n",
1551 DRV_VERSION);
1552
1553 dev = alloc_etherdev(sizeof(struct enc28j60_net));
1554 if (!dev) {
1555 ret = -ENOMEM;
1556 goto error_alloc;
1557 }
1558 priv = netdev_priv(dev);
1559
1560 priv->netdev = dev; /* priv to netdev reference */
1561 priv->spi = spi; /* priv to spi reference */
1562 priv->msg_enable = netif_msg_init(debug.msg_enable,
1563 ENC28J60_MSG_DEFAULT);
1564 mutex_init(&priv->lock);
1565 INIT_WORK(&priv->tx_work, enc28j60_tx_work_handler);
1566 INIT_WORK(&priv->setrx_work, enc28j60_setrx_work_handler);
1567 INIT_WORK(&priv->irq_work, enc28j60_irq_work_handler);
1568 INIT_WORK(&priv->restart_work, enc28j60_restart_work_handler);
1569 spi_set_drvdata(spi, priv); /* spi to priv reference */
1570 SET_NETDEV_DEV(dev, &spi->dev);
1571
1572 if (!enc28j60_chipset_init(dev)) {
1573 if (netif_msg_probe(priv))
1574 dev_info(&spi->dev, DRV_NAME " chip not found\n");
1575 ret = -EIO;
1576 goto error_irq;
1577 }
1578 eth_hw_addr_random(dev);
1579 enc28j60_set_hw_macaddr(dev);
1580
1581 /* Board setup must set the relevant edge trigger type;
1582 * level triggers won't currently work.
1583 */
1584 ret = request_irq(spi->irq, enc28j60_irq, 0, DRV_NAME, priv);
1585 if (ret < 0) {
1586 if (netif_msg_probe(priv))
1587 dev_err(&spi->dev, DRV_NAME ": request irq %d failed "
1588 "(ret = %d)\n", spi->irq, ret);
1589 goto error_irq;
1590 }
1591
1592 dev->if_port = IF_PORT_10BASET;
1593 dev->irq = spi->irq;
1594 dev->netdev_ops = &enc28j60_netdev_ops;
1595 dev->watchdog_timeo = TX_TIMEOUT;
1596 SET_ETHTOOL_OPS(dev, &enc28j60_ethtool_ops);
1597
1598 enc28j60_lowpower(priv, true);
1599
1600 ret = register_netdev(dev);
1601 if (ret) {
1602 if (netif_msg_probe(priv))
1603 dev_err(&spi->dev, "register netdev " DRV_NAME
1604 " failed (ret = %d)\n", ret);
1605 goto error_register;
1606 }
1607 dev_info(&dev->dev, DRV_NAME " driver registered\n");
1608
1609 return 0;
1610
1611error_register:
1612 free_irq(spi->irq, priv);
1613error_irq:
1614 free_netdev(dev);
1615error_alloc:
1616 return ret;
1617}
1618
1619static int enc28j60_remove(struct spi_device *spi)
1620{
1621 struct enc28j60_net *priv = spi_get_drvdata(spi);
1622
1623 if (netif_msg_drv(priv))
1624 printk(KERN_DEBUG DRV_NAME ": remove\n");
1625
1626 unregister_netdev(priv->netdev);
1627 free_irq(spi->irq, priv);
1628 free_netdev(priv->netdev);
1629
1630 return 0;
1631}
1632
1633static struct spi_driver enc28j60_driver = {
1634 .driver = {
1635 .name = DRV_NAME,
1636 .owner = THIS_MODULE,
1637 },
1638 .probe = enc28j60_probe,
1639 .remove = enc28j60_remove,
1640};
1641
1642static int __init enc28j60_init(void)
1643{
1644 msec20_to_jiffies = msecs_to_jiffies(20);
1645
1646 return spi_register_driver(&enc28j60_driver);
1647}
1648
1649module_init(enc28j60_init);
1650
1651static void __exit enc28j60_exit(void)
1652{
1653 spi_unregister_driver(&enc28j60_driver);
1654}
1655
1656module_exit(enc28j60_exit);
1657
1658MODULE_DESCRIPTION(DRV_NAME " ethernet driver");
1659MODULE_AUTHOR("Claudio Lanconelli <lanconelli.claudio@eptar.com>");
1660MODULE_LICENSE("GPL");
1661module_param_named(debug, debug.msg_enable, int, 0);
1662MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., ffff=all)");
1663MODULE_ALIAS("spi:" DRV_NAME);