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1// SPDX-License-Identifier: GPL-2.0
2/* Copyright(c) 2007 - 2018 Intel Corporation. */
3
4/* e1000_82575
5 * e1000_82576
6 */
7
8#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9
10#include <linux/types.h>
11#include <linux/if_ether.h>
12#include <linux/i2c.h>
13
14#include "e1000_mac.h"
15#include "e1000_82575.h"
16#include "e1000_i210.h"
17#include "igb.h"
18
19static s32 igb_get_invariants_82575(struct e1000_hw *);
20static s32 igb_acquire_phy_82575(struct e1000_hw *);
21static void igb_release_phy_82575(struct e1000_hw *);
22static s32 igb_acquire_nvm_82575(struct e1000_hw *);
23static void igb_release_nvm_82575(struct e1000_hw *);
24static s32 igb_check_for_link_82575(struct e1000_hw *);
25static s32 igb_get_cfg_done_82575(struct e1000_hw *);
26static s32 igb_init_hw_82575(struct e1000_hw *);
27static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *);
28static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *);
29static s32 igb_reset_hw_82575(struct e1000_hw *);
30static s32 igb_reset_hw_82580(struct e1000_hw *);
31static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *, bool);
32static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *, bool);
33static s32 igb_set_d3_lplu_state_82580(struct e1000_hw *, bool);
34static s32 igb_setup_copper_link_82575(struct e1000_hw *);
35static s32 igb_setup_serdes_link_82575(struct e1000_hw *);
36static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16);
37static void igb_clear_hw_cntrs_82575(struct e1000_hw *);
38static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *, u16);
39static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *,
40 u16 *);
41static s32 igb_get_phy_id_82575(struct e1000_hw *);
42static void igb_release_swfw_sync_82575(struct e1000_hw *, u16);
43static bool igb_sgmii_active_82575(struct e1000_hw *);
44static s32 igb_reset_init_script_82575(struct e1000_hw *);
45static s32 igb_read_mac_addr_82575(struct e1000_hw *);
46static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw);
47static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw);
48static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw);
49static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw);
50static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw);
51static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw);
52static const u16 e1000_82580_rxpbs_table[] = {
53 36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 };
54
55/* Due to a hw errata, if the host tries to configure the VFTA register
56 * while performing queries from the BMC or DMA, then the VFTA in some
57 * cases won't be written.
58 */
59
60/**
61 * igb_write_vfta_i350 - Write value to VLAN filter table
62 * @hw: pointer to the HW structure
63 * @offset: register offset in VLAN filter table
64 * @value: register value written to VLAN filter table
65 *
66 * Writes value at the given offset in the register array which stores
67 * the VLAN filter table.
68 **/
69static void igb_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value)
70{
71 struct igb_adapter *adapter = hw->back;
72 int i;
73
74 for (i = 10; i--;)
75 array_wr32(E1000_VFTA, offset, value);
76
77 wrfl();
78 adapter->shadow_vfta[offset] = value;
79}
80
81/**
82 * igb_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
83 * @hw: pointer to the HW structure
84 *
85 * Called to determine if the I2C pins are being used for I2C or as an
86 * external MDIO interface since the two options are mutually exclusive.
87 **/
88static bool igb_sgmii_uses_mdio_82575(struct e1000_hw *hw)
89{
90 u32 reg = 0;
91 bool ext_mdio = false;
92
93 switch (hw->mac.type) {
94 case e1000_82575:
95 case e1000_82576:
96 reg = rd32(E1000_MDIC);
97 ext_mdio = !!(reg & E1000_MDIC_DEST);
98 break;
99 case e1000_82580:
100 case e1000_i350:
101 case e1000_i354:
102 case e1000_i210:
103 case e1000_i211:
104 reg = rd32(E1000_MDICNFG);
105 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
106 break;
107 default:
108 break;
109 }
110 return ext_mdio;
111}
112
113/**
114 * igb_check_for_link_media_swap - Check which M88E1112 interface linked
115 * @hw: pointer to the HW structure
116 *
117 * Poll the M88E1112 interfaces to see which interface achieved link.
118 */
119static s32 igb_check_for_link_media_swap(struct e1000_hw *hw)
120{
121 struct e1000_phy_info *phy = &hw->phy;
122 s32 ret_val;
123 u16 data;
124 u8 port = 0;
125
126 /* Check the copper medium. */
127 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
128 if (ret_val)
129 return ret_val;
130
131 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
132 if (ret_val)
133 return ret_val;
134
135 if (data & E1000_M88E1112_STATUS_LINK)
136 port = E1000_MEDIA_PORT_COPPER;
137
138 /* Check the other medium. */
139 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1);
140 if (ret_val)
141 return ret_val;
142
143 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
144 if (ret_val)
145 return ret_val;
146
147
148 if (data & E1000_M88E1112_STATUS_LINK)
149 port = E1000_MEDIA_PORT_OTHER;
150
151 /* Determine if a swap needs to happen. */
152 if (port && (hw->dev_spec._82575.media_port != port)) {
153 hw->dev_spec._82575.media_port = port;
154 hw->dev_spec._82575.media_changed = true;
155 }
156
157 if (port == E1000_MEDIA_PORT_COPPER) {
158 /* reset page to 0 */
159 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
160 if (ret_val)
161 return ret_val;
162 igb_check_for_link_82575(hw);
163 } else {
164 igb_check_for_link_82575(hw);
165 /* reset page to 0 */
166 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
167 if (ret_val)
168 return ret_val;
169 }
170
171 return 0;
172}
173
174/**
175 * igb_init_phy_params_82575 - Init PHY func ptrs.
176 * @hw: pointer to the HW structure
177 **/
178static s32 igb_init_phy_params_82575(struct e1000_hw *hw)
179{
180 struct e1000_phy_info *phy = &hw->phy;
181 s32 ret_val = 0;
182 u32 ctrl_ext;
183
184 if (hw->phy.media_type != e1000_media_type_copper) {
185 phy->type = e1000_phy_none;
186 goto out;
187 }
188
189 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
190 phy->reset_delay_us = 100;
191
192 ctrl_ext = rd32(E1000_CTRL_EXT);
193
194 if (igb_sgmii_active_82575(hw)) {
195 phy->ops.reset = igb_phy_hw_reset_sgmii_82575;
196 ctrl_ext |= E1000_CTRL_I2C_ENA;
197 } else {
198 phy->ops.reset = igb_phy_hw_reset;
199 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
200 }
201
202 wr32(E1000_CTRL_EXT, ctrl_ext);
203 igb_reset_mdicnfg_82580(hw);
204
205 if (igb_sgmii_active_82575(hw) && !igb_sgmii_uses_mdio_82575(hw)) {
206 phy->ops.read_reg = igb_read_phy_reg_sgmii_82575;
207 phy->ops.write_reg = igb_write_phy_reg_sgmii_82575;
208 } else {
209 switch (hw->mac.type) {
210 case e1000_82580:
211 case e1000_i350:
212 case e1000_i354:
213 case e1000_i210:
214 case e1000_i211:
215 phy->ops.read_reg = igb_read_phy_reg_82580;
216 phy->ops.write_reg = igb_write_phy_reg_82580;
217 break;
218 default:
219 phy->ops.read_reg = igb_read_phy_reg_igp;
220 phy->ops.write_reg = igb_write_phy_reg_igp;
221 }
222 }
223
224 /* set lan id */
225 hw->bus.func = FIELD_GET(E1000_STATUS_FUNC_MASK, rd32(E1000_STATUS));
226
227 /* Set phy->phy_addr and phy->id. */
228 ret_val = igb_get_phy_id_82575(hw);
229 if (ret_val)
230 return ret_val;
231
232 /* Verify phy id and set remaining function pointers */
233 switch (phy->id) {
234 case M88E1543_E_PHY_ID:
235 case M88E1512_E_PHY_ID:
236 case I347AT4_E_PHY_ID:
237 case M88E1112_E_PHY_ID:
238 case M88E1111_I_PHY_ID:
239 phy->type = e1000_phy_m88;
240 phy->ops.check_polarity = igb_check_polarity_m88;
241 phy->ops.get_phy_info = igb_get_phy_info_m88;
242 if (phy->id != M88E1111_I_PHY_ID)
243 phy->ops.get_cable_length =
244 igb_get_cable_length_m88_gen2;
245 else
246 phy->ops.get_cable_length = igb_get_cable_length_m88;
247 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
248 /* Check if this PHY is configured for media swap. */
249 if (phy->id == M88E1112_E_PHY_ID) {
250 u16 data;
251
252 ret_val = phy->ops.write_reg(hw,
253 E1000_M88E1112_PAGE_ADDR,
254 2);
255 if (ret_val)
256 goto out;
257
258 ret_val = phy->ops.read_reg(hw,
259 E1000_M88E1112_MAC_CTRL_1,
260 &data);
261 if (ret_val)
262 goto out;
263
264 data = FIELD_GET(E1000_M88E1112_MAC_CTRL_1_MODE_MASK,
265 data);
266 if (data == E1000_M88E1112_AUTO_COPPER_SGMII ||
267 data == E1000_M88E1112_AUTO_COPPER_BASEX)
268 hw->mac.ops.check_for_link =
269 igb_check_for_link_media_swap;
270 }
271 if (phy->id == M88E1512_E_PHY_ID) {
272 ret_val = igb_initialize_M88E1512_phy(hw);
273 if (ret_val)
274 goto out;
275 }
276 if (phy->id == M88E1543_E_PHY_ID) {
277 ret_val = igb_initialize_M88E1543_phy(hw);
278 if (ret_val)
279 goto out;
280 }
281 break;
282 case IGP03E1000_E_PHY_ID:
283 phy->type = e1000_phy_igp_3;
284 phy->ops.get_phy_info = igb_get_phy_info_igp;
285 phy->ops.get_cable_length = igb_get_cable_length_igp_2;
286 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp;
287 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575;
288 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state;
289 break;
290 case I82580_I_PHY_ID:
291 case I350_I_PHY_ID:
292 phy->type = e1000_phy_82580;
293 phy->ops.force_speed_duplex =
294 igb_phy_force_speed_duplex_82580;
295 phy->ops.get_cable_length = igb_get_cable_length_82580;
296 phy->ops.get_phy_info = igb_get_phy_info_82580;
297 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
298 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
299 break;
300 case I210_I_PHY_ID:
301 phy->type = e1000_phy_i210;
302 phy->ops.check_polarity = igb_check_polarity_m88;
303 phy->ops.get_cfg_done = igb_get_cfg_done_i210;
304 phy->ops.get_phy_info = igb_get_phy_info_m88;
305 phy->ops.get_cable_length = igb_get_cable_length_m88_gen2;
306 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
307 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
308 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
309 break;
310 case BCM54616_E_PHY_ID:
311 phy->type = e1000_phy_bcm54616;
312 break;
313 default:
314 ret_val = -E1000_ERR_PHY;
315 goto out;
316 }
317
318out:
319 return ret_val;
320}
321
322/**
323 * igb_init_nvm_params_82575 - Init NVM func ptrs.
324 * @hw: pointer to the HW structure
325 **/
326static s32 igb_init_nvm_params_82575(struct e1000_hw *hw)
327{
328 struct e1000_nvm_info *nvm = &hw->nvm;
329 u32 eecd = rd32(E1000_EECD);
330 u16 size;
331
332 size = FIELD_GET(E1000_EECD_SIZE_EX_MASK, eecd);
333
334 /* Added to a constant, "size" becomes the left-shift value
335 * for setting word_size.
336 */
337 size += NVM_WORD_SIZE_BASE_SHIFT;
338
339 /* Just in case size is out of range, cap it to the largest
340 * EEPROM size supported
341 */
342 if (size > 15)
343 size = 15;
344
345 nvm->word_size = BIT(size);
346 nvm->opcode_bits = 8;
347 nvm->delay_usec = 1;
348
349 switch (nvm->override) {
350 case e1000_nvm_override_spi_large:
351 nvm->page_size = 32;
352 nvm->address_bits = 16;
353 break;
354 case e1000_nvm_override_spi_small:
355 nvm->page_size = 8;
356 nvm->address_bits = 8;
357 break;
358 default:
359 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
360 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
361 16 : 8;
362 break;
363 }
364 if (nvm->word_size == BIT(15))
365 nvm->page_size = 128;
366
367 nvm->type = e1000_nvm_eeprom_spi;
368
369 /* NVM Function Pointers */
370 nvm->ops.acquire = igb_acquire_nvm_82575;
371 nvm->ops.release = igb_release_nvm_82575;
372 nvm->ops.write = igb_write_nvm_spi;
373 nvm->ops.validate = igb_validate_nvm_checksum;
374 nvm->ops.update = igb_update_nvm_checksum;
375 if (nvm->word_size < BIT(15))
376 nvm->ops.read = igb_read_nvm_eerd;
377 else
378 nvm->ops.read = igb_read_nvm_spi;
379
380 /* override generic family function pointers for specific descendants */
381 switch (hw->mac.type) {
382 case e1000_82580:
383 nvm->ops.validate = igb_validate_nvm_checksum_82580;
384 nvm->ops.update = igb_update_nvm_checksum_82580;
385 break;
386 case e1000_i354:
387 case e1000_i350:
388 nvm->ops.validate = igb_validate_nvm_checksum_i350;
389 nvm->ops.update = igb_update_nvm_checksum_i350;
390 break;
391 default:
392 break;
393 }
394
395 return 0;
396}
397
398/**
399 * igb_init_mac_params_82575 - Init MAC func ptrs.
400 * @hw: pointer to the HW structure
401 **/
402static s32 igb_init_mac_params_82575(struct e1000_hw *hw)
403{
404 struct e1000_mac_info *mac = &hw->mac;
405 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
406
407 /* Set mta register count */
408 mac->mta_reg_count = 128;
409 /* Set uta register count */
410 mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128;
411 /* Set rar entry count */
412 switch (mac->type) {
413 case e1000_82576:
414 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
415 break;
416 case e1000_82580:
417 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
418 break;
419 case e1000_i350:
420 case e1000_i354:
421 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
422 break;
423 default:
424 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
425 break;
426 }
427 /* reset */
428 if (mac->type >= e1000_82580)
429 mac->ops.reset_hw = igb_reset_hw_82580;
430 else
431 mac->ops.reset_hw = igb_reset_hw_82575;
432
433 if (mac->type >= e1000_i210) {
434 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_i210;
435 mac->ops.release_swfw_sync = igb_release_swfw_sync_i210;
436
437 } else {
438 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_82575;
439 mac->ops.release_swfw_sync = igb_release_swfw_sync_82575;
440 }
441
442 if ((hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i354))
443 mac->ops.write_vfta = igb_write_vfta_i350;
444 else
445 mac->ops.write_vfta = igb_write_vfta;
446
447 /* Set if part includes ASF firmware */
448 mac->asf_firmware_present = true;
449 /* Set if manageability features are enabled. */
450 mac->arc_subsystem_valid =
451 (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK)
452 ? true : false;
453 /* enable EEE on i350 parts and later parts */
454 if (mac->type >= e1000_i350)
455 dev_spec->eee_disable = false;
456 else
457 dev_spec->eee_disable = true;
458 /* Allow a single clear of the SW semaphore on I210 and newer */
459 if (mac->type >= e1000_i210)
460 dev_spec->clear_semaphore_once = true;
461 /* physical interface link setup */
462 mac->ops.setup_physical_interface =
463 (hw->phy.media_type == e1000_media_type_copper)
464 ? igb_setup_copper_link_82575
465 : igb_setup_serdes_link_82575;
466
467 if (mac->type == e1000_82580 || mac->type == e1000_i350) {
468 switch (hw->device_id) {
469 /* feature not supported on these id's */
470 case E1000_DEV_ID_DH89XXCC_SGMII:
471 case E1000_DEV_ID_DH89XXCC_SERDES:
472 case E1000_DEV_ID_DH89XXCC_BACKPLANE:
473 case E1000_DEV_ID_DH89XXCC_SFP:
474 break;
475 default:
476 hw->dev_spec._82575.mas_capable = true;
477 break;
478 }
479 }
480 return 0;
481}
482
483/**
484 * igb_set_sfp_media_type_82575 - derives SFP module media type.
485 * @hw: pointer to the HW structure
486 *
487 * The media type is chosen based on SFP module.
488 * compatibility flags retrieved from SFP ID EEPROM.
489 **/
490static s32 igb_set_sfp_media_type_82575(struct e1000_hw *hw)
491{
492 s32 ret_val = E1000_ERR_CONFIG;
493 u32 ctrl_ext = 0;
494 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
495 struct e1000_sfp_flags *eth_flags = &dev_spec->eth_flags;
496 u8 tranceiver_type = 0;
497 s32 timeout = 3;
498
499 /* Turn I2C interface ON and power on sfp cage */
500 ctrl_ext = rd32(E1000_CTRL_EXT);
501 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
502 wr32(E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);
503
504 wrfl();
505
506 /* Read SFP module data */
507 while (timeout) {
508 ret_val = igb_read_sfp_data_byte(hw,
509 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET),
510 &tranceiver_type);
511 if (ret_val == 0)
512 break;
513 msleep(100);
514 timeout--;
515 }
516 if (ret_val != 0)
517 goto out;
518
519 ret_val = igb_read_sfp_data_byte(hw,
520 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),
521 (u8 *)eth_flags);
522 if (ret_val != 0)
523 goto out;
524
525 /* Check if there is some SFP module plugged and powered */
526 if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||
527 (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) {
528 dev_spec->module_plugged = true;
529 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) {
530 hw->phy.media_type = e1000_media_type_internal_serdes;
531 } else if (eth_flags->e100_base_fx || eth_flags->e100_base_lx) {
532 dev_spec->sgmii_active = true;
533 hw->phy.media_type = e1000_media_type_internal_serdes;
534 } else if (eth_flags->e1000_base_t) {
535 dev_spec->sgmii_active = true;
536 hw->phy.media_type = e1000_media_type_copper;
537 } else {
538 hw->phy.media_type = e1000_media_type_unknown;
539 hw_dbg("PHY module has not been recognized\n");
540 goto out;
541 }
542 } else {
543 hw->phy.media_type = e1000_media_type_unknown;
544 }
545 ret_val = 0;
546out:
547 /* Restore I2C interface setting */
548 wr32(E1000_CTRL_EXT, ctrl_ext);
549 return ret_val;
550}
551
552static s32 igb_get_invariants_82575(struct e1000_hw *hw)
553{
554 struct e1000_mac_info *mac = &hw->mac;
555 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
556 s32 ret_val;
557 u32 ctrl_ext = 0;
558 u32 link_mode = 0;
559
560 switch (hw->device_id) {
561 case E1000_DEV_ID_82575EB_COPPER:
562 case E1000_DEV_ID_82575EB_FIBER_SERDES:
563 case E1000_DEV_ID_82575GB_QUAD_COPPER:
564 mac->type = e1000_82575;
565 break;
566 case E1000_DEV_ID_82576:
567 case E1000_DEV_ID_82576_NS:
568 case E1000_DEV_ID_82576_NS_SERDES:
569 case E1000_DEV_ID_82576_FIBER:
570 case E1000_DEV_ID_82576_SERDES:
571 case E1000_DEV_ID_82576_QUAD_COPPER:
572 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
573 case E1000_DEV_ID_82576_SERDES_QUAD:
574 mac->type = e1000_82576;
575 break;
576 case E1000_DEV_ID_82580_COPPER:
577 case E1000_DEV_ID_82580_FIBER:
578 case E1000_DEV_ID_82580_QUAD_FIBER:
579 case E1000_DEV_ID_82580_SERDES:
580 case E1000_DEV_ID_82580_SGMII:
581 case E1000_DEV_ID_82580_COPPER_DUAL:
582 case E1000_DEV_ID_DH89XXCC_SGMII:
583 case E1000_DEV_ID_DH89XXCC_SERDES:
584 case E1000_DEV_ID_DH89XXCC_BACKPLANE:
585 case E1000_DEV_ID_DH89XXCC_SFP:
586 mac->type = e1000_82580;
587 break;
588 case E1000_DEV_ID_I350_COPPER:
589 case E1000_DEV_ID_I350_FIBER:
590 case E1000_DEV_ID_I350_SERDES:
591 case E1000_DEV_ID_I350_SGMII:
592 mac->type = e1000_i350;
593 break;
594 case E1000_DEV_ID_I210_COPPER:
595 case E1000_DEV_ID_I210_FIBER:
596 case E1000_DEV_ID_I210_SERDES:
597 case E1000_DEV_ID_I210_SGMII:
598 case E1000_DEV_ID_I210_COPPER_FLASHLESS:
599 case E1000_DEV_ID_I210_SERDES_FLASHLESS:
600 mac->type = e1000_i210;
601 break;
602 case E1000_DEV_ID_I211_COPPER:
603 mac->type = e1000_i211;
604 break;
605 case E1000_DEV_ID_I354_BACKPLANE_1GBPS:
606 case E1000_DEV_ID_I354_SGMII:
607 case E1000_DEV_ID_I354_BACKPLANE_2_5GBPS:
608 mac->type = e1000_i354;
609 break;
610 default:
611 return -E1000_ERR_MAC_INIT;
612 }
613
614 /* Set media type */
615 /* The 82575 uses bits 22:23 for link mode. The mode can be changed
616 * based on the EEPROM. We cannot rely upon device ID. There
617 * is no distinguishable difference between fiber and internal
618 * SerDes mode on the 82575. There can be an external PHY attached
619 * on the SGMII interface. For this, we'll set sgmii_active to true.
620 */
621 hw->phy.media_type = e1000_media_type_copper;
622 dev_spec->sgmii_active = false;
623 dev_spec->module_plugged = false;
624
625 ctrl_ext = rd32(E1000_CTRL_EXT);
626
627 link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK;
628 switch (link_mode) {
629 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
630 hw->phy.media_type = e1000_media_type_internal_serdes;
631 break;
632 case E1000_CTRL_EXT_LINK_MODE_SGMII:
633 /* Get phy control interface type set (MDIO vs. I2C)*/
634 if (igb_sgmii_uses_mdio_82575(hw)) {
635 hw->phy.media_type = e1000_media_type_copper;
636 dev_spec->sgmii_active = true;
637 break;
638 }
639 fallthrough; /* for I2C based SGMII */
640 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
641 /* read media type from SFP EEPROM */
642 ret_val = igb_set_sfp_media_type_82575(hw);
643 if ((ret_val != 0) ||
644 (hw->phy.media_type == e1000_media_type_unknown)) {
645 /* If media type was not identified then return media
646 * type defined by the CTRL_EXT settings.
647 */
648 hw->phy.media_type = e1000_media_type_internal_serdes;
649
650 if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) {
651 hw->phy.media_type = e1000_media_type_copper;
652 dev_spec->sgmii_active = true;
653 }
654
655 break;
656 }
657
658 /* change current link mode setting */
659 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
660
661 if (dev_spec->sgmii_active)
662 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII;
663 else
664 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
665
666 wr32(E1000_CTRL_EXT, ctrl_ext);
667
668 break;
669 default:
670 break;
671 }
672
673 /* mac initialization and operations */
674 ret_val = igb_init_mac_params_82575(hw);
675 if (ret_val)
676 goto out;
677
678 /* NVM initialization */
679 ret_val = igb_init_nvm_params_82575(hw);
680 switch (hw->mac.type) {
681 case e1000_i210:
682 case e1000_i211:
683 ret_val = igb_init_nvm_params_i210(hw);
684 break;
685 default:
686 break;
687 }
688
689 if (ret_val)
690 goto out;
691
692 /* if part supports SR-IOV then initialize mailbox parameters */
693 switch (mac->type) {
694 case e1000_82576:
695 case e1000_i350:
696 igb_init_mbx_params_pf(hw);
697 break;
698 default:
699 break;
700 }
701
702 /* setup PHY parameters */
703 ret_val = igb_init_phy_params_82575(hw);
704
705out:
706 return ret_val;
707}
708
709/**
710 * igb_acquire_phy_82575 - Acquire rights to access PHY
711 * @hw: pointer to the HW structure
712 *
713 * Acquire access rights to the correct PHY. This is a
714 * function pointer entry point called by the api module.
715 **/
716static s32 igb_acquire_phy_82575(struct e1000_hw *hw)
717{
718 u16 mask = E1000_SWFW_PHY0_SM;
719
720 if (hw->bus.func == E1000_FUNC_1)
721 mask = E1000_SWFW_PHY1_SM;
722 else if (hw->bus.func == E1000_FUNC_2)
723 mask = E1000_SWFW_PHY2_SM;
724 else if (hw->bus.func == E1000_FUNC_3)
725 mask = E1000_SWFW_PHY3_SM;
726
727 return hw->mac.ops.acquire_swfw_sync(hw, mask);
728}
729
730/**
731 * igb_release_phy_82575 - Release rights to access PHY
732 * @hw: pointer to the HW structure
733 *
734 * A wrapper to release access rights to the correct PHY. This is a
735 * function pointer entry point called by the api module.
736 **/
737static void igb_release_phy_82575(struct e1000_hw *hw)
738{
739 u16 mask = E1000_SWFW_PHY0_SM;
740
741 if (hw->bus.func == E1000_FUNC_1)
742 mask = E1000_SWFW_PHY1_SM;
743 else if (hw->bus.func == E1000_FUNC_2)
744 mask = E1000_SWFW_PHY2_SM;
745 else if (hw->bus.func == E1000_FUNC_3)
746 mask = E1000_SWFW_PHY3_SM;
747
748 hw->mac.ops.release_swfw_sync(hw, mask);
749}
750
751/**
752 * igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
753 * @hw: pointer to the HW structure
754 * @offset: register offset to be read
755 * @data: pointer to the read data
756 *
757 * Reads the PHY register at offset using the serial gigabit media independent
758 * interface and stores the retrieved information in data.
759 **/
760static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
761 u16 *data)
762{
763 s32 ret_val = -E1000_ERR_PARAM;
764
765 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
766 hw_dbg("PHY Address %u is out of range\n", offset);
767 goto out;
768 }
769
770 ret_val = hw->phy.ops.acquire(hw);
771 if (ret_val)
772 goto out;
773
774 ret_val = igb_read_phy_reg_i2c(hw, offset, data);
775
776 hw->phy.ops.release(hw);
777
778out:
779 return ret_val;
780}
781
782/**
783 * igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
784 * @hw: pointer to the HW structure
785 * @offset: register offset to write to
786 * @data: data to write at register offset
787 *
788 * Writes the data to PHY register at the offset using the serial gigabit
789 * media independent interface.
790 **/
791static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
792 u16 data)
793{
794 s32 ret_val = -E1000_ERR_PARAM;
795
796
797 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
798 hw_dbg("PHY Address %d is out of range\n", offset);
799 goto out;
800 }
801
802 ret_val = hw->phy.ops.acquire(hw);
803 if (ret_val)
804 goto out;
805
806 ret_val = igb_write_phy_reg_i2c(hw, offset, data);
807
808 hw->phy.ops.release(hw);
809
810out:
811 return ret_val;
812}
813
814/**
815 * igb_get_phy_id_82575 - Retrieve PHY addr and id
816 * @hw: pointer to the HW structure
817 *
818 * Retrieves the PHY address and ID for both PHY's which do and do not use
819 * sgmi interface.
820 **/
821static s32 igb_get_phy_id_82575(struct e1000_hw *hw)
822{
823 struct e1000_phy_info *phy = &hw->phy;
824 s32 ret_val = 0;
825 u16 phy_id;
826 u32 ctrl_ext;
827 u32 mdic;
828
829 /* Extra read required for some PHY's on i354 */
830 if (hw->mac.type == e1000_i354)
831 igb_get_phy_id(hw);
832
833 /* For SGMII PHYs, we try the list of possible addresses until
834 * we find one that works. For non-SGMII PHYs
835 * (e.g. integrated copper PHYs), an address of 1 should
836 * work. The result of this function should mean phy->phy_addr
837 * and phy->id are set correctly.
838 */
839 if (!(igb_sgmii_active_82575(hw))) {
840 phy->addr = 1;
841 ret_val = igb_get_phy_id(hw);
842 goto out;
843 }
844
845 if (igb_sgmii_uses_mdio_82575(hw)) {
846 switch (hw->mac.type) {
847 case e1000_82575:
848 case e1000_82576:
849 mdic = rd32(E1000_MDIC);
850 mdic &= E1000_MDIC_PHY_MASK;
851 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
852 break;
853 case e1000_82580:
854 case e1000_i350:
855 case e1000_i354:
856 case e1000_i210:
857 case e1000_i211:
858 mdic = rd32(E1000_MDICNFG);
859 mdic &= E1000_MDICNFG_PHY_MASK;
860 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
861 break;
862 default:
863 ret_val = -E1000_ERR_PHY;
864 goto out;
865 }
866 ret_val = igb_get_phy_id(hw);
867 goto out;
868 }
869
870 /* Power on sgmii phy if it is disabled */
871 ctrl_ext = rd32(E1000_CTRL_EXT);
872 wr32(E1000_CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
873 wrfl();
874 msleep(300);
875
876 /* The address field in the I2CCMD register is 3 bits and 0 is invalid.
877 * Therefore, we need to test 1-7
878 */
879 for (phy->addr = 1; phy->addr < 8; phy->addr++) {
880 ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
881 if (ret_val == 0) {
882 hw_dbg("Vendor ID 0x%08X read at address %u\n",
883 phy_id, phy->addr);
884 /* At the time of this writing, The M88 part is
885 * the only supported SGMII PHY product.
886 */
887 if (phy_id == M88_VENDOR)
888 break;
889 } else {
890 hw_dbg("PHY address %u was unreadable\n", phy->addr);
891 }
892 }
893
894 /* A valid PHY type couldn't be found. */
895 if (phy->addr == 8) {
896 phy->addr = 0;
897 ret_val = -E1000_ERR_PHY;
898 goto out;
899 } else {
900 ret_val = igb_get_phy_id(hw);
901 }
902
903 /* restore previous sfp cage power state */
904 wr32(E1000_CTRL_EXT, ctrl_ext);
905
906out:
907 return ret_val;
908}
909
910/**
911 * igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset
912 * @hw: pointer to the HW structure
913 *
914 * Resets the PHY using the serial gigabit media independent interface.
915 **/
916static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
917{
918 struct e1000_phy_info *phy = &hw->phy;
919 s32 ret_val;
920
921 /* This isn't a true "hard" reset, but is the only reset
922 * available to us at this time.
923 */
924
925 hw_dbg("Soft resetting SGMII attached PHY...\n");
926
927 /* SFP documentation requires the following to configure the SPF module
928 * to work on SGMII. No further documentation is given.
929 */
930 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
931 if (ret_val)
932 goto out;
933
934 ret_val = igb_phy_sw_reset(hw);
935 if (ret_val)
936 goto out;
937
938 if (phy->id == M88E1512_E_PHY_ID)
939 ret_val = igb_initialize_M88E1512_phy(hw);
940 if (phy->id == M88E1543_E_PHY_ID)
941 ret_val = igb_initialize_M88E1543_phy(hw);
942out:
943 return ret_val;
944}
945
946/**
947 * igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
948 * @hw: pointer to the HW structure
949 * @active: true to enable LPLU, false to disable
950 *
951 * Sets the LPLU D0 state according to the active flag. When
952 * activating LPLU this function also disables smart speed
953 * and vice versa. LPLU will not be activated unless the
954 * device autonegotiation advertisement meets standards of
955 * either 10 or 10/100 or 10/100/1000 at all duplexes.
956 * This is a function pointer entry point only called by
957 * PHY setup routines.
958 **/
959static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
960{
961 struct e1000_phy_info *phy = &hw->phy;
962 s32 ret_val;
963 u16 data;
964
965 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
966 if (ret_val)
967 goto out;
968
969 if (active) {
970 data |= IGP02E1000_PM_D0_LPLU;
971 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
972 data);
973 if (ret_val)
974 goto out;
975
976 /* When LPLU is enabled, we should disable SmartSpeed */
977 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
978 &data);
979 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
980 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
981 data);
982 if (ret_val)
983 goto out;
984 } else {
985 data &= ~IGP02E1000_PM_D0_LPLU;
986 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
987 data);
988 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
989 * during Dx states where the power conservation is most
990 * important. During driver activity we should enable
991 * SmartSpeed, so performance is maintained.
992 */
993 if (phy->smart_speed == e1000_smart_speed_on) {
994 ret_val = phy->ops.read_reg(hw,
995 IGP01E1000_PHY_PORT_CONFIG, &data);
996 if (ret_val)
997 goto out;
998
999 data |= IGP01E1000_PSCFR_SMART_SPEED;
1000 ret_val = phy->ops.write_reg(hw,
1001 IGP01E1000_PHY_PORT_CONFIG, data);
1002 if (ret_val)
1003 goto out;
1004 } else if (phy->smart_speed == e1000_smart_speed_off) {
1005 ret_val = phy->ops.read_reg(hw,
1006 IGP01E1000_PHY_PORT_CONFIG, &data);
1007 if (ret_val)
1008 goto out;
1009
1010 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1011 ret_val = phy->ops.write_reg(hw,
1012 IGP01E1000_PHY_PORT_CONFIG, data);
1013 if (ret_val)
1014 goto out;
1015 }
1016 }
1017
1018out:
1019 return ret_val;
1020}
1021
1022/**
1023 * igb_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
1024 * @hw: pointer to the HW structure
1025 * @active: true to enable LPLU, false to disable
1026 *
1027 * Sets the LPLU D0 state according to the active flag. When
1028 * activating LPLU this function also disables smart speed
1029 * and vice versa. LPLU will not be activated unless the
1030 * device autonegotiation advertisement meets standards of
1031 * either 10 or 10/100 or 10/100/1000 at all duplexes.
1032 * This is a function pointer entry point only called by
1033 * PHY setup routines.
1034 **/
1035static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
1036{
1037 struct e1000_phy_info *phy = &hw->phy;
1038 u16 data;
1039
1040 data = rd32(E1000_82580_PHY_POWER_MGMT);
1041
1042 if (active) {
1043 data |= E1000_82580_PM_D0_LPLU;
1044
1045 /* When LPLU is enabled, we should disable SmartSpeed */
1046 data &= ~E1000_82580_PM_SPD;
1047 } else {
1048 data &= ~E1000_82580_PM_D0_LPLU;
1049
1050 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
1051 * during Dx states where the power conservation is most
1052 * important. During driver activity we should enable
1053 * SmartSpeed, so performance is maintained.
1054 */
1055 if (phy->smart_speed == e1000_smart_speed_on)
1056 data |= E1000_82580_PM_SPD;
1057 else if (phy->smart_speed == e1000_smart_speed_off)
1058 data &= ~E1000_82580_PM_SPD; }
1059
1060 wr32(E1000_82580_PHY_POWER_MGMT, data);
1061 return 0;
1062}
1063
1064/**
1065 * igb_set_d3_lplu_state_82580 - Sets low power link up state for D3
1066 * @hw: pointer to the HW structure
1067 * @active: boolean used to enable/disable lplu
1068 *
1069 * Success returns 0, Failure returns 1
1070 *
1071 * The low power link up (lplu) state is set to the power management level D3
1072 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1073 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1074 * is used during Dx states where the power conservation is most important.
1075 * During driver activity, SmartSpeed should be enabled so performance is
1076 * maintained.
1077 **/
1078static s32 igb_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
1079{
1080 struct e1000_phy_info *phy = &hw->phy;
1081 u16 data;
1082
1083 data = rd32(E1000_82580_PHY_POWER_MGMT);
1084
1085 if (!active) {
1086 data &= ~E1000_82580_PM_D3_LPLU;
1087 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
1088 * during Dx states where the power conservation is most
1089 * important. During driver activity we should enable
1090 * SmartSpeed, so performance is maintained.
1091 */
1092 if (phy->smart_speed == e1000_smart_speed_on)
1093 data |= E1000_82580_PM_SPD;
1094 else if (phy->smart_speed == e1000_smart_speed_off)
1095 data &= ~E1000_82580_PM_SPD;
1096 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1097 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1098 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1099 data |= E1000_82580_PM_D3_LPLU;
1100 /* When LPLU is enabled, we should disable SmartSpeed */
1101 data &= ~E1000_82580_PM_SPD;
1102 }
1103
1104 wr32(E1000_82580_PHY_POWER_MGMT, data);
1105 return 0;
1106}
1107
1108/**
1109 * igb_acquire_nvm_82575 - Request for access to EEPROM
1110 * @hw: pointer to the HW structure
1111 *
1112 * Acquire the necessary semaphores for exclusive access to the EEPROM.
1113 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
1114 * Return successful if access grant bit set, else clear the request for
1115 * EEPROM access and return -E1000_ERR_NVM (-1).
1116 **/
1117static s32 igb_acquire_nvm_82575(struct e1000_hw *hw)
1118{
1119 s32 ret_val;
1120
1121 ret_val = hw->mac.ops.acquire_swfw_sync(hw, E1000_SWFW_EEP_SM);
1122 if (ret_val)
1123 goto out;
1124
1125 ret_val = igb_acquire_nvm(hw);
1126
1127 if (ret_val)
1128 hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM);
1129
1130out:
1131 return ret_val;
1132}
1133
1134/**
1135 * igb_release_nvm_82575 - Release exclusive access to EEPROM
1136 * @hw: pointer to the HW structure
1137 *
1138 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
1139 * then release the semaphores acquired.
1140 **/
1141static void igb_release_nvm_82575(struct e1000_hw *hw)
1142{
1143 igb_release_nvm(hw);
1144 hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM);
1145}
1146
1147/**
1148 * igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
1149 * @hw: pointer to the HW structure
1150 * @mask: specifies which semaphore to acquire
1151 *
1152 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
1153 * will also specify which port we're acquiring the lock for.
1154 **/
1155static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1156{
1157 u32 swfw_sync;
1158 u32 swmask = mask;
1159 u32 fwmask = mask << 16;
1160 s32 ret_val = 0;
1161 s32 i = 0, timeout = 200;
1162
1163 while (i < timeout) {
1164 if (igb_get_hw_semaphore(hw)) {
1165 ret_val = -E1000_ERR_SWFW_SYNC;
1166 goto out;
1167 }
1168
1169 swfw_sync = rd32(E1000_SW_FW_SYNC);
1170 if (!(swfw_sync & (fwmask | swmask)))
1171 break;
1172
1173 /* Firmware currently using resource (fwmask)
1174 * or other software thread using resource (swmask)
1175 */
1176 igb_put_hw_semaphore(hw);
1177 mdelay(5);
1178 i++;
1179 }
1180
1181 if (i == timeout) {
1182 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
1183 ret_val = -E1000_ERR_SWFW_SYNC;
1184 goto out;
1185 }
1186
1187 swfw_sync |= swmask;
1188 wr32(E1000_SW_FW_SYNC, swfw_sync);
1189
1190 igb_put_hw_semaphore(hw);
1191
1192out:
1193 return ret_val;
1194}
1195
1196/**
1197 * igb_release_swfw_sync_82575 - Release SW/FW semaphore
1198 * @hw: pointer to the HW structure
1199 * @mask: specifies which semaphore to acquire
1200 *
1201 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
1202 * will also specify which port we're releasing the lock for.
1203 **/
1204static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1205{
1206 u32 swfw_sync;
1207
1208 while (igb_get_hw_semaphore(hw) != 0)
1209 ; /* Empty */
1210
1211 swfw_sync = rd32(E1000_SW_FW_SYNC);
1212 swfw_sync &= ~mask;
1213 wr32(E1000_SW_FW_SYNC, swfw_sync);
1214
1215 igb_put_hw_semaphore(hw);
1216}
1217
1218/**
1219 * igb_get_cfg_done_82575 - Read config done bit
1220 * @hw: pointer to the HW structure
1221 *
1222 * Read the management control register for the config done bit for
1223 * completion status. NOTE: silicon which is EEPROM-less will fail trying
1224 * to read the config done bit, so an error is *ONLY* logged and returns
1225 * 0. If we were to return with error, EEPROM-less silicon
1226 * would not be able to be reset or change link.
1227 **/
1228static s32 igb_get_cfg_done_82575(struct e1000_hw *hw)
1229{
1230 s32 timeout = PHY_CFG_TIMEOUT;
1231 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
1232
1233 if (hw->bus.func == 1)
1234 mask = E1000_NVM_CFG_DONE_PORT_1;
1235 else if (hw->bus.func == E1000_FUNC_2)
1236 mask = E1000_NVM_CFG_DONE_PORT_2;
1237 else if (hw->bus.func == E1000_FUNC_3)
1238 mask = E1000_NVM_CFG_DONE_PORT_3;
1239
1240 while (timeout) {
1241 if (rd32(E1000_EEMNGCTL) & mask)
1242 break;
1243 usleep_range(1000, 2000);
1244 timeout--;
1245 }
1246 if (!timeout)
1247 hw_dbg("MNG configuration cycle has not completed.\n");
1248
1249 /* If EEPROM is not marked present, init the PHY manually */
1250 if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) &&
1251 (hw->phy.type == e1000_phy_igp_3))
1252 igb_phy_init_script_igp3(hw);
1253
1254 return 0;
1255}
1256
1257/**
1258 * igb_get_link_up_info_82575 - Get link speed/duplex info
1259 * @hw: pointer to the HW structure
1260 * @speed: stores the current speed
1261 * @duplex: stores the current duplex
1262 *
1263 * This is a wrapper function, if using the serial gigabit media independent
1264 * interface, use PCS to retrieve the link speed and duplex information.
1265 * Otherwise, use the generic function to get the link speed and duplex info.
1266 **/
1267static s32 igb_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
1268 u16 *duplex)
1269{
1270 s32 ret_val;
1271
1272 if (hw->phy.media_type != e1000_media_type_copper)
1273 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, speed,
1274 duplex);
1275 else
1276 ret_val = igb_get_speed_and_duplex_copper(hw, speed,
1277 duplex);
1278
1279 return ret_val;
1280}
1281
1282/**
1283 * igb_check_for_link_82575 - Check for link
1284 * @hw: pointer to the HW structure
1285 *
1286 * If sgmii is enabled, then use the pcs register to determine link, otherwise
1287 * use the generic interface for determining link.
1288 **/
1289static s32 igb_check_for_link_82575(struct e1000_hw *hw)
1290{
1291 s32 ret_val;
1292 u16 speed, duplex;
1293
1294 if (hw->phy.media_type != e1000_media_type_copper) {
1295 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed,
1296 &duplex);
1297 /* Use this flag to determine if link needs to be checked or
1298 * not. If we have link clear the flag so that we do not
1299 * continue to check for link.
1300 */
1301 hw->mac.get_link_status = !hw->mac.serdes_has_link;
1302
1303 /* Configure Flow Control now that Auto-Neg has completed.
1304 * First, we need to restore the desired flow control
1305 * settings because we may have had to re-autoneg with a
1306 * different link partner.
1307 */
1308 ret_val = igb_config_fc_after_link_up(hw);
1309 if (ret_val)
1310 hw_dbg("Error configuring flow control\n");
1311 } else {
1312 ret_val = igb_check_for_copper_link(hw);
1313 }
1314
1315 return ret_val;
1316}
1317
1318/**
1319 * igb_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1320 * @hw: pointer to the HW structure
1321 **/
1322void igb_power_up_serdes_link_82575(struct e1000_hw *hw)
1323{
1324 u32 reg;
1325
1326
1327 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1328 !igb_sgmii_active_82575(hw))
1329 return;
1330
1331 /* Enable PCS to turn on link */
1332 reg = rd32(E1000_PCS_CFG0);
1333 reg |= E1000_PCS_CFG_PCS_EN;
1334 wr32(E1000_PCS_CFG0, reg);
1335
1336 /* Power up the laser */
1337 reg = rd32(E1000_CTRL_EXT);
1338 reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1339 wr32(E1000_CTRL_EXT, reg);
1340
1341 /* flush the write to verify completion */
1342 wrfl();
1343 usleep_range(1000, 2000);
1344}
1345
1346/**
1347 * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1348 * @hw: pointer to the HW structure
1349 * @speed: stores the current speed
1350 * @duplex: stores the current duplex
1351 *
1352 * Using the physical coding sub-layer (PCS), retrieve the current speed and
1353 * duplex, then store the values in the pointers provided.
1354 **/
1355static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed,
1356 u16 *duplex)
1357{
1358 struct e1000_mac_info *mac = &hw->mac;
1359 u32 pcs, status;
1360
1361 /* Set up defaults for the return values of this function */
1362 mac->serdes_has_link = false;
1363 *speed = 0;
1364 *duplex = 0;
1365
1366 /* Read the PCS Status register for link state. For non-copper mode,
1367 * the status register is not accurate. The PCS status register is
1368 * used instead.
1369 */
1370 pcs = rd32(E1000_PCS_LSTAT);
1371
1372 /* The link up bit determines when link is up on autoneg. The sync ok
1373 * gets set once both sides sync up and agree upon link. Stable link
1374 * can be determined by checking for both link up and link sync ok
1375 */
1376 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) {
1377 mac->serdes_has_link = true;
1378
1379 /* Detect and store PCS speed */
1380 if (pcs & E1000_PCS_LSTS_SPEED_1000)
1381 *speed = SPEED_1000;
1382 else if (pcs & E1000_PCS_LSTS_SPEED_100)
1383 *speed = SPEED_100;
1384 else
1385 *speed = SPEED_10;
1386
1387 /* Detect and store PCS duplex */
1388 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL)
1389 *duplex = FULL_DUPLEX;
1390 else
1391 *duplex = HALF_DUPLEX;
1392
1393 /* Check if it is an I354 2.5Gb backplane connection. */
1394 if (mac->type == e1000_i354) {
1395 status = rd32(E1000_STATUS);
1396 if ((status & E1000_STATUS_2P5_SKU) &&
1397 !(status & E1000_STATUS_2P5_SKU_OVER)) {
1398 *speed = SPEED_2500;
1399 *duplex = FULL_DUPLEX;
1400 hw_dbg("2500 Mbs, ");
1401 hw_dbg("Full Duplex\n");
1402 }
1403 }
1404
1405 }
1406
1407 return 0;
1408}
1409
1410/**
1411 * igb_shutdown_serdes_link_82575 - Remove link during power down
1412 * @hw: pointer to the HW structure
1413 *
1414 * In the case of fiber serdes, shut down optics and PCS on driver unload
1415 * when management pass thru is not enabled.
1416 **/
1417void igb_shutdown_serdes_link_82575(struct e1000_hw *hw)
1418{
1419 u32 reg;
1420
1421 if (hw->phy.media_type != e1000_media_type_internal_serdes &&
1422 igb_sgmii_active_82575(hw))
1423 return;
1424
1425 if (!igb_enable_mng_pass_thru(hw)) {
1426 /* Disable PCS to turn off link */
1427 reg = rd32(E1000_PCS_CFG0);
1428 reg &= ~E1000_PCS_CFG_PCS_EN;
1429 wr32(E1000_PCS_CFG0, reg);
1430
1431 /* shutdown the laser */
1432 reg = rd32(E1000_CTRL_EXT);
1433 reg |= E1000_CTRL_EXT_SDP3_DATA;
1434 wr32(E1000_CTRL_EXT, reg);
1435
1436 /* flush the write to verify completion */
1437 wrfl();
1438 usleep_range(1000, 2000);
1439 }
1440}
1441
1442/**
1443 * igb_reset_hw_82575 - Reset hardware
1444 * @hw: pointer to the HW structure
1445 *
1446 * This resets the hardware into a known state. This is a
1447 * function pointer entry point called by the api module.
1448 **/
1449static s32 igb_reset_hw_82575(struct e1000_hw *hw)
1450{
1451 u32 ctrl;
1452 s32 ret_val;
1453
1454 /* Prevent the PCI-E bus from sticking if there is no TLP connection
1455 * on the last TLP read/write transaction when MAC is reset.
1456 */
1457 ret_val = igb_disable_pcie_master(hw);
1458 if (ret_val)
1459 hw_dbg("PCI-E Master disable polling has failed.\n");
1460
1461 /* set the completion timeout for interface */
1462 ret_val = igb_set_pcie_completion_timeout(hw);
1463 if (ret_val)
1464 hw_dbg("PCI-E Set completion timeout has failed.\n");
1465
1466 hw_dbg("Masking off all interrupts\n");
1467 wr32(E1000_IMC, 0xffffffff);
1468
1469 wr32(E1000_RCTL, 0);
1470 wr32(E1000_TCTL, E1000_TCTL_PSP);
1471 wrfl();
1472
1473 usleep_range(10000, 20000);
1474
1475 ctrl = rd32(E1000_CTRL);
1476
1477 hw_dbg("Issuing a global reset to MAC\n");
1478 wr32(E1000_CTRL, ctrl | E1000_CTRL_RST);
1479
1480 ret_val = igb_get_auto_rd_done(hw);
1481 if (ret_val) {
1482 /* When auto config read does not complete, do not
1483 * return with an error. This can happen in situations
1484 * where there is no eeprom and prevents getting link.
1485 */
1486 hw_dbg("Auto Read Done did not complete\n");
1487 }
1488
1489 /* If EEPROM is not present, run manual init scripts */
1490 if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0)
1491 igb_reset_init_script_82575(hw);
1492
1493 /* Clear any pending interrupt events. */
1494 wr32(E1000_IMC, 0xffffffff);
1495 rd32(E1000_ICR);
1496
1497 /* Install any alternate MAC address into RAR0 */
1498 ret_val = igb_check_alt_mac_addr(hw);
1499
1500 return ret_val;
1501}
1502
1503/**
1504 * igb_init_hw_82575 - Initialize hardware
1505 * @hw: pointer to the HW structure
1506 *
1507 * This inits the hardware readying it for operation.
1508 **/
1509static s32 igb_init_hw_82575(struct e1000_hw *hw)
1510{
1511 struct e1000_mac_info *mac = &hw->mac;
1512 s32 ret_val;
1513 u16 i, rar_count = mac->rar_entry_count;
1514
1515 if ((hw->mac.type >= e1000_i210) &&
1516 !(igb_get_flash_presence_i210(hw))) {
1517 ret_val = igb_pll_workaround_i210(hw);
1518 if (ret_val)
1519 return ret_val;
1520 }
1521
1522 /* Initialize identification LED */
1523 ret_val = igb_id_led_init(hw);
1524 if (ret_val) {
1525 hw_dbg("Error initializing identification LED\n");
1526 /* This is not fatal and we should not stop init due to this */
1527 }
1528
1529 /* Disabling VLAN filtering */
1530 hw_dbg("Initializing the IEEE VLAN\n");
1531 igb_clear_vfta(hw);
1532
1533 /* Setup the receive address */
1534 igb_init_rx_addrs(hw, rar_count);
1535
1536 /* Zero out the Multicast HASH table */
1537 hw_dbg("Zeroing the MTA\n");
1538 for (i = 0; i < mac->mta_reg_count; i++)
1539 array_wr32(E1000_MTA, i, 0);
1540
1541 /* Zero out the Unicast HASH table */
1542 hw_dbg("Zeroing the UTA\n");
1543 for (i = 0; i < mac->uta_reg_count; i++)
1544 array_wr32(E1000_UTA, i, 0);
1545
1546 /* Setup link and flow control */
1547 ret_val = igb_setup_link(hw);
1548
1549 /* Clear all of the statistics registers (clear on read). It is
1550 * important that we do this after we have tried to establish link
1551 * because the symbol error count will increment wildly if there
1552 * is no link.
1553 */
1554 igb_clear_hw_cntrs_82575(hw);
1555 return ret_val;
1556}
1557
1558/**
1559 * igb_setup_copper_link_82575 - Configure copper link settings
1560 * @hw: pointer to the HW structure
1561 *
1562 * Configures the link for auto-neg or forced speed and duplex. Then we check
1563 * for link, once link is established calls to configure collision distance
1564 * and flow control are called.
1565 **/
1566static s32 igb_setup_copper_link_82575(struct e1000_hw *hw)
1567{
1568 u32 ctrl;
1569 s32 ret_val;
1570 u32 phpm_reg;
1571
1572 ctrl = rd32(E1000_CTRL);
1573 ctrl |= E1000_CTRL_SLU;
1574 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1575 wr32(E1000_CTRL, ctrl);
1576
1577 /* Clear Go Link Disconnect bit on supported devices */
1578 switch (hw->mac.type) {
1579 case e1000_82580:
1580 case e1000_i350:
1581 case e1000_i210:
1582 case e1000_i211:
1583 phpm_reg = rd32(E1000_82580_PHY_POWER_MGMT);
1584 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1585 wr32(E1000_82580_PHY_POWER_MGMT, phpm_reg);
1586 break;
1587 default:
1588 break;
1589 }
1590
1591 ret_val = igb_setup_serdes_link_82575(hw);
1592 if (ret_val)
1593 goto out;
1594
1595 if (igb_sgmii_active_82575(hw) && !hw->phy.reset_disable) {
1596 /* allow time for SFP cage time to power up phy */
1597 msleep(300);
1598
1599 ret_val = hw->phy.ops.reset(hw);
1600 if (ret_val) {
1601 hw_dbg("Error resetting the PHY.\n");
1602 goto out;
1603 }
1604 }
1605 switch (hw->phy.type) {
1606 case e1000_phy_i210:
1607 case e1000_phy_m88:
1608 switch (hw->phy.id) {
1609 case I347AT4_E_PHY_ID:
1610 case M88E1112_E_PHY_ID:
1611 case M88E1543_E_PHY_ID:
1612 case M88E1512_E_PHY_ID:
1613 case I210_I_PHY_ID:
1614 ret_val = igb_copper_link_setup_m88_gen2(hw);
1615 break;
1616 default:
1617 ret_val = igb_copper_link_setup_m88(hw);
1618 break;
1619 }
1620 break;
1621 case e1000_phy_igp_3:
1622 ret_val = igb_copper_link_setup_igp(hw);
1623 break;
1624 case e1000_phy_82580:
1625 ret_val = igb_copper_link_setup_82580(hw);
1626 break;
1627 case e1000_phy_bcm54616:
1628 ret_val = 0;
1629 break;
1630 default:
1631 ret_val = -E1000_ERR_PHY;
1632 break;
1633 }
1634
1635 if (ret_val)
1636 goto out;
1637
1638 ret_val = igb_setup_copper_link(hw);
1639out:
1640 return ret_val;
1641}
1642
1643/**
1644 * igb_setup_serdes_link_82575 - Setup link for serdes
1645 * @hw: pointer to the HW structure
1646 *
1647 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1648 * used on copper connections where the serialized gigabit media independent
1649 * interface (sgmii), or serdes fiber is being used. Configures the link
1650 * for auto-negotiation or forces speed/duplex.
1651 **/
1652static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw)
1653{
1654 u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
1655 bool pcs_autoneg;
1656 s32 ret_val = 0;
1657 u16 data;
1658
1659 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1660 !igb_sgmii_active_82575(hw))
1661 return ret_val;
1662
1663
1664 /* On the 82575, SerDes loopback mode persists until it is
1665 * explicitly turned off or a power cycle is performed. A read to
1666 * the register does not indicate its status. Therefore, we ensure
1667 * loopback mode is disabled during initialization.
1668 */
1669 wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1670
1671 /* power on the sfp cage if present and turn on I2C */
1672 ctrl_ext = rd32(E1000_CTRL_EXT);
1673 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1674 ctrl_ext |= E1000_CTRL_I2C_ENA;
1675 wr32(E1000_CTRL_EXT, ctrl_ext);
1676
1677 ctrl_reg = rd32(E1000_CTRL);
1678 ctrl_reg |= E1000_CTRL_SLU;
1679
1680 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) {
1681 /* set both sw defined pins */
1682 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1683
1684 /* Set switch control to serdes energy detect */
1685 reg = rd32(E1000_CONNSW);
1686 reg |= E1000_CONNSW_ENRGSRC;
1687 wr32(E1000_CONNSW, reg);
1688 }
1689
1690 reg = rd32(E1000_PCS_LCTL);
1691
1692 /* default pcs_autoneg to the same setting as mac autoneg */
1693 pcs_autoneg = hw->mac.autoneg;
1694
1695 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1696 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1697 /* sgmii mode lets the phy handle forcing speed/duplex */
1698 pcs_autoneg = true;
1699 /* autoneg time out should be disabled for SGMII mode */
1700 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1701 break;
1702 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1703 /* disable PCS autoneg and support parallel detect only */
1704 pcs_autoneg = false;
1705 fallthrough;
1706 default:
1707 if (hw->mac.type == e1000_82575 ||
1708 hw->mac.type == e1000_82576) {
1709 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1710 if (ret_val) {
1711 hw_dbg(KERN_DEBUG "NVM Read Error\n\n");
1712 return ret_val;
1713 }
1714
1715 if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
1716 pcs_autoneg = false;
1717 }
1718
1719 /* non-SGMII modes only supports a speed of 1000/Full for the
1720 * link so it is best to just force the MAC and let the pcs
1721 * link either autoneg or be forced to 1000/Full
1722 */
1723 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1724 E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1725
1726 /* set speed of 1000/Full if speed/duplex is forced */
1727 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1728 break;
1729 }
1730
1731 wr32(E1000_CTRL, ctrl_reg);
1732
1733 /* New SerDes mode allows for forcing speed or autonegotiating speed
1734 * at 1gb. Autoneg should be default set by most drivers. This is the
1735 * mode that will be compatible with older link partners and switches.
1736 * However, both are supported by the hardware and some drivers/tools.
1737 */
1738 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1739 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1740
1741 if (pcs_autoneg) {
1742 /* Set PCS register for autoneg */
1743 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1744 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1745
1746 /* Disable force flow control for autoneg */
1747 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;
1748
1749 /* Configure flow control advertisement for autoneg */
1750 anadv_reg = rd32(E1000_PCS_ANADV);
1751 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);
1752 switch (hw->fc.requested_mode) {
1753 case e1000_fc_full:
1754 case e1000_fc_rx_pause:
1755 anadv_reg |= E1000_TXCW_ASM_DIR;
1756 anadv_reg |= E1000_TXCW_PAUSE;
1757 break;
1758 case e1000_fc_tx_pause:
1759 anadv_reg |= E1000_TXCW_ASM_DIR;
1760 break;
1761 default:
1762 break;
1763 }
1764 wr32(E1000_PCS_ANADV, anadv_reg);
1765
1766 hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1767 } else {
1768 /* Set PCS register for forced link */
1769 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */
1770
1771 /* Force flow control for forced link */
1772 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1773
1774 hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1775 }
1776
1777 wr32(E1000_PCS_LCTL, reg);
1778
1779 if (!pcs_autoneg && !igb_sgmii_active_82575(hw))
1780 igb_force_mac_fc(hw);
1781
1782 return ret_val;
1783}
1784
1785/**
1786 * igb_sgmii_active_82575 - Return sgmii state
1787 * @hw: pointer to the HW structure
1788 *
1789 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1790 * which can be enabled for use in the embedded applications. Simply
1791 * return the current state of the sgmii interface.
1792 **/
1793static bool igb_sgmii_active_82575(struct e1000_hw *hw)
1794{
1795 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1796 return dev_spec->sgmii_active;
1797}
1798
1799/**
1800 * igb_reset_init_script_82575 - Inits HW defaults after reset
1801 * @hw: pointer to the HW structure
1802 *
1803 * Inits recommended HW defaults after a reset when there is no EEPROM
1804 * detected. This is only for the 82575.
1805 **/
1806static s32 igb_reset_init_script_82575(struct e1000_hw *hw)
1807{
1808 if (hw->mac.type == e1000_82575) {
1809 hw_dbg("Running reset init script for 82575\n");
1810 /* SerDes configuration via SERDESCTRL */
1811 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C);
1812 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78);
1813 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23);
1814 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15);
1815
1816 /* CCM configuration via CCMCTL register */
1817 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00);
1818 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00);
1819
1820 /* PCIe lanes configuration */
1821 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC);
1822 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF);
1823 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05);
1824 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81);
1825
1826 /* PCIe PLL Configuration */
1827 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47);
1828 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00);
1829 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00);
1830 }
1831
1832 return 0;
1833}
1834
1835/**
1836 * igb_read_mac_addr_82575 - Read device MAC address
1837 * @hw: pointer to the HW structure
1838 **/
1839static s32 igb_read_mac_addr_82575(struct e1000_hw *hw)
1840{
1841 s32 ret_val = 0;
1842
1843 /* If there's an alternate MAC address place it in RAR0
1844 * so that it will override the Si installed default perm
1845 * address.
1846 */
1847 ret_val = igb_check_alt_mac_addr(hw);
1848 if (ret_val)
1849 goto out;
1850
1851 ret_val = igb_read_mac_addr(hw);
1852
1853out:
1854 return ret_val;
1855}
1856
1857/**
1858 * igb_power_down_phy_copper_82575 - Remove link during PHY power down
1859 * @hw: pointer to the HW structure
1860 *
1861 * In the case of a PHY power down to save power, or to turn off link during a
1862 * driver unload, or wake on lan is not enabled, remove the link.
1863 **/
1864void igb_power_down_phy_copper_82575(struct e1000_hw *hw)
1865{
1866 /* If the management interface is not enabled, then power down */
1867 if (!(igb_enable_mng_pass_thru(hw) || igb_check_reset_block(hw)))
1868 igb_power_down_phy_copper(hw);
1869}
1870
1871/**
1872 * igb_clear_hw_cntrs_82575 - Clear device specific hardware counters
1873 * @hw: pointer to the HW structure
1874 *
1875 * Clears the hardware counters by reading the counter registers.
1876 **/
1877static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw)
1878{
1879 igb_clear_hw_cntrs_base(hw);
1880
1881 rd32(E1000_PRC64);
1882 rd32(E1000_PRC127);
1883 rd32(E1000_PRC255);
1884 rd32(E1000_PRC511);
1885 rd32(E1000_PRC1023);
1886 rd32(E1000_PRC1522);
1887 rd32(E1000_PTC64);
1888 rd32(E1000_PTC127);
1889 rd32(E1000_PTC255);
1890 rd32(E1000_PTC511);
1891 rd32(E1000_PTC1023);
1892 rd32(E1000_PTC1522);
1893
1894 rd32(E1000_ALGNERRC);
1895 rd32(E1000_RXERRC);
1896 rd32(E1000_TNCRS);
1897 rd32(E1000_CEXTERR);
1898 rd32(E1000_TSCTC);
1899 rd32(E1000_TSCTFC);
1900
1901 rd32(E1000_MGTPRC);
1902 rd32(E1000_MGTPDC);
1903 rd32(E1000_MGTPTC);
1904
1905 rd32(E1000_IAC);
1906 rd32(E1000_ICRXOC);
1907
1908 rd32(E1000_ICRXPTC);
1909 rd32(E1000_ICRXATC);
1910 rd32(E1000_ICTXPTC);
1911 rd32(E1000_ICTXATC);
1912 rd32(E1000_ICTXQEC);
1913 rd32(E1000_ICTXQMTC);
1914 rd32(E1000_ICRXDMTC);
1915
1916 rd32(E1000_CBTMPC);
1917 rd32(E1000_HTDPMC);
1918 rd32(E1000_CBRMPC);
1919 rd32(E1000_RPTHC);
1920 rd32(E1000_HGPTC);
1921 rd32(E1000_HTCBDPC);
1922 rd32(E1000_HGORCL);
1923 rd32(E1000_HGORCH);
1924 rd32(E1000_HGOTCL);
1925 rd32(E1000_HGOTCH);
1926 rd32(E1000_LENERRS);
1927
1928 /* This register should not be read in copper configurations */
1929 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1930 igb_sgmii_active_82575(hw))
1931 rd32(E1000_SCVPC);
1932}
1933
1934/**
1935 * igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable
1936 * @hw: pointer to the HW structure
1937 *
1938 * After rx enable if manageability is enabled then there is likely some
1939 * bad data at the start of the fifo and possibly in the DMA fifo. This
1940 * function clears the fifos and flushes any packets that came in as rx was
1941 * being enabled.
1942 **/
1943void igb_rx_fifo_flush_82575(struct e1000_hw *hw)
1944{
1945 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
1946 int i, ms_wait;
1947
1948 /* disable IPv6 options as per hardware errata */
1949 rfctl = rd32(E1000_RFCTL);
1950 rfctl |= E1000_RFCTL_IPV6_EX_DIS;
1951 wr32(E1000_RFCTL, rfctl);
1952
1953 if (hw->mac.type != e1000_82575 ||
1954 !(rd32(E1000_MANC) & E1000_MANC_RCV_TCO_EN))
1955 return;
1956
1957 /* Disable all RX queues */
1958 for (i = 0; i < 4; i++) {
1959 rxdctl[i] = rd32(E1000_RXDCTL(i));
1960 wr32(E1000_RXDCTL(i),
1961 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
1962 }
1963 /* Poll all queues to verify they have shut down */
1964 for (ms_wait = 0; ms_wait < 10; ms_wait++) {
1965 usleep_range(1000, 2000);
1966 rx_enabled = 0;
1967 for (i = 0; i < 4; i++)
1968 rx_enabled |= rd32(E1000_RXDCTL(i));
1969 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
1970 break;
1971 }
1972
1973 if (ms_wait == 10)
1974 hw_dbg("Queue disable timed out after 10ms\n");
1975
1976 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
1977 * incoming packets are rejected. Set enable and wait 2ms so that
1978 * any packet that was coming in as RCTL.EN was set is flushed
1979 */
1980 wr32(E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
1981
1982 rlpml = rd32(E1000_RLPML);
1983 wr32(E1000_RLPML, 0);
1984
1985 rctl = rd32(E1000_RCTL);
1986 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
1987 temp_rctl |= E1000_RCTL_LPE;
1988
1989 wr32(E1000_RCTL, temp_rctl);
1990 wr32(E1000_RCTL, temp_rctl | E1000_RCTL_EN);
1991 wrfl();
1992 usleep_range(2000, 3000);
1993
1994 /* Enable RX queues that were previously enabled and restore our
1995 * previous state
1996 */
1997 for (i = 0; i < 4; i++)
1998 wr32(E1000_RXDCTL(i), rxdctl[i]);
1999 wr32(E1000_RCTL, rctl);
2000 wrfl();
2001
2002 wr32(E1000_RLPML, rlpml);
2003 wr32(E1000_RFCTL, rfctl);
2004
2005 /* Flush receive errors generated by workaround */
2006 rd32(E1000_ROC);
2007 rd32(E1000_RNBC);
2008 rd32(E1000_MPC);
2009}
2010
2011/**
2012 * igb_set_pcie_completion_timeout - set pci-e completion timeout
2013 * @hw: pointer to the HW structure
2014 *
2015 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
2016 * however the hardware default for these parts is 500us to 1ms which is less
2017 * than the 10ms recommended by the pci-e spec. To address this we need to
2018 * increase the value to either 10ms to 200ms for capability version 1 config,
2019 * or 16ms to 55ms for version 2.
2020 **/
2021static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw)
2022{
2023 u32 gcr = rd32(E1000_GCR);
2024 s32 ret_val = 0;
2025 u16 pcie_devctl2;
2026
2027 /* only take action if timeout value is defaulted to 0 */
2028 if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
2029 goto out;
2030
2031 /* if capabilities version is type 1 we can write the
2032 * timeout of 10ms to 200ms through the GCR register
2033 */
2034 if (!(gcr & E1000_GCR_CAP_VER2)) {
2035 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
2036 goto out;
2037 }
2038
2039 /* for version 2 capabilities we need to write the config space
2040 * directly in order to set the completion timeout value for
2041 * 16ms to 55ms
2042 */
2043 ret_val = igb_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2044 &pcie_devctl2);
2045 if (ret_val)
2046 goto out;
2047
2048 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
2049
2050 ret_val = igb_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2051 &pcie_devctl2);
2052out:
2053 /* disable completion timeout resend */
2054 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
2055
2056 wr32(E1000_GCR, gcr);
2057 return ret_val;
2058}
2059
2060/**
2061 * igb_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
2062 * @hw: pointer to the hardware struct
2063 * @enable: state to enter, either enabled or disabled
2064 * @pf: Physical Function pool - do not set anti-spoofing for the PF
2065 *
2066 * enables/disables L2 switch anti-spoofing functionality.
2067 **/
2068void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
2069{
2070 u32 reg_val, reg_offset;
2071
2072 switch (hw->mac.type) {
2073 case e1000_82576:
2074 reg_offset = E1000_DTXSWC;
2075 break;
2076 case e1000_i350:
2077 case e1000_i354:
2078 reg_offset = E1000_TXSWC;
2079 break;
2080 default:
2081 return;
2082 }
2083
2084 reg_val = rd32(reg_offset);
2085 if (enable) {
2086 reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2087 E1000_DTXSWC_VLAN_SPOOF_MASK);
2088 /* The PF can spoof - it has to in order to
2089 * support emulation mode NICs
2090 */
2091 reg_val ^= (BIT(pf) | BIT(pf + MAX_NUM_VFS));
2092 } else {
2093 reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2094 E1000_DTXSWC_VLAN_SPOOF_MASK);
2095 }
2096 wr32(reg_offset, reg_val);
2097}
2098
2099/**
2100 * igb_vmdq_set_loopback_pf - enable or disable vmdq loopback
2101 * @hw: pointer to the hardware struct
2102 * @enable: state to enter, either enabled or disabled
2103 *
2104 * enables/disables L2 switch loopback functionality.
2105 **/
2106void igb_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
2107{
2108 u32 dtxswc;
2109
2110 switch (hw->mac.type) {
2111 case e1000_82576:
2112 dtxswc = rd32(E1000_DTXSWC);
2113 if (enable)
2114 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2115 else
2116 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2117 wr32(E1000_DTXSWC, dtxswc);
2118 break;
2119 case e1000_i354:
2120 case e1000_i350:
2121 dtxswc = rd32(E1000_TXSWC);
2122 if (enable)
2123 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2124 else
2125 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2126 wr32(E1000_TXSWC, dtxswc);
2127 break;
2128 default:
2129 /* Currently no other hardware supports loopback */
2130 break;
2131 }
2132
2133}
2134
2135/**
2136 * igb_vmdq_set_replication_pf - enable or disable vmdq replication
2137 * @hw: pointer to the hardware struct
2138 * @enable: state to enter, either enabled or disabled
2139 *
2140 * enables/disables replication of packets across multiple pools.
2141 **/
2142void igb_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
2143{
2144 u32 vt_ctl = rd32(E1000_VT_CTL);
2145
2146 if (enable)
2147 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
2148 else
2149 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
2150
2151 wr32(E1000_VT_CTL, vt_ctl);
2152}
2153
2154/**
2155 * igb_read_phy_reg_82580 - Read 82580 MDI control register
2156 * @hw: pointer to the HW structure
2157 * @offset: register offset to be read
2158 * @data: pointer to the read data
2159 *
2160 * Reads the MDI control register in the PHY at offset and stores the
2161 * information read to data.
2162 **/
2163s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
2164{
2165 s32 ret_val;
2166
2167 ret_val = hw->phy.ops.acquire(hw);
2168 if (ret_val)
2169 goto out;
2170
2171 ret_val = igb_read_phy_reg_mdic(hw, offset, data);
2172
2173 hw->phy.ops.release(hw);
2174
2175out:
2176 return ret_val;
2177}
2178
2179/**
2180 * igb_write_phy_reg_82580 - Write 82580 MDI control register
2181 * @hw: pointer to the HW structure
2182 * @offset: register offset to write to
2183 * @data: data to write to register at offset
2184 *
2185 * Writes data to MDI control register in the PHY at offset.
2186 **/
2187s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
2188{
2189 s32 ret_val;
2190
2191
2192 ret_val = hw->phy.ops.acquire(hw);
2193 if (ret_val)
2194 goto out;
2195
2196 ret_val = igb_write_phy_reg_mdic(hw, offset, data);
2197
2198 hw->phy.ops.release(hw);
2199
2200out:
2201 return ret_val;
2202}
2203
2204/**
2205 * igb_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2206 * @hw: pointer to the HW structure
2207 *
2208 * This resets the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
2209 * the values found in the EEPROM. This addresses an issue in which these
2210 * bits are not restored from EEPROM after reset.
2211 **/
2212static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw)
2213{
2214 s32 ret_val = 0;
2215 u32 mdicnfg;
2216 u16 nvm_data = 0;
2217
2218 if (hw->mac.type != e1000_82580)
2219 goto out;
2220 if (!igb_sgmii_active_82575(hw))
2221 goto out;
2222
2223 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2224 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2225 &nvm_data);
2226 if (ret_val) {
2227 hw_dbg("NVM Read Error\n");
2228 goto out;
2229 }
2230
2231 mdicnfg = rd32(E1000_MDICNFG);
2232 if (nvm_data & NVM_WORD24_EXT_MDIO)
2233 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
2234 if (nvm_data & NVM_WORD24_COM_MDIO)
2235 mdicnfg |= E1000_MDICNFG_COM_MDIO;
2236 wr32(E1000_MDICNFG, mdicnfg);
2237out:
2238 return ret_val;
2239}
2240
2241/**
2242 * igb_reset_hw_82580 - Reset hardware
2243 * @hw: pointer to the HW structure
2244 *
2245 * This resets function or entire device (all ports, etc.)
2246 * to a known state.
2247 **/
2248static s32 igb_reset_hw_82580(struct e1000_hw *hw)
2249{
2250 s32 ret_val = 0;
2251 /* BH SW mailbox bit in SW_FW_SYNC */
2252 u16 swmbsw_mask = E1000_SW_SYNCH_MB;
2253 u32 ctrl;
2254 bool global_device_reset = hw->dev_spec._82575.global_device_reset;
2255
2256 hw->dev_spec._82575.global_device_reset = false;
2257
2258 /* due to hw errata, global device reset doesn't always
2259 * work on 82580
2260 */
2261 if (hw->mac.type == e1000_82580)
2262 global_device_reset = false;
2263
2264 /* Get current control state. */
2265 ctrl = rd32(E1000_CTRL);
2266
2267 /* Prevent the PCI-E bus from sticking if there is no TLP connection
2268 * on the last TLP read/write transaction when MAC is reset.
2269 */
2270 ret_val = igb_disable_pcie_master(hw);
2271 if (ret_val)
2272 hw_dbg("PCI-E Master disable polling has failed.\n");
2273
2274 hw_dbg("Masking off all interrupts\n");
2275 wr32(E1000_IMC, 0xffffffff);
2276 wr32(E1000_RCTL, 0);
2277 wr32(E1000_TCTL, E1000_TCTL_PSP);
2278 wrfl();
2279
2280 usleep_range(10000, 11000);
2281
2282 /* Determine whether or not a global dev reset is requested */
2283 if (global_device_reset &&
2284 hw->mac.ops.acquire_swfw_sync(hw, swmbsw_mask))
2285 global_device_reset = false;
2286
2287 if (global_device_reset &&
2288 !(rd32(E1000_STATUS) & E1000_STAT_DEV_RST_SET))
2289 ctrl |= E1000_CTRL_DEV_RST;
2290 else
2291 ctrl |= E1000_CTRL_RST;
2292
2293 wr32(E1000_CTRL, ctrl);
2294 wrfl();
2295
2296 /* Add delay to insure DEV_RST has time to complete */
2297 if (global_device_reset)
2298 usleep_range(5000, 6000);
2299
2300 ret_val = igb_get_auto_rd_done(hw);
2301 if (ret_val) {
2302 /* When auto config read does not complete, do not
2303 * return with an error. This can happen in situations
2304 * where there is no eeprom and prevents getting link.
2305 */
2306 hw_dbg("Auto Read Done did not complete\n");
2307 }
2308
2309 /* clear global device reset status bit */
2310 wr32(E1000_STATUS, E1000_STAT_DEV_RST_SET);
2311
2312 /* Clear any pending interrupt events. */
2313 wr32(E1000_IMC, 0xffffffff);
2314 rd32(E1000_ICR);
2315
2316 ret_val = igb_reset_mdicnfg_82580(hw);
2317 if (ret_val)
2318 hw_dbg("Could not reset MDICNFG based on EEPROM\n");
2319
2320 /* Install any alternate MAC address into RAR0 */
2321 ret_val = igb_check_alt_mac_addr(hw);
2322
2323 /* Release semaphore */
2324 if (global_device_reset)
2325 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
2326
2327 return ret_val;
2328}
2329
2330/**
2331 * igb_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size
2332 * @data: data received by reading RXPBS register
2333 *
2334 * The 82580 uses a table based approach for packet buffer allocation sizes.
2335 * This function converts the retrieved value into the correct table value
2336 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2337 * 0x0 36 72 144 1 2 4 8 16
2338 * 0x8 35 70 140 rsv rsv rsv rsv rsv
2339 */
2340u16 igb_rxpbs_adjust_82580(u32 data)
2341{
2342 u16 ret_val = 0;
2343
2344 if (data < ARRAY_SIZE(e1000_82580_rxpbs_table))
2345 ret_val = e1000_82580_rxpbs_table[data];
2346
2347 return ret_val;
2348}
2349
2350/**
2351 * igb_validate_nvm_checksum_with_offset - Validate EEPROM
2352 * checksum
2353 * @hw: pointer to the HW structure
2354 * @offset: offset in words of the checksum protected region
2355 *
2356 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2357 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
2358 **/
2359static s32 igb_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
2360 u16 offset)
2361{
2362 s32 ret_val = 0;
2363 u16 checksum = 0;
2364 u16 i, nvm_data;
2365
2366 for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
2367 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2368 if (ret_val) {
2369 hw_dbg("NVM Read Error\n");
2370 goto out;
2371 }
2372 checksum += nvm_data;
2373 }
2374
2375 if (checksum != (u16) NVM_SUM) {
2376 hw_dbg("NVM Checksum Invalid\n");
2377 ret_val = -E1000_ERR_NVM;
2378 goto out;
2379 }
2380
2381out:
2382 return ret_val;
2383}
2384
2385/**
2386 * igb_update_nvm_checksum_with_offset - Update EEPROM
2387 * checksum
2388 * @hw: pointer to the HW structure
2389 * @offset: offset in words of the checksum protected region
2390 *
2391 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
2392 * up to the checksum. Then calculates the EEPROM checksum and writes the
2393 * value to the EEPROM.
2394 **/
2395static s32 igb_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2396{
2397 s32 ret_val;
2398 u16 checksum = 0;
2399 u16 i, nvm_data;
2400
2401 for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
2402 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2403 if (ret_val) {
2404 hw_dbg("NVM Read Error while updating checksum.\n");
2405 goto out;
2406 }
2407 checksum += nvm_data;
2408 }
2409 checksum = (u16) NVM_SUM - checksum;
2410 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2411 &checksum);
2412 if (ret_val)
2413 hw_dbg("NVM Write Error while updating checksum.\n");
2414
2415out:
2416 return ret_val;
2417}
2418
2419/**
2420 * igb_validate_nvm_checksum_82580 - Validate EEPROM checksum
2421 * @hw: pointer to the HW structure
2422 *
2423 * Calculates the EEPROM section checksum by reading/adding each word of
2424 * the EEPROM and then verifies that the sum of the EEPROM is
2425 * equal to 0xBABA.
2426 **/
2427static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw)
2428{
2429 s32 ret_val = 0;
2430 u16 eeprom_regions_count = 1;
2431 u16 j, nvm_data;
2432 u16 nvm_offset;
2433
2434 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2435 if (ret_val) {
2436 hw_dbg("NVM Read Error\n");
2437 goto out;
2438 }
2439
2440 if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
2441 /* if checksums compatibility bit is set validate checksums
2442 * for all 4 ports.
2443 */
2444 eeprom_regions_count = 4;
2445 }
2446
2447 for (j = 0; j < eeprom_regions_count; j++) {
2448 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2449 ret_val = igb_validate_nvm_checksum_with_offset(hw,
2450 nvm_offset);
2451 if (ret_val != 0)
2452 goto out;
2453 }
2454
2455out:
2456 return ret_val;
2457}
2458
2459/**
2460 * igb_update_nvm_checksum_82580 - Update EEPROM checksum
2461 * @hw: pointer to the HW structure
2462 *
2463 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2464 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2465 * checksum and writes the value to the EEPROM.
2466 **/
2467static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw)
2468{
2469 s32 ret_val;
2470 u16 j, nvm_data;
2471 u16 nvm_offset;
2472
2473 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2474 if (ret_val) {
2475 hw_dbg("NVM Read Error while updating checksum compatibility bit.\n");
2476 goto out;
2477 }
2478
2479 if ((nvm_data & NVM_COMPATIBILITY_BIT_MASK) == 0) {
2480 /* set compatibility bit to validate checksums appropriately */
2481 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2482 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2483 &nvm_data);
2484 if (ret_val) {
2485 hw_dbg("NVM Write Error while updating checksum compatibility bit.\n");
2486 goto out;
2487 }
2488 }
2489
2490 for (j = 0; j < 4; j++) {
2491 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2492 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
2493 if (ret_val)
2494 goto out;
2495 }
2496
2497out:
2498 return ret_val;
2499}
2500
2501/**
2502 * igb_validate_nvm_checksum_i350 - Validate EEPROM checksum
2503 * @hw: pointer to the HW structure
2504 *
2505 * Calculates the EEPROM section checksum by reading/adding each word of
2506 * the EEPROM and then verifies that the sum of the EEPROM is
2507 * equal to 0xBABA.
2508 **/
2509static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw)
2510{
2511 s32 ret_val = 0;
2512 u16 j;
2513 u16 nvm_offset;
2514
2515 for (j = 0; j < 4; j++) {
2516 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2517 ret_val = igb_validate_nvm_checksum_with_offset(hw,
2518 nvm_offset);
2519 if (ret_val != 0)
2520 goto out;
2521 }
2522
2523out:
2524 return ret_val;
2525}
2526
2527/**
2528 * igb_update_nvm_checksum_i350 - Update EEPROM checksum
2529 * @hw: pointer to the HW structure
2530 *
2531 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2532 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2533 * checksum and writes the value to the EEPROM.
2534 **/
2535static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw)
2536{
2537 s32 ret_val = 0;
2538 u16 j;
2539 u16 nvm_offset;
2540
2541 for (j = 0; j < 4; j++) {
2542 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2543 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
2544 if (ret_val != 0)
2545 goto out;
2546 }
2547
2548out:
2549 return ret_val;
2550}
2551
2552/**
2553 * __igb_access_emi_reg - Read/write EMI register
2554 * @hw: pointer to the HW structure
2555 * @address: EMI address to program
2556 * @data: pointer to value to read/write from/to the EMI address
2557 * @read: boolean flag to indicate read or write
2558 **/
2559static s32 __igb_access_emi_reg(struct e1000_hw *hw, u16 address,
2560 u16 *data, bool read)
2561{
2562 s32 ret_val = 0;
2563
2564 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);
2565 if (ret_val)
2566 return ret_val;
2567
2568 if (read)
2569 ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data);
2570 else
2571 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data);
2572
2573 return ret_val;
2574}
2575
2576/**
2577 * igb_read_emi_reg - Read Extended Management Interface register
2578 * @hw: pointer to the HW structure
2579 * @addr: EMI address to program
2580 * @data: value to be read from the EMI address
2581 **/
2582s32 igb_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data)
2583{
2584 return __igb_access_emi_reg(hw, addr, data, true);
2585}
2586
2587/**
2588 * igb_set_eee_i350 - Enable/disable EEE support
2589 * @hw: pointer to the HW structure
2590 * @adv1G: boolean flag enabling 1G EEE advertisement
2591 * @adv100M: boolean flag enabling 100M EEE advertisement
2592 *
2593 * Enable/disable EEE based on setting in dev_spec structure.
2594 *
2595 **/
2596s32 igb_set_eee_i350(struct e1000_hw *hw, bool adv1G, bool adv100M)
2597{
2598 u32 ipcnfg, eeer;
2599
2600 if ((hw->mac.type < e1000_i350) ||
2601 (hw->phy.media_type != e1000_media_type_copper))
2602 goto out;
2603 ipcnfg = rd32(E1000_IPCNFG);
2604 eeer = rd32(E1000_EEER);
2605
2606 /* enable or disable per user setting */
2607 if (!(hw->dev_spec._82575.eee_disable)) {
2608 u32 eee_su = rd32(E1000_EEE_SU);
2609
2610 if (adv100M)
2611 ipcnfg |= E1000_IPCNFG_EEE_100M_AN;
2612 else
2613 ipcnfg &= ~E1000_IPCNFG_EEE_100M_AN;
2614
2615 if (adv1G)
2616 ipcnfg |= E1000_IPCNFG_EEE_1G_AN;
2617 else
2618 ipcnfg &= ~E1000_IPCNFG_EEE_1G_AN;
2619
2620 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2621 E1000_EEER_LPI_FC);
2622
2623 /* This bit should not be set in normal operation. */
2624 if (eee_su & E1000_EEE_SU_LPI_CLK_STP)
2625 hw_dbg("LPI Clock Stop Bit should not be set!\n");
2626
2627 } else {
2628 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN |
2629 E1000_IPCNFG_EEE_100M_AN);
2630 eeer &= ~(E1000_EEER_TX_LPI_EN |
2631 E1000_EEER_RX_LPI_EN |
2632 E1000_EEER_LPI_FC);
2633 }
2634 wr32(E1000_IPCNFG, ipcnfg);
2635 wr32(E1000_EEER, eeer);
2636 rd32(E1000_IPCNFG);
2637 rd32(E1000_EEER);
2638out:
2639
2640 return 0;
2641}
2642
2643/**
2644 * igb_set_eee_i354 - Enable/disable EEE support
2645 * @hw: pointer to the HW structure
2646 * @adv1G: boolean flag enabling 1G EEE advertisement
2647 * @adv100M: boolean flag enabling 100M EEE advertisement
2648 *
2649 * Enable/disable EEE legacy mode based on setting in dev_spec structure.
2650 *
2651 **/
2652s32 igb_set_eee_i354(struct e1000_hw *hw, bool adv1G, bool adv100M)
2653{
2654 struct e1000_phy_info *phy = &hw->phy;
2655 s32 ret_val = 0;
2656 u16 phy_data;
2657
2658 if ((hw->phy.media_type != e1000_media_type_copper) ||
2659 ((phy->id != M88E1543_E_PHY_ID) &&
2660 (phy->id != M88E1512_E_PHY_ID)))
2661 goto out;
2662
2663 if (!hw->dev_spec._82575.eee_disable) {
2664 /* Switch to PHY page 18. */
2665 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18);
2666 if (ret_val)
2667 goto out;
2668
2669 ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2670 &phy_data);
2671 if (ret_val)
2672 goto out;
2673
2674 phy_data |= E1000_M88E1543_EEE_CTRL_1_MS;
2675 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2676 phy_data);
2677 if (ret_val)
2678 goto out;
2679
2680 /* Return the PHY to page 0. */
2681 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2682 if (ret_val)
2683 goto out;
2684
2685 /* Turn on EEE advertisement. */
2686 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2687 E1000_EEE_ADV_DEV_I354,
2688 &phy_data);
2689 if (ret_val)
2690 goto out;
2691
2692 if (adv100M)
2693 phy_data |= E1000_EEE_ADV_100_SUPPORTED;
2694 else
2695 phy_data &= ~E1000_EEE_ADV_100_SUPPORTED;
2696
2697 if (adv1G)
2698 phy_data |= E1000_EEE_ADV_1000_SUPPORTED;
2699 else
2700 phy_data &= ~E1000_EEE_ADV_1000_SUPPORTED;
2701
2702 ret_val = igb_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2703 E1000_EEE_ADV_DEV_I354,
2704 phy_data);
2705 } else {
2706 /* Turn off EEE advertisement. */
2707 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2708 E1000_EEE_ADV_DEV_I354,
2709 &phy_data);
2710 if (ret_val)
2711 goto out;
2712
2713 phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED |
2714 E1000_EEE_ADV_1000_SUPPORTED);
2715 ret_val = igb_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2716 E1000_EEE_ADV_DEV_I354,
2717 phy_data);
2718 }
2719
2720out:
2721 return ret_val;
2722}
2723
2724/**
2725 * igb_get_eee_status_i354 - Get EEE status
2726 * @hw: pointer to the HW structure
2727 * @status: EEE status
2728 *
2729 * Get EEE status by guessing based on whether Tx or Rx LPI indications have
2730 * been received.
2731 **/
2732s32 igb_get_eee_status_i354(struct e1000_hw *hw, bool *status)
2733{
2734 struct e1000_phy_info *phy = &hw->phy;
2735 s32 ret_val = 0;
2736 u16 phy_data;
2737
2738 /* Check if EEE is supported on this device. */
2739 if ((hw->phy.media_type != e1000_media_type_copper) ||
2740 ((phy->id != M88E1543_E_PHY_ID) &&
2741 (phy->id != M88E1512_E_PHY_ID)))
2742 goto out;
2743
2744 ret_val = igb_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354,
2745 E1000_PCS_STATUS_DEV_I354,
2746 &phy_data);
2747 if (ret_val)
2748 goto out;
2749
2750 *status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD |
2751 E1000_PCS_STATUS_RX_LPI_RCVD) ? true : false;
2752
2753out:
2754 return ret_val;
2755}
2756
2757#ifdef CONFIG_IGB_HWMON
2758static const u8 e1000_emc_temp_data[4] = {
2759 E1000_EMC_INTERNAL_DATA,
2760 E1000_EMC_DIODE1_DATA,
2761 E1000_EMC_DIODE2_DATA,
2762 E1000_EMC_DIODE3_DATA
2763};
2764static const u8 e1000_emc_therm_limit[4] = {
2765 E1000_EMC_INTERNAL_THERM_LIMIT,
2766 E1000_EMC_DIODE1_THERM_LIMIT,
2767 E1000_EMC_DIODE2_THERM_LIMIT,
2768 E1000_EMC_DIODE3_THERM_LIMIT
2769};
2770
2771/**
2772 * igb_get_thermal_sensor_data_generic - Gathers thermal sensor data
2773 * @hw: pointer to hardware structure
2774 *
2775 * Updates the temperatures in mac.thermal_sensor_data
2776 **/
2777static s32 igb_get_thermal_sensor_data_generic(struct e1000_hw *hw)
2778{
2779 u16 ets_offset;
2780 u16 ets_cfg;
2781 u16 ets_sensor;
2782 u8 num_sensors;
2783 u8 sensor_index;
2784 u8 sensor_location;
2785 u8 i;
2786 struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
2787
2788 if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0))
2789 return E1000_NOT_IMPLEMENTED;
2790
2791 data->sensor[0].temp = (rd32(E1000_THMJT) & 0xFF);
2792
2793 /* Return the internal sensor only if ETS is unsupported */
2794 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset);
2795 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
2796 return 0;
2797
2798 hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg);
2799 if (FIELD_GET(NVM_ETS_TYPE_MASK, ets_cfg)
2800 != NVM_ETS_TYPE_EMC)
2801 return E1000_NOT_IMPLEMENTED;
2802
2803 num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK);
2804 if (num_sensors > E1000_MAX_SENSORS)
2805 num_sensors = E1000_MAX_SENSORS;
2806
2807 for (i = 1; i < num_sensors; i++) {
2808 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor);
2809 sensor_index = FIELD_GET(NVM_ETS_DATA_INDEX_MASK, ets_sensor);
2810 sensor_location = FIELD_GET(NVM_ETS_DATA_LOC_MASK, ets_sensor);
2811
2812 if (sensor_location != 0)
2813 hw->phy.ops.read_i2c_byte(hw,
2814 e1000_emc_temp_data[sensor_index],
2815 E1000_I2C_THERMAL_SENSOR_ADDR,
2816 &data->sensor[i].temp);
2817 }
2818 return 0;
2819}
2820
2821/**
2822 * igb_init_thermal_sensor_thresh_generic - Sets thermal sensor thresholds
2823 * @hw: pointer to hardware structure
2824 *
2825 * Sets the thermal sensor thresholds according to the NVM map
2826 * and save off the threshold and location values into mac.thermal_sensor_data
2827 **/
2828static s32 igb_init_thermal_sensor_thresh_generic(struct e1000_hw *hw)
2829{
2830 u16 ets_offset;
2831 u16 ets_cfg;
2832 u16 ets_sensor;
2833 u8 low_thresh_delta;
2834 u8 num_sensors;
2835 u8 sensor_index;
2836 u8 sensor_location;
2837 u8 therm_limit;
2838 u8 i;
2839 struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
2840
2841 if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0))
2842 return E1000_NOT_IMPLEMENTED;
2843
2844 memset(data, 0, sizeof(struct e1000_thermal_sensor_data));
2845
2846 data->sensor[0].location = 0x1;
2847 data->sensor[0].caution_thresh =
2848 (rd32(E1000_THHIGHTC) & 0xFF);
2849 data->sensor[0].max_op_thresh =
2850 (rd32(E1000_THLOWTC) & 0xFF);
2851
2852 /* Return the internal sensor only if ETS is unsupported */
2853 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset);
2854 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
2855 return 0;
2856
2857 hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg);
2858 if (FIELD_GET(NVM_ETS_TYPE_MASK, ets_cfg)
2859 != NVM_ETS_TYPE_EMC)
2860 return E1000_NOT_IMPLEMENTED;
2861
2862 low_thresh_delta = FIELD_GET(NVM_ETS_LTHRES_DELTA_MASK, ets_cfg);
2863 num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK);
2864
2865 for (i = 1; i <= num_sensors; i++) {
2866 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor);
2867 sensor_index = FIELD_GET(NVM_ETS_DATA_INDEX_MASK, ets_sensor);
2868 sensor_location = FIELD_GET(NVM_ETS_DATA_LOC_MASK, ets_sensor);
2869 therm_limit = ets_sensor & NVM_ETS_DATA_HTHRESH_MASK;
2870
2871 hw->phy.ops.write_i2c_byte(hw,
2872 e1000_emc_therm_limit[sensor_index],
2873 E1000_I2C_THERMAL_SENSOR_ADDR,
2874 therm_limit);
2875
2876 if ((i < E1000_MAX_SENSORS) && (sensor_location != 0)) {
2877 data->sensor[i].location = sensor_location;
2878 data->sensor[i].caution_thresh = therm_limit;
2879 data->sensor[i].max_op_thresh = therm_limit -
2880 low_thresh_delta;
2881 }
2882 }
2883 return 0;
2884}
2885
2886#endif
2887static struct e1000_mac_operations e1000_mac_ops_82575 = {
2888 .init_hw = igb_init_hw_82575,
2889 .check_for_link = igb_check_for_link_82575,
2890 .rar_set = igb_rar_set,
2891 .read_mac_addr = igb_read_mac_addr_82575,
2892 .get_speed_and_duplex = igb_get_link_up_info_82575,
2893#ifdef CONFIG_IGB_HWMON
2894 .get_thermal_sensor_data = igb_get_thermal_sensor_data_generic,
2895 .init_thermal_sensor_thresh = igb_init_thermal_sensor_thresh_generic,
2896#endif
2897};
2898
2899static const struct e1000_phy_operations e1000_phy_ops_82575 = {
2900 .acquire = igb_acquire_phy_82575,
2901 .get_cfg_done = igb_get_cfg_done_82575,
2902 .release = igb_release_phy_82575,
2903 .write_i2c_byte = igb_write_i2c_byte,
2904 .read_i2c_byte = igb_read_i2c_byte,
2905};
2906
2907static struct e1000_nvm_operations e1000_nvm_ops_82575 = {
2908 .acquire = igb_acquire_nvm_82575,
2909 .read = igb_read_nvm_eerd,
2910 .release = igb_release_nvm_82575,
2911 .write = igb_write_nvm_spi,
2912};
2913
2914const struct e1000_info e1000_82575_info = {
2915 .get_invariants = igb_get_invariants_82575,
2916 .mac_ops = &e1000_mac_ops_82575,
2917 .phy_ops = &e1000_phy_ops_82575,
2918 .nvm_ops = &e1000_nvm_ops_82575,
2919};
2920
1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2014 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, see <http://www.gnu.org/licenses/>.
17
18 The full GNU General Public License is included in this distribution in
19 the file called "COPYING".
20
21 Contact Information:
22 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24
25*******************************************************************************/
26
27/* e1000_82575
28 * e1000_82576
29 */
30
31#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
32
33#include <linux/types.h>
34#include <linux/if_ether.h>
35#include <linux/i2c.h>
36
37#include "e1000_mac.h"
38#include "e1000_82575.h"
39#include "e1000_i210.h"
40
41static s32 igb_get_invariants_82575(struct e1000_hw *);
42static s32 igb_acquire_phy_82575(struct e1000_hw *);
43static void igb_release_phy_82575(struct e1000_hw *);
44static s32 igb_acquire_nvm_82575(struct e1000_hw *);
45static void igb_release_nvm_82575(struct e1000_hw *);
46static s32 igb_check_for_link_82575(struct e1000_hw *);
47static s32 igb_get_cfg_done_82575(struct e1000_hw *);
48static s32 igb_init_hw_82575(struct e1000_hw *);
49static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *);
50static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *);
51static s32 igb_read_phy_reg_82580(struct e1000_hw *, u32, u16 *);
52static s32 igb_write_phy_reg_82580(struct e1000_hw *, u32, u16);
53static s32 igb_reset_hw_82575(struct e1000_hw *);
54static s32 igb_reset_hw_82580(struct e1000_hw *);
55static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *, bool);
56static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *, bool);
57static s32 igb_set_d3_lplu_state_82580(struct e1000_hw *, bool);
58static s32 igb_setup_copper_link_82575(struct e1000_hw *);
59static s32 igb_setup_serdes_link_82575(struct e1000_hw *);
60static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16);
61static void igb_clear_hw_cntrs_82575(struct e1000_hw *);
62static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *, u16);
63static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *,
64 u16 *);
65static s32 igb_get_phy_id_82575(struct e1000_hw *);
66static void igb_release_swfw_sync_82575(struct e1000_hw *, u16);
67static bool igb_sgmii_active_82575(struct e1000_hw *);
68static s32 igb_reset_init_script_82575(struct e1000_hw *);
69static s32 igb_read_mac_addr_82575(struct e1000_hw *);
70static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw);
71static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw);
72static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw);
73static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw);
74static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw);
75static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw);
76static const u16 e1000_82580_rxpbs_table[] =
77 { 36, 72, 144, 1, 2, 4, 8, 16,
78 35, 70, 140 };
79
80/**
81 * igb_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
82 * @hw: pointer to the HW structure
83 *
84 * Called to determine if the I2C pins are being used for I2C or as an
85 * external MDIO interface since the two options are mutually exclusive.
86 **/
87static bool igb_sgmii_uses_mdio_82575(struct e1000_hw *hw)
88{
89 u32 reg = 0;
90 bool ext_mdio = false;
91
92 switch (hw->mac.type) {
93 case e1000_82575:
94 case e1000_82576:
95 reg = rd32(E1000_MDIC);
96 ext_mdio = !!(reg & E1000_MDIC_DEST);
97 break;
98 case e1000_82580:
99 case e1000_i350:
100 case e1000_i354:
101 case e1000_i210:
102 case e1000_i211:
103 reg = rd32(E1000_MDICNFG);
104 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
105 break;
106 default:
107 break;
108 }
109 return ext_mdio;
110}
111
112/**
113 * igb_check_for_link_media_swap - Check which M88E1112 interface linked
114 * @hw: pointer to the HW structure
115 *
116 * Poll the M88E1112 interfaces to see which interface achieved link.
117 */
118static s32 igb_check_for_link_media_swap(struct e1000_hw *hw)
119{
120 struct e1000_phy_info *phy = &hw->phy;
121 s32 ret_val;
122 u16 data;
123 u8 port = 0;
124
125 /* Check the copper medium. */
126 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
127 if (ret_val)
128 return ret_val;
129
130 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
131 if (ret_val)
132 return ret_val;
133
134 if (data & E1000_M88E1112_STATUS_LINK)
135 port = E1000_MEDIA_PORT_COPPER;
136
137 /* Check the other medium. */
138 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1);
139 if (ret_val)
140 return ret_val;
141
142 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
143 if (ret_val)
144 return ret_val;
145
146 /* reset page to 0 */
147 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
148 if (ret_val)
149 return ret_val;
150
151 if (data & E1000_M88E1112_STATUS_LINK)
152 port = E1000_MEDIA_PORT_OTHER;
153
154 /* Determine if a swap needs to happen. */
155 if (port && (hw->dev_spec._82575.media_port != port)) {
156 hw->dev_spec._82575.media_port = port;
157 hw->dev_spec._82575.media_changed = true;
158 } else {
159 ret_val = igb_check_for_link_82575(hw);
160 }
161
162 return E1000_SUCCESS;
163}
164
165/**
166 * igb_init_phy_params_82575 - Init PHY func ptrs.
167 * @hw: pointer to the HW structure
168 **/
169static s32 igb_init_phy_params_82575(struct e1000_hw *hw)
170{
171 struct e1000_phy_info *phy = &hw->phy;
172 s32 ret_val = 0;
173 u32 ctrl_ext;
174
175 if (hw->phy.media_type != e1000_media_type_copper) {
176 phy->type = e1000_phy_none;
177 goto out;
178 }
179
180 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
181 phy->reset_delay_us = 100;
182
183 ctrl_ext = rd32(E1000_CTRL_EXT);
184
185 if (igb_sgmii_active_82575(hw)) {
186 phy->ops.reset = igb_phy_hw_reset_sgmii_82575;
187 ctrl_ext |= E1000_CTRL_I2C_ENA;
188 } else {
189 phy->ops.reset = igb_phy_hw_reset;
190 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
191 }
192
193 wr32(E1000_CTRL_EXT, ctrl_ext);
194 igb_reset_mdicnfg_82580(hw);
195
196 if (igb_sgmii_active_82575(hw) && !igb_sgmii_uses_mdio_82575(hw)) {
197 phy->ops.read_reg = igb_read_phy_reg_sgmii_82575;
198 phy->ops.write_reg = igb_write_phy_reg_sgmii_82575;
199 } else {
200 switch (hw->mac.type) {
201 case e1000_82580:
202 case e1000_i350:
203 case e1000_i354:
204 phy->ops.read_reg = igb_read_phy_reg_82580;
205 phy->ops.write_reg = igb_write_phy_reg_82580;
206 break;
207 case e1000_i210:
208 case e1000_i211:
209 phy->ops.read_reg = igb_read_phy_reg_gs40g;
210 phy->ops.write_reg = igb_write_phy_reg_gs40g;
211 break;
212 default:
213 phy->ops.read_reg = igb_read_phy_reg_igp;
214 phy->ops.write_reg = igb_write_phy_reg_igp;
215 }
216 }
217
218 /* set lan id */
219 hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >>
220 E1000_STATUS_FUNC_SHIFT;
221
222 /* Set phy->phy_addr and phy->id. */
223 ret_val = igb_get_phy_id_82575(hw);
224 if (ret_val)
225 return ret_val;
226
227 /* Verify phy id and set remaining function pointers */
228 switch (phy->id) {
229 case M88E1543_E_PHY_ID:
230 case I347AT4_E_PHY_ID:
231 case M88E1112_E_PHY_ID:
232 case M88E1111_I_PHY_ID:
233 phy->type = e1000_phy_m88;
234 phy->ops.check_polarity = igb_check_polarity_m88;
235 phy->ops.get_phy_info = igb_get_phy_info_m88;
236 if (phy->id != M88E1111_I_PHY_ID)
237 phy->ops.get_cable_length =
238 igb_get_cable_length_m88_gen2;
239 else
240 phy->ops.get_cable_length = igb_get_cable_length_m88;
241 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
242 /* Check if this PHY is confgured for media swap. */
243 if (phy->id == M88E1112_E_PHY_ID) {
244 u16 data;
245
246 ret_val = phy->ops.write_reg(hw,
247 E1000_M88E1112_PAGE_ADDR,
248 2);
249 if (ret_val)
250 goto out;
251
252 ret_val = phy->ops.read_reg(hw,
253 E1000_M88E1112_MAC_CTRL_1,
254 &data);
255 if (ret_val)
256 goto out;
257
258 data = (data & E1000_M88E1112_MAC_CTRL_1_MODE_MASK) >>
259 E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT;
260 if (data == E1000_M88E1112_AUTO_COPPER_SGMII ||
261 data == E1000_M88E1112_AUTO_COPPER_BASEX)
262 hw->mac.ops.check_for_link =
263 igb_check_for_link_media_swap;
264 }
265 break;
266 case IGP03E1000_E_PHY_ID:
267 phy->type = e1000_phy_igp_3;
268 phy->ops.get_phy_info = igb_get_phy_info_igp;
269 phy->ops.get_cable_length = igb_get_cable_length_igp_2;
270 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp;
271 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575;
272 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state;
273 break;
274 case I82580_I_PHY_ID:
275 case I350_I_PHY_ID:
276 phy->type = e1000_phy_82580;
277 phy->ops.force_speed_duplex =
278 igb_phy_force_speed_duplex_82580;
279 phy->ops.get_cable_length = igb_get_cable_length_82580;
280 phy->ops.get_phy_info = igb_get_phy_info_82580;
281 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
282 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
283 break;
284 case I210_I_PHY_ID:
285 phy->type = e1000_phy_i210;
286 phy->ops.check_polarity = igb_check_polarity_m88;
287 phy->ops.get_phy_info = igb_get_phy_info_m88;
288 phy->ops.get_cable_length = igb_get_cable_length_m88_gen2;
289 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
290 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
291 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
292 break;
293 default:
294 ret_val = -E1000_ERR_PHY;
295 goto out;
296 }
297
298out:
299 return ret_val;
300}
301
302/**
303 * igb_init_nvm_params_82575 - Init NVM func ptrs.
304 * @hw: pointer to the HW structure
305 **/
306static s32 igb_init_nvm_params_82575(struct e1000_hw *hw)
307{
308 struct e1000_nvm_info *nvm = &hw->nvm;
309 u32 eecd = rd32(E1000_EECD);
310 u16 size;
311
312 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
313 E1000_EECD_SIZE_EX_SHIFT);
314
315 /* Added to a constant, "size" becomes the left-shift value
316 * for setting word_size.
317 */
318 size += NVM_WORD_SIZE_BASE_SHIFT;
319
320 /* Just in case size is out of range, cap it to the largest
321 * EEPROM size supported
322 */
323 if (size > 15)
324 size = 15;
325
326 nvm->word_size = 1 << size;
327 nvm->opcode_bits = 8;
328 nvm->delay_usec = 1;
329
330 switch (nvm->override) {
331 case e1000_nvm_override_spi_large:
332 nvm->page_size = 32;
333 nvm->address_bits = 16;
334 break;
335 case e1000_nvm_override_spi_small:
336 nvm->page_size = 8;
337 nvm->address_bits = 8;
338 break;
339 default:
340 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
341 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
342 16 : 8;
343 break;
344 }
345 if (nvm->word_size == (1 << 15))
346 nvm->page_size = 128;
347
348 nvm->type = e1000_nvm_eeprom_spi;
349
350 /* NVM Function Pointers */
351 nvm->ops.acquire = igb_acquire_nvm_82575;
352 nvm->ops.release = igb_release_nvm_82575;
353 nvm->ops.write = igb_write_nvm_spi;
354 nvm->ops.validate = igb_validate_nvm_checksum;
355 nvm->ops.update = igb_update_nvm_checksum;
356 if (nvm->word_size < (1 << 15))
357 nvm->ops.read = igb_read_nvm_eerd;
358 else
359 nvm->ops.read = igb_read_nvm_spi;
360
361 /* override generic family function pointers for specific descendants */
362 switch (hw->mac.type) {
363 case e1000_82580:
364 nvm->ops.validate = igb_validate_nvm_checksum_82580;
365 nvm->ops.update = igb_update_nvm_checksum_82580;
366 break;
367 case e1000_i354:
368 case e1000_i350:
369 nvm->ops.validate = igb_validate_nvm_checksum_i350;
370 nvm->ops.update = igb_update_nvm_checksum_i350;
371 break;
372 default:
373 break;
374 }
375
376 return 0;
377}
378
379/**
380 * igb_init_mac_params_82575 - Init MAC func ptrs.
381 * @hw: pointer to the HW structure
382 **/
383static s32 igb_init_mac_params_82575(struct e1000_hw *hw)
384{
385 struct e1000_mac_info *mac = &hw->mac;
386 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
387
388 /* Set mta register count */
389 mac->mta_reg_count = 128;
390 /* Set rar entry count */
391 switch (mac->type) {
392 case e1000_82576:
393 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
394 break;
395 case e1000_82580:
396 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
397 break;
398 case e1000_i350:
399 case e1000_i354:
400 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
401 break;
402 default:
403 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
404 break;
405 }
406 /* reset */
407 if (mac->type >= e1000_82580)
408 mac->ops.reset_hw = igb_reset_hw_82580;
409 else
410 mac->ops.reset_hw = igb_reset_hw_82575;
411
412 if (mac->type >= e1000_i210) {
413 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_i210;
414 mac->ops.release_swfw_sync = igb_release_swfw_sync_i210;
415
416 } else {
417 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_82575;
418 mac->ops.release_swfw_sync = igb_release_swfw_sync_82575;
419 }
420
421 /* Set if part includes ASF firmware */
422 mac->asf_firmware_present = true;
423 /* Set if manageability features are enabled. */
424 mac->arc_subsystem_valid =
425 (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK)
426 ? true : false;
427 /* enable EEE on i350 parts and later parts */
428 if (mac->type >= e1000_i350)
429 dev_spec->eee_disable = false;
430 else
431 dev_spec->eee_disable = true;
432 /* Allow a single clear of the SW semaphore on I210 and newer */
433 if (mac->type >= e1000_i210)
434 dev_spec->clear_semaphore_once = true;
435 /* physical interface link setup */
436 mac->ops.setup_physical_interface =
437 (hw->phy.media_type == e1000_media_type_copper)
438 ? igb_setup_copper_link_82575
439 : igb_setup_serdes_link_82575;
440
441 if (mac->type == e1000_82580) {
442 switch (hw->device_id) {
443 /* feature not supported on these id's */
444 case E1000_DEV_ID_DH89XXCC_SGMII:
445 case E1000_DEV_ID_DH89XXCC_SERDES:
446 case E1000_DEV_ID_DH89XXCC_BACKPLANE:
447 case E1000_DEV_ID_DH89XXCC_SFP:
448 break;
449 default:
450 hw->dev_spec._82575.mas_capable = true;
451 break;
452 }
453 }
454 return 0;
455}
456
457/**
458 * igb_set_sfp_media_type_82575 - derives SFP module media type.
459 * @hw: pointer to the HW structure
460 *
461 * The media type is chosen based on SFP module.
462 * compatibility flags retrieved from SFP ID EEPROM.
463 **/
464static s32 igb_set_sfp_media_type_82575(struct e1000_hw *hw)
465{
466 s32 ret_val = E1000_ERR_CONFIG;
467 u32 ctrl_ext = 0;
468 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
469 struct e1000_sfp_flags *eth_flags = &dev_spec->eth_flags;
470 u8 tranceiver_type = 0;
471 s32 timeout = 3;
472
473 /* Turn I2C interface ON and power on sfp cage */
474 ctrl_ext = rd32(E1000_CTRL_EXT);
475 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
476 wr32(E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);
477
478 wrfl();
479
480 /* Read SFP module data */
481 while (timeout) {
482 ret_val = igb_read_sfp_data_byte(hw,
483 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET),
484 &tranceiver_type);
485 if (ret_val == 0)
486 break;
487 msleep(100);
488 timeout--;
489 }
490 if (ret_val != 0)
491 goto out;
492
493 ret_val = igb_read_sfp_data_byte(hw,
494 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),
495 (u8 *)eth_flags);
496 if (ret_val != 0)
497 goto out;
498
499 /* Check if there is some SFP module plugged and powered */
500 if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||
501 (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) {
502 dev_spec->module_plugged = true;
503 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) {
504 hw->phy.media_type = e1000_media_type_internal_serdes;
505 } else if (eth_flags->e100_base_fx) {
506 dev_spec->sgmii_active = true;
507 hw->phy.media_type = e1000_media_type_internal_serdes;
508 } else if (eth_flags->e1000_base_t) {
509 dev_spec->sgmii_active = true;
510 hw->phy.media_type = e1000_media_type_copper;
511 } else {
512 hw->phy.media_type = e1000_media_type_unknown;
513 hw_dbg("PHY module has not been recognized\n");
514 goto out;
515 }
516 } else {
517 hw->phy.media_type = e1000_media_type_unknown;
518 }
519 ret_val = 0;
520out:
521 /* Restore I2C interface setting */
522 wr32(E1000_CTRL_EXT, ctrl_ext);
523 return ret_val;
524}
525
526static s32 igb_get_invariants_82575(struct e1000_hw *hw)
527{
528 struct e1000_mac_info *mac = &hw->mac;
529 struct e1000_dev_spec_82575 * dev_spec = &hw->dev_spec._82575;
530 s32 ret_val;
531 u32 ctrl_ext = 0;
532 u32 link_mode = 0;
533
534 switch (hw->device_id) {
535 case E1000_DEV_ID_82575EB_COPPER:
536 case E1000_DEV_ID_82575EB_FIBER_SERDES:
537 case E1000_DEV_ID_82575GB_QUAD_COPPER:
538 mac->type = e1000_82575;
539 break;
540 case E1000_DEV_ID_82576:
541 case E1000_DEV_ID_82576_NS:
542 case E1000_DEV_ID_82576_NS_SERDES:
543 case E1000_DEV_ID_82576_FIBER:
544 case E1000_DEV_ID_82576_SERDES:
545 case E1000_DEV_ID_82576_QUAD_COPPER:
546 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
547 case E1000_DEV_ID_82576_SERDES_QUAD:
548 mac->type = e1000_82576;
549 break;
550 case E1000_DEV_ID_82580_COPPER:
551 case E1000_DEV_ID_82580_FIBER:
552 case E1000_DEV_ID_82580_QUAD_FIBER:
553 case E1000_DEV_ID_82580_SERDES:
554 case E1000_DEV_ID_82580_SGMII:
555 case E1000_DEV_ID_82580_COPPER_DUAL:
556 case E1000_DEV_ID_DH89XXCC_SGMII:
557 case E1000_DEV_ID_DH89XXCC_SERDES:
558 case E1000_DEV_ID_DH89XXCC_BACKPLANE:
559 case E1000_DEV_ID_DH89XXCC_SFP:
560 mac->type = e1000_82580;
561 break;
562 case E1000_DEV_ID_I350_COPPER:
563 case E1000_DEV_ID_I350_FIBER:
564 case E1000_DEV_ID_I350_SERDES:
565 case E1000_DEV_ID_I350_SGMII:
566 mac->type = e1000_i350;
567 break;
568 case E1000_DEV_ID_I210_COPPER:
569 case E1000_DEV_ID_I210_FIBER:
570 case E1000_DEV_ID_I210_SERDES:
571 case E1000_DEV_ID_I210_SGMII:
572 case E1000_DEV_ID_I210_COPPER_FLASHLESS:
573 case E1000_DEV_ID_I210_SERDES_FLASHLESS:
574 mac->type = e1000_i210;
575 break;
576 case E1000_DEV_ID_I211_COPPER:
577 mac->type = e1000_i211;
578 break;
579 case E1000_DEV_ID_I354_BACKPLANE_1GBPS:
580 case E1000_DEV_ID_I354_SGMII:
581 case E1000_DEV_ID_I354_BACKPLANE_2_5GBPS:
582 mac->type = e1000_i354;
583 break;
584 default:
585 return -E1000_ERR_MAC_INIT;
586 break;
587 }
588
589 /* Set media type */
590 /* The 82575 uses bits 22:23 for link mode. The mode can be changed
591 * based on the EEPROM. We cannot rely upon device ID. There
592 * is no distinguishable difference between fiber and internal
593 * SerDes mode on the 82575. There can be an external PHY attached
594 * on the SGMII interface. For this, we'll set sgmii_active to true.
595 */
596 hw->phy.media_type = e1000_media_type_copper;
597 dev_spec->sgmii_active = false;
598 dev_spec->module_plugged = false;
599
600 ctrl_ext = rd32(E1000_CTRL_EXT);
601
602 link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK;
603 switch (link_mode) {
604 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
605 hw->phy.media_type = e1000_media_type_internal_serdes;
606 break;
607 case E1000_CTRL_EXT_LINK_MODE_SGMII:
608 /* Get phy control interface type set (MDIO vs. I2C)*/
609 if (igb_sgmii_uses_mdio_82575(hw)) {
610 hw->phy.media_type = e1000_media_type_copper;
611 dev_spec->sgmii_active = true;
612 break;
613 }
614 /* fall through for I2C based SGMII */
615 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
616 /* read media type from SFP EEPROM */
617 ret_val = igb_set_sfp_media_type_82575(hw);
618 if ((ret_val != 0) ||
619 (hw->phy.media_type == e1000_media_type_unknown)) {
620 /* If media type was not identified then return media
621 * type defined by the CTRL_EXT settings.
622 */
623 hw->phy.media_type = e1000_media_type_internal_serdes;
624
625 if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) {
626 hw->phy.media_type = e1000_media_type_copper;
627 dev_spec->sgmii_active = true;
628 }
629
630 break;
631 }
632
633 /* do not change link mode for 100BaseFX */
634 if (dev_spec->eth_flags.e100_base_fx)
635 break;
636
637 /* change current link mode setting */
638 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
639
640 if (hw->phy.media_type == e1000_media_type_copper)
641 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII;
642 else
643 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
644
645 wr32(E1000_CTRL_EXT, ctrl_ext);
646
647 break;
648 default:
649 break;
650 }
651
652 /* mac initialization and operations */
653 ret_val = igb_init_mac_params_82575(hw);
654 if (ret_val)
655 goto out;
656
657 /* NVM initialization */
658 ret_val = igb_init_nvm_params_82575(hw);
659 switch (hw->mac.type) {
660 case e1000_i210:
661 case e1000_i211:
662 ret_val = igb_init_nvm_params_i210(hw);
663 break;
664 default:
665 break;
666 }
667
668 if (ret_val)
669 goto out;
670
671 /* if part supports SR-IOV then initialize mailbox parameters */
672 switch (mac->type) {
673 case e1000_82576:
674 case e1000_i350:
675 igb_init_mbx_params_pf(hw);
676 break;
677 default:
678 break;
679 }
680
681 /* setup PHY parameters */
682 ret_val = igb_init_phy_params_82575(hw);
683
684out:
685 return ret_val;
686}
687
688/**
689 * igb_acquire_phy_82575 - Acquire rights to access PHY
690 * @hw: pointer to the HW structure
691 *
692 * Acquire access rights to the correct PHY. This is a
693 * function pointer entry point called by the api module.
694 **/
695static s32 igb_acquire_phy_82575(struct e1000_hw *hw)
696{
697 u16 mask = E1000_SWFW_PHY0_SM;
698
699 if (hw->bus.func == E1000_FUNC_1)
700 mask = E1000_SWFW_PHY1_SM;
701 else if (hw->bus.func == E1000_FUNC_2)
702 mask = E1000_SWFW_PHY2_SM;
703 else if (hw->bus.func == E1000_FUNC_3)
704 mask = E1000_SWFW_PHY3_SM;
705
706 return hw->mac.ops.acquire_swfw_sync(hw, mask);
707}
708
709/**
710 * igb_release_phy_82575 - Release rights to access PHY
711 * @hw: pointer to the HW structure
712 *
713 * A wrapper to release access rights to the correct PHY. This is a
714 * function pointer entry point called by the api module.
715 **/
716static void igb_release_phy_82575(struct e1000_hw *hw)
717{
718 u16 mask = E1000_SWFW_PHY0_SM;
719
720 if (hw->bus.func == E1000_FUNC_1)
721 mask = E1000_SWFW_PHY1_SM;
722 else if (hw->bus.func == E1000_FUNC_2)
723 mask = E1000_SWFW_PHY2_SM;
724 else if (hw->bus.func == E1000_FUNC_3)
725 mask = E1000_SWFW_PHY3_SM;
726
727 hw->mac.ops.release_swfw_sync(hw, mask);
728}
729
730/**
731 * igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
732 * @hw: pointer to the HW structure
733 * @offset: register offset to be read
734 * @data: pointer to the read data
735 *
736 * Reads the PHY register at offset using the serial gigabit media independent
737 * interface and stores the retrieved information in data.
738 **/
739static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
740 u16 *data)
741{
742 s32 ret_val = -E1000_ERR_PARAM;
743
744 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
745 hw_dbg("PHY Address %u is out of range\n", offset);
746 goto out;
747 }
748
749 ret_val = hw->phy.ops.acquire(hw);
750 if (ret_val)
751 goto out;
752
753 ret_val = igb_read_phy_reg_i2c(hw, offset, data);
754
755 hw->phy.ops.release(hw);
756
757out:
758 return ret_val;
759}
760
761/**
762 * igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
763 * @hw: pointer to the HW structure
764 * @offset: register offset to write to
765 * @data: data to write at register offset
766 *
767 * Writes the data to PHY register at the offset using the serial gigabit
768 * media independent interface.
769 **/
770static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
771 u16 data)
772{
773 s32 ret_val = -E1000_ERR_PARAM;
774
775
776 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
777 hw_dbg("PHY Address %d is out of range\n", offset);
778 goto out;
779 }
780
781 ret_val = hw->phy.ops.acquire(hw);
782 if (ret_val)
783 goto out;
784
785 ret_val = igb_write_phy_reg_i2c(hw, offset, data);
786
787 hw->phy.ops.release(hw);
788
789out:
790 return ret_val;
791}
792
793/**
794 * igb_get_phy_id_82575 - Retrieve PHY addr and id
795 * @hw: pointer to the HW structure
796 *
797 * Retrieves the PHY address and ID for both PHY's which do and do not use
798 * sgmi interface.
799 **/
800static s32 igb_get_phy_id_82575(struct e1000_hw *hw)
801{
802 struct e1000_phy_info *phy = &hw->phy;
803 s32 ret_val = 0;
804 u16 phy_id;
805 u32 ctrl_ext;
806 u32 mdic;
807
808 /* Extra read required for some PHY's on i354 */
809 if (hw->mac.type == e1000_i354)
810 igb_get_phy_id(hw);
811
812 /* For SGMII PHYs, we try the list of possible addresses until
813 * we find one that works. For non-SGMII PHYs
814 * (e.g. integrated copper PHYs), an address of 1 should
815 * work. The result of this function should mean phy->phy_addr
816 * and phy->id are set correctly.
817 */
818 if (!(igb_sgmii_active_82575(hw))) {
819 phy->addr = 1;
820 ret_val = igb_get_phy_id(hw);
821 goto out;
822 }
823
824 if (igb_sgmii_uses_mdio_82575(hw)) {
825 switch (hw->mac.type) {
826 case e1000_82575:
827 case e1000_82576:
828 mdic = rd32(E1000_MDIC);
829 mdic &= E1000_MDIC_PHY_MASK;
830 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
831 break;
832 case e1000_82580:
833 case e1000_i350:
834 case e1000_i354:
835 case e1000_i210:
836 case e1000_i211:
837 mdic = rd32(E1000_MDICNFG);
838 mdic &= E1000_MDICNFG_PHY_MASK;
839 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
840 break;
841 default:
842 ret_val = -E1000_ERR_PHY;
843 goto out;
844 break;
845 }
846 ret_val = igb_get_phy_id(hw);
847 goto out;
848 }
849
850 /* Power on sgmii phy if it is disabled */
851 ctrl_ext = rd32(E1000_CTRL_EXT);
852 wr32(E1000_CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
853 wrfl();
854 msleep(300);
855
856 /* The address field in the I2CCMD register is 3 bits and 0 is invalid.
857 * Therefore, we need to test 1-7
858 */
859 for (phy->addr = 1; phy->addr < 8; phy->addr++) {
860 ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
861 if (ret_val == 0) {
862 hw_dbg("Vendor ID 0x%08X read at address %u\n",
863 phy_id, phy->addr);
864 /* At the time of this writing, The M88 part is
865 * the only supported SGMII PHY product.
866 */
867 if (phy_id == M88_VENDOR)
868 break;
869 } else {
870 hw_dbg("PHY address %u was unreadable\n", phy->addr);
871 }
872 }
873
874 /* A valid PHY type couldn't be found. */
875 if (phy->addr == 8) {
876 phy->addr = 0;
877 ret_val = -E1000_ERR_PHY;
878 goto out;
879 } else {
880 ret_val = igb_get_phy_id(hw);
881 }
882
883 /* restore previous sfp cage power state */
884 wr32(E1000_CTRL_EXT, ctrl_ext);
885
886out:
887 return ret_val;
888}
889
890/**
891 * igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset
892 * @hw: pointer to the HW structure
893 *
894 * Resets the PHY using the serial gigabit media independent interface.
895 **/
896static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
897{
898 s32 ret_val;
899
900 /* This isn't a true "hard" reset, but is the only reset
901 * available to us at this time.
902 */
903
904 hw_dbg("Soft resetting SGMII attached PHY...\n");
905
906 /* SFP documentation requires the following to configure the SPF module
907 * to work on SGMII. No further documentation is given.
908 */
909 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
910 if (ret_val)
911 goto out;
912
913 ret_val = igb_phy_sw_reset(hw);
914
915out:
916 return ret_val;
917}
918
919/**
920 * igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
921 * @hw: pointer to the HW structure
922 * @active: true to enable LPLU, false to disable
923 *
924 * Sets the LPLU D0 state according to the active flag. When
925 * activating LPLU this function also disables smart speed
926 * and vice versa. LPLU will not be activated unless the
927 * device autonegotiation advertisement meets standards of
928 * either 10 or 10/100 or 10/100/1000 at all duplexes.
929 * This is a function pointer entry point only called by
930 * PHY setup routines.
931 **/
932static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
933{
934 struct e1000_phy_info *phy = &hw->phy;
935 s32 ret_val;
936 u16 data;
937
938 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
939 if (ret_val)
940 goto out;
941
942 if (active) {
943 data |= IGP02E1000_PM_D0_LPLU;
944 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
945 data);
946 if (ret_val)
947 goto out;
948
949 /* When LPLU is enabled, we should disable SmartSpeed */
950 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
951 &data);
952 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
953 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
954 data);
955 if (ret_val)
956 goto out;
957 } else {
958 data &= ~IGP02E1000_PM_D0_LPLU;
959 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
960 data);
961 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
962 * during Dx states where the power conservation is most
963 * important. During driver activity we should enable
964 * SmartSpeed, so performance is maintained.
965 */
966 if (phy->smart_speed == e1000_smart_speed_on) {
967 ret_val = phy->ops.read_reg(hw,
968 IGP01E1000_PHY_PORT_CONFIG, &data);
969 if (ret_val)
970 goto out;
971
972 data |= IGP01E1000_PSCFR_SMART_SPEED;
973 ret_val = phy->ops.write_reg(hw,
974 IGP01E1000_PHY_PORT_CONFIG, data);
975 if (ret_val)
976 goto out;
977 } else if (phy->smart_speed == e1000_smart_speed_off) {
978 ret_val = phy->ops.read_reg(hw,
979 IGP01E1000_PHY_PORT_CONFIG, &data);
980 if (ret_val)
981 goto out;
982
983 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
984 ret_val = phy->ops.write_reg(hw,
985 IGP01E1000_PHY_PORT_CONFIG, data);
986 if (ret_val)
987 goto out;
988 }
989 }
990
991out:
992 return ret_val;
993}
994
995/**
996 * igb_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
997 * @hw: pointer to the HW structure
998 * @active: true to enable LPLU, false to disable
999 *
1000 * Sets the LPLU D0 state according to the active flag. When
1001 * activating LPLU this function also disables smart speed
1002 * and vice versa. LPLU will not be activated unless the
1003 * device autonegotiation advertisement meets standards of
1004 * either 10 or 10/100 or 10/100/1000 at all duplexes.
1005 * This is a function pointer entry point only called by
1006 * PHY setup routines.
1007 **/
1008static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
1009{
1010 struct e1000_phy_info *phy = &hw->phy;
1011 s32 ret_val = 0;
1012 u16 data;
1013
1014 data = rd32(E1000_82580_PHY_POWER_MGMT);
1015
1016 if (active) {
1017 data |= E1000_82580_PM_D0_LPLU;
1018
1019 /* When LPLU is enabled, we should disable SmartSpeed */
1020 data &= ~E1000_82580_PM_SPD;
1021 } else {
1022 data &= ~E1000_82580_PM_D0_LPLU;
1023
1024 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
1025 * during Dx states where the power conservation is most
1026 * important. During driver activity we should enable
1027 * SmartSpeed, so performance is maintained.
1028 */
1029 if (phy->smart_speed == e1000_smart_speed_on)
1030 data |= E1000_82580_PM_SPD;
1031 else if (phy->smart_speed == e1000_smart_speed_off)
1032 data &= ~E1000_82580_PM_SPD; }
1033
1034 wr32(E1000_82580_PHY_POWER_MGMT, data);
1035 return ret_val;
1036}
1037
1038/**
1039 * igb_set_d3_lplu_state_82580 - Sets low power link up state for D3
1040 * @hw: pointer to the HW structure
1041 * @active: boolean used to enable/disable lplu
1042 *
1043 * Success returns 0, Failure returns 1
1044 *
1045 * The low power link up (lplu) state is set to the power management level D3
1046 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1047 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1048 * is used during Dx states where the power conservation is most important.
1049 * During driver activity, SmartSpeed should be enabled so performance is
1050 * maintained.
1051 **/
1052static s32 igb_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
1053{
1054 struct e1000_phy_info *phy = &hw->phy;
1055 s32 ret_val = 0;
1056 u16 data;
1057
1058 data = rd32(E1000_82580_PHY_POWER_MGMT);
1059
1060 if (!active) {
1061 data &= ~E1000_82580_PM_D3_LPLU;
1062 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
1063 * during Dx states where the power conservation is most
1064 * important. During driver activity we should enable
1065 * SmartSpeed, so performance is maintained.
1066 */
1067 if (phy->smart_speed == e1000_smart_speed_on)
1068 data |= E1000_82580_PM_SPD;
1069 else if (phy->smart_speed == e1000_smart_speed_off)
1070 data &= ~E1000_82580_PM_SPD;
1071 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1072 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1073 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1074 data |= E1000_82580_PM_D3_LPLU;
1075 /* When LPLU is enabled, we should disable SmartSpeed */
1076 data &= ~E1000_82580_PM_SPD;
1077 }
1078
1079 wr32(E1000_82580_PHY_POWER_MGMT, data);
1080 return ret_val;
1081}
1082
1083/**
1084 * igb_acquire_nvm_82575 - Request for access to EEPROM
1085 * @hw: pointer to the HW structure
1086 *
1087 * Acquire the necessary semaphores for exclusive access to the EEPROM.
1088 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
1089 * Return successful if access grant bit set, else clear the request for
1090 * EEPROM access and return -E1000_ERR_NVM (-1).
1091 **/
1092static s32 igb_acquire_nvm_82575(struct e1000_hw *hw)
1093{
1094 s32 ret_val;
1095
1096 ret_val = hw->mac.ops.acquire_swfw_sync(hw, E1000_SWFW_EEP_SM);
1097 if (ret_val)
1098 goto out;
1099
1100 ret_val = igb_acquire_nvm(hw);
1101
1102 if (ret_val)
1103 hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM);
1104
1105out:
1106 return ret_val;
1107}
1108
1109/**
1110 * igb_release_nvm_82575 - Release exclusive access to EEPROM
1111 * @hw: pointer to the HW structure
1112 *
1113 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
1114 * then release the semaphores acquired.
1115 **/
1116static void igb_release_nvm_82575(struct e1000_hw *hw)
1117{
1118 igb_release_nvm(hw);
1119 hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM);
1120}
1121
1122/**
1123 * igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
1124 * @hw: pointer to the HW structure
1125 * @mask: specifies which semaphore to acquire
1126 *
1127 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
1128 * will also specify which port we're acquiring the lock for.
1129 **/
1130static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1131{
1132 u32 swfw_sync;
1133 u32 swmask = mask;
1134 u32 fwmask = mask << 16;
1135 s32 ret_val = 0;
1136 s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
1137
1138 while (i < timeout) {
1139 if (igb_get_hw_semaphore(hw)) {
1140 ret_val = -E1000_ERR_SWFW_SYNC;
1141 goto out;
1142 }
1143
1144 swfw_sync = rd32(E1000_SW_FW_SYNC);
1145 if (!(swfw_sync & (fwmask | swmask)))
1146 break;
1147
1148 /* Firmware currently using resource (fwmask)
1149 * or other software thread using resource (swmask)
1150 */
1151 igb_put_hw_semaphore(hw);
1152 mdelay(5);
1153 i++;
1154 }
1155
1156 if (i == timeout) {
1157 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
1158 ret_val = -E1000_ERR_SWFW_SYNC;
1159 goto out;
1160 }
1161
1162 swfw_sync |= swmask;
1163 wr32(E1000_SW_FW_SYNC, swfw_sync);
1164
1165 igb_put_hw_semaphore(hw);
1166
1167out:
1168 return ret_val;
1169}
1170
1171/**
1172 * igb_release_swfw_sync_82575 - Release SW/FW semaphore
1173 * @hw: pointer to the HW structure
1174 * @mask: specifies which semaphore to acquire
1175 *
1176 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
1177 * will also specify which port we're releasing the lock for.
1178 **/
1179static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1180{
1181 u32 swfw_sync;
1182
1183 while (igb_get_hw_semaphore(hw) != 0);
1184 /* Empty */
1185
1186 swfw_sync = rd32(E1000_SW_FW_SYNC);
1187 swfw_sync &= ~mask;
1188 wr32(E1000_SW_FW_SYNC, swfw_sync);
1189
1190 igb_put_hw_semaphore(hw);
1191}
1192
1193/**
1194 * igb_get_cfg_done_82575 - Read config done bit
1195 * @hw: pointer to the HW structure
1196 *
1197 * Read the management control register for the config done bit for
1198 * completion status. NOTE: silicon which is EEPROM-less will fail trying
1199 * to read the config done bit, so an error is *ONLY* logged and returns
1200 * 0. If we were to return with error, EEPROM-less silicon
1201 * would not be able to be reset or change link.
1202 **/
1203static s32 igb_get_cfg_done_82575(struct e1000_hw *hw)
1204{
1205 s32 timeout = PHY_CFG_TIMEOUT;
1206 s32 ret_val = 0;
1207 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
1208
1209 if (hw->bus.func == 1)
1210 mask = E1000_NVM_CFG_DONE_PORT_1;
1211 else if (hw->bus.func == E1000_FUNC_2)
1212 mask = E1000_NVM_CFG_DONE_PORT_2;
1213 else if (hw->bus.func == E1000_FUNC_3)
1214 mask = E1000_NVM_CFG_DONE_PORT_3;
1215
1216 while (timeout) {
1217 if (rd32(E1000_EEMNGCTL) & mask)
1218 break;
1219 msleep(1);
1220 timeout--;
1221 }
1222 if (!timeout)
1223 hw_dbg("MNG configuration cycle has not completed.\n");
1224
1225 /* If EEPROM is not marked present, init the PHY manually */
1226 if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) &&
1227 (hw->phy.type == e1000_phy_igp_3))
1228 igb_phy_init_script_igp3(hw);
1229
1230 return ret_val;
1231}
1232
1233/**
1234 * igb_get_link_up_info_82575 - Get link speed/duplex info
1235 * @hw: pointer to the HW structure
1236 * @speed: stores the current speed
1237 * @duplex: stores the current duplex
1238 *
1239 * This is a wrapper function, if using the serial gigabit media independent
1240 * interface, use PCS to retrieve the link speed and duplex information.
1241 * Otherwise, use the generic function to get the link speed and duplex info.
1242 **/
1243static s32 igb_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
1244 u16 *duplex)
1245{
1246 s32 ret_val;
1247
1248 if (hw->phy.media_type != e1000_media_type_copper)
1249 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, speed,
1250 duplex);
1251 else
1252 ret_val = igb_get_speed_and_duplex_copper(hw, speed,
1253 duplex);
1254
1255 return ret_val;
1256}
1257
1258/**
1259 * igb_check_for_link_82575 - Check for link
1260 * @hw: pointer to the HW structure
1261 *
1262 * If sgmii is enabled, then use the pcs register to determine link, otherwise
1263 * use the generic interface for determining link.
1264 **/
1265static s32 igb_check_for_link_82575(struct e1000_hw *hw)
1266{
1267 s32 ret_val;
1268 u16 speed, duplex;
1269
1270 if (hw->phy.media_type != e1000_media_type_copper) {
1271 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed,
1272 &duplex);
1273 /* Use this flag to determine if link needs to be checked or
1274 * not. If we have link clear the flag so that we do not
1275 * continue to check for link.
1276 */
1277 hw->mac.get_link_status = !hw->mac.serdes_has_link;
1278
1279 /* Configure Flow Control now that Auto-Neg has completed.
1280 * First, we need to restore the desired flow control
1281 * settings because we may have had to re-autoneg with a
1282 * different link partner.
1283 */
1284 ret_val = igb_config_fc_after_link_up(hw);
1285 if (ret_val)
1286 hw_dbg("Error configuring flow control\n");
1287 } else {
1288 ret_val = igb_check_for_copper_link(hw);
1289 }
1290
1291 return ret_val;
1292}
1293
1294/**
1295 * igb_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1296 * @hw: pointer to the HW structure
1297 **/
1298void igb_power_up_serdes_link_82575(struct e1000_hw *hw)
1299{
1300 u32 reg;
1301
1302
1303 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1304 !igb_sgmii_active_82575(hw))
1305 return;
1306
1307 /* Enable PCS to turn on link */
1308 reg = rd32(E1000_PCS_CFG0);
1309 reg |= E1000_PCS_CFG_PCS_EN;
1310 wr32(E1000_PCS_CFG0, reg);
1311
1312 /* Power up the laser */
1313 reg = rd32(E1000_CTRL_EXT);
1314 reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1315 wr32(E1000_CTRL_EXT, reg);
1316
1317 /* flush the write to verify completion */
1318 wrfl();
1319 msleep(1);
1320}
1321
1322/**
1323 * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1324 * @hw: pointer to the HW structure
1325 * @speed: stores the current speed
1326 * @duplex: stores the current duplex
1327 *
1328 * Using the physical coding sub-layer (PCS), retrieve the current speed and
1329 * duplex, then store the values in the pointers provided.
1330 **/
1331static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed,
1332 u16 *duplex)
1333{
1334 struct e1000_mac_info *mac = &hw->mac;
1335 u32 pcs, status;
1336
1337 /* Set up defaults for the return values of this function */
1338 mac->serdes_has_link = false;
1339 *speed = 0;
1340 *duplex = 0;
1341
1342 /* Read the PCS Status register for link state. For non-copper mode,
1343 * the status register is not accurate. The PCS status register is
1344 * used instead.
1345 */
1346 pcs = rd32(E1000_PCS_LSTAT);
1347
1348 /* The link up bit determines when link is up on autoneg. The sync ok
1349 * gets set once both sides sync up and agree upon link. Stable link
1350 * can be determined by checking for both link up and link sync ok
1351 */
1352 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) {
1353 mac->serdes_has_link = true;
1354
1355 /* Detect and store PCS speed */
1356 if (pcs & E1000_PCS_LSTS_SPEED_1000)
1357 *speed = SPEED_1000;
1358 else if (pcs & E1000_PCS_LSTS_SPEED_100)
1359 *speed = SPEED_100;
1360 else
1361 *speed = SPEED_10;
1362
1363 /* Detect and store PCS duplex */
1364 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL)
1365 *duplex = FULL_DUPLEX;
1366 else
1367 *duplex = HALF_DUPLEX;
1368
1369 /* Check if it is an I354 2.5Gb backplane connection. */
1370 if (mac->type == e1000_i354) {
1371 status = rd32(E1000_STATUS);
1372 if ((status & E1000_STATUS_2P5_SKU) &&
1373 !(status & E1000_STATUS_2P5_SKU_OVER)) {
1374 *speed = SPEED_2500;
1375 *duplex = FULL_DUPLEX;
1376 hw_dbg("2500 Mbs, ");
1377 hw_dbg("Full Duplex\n");
1378 }
1379 }
1380
1381 }
1382
1383 return 0;
1384}
1385
1386/**
1387 * igb_shutdown_serdes_link_82575 - Remove link during power down
1388 * @hw: pointer to the HW structure
1389 *
1390 * In the case of fiber serdes, shut down optics and PCS on driver unload
1391 * when management pass thru is not enabled.
1392 **/
1393void igb_shutdown_serdes_link_82575(struct e1000_hw *hw)
1394{
1395 u32 reg;
1396
1397 if (hw->phy.media_type != e1000_media_type_internal_serdes &&
1398 igb_sgmii_active_82575(hw))
1399 return;
1400
1401 if (!igb_enable_mng_pass_thru(hw)) {
1402 /* Disable PCS to turn off link */
1403 reg = rd32(E1000_PCS_CFG0);
1404 reg &= ~E1000_PCS_CFG_PCS_EN;
1405 wr32(E1000_PCS_CFG0, reg);
1406
1407 /* shutdown the laser */
1408 reg = rd32(E1000_CTRL_EXT);
1409 reg |= E1000_CTRL_EXT_SDP3_DATA;
1410 wr32(E1000_CTRL_EXT, reg);
1411
1412 /* flush the write to verify completion */
1413 wrfl();
1414 msleep(1);
1415 }
1416}
1417
1418/**
1419 * igb_reset_hw_82575 - Reset hardware
1420 * @hw: pointer to the HW structure
1421 *
1422 * This resets the hardware into a known state. This is a
1423 * function pointer entry point called by the api module.
1424 **/
1425static s32 igb_reset_hw_82575(struct e1000_hw *hw)
1426{
1427 u32 ctrl;
1428 s32 ret_val;
1429
1430 /* Prevent the PCI-E bus from sticking if there is no TLP connection
1431 * on the last TLP read/write transaction when MAC is reset.
1432 */
1433 ret_val = igb_disable_pcie_master(hw);
1434 if (ret_val)
1435 hw_dbg("PCI-E Master disable polling has failed.\n");
1436
1437 /* set the completion timeout for interface */
1438 ret_val = igb_set_pcie_completion_timeout(hw);
1439 if (ret_val) {
1440 hw_dbg("PCI-E Set completion timeout has failed.\n");
1441 }
1442
1443 hw_dbg("Masking off all interrupts\n");
1444 wr32(E1000_IMC, 0xffffffff);
1445
1446 wr32(E1000_RCTL, 0);
1447 wr32(E1000_TCTL, E1000_TCTL_PSP);
1448 wrfl();
1449
1450 msleep(10);
1451
1452 ctrl = rd32(E1000_CTRL);
1453
1454 hw_dbg("Issuing a global reset to MAC\n");
1455 wr32(E1000_CTRL, ctrl | E1000_CTRL_RST);
1456
1457 ret_val = igb_get_auto_rd_done(hw);
1458 if (ret_val) {
1459 /* When auto config read does not complete, do not
1460 * return with an error. This can happen in situations
1461 * where there is no eeprom and prevents getting link.
1462 */
1463 hw_dbg("Auto Read Done did not complete\n");
1464 }
1465
1466 /* If EEPROM is not present, run manual init scripts */
1467 if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0)
1468 igb_reset_init_script_82575(hw);
1469
1470 /* Clear any pending interrupt events. */
1471 wr32(E1000_IMC, 0xffffffff);
1472 rd32(E1000_ICR);
1473
1474 /* Install any alternate MAC address into RAR0 */
1475 ret_val = igb_check_alt_mac_addr(hw);
1476
1477 return ret_val;
1478}
1479
1480/**
1481 * igb_init_hw_82575 - Initialize hardware
1482 * @hw: pointer to the HW structure
1483 *
1484 * This inits the hardware readying it for operation.
1485 **/
1486static s32 igb_init_hw_82575(struct e1000_hw *hw)
1487{
1488 struct e1000_mac_info *mac = &hw->mac;
1489 s32 ret_val;
1490 u16 i, rar_count = mac->rar_entry_count;
1491
1492 /* Initialize identification LED */
1493 ret_val = igb_id_led_init(hw);
1494 if (ret_val) {
1495 hw_dbg("Error initializing identification LED\n");
1496 /* This is not fatal and we should not stop init due to this */
1497 }
1498
1499 /* Disabling VLAN filtering */
1500 hw_dbg("Initializing the IEEE VLAN\n");
1501 if ((hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i354))
1502 igb_clear_vfta_i350(hw);
1503 else
1504 igb_clear_vfta(hw);
1505
1506 /* Setup the receive address */
1507 igb_init_rx_addrs(hw, rar_count);
1508
1509 /* Zero out the Multicast HASH table */
1510 hw_dbg("Zeroing the MTA\n");
1511 for (i = 0; i < mac->mta_reg_count; i++)
1512 array_wr32(E1000_MTA, i, 0);
1513
1514 /* Zero out the Unicast HASH table */
1515 hw_dbg("Zeroing the UTA\n");
1516 for (i = 0; i < mac->uta_reg_count; i++)
1517 array_wr32(E1000_UTA, i, 0);
1518
1519 /* Setup link and flow control */
1520 ret_val = igb_setup_link(hw);
1521
1522 /* Clear all of the statistics registers (clear on read). It is
1523 * important that we do this after we have tried to establish link
1524 * because the symbol error count will increment wildly if there
1525 * is no link.
1526 */
1527 igb_clear_hw_cntrs_82575(hw);
1528 return ret_val;
1529}
1530
1531/**
1532 * igb_setup_copper_link_82575 - Configure copper link settings
1533 * @hw: pointer to the HW structure
1534 *
1535 * Configures the link for auto-neg or forced speed and duplex. Then we check
1536 * for link, once link is established calls to configure collision distance
1537 * and flow control are called.
1538 **/
1539static s32 igb_setup_copper_link_82575(struct e1000_hw *hw)
1540{
1541 u32 ctrl;
1542 s32 ret_val;
1543 u32 phpm_reg;
1544
1545 ctrl = rd32(E1000_CTRL);
1546 ctrl |= E1000_CTRL_SLU;
1547 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1548 wr32(E1000_CTRL, ctrl);
1549
1550 /* Clear Go Link Disconnect bit on supported devices */
1551 switch (hw->mac.type) {
1552 case e1000_82580:
1553 case e1000_i350:
1554 case e1000_i210:
1555 case e1000_i211:
1556 phpm_reg = rd32(E1000_82580_PHY_POWER_MGMT);
1557 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1558 wr32(E1000_82580_PHY_POWER_MGMT, phpm_reg);
1559 break;
1560 default:
1561 break;
1562 }
1563
1564 ret_val = igb_setup_serdes_link_82575(hw);
1565 if (ret_val)
1566 goto out;
1567
1568 if (igb_sgmii_active_82575(hw) && !hw->phy.reset_disable) {
1569 /* allow time for SFP cage time to power up phy */
1570 msleep(300);
1571
1572 ret_val = hw->phy.ops.reset(hw);
1573 if (ret_val) {
1574 hw_dbg("Error resetting the PHY.\n");
1575 goto out;
1576 }
1577 }
1578 switch (hw->phy.type) {
1579 case e1000_phy_i210:
1580 case e1000_phy_m88:
1581 switch (hw->phy.id) {
1582 case I347AT4_E_PHY_ID:
1583 case M88E1112_E_PHY_ID:
1584 case M88E1543_E_PHY_ID:
1585 case I210_I_PHY_ID:
1586 ret_val = igb_copper_link_setup_m88_gen2(hw);
1587 break;
1588 default:
1589 ret_val = igb_copper_link_setup_m88(hw);
1590 break;
1591 }
1592 break;
1593 case e1000_phy_igp_3:
1594 ret_val = igb_copper_link_setup_igp(hw);
1595 break;
1596 case e1000_phy_82580:
1597 ret_val = igb_copper_link_setup_82580(hw);
1598 break;
1599 default:
1600 ret_val = -E1000_ERR_PHY;
1601 break;
1602 }
1603
1604 if (ret_val)
1605 goto out;
1606
1607 ret_val = igb_setup_copper_link(hw);
1608out:
1609 return ret_val;
1610}
1611
1612/**
1613 * igb_setup_serdes_link_82575 - Setup link for serdes
1614 * @hw: pointer to the HW structure
1615 *
1616 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1617 * used on copper connections where the serialized gigabit media independent
1618 * interface (sgmii), or serdes fiber is being used. Configures the link
1619 * for auto-negotiation or forces speed/duplex.
1620 **/
1621static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw)
1622{
1623 u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
1624 bool pcs_autoneg;
1625 s32 ret_val = E1000_SUCCESS;
1626 u16 data;
1627
1628 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1629 !igb_sgmii_active_82575(hw))
1630 return ret_val;
1631
1632
1633 /* On the 82575, SerDes loopback mode persists until it is
1634 * explicitly turned off or a power cycle is performed. A read to
1635 * the register does not indicate its status. Therefore, we ensure
1636 * loopback mode is disabled during initialization.
1637 */
1638 wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1639
1640 /* power on the sfp cage if present and turn on I2C */
1641 ctrl_ext = rd32(E1000_CTRL_EXT);
1642 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1643 ctrl_ext |= E1000_CTRL_I2C_ENA;
1644 wr32(E1000_CTRL_EXT, ctrl_ext);
1645
1646 ctrl_reg = rd32(E1000_CTRL);
1647 ctrl_reg |= E1000_CTRL_SLU;
1648
1649 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) {
1650 /* set both sw defined pins */
1651 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1652
1653 /* Set switch control to serdes energy detect */
1654 reg = rd32(E1000_CONNSW);
1655 reg |= E1000_CONNSW_ENRGSRC;
1656 wr32(E1000_CONNSW, reg);
1657 }
1658
1659 reg = rd32(E1000_PCS_LCTL);
1660
1661 /* default pcs_autoneg to the same setting as mac autoneg */
1662 pcs_autoneg = hw->mac.autoneg;
1663
1664 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1665 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1666 /* sgmii mode lets the phy handle forcing speed/duplex */
1667 pcs_autoneg = true;
1668 /* autoneg time out should be disabled for SGMII mode */
1669 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1670 break;
1671 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1672 /* disable PCS autoneg and support parallel detect only */
1673 pcs_autoneg = false;
1674 default:
1675 if (hw->mac.type == e1000_82575 ||
1676 hw->mac.type == e1000_82576) {
1677 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1678 if (ret_val) {
1679 printk(KERN_DEBUG "NVM Read Error\n\n");
1680 return ret_val;
1681 }
1682
1683 if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
1684 pcs_autoneg = false;
1685 }
1686
1687 /* non-SGMII modes only supports a speed of 1000/Full for the
1688 * link so it is best to just force the MAC and let the pcs
1689 * link either autoneg or be forced to 1000/Full
1690 */
1691 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1692 E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1693
1694 /* set speed of 1000/Full if speed/duplex is forced */
1695 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1696 break;
1697 }
1698
1699 wr32(E1000_CTRL, ctrl_reg);
1700
1701 /* New SerDes mode allows for forcing speed or autonegotiating speed
1702 * at 1gb. Autoneg should be default set by most drivers. This is the
1703 * mode that will be compatible with older link partners and switches.
1704 * However, both are supported by the hardware and some drivers/tools.
1705 */
1706 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1707 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1708
1709 if (pcs_autoneg) {
1710 /* Set PCS register for autoneg */
1711 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1712 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1713
1714 /* Disable force flow control for autoneg */
1715 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;
1716
1717 /* Configure flow control advertisement for autoneg */
1718 anadv_reg = rd32(E1000_PCS_ANADV);
1719 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);
1720 switch (hw->fc.requested_mode) {
1721 case e1000_fc_full:
1722 case e1000_fc_rx_pause:
1723 anadv_reg |= E1000_TXCW_ASM_DIR;
1724 anadv_reg |= E1000_TXCW_PAUSE;
1725 break;
1726 case e1000_fc_tx_pause:
1727 anadv_reg |= E1000_TXCW_ASM_DIR;
1728 break;
1729 default:
1730 break;
1731 }
1732 wr32(E1000_PCS_ANADV, anadv_reg);
1733
1734 hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1735 } else {
1736 /* Set PCS register for forced link */
1737 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */
1738
1739 /* Force flow control for forced link */
1740 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1741
1742 hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1743 }
1744
1745 wr32(E1000_PCS_LCTL, reg);
1746
1747 if (!pcs_autoneg && !igb_sgmii_active_82575(hw))
1748 igb_force_mac_fc(hw);
1749
1750 return ret_val;
1751}
1752
1753/**
1754 * igb_sgmii_active_82575 - Return sgmii state
1755 * @hw: pointer to the HW structure
1756 *
1757 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1758 * which can be enabled for use in the embedded applications. Simply
1759 * return the current state of the sgmii interface.
1760 **/
1761static bool igb_sgmii_active_82575(struct e1000_hw *hw)
1762{
1763 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1764 return dev_spec->sgmii_active;
1765}
1766
1767/**
1768 * igb_reset_init_script_82575 - Inits HW defaults after reset
1769 * @hw: pointer to the HW structure
1770 *
1771 * Inits recommended HW defaults after a reset when there is no EEPROM
1772 * detected. This is only for the 82575.
1773 **/
1774static s32 igb_reset_init_script_82575(struct e1000_hw *hw)
1775{
1776 if (hw->mac.type == e1000_82575) {
1777 hw_dbg("Running reset init script for 82575\n");
1778 /* SerDes configuration via SERDESCTRL */
1779 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C);
1780 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78);
1781 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23);
1782 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15);
1783
1784 /* CCM configuration via CCMCTL register */
1785 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00);
1786 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00);
1787
1788 /* PCIe lanes configuration */
1789 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC);
1790 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF);
1791 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05);
1792 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81);
1793
1794 /* PCIe PLL Configuration */
1795 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47);
1796 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00);
1797 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00);
1798 }
1799
1800 return 0;
1801}
1802
1803/**
1804 * igb_read_mac_addr_82575 - Read device MAC address
1805 * @hw: pointer to the HW structure
1806 **/
1807static s32 igb_read_mac_addr_82575(struct e1000_hw *hw)
1808{
1809 s32 ret_val = 0;
1810
1811 /* If there's an alternate MAC address place it in RAR0
1812 * so that it will override the Si installed default perm
1813 * address.
1814 */
1815 ret_val = igb_check_alt_mac_addr(hw);
1816 if (ret_val)
1817 goto out;
1818
1819 ret_val = igb_read_mac_addr(hw);
1820
1821out:
1822 return ret_val;
1823}
1824
1825/**
1826 * igb_power_down_phy_copper_82575 - Remove link during PHY power down
1827 * @hw: pointer to the HW structure
1828 *
1829 * In the case of a PHY power down to save power, or to turn off link during a
1830 * driver unload, or wake on lan is not enabled, remove the link.
1831 **/
1832void igb_power_down_phy_copper_82575(struct e1000_hw *hw)
1833{
1834 /* If the management interface is not enabled, then power down */
1835 if (!(igb_enable_mng_pass_thru(hw) || igb_check_reset_block(hw)))
1836 igb_power_down_phy_copper(hw);
1837}
1838
1839/**
1840 * igb_clear_hw_cntrs_82575 - Clear device specific hardware counters
1841 * @hw: pointer to the HW structure
1842 *
1843 * Clears the hardware counters by reading the counter registers.
1844 **/
1845static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw)
1846{
1847 igb_clear_hw_cntrs_base(hw);
1848
1849 rd32(E1000_PRC64);
1850 rd32(E1000_PRC127);
1851 rd32(E1000_PRC255);
1852 rd32(E1000_PRC511);
1853 rd32(E1000_PRC1023);
1854 rd32(E1000_PRC1522);
1855 rd32(E1000_PTC64);
1856 rd32(E1000_PTC127);
1857 rd32(E1000_PTC255);
1858 rd32(E1000_PTC511);
1859 rd32(E1000_PTC1023);
1860 rd32(E1000_PTC1522);
1861
1862 rd32(E1000_ALGNERRC);
1863 rd32(E1000_RXERRC);
1864 rd32(E1000_TNCRS);
1865 rd32(E1000_CEXTERR);
1866 rd32(E1000_TSCTC);
1867 rd32(E1000_TSCTFC);
1868
1869 rd32(E1000_MGTPRC);
1870 rd32(E1000_MGTPDC);
1871 rd32(E1000_MGTPTC);
1872
1873 rd32(E1000_IAC);
1874 rd32(E1000_ICRXOC);
1875
1876 rd32(E1000_ICRXPTC);
1877 rd32(E1000_ICRXATC);
1878 rd32(E1000_ICTXPTC);
1879 rd32(E1000_ICTXATC);
1880 rd32(E1000_ICTXQEC);
1881 rd32(E1000_ICTXQMTC);
1882 rd32(E1000_ICRXDMTC);
1883
1884 rd32(E1000_CBTMPC);
1885 rd32(E1000_HTDPMC);
1886 rd32(E1000_CBRMPC);
1887 rd32(E1000_RPTHC);
1888 rd32(E1000_HGPTC);
1889 rd32(E1000_HTCBDPC);
1890 rd32(E1000_HGORCL);
1891 rd32(E1000_HGORCH);
1892 rd32(E1000_HGOTCL);
1893 rd32(E1000_HGOTCH);
1894 rd32(E1000_LENERRS);
1895
1896 /* This register should not be read in copper configurations */
1897 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1898 igb_sgmii_active_82575(hw))
1899 rd32(E1000_SCVPC);
1900}
1901
1902/**
1903 * igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable
1904 * @hw: pointer to the HW structure
1905 *
1906 * After rx enable if managability is enabled then there is likely some
1907 * bad data at the start of the fifo and possibly in the DMA fifo. This
1908 * function clears the fifos and flushes any packets that came in as rx was
1909 * being enabled.
1910 **/
1911void igb_rx_fifo_flush_82575(struct e1000_hw *hw)
1912{
1913 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
1914 int i, ms_wait;
1915
1916 if (hw->mac.type != e1000_82575 ||
1917 !(rd32(E1000_MANC) & E1000_MANC_RCV_TCO_EN))
1918 return;
1919
1920 /* Disable all RX queues */
1921 for (i = 0; i < 4; i++) {
1922 rxdctl[i] = rd32(E1000_RXDCTL(i));
1923 wr32(E1000_RXDCTL(i),
1924 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
1925 }
1926 /* Poll all queues to verify they have shut down */
1927 for (ms_wait = 0; ms_wait < 10; ms_wait++) {
1928 msleep(1);
1929 rx_enabled = 0;
1930 for (i = 0; i < 4; i++)
1931 rx_enabled |= rd32(E1000_RXDCTL(i));
1932 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
1933 break;
1934 }
1935
1936 if (ms_wait == 10)
1937 hw_dbg("Queue disable timed out after 10ms\n");
1938
1939 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
1940 * incoming packets are rejected. Set enable and wait 2ms so that
1941 * any packet that was coming in as RCTL.EN was set is flushed
1942 */
1943 rfctl = rd32(E1000_RFCTL);
1944 wr32(E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
1945
1946 rlpml = rd32(E1000_RLPML);
1947 wr32(E1000_RLPML, 0);
1948
1949 rctl = rd32(E1000_RCTL);
1950 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
1951 temp_rctl |= E1000_RCTL_LPE;
1952
1953 wr32(E1000_RCTL, temp_rctl);
1954 wr32(E1000_RCTL, temp_rctl | E1000_RCTL_EN);
1955 wrfl();
1956 msleep(2);
1957
1958 /* Enable RX queues that were previously enabled and restore our
1959 * previous state
1960 */
1961 for (i = 0; i < 4; i++)
1962 wr32(E1000_RXDCTL(i), rxdctl[i]);
1963 wr32(E1000_RCTL, rctl);
1964 wrfl();
1965
1966 wr32(E1000_RLPML, rlpml);
1967 wr32(E1000_RFCTL, rfctl);
1968
1969 /* Flush receive errors generated by workaround */
1970 rd32(E1000_ROC);
1971 rd32(E1000_RNBC);
1972 rd32(E1000_MPC);
1973}
1974
1975/**
1976 * igb_set_pcie_completion_timeout - set pci-e completion timeout
1977 * @hw: pointer to the HW structure
1978 *
1979 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
1980 * however the hardware default for these parts is 500us to 1ms which is less
1981 * than the 10ms recommended by the pci-e spec. To address this we need to
1982 * increase the value to either 10ms to 200ms for capability version 1 config,
1983 * or 16ms to 55ms for version 2.
1984 **/
1985static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw)
1986{
1987 u32 gcr = rd32(E1000_GCR);
1988 s32 ret_val = 0;
1989 u16 pcie_devctl2;
1990
1991 /* only take action if timeout value is defaulted to 0 */
1992 if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
1993 goto out;
1994
1995 /* if capabilities version is type 1 we can write the
1996 * timeout of 10ms to 200ms through the GCR register
1997 */
1998 if (!(gcr & E1000_GCR_CAP_VER2)) {
1999 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
2000 goto out;
2001 }
2002
2003 /* for version 2 capabilities we need to write the config space
2004 * directly in order to set the completion timeout value for
2005 * 16ms to 55ms
2006 */
2007 ret_val = igb_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2008 &pcie_devctl2);
2009 if (ret_val)
2010 goto out;
2011
2012 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
2013
2014 ret_val = igb_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2015 &pcie_devctl2);
2016out:
2017 /* disable completion timeout resend */
2018 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
2019
2020 wr32(E1000_GCR, gcr);
2021 return ret_val;
2022}
2023
2024/**
2025 * igb_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
2026 * @hw: pointer to the hardware struct
2027 * @enable: state to enter, either enabled or disabled
2028 * @pf: Physical Function pool - do not set anti-spoofing for the PF
2029 *
2030 * enables/disables L2 switch anti-spoofing functionality.
2031 **/
2032void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
2033{
2034 u32 reg_val, reg_offset;
2035
2036 switch (hw->mac.type) {
2037 case e1000_82576:
2038 reg_offset = E1000_DTXSWC;
2039 break;
2040 case e1000_i350:
2041 case e1000_i354:
2042 reg_offset = E1000_TXSWC;
2043 break;
2044 default:
2045 return;
2046 }
2047
2048 reg_val = rd32(reg_offset);
2049 if (enable) {
2050 reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2051 E1000_DTXSWC_VLAN_SPOOF_MASK);
2052 /* The PF can spoof - it has to in order to
2053 * support emulation mode NICs
2054 */
2055 reg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
2056 } else {
2057 reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2058 E1000_DTXSWC_VLAN_SPOOF_MASK);
2059 }
2060 wr32(reg_offset, reg_val);
2061}
2062
2063/**
2064 * igb_vmdq_set_loopback_pf - enable or disable vmdq loopback
2065 * @hw: pointer to the hardware struct
2066 * @enable: state to enter, either enabled or disabled
2067 *
2068 * enables/disables L2 switch loopback functionality.
2069 **/
2070void igb_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
2071{
2072 u32 dtxswc;
2073
2074 switch (hw->mac.type) {
2075 case e1000_82576:
2076 dtxswc = rd32(E1000_DTXSWC);
2077 if (enable)
2078 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2079 else
2080 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2081 wr32(E1000_DTXSWC, dtxswc);
2082 break;
2083 case e1000_i354:
2084 case e1000_i350:
2085 dtxswc = rd32(E1000_TXSWC);
2086 if (enable)
2087 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2088 else
2089 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2090 wr32(E1000_TXSWC, dtxswc);
2091 break;
2092 default:
2093 /* Currently no other hardware supports loopback */
2094 break;
2095 }
2096
2097}
2098
2099/**
2100 * igb_vmdq_set_replication_pf - enable or disable vmdq replication
2101 * @hw: pointer to the hardware struct
2102 * @enable: state to enter, either enabled or disabled
2103 *
2104 * enables/disables replication of packets across multiple pools.
2105 **/
2106void igb_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
2107{
2108 u32 vt_ctl = rd32(E1000_VT_CTL);
2109
2110 if (enable)
2111 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
2112 else
2113 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
2114
2115 wr32(E1000_VT_CTL, vt_ctl);
2116}
2117
2118/**
2119 * igb_read_phy_reg_82580 - Read 82580 MDI control register
2120 * @hw: pointer to the HW structure
2121 * @offset: register offset to be read
2122 * @data: pointer to the read data
2123 *
2124 * Reads the MDI control register in the PHY at offset and stores the
2125 * information read to data.
2126 **/
2127static s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
2128{
2129 s32 ret_val;
2130
2131 ret_val = hw->phy.ops.acquire(hw);
2132 if (ret_val)
2133 goto out;
2134
2135 ret_val = igb_read_phy_reg_mdic(hw, offset, data);
2136
2137 hw->phy.ops.release(hw);
2138
2139out:
2140 return ret_val;
2141}
2142
2143/**
2144 * igb_write_phy_reg_82580 - Write 82580 MDI control register
2145 * @hw: pointer to the HW structure
2146 * @offset: register offset to write to
2147 * @data: data to write to register at offset
2148 *
2149 * Writes data to MDI control register in the PHY at offset.
2150 **/
2151static s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
2152{
2153 s32 ret_val;
2154
2155
2156 ret_val = hw->phy.ops.acquire(hw);
2157 if (ret_val)
2158 goto out;
2159
2160 ret_val = igb_write_phy_reg_mdic(hw, offset, data);
2161
2162 hw->phy.ops.release(hw);
2163
2164out:
2165 return ret_val;
2166}
2167
2168/**
2169 * igb_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2170 * @hw: pointer to the HW structure
2171 *
2172 * This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
2173 * the values found in the EEPROM. This addresses an issue in which these
2174 * bits are not restored from EEPROM after reset.
2175 **/
2176static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw)
2177{
2178 s32 ret_val = 0;
2179 u32 mdicnfg;
2180 u16 nvm_data = 0;
2181
2182 if (hw->mac.type != e1000_82580)
2183 goto out;
2184 if (!igb_sgmii_active_82575(hw))
2185 goto out;
2186
2187 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2188 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2189 &nvm_data);
2190 if (ret_val) {
2191 hw_dbg("NVM Read Error\n");
2192 goto out;
2193 }
2194
2195 mdicnfg = rd32(E1000_MDICNFG);
2196 if (nvm_data & NVM_WORD24_EXT_MDIO)
2197 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
2198 if (nvm_data & NVM_WORD24_COM_MDIO)
2199 mdicnfg |= E1000_MDICNFG_COM_MDIO;
2200 wr32(E1000_MDICNFG, mdicnfg);
2201out:
2202 return ret_val;
2203}
2204
2205/**
2206 * igb_reset_hw_82580 - Reset hardware
2207 * @hw: pointer to the HW structure
2208 *
2209 * This resets function or entire device (all ports, etc.)
2210 * to a known state.
2211 **/
2212static s32 igb_reset_hw_82580(struct e1000_hw *hw)
2213{
2214 s32 ret_val = 0;
2215 /* BH SW mailbox bit in SW_FW_SYNC */
2216 u16 swmbsw_mask = E1000_SW_SYNCH_MB;
2217 u32 ctrl;
2218 bool global_device_reset = hw->dev_spec._82575.global_device_reset;
2219
2220 hw->dev_spec._82575.global_device_reset = false;
2221
2222 /* due to hw errata, global device reset doesn't always
2223 * work on 82580
2224 */
2225 if (hw->mac.type == e1000_82580)
2226 global_device_reset = false;
2227
2228 /* Get current control state. */
2229 ctrl = rd32(E1000_CTRL);
2230
2231 /* Prevent the PCI-E bus from sticking if there is no TLP connection
2232 * on the last TLP read/write transaction when MAC is reset.
2233 */
2234 ret_val = igb_disable_pcie_master(hw);
2235 if (ret_val)
2236 hw_dbg("PCI-E Master disable polling has failed.\n");
2237
2238 hw_dbg("Masking off all interrupts\n");
2239 wr32(E1000_IMC, 0xffffffff);
2240 wr32(E1000_RCTL, 0);
2241 wr32(E1000_TCTL, E1000_TCTL_PSP);
2242 wrfl();
2243
2244 msleep(10);
2245
2246 /* Determine whether or not a global dev reset is requested */
2247 if (global_device_reset &&
2248 hw->mac.ops.acquire_swfw_sync(hw, swmbsw_mask))
2249 global_device_reset = false;
2250
2251 if (global_device_reset &&
2252 !(rd32(E1000_STATUS) & E1000_STAT_DEV_RST_SET))
2253 ctrl |= E1000_CTRL_DEV_RST;
2254 else
2255 ctrl |= E1000_CTRL_RST;
2256
2257 wr32(E1000_CTRL, ctrl);
2258 wrfl();
2259
2260 /* Add delay to insure DEV_RST has time to complete */
2261 if (global_device_reset)
2262 msleep(5);
2263
2264 ret_val = igb_get_auto_rd_done(hw);
2265 if (ret_val) {
2266 /* When auto config read does not complete, do not
2267 * return with an error. This can happen in situations
2268 * where there is no eeprom and prevents getting link.
2269 */
2270 hw_dbg("Auto Read Done did not complete\n");
2271 }
2272
2273 /* clear global device reset status bit */
2274 wr32(E1000_STATUS, E1000_STAT_DEV_RST_SET);
2275
2276 /* Clear any pending interrupt events. */
2277 wr32(E1000_IMC, 0xffffffff);
2278 rd32(E1000_ICR);
2279
2280 ret_val = igb_reset_mdicnfg_82580(hw);
2281 if (ret_val)
2282 hw_dbg("Could not reset MDICNFG based on EEPROM\n");
2283
2284 /* Install any alternate MAC address into RAR0 */
2285 ret_val = igb_check_alt_mac_addr(hw);
2286
2287 /* Release semaphore */
2288 if (global_device_reset)
2289 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
2290
2291 return ret_val;
2292}
2293
2294/**
2295 * igb_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size
2296 * @data: data received by reading RXPBS register
2297 *
2298 * The 82580 uses a table based approach for packet buffer allocation sizes.
2299 * This function converts the retrieved value into the correct table value
2300 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2301 * 0x0 36 72 144 1 2 4 8 16
2302 * 0x8 35 70 140 rsv rsv rsv rsv rsv
2303 */
2304u16 igb_rxpbs_adjust_82580(u32 data)
2305{
2306 u16 ret_val = 0;
2307
2308 if (data < ARRAY_SIZE(e1000_82580_rxpbs_table))
2309 ret_val = e1000_82580_rxpbs_table[data];
2310
2311 return ret_val;
2312}
2313
2314/**
2315 * igb_validate_nvm_checksum_with_offset - Validate EEPROM
2316 * checksum
2317 * @hw: pointer to the HW structure
2318 * @offset: offset in words of the checksum protected region
2319 *
2320 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2321 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
2322 **/
2323static s32 igb_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
2324 u16 offset)
2325{
2326 s32 ret_val = 0;
2327 u16 checksum = 0;
2328 u16 i, nvm_data;
2329
2330 for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
2331 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2332 if (ret_val) {
2333 hw_dbg("NVM Read Error\n");
2334 goto out;
2335 }
2336 checksum += nvm_data;
2337 }
2338
2339 if (checksum != (u16) NVM_SUM) {
2340 hw_dbg("NVM Checksum Invalid\n");
2341 ret_val = -E1000_ERR_NVM;
2342 goto out;
2343 }
2344
2345out:
2346 return ret_val;
2347}
2348
2349/**
2350 * igb_update_nvm_checksum_with_offset - Update EEPROM
2351 * checksum
2352 * @hw: pointer to the HW structure
2353 * @offset: offset in words of the checksum protected region
2354 *
2355 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
2356 * up to the checksum. Then calculates the EEPROM checksum and writes the
2357 * value to the EEPROM.
2358 **/
2359static s32 igb_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2360{
2361 s32 ret_val;
2362 u16 checksum = 0;
2363 u16 i, nvm_data;
2364
2365 for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
2366 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2367 if (ret_val) {
2368 hw_dbg("NVM Read Error while updating checksum.\n");
2369 goto out;
2370 }
2371 checksum += nvm_data;
2372 }
2373 checksum = (u16) NVM_SUM - checksum;
2374 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2375 &checksum);
2376 if (ret_val)
2377 hw_dbg("NVM Write Error while updating checksum.\n");
2378
2379out:
2380 return ret_val;
2381}
2382
2383/**
2384 * igb_validate_nvm_checksum_82580 - Validate EEPROM checksum
2385 * @hw: pointer to the HW structure
2386 *
2387 * Calculates the EEPROM section checksum by reading/adding each word of
2388 * the EEPROM and then verifies that the sum of the EEPROM is
2389 * equal to 0xBABA.
2390 **/
2391static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw)
2392{
2393 s32 ret_val = 0;
2394 u16 eeprom_regions_count = 1;
2395 u16 j, nvm_data;
2396 u16 nvm_offset;
2397
2398 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2399 if (ret_val) {
2400 hw_dbg("NVM Read Error\n");
2401 goto out;
2402 }
2403
2404 if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
2405 /* if checksums compatibility bit is set validate checksums
2406 * for all 4 ports.
2407 */
2408 eeprom_regions_count = 4;
2409 }
2410
2411 for (j = 0; j < eeprom_regions_count; j++) {
2412 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2413 ret_val = igb_validate_nvm_checksum_with_offset(hw,
2414 nvm_offset);
2415 if (ret_val != 0)
2416 goto out;
2417 }
2418
2419out:
2420 return ret_val;
2421}
2422
2423/**
2424 * igb_update_nvm_checksum_82580 - Update EEPROM checksum
2425 * @hw: pointer to the HW structure
2426 *
2427 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2428 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2429 * checksum and writes the value to the EEPROM.
2430 **/
2431static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw)
2432{
2433 s32 ret_val;
2434 u16 j, nvm_data;
2435 u16 nvm_offset;
2436
2437 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2438 if (ret_val) {
2439 hw_dbg("NVM Read Error while updating checksum"
2440 " compatibility bit.\n");
2441 goto out;
2442 }
2443
2444 if ((nvm_data & NVM_COMPATIBILITY_BIT_MASK) == 0) {
2445 /* set compatibility bit to validate checksums appropriately */
2446 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2447 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2448 &nvm_data);
2449 if (ret_val) {
2450 hw_dbg("NVM Write Error while updating checksum"
2451 " compatibility bit.\n");
2452 goto out;
2453 }
2454 }
2455
2456 for (j = 0; j < 4; j++) {
2457 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2458 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
2459 if (ret_val)
2460 goto out;
2461 }
2462
2463out:
2464 return ret_val;
2465}
2466
2467/**
2468 * igb_validate_nvm_checksum_i350 - Validate EEPROM checksum
2469 * @hw: pointer to the HW structure
2470 *
2471 * Calculates the EEPROM section checksum by reading/adding each word of
2472 * the EEPROM and then verifies that the sum of the EEPROM is
2473 * equal to 0xBABA.
2474 **/
2475static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw)
2476{
2477 s32 ret_val = 0;
2478 u16 j;
2479 u16 nvm_offset;
2480
2481 for (j = 0; j < 4; j++) {
2482 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2483 ret_val = igb_validate_nvm_checksum_with_offset(hw,
2484 nvm_offset);
2485 if (ret_val != 0)
2486 goto out;
2487 }
2488
2489out:
2490 return ret_val;
2491}
2492
2493/**
2494 * igb_update_nvm_checksum_i350 - Update EEPROM checksum
2495 * @hw: pointer to the HW structure
2496 *
2497 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2498 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2499 * checksum and writes the value to the EEPROM.
2500 **/
2501static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw)
2502{
2503 s32 ret_val = 0;
2504 u16 j;
2505 u16 nvm_offset;
2506
2507 for (j = 0; j < 4; j++) {
2508 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2509 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
2510 if (ret_val != 0)
2511 goto out;
2512 }
2513
2514out:
2515 return ret_val;
2516}
2517
2518/**
2519 * __igb_access_emi_reg - Read/write EMI register
2520 * @hw: pointer to the HW structure
2521 * @addr: EMI address to program
2522 * @data: pointer to value to read/write from/to the EMI address
2523 * @read: boolean flag to indicate read or write
2524 **/
2525static s32 __igb_access_emi_reg(struct e1000_hw *hw, u16 address,
2526 u16 *data, bool read)
2527{
2528 s32 ret_val = E1000_SUCCESS;
2529
2530 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);
2531 if (ret_val)
2532 return ret_val;
2533
2534 if (read)
2535 ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data);
2536 else
2537 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data);
2538
2539 return ret_val;
2540}
2541
2542/**
2543 * igb_read_emi_reg - Read Extended Management Interface register
2544 * @hw: pointer to the HW structure
2545 * @addr: EMI address to program
2546 * @data: value to be read from the EMI address
2547 **/
2548s32 igb_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data)
2549{
2550 return __igb_access_emi_reg(hw, addr, data, true);
2551}
2552
2553/**
2554 * igb_set_eee_i350 - Enable/disable EEE support
2555 * @hw: pointer to the HW structure
2556 *
2557 * Enable/disable EEE based on setting in dev_spec structure.
2558 *
2559 **/
2560s32 igb_set_eee_i350(struct e1000_hw *hw)
2561{
2562 s32 ret_val = 0;
2563 u32 ipcnfg, eeer;
2564
2565 if ((hw->mac.type < e1000_i350) ||
2566 (hw->phy.media_type != e1000_media_type_copper))
2567 goto out;
2568 ipcnfg = rd32(E1000_IPCNFG);
2569 eeer = rd32(E1000_EEER);
2570
2571 /* enable or disable per user setting */
2572 if (!(hw->dev_spec._82575.eee_disable)) {
2573 u32 eee_su = rd32(E1000_EEE_SU);
2574
2575 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2576 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2577 E1000_EEER_LPI_FC);
2578
2579 /* This bit should not be set in normal operation. */
2580 if (eee_su & E1000_EEE_SU_LPI_CLK_STP)
2581 hw_dbg("LPI Clock Stop Bit should not be set!\n");
2582
2583 } else {
2584 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN |
2585 E1000_IPCNFG_EEE_100M_AN);
2586 eeer &= ~(E1000_EEER_TX_LPI_EN |
2587 E1000_EEER_RX_LPI_EN |
2588 E1000_EEER_LPI_FC);
2589 }
2590 wr32(E1000_IPCNFG, ipcnfg);
2591 wr32(E1000_EEER, eeer);
2592 rd32(E1000_IPCNFG);
2593 rd32(E1000_EEER);
2594out:
2595
2596 return ret_val;
2597}
2598
2599/**
2600 * igb_set_eee_i354 - Enable/disable EEE support
2601 * @hw: pointer to the HW structure
2602 *
2603 * Enable/disable EEE legacy mode based on setting in dev_spec structure.
2604 *
2605 **/
2606s32 igb_set_eee_i354(struct e1000_hw *hw)
2607{
2608 struct e1000_phy_info *phy = &hw->phy;
2609 s32 ret_val = 0;
2610 u16 phy_data;
2611
2612 if ((hw->phy.media_type != e1000_media_type_copper) ||
2613 (phy->id != M88E1543_E_PHY_ID))
2614 goto out;
2615
2616 if (!hw->dev_spec._82575.eee_disable) {
2617 /* Switch to PHY page 18. */
2618 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18);
2619 if (ret_val)
2620 goto out;
2621
2622 ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2623 &phy_data);
2624 if (ret_val)
2625 goto out;
2626
2627 phy_data |= E1000_M88E1543_EEE_CTRL_1_MS;
2628 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2629 phy_data);
2630 if (ret_val)
2631 goto out;
2632
2633 /* Return the PHY to page 0. */
2634 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2635 if (ret_val)
2636 goto out;
2637
2638 /* Turn on EEE advertisement. */
2639 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2640 E1000_EEE_ADV_DEV_I354,
2641 &phy_data);
2642 if (ret_val)
2643 goto out;
2644
2645 phy_data |= E1000_EEE_ADV_100_SUPPORTED |
2646 E1000_EEE_ADV_1000_SUPPORTED;
2647 ret_val = igb_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2648 E1000_EEE_ADV_DEV_I354,
2649 phy_data);
2650 } else {
2651 /* Turn off EEE advertisement. */
2652 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2653 E1000_EEE_ADV_DEV_I354,
2654 &phy_data);
2655 if (ret_val)
2656 goto out;
2657
2658 phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED |
2659 E1000_EEE_ADV_1000_SUPPORTED);
2660 ret_val = igb_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2661 E1000_EEE_ADV_DEV_I354,
2662 phy_data);
2663 }
2664
2665out:
2666 return ret_val;
2667}
2668
2669/**
2670 * igb_get_eee_status_i354 - Get EEE status
2671 * @hw: pointer to the HW structure
2672 * @status: EEE status
2673 *
2674 * Get EEE status by guessing based on whether Tx or Rx LPI indications have
2675 * been received.
2676 **/
2677s32 igb_get_eee_status_i354(struct e1000_hw *hw, bool *status)
2678{
2679 struct e1000_phy_info *phy = &hw->phy;
2680 s32 ret_val = 0;
2681 u16 phy_data;
2682
2683 /* Check if EEE is supported on this device. */
2684 if ((hw->phy.media_type != e1000_media_type_copper) ||
2685 (phy->id != M88E1543_E_PHY_ID))
2686 goto out;
2687
2688 ret_val = igb_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354,
2689 E1000_PCS_STATUS_DEV_I354,
2690 &phy_data);
2691 if (ret_val)
2692 goto out;
2693
2694 *status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD |
2695 E1000_PCS_STATUS_RX_LPI_RCVD) ? true : false;
2696
2697out:
2698 return ret_val;
2699}
2700
2701static const u8 e1000_emc_temp_data[4] = {
2702 E1000_EMC_INTERNAL_DATA,
2703 E1000_EMC_DIODE1_DATA,
2704 E1000_EMC_DIODE2_DATA,
2705 E1000_EMC_DIODE3_DATA
2706};
2707static const u8 e1000_emc_therm_limit[4] = {
2708 E1000_EMC_INTERNAL_THERM_LIMIT,
2709 E1000_EMC_DIODE1_THERM_LIMIT,
2710 E1000_EMC_DIODE2_THERM_LIMIT,
2711 E1000_EMC_DIODE3_THERM_LIMIT
2712};
2713
2714#ifdef CONFIG_IGB_HWMON
2715/**
2716 * igb_get_thermal_sensor_data_generic - Gathers thermal sensor data
2717 * @hw: pointer to hardware structure
2718 *
2719 * Updates the temperatures in mac.thermal_sensor_data
2720 **/
2721static s32 igb_get_thermal_sensor_data_generic(struct e1000_hw *hw)
2722{
2723 s32 status = E1000_SUCCESS;
2724 u16 ets_offset;
2725 u16 ets_cfg;
2726 u16 ets_sensor;
2727 u8 num_sensors;
2728 u8 sensor_index;
2729 u8 sensor_location;
2730 u8 i;
2731 struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
2732
2733 if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0))
2734 return E1000_NOT_IMPLEMENTED;
2735
2736 data->sensor[0].temp = (rd32(E1000_THMJT) & 0xFF);
2737
2738 /* Return the internal sensor only if ETS is unsupported */
2739 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset);
2740 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
2741 return status;
2742
2743 hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg);
2744 if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT)
2745 != NVM_ETS_TYPE_EMC)
2746 return E1000_NOT_IMPLEMENTED;
2747
2748 num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK);
2749 if (num_sensors > E1000_MAX_SENSORS)
2750 num_sensors = E1000_MAX_SENSORS;
2751
2752 for (i = 1; i < num_sensors; i++) {
2753 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor);
2754 sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >>
2755 NVM_ETS_DATA_INDEX_SHIFT);
2756 sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >>
2757 NVM_ETS_DATA_LOC_SHIFT);
2758
2759 if (sensor_location != 0)
2760 hw->phy.ops.read_i2c_byte(hw,
2761 e1000_emc_temp_data[sensor_index],
2762 E1000_I2C_THERMAL_SENSOR_ADDR,
2763 &data->sensor[i].temp);
2764 }
2765 return status;
2766}
2767
2768/**
2769 * igb_init_thermal_sensor_thresh_generic - Sets thermal sensor thresholds
2770 * @hw: pointer to hardware structure
2771 *
2772 * Sets the thermal sensor thresholds according to the NVM map
2773 * and save off the threshold and location values into mac.thermal_sensor_data
2774 **/
2775static s32 igb_init_thermal_sensor_thresh_generic(struct e1000_hw *hw)
2776{
2777 s32 status = E1000_SUCCESS;
2778 u16 ets_offset;
2779 u16 ets_cfg;
2780 u16 ets_sensor;
2781 u8 low_thresh_delta;
2782 u8 num_sensors;
2783 u8 sensor_index;
2784 u8 sensor_location;
2785 u8 therm_limit;
2786 u8 i;
2787 struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
2788
2789 if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0))
2790 return E1000_NOT_IMPLEMENTED;
2791
2792 memset(data, 0, sizeof(struct e1000_thermal_sensor_data));
2793
2794 data->sensor[0].location = 0x1;
2795 data->sensor[0].caution_thresh =
2796 (rd32(E1000_THHIGHTC) & 0xFF);
2797 data->sensor[0].max_op_thresh =
2798 (rd32(E1000_THLOWTC) & 0xFF);
2799
2800 /* Return the internal sensor only if ETS is unsupported */
2801 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset);
2802 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
2803 return status;
2804
2805 hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg);
2806 if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT)
2807 != NVM_ETS_TYPE_EMC)
2808 return E1000_NOT_IMPLEMENTED;
2809
2810 low_thresh_delta = ((ets_cfg & NVM_ETS_LTHRES_DELTA_MASK) >>
2811 NVM_ETS_LTHRES_DELTA_SHIFT);
2812 num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK);
2813
2814 for (i = 1; i <= num_sensors; i++) {
2815 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor);
2816 sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >>
2817 NVM_ETS_DATA_INDEX_SHIFT);
2818 sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >>
2819 NVM_ETS_DATA_LOC_SHIFT);
2820 therm_limit = ets_sensor & NVM_ETS_DATA_HTHRESH_MASK;
2821
2822 hw->phy.ops.write_i2c_byte(hw,
2823 e1000_emc_therm_limit[sensor_index],
2824 E1000_I2C_THERMAL_SENSOR_ADDR,
2825 therm_limit);
2826
2827 if ((i < E1000_MAX_SENSORS) && (sensor_location != 0)) {
2828 data->sensor[i].location = sensor_location;
2829 data->sensor[i].caution_thresh = therm_limit;
2830 data->sensor[i].max_op_thresh = therm_limit -
2831 low_thresh_delta;
2832 }
2833 }
2834 return status;
2835}
2836
2837#endif
2838static struct e1000_mac_operations e1000_mac_ops_82575 = {
2839 .init_hw = igb_init_hw_82575,
2840 .check_for_link = igb_check_for_link_82575,
2841 .rar_set = igb_rar_set,
2842 .read_mac_addr = igb_read_mac_addr_82575,
2843 .get_speed_and_duplex = igb_get_link_up_info_82575,
2844#ifdef CONFIG_IGB_HWMON
2845 .get_thermal_sensor_data = igb_get_thermal_sensor_data_generic,
2846 .init_thermal_sensor_thresh = igb_init_thermal_sensor_thresh_generic,
2847#endif
2848};
2849
2850static struct e1000_phy_operations e1000_phy_ops_82575 = {
2851 .acquire = igb_acquire_phy_82575,
2852 .get_cfg_done = igb_get_cfg_done_82575,
2853 .release = igb_release_phy_82575,
2854 .write_i2c_byte = igb_write_i2c_byte,
2855 .read_i2c_byte = igb_read_i2c_byte,
2856};
2857
2858static struct e1000_nvm_operations e1000_nvm_ops_82575 = {
2859 .acquire = igb_acquire_nvm_82575,
2860 .read = igb_read_nvm_eerd,
2861 .release = igb_release_nvm_82575,
2862 .write = igb_write_nvm_spi,
2863};
2864
2865const struct e1000_info e1000_82575_info = {
2866 .get_invariants = igb_get_invariants_82575,
2867 .mac_ops = &e1000_mac_ops_82575,
2868 .phy_ops = &e1000_phy_ops_82575,
2869 .nvm_ops = &e1000_nvm_ops_82575,
2870};
2871