Loading...
Note: File does not exist in v6.13.7.
1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
4 * Copyright(c) 2013 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * The full GNU General Public License is included in this distribution in
16 * the file called "COPYING".
17 *
18 * Contact Information:
19 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
20 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
21 *
22 ******************************************************************************/
23
24#ifndef _I40E_TXRX_H_
25#define _I40E_TXRX_H_
26
27/* Interrupt Throttling and Rate Limiting (storm control) Goodies */
28
29#define I40E_MAX_ITR 0x0FF0 /* reg uses 2 usec resolution */
30#define I40E_MIN_ITR 0x0004 /* reg uses 2 usec resolution */
31#define I40E_MAX_IRATE 0x03F
32#define I40E_MIN_IRATE 0x001
33#define I40E_IRATE_USEC_RESOLUTION 4
34#define I40E_ITR_100K 0x0005
35#define I40E_ITR_20K 0x0019
36#define I40E_ITR_8K 0x003E
37#define I40E_ITR_4K 0x007A
38#define I40E_ITR_RX_DEF I40E_ITR_8K
39#define I40E_ITR_TX_DEF I40E_ITR_4K
40#define I40E_ITR_DYNAMIC 0x8000 /* use top bit as a flag */
41#define I40E_MIN_INT_RATE 250 /* ~= 1000000 / (I40E_MAX_ITR * 2) */
42#define I40E_MAX_INT_RATE 500000 /* == 1000000 / (I40E_MIN_ITR * 2) */
43#define I40E_DEFAULT_IRQ_WORK 256
44#define ITR_TO_REG(setting) ((setting & ~I40E_ITR_DYNAMIC) >> 1)
45#define ITR_IS_DYNAMIC(setting) (!!(setting & I40E_ITR_DYNAMIC))
46#define ITR_REG_TO_USEC(itr_reg) (itr_reg << 1)
47
48#define I40E_QUEUE_END_OF_LIST 0x7FF
49
50/* this enum matches hardware bits and is meant to be used by DYN_CTLN
51 * registers and QINT registers or more generally anywhere in the manual
52 * mentioning ITR_INDX, ITR_NONE cannot be used as an index 'n' into any
53 * register but instead is a special value meaning "don't update" ITR0/1/2.
54 */
55enum i40e_dyn_idx_t {
56 I40E_IDX_ITR0 = 0,
57 I40E_IDX_ITR1 = 1,
58 I40E_IDX_ITR2 = 2,
59 I40E_ITR_NONE = 3 /* ITR_NONE must not be used as an index */
60};
61
62/* these are indexes into ITRN registers */
63#define I40E_RX_ITR I40E_IDX_ITR0
64#define I40E_TX_ITR I40E_IDX_ITR1
65#define I40E_PE_ITR I40E_IDX_ITR2
66
67/* Supported RSS offloads */
68#define I40E_DEFAULT_RSS_HENA ( \
69 ((u64)1 << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | \
70 ((u64)1 << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) | \
71 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \
72 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \
73 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN) | \
74 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \
75 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \
76 ((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV4) | \
77 ((u64)1 << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \
78 ((u64)1 << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP) | \
79 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \
80 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN) | \
81 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \
82 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \
83 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \
84 ((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV6) | \
85 ((u64)1 << I40E_FILTER_PCTYPE_L2_PAYLOAD))
86
87/* Supported Rx Buffer Sizes */
88#define I40E_RXBUFFER_512 512 /* Used for packet split */
89#define I40E_RXBUFFER_2048 2048
90#define I40E_RXBUFFER_3072 3072 /* For FCoE MTU of 2158 */
91#define I40E_RXBUFFER_4096 4096
92#define I40E_RXBUFFER_8192 8192
93#define I40E_MAX_RXBUFFER 9728 /* largest size for single descriptor */
94
95/* NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN means we
96 * reserve 2 more, and skb_shared_info adds an additional 384 bytes more,
97 * this adds up to 512 bytes of extra data meaning the smallest allocation
98 * we could have is 1K.
99 * i.e. RXBUFFER_512 --> size-1024 slab
100 */
101#define I40E_RX_HDR_SIZE I40E_RXBUFFER_512
102
103/* How many Rx Buffers do we bundle into one write to the hardware ? */
104#define I40E_RX_BUFFER_WRITE 16 /* Must be power of 2 */
105#define I40E_RX_NEXT_DESC(r, i, n) \
106 do { \
107 (i)++; \
108 if ((i) == (r)->count) \
109 i = 0; \
110 (n) = I40E_RX_DESC((r), (i)); \
111 } while (0)
112
113#define I40E_RX_NEXT_DESC_PREFETCH(r, i, n) \
114 do { \
115 I40E_RX_NEXT_DESC((r), (i), (n)); \
116 prefetch((n)); \
117 } while (0)
118
119#define i40e_rx_desc i40e_32byte_rx_desc
120
121#define I40E_MIN_TX_LEN 17
122#define I40E_MAX_DATA_PER_TXD 16383 /* aka 16kB - 1 */
123
124/* Tx Descriptors needed, worst case */
125#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), I40E_MAX_DATA_PER_TXD)
126#define DESC_NEEDED ((MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE)) + 4)
127
128#define I40E_TX_FLAGS_CSUM (u32)(1)
129#define I40E_TX_FLAGS_HW_VLAN (u32)(1 << 1)
130#define I40E_TX_FLAGS_SW_VLAN (u32)(1 << 2)
131#define I40E_TX_FLAGS_TSO (u32)(1 << 3)
132#define I40E_TX_FLAGS_IPV4 (u32)(1 << 4)
133#define I40E_TX_FLAGS_IPV6 (u32)(1 << 5)
134#define I40E_TX_FLAGS_FCCRC (u32)(1 << 6)
135#define I40E_TX_FLAGS_FSO (u32)(1 << 7)
136#define I40E_TX_FLAGS_VLAN_MASK 0xffff0000
137#define I40E_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000
138#define I40E_TX_FLAGS_VLAN_PRIO_SHIFT 29
139#define I40E_TX_FLAGS_VLAN_SHIFT 16
140
141struct i40e_tx_buffer {
142 struct i40e_tx_desc *next_to_watch;
143 unsigned long time_stamp;
144 struct sk_buff *skb;
145 unsigned int bytecount;
146 unsigned short gso_segs;
147 DEFINE_DMA_UNMAP_ADDR(dma);
148 DEFINE_DMA_UNMAP_LEN(len);
149 u32 tx_flags;
150};
151
152struct i40e_rx_buffer {
153 struct sk_buff *skb;
154 dma_addr_t dma;
155 struct page *page;
156 dma_addr_t page_dma;
157 unsigned int page_offset;
158};
159
160struct i40e_queue_stats {
161 u64 packets;
162 u64 bytes;
163};
164
165struct i40e_tx_queue_stats {
166 u64 restart_queue;
167 u64 tx_busy;
168 u64 tx_done_old;
169};
170
171struct i40e_rx_queue_stats {
172 u64 non_eop_descs;
173 u64 alloc_page_failed;
174 u64 alloc_buff_failed;
175};
176
177enum i40e_ring_state_t {
178 __I40E_TX_FDIR_INIT_DONE,
179 __I40E_TX_XPS_INIT_DONE,
180 __I40E_TX_DETECT_HANG,
181 __I40E_HANG_CHECK_ARMED,
182 __I40E_RX_PS_ENABLED,
183 __I40E_RX_LRO_ENABLED,
184 __I40E_RX_16BYTE_DESC_ENABLED,
185};
186
187#define ring_is_ps_enabled(ring) \
188 test_bit(__I40E_RX_PS_ENABLED, &(ring)->state)
189#define set_ring_ps_enabled(ring) \
190 set_bit(__I40E_RX_PS_ENABLED, &(ring)->state)
191#define clear_ring_ps_enabled(ring) \
192 clear_bit(__I40E_RX_PS_ENABLED, &(ring)->state)
193#define check_for_tx_hang(ring) \
194 test_bit(__I40E_TX_DETECT_HANG, &(ring)->state)
195#define set_check_for_tx_hang(ring) \
196 set_bit(__I40E_TX_DETECT_HANG, &(ring)->state)
197#define clear_check_for_tx_hang(ring) \
198 clear_bit(__I40E_TX_DETECT_HANG, &(ring)->state)
199#define ring_is_lro_enabled(ring) \
200 test_bit(__I40E_RX_LRO_ENABLED, &(ring)->state)
201#define set_ring_lro_enabled(ring) \
202 set_bit(__I40E_RX_LRO_ENABLED, &(ring)->state)
203#define clear_ring_lro_enabled(ring) \
204 clear_bit(__I40E_RX_LRO_ENABLED, &(ring)->state)
205#define ring_is_16byte_desc_enabled(ring) \
206 test_bit(__I40E_RX_16BYTE_DESC_ENABLED, &(ring)->state)
207#define set_ring_16byte_desc_enabled(ring) \
208 set_bit(__I40E_RX_16BYTE_DESC_ENABLED, &(ring)->state)
209#define clear_ring_16byte_desc_enabled(ring) \
210 clear_bit(__I40E_RX_16BYTE_DESC_ENABLED, &(ring)->state)
211
212/* struct that defines a descriptor ring, associated with a VSI */
213struct i40e_ring {
214 struct i40e_ring *next; /* pointer to next ring in q_vector */
215 void *desc; /* Descriptor ring memory */
216 struct device *dev; /* Used for DMA mapping */
217 struct net_device *netdev; /* netdev ring maps to */
218 union {
219 struct i40e_tx_buffer *tx_bi;
220 struct i40e_rx_buffer *rx_bi;
221 };
222 unsigned long state;
223 u16 queue_index; /* Queue number of ring */
224 u8 dcb_tc; /* Traffic class of ring */
225 u8 __iomem *tail;
226
227 u16 count; /* Number of descriptors */
228 u16 reg_idx; /* HW register index of the ring */
229 u16 rx_hdr_len;
230 u16 rx_buf_len;
231 u8 dtype;
232#define I40E_RX_DTYPE_NO_SPLIT 0
233#define I40E_RX_DTYPE_SPLIT_ALWAYS 1
234#define I40E_RX_DTYPE_HEADER_SPLIT 2
235 u8 hsplit;
236#define I40E_RX_SPLIT_L2 0x1
237#define I40E_RX_SPLIT_IP 0x2
238#define I40E_RX_SPLIT_TCP_UDP 0x4
239#define I40E_RX_SPLIT_SCTP 0x8
240
241 /* used in interrupt processing */
242 u16 next_to_use;
243 u16 next_to_clean;
244
245 u8 atr_sample_rate;
246 u8 atr_count;
247
248 bool ring_active; /* is ring online or not */
249
250 /* stats structs */
251 struct i40e_queue_stats stats;
252 struct u64_stats_sync syncp;
253 union {
254 struct i40e_tx_queue_stats tx_stats;
255 struct i40e_rx_queue_stats rx_stats;
256 };
257
258 unsigned int size; /* length of descriptor ring in bytes */
259 dma_addr_t dma; /* physical address of ring */
260
261 struct i40e_vsi *vsi; /* Backreference to associated VSI */
262 struct i40e_q_vector *q_vector; /* Backreference to associated vector */
263
264 struct rcu_head rcu; /* to avoid race on free */
265} ____cacheline_internodealigned_in_smp;
266
267enum i40e_latency_range {
268 I40E_LOWEST_LATENCY = 0,
269 I40E_LOW_LATENCY = 1,
270 I40E_BULK_LATENCY = 2,
271};
272
273struct i40e_ring_container {
274 /* array of pointers to rings */
275 struct i40e_ring *ring;
276 unsigned int total_bytes; /* total bytes processed this int */
277 unsigned int total_packets; /* total packets processed this int */
278 u16 count;
279 enum i40e_latency_range latency_range;
280 u16 itr;
281};
282
283/* iterator for handling rings in ring container */
284#define i40e_for_each_ring(pos, head) \
285 for (pos = (head).ring; pos != NULL; pos = pos->next)
286
287void i40evf_alloc_rx_buffers(struct i40e_ring *rxr, u16 cleaned_count);
288netdev_tx_t i40evf_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
289void i40evf_clean_tx_ring(struct i40e_ring *tx_ring);
290void i40evf_clean_rx_ring(struct i40e_ring *rx_ring);
291int i40evf_setup_tx_descriptors(struct i40e_ring *tx_ring);
292int i40evf_setup_rx_descriptors(struct i40e_ring *rx_ring);
293void i40evf_free_tx_resources(struct i40e_ring *tx_ring);
294void i40evf_free_rx_resources(struct i40e_ring *rx_ring);
295int i40evf_napi_poll(struct napi_struct *napi, int budget);
296#endif /* _I40E_TXRX_H_ */