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1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
4 * Copyright(c) 2013 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * The full GNU General Public License is included in this distribution in
16 * the file called "COPYING".
17 *
18 * Contact Information:
19 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
20 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
21 *
22 ******************************************************************************/
23
24#ifndef _I40E_ADMINQ_CMD_H_
25#define _I40E_ADMINQ_CMD_H_
26
27/* This header file defines the i40e Admin Queue commands and is shared between
28 * i40e Firmware and Software.
29 *
30 * This file needs to comply with the Linux Kernel coding style.
31 */
32
33#define I40E_FW_API_VERSION_MAJOR 0x0001
34#define I40E_FW_API_VERSION_MINOR 0x0001
35#define I40E_FW_API_VERSION_A0_MINOR 0x0000
36
37struct i40e_aq_desc {
38 __le16 flags;
39 __le16 opcode;
40 __le16 datalen;
41 __le16 retval;
42 __le32 cookie_high;
43 __le32 cookie_low;
44 union {
45 struct {
46 __le32 param0;
47 __le32 param1;
48 __le32 param2;
49 __le32 param3;
50 } internal;
51 struct {
52 __le32 param0;
53 __le32 param1;
54 __le32 addr_high;
55 __le32 addr_low;
56 } external;
57 u8 raw[16];
58 } params;
59};
60
61/* Flags sub-structure
62 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
63 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
64 */
65
66/* command flags and offsets*/
67#define I40E_AQ_FLAG_DD_SHIFT 0
68#define I40E_AQ_FLAG_CMP_SHIFT 1
69#define I40E_AQ_FLAG_ERR_SHIFT 2
70#define I40E_AQ_FLAG_VFE_SHIFT 3
71#define I40E_AQ_FLAG_LB_SHIFT 9
72#define I40E_AQ_FLAG_RD_SHIFT 10
73#define I40E_AQ_FLAG_VFC_SHIFT 11
74#define I40E_AQ_FLAG_BUF_SHIFT 12
75#define I40E_AQ_FLAG_SI_SHIFT 13
76#define I40E_AQ_FLAG_EI_SHIFT 14
77#define I40E_AQ_FLAG_FE_SHIFT 15
78
79#define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */
80#define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */
81#define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */
82#define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */
83#define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */
84#define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */
85#define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */
86#define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */
87#define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */
88#define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */
89#define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */
90
91/* error codes */
92enum i40e_admin_queue_err {
93 I40E_AQ_RC_OK = 0, /* success */
94 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */
95 I40E_AQ_RC_ENOENT = 2, /* No such element */
96 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */
97 I40E_AQ_RC_EINTR = 4, /* operation interrupted */
98 I40E_AQ_RC_EIO = 5, /* I/O error */
99 I40E_AQ_RC_ENXIO = 6, /* No such resource */
100 I40E_AQ_RC_E2BIG = 7, /* Arg too long */
101 I40E_AQ_RC_EAGAIN = 8, /* Try again */
102 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */
103 I40E_AQ_RC_EACCES = 10, /* Permission denied */
104 I40E_AQ_RC_EFAULT = 11, /* Bad address */
105 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */
106 I40E_AQ_RC_EEXIST = 13, /* object already exists */
107 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */
108 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */
109 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */
110 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */
111 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */
112 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed because of prev cmd error */
113 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */
114 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
115 I40E_AQ_RC_EFBIG = 22, /* File too large */
116};
117
118/* Admin Queue command opcodes */
119enum i40e_admin_queue_opc {
120 /* aq commands */
121 i40e_aqc_opc_get_version = 0x0001,
122 i40e_aqc_opc_driver_version = 0x0002,
123 i40e_aqc_opc_queue_shutdown = 0x0003,
124
125 /* resource ownership */
126 i40e_aqc_opc_request_resource = 0x0008,
127 i40e_aqc_opc_release_resource = 0x0009,
128
129 i40e_aqc_opc_list_func_capabilities = 0x000A,
130 i40e_aqc_opc_list_dev_capabilities = 0x000B,
131
132 i40e_aqc_opc_set_cppm_configuration = 0x0103,
133 i40e_aqc_opc_set_arp_proxy_entry = 0x0104,
134 i40e_aqc_opc_set_ns_proxy_entry = 0x0105,
135
136 /* LAA */
137 i40e_aqc_opc_mng_laa = 0x0106, /* AQ obsolete */
138 i40e_aqc_opc_mac_address_read = 0x0107,
139 i40e_aqc_opc_mac_address_write = 0x0108,
140
141 /* PXE */
142 i40e_aqc_opc_clear_pxe_mode = 0x0110,
143
144 /* internal switch commands */
145 i40e_aqc_opc_get_switch_config = 0x0200,
146 i40e_aqc_opc_add_statistics = 0x0201,
147 i40e_aqc_opc_remove_statistics = 0x0202,
148 i40e_aqc_opc_set_port_parameters = 0x0203,
149 i40e_aqc_opc_get_switch_resource_alloc = 0x0204,
150
151 i40e_aqc_opc_add_vsi = 0x0210,
152 i40e_aqc_opc_update_vsi_parameters = 0x0211,
153 i40e_aqc_opc_get_vsi_parameters = 0x0212,
154
155 i40e_aqc_opc_add_pv = 0x0220,
156 i40e_aqc_opc_update_pv_parameters = 0x0221,
157 i40e_aqc_opc_get_pv_parameters = 0x0222,
158
159 i40e_aqc_opc_add_veb = 0x0230,
160 i40e_aqc_opc_update_veb_parameters = 0x0231,
161 i40e_aqc_opc_get_veb_parameters = 0x0232,
162
163 i40e_aqc_opc_delete_element = 0x0243,
164
165 i40e_aqc_opc_add_macvlan = 0x0250,
166 i40e_aqc_opc_remove_macvlan = 0x0251,
167 i40e_aqc_opc_add_vlan = 0x0252,
168 i40e_aqc_opc_remove_vlan = 0x0253,
169 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254,
170 i40e_aqc_opc_add_tag = 0x0255,
171 i40e_aqc_opc_remove_tag = 0x0256,
172 i40e_aqc_opc_add_multicast_etag = 0x0257,
173 i40e_aqc_opc_remove_multicast_etag = 0x0258,
174 i40e_aqc_opc_update_tag = 0x0259,
175 i40e_aqc_opc_add_control_packet_filter = 0x025A,
176 i40e_aqc_opc_remove_control_packet_filter = 0x025B,
177 i40e_aqc_opc_add_cloud_filters = 0x025C,
178 i40e_aqc_opc_remove_cloud_filters = 0x025D,
179
180 i40e_aqc_opc_add_mirror_rule = 0x0260,
181 i40e_aqc_opc_delete_mirror_rule = 0x0261,
182
183 i40e_aqc_opc_set_storm_control_config = 0x0280,
184 i40e_aqc_opc_get_storm_control_config = 0x0281,
185
186 /* DCB commands */
187 i40e_aqc_opc_dcb_ignore_pfc = 0x0301,
188 i40e_aqc_opc_dcb_updated = 0x0302,
189
190 /* TX scheduler */
191 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400,
192 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406,
193 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407,
194 i40e_aqc_opc_query_vsi_bw_config = 0x0408,
195 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A,
196 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410,
197
198 i40e_aqc_opc_enable_switching_comp_ets = 0x0413,
199 i40e_aqc_opc_modify_switching_comp_ets = 0x0414,
200 i40e_aqc_opc_disable_switching_comp_ets = 0x0415,
201 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416,
202 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417,
203 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418,
204 i40e_aqc_opc_query_port_ets_config = 0x0419,
205 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A,
206 i40e_aqc_opc_suspend_port_tx = 0x041B,
207 i40e_aqc_opc_resume_port_tx = 0x041C,
208
209 /* hmc */
210 i40e_aqc_opc_query_hmc_resource_profile = 0x0500,
211 i40e_aqc_opc_set_hmc_resource_profile = 0x0501,
212
213 /* phy commands*/
214 i40e_aqc_opc_get_phy_abilities = 0x0600,
215 i40e_aqc_opc_set_phy_config = 0x0601,
216 i40e_aqc_opc_set_mac_config = 0x0603,
217 i40e_aqc_opc_set_link_restart_an = 0x0605,
218 i40e_aqc_opc_get_link_status = 0x0607,
219 i40e_aqc_opc_set_phy_int_mask = 0x0613,
220 i40e_aqc_opc_get_local_advt_reg = 0x0614,
221 i40e_aqc_opc_set_local_advt_reg = 0x0615,
222 i40e_aqc_opc_get_partner_advt = 0x0616,
223 i40e_aqc_opc_set_lb_modes = 0x0618,
224 i40e_aqc_opc_get_phy_wol_caps = 0x0621,
225 i40e_aqc_opc_set_phy_reset = 0x0622,
226 i40e_aqc_opc_upload_ext_phy_fm = 0x0625,
227
228 /* NVM commands */
229 i40e_aqc_opc_nvm_read = 0x0701,
230 i40e_aqc_opc_nvm_erase = 0x0702,
231 i40e_aqc_opc_nvm_update = 0x0703,
232
233 /* virtualization commands */
234 i40e_aqc_opc_send_msg_to_pf = 0x0801,
235 i40e_aqc_opc_send_msg_to_vf = 0x0802,
236 i40e_aqc_opc_send_msg_to_peer = 0x0803,
237
238 /* alternate structure */
239 i40e_aqc_opc_alternate_write = 0x0900,
240 i40e_aqc_opc_alternate_write_indirect = 0x0901,
241 i40e_aqc_opc_alternate_read = 0x0902,
242 i40e_aqc_opc_alternate_read_indirect = 0x0903,
243 i40e_aqc_opc_alternate_write_done = 0x0904,
244 i40e_aqc_opc_alternate_set_mode = 0x0905,
245 i40e_aqc_opc_alternate_clear_port = 0x0906,
246
247 /* LLDP commands */
248 i40e_aqc_opc_lldp_get_mib = 0x0A00,
249 i40e_aqc_opc_lldp_update_mib = 0x0A01,
250 i40e_aqc_opc_lldp_add_tlv = 0x0A02,
251 i40e_aqc_opc_lldp_update_tlv = 0x0A03,
252 i40e_aqc_opc_lldp_delete_tlv = 0x0A04,
253 i40e_aqc_opc_lldp_stop = 0x0A05,
254 i40e_aqc_opc_lldp_start = 0x0A06,
255
256 /* Tunnel commands */
257 i40e_aqc_opc_add_udp_tunnel = 0x0B00,
258 i40e_aqc_opc_del_udp_tunnel = 0x0B01,
259 i40e_aqc_opc_tunnel_key_structure = 0x0B10,
260
261 /* Async Events */
262 i40e_aqc_opc_event_lan_overflow = 0x1001,
263
264 /* OEM commands */
265 i40e_aqc_opc_oem_parameter_change = 0xFE00,
266 i40e_aqc_opc_oem_device_status_change = 0xFE01,
267
268 /* debug commands */
269 i40e_aqc_opc_debug_get_deviceid = 0xFF00,
270 i40e_aqc_opc_debug_set_mode = 0xFF01,
271 i40e_aqc_opc_debug_read_reg = 0xFF03,
272 i40e_aqc_opc_debug_write_reg = 0xFF04,
273 i40e_aqc_opc_debug_read_reg_sg = 0xFF05,
274 i40e_aqc_opc_debug_write_reg_sg = 0xFF06,
275 i40e_aqc_opc_debug_modify_reg = 0xFF07,
276 i40e_aqc_opc_debug_dump_internals = 0xFF08,
277 i40e_aqc_opc_debug_modify_internals = 0xFF09,
278};
279
280/* command structures and indirect data structures */
281
282/* Structure naming conventions:
283 * - no suffix for direct command descriptor structures
284 * - _data for indirect sent data
285 * - _resp for indirect return data (data which is both will use _data)
286 * - _completion for direct return data
287 * - _element_ for repeated elements (may also be _data or _resp)
288 *
289 * Command structures are expected to overlay the params.raw member of the basic
290 * descriptor, and as such cannot exceed 16 bytes in length.
291 */
292
293/* This macro is used to generate a compilation error if a structure
294 * is not exactly the correct length. It gives a divide by zero error if the
295 * structure is not of the correct size, otherwise it creates an enum that is
296 * never used.
297 */
298#define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \
299 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }
300
301/* This macro is used extensively to ensure that command structures are 16
302 * bytes in length as they have to map to the raw array of that size.
303 */
304#define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X)
305
306/* internal (0x00XX) commands */
307
308/* Get version (direct 0x0001) */
309struct i40e_aqc_get_version {
310 __le32 rom_ver;
311 __le32 fw_build;
312 __le16 fw_major;
313 __le16 fw_minor;
314 __le16 api_major;
315 __le16 api_minor;
316};
317
318I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version);
319
320/* Send driver version (indirect 0x0002) */
321struct i40e_aqc_driver_version {
322 u8 driver_major_ver;
323 u8 driver_minor_ver;
324 u8 driver_build_ver;
325 u8 driver_subbuild_ver;
326 u8 reserved[4];
327 __le32 address_high;
328 __le32 address_low;
329};
330
331I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version);
332
333/* Queue Shutdown (direct 0x0003) */
334struct i40e_aqc_queue_shutdown {
335 __le32 driver_unloading;
336#define I40E_AQ_DRIVER_UNLOADING 0x1
337 u8 reserved[12];
338};
339
340I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown);
341
342/* Request resource ownership (direct 0x0008)
343 * Release resource ownership (direct 0x0009)
344 */
345#define I40E_AQ_RESOURCE_NVM 1
346#define I40E_AQ_RESOURCE_SDP 2
347#define I40E_AQ_RESOURCE_ACCESS_READ 1
348#define I40E_AQ_RESOURCE_ACCESS_WRITE 2
349#define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000
350#define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000
351
352struct i40e_aqc_request_resource {
353 __le16 resource_id;
354 __le16 access_type;
355 __le32 timeout;
356 __le32 resource_number;
357 u8 reserved[4];
358};
359
360I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource);
361
362/* Get function capabilities (indirect 0x000A)
363 * Get device capabilities (indirect 0x000B)
364 */
365struct i40e_aqc_list_capabilites {
366 u8 command_flags;
367#define I40E_AQ_LIST_CAP_PF_INDEX_EN 1
368 u8 pf_index;
369 u8 reserved[2];
370 __le32 count;
371 __le32 addr_high;
372 __le32 addr_low;
373};
374
375I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites);
376
377struct i40e_aqc_list_capabilities_element_resp {
378 __le16 id;
379 u8 major_rev;
380 u8 minor_rev;
381 __le32 number;
382 __le32 logical_id;
383 __le32 phys_id;
384 u8 reserved[16];
385};
386
387/* list of caps */
388
389#define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001
390#define I40E_AQ_CAP_ID_MNG_MODE 0x0002
391#define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003
392#define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004
393#define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005
394#define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006
395#define I40E_AQ_CAP_ID_SRIOV 0x0012
396#define I40E_AQ_CAP_ID_VF 0x0013
397#define I40E_AQ_CAP_ID_VMDQ 0x0014
398#define I40E_AQ_CAP_ID_8021QBG 0x0015
399#define I40E_AQ_CAP_ID_8021QBR 0x0016
400#define I40E_AQ_CAP_ID_VSI 0x0017
401#define I40E_AQ_CAP_ID_DCB 0x0018
402#define I40E_AQ_CAP_ID_FCOE 0x0021
403#define I40E_AQ_CAP_ID_RSS 0x0040
404#define I40E_AQ_CAP_ID_RXQ 0x0041
405#define I40E_AQ_CAP_ID_TXQ 0x0042
406#define I40E_AQ_CAP_ID_MSIX 0x0043
407#define I40E_AQ_CAP_ID_VF_MSIX 0x0044
408#define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045
409#define I40E_AQ_CAP_ID_1588 0x0046
410#define I40E_AQ_CAP_ID_IWARP 0x0051
411#define I40E_AQ_CAP_ID_LED 0x0061
412#define I40E_AQ_CAP_ID_SDP 0x0062
413#define I40E_AQ_CAP_ID_MDIO 0x0063
414#define I40E_AQ_CAP_ID_FLEX10 0x00F1
415#define I40E_AQ_CAP_ID_CEM 0x00F2
416
417/* Set CPPM Configuration (direct 0x0103) */
418struct i40e_aqc_cppm_configuration {
419 __le16 command_flags;
420#define I40E_AQ_CPPM_EN_LTRC 0x0800
421#define I40E_AQ_CPPM_EN_DMCTH 0x1000
422#define I40E_AQ_CPPM_EN_DMCTLX 0x2000
423#define I40E_AQ_CPPM_EN_HPTC 0x4000
424#define I40E_AQ_CPPM_EN_DMARC 0x8000
425 __le16 ttlx;
426 __le32 dmacr;
427 __le16 dmcth;
428 u8 hptc;
429 u8 reserved;
430 __le32 pfltrc;
431};
432
433I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration);
434
435/* Set ARP Proxy command / response (indirect 0x0104) */
436struct i40e_aqc_arp_proxy_data {
437 __le16 command_flags;
438#define I40E_AQ_ARP_INIT_IPV4 0x0008
439#define I40E_AQ_ARP_UNSUP_CTL 0x0010
440#define I40E_AQ_ARP_ENA 0x0020
441#define I40E_AQ_ARP_ADD_IPV4 0x0040
442#define I40E_AQ_ARP_DEL_IPV4 0x0080
443 __le16 table_id;
444 __le32 pfpm_proxyfc;
445 __le32 ip_addr;
446 u8 mac_addr[6];
447};
448
449/* Set NS Proxy Table Entry Command (indirect 0x0105) */
450struct i40e_aqc_ns_proxy_data {
451 __le16 table_idx_mac_addr_0;
452 __le16 table_idx_mac_addr_1;
453 __le16 table_idx_ipv6_0;
454 __le16 table_idx_ipv6_1;
455 __le16 control;
456#define I40E_AQ_NS_PROXY_ADD_0 0x0100
457#define I40E_AQ_NS_PROXY_DEL_0 0x0200
458#define I40E_AQ_NS_PROXY_ADD_1 0x0400
459#define I40E_AQ_NS_PROXY_DEL_1 0x0800
460#define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x1000
461#define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x2000
462#define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x4000
463#define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x8000
464#define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0001
465#define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0002
466#define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0004
467 u8 mac_addr_0[6];
468 u8 mac_addr_1[6];
469 u8 local_mac_addr[6];
470 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */
471 u8 ipv6_addr_1[16];
472};
473
474/* Manage LAA Command (0x0106) - obsolete */
475struct i40e_aqc_mng_laa {
476 __le16 command_flags;
477#define I40E_AQ_LAA_FLAG_WR 0x8000
478 u8 reserved[2];
479 __le32 sal;
480 __le16 sah;
481 u8 reserved2[6];
482};
483
484/* Manage MAC Address Read Command (indirect 0x0107) */
485struct i40e_aqc_mac_address_read {
486 __le16 command_flags;
487#define I40E_AQC_LAN_ADDR_VALID 0x10
488#define I40E_AQC_SAN_ADDR_VALID 0x20
489#define I40E_AQC_PORT_ADDR_VALID 0x40
490#define I40E_AQC_WOL_ADDR_VALID 0x80
491#define I40E_AQC_ADDR_VALID_MASK 0xf0
492 u8 reserved[6];
493 __le32 addr_high;
494 __le32 addr_low;
495};
496
497I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read);
498
499struct i40e_aqc_mac_address_read_data {
500 u8 pf_lan_mac[6];
501 u8 pf_san_mac[6];
502 u8 port_mac[6];
503 u8 pf_wol_mac[6];
504};
505
506I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data);
507
508/* Manage MAC Address Write Command (0x0108) */
509struct i40e_aqc_mac_address_write {
510 __le16 command_flags;
511#define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000
512#define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000
513#define I40E_AQC_WRITE_TYPE_PORT 0x8000
514#define I40E_AQC_WRITE_TYPE_MASK 0xc000
515 __le16 mac_sah;
516 __le32 mac_sal;
517 u8 reserved[8];
518};
519
520I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write);
521
522/* PXE commands (0x011x) */
523
524/* Clear PXE Command and response (direct 0x0110) */
525struct i40e_aqc_clear_pxe {
526 u8 rx_cnt;
527 u8 reserved[15];
528};
529
530I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe);
531
532/* Switch configuration commands (0x02xx) */
533
534/* Used by many indirect commands that only pass an seid and a buffer in the
535 * command
536 */
537struct i40e_aqc_switch_seid {
538 __le16 seid;
539 u8 reserved[6];
540 __le32 addr_high;
541 __le32 addr_low;
542};
543
544I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid);
545
546/* Get Switch Configuration command (indirect 0x0200)
547 * uses i40e_aqc_switch_seid for the descriptor
548 */
549struct i40e_aqc_get_switch_config_header_resp {
550 __le16 num_reported;
551 __le16 num_total;
552 u8 reserved[12];
553};
554
555struct i40e_aqc_switch_config_element_resp {
556 u8 element_type;
557#define I40E_AQ_SW_ELEM_TYPE_MAC 1
558#define I40E_AQ_SW_ELEM_TYPE_PF 2
559#define I40E_AQ_SW_ELEM_TYPE_VF 3
560#define I40E_AQ_SW_ELEM_TYPE_EMP 4
561#define I40E_AQ_SW_ELEM_TYPE_BMC 5
562#define I40E_AQ_SW_ELEM_TYPE_PV 16
563#define I40E_AQ_SW_ELEM_TYPE_VEB 17
564#define I40E_AQ_SW_ELEM_TYPE_PA 18
565#define I40E_AQ_SW_ELEM_TYPE_VSI 19
566 u8 revision;
567#define I40E_AQ_SW_ELEM_REV_1 1
568 __le16 seid;
569 __le16 uplink_seid;
570 __le16 downlink_seid;
571 u8 reserved[3];
572 u8 connection_type;
573#define I40E_AQ_CONN_TYPE_REGULAR 0x1
574#define I40E_AQ_CONN_TYPE_DEFAULT 0x2
575#define I40E_AQ_CONN_TYPE_CASCADED 0x3
576 __le16 scheduler_id;
577 __le16 element_info;
578};
579
580/* Get Switch Configuration (indirect 0x0200)
581 * an array of elements are returned in the response buffer
582 * the first in the array is the header, remainder are elements
583 */
584struct i40e_aqc_get_switch_config_resp {
585 struct i40e_aqc_get_switch_config_header_resp header;
586 struct i40e_aqc_switch_config_element_resp element[1];
587};
588
589/* Add Statistics (direct 0x0201)
590 * Remove Statistics (direct 0x0202)
591 */
592struct i40e_aqc_add_remove_statistics {
593 __le16 seid;
594 __le16 vlan;
595 __le16 stat_index;
596 u8 reserved[10];
597};
598
599I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics);
600
601/* Set Port Parameters command (direct 0x0203) */
602struct i40e_aqc_set_port_parameters {
603 __le16 command_flags;
604#define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1
605#define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */
606#define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4
607 __le16 bad_frame_vsi;
608 __le16 default_seid; /* reserved for command */
609 u8 reserved[10];
610};
611
612I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters);
613
614/* Get Switch Resource Allocation (indirect 0x0204) */
615struct i40e_aqc_get_switch_resource_alloc {
616 u8 num_entries; /* reserved for command */
617 u8 reserved[7];
618 __le32 addr_high;
619 __le32 addr_low;
620};
621
622I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc);
623
624/* expect an array of these structs in the response buffer */
625struct i40e_aqc_switch_resource_alloc_element_resp {
626 u8 resource_type;
627#define I40E_AQ_RESOURCE_TYPE_VEB 0x0
628#define I40E_AQ_RESOURCE_TYPE_VSI 0x1
629#define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2
630#define I40E_AQ_RESOURCE_TYPE_STAG 0x3
631#define I40E_AQ_RESOURCE_TYPE_ETAG 0x4
632#define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5
633#define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6
634#define I40E_AQ_RESOURCE_TYPE_VLAN 0x7
635#define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8
636#define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9
637#define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA
638#define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB
639#define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC
640#define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD
641#define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF
642#define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10
643#define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11
644#define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12
645#define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13
646 u8 reserved1;
647 __le16 guaranteed;
648 __le16 total;
649 __le16 used;
650 __le16 total_unalloced;
651 u8 reserved2[6];
652};
653
654/* Add VSI (indirect 0x0210)
655 * this indirect command uses struct i40e_aqc_vsi_properties_data
656 * as the indirect buffer (128 bytes)
657 *
658 * Update VSI (indirect 0x211)
659 * uses the same data structure as Add VSI
660 *
661 * Get VSI (indirect 0x0212)
662 * uses the same completion and data structure as Add VSI
663 */
664struct i40e_aqc_add_get_update_vsi {
665 __le16 uplink_seid;
666 u8 connection_type;
667#define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1
668#define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2
669#define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3
670 u8 reserved1;
671 u8 vf_id;
672 u8 reserved2;
673 __le16 vsi_flags;
674#define I40E_AQ_VSI_TYPE_SHIFT 0x0
675#define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT)
676#define I40E_AQ_VSI_TYPE_VF 0x0
677#define I40E_AQ_VSI_TYPE_VMDQ2 0x1
678#define I40E_AQ_VSI_TYPE_PF 0x2
679#define I40E_AQ_VSI_TYPE_EMP_MNG 0x3
680#define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4
681#define I40E_AQ_VSI_FLAG_CLOUD_VSI 0x8
682 __le32 addr_high;
683 __le32 addr_low;
684};
685
686I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi);
687
688struct i40e_aqc_add_get_update_vsi_completion {
689 __le16 seid;
690 __le16 vsi_number;
691 __le16 vsi_used;
692 __le16 vsi_free;
693 __le32 addr_high;
694 __le32 addr_low;
695};
696
697I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion);
698
699struct i40e_aqc_vsi_properties_data {
700 /* first 96 byte are written by SW */
701 __le16 valid_sections;
702#define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001
703#define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002
704#define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004
705#define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008
706#define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010
707#define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020
708#define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040
709#define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080
710#define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100
711#define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200
712 /* switch section */
713 __le16 switch_id; /* 12bit id combined with flags below */
714#define I40E_AQ_VSI_SW_ID_SHIFT 0x0000
715#define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT)
716#define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000
717#define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000
718#define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000
719 u8 sw_reserved[2];
720 /* security section */
721 u8 sec_flags;
722#define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01
723#define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02
724#define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04
725 u8 sec_reserved;
726 /* VLAN section */
727 __le16 pvid; /* VLANS include priority bits */
728 __le16 fcoe_pvid;
729 u8 port_vlan_flags;
730#define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00
731#define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \
732 I40E_AQ_VSI_PVLAN_MODE_SHIFT)
733#define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01
734#define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02
735#define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03
736#define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04
737#define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03
738#define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \
739 I40E_AQ_VSI_PVLAN_EMOD_SHIFT)
740#define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0
741#define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08
742#define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10
743#define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18
744 u8 pvlan_reserved[3];
745 /* ingress egress up sections */
746 __le32 ingress_table; /* bitmap, 3 bits per up */
747#define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0
748#define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \
749 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT)
750#define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3
751#define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \
752 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT)
753#define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6
754#define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \
755 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT)
756#define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9
757#define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \
758 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT)
759#define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12
760#define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \
761 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT)
762#define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15
763#define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \
764 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT)
765#define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18
766#define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \
767 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT)
768#define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21
769#define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \
770 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT)
771 __le32 egress_table; /* same defines as for ingress table */
772 /* cascaded PV section */
773 __le16 cas_pv_tag;
774 u8 cas_pv_flags;
775#define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00
776#define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \
777 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT)
778#define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00
779#define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01
780#define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02
781#define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10
782#define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20
783#define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40
784 u8 cas_pv_reserved;
785 /* queue mapping section */
786 __le16 mapping_flags;
787#define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0
788#define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1
789 __le16 queue_mapping[16];
790#define I40E_AQ_VSI_QUEUE_SHIFT 0x0
791#define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT)
792 __le16 tc_mapping[8];
793#define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0
794#define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \
795 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT)
796#define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9
797#define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \
798 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)
799 /* queueing option section */
800 u8 queueing_opt_flags;
801#define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10
802#define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20
803 u8 queueing_opt_reserved[3];
804 /* scheduler section */
805 u8 up_enable_bits;
806 u8 sched_reserved;
807 /* outer up section */
808 __le32 outer_up_table; /* same structure and defines as ingress table */
809 u8 cmd_reserved[8];
810 /* last 32 bytes are written by FW */
811 __le16 qs_handle[8];
812#define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF
813 __le16 stat_counter_idx;
814 __le16 sched_id;
815 u8 resp_reserved[12];
816};
817
818I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data);
819
820/* Add Port Virtualizer (direct 0x0220)
821 * also used for update PV (direct 0x0221) but only flags are used
822 * (IS_CTRL_PORT only works on add PV)
823 */
824struct i40e_aqc_add_update_pv {
825 __le16 command_flags;
826#define I40E_AQC_PV_FLAG_PV_TYPE 0x1
827#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2
828#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4
829#define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8
830 __le16 uplink_seid;
831 __le16 connected_seid;
832 u8 reserved[10];
833};
834
835I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv);
836
837struct i40e_aqc_add_update_pv_completion {
838 /* reserved for update; for add also encodes error if rc == ENOSPC */
839 __le16 pv_seid;
840#define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1
841#define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2
842#define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4
843#define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8
844 u8 reserved[14];
845};
846
847I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion);
848
849/* Get PV Params (direct 0x0222)
850 * uses i40e_aqc_switch_seid for the descriptor
851 */
852
853struct i40e_aqc_get_pv_params_completion {
854 __le16 seid;
855 __le16 default_stag;
856 __le16 pv_flags; /* same flags as add_pv */
857#define I40E_AQC_GET_PV_PV_TYPE 0x1
858#define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2
859#define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4
860 u8 reserved[8];
861 __le16 default_port_seid;
862};
863
864I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion);
865
866/* Add VEB (direct 0x0230) */
867struct i40e_aqc_add_veb {
868 __le16 uplink_seid;
869 __le16 downlink_seid;
870 __le16 veb_flags;
871#define I40E_AQC_ADD_VEB_FLOATING 0x1
872#define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1
873#define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \
874 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT)
875#define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2
876#define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4
877#define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8
878 u8 enable_tcs;
879 u8 reserved[9];
880};
881
882I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb);
883
884struct i40e_aqc_add_veb_completion {
885 u8 reserved[6];
886 __le16 switch_seid;
887 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */
888 __le16 veb_seid;
889#define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1
890#define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2
891#define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4
892#define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8
893 __le16 statistic_index;
894 __le16 vebs_used;
895 __le16 vebs_free;
896};
897
898I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion);
899
900/* Get VEB Parameters (direct 0x0232)
901 * uses i40e_aqc_switch_seid for the descriptor
902 */
903struct i40e_aqc_get_veb_parameters_completion {
904 __le16 seid;
905 __le16 switch_id;
906 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */
907 __le16 statistic_index;
908 __le16 vebs_used;
909 __le16 vebs_free;
910 u8 reserved[4];
911};
912
913I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion);
914
915/* Delete Element (direct 0x0243)
916 * uses the generic i40e_aqc_switch_seid
917 */
918
919/* Add MAC-VLAN (indirect 0x0250) */
920
921/* used for the command for most vlan commands */
922struct i40e_aqc_macvlan {
923 __le16 num_addresses;
924 __le16 seid[3];
925#define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0
926#define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \
927 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
928#define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000
929 __le32 addr_high;
930 __le32 addr_low;
931};
932
933I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan);
934
935/* indirect data for command and response */
936struct i40e_aqc_add_macvlan_element_data {
937 u8 mac_addr[6];
938 __le16 vlan_tag;
939 __le16 flags;
940#define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001
941#define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002
942#define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004
943#define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008
944 __le16 queue_number;
945#define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0
946#define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \
947 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
948 /* response section */
949 u8 match_method;
950#define I40E_AQC_MM_PERFECT_MATCH 0x01
951#define I40E_AQC_MM_HASH_MATCH 0x02
952#define I40E_AQC_MM_ERR_NO_RES 0xFF
953 u8 reserved1[3];
954};
955
956struct i40e_aqc_add_remove_macvlan_completion {
957 __le16 perfect_mac_used;
958 __le16 perfect_mac_free;
959 __le16 unicast_hash_free;
960 __le16 multicast_hash_free;
961 __le32 addr_high;
962 __le32 addr_low;
963};
964
965I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion);
966
967/* Remove MAC-VLAN (indirect 0x0251)
968 * uses i40e_aqc_macvlan for the descriptor
969 * data points to an array of num_addresses of elements
970 */
971
972struct i40e_aqc_remove_macvlan_element_data {
973 u8 mac_addr[6];
974 __le16 vlan_tag;
975 u8 flags;
976#define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01
977#define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02
978#define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08
979#define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10
980 u8 reserved[3];
981 /* reply section */
982 u8 error_code;
983#define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0
984#define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF
985 u8 reply_reserved[3];
986};
987
988/* Add VLAN (indirect 0x0252)
989 * Remove VLAN (indirect 0x0253)
990 * use the generic i40e_aqc_macvlan for the command
991 */
992struct i40e_aqc_add_remove_vlan_element_data {
993 __le16 vlan_tag;
994 u8 vlan_flags;
995/* flags for add VLAN */
996#define I40E_AQC_ADD_VLAN_LOCAL 0x1
997#define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1
998#define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << \
999 I40E_AQC_ADD_PVLAN_TYPE_SHIFT)
1000#define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0
1001#define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2
1002#define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4
1003#define I40E_AQC_VLAN_PTYPE_SHIFT 3
1004#define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT)
1005#define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0
1006#define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8
1007#define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10
1008#define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18
1009/* flags for remove VLAN */
1010#define I40E_AQC_REMOVE_VLAN_ALL 0x1
1011 u8 reserved;
1012 u8 result;
1013/* flags for add VLAN */
1014#define I40E_AQC_ADD_VLAN_SUCCESS 0x0
1015#define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE
1016#define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF
1017/* flags for remove VLAN */
1018#define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0
1019#define I40E_AQC_REMOVE_VLAN_FAIL 0xFF
1020 u8 reserved1[3];
1021};
1022
1023struct i40e_aqc_add_remove_vlan_completion {
1024 u8 reserved[4];
1025 __le16 vlans_used;
1026 __le16 vlans_free;
1027 __le32 addr_high;
1028 __le32 addr_low;
1029};
1030
1031/* Set VSI Promiscuous Modes (direct 0x0254) */
1032struct i40e_aqc_set_vsi_promiscuous_modes {
1033 __le16 promiscuous_flags;
1034 __le16 valid_flags;
1035/* flags used for both fields above */
1036#define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01
1037#define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02
1038#define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04
1039#define I40E_AQC_SET_VSI_DEFAULT 0x08
1040#define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10
1041 __le16 seid;
1042#define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF
1043 u8 reserved[10];
1044};
1045
1046I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes);
1047
1048/* Add S/E-tag command (direct 0x0255)
1049 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1050 */
1051struct i40e_aqc_add_tag {
1052 __le16 flags;
1053#define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001
1054 __le16 seid;
1055#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0
1056#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1057 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT)
1058 __le16 tag;
1059 __le16 queue_number;
1060 u8 reserved[8];
1061};
1062
1063I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag);
1064
1065struct i40e_aqc_add_remove_tag_completion {
1066 u8 reserved[12];
1067 __le16 tags_used;
1068 __le16 tags_free;
1069};
1070
1071I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion);
1072
1073/* Remove S/E-tag command (direct 0x0256)
1074 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1075 */
1076struct i40e_aqc_remove_tag {
1077 __le16 seid;
1078#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0
1079#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1080 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT)
1081 __le16 tag;
1082 u8 reserved[12];
1083};
1084
1085/* Add multicast E-Tag (direct 0x0257)
1086 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields
1087 * and no external data
1088 */
1089struct i40e_aqc_add_remove_mcast_etag {
1090 __le16 pv_seid;
1091 __le16 etag;
1092 u8 num_unicast_etags;
1093 u8 reserved[3];
1094 __le32 addr_high; /* address of array of 2-byte s-tags */
1095 __le32 addr_low;
1096};
1097
1098I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag);
1099
1100struct i40e_aqc_add_remove_mcast_etag_completion {
1101 u8 reserved[4];
1102 __le16 mcast_etags_used;
1103 __le16 mcast_etags_free;
1104 __le32 addr_high;
1105 __le32 addr_low;
1106
1107};
1108
1109I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion);
1110
1111/* Update S/E-Tag (direct 0x0259) */
1112struct i40e_aqc_update_tag {
1113 __le16 seid;
1114#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0
1115#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1116 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT)
1117 __le16 old_tag;
1118 __le16 new_tag;
1119 u8 reserved[10];
1120};
1121
1122I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag);
1123
1124struct i40e_aqc_update_tag_completion {
1125 u8 reserved[12];
1126 __le16 tags_used;
1127 __le16 tags_free;
1128};
1129
1130I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion);
1131
1132/* Add Control Packet filter (direct 0x025A)
1133 * Remove Control Packet filter (direct 0x025B)
1134 * uses the i40e_aqc_add_oveb_cloud,
1135 * and the generic direct completion structure
1136 */
1137struct i40e_aqc_add_remove_control_packet_filter {
1138 u8 mac[6];
1139 __le16 etype;
1140 __le16 flags;
1141#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001
1142#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002
1143#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004
1144#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008
1145#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000
1146 __le16 seid;
1147#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0
1148#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \
1149 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT)
1150 __le16 queue;
1151 u8 reserved[2];
1152};
1153
1154I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter);
1155
1156struct i40e_aqc_add_remove_control_packet_filter_completion {
1157 __le16 mac_etype_used;
1158 __le16 etype_used;
1159 __le16 mac_etype_free;
1160 __le16 etype_free;
1161 u8 reserved[8];
1162};
1163
1164I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion);
1165
1166/* Add Cloud filters (indirect 0x025C)
1167 * Remove Cloud filters (indirect 0x025D)
1168 * uses the i40e_aqc_add_remove_cloud_filters,
1169 * and the generic indirect completion structure
1170 */
1171struct i40e_aqc_add_remove_cloud_filters {
1172 u8 num_filters;
1173 u8 reserved;
1174 __le16 seid;
1175#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0
1176#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \
1177 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT)
1178 u8 reserved2[4];
1179 __le32 addr_high;
1180 __le32 addr_low;
1181};
1182
1183I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters);
1184
1185struct i40e_aqc_add_remove_cloud_filters_element_data {
1186 u8 outer_mac[6];
1187 u8 inner_mac[6];
1188 __le16 inner_vlan;
1189 union {
1190 struct {
1191 u8 reserved[12];
1192 u8 data[4];
1193 } v4;
1194 struct {
1195 u8 data[16];
1196 } v6;
1197 } ipaddr;
1198 __le16 flags;
1199#define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0
1200#define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \
1201 I40E_AQC_ADD_CLOUD_FILTER_SHIFT)
1202#define I40E_AQC_ADD_CLOUD_FILTER_OIP_GRE 0x0002
1203#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_GRE 0x0004
1204#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_VNL 0x0007
1205/* 0x0000 reserved */
1206#define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001
1207/* 0x0002 reserved */
1208#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003
1209#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004
1210/* 0x0005 reserved */
1211#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006
1212/* 0x0007 reserved */
1213/* 0x0008 reserved */
1214#define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009
1215#define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A
1216#define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B
1217#define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C
1218
1219#define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080
1220#define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6
1221#define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0
1222#define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0
1223#define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100
1224
1225#define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9
1226#define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00
1227#define I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN 0
1228#define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1
1229#define I40E_AQC_ADD_CLOUD_TNL_TYPE_NGE 2
1230#define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3
1231
1232 __le32 tenant_id;
1233 u8 reserved[4];
1234 __le16 queue_number;
1235#define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0
1236#define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x3F << \
1237 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT)
1238 u8 reserved2[14];
1239 /* response section */
1240 u8 allocation_result;
1241#define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0
1242#define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF
1243 u8 response_reserved[7];
1244};
1245
1246struct i40e_aqc_remove_cloud_filters_completion {
1247 __le16 perfect_ovlan_used;
1248 __le16 perfect_ovlan_free;
1249 __le16 vlan_used;
1250 __le16 vlan_free;
1251 __le32 addr_high;
1252 __le32 addr_low;
1253};
1254
1255I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion);
1256
1257/* Add Mirror Rule (indirect or direct 0x0260)
1258 * Delete Mirror Rule (indirect or direct 0x0261)
1259 * note: some rule types (4,5) do not use an external buffer.
1260 * take care to set the flags correctly.
1261 */
1262struct i40e_aqc_add_delete_mirror_rule {
1263 __le16 seid;
1264 __le16 rule_type;
1265#define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0
1266#define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \
1267 I40E_AQC_MIRROR_RULE_TYPE_SHIFT)
1268#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1
1269#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2
1270#define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3
1271#define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4
1272#define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5
1273 __le16 num_entries;
1274 __le16 destination; /* VSI for add, rule id for delete */
1275 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */
1276 __le32 addr_low;
1277};
1278
1279I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule);
1280
1281struct i40e_aqc_add_delete_mirror_rule_completion {
1282 u8 reserved[2];
1283 __le16 rule_id; /* only used on add */
1284 __le16 mirror_rules_used;
1285 __le16 mirror_rules_free;
1286 __le32 addr_high;
1287 __le32 addr_low;
1288};
1289
1290I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion);
1291
1292/* Set Storm Control Configuration (direct 0x0280)
1293 * Get Storm Control Configuration (direct 0x0281)
1294 * the command and response use the same descriptor structure
1295 */
1296struct i40e_aqc_set_get_storm_control_config {
1297 __le32 broadcast_threshold;
1298 __le32 multicast_threshold;
1299 __le32 control_flags;
1300#define I40E_AQC_STORM_CONTROL_MDIPW 0x01
1301#define I40E_AQC_STORM_CONTROL_MDICW 0x02
1302#define I40E_AQC_STORM_CONTROL_BDIPW 0x04
1303#define I40E_AQC_STORM_CONTROL_BDICW 0x08
1304#define I40E_AQC_STORM_CONTROL_BIDU 0x10
1305#define I40E_AQC_STORM_CONTROL_INTERVAL_SHIFT 8
1306#define I40E_AQC_STORM_CONTROL_INTERVAL_MASK (0x3FF << \
1307 I40E_AQC_STORM_CONTROL_INTERVAL_SHIFT)
1308 u8 reserved[4];
1309};
1310
1311I40E_CHECK_CMD_LENGTH(i40e_aqc_set_get_storm_control_config);
1312
1313/* DCB 0x03xx*/
1314
1315/* PFC Ignore (direct 0x0301)
1316 * the command and response use the same descriptor structure
1317 */
1318struct i40e_aqc_pfc_ignore {
1319 u8 tc_bitmap;
1320 u8 command_flags; /* unused on response */
1321#define I40E_AQC_PFC_IGNORE_SET 0x80
1322#define I40E_AQC_PFC_IGNORE_CLEAR 0x0
1323 u8 reserved[14];
1324};
1325
1326I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore);
1327
1328/* DCB Update (direct 0x0302) uses the i40e_aq_desc structure
1329 * with no parameters
1330 */
1331
1332/* TX scheduler 0x04xx */
1333
1334/* Almost all the indirect commands use
1335 * this generic struct to pass the SEID in param0
1336 */
1337struct i40e_aqc_tx_sched_ind {
1338 __le16 vsi_seid;
1339 u8 reserved[6];
1340 __le32 addr_high;
1341 __le32 addr_low;
1342};
1343
1344I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind);
1345
1346/* Several commands respond with a set of queue set handles */
1347struct i40e_aqc_qs_handles_resp {
1348 __le16 qs_handles[8];
1349};
1350
1351/* Configure VSI BW limits (direct 0x0400) */
1352struct i40e_aqc_configure_vsi_bw_limit {
1353 __le16 vsi_seid;
1354 u8 reserved[2];
1355 __le16 credit;
1356 u8 reserved1[2];
1357 u8 max_credit; /* 0-3, limit = 2^max */
1358 u8 reserved2[7];
1359};
1360
1361I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit);
1362
1363/* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406)
1364 * responds with i40e_aqc_qs_handles_resp
1365 */
1366struct i40e_aqc_configure_vsi_ets_sla_bw_data {
1367 u8 tc_valid_bits;
1368 u8 reserved[15];
1369 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */
1370
1371 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1372 __le16 tc_bw_max[2];
1373 u8 reserved1[28];
1374};
1375
1376/* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)
1377 * responds with i40e_aqc_qs_handles_resp
1378 */
1379struct i40e_aqc_configure_vsi_tc_bw_data {
1380 u8 tc_valid_bits;
1381 u8 reserved[3];
1382 u8 tc_bw_credits[8];
1383 u8 reserved1[4];
1384 __le16 qs_handles[8];
1385};
1386
1387/* Query vsi bw configuration (indirect 0x0408) */
1388struct i40e_aqc_query_vsi_bw_config_resp {
1389 u8 tc_valid_bits;
1390 u8 tc_suspended_bits;
1391 u8 reserved[14];
1392 __le16 qs_handles[8];
1393 u8 reserved1[4];
1394 __le16 port_bw_limit;
1395 u8 reserved2[2];
1396 u8 max_bw; /* 0-3, limit = 2^max */
1397 u8 reserved3[23];
1398};
1399
1400/* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */
1401struct i40e_aqc_query_vsi_ets_sla_config_resp {
1402 u8 tc_valid_bits;
1403 u8 reserved[3];
1404 u8 share_credits[8];
1405 __le16 credits[8];
1406
1407 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1408 __le16 tc_bw_max[2];
1409};
1410
1411/* Configure Switching Component Bandwidth Limit (direct 0x0410) */
1412struct i40e_aqc_configure_switching_comp_bw_limit {
1413 __le16 seid;
1414 u8 reserved[2];
1415 __le16 credit;
1416 u8 reserved1[2];
1417 u8 max_bw; /* 0-3, limit = 2^max */
1418 u8 reserved2[7];
1419};
1420
1421I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit);
1422
1423/* Enable Physical Port ETS (indirect 0x0413)
1424 * Modify Physical Port ETS (indirect 0x0414)
1425 * Disable Physical Port ETS (indirect 0x0415)
1426 */
1427struct i40e_aqc_configure_switching_comp_ets_data {
1428 u8 reserved[4];
1429 u8 tc_valid_bits;
1430 u8 reserved1;
1431 u8 tc_strict_priority_flags;
1432 u8 reserved2[17];
1433 u8 tc_bw_share_credits[8];
1434 u8 reserved3[96];
1435};
1436
1437/* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
1438struct i40e_aqc_configure_switching_comp_ets_bw_limit_data {
1439 u8 tc_valid_bits;
1440 u8 reserved[15];
1441 __le16 tc_bw_credit[8];
1442
1443 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1444 __le16 tc_bw_max[2];
1445 u8 reserved1[28];
1446};
1447
1448/* Configure Switching Component Bandwidth Allocation per Tc
1449 * (indirect 0x0417)
1450 */
1451struct i40e_aqc_configure_switching_comp_bw_config_data {
1452 u8 tc_valid_bits;
1453 u8 reserved[2];
1454 u8 absolute_credits; /* bool */
1455 u8 tc_bw_share_credits[8];
1456 u8 reserved1[20];
1457};
1458
1459/* Query Switching Component Configuration (indirect 0x0418) */
1460struct i40e_aqc_query_switching_comp_ets_config_resp {
1461 u8 tc_valid_bits;
1462 u8 reserved[35];
1463 __le16 port_bw_limit;
1464 u8 reserved1[2];
1465 u8 tc_bw_max; /* 0-3, limit = 2^max */
1466 u8 reserved2[23];
1467};
1468
1469/* Query PhysicalPort ETS Configuration (indirect 0x0419) */
1470struct i40e_aqc_query_port_ets_config_resp {
1471 u8 reserved[4];
1472 u8 tc_valid_bits;
1473 u8 reserved1;
1474 u8 tc_strict_priority_bits;
1475 u8 reserved2;
1476 u8 tc_bw_share_credits[8];
1477 __le16 tc_bw_limits[8];
1478
1479 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */
1480 __le16 tc_bw_max[2];
1481 u8 reserved3[32];
1482};
1483
1484/* Query Switching Component Bandwidth Allocation per Traffic Type
1485 * (indirect 0x041A)
1486 */
1487struct i40e_aqc_query_switching_comp_bw_config_resp {
1488 u8 tc_valid_bits;
1489 u8 reserved[2];
1490 u8 absolute_credits_enable; /* bool */
1491 u8 tc_bw_share_credits[8];
1492 __le16 tc_bw_limits[8];
1493
1494 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1495 __le16 tc_bw_max[2];
1496};
1497
1498/* Suspend/resume port TX traffic
1499 * (direct 0x041B and 0x041C) uses the generic SEID struct
1500 */
1501
1502/* Get and set the active HMC resource profile and status.
1503 * (direct 0x0500) and (direct 0x0501)
1504 */
1505struct i40e_aq_get_set_hmc_resource_profile {
1506 u8 pm_profile;
1507 u8 pe_vf_enabled;
1508 u8 reserved[14];
1509};
1510
1511I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile);
1512
1513enum i40e_aq_hmc_profile {
1514 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */
1515 I40E_HMC_PROFILE_DEFAULT = 1,
1516 I40E_HMC_PROFILE_FAVOR_VF = 2,
1517 I40E_HMC_PROFILE_EQUAL = 3,
1518};
1519
1520#define I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK 0xF
1521#define I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK 0x3F
1522
1523/* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */
1524
1525/* set in param0 for get phy abilities to report qualified modules */
1526#define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001
1527#define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002
1528
1529enum i40e_aq_phy_type {
1530 I40E_PHY_TYPE_SGMII = 0x0,
1531 I40E_PHY_TYPE_1000BASE_KX = 0x1,
1532 I40E_PHY_TYPE_10GBASE_KX4 = 0x2,
1533 I40E_PHY_TYPE_10GBASE_KR = 0x3,
1534 I40E_PHY_TYPE_40GBASE_KR4 = 0x4,
1535 I40E_PHY_TYPE_XAUI = 0x5,
1536 I40E_PHY_TYPE_XFI = 0x6,
1537 I40E_PHY_TYPE_SFI = 0x7,
1538 I40E_PHY_TYPE_XLAUI = 0x8,
1539 I40E_PHY_TYPE_XLPPI = 0x9,
1540 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA,
1541 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB,
1542 I40E_PHY_TYPE_100BASE_TX = 0x11,
1543 I40E_PHY_TYPE_1000BASE_T = 0x12,
1544 I40E_PHY_TYPE_10GBASE_T = 0x13,
1545 I40E_PHY_TYPE_10GBASE_SR = 0x14,
1546 I40E_PHY_TYPE_10GBASE_LR = 0x15,
1547 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16,
1548 I40E_PHY_TYPE_10GBASE_CR1 = 0x17,
1549 I40E_PHY_TYPE_40GBASE_CR4 = 0x18,
1550 I40E_PHY_TYPE_40GBASE_SR4 = 0x19,
1551 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A,
1552 I40E_PHY_TYPE_20GBASE_KR2 = 0x1B,
1553 I40E_PHY_TYPE_MAX
1554};
1555
1556#define I40E_LINK_SPEED_100MB_SHIFT 0x1
1557#define I40E_LINK_SPEED_1000MB_SHIFT 0x2
1558#define I40E_LINK_SPEED_10GB_SHIFT 0x3
1559#define I40E_LINK_SPEED_40GB_SHIFT 0x4
1560#define I40E_LINK_SPEED_20GB_SHIFT 0x5
1561
1562enum i40e_aq_link_speed {
1563 I40E_LINK_SPEED_UNKNOWN = 0,
1564 I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT),
1565 I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT),
1566 I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT),
1567 I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT),
1568 I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT)
1569};
1570
1571struct i40e_aqc_module_desc {
1572 u8 oui[3];
1573 u8 reserved1;
1574 u8 part_number[16];
1575 u8 revision[4];
1576 u8 reserved2[8];
1577};
1578
1579struct i40e_aq_get_phy_abilities_resp {
1580 __le32 phy_type; /* bitmap using the above enum for offsets */
1581 u8 link_speed; /* bitmap using the above enum bit patterns */
1582 u8 abilities;
1583#define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01
1584#define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02
1585#define I40E_AQ_PHY_FLAG_LOW_POWER 0x04
1586#define I40E_AQ_PHY_FLAG_AN_SHIFT 3
1587#define I40E_AQ_PHY_FLAG_AN_MASK (0x3 << I40E_AQ_PHY_FLAG_AN_SHIFT)
1588#define I40E_AQ_PHY_FLAG_AN_OFF 0x00 /* link forced on */
1589#define I40E_AQ_PHY_FLAG_AN_OFF_LINK_DOWN 0x01
1590#define I40E_AQ_PHY_FLAG_AN_ON 0x02
1591#define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20
1592 __le16 eee_capability;
1593#define I40E_AQ_EEE_100BASE_TX 0x0002
1594#define I40E_AQ_EEE_1000BASE_T 0x0004
1595#define I40E_AQ_EEE_10GBASE_T 0x0008
1596#define I40E_AQ_EEE_1000BASE_KX 0x0010
1597#define I40E_AQ_EEE_10GBASE_KX4 0x0020
1598#define I40E_AQ_EEE_10GBASE_KR 0x0040
1599 __le32 eeer_val;
1600 u8 d3_lpan;
1601#define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01
1602 u8 reserved[3];
1603 u8 phy_id[4];
1604 u8 module_type[3];
1605 u8 qualified_module_count;
1606#define I40E_AQ_PHY_MAX_QMS 16
1607 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS];
1608};
1609
1610/* Set PHY Config (direct 0x0601) */
1611struct i40e_aq_set_phy_config { /* same bits as above in all */
1612 __le32 phy_type;
1613 u8 link_speed;
1614 u8 abilities;
1615/* bits 0-2 use the values from get_phy_abilities_resp */
1616#define I40E_AQ_PHY_ENABLE_LINK 0x08
1617#define I40E_AQ_PHY_ENABLE_AN 0x10
1618#define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20
1619 __le16 eee_capability;
1620 __le32 eeer;
1621 u8 low_power_ctrl;
1622 u8 reserved[3];
1623};
1624
1625I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);
1626
1627/* Set MAC Config command data structure (direct 0x0603) */
1628struct i40e_aq_set_mac_config {
1629 __le16 max_frame_size;
1630 u8 params;
1631#define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04
1632#define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78
1633#define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3
1634#define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0
1635#define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF
1636#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9
1637#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8
1638#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7
1639#define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6
1640#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5
1641#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4
1642#define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3
1643#define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2
1644#define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1
1645 u8 tx_timer_priority; /* bitmap */
1646 __le16 tx_timer_value;
1647 __le16 fc_refresh_threshold;
1648 u8 reserved[8];
1649};
1650
1651I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config);
1652
1653/* Restart Auto-Negotiation (direct 0x605) */
1654struct i40e_aqc_set_link_restart_an {
1655 u8 command;
1656#define I40E_AQ_PHY_RESTART_AN 0x02
1657#define I40E_AQ_PHY_LINK_ENABLE 0x04
1658 u8 reserved[15];
1659};
1660
1661I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an);
1662
1663/* Get Link Status cmd & response data structure (direct 0x0607) */
1664struct i40e_aqc_get_link_status {
1665 __le16 command_flags; /* only field set on command */
1666#define I40E_AQ_LSE_MASK 0x3
1667#define I40E_AQ_LSE_NOP 0x0
1668#define I40E_AQ_LSE_DISABLE 0x2
1669#define I40E_AQ_LSE_ENABLE 0x3
1670/* only response uses this flag */
1671#define I40E_AQ_LSE_IS_ENABLED 0x1
1672 u8 phy_type; /* i40e_aq_phy_type */
1673 u8 link_speed; /* i40e_aq_link_speed */
1674 u8 link_info;
1675#define I40E_AQ_LINK_UP 0x01
1676#define I40E_AQ_LINK_FAULT 0x02
1677#define I40E_AQ_LINK_FAULT_TX 0x04
1678#define I40E_AQ_LINK_FAULT_RX 0x08
1679#define I40E_AQ_LINK_FAULT_REMOTE 0x10
1680#define I40E_AQ_MEDIA_AVAILABLE 0x40
1681#define I40E_AQ_SIGNAL_DETECT 0x80
1682 u8 an_info;
1683#define I40E_AQ_AN_COMPLETED 0x01
1684#define I40E_AQ_LP_AN_ABILITY 0x02
1685#define I40E_AQ_PD_FAULT 0x04
1686#define I40E_AQ_FEC_EN 0x08
1687#define I40E_AQ_PHY_LOW_POWER 0x10
1688#define I40E_AQ_LINK_PAUSE_TX 0x20
1689#define I40E_AQ_LINK_PAUSE_RX 0x40
1690#define I40E_AQ_QUALIFIED_MODULE 0x80
1691 u8 ext_info;
1692#define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01
1693#define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02
1694#define I40E_AQ_LINK_TX_SHIFT 0x02
1695#define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT)
1696#define I40E_AQ_LINK_TX_ACTIVE 0x00
1697#define I40E_AQ_LINK_TX_DRAINED 0x01
1698#define I40E_AQ_LINK_TX_FLUSHED 0x03
1699 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */
1700 __le16 max_frame_size;
1701 u8 config;
1702#define I40E_AQ_CONFIG_CRC_ENA 0x04
1703#define I40E_AQ_CONFIG_PACING_MASK 0x78
1704 u8 reserved[5];
1705};
1706
1707I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status);
1708
1709/* Set event mask command (direct 0x613) */
1710struct i40e_aqc_set_phy_int_mask {
1711 u8 reserved[8];
1712 __le16 event_mask;
1713#define I40E_AQ_EVENT_LINK_UPDOWN 0x0002
1714#define I40E_AQ_EVENT_MEDIA_NA 0x0004
1715#define I40E_AQ_EVENT_LINK_FAULT 0x0008
1716#define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010
1717#define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020
1718#define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040
1719#define I40E_AQ_EVENT_AN_COMPLETED 0x0080
1720#define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100
1721#define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200
1722 u8 reserved1[6];
1723};
1724
1725I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask);
1726
1727/* Get Local AN advt register (direct 0x0614)
1728 * Set Local AN advt register (direct 0x0615)
1729 * Get Link Partner AN advt register (direct 0x0616)
1730 */
1731struct i40e_aqc_an_advt_reg {
1732 __le32 local_an_reg0;
1733 __le16 local_an_reg1;
1734 u8 reserved[10];
1735};
1736
1737I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg);
1738
1739/* Set Loopback mode (0x0618) */
1740struct i40e_aqc_set_lb_mode {
1741 __le16 lb_mode;
1742#define I40E_AQ_LB_PHY_LOCAL 0x01
1743#define I40E_AQ_LB_PHY_REMOTE 0x02
1744#define I40E_AQ_LB_MAC_LOCAL 0x04
1745 u8 reserved[14];
1746};
1747
1748I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode);
1749
1750/* Set PHY Reset command (0x0622) */
1751struct i40e_aqc_set_phy_reset {
1752 u8 reset_flags;
1753#define I40E_AQ_PHY_RESET_REQUEST 0x02
1754 u8 reserved[15];
1755};
1756
1757I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_reset);
1758
1759enum i40e_aq_phy_reg_type {
1760 I40E_AQC_PHY_REG_INTERNAL = 0x1,
1761 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2,
1762 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3
1763};
1764
1765/* NVM Read command (indirect 0x0701)
1766 * NVM Erase commands (direct 0x0702)
1767 * NVM Update commands (indirect 0x0703)
1768 */
1769struct i40e_aqc_nvm_update {
1770 u8 command_flags;
1771#define I40E_AQ_NVM_LAST_CMD 0x01
1772#define I40E_AQ_NVM_FLASH_ONLY 0x80
1773 u8 module_pointer;
1774 __le16 length;
1775 __le32 offset;
1776 __le32 addr_high;
1777 __le32 addr_low;
1778};
1779
1780I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update);
1781
1782/* Send to PF command (indirect 0x0801) id is only used by PF
1783 * Send to VF command (indirect 0x0802) id is only used by PF
1784 * Send to Peer PF command (indirect 0x0803)
1785 */
1786struct i40e_aqc_pf_vf_message {
1787 __le32 id;
1788 u8 reserved[4];
1789 __le32 addr_high;
1790 __le32 addr_low;
1791};
1792
1793I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message);
1794
1795/* Alternate structure */
1796
1797/* Direct write (direct 0x0900)
1798 * Direct read (direct 0x0902)
1799 */
1800struct i40e_aqc_alternate_write {
1801 __le32 address0;
1802 __le32 data0;
1803 __le32 address1;
1804 __le32 data1;
1805};
1806
1807I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write);
1808
1809/* Indirect write (indirect 0x0901)
1810 * Indirect read (indirect 0x0903)
1811 */
1812
1813struct i40e_aqc_alternate_ind_write {
1814 __le32 address;
1815 __le32 length;
1816 __le32 addr_high;
1817 __le32 addr_low;
1818};
1819
1820I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write);
1821
1822/* Done alternate write (direct 0x0904)
1823 * uses i40e_aq_desc
1824 */
1825struct i40e_aqc_alternate_write_done {
1826 __le16 cmd_flags;
1827#define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1
1828#define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0
1829#define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1
1830#define I40E_AQ_ALTERNATE_RESET_NEEDED 2
1831 u8 reserved[14];
1832};
1833
1834I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done);
1835
1836/* Set OEM mode (direct 0x0905) */
1837struct i40e_aqc_alternate_set_mode {
1838 __le32 mode;
1839#define I40E_AQ_ALTERNATE_MODE_NONE 0
1840#define I40E_AQ_ALTERNATE_MODE_OEM 1
1841 u8 reserved[12];
1842};
1843
1844I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode);
1845
1846/* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */
1847
1848/* async events 0x10xx */
1849
1850/* Lan Queue Overflow Event (direct, 0x1001) */
1851struct i40e_aqc_lan_overflow {
1852 __le32 prtdcb_rupto;
1853 __le32 otx_ctl;
1854 u8 reserved[8];
1855};
1856
1857I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow);
1858
1859/* Get LLDP MIB (indirect 0x0A00) */
1860struct i40e_aqc_lldp_get_mib {
1861 u8 type;
1862 u8 reserved1;
1863#define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3
1864#define I40E_AQ_LLDP_MIB_LOCAL 0x0
1865#define I40E_AQ_LLDP_MIB_REMOTE 0x1
1866#define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2
1867#define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC
1868#define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2
1869#define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0
1870#define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1
1871#define I40E_AQ_LLDP_TX_SHIFT 0x4
1872#define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT)
1873/* TX pause flags use I40E_AQ_LINK_TX_* above */
1874 __le16 local_len;
1875 __le16 remote_len;
1876 u8 reserved2[2];
1877 __le32 addr_high;
1878 __le32 addr_low;
1879};
1880
1881I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib);
1882
1883/* Configure LLDP MIB Change Event (direct 0x0A01)
1884 * also used for the event (with type in the command field)
1885 */
1886struct i40e_aqc_lldp_update_mib {
1887 u8 command;
1888#define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
1889#define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1
1890 u8 reserved[7];
1891 __le32 addr_high;
1892 __le32 addr_low;
1893};
1894
1895I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib);
1896
1897/* Add LLDP TLV (indirect 0x0A02)
1898 * Delete LLDP TLV (indirect 0x0A04)
1899 */
1900struct i40e_aqc_lldp_add_tlv {
1901 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
1902 u8 reserved1[1];
1903 __le16 len;
1904 u8 reserved2[4];
1905 __le32 addr_high;
1906 __le32 addr_low;
1907};
1908
1909I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv);
1910
1911/* Update LLDP TLV (indirect 0x0A03) */
1912struct i40e_aqc_lldp_update_tlv {
1913 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
1914 u8 reserved;
1915 __le16 old_len;
1916 __le16 new_offset;
1917 __le16 new_len;
1918 __le32 addr_high;
1919 __le32 addr_low;
1920};
1921
1922I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv);
1923
1924/* Stop LLDP (direct 0x0A05) */
1925struct i40e_aqc_lldp_stop {
1926 u8 command;
1927#define I40E_AQ_LLDP_AGENT_STOP 0x0
1928#define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1
1929 u8 reserved[15];
1930};
1931
1932I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop);
1933
1934/* Start LLDP (direct 0x0A06) */
1935
1936struct i40e_aqc_lldp_start {
1937 u8 command;
1938#define I40E_AQ_LLDP_AGENT_START 0x1
1939 u8 reserved[15];
1940};
1941
1942I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start);
1943
1944/* Apply MIB changes (0x0A07)
1945 * uses the generic struc as it contains no data
1946 */
1947
1948/* Add Udp Tunnel command and completion (direct 0x0B00) */
1949struct i40e_aqc_add_udp_tunnel {
1950 __le16 udp_port;
1951 u8 header_len; /* in DWords, 1 to 15 */
1952 u8 protocol_type;
1953#define I40E_AQC_TUNNEL_TYPE_TEREDO 0x0
1954#define I40E_AQC_TUNNEL_TYPE_VXLAN 0x2
1955#define I40E_AQC_TUNNEL_TYPE_NGE 0x3
1956 u8 variable_udp_length;
1957#define I40E_AQC_TUNNEL_FIXED_UDP_LENGTH 0x0
1958#define I40E_AQC_TUNNEL_VARIABLE_UDP_LENGTH 0x1
1959 u8 udp_key_index;
1960#define I40E_AQC_TUNNEL_KEY_INDEX_VXLAN 0x0
1961#define I40E_AQC_TUNNEL_KEY_INDEX_NGE 0x1
1962#define I40E_AQC_TUNNEL_KEY_INDEX_PROPRIETARY_UDP 0x2
1963 u8 reserved[10];
1964};
1965
1966I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel);
1967
1968struct i40e_aqc_add_udp_tunnel_completion {
1969 __le16 udp_port;
1970 u8 filter_entry_index;
1971 u8 multiple_pfs;
1972#define I40E_AQC_SINGLE_PF 0x0
1973#define I40E_AQC_MULTIPLE_PFS 0x1
1974 u8 total_filters;
1975 u8 reserved[11];
1976};
1977
1978I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion);
1979
1980/* remove UDP Tunnel command (0x0B01) */
1981struct i40e_aqc_remove_udp_tunnel {
1982 u8 reserved[2];
1983 u8 index; /* 0 to 15 */
1984 u8 pf_filters;
1985 u8 total_filters;
1986 u8 reserved2[11];
1987};
1988
1989I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel);
1990
1991struct i40e_aqc_del_udp_tunnel_completion {
1992 __le16 udp_port;
1993 u8 index; /* 0 to 15 */
1994 u8 multiple_pfs;
1995 u8 total_filters_used;
1996 u8 reserved;
1997 u8 tunnels_free;
1998 u8 reserved1[9];
1999};
2000
2001I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion);
2002
2003/* tunnel key structure 0x0B10 */
2004
2005struct i40e_aqc_tunnel_key_structure_A0 {
2006 __le16 key1_off;
2007 __le16 key1_len;
2008 __le16 key2_off;
2009 __le16 key2_len;
2010 __le16 flags;
2011#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01
2012/* response flags */
2013#define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01
2014#define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02
2015#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03
2016 u8 resreved[6];
2017};
2018
2019I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure_A0);
2020
2021struct i40e_aqc_tunnel_key_structure {
2022 u8 key1_off;
2023 u8 key2_off;
2024 u8 key1_len; /* 0 to 15 */
2025 u8 key2_len; /* 0 to 15 */
2026 u8 flags;
2027#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01
2028/* response flags */
2029#define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01
2030#define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02
2031#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03
2032 u8 network_key_index;
2033#define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0
2034#define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1
2035#define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2
2036#define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3
2037 u8 reserved[10];
2038};
2039
2040I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure);
2041
2042/* OEM mode commands (direct 0xFE0x) */
2043struct i40e_aqc_oem_param_change {
2044 __le32 param_type;
2045#define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0
2046#define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1
2047#define I40E_AQ_OEM_PARAM_MAC 2
2048 __le32 param_value1;
2049 u8 param_value2[8];
2050};
2051
2052I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change);
2053
2054struct i40e_aqc_oem_state_change {
2055 __le32 state;
2056#define I40E_AQ_OEM_STATE_LINK_DOWN 0x0
2057#define I40E_AQ_OEM_STATE_LINK_UP 0x1
2058 u8 reserved[12];
2059};
2060
2061I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change);
2062
2063/* debug commands */
2064
2065/* get device id (0xFF00) uses the generic structure */
2066
2067/* set test more (0xFF01, internal) */
2068
2069struct i40e_acq_set_test_mode {
2070 u8 mode;
2071#define I40E_AQ_TEST_PARTIAL 0
2072#define I40E_AQ_TEST_FULL 1
2073#define I40E_AQ_TEST_NVM 2
2074 u8 reserved[3];
2075 u8 command;
2076#define I40E_AQ_TEST_OPEN 0
2077#define I40E_AQ_TEST_CLOSE 1
2078#define I40E_AQ_TEST_INC 2
2079 u8 reserved2[3];
2080 __le32 address_high;
2081 __le32 address_low;
2082};
2083
2084I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode);
2085
2086/* Debug Read Register command (0xFF03)
2087 * Debug Write Register command (0xFF04)
2088 */
2089struct i40e_aqc_debug_reg_read_write {
2090 __le32 reserved;
2091 __le32 address;
2092 __le32 value_high;
2093 __le32 value_low;
2094};
2095
2096I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write);
2097
2098/* Scatter/gather Reg Read (indirect 0xFF05)
2099 * Scatter/gather Reg Write (indirect 0xFF06)
2100 */
2101
2102/* i40e_aq_desc is used for the command */
2103struct i40e_aqc_debug_reg_sg_element_data {
2104 __le32 address;
2105 __le32 value;
2106};
2107
2108/* Debug Modify register (direct 0xFF07) */
2109struct i40e_aqc_debug_modify_reg {
2110 __le32 address;
2111 __le32 value;
2112 __le32 clear_mask;
2113 __le32 set_mask;
2114};
2115
2116I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg);
2117
2118/* dump internal data (0xFF08, indirect) */
2119
2120#define I40E_AQ_CLUSTER_ID_AUX 0
2121#define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1
2122#define I40E_AQ_CLUSTER_ID_TXSCHED 2
2123#define I40E_AQ_CLUSTER_ID_HMC 3
2124#define I40E_AQ_CLUSTER_ID_MAC0 4
2125#define I40E_AQ_CLUSTER_ID_MAC1 5
2126#define I40E_AQ_CLUSTER_ID_MAC2 6
2127#define I40E_AQ_CLUSTER_ID_MAC3 7
2128#define I40E_AQ_CLUSTER_ID_DCB 8
2129#define I40E_AQ_CLUSTER_ID_EMP_MEM 9
2130#define I40E_AQ_CLUSTER_ID_PKT_BUF 10
2131#define I40E_AQ_CLUSTER_ID_ALTRAM 11
2132
2133struct i40e_aqc_debug_dump_internals {
2134 u8 cluster_id;
2135 u8 table_id;
2136 __le16 data_size;
2137 __le32 idx;
2138 __le32 address_high;
2139 __le32 address_low;
2140};
2141
2142I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals);
2143
2144struct i40e_aqc_debug_modify_internals {
2145 u8 cluster_id;
2146 u8 cluster_specific_params[7];
2147 __le32 address_high;
2148 __le32 address_low;
2149};
2150
2151I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals);
2152
2153#endif