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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Synopsys DesignWare I2C adapter driver (master only).
4 *
5 * Based on the TI DAVINCI I2C adapter driver.
6 *
7 * Copyright (C) 2006 Texas Instruments.
8 * Copyright (C) 2007 MontaVista Software Inc.
9 * Copyright (C) 2009 Provigent Ltd.
10 * Copyright (C) 2011, 2015, 2016 Intel Corporation.
11 */
12#include <linux/delay.h>
13#include <linux/err.h>
14#include <linux/errno.h>
15#include <linux/i2c.h>
16#include <linux/interrupt.h>
17#include <linux/io.h>
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/pci.h>
21#include <linux/pm.h>
22#include <linux/pm_runtime.h>
23#include <linux/power_supply.h>
24#include <linux/sched.h>
25#include <linux/slab.h>
26
27#include "i2c-designware-core.h"
28#include "i2c-ccgx-ucsi.h"
29
30#define DRIVER_NAME "i2c-designware-pci"
31
32enum dw_pci_ctl_id_t {
33 medfield,
34 merrifield,
35 baytrail,
36 cherrytrail,
37 haswell,
38 elkhartlake,
39 navi_amd,
40};
41
42/*
43 * This is a legacy structure to describe the hardware counters
44 * to configure signal timings on the bus. For Device Tree platforms
45 * one should use the respective properties and for ACPI there is
46 * a set of ACPI methods that provide these counters. No new
47 * platform should use this structure.
48 */
49struct dw_scl_sda_cfg {
50 u16 ss_hcnt;
51 u16 fs_hcnt;
52 u16 ss_lcnt;
53 u16 fs_lcnt;
54 u32 sda_hold_time;
55};
56
57struct dw_pci_controller {
58 u32 bus_num;
59 u32 flags;
60 struct dw_scl_sda_cfg *scl_sda_cfg;
61 int (*setup)(struct pci_dev *pdev, struct dw_pci_controller *c);
62 u32 (*get_clk_rate_khz)(struct dw_i2c_dev *dev);
63};
64
65/* Merrifield HCNT/LCNT/SDA hold time */
66static struct dw_scl_sda_cfg mrfld_config = {
67 .ss_hcnt = 0x2f8,
68 .fs_hcnt = 0x87,
69 .ss_lcnt = 0x37b,
70 .fs_lcnt = 0x10a,
71};
72
73/* BayTrail HCNT/LCNT/SDA hold time */
74static struct dw_scl_sda_cfg byt_config = {
75 .ss_hcnt = 0x200,
76 .fs_hcnt = 0x55,
77 .ss_lcnt = 0x200,
78 .fs_lcnt = 0x99,
79 .sda_hold_time = 0x6,
80};
81
82/* Haswell HCNT/LCNT/SDA hold time */
83static struct dw_scl_sda_cfg hsw_config = {
84 .ss_hcnt = 0x01b0,
85 .fs_hcnt = 0x48,
86 .ss_lcnt = 0x01fb,
87 .fs_lcnt = 0xa0,
88 .sda_hold_time = 0x9,
89};
90
91/* NAVI-AMD HCNT/LCNT/SDA hold time */
92static struct dw_scl_sda_cfg navi_amd_config = {
93 .ss_hcnt = 0x1ae,
94 .ss_lcnt = 0x23a,
95 .sda_hold_time = 0x9,
96};
97
98static u32 mfld_get_clk_rate_khz(struct dw_i2c_dev *dev)
99{
100 return 25000;
101}
102
103static int mfld_setup(struct pci_dev *pdev, struct dw_pci_controller *c)
104{
105 struct dw_i2c_dev *dev = pci_get_drvdata(pdev);
106
107 switch (pdev->device) {
108 case 0x0817:
109 dev->timings.bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ;
110 fallthrough;
111 case 0x0818:
112 case 0x0819:
113 c->bus_num = pdev->device - 0x817 + 3;
114 return 0;
115 case 0x082C:
116 case 0x082D:
117 case 0x082E:
118 c->bus_num = pdev->device - 0x82C + 0;
119 return 0;
120 }
121 return -ENODEV;
122}
123
124static int mrfld_setup(struct pci_dev *pdev, struct dw_pci_controller *c)
125{
126 /*
127 * On Intel Merrifield the user visible i2c buses are enumerated
128 * [1..7]. So, we add 1 to shift the default range. Besides that the
129 * first PCI slot provides 4 functions, that's why we have to add 0 to
130 * the first slot and 4 to the next one.
131 */
132 switch (PCI_SLOT(pdev->devfn)) {
133 case 8:
134 c->bus_num = PCI_FUNC(pdev->devfn) + 0 + 1;
135 return 0;
136 case 9:
137 c->bus_num = PCI_FUNC(pdev->devfn) + 4 + 1;
138 return 0;
139 }
140 return -ENODEV;
141}
142
143static u32 ehl_get_clk_rate_khz(struct dw_i2c_dev *dev)
144{
145 return 100000;
146}
147
148static u32 navi_amd_get_clk_rate_khz(struct dw_i2c_dev *dev)
149{
150 return 100000;
151}
152
153static int navi_amd_setup(struct pci_dev *pdev, struct dw_pci_controller *c)
154{
155 struct dw_i2c_dev *dev = pci_get_drvdata(pdev);
156
157 dev->flags |= MODEL_AMD_NAVI_GPU | ACCESS_POLLING;
158 dev->timings.bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ;
159 return 0;
160}
161
162static struct dw_pci_controller dw_pci_controllers[] = {
163 [medfield] = {
164 .bus_num = -1,
165 .setup = mfld_setup,
166 .get_clk_rate_khz = mfld_get_clk_rate_khz,
167 },
168 [merrifield] = {
169 .bus_num = -1,
170 .scl_sda_cfg = &mrfld_config,
171 .setup = mrfld_setup,
172 },
173 [baytrail] = {
174 .bus_num = -1,
175 .scl_sda_cfg = &byt_config,
176 },
177 [haswell] = {
178 .bus_num = -1,
179 .scl_sda_cfg = &hsw_config,
180 },
181 [cherrytrail] = {
182 .bus_num = -1,
183 .scl_sda_cfg = &byt_config,
184 },
185 [elkhartlake] = {
186 .bus_num = -1,
187 .get_clk_rate_khz = ehl_get_clk_rate_khz,
188 },
189 [navi_amd] = {
190 .bus_num = -1,
191 .scl_sda_cfg = &navi_amd_config,
192 .setup = navi_amd_setup,
193 .get_clk_rate_khz = navi_amd_get_clk_rate_khz,
194 },
195};
196
197static const struct property_entry dgpu_properties[] = {
198 /* USB-C doesn't power the system */
199 PROPERTY_ENTRY_U8("scope", POWER_SUPPLY_SCOPE_DEVICE),
200 {}
201};
202
203static const struct software_node dgpu_node = {
204 .properties = dgpu_properties,
205};
206
207static int i2c_dw_pci_probe(struct pci_dev *pdev,
208 const struct pci_device_id *id)
209{
210 struct device *device = &pdev->dev;
211 struct dw_i2c_dev *dev;
212 struct i2c_adapter *adap;
213 int r;
214 struct dw_pci_controller *controller;
215 struct dw_scl_sda_cfg *cfg;
216
217 if (id->driver_data >= ARRAY_SIZE(dw_pci_controllers))
218 return dev_err_probe(device, -EINVAL, "Invalid driver data %ld\n",
219 id->driver_data);
220
221 controller = &dw_pci_controllers[id->driver_data];
222
223 r = pcim_enable_device(pdev);
224 if (r)
225 return dev_err_probe(device, r, "Failed to enable I2C PCI device\n");
226
227 pci_set_master(pdev);
228
229 r = pcim_iomap_regions(pdev, 1 << 0, pci_name(pdev));
230 if (r)
231 return dev_err_probe(device, r, "I/O memory remapping failed\n");
232
233 dev = devm_kzalloc(device, sizeof(*dev), GFP_KERNEL);
234 if (!dev)
235 return -ENOMEM;
236
237 r = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
238 if (r < 0)
239 return r;
240
241 dev->get_clk_rate_khz = controller->get_clk_rate_khz;
242 dev->base = pcim_iomap_table(pdev)[0];
243 dev->dev = device;
244 dev->irq = pci_irq_vector(pdev, 0);
245 dev->flags |= controller->flags;
246
247 pci_set_drvdata(pdev, dev);
248
249 if (controller->setup) {
250 r = controller->setup(pdev, controller);
251 if (r)
252 return r;
253 }
254
255 r = i2c_dw_fw_parse_and_configure(dev);
256 if (r)
257 return r;
258
259 i2c_dw_configure(dev);
260
261 if (controller->scl_sda_cfg) {
262 cfg = controller->scl_sda_cfg;
263 dev->ss_hcnt = cfg->ss_hcnt;
264 dev->fs_hcnt = cfg->fs_hcnt;
265 dev->ss_lcnt = cfg->ss_lcnt;
266 dev->fs_lcnt = cfg->fs_lcnt;
267 dev->sda_hold_time = cfg->sda_hold_time;
268 }
269
270 adap = &dev->adapter;
271 adap->owner = THIS_MODULE;
272 adap->class = 0;
273 adap->nr = controller->bus_num;
274
275 r = i2c_dw_probe(dev);
276 if (r)
277 return r;
278
279 if ((dev->flags & MODEL_MASK) == MODEL_AMD_NAVI_GPU) {
280 dev->slave = i2c_new_ccgx_ucsi(&dev->adapter, dev->irq, &dgpu_node);
281 if (IS_ERR(dev->slave))
282 return dev_err_probe(device, PTR_ERR(dev->slave),
283 "register UCSI failed\n");
284 }
285
286 pm_runtime_set_autosuspend_delay(device, 1000);
287 pm_runtime_use_autosuspend(device);
288 pm_runtime_put_autosuspend(device);
289 pm_runtime_allow(device);
290
291 return 0;
292}
293
294static void i2c_dw_pci_remove(struct pci_dev *pdev)
295{
296 struct dw_i2c_dev *dev = pci_get_drvdata(pdev);
297 struct device *device = &pdev->dev;
298
299 i2c_dw_disable(dev);
300
301 pm_runtime_forbid(device);
302 pm_runtime_get_noresume(device);
303
304 i2c_del_adapter(&dev->adapter);
305}
306
307static const struct pci_device_id i2c_designware_pci_ids[] = {
308 /* Medfield */
309 { PCI_VDEVICE(INTEL, 0x0817), medfield },
310 { PCI_VDEVICE(INTEL, 0x0818), medfield },
311 { PCI_VDEVICE(INTEL, 0x0819), medfield },
312 { PCI_VDEVICE(INTEL, 0x082C), medfield },
313 { PCI_VDEVICE(INTEL, 0x082D), medfield },
314 { PCI_VDEVICE(INTEL, 0x082E), medfield },
315 /* Merrifield */
316 { PCI_VDEVICE(INTEL, 0x1195), merrifield },
317 { PCI_VDEVICE(INTEL, 0x1196), merrifield },
318 /* Baytrail */
319 { PCI_VDEVICE(INTEL, 0x0F41), baytrail },
320 { PCI_VDEVICE(INTEL, 0x0F42), baytrail },
321 { PCI_VDEVICE(INTEL, 0x0F43), baytrail },
322 { PCI_VDEVICE(INTEL, 0x0F44), baytrail },
323 { PCI_VDEVICE(INTEL, 0x0F45), baytrail },
324 { PCI_VDEVICE(INTEL, 0x0F46), baytrail },
325 { PCI_VDEVICE(INTEL, 0x0F47), baytrail },
326 /* Haswell */
327 { PCI_VDEVICE(INTEL, 0x9c61), haswell },
328 { PCI_VDEVICE(INTEL, 0x9c62), haswell },
329 /* Braswell / Cherrytrail */
330 { PCI_VDEVICE(INTEL, 0x22C1), cherrytrail },
331 { PCI_VDEVICE(INTEL, 0x22C2), cherrytrail },
332 { PCI_VDEVICE(INTEL, 0x22C3), cherrytrail },
333 { PCI_VDEVICE(INTEL, 0x22C4), cherrytrail },
334 { PCI_VDEVICE(INTEL, 0x22C5), cherrytrail },
335 { PCI_VDEVICE(INTEL, 0x22C6), cherrytrail },
336 { PCI_VDEVICE(INTEL, 0x22C7), cherrytrail },
337 /* Elkhart Lake (PSE I2C) */
338 { PCI_VDEVICE(INTEL, 0x4bb9), elkhartlake },
339 { PCI_VDEVICE(INTEL, 0x4bba), elkhartlake },
340 { PCI_VDEVICE(INTEL, 0x4bbb), elkhartlake },
341 { PCI_VDEVICE(INTEL, 0x4bbc), elkhartlake },
342 { PCI_VDEVICE(INTEL, 0x4bbd), elkhartlake },
343 { PCI_VDEVICE(INTEL, 0x4bbe), elkhartlake },
344 { PCI_VDEVICE(INTEL, 0x4bbf), elkhartlake },
345 { PCI_VDEVICE(INTEL, 0x4bc0), elkhartlake },
346 /* AMD NAVI */
347 { PCI_VDEVICE(ATI, 0x7314), navi_amd },
348 { PCI_VDEVICE(ATI, 0x73a4), navi_amd },
349 { PCI_VDEVICE(ATI, 0x73e4), navi_amd },
350 { PCI_VDEVICE(ATI, 0x73c4), navi_amd },
351 { PCI_VDEVICE(ATI, 0x7444), navi_amd },
352 { PCI_VDEVICE(ATI, 0x7464), navi_amd },
353 {}
354};
355MODULE_DEVICE_TABLE(pci, i2c_designware_pci_ids);
356
357static struct pci_driver dw_i2c_driver = {
358 .name = DRIVER_NAME,
359 .probe = i2c_dw_pci_probe,
360 .remove = i2c_dw_pci_remove,
361 .driver = {
362 .pm = pm_ptr(&i2c_dw_dev_pm_ops),
363 },
364 .id_table = i2c_designware_pci_ids,
365};
366module_pci_driver(dw_i2c_driver);
367
368MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
369MODULE_DESCRIPTION("Synopsys DesignWare PCI I2C bus adapter");
370MODULE_LICENSE("GPL");
371MODULE_IMPORT_NS("I2C_DW");
372MODULE_IMPORT_NS("I2C_DW_COMMON");
1/*
2 * Synopsys DesignWare I2C adapter driver (master only).
3 *
4 * Based on the TI DAVINCI I2C adapter driver.
5 *
6 * Copyright (C) 2006 Texas Instruments.
7 * Copyright (C) 2007 MontaVista Software Inc.
8 * Copyright (C) 2009 Provigent Ltd.
9 * Copyright (C) 2011 Intel corporation.
10 *
11 * ----------------------------------------------------------------------------
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 * ----------------------------------------------------------------------------
27 *
28 */
29
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/delay.h>
33#include <linux/i2c.h>
34#include <linux/errno.h>
35#include <linux/sched.h>
36#include <linux/err.h>
37#include <linux/interrupt.h>
38#include <linux/io.h>
39#include <linux/slab.h>
40#include <linux/pci.h>
41#include <linux/pm_runtime.h>
42#include "i2c-designware-core.h"
43
44#define DRIVER_NAME "i2c-designware-pci"
45
46enum dw_pci_ctl_id_t {
47 moorestown_0,
48 moorestown_1,
49 moorestown_2,
50
51 medfield_0,
52 medfield_1,
53 medfield_2,
54 medfield_3,
55 medfield_4,
56 medfield_5,
57
58 baytrail,
59};
60
61struct dw_scl_sda_cfg {
62 u32 ss_hcnt;
63 u32 fs_hcnt;
64 u32 ss_lcnt;
65 u32 fs_lcnt;
66 u32 sda_hold;
67};
68
69struct dw_pci_controller {
70 u32 bus_num;
71 u32 bus_cfg;
72 u32 tx_fifo_depth;
73 u32 rx_fifo_depth;
74 u32 clk_khz;
75 u32 functionality;
76 struct dw_scl_sda_cfg *scl_sda_cfg;
77};
78
79#define INTEL_MID_STD_CFG (DW_IC_CON_MASTER | \
80 DW_IC_CON_SLAVE_DISABLE | \
81 DW_IC_CON_RESTART_EN)
82
83#define DW_DEFAULT_FUNCTIONALITY (I2C_FUNC_I2C | \
84 I2C_FUNC_SMBUS_BYTE | \
85 I2C_FUNC_SMBUS_BYTE_DATA | \
86 I2C_FUNC_SMBUS_WORD_DATA | \
87 I2C_FUNC_SMBUS_I2C_BLOCK)
88
89/* BayTrail HCNT/LCNT/SDA hold time */
90static struct dw_scl_sda_cfg byt_config = {
91 .ss_hcnt = 0x200,
92 .fs_hcnt = 0x55,
93 .ss_lcnt = 0x200,
94 .fs_lcnt = 0x99,
95 .sda_hold = 0x6,
96};
97
98static struct dw_pci_controller dw_pci_controllers[] = {
99 [moorestown_0] = {
100 .bus_num = 0,
101 .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
102 .tx_fifo_depth = 32,
103 .rx_fifo_depth = 32,
104 .clk_khz = 25000,
105 },
106 [moorestown_1] = {
107 .bus_num = 1,
108 .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
109 .tx_fifo_depth = 32,
110 .rx_fifo_depth = 32,
111 .clk_khz = 25000,
112 },
113 [moorestown_2] = {
114 .bus_num = 2,
115 .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
116 .tx_fifo_depth = 32,
117 .rx_fifo_depth = 32,
118 .clk_khz = 25000,
119 },
120 [medfield_0] = {
121 .bus_num = 0,
122 .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
123 .tx_fifo_depth = 32,
124 .rx_fifo_depth = 32,
125 .clk_khz = 25000,
126 },
127 [medfield_1] = {
128 .bus_num = 1,
129 .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
130 .tx_fifo_depth = 32,
131 .rx_fifo_depth = 32,
132 .clk_khz = 25000,
133 },
134 [medfield_2] = {
135 .bus_num = 2,
136 .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
137 .tx_fifo_depth = 32,
138 .rx_fifo_depth = 32,
139 .clk_khz = 25000,
140 },
141 [medfield_3] = {
142 .bus_num = 3,
143 .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_STD,
144 .tx_fifo_depth = 32,
145 .rx_fifo_depth = 32,
146 .clk_khz = 25000,
147 },
148 [medfield_4] = {
149 .bus_num = 4,
150 .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
151 .tx_fifo_depth = 32,
152 .rx_fifo_depth = 32,
153 .clk_khz = 25000,
154 },
155 [medfield_5] = {
156 .bus_num = 5,
157 .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
158 .tx_fifo_depth = 32,
159 .rx_fifo_depth = 32,
160 .clk_khz = 25000,
161 },
162 [baytrail] = {
163 .bus_num = -1,
164 .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
165 .tx_fifo_depth = 32,
166 .rx_fifo_depth = 32,
167 .clk_khz = 100000,
168 .functionality = I2C_FUNC_10BIT_ADDR,
169 .scl_sda_cfg = &byt_config,
170 },
171};
172static struct i2c_algorithm i2c_dw_algo = {
173 .master_xfer = i2c_dw_xfer,
174 .functionality = i2c_dw_func,
175};
176
177#ifdef CONFIG_PM
178static int i2c_dw_pci_suspend(struct device *dev)
179{
180 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
181
182 i2c_dw_disable(pci_get_drvdata(pdev));
183 return 0;
184}
185
186static int i2c_dw_pci_resume(struct device *dev)
187{
188 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
189
190 return i2c_dw_init(pci_get_drvdata(pdev));
191}
192#endif
193
194static UNIVERSAL_DEV_PM_OPS(i2c_dw_pm_ops, i2c_dw_pci_suspend,
195 i2c_dw_pci_resume, NULL);
196
197static u32 i2c_dw_get_clk_rate_khz(struct dw_i2c_dev *dev)
198{
199 return dev->controller->clk_khz;
200}
201
202static int i2c_dw_pci_probe(struct pci_dev *pdev,
203 const struct pci_device_id *id)
204{
205 struct dw_i2c_dev *dev;
206 struct i2c_adapter *adap;
207 int r;
208 struct dw_pci_controller *controller;
209 struct dw_scl_sda_cfg *cfg;
210
211 if (id->driver_data >= ARRAY_SIZE(dw_pci_controllers)) {
212 dev_err(&pdev->dev, "%s: invalid driver data %ld\n", __func__,
213 id->driver_data);
214 return -EINVAL;
215 }
216
217 controller = &dw_pci_controllers[id->driver_data];
218
219 r = pcim_enable_device(pdev);
220 if (r) {
221 dev_err(&pdev->dev, "Failed to enable I2C PCI device (%d)\n",
222 r);
223 return r;
224 }
225
226 r = pcim_iomap_regions(pdev, 1 << 0, pci_name(pdev));
227 if (r) {
228 dev_err(&pdev->dev, "I/O memory remapping failed\n");
229 return r;
230 }
231
232 dev = devm_kzalloc(&pdev->dev, sizeof(struct dw_i2c_dev), GFP_KERNEL);
233 if (!dev)
234 return -ENOMEM;
235
236 init_completion(&dev->cmd_complete);
237 mutex_init(&dev->lock);
238 dev->clk = NULL;
239 dev->controller = controller;
240 dev->get_clk_rate_khz = i2c_dw_get_clk_rate_khz;
241 dev->base = pcim_iomap_table(pdev)[0];
242 dev->dev = &pdev->dev;
243 dev->functionality = controller->functionality |
244 DW_DEFAULT_FUNCTIONALITY;
245
246 dev->master_cfg = controller->bus_cfg;
247 if (controller->scl_sda_cfg) {
248 cfg = controller->scl_sda_cfg;
249 dev->ss_hcnt = cfg->ss_hcnt;
250 dev->fs_hcnt = cfg->fs_hcnt;
251 dev->ss_lcnt = cfg->ss_lcnt;
252 dev->fs_lcnt = cfg->fs_lcnt;
253 dev->sda_hold_time = cfg->sda_hold;
254 }
255
256 pci_set_drvdata(pdev, dev);
257
258 dev->tx_fifo_depth = controller->tx_fifo_depth;
259 dev->rx_fifo_depth = controller->rx_fifo_depth;
260 r = i2c_dw_init(dev);
261 if (r)
262 return r;
263
264 adap = &dev->adapter;
265 i2c_set_adapdata(adap, dev);
266 adap->owner = THIS_MODULE;
267 adap->class = 0;
268 adap->algo = &i2c_dw_algo;
269 adap->dev.parent = &pdev->dev;
270 adap->nr = controller->bus_num;
271
272 snprintf(adap->name, sizeof(adap->name), "i2c-designware-pci");
273
274 r = devm_request_irq(&pdev->dev, pdev->irq, i2c_dw_isr, IRQF_SHARED,
275 adap->name, dev);
276 if (r) {
277 dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq);
278 return r;
279 }
280
281 i2c_dw_disable_int(dev);
282 i2c_dw_clear_int(dev);
283 r = i2c_add_numbered_adapter(adap);
284 if (r) {
285 dev_err(&pdev->dev, "failure adding adapter\n");
286 return r;
287 }
288
289 pm_runtime_set_autosuspend_delay(&pdev->dev, 1000);
290 pm_runtime_use_autosuspend(&pdev->dev);
291 pm_runtime_put_autosuspend(&pdev->dev);
292 pm_runtime_allow(&pdev->dev);
293
294 return 0;
295}
296
297static void i2c_dw_pci_remove(struct pci_dev *pdev)
298{
299 struct dw_i2c_dev *dev = pci_get_drvdata(pdev);
300
301 i2c_dw_disable(dev);
302 pm_runtime_forbid(&pdev->dev);
303 pm_runtime_get_noresume(&pdev->dev);
304
305 i2c_del_adapter(&dev->adapter);
306}
307
308/* work with hotplug and coldplug */
309MODULE_ALIAS("i2c_designware-pci");
310
311static const struct pci_device_id i2_designware_pci_ids[] = {
312 /* Moorestown */
313 { PCI_VDEVICE(INTEL, 0x0802), moorestown_0 },
314 { PCI_VDEVICE(INTEL, 0x0803), moorestown_1 },
315 { PCI_VDEVICE(INTEL, 0x0804), moorestown_2 },
316 /* Medfield */
317 { PCI_VDEVICE(INTEL, 0x0817), medfield_3,},
318 { PCI_VDEVICE(INTEL, 0x0818), medfield_4 },
319 { PCI_VDEVICE(INTEL, 0x0819), medfield_5 },
320 { PCI_VDEVICE(INTEL, 0x082C), medfield_0 },
321 { PCI_VDEVICE(INTEL, 0x082D), medfield_1 },
322 { PCI_VDEVICE(INTEL, 0x082E), medfield_2 },
323 /* Baytrail */
324 { PCI_VDEVICE(INTEL, 0x0F41), baytrail },
325 { PCI_VDEVICE(INTEL, 0x0F42), baytrail },
326 { PCI_VDEVICE(INTEL, 0x0F43), baytrail },
327 { PCI_VDEVICE(INTEL, 0x0F44), baytrail },
328 { PCI_VDEVICE(INTEL, 0x0F45), baytrail },
329 { PCI_VDEVICE(INTEL, 0x0F46), baytrail },
330 { PCI_VDEVICE(INTEL, 0x0F47), baytrail },
331 { 0,}
332};
333MODULE_DEVICE_TABLE(pci, i2_designware_pci_ids);
334
335static struct pci_driver dw_i2c_driver = {
336 .name = DRIVER_NAME,
337 .id_table = i2_designware_pci_ids,
338 .probe = i2c_dw_pci_probe,
339 .remove = i2c_dw_pci_remove,
340 .driver = {
341 .pm = &i2c_dw_pm_ops,
342 },
343};
344
345module_pci_driver(dw_i2c_driver);
346
347MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
348MODULE_DESCRIPTION("Synopsys DesignWare PCI I2C bus adapter");
349MODULE_LICENSE("GPL");