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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
4 */
5
6#ifndef _CORESIGHT_CORESIGHT_ETM_H
7#define _CORESIGHT_CORESIGHT_ETM_H
8
9#include <asm/local.h>
10#include <linux/const.h>
11#include <linux/spinlock.h>
12#include <linux/types.h>
13#include "coresight-priv.h"
14
15/*
16 * Device registers:
17 * 0x000 - 0x2FC: Trace registers
18 * 0x300 - 0x314: Management registers
19 * 0x318 - 0xEFC: Trace registers
20 * 0xF00: Management registers
21 * 0xFA0 - 0xFA4: Trace registers
22 * 0xFA8 - 0xFFC: Management registers
23 */
24/* Trace registers (0x000-0x2FC) */
25/* Main control and configuration registers */
26#define TRCPRGCTLR 0x004
27#define TRCPROCSELR 0x008
28#define TRCSTATR 0x00C
29#define TRCCONFIGR 0x010
30#define TRCAUXCTLR 0x018
31#define TRCEVENTCTL0R 0x020
32#define TRCEVENTCTL1R 0x024
33#define TRCRSR 0x028
34#define TRCSTALLCTLR 0x02C
35#define TRCTSCTLR 0x030
36#define TRCSYNCPR 0x034
37#define TRCCCCTLR 0x038
38#define TRCBBCTLR 0x03C
39#define TRCTRACEIDR 0x040
40#define TRCQCTLR 0x044
41/* Filtering control registers */
42#define TRCVICTLR 0x080
43#define TRCVIIECTLR 0x084
44#define TRCVISSCTLR 0x088
45#define TRCVIPCSSCTLR 0x08C
46/* Derived resources registers */
47#define TRCSEQEVRn(n) (0x100 + (n * 4)) /* n = 0-2 */
48#define TRCSEQRSTEVR 0x118
49#define TRCSEQSTR 0x11C
50#define TRCEXTINSELR 0x120
51#define TRCEXTINSELRn(n) (0x120 + (n * 4)) /* n = 0-3 */
52#define TRCCNTRLDVRn(n) (0x140 + (n * 4)) /* n = 0-3 */
53#define TRCCNTCTLRn(n) (0x150 + (n * 4)) /* n = 0-3 */
54#define TRCCNTVRn(n) (0x160 + (n * 4)) /* n = 0-3 */
55/* ID registers */
56#define TRCIDR8 0x180
57#define TRCIDR9 0x184
58#define TRCIDR10 0x188
59#define TRCIDR11 0x18C
60#define TRCIDR12 0x190
61#define TRCIDR13 0x194
62#define TRCIMSPEC0 0x1C0
63#define TRCIMSPECn(n) (0x1C0 + (n * 4)) /* n = 1-7 */
64#define TRCIDR0 0x1E0
65#define TRCIDR1 0x1E4
66#define TRCIDR2 0x1E8
67#define TRCIDR3 0x1EC
68#define TRCIDR4 0x1F0
69#define TRCIDR5 0x1F4
70#define TRCIDR6 0x1F8
71#define TRCIDR7 0x1FC
72/*
73 * Resource selection registers, n = 2-31.
74 * First pair (regs 0, 1) is always present and is reserved.
75 */
76#define TRCRSCTLRn(n) (0x200 + (n * 4))
77/* Single-shot comparator registers, n = 0-7 */
78#define TRCSSCCRn(n) (0x280 + (n * 4))
79#define TRCSSCSRn(n) (0x2A0 + (n * 4))
80#define TRCSSPCICRn(n) (0x2C0 + (n * 4))
81/* Management registers (0x300-0x314) */
82#define TRCOSLAR 0x300
83#define TRCOSLSR 0x304
84#define TRCPDCR 0x310
85#define TRCPDSR 0x314
86/* Trace registers (0x318-0xEFC) */
87/* Address Comparator registers n = 0-15 */
88#define TRCACVRn(n) (0x400 + (n * 8))
89#define TRCACATRn(n) (0x480 + (n * 8))
90/* ContextID/Virtual ContextID comparators, n = 0-7 */
91#define TRCCIDCVRn(n) (0x600 + (n * 8))
92#define TRCVMIDCVRn(n) (0x640 + (n * 8))
93#define TRCCIDCCTLR0 0x680
94#define TRCCIDCCTLR1 0x684
95#define TRCVMIDCCTLR0 0x688
96#define TRCVMIDCCTLR1 0x68C
97/* Management register (0xF00) */
98/* Integration control registers */
99#define TRCITCTRL 0xF00
100/* Trace registers (0xFA0-0xFA4) */
101/* Claim tag registers */
102#define TRCCLAIMSET 0xFA0
103#define TRCCLAIMCLR 0xFA4
104/* Management registers (0xFA8-0xFFC) */
105#define TRCDEVAFF0 0xFA8
106#define TRCDEVAFF1 0xFAC
107#define TRCLAR 0xFB0
108#define TRCLSR 0xFB4
109#define TRCAUTHSTATUS 0xFB8
110#define TRCDEVARCH 0xFBC
111#define TRCDEVID 0xFC8
112#define TRCDEVTYPE 0xFCC
113#define TRCPIDR4 0xFD0
114#define TRCPIDR5 0xFD4
115#define TRCPIDR6 0xFD8
116#define TRCPIDR7 0xFDC
117#define TRCPIDR0 0xFE0
118#define TRCPIDR1 0xFE4
119#define TRCPIDR2 0xFE8
120#define TRCPIDR3 0xFEC
121#define TRCCIDR0 0xFF0
122#define TRCCIDR1 0xFF4
123#define TRCCIDR2 0xFF8
124#define TRCCIDR3 0xFFC
125
126#define TRCRSR_TA BIT(12)
127
128/*
129 * Bit positions of registers that are defined above, in the sysreg.h style
130 * of _MASK for multi bit fields and BIT() for single bits.
131 */
132#define TRCIDR0_INSTP0_MASK GENMASK(2, 1)
133#define TRCIDR0_TRCBB BIT(5)
134#define TRCIDR0_TRCCOND BIT(6)
135#define TRCIDR0_TRCCCI BIT(7)
136#define TRCIDR0_RETSTACK BIT(9)
137#define TRCIDR0_NUMEVENT_MASK GENMASK(11, 10)
138#define TRCIDR0_QFILT BIT(14)
139#define TRCIDR0_QSUPP_MASK GENMASK(16, 15)
140#define TRCIDR0_TSSIZE_MASK GENMASK(28, 24)
141
142#define TRCIDR2_CIDSIZE_MASK GENMASK(9, 5)
143#define TRCIDR2_VMIDSIZE_MASK GENMASK(14, 10)
144#define TRCIDR2_CCSIZE_MASK GENMASK(28, 25)
145
146#define TRCIDR3_CCITMIN_MASK GENMASK(11, 0)
147#define TRCIDR3_EXLEVEL_S_MASK GENMASK(19, 16)
148#define TRCIDR3_EXLEVEL_NS_MASK GENMASK(23, 20)
149#define TRCIDR3_TRCERR BIT(24)
150#define TRCIDR3_SYNCPR BIT(25)
151#define TRCIDR3_STALLCTL BIT(26)
152#define TRCIDR3_SYSSTALL BIT(27)
153#define TRCIDR3_NUMPROC_LO_MASK GENMASK(30, 28)
154#define TRCIDR3_NUMPROC_HI_MASK GENMASK(13, 12)
155#define TRCIDR3_NOOVERFLOW BIT(31)
156
157#define TRCIDR4_NUMACPAIRS_MASK GENMASK(3, 0)
158#define TRCIDR4_NUMPC_MASK GENMASK(15, 12)
159#define TRCIDR4_NUMRSPAIR_MASK GENMASK(19, 16)
160#define TRCIDR4_NUMSSCC_MASK GENMASK(23, 20)
161#define TRCIDR4_NUMCIDC_MASK GENMASK(27, 24)
162#define TRCIDR4_NUMVMIDC_MASK GENMASK(31, 28)
163
164#define TRCIDR5_NUMEXTIN_MASK GENMASK(8, 0)
165#define TRCIDR5_TRACEIDSIZE_MASK GENMASK(21, 16)
166#define TRCIDR5_ATBTRIG BIT(22)
167#define TRCIDR5_LPOVERRIDE BIT(23)
168#define TRCIDR5_NUMSEQSTATE_MASK GENMASK(27, 25)
169#define TRCIDR5_NUMCNTR_MASK GENMASK(30, 28)
170
171#define TRCCONFIGR_INSTP0_LOAD BIT(1)
172#define TRCCONFIGR_INSTP0_STORE BIT(2)
173#define TRCCONFIGR_INSTP0_LOAD_STORE (TRCCONFIGR_INSTP0_LOAD | TRCCONFIGR_INSTP0_STORE)
174#define TRCCONFIGR_BB BIT(3)
175#define TRCCONFIGR_CCI BIT(4)
176#define TRCCONFIGR_CID BIT(6)
177#define TRCCONFIGR_VMID BIT(7)
178#define TRCCONFIGR_COND_MASK GENMASK(10, 8)
179#define TRCCONFIGR_TS BIT(11)
180#define TRCCONFIGR_RS BIT(12)
181#define TRCCONFIGR_QE_W_COUNTS BIT(13)
182#define TRCCONFIGR_QE_WO_COUNTS BIT(14)
183#define TRCCONFIGR_VMIDOPT BIT(15)
184#define TRCCONFIGR_DA BIT(16)
185#define TRCCONFIGR_DV BIT(17)
186
187#define TRCEVENTCTL1R_INSTEN_MASK GENMASK(3, 0)
188#define TRCEVENTCTL1R_INSTEN_0 BIT(0)
189#define TRCEVENTCTL1R_INSTEN_1 BIT(1)
190#define TRCEVENTCTL1R_INSTEN_2 BIT(2)
191#define TRCEVENTCTL1R_INSTEN_3 BIT(3)
192#define TRCEVENTCTL1R_ATB BIT(11)
193#define TRCEVENTCTL1R_LPOVERRIDE BIT(12)
194
195#define TRCSTALLCTLR_ISTALL BIT(8)
196#define TRCSTALLCTLR_INSTPRIORITY BIT(10)
197#define TRCSTALLCTLR_NOOVERFLOW BIT(13)
198
199#define TRCVICTLR_EVENT_MASK GENMASK(7, 0)
200#define TRCVICTLR_SSSTATUS BIT(9)
201#define TRCVICTLR_TRCRESET BIT(10)
202#define TRCVICTLR_TRCERR BIT(11)
203#define TRCVICTLR_EXLEVEL_MASK GENMASK(22, 16)
204#define TRCVICTLR_EXLEVEL_S_MASK GENMASK(19, 16)
205#define TRCVICTLR_EXLEVEL_NS_MASK GENMASK(22, 20)
206
207#define TRCACATRn_TYPE_MASK GENMASK(1, 0)
208#define TRCACATRn_CONTEXTTYPE_MASK GENMASK(3, 2)
209#define TRCACATRn_CONTEXTTYPE_CTXID BIT(2)
210#define TRCACATRn_CONTEXTTYPE_VMID BIT(3)
211#define TRCACATRn_CONTEXT_MASK GENMASK(6, 4)
212#define TRCACATRn_EXLEVEL_MASK GENMASK(14, 8)
213
214#define TRCSSCSRn_STATUS BIT(31)
215#define TRCSSCCRn_SAC_ARC_RST_MASK GENMASK(24, 0)
216
217#define TRCSSPCICRn_PC_MASK GENMASK(7, 0)
218
219#define TRCBBCTLR_MODE BIT(8)
220#define TRCBBCTLR_RANGE_MASK GENMASK(7, 0)
221
222#define TRCRSCTLRn_PAIRINV BIT(21)
223#define TRCRSCTLRn_INV BIT(20)
224#define TRCRSCTLRn_GROUP_MASK GENMASK(19, 16)
225#define TRCRSCTLRn_SELECT_MASK GENMASK(15, 0)
226
227/*
228 * System instructions to access ETM registers.
229 * See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions
230 */
231#define ETM4x_OFFSET_TO_REG(x) ((x) >> 2)
232
233#define ETM4x_CRn(n) (((n) >> 7) & 0x7)
234#define ETM4x_Op2(n) (((n) >> 4) & 0x7)
235#define ETM4x_CRm(n) ((n) & 0xf)
236
237#include <asm/sysreg.h>
238#define ETM4x_REG_NUM_TO_SYSREG(n) \
239 sys_reg(2, 1, ETM4x_CRn(n), ETM4x_CRm(n), ETM4x_Op2(n))
240
241#define READ_ETM4x_REG(reg) \
242 read_sysreg_s(ETM4x_REG_NUM_TO_SYSREG((reg)))
243#define WRITE_ETM4x_REG(val, reg) \
244 write_sysreg_s(val, ETM4x_REG_NUM_TO_SYSREG((reg)))
245
246#define read_etm4x_sysreg_const_offset(offset) \
247 READ_ETM4x_REG(ETM4x_OFFSET_TO_REG(offset))
248
249#define write_etm4x_sysreg_const_offset(val, offset) \
250 WRITE_ETM4x_REG(val, ETM4x_OFFSET_TO_REG(offset))
251
252#define CASE_READ(res, x) \
253 case (x): { (res) = read_etm4x_sysreg_const_offset((x)); break; }
254
255#define CASE_WRITE(val, x) \
256 case (x): { write_etm4x_sysreg_const_offset((val), (x)); break; }
257
258#define CASE_NOP(__unused, x) \
259 case (x): /* fall through */
260
261#define ETE_ONLY_SYSREG_LIST(op, val) \
262 CASE_##op((val), TRCRSR) \
263 CASE_##op((val), TRCEXTINSELRn(1)) \
264 CASE_##op((val), TRCEXTINSELRn(2)) \
265 CASE_##op((val), TRCEXTINSELRn(3))
266
267/* List of registers accessible via System instructions */
268#define ETM4x_ONLY_SYSREG_LIST(op, val) \
269 CASE_##op((val), TRCPROCSELR) \
270 CASE_##op((val), TRCOSLAR)
271
272#define ETM_COMMON_SYSREG_LIST(op, val) \
273 CASE_##op((val), TRCPRGCTLR) \
274 CASE_##op((val), TRCSTATR) \
275 CASE_##op((val), TRCCONFIGR) \
276 CASE_##op((val), TRCAUXCTLR) \
277 CASE_##op((val), TRCEVENTCTL0R) \
278 CASE_##op((val), TRCEVENTCTL1R) \
279 CASE_##op((val), TRCSTALLCTLR) \
280 CASE_##op((val), TRCTSCTLR) \
281 CASE_##op((val), TRCSYNCPR) \
282 CASE_##op((val), TRCCCCTLR) \
283 CASE_##op((val), TRCBBCTLR) \
284 CASE_##op((val), TRCTRACEIDR) \
285 CASE_##op((val), TRCQCTLR) \
286 CASE_##op((val), TRCVICTLR) \
287 CASE_##op((val), TRCVIIECTLR) \
288 CASE_##op((val), TRCVISSCTLR) \
289 CASE_##op((val), TRCVIPCSSCTLR) \
290 CASE_##op((val), TRCSEQEVRn(0)) \
291 CASE_##op((val), TRCSEQEVRn(1)) \
292 CASE_##op((val), TRCSEQEVRn(2)) \
293 CASE_##op((val), TRCSEQRSTEVR) \
294 CASE_##op((val), TRCSEQSTR) \
295 CASE_##op((val), TRCEXTINSELR) \
296 CASE_##op((val), TRCCNTRLDVRn(0)) \
297 CASE_##op((val), TRCCNTRLDVRn(1)) \
298 CASE_##op((val), TRCCNTRLDVRn(2)) \
299 CASE_##op((val), TRCCNTRLDVRn(3)) \
300 CASE_##op((val), TRCCNTCTLRn(0)) \
301 CASE_##op((val), TRCCNTCTLRn(1)) \
302 CASE_##op((val), TRCCNTCTLRn(2)) \
303 CASE_##op((val), TRCCNTCTLRn(3)) \
304 CASE_##op((val), TRCCNTVRn(0)) \
305 CASE_##op((val), TRCCNTVRn(1)) \
306 CASE_##op((val), TRCCNTVRn(2)) \
307 CASE_##op((val), TRCCNTVRn(3)) \
308 CASE_##op((val), TRCIDR8) \
309 CASE_##op((val), TRCIDR9) \
310 CASE_##op((val), TRCIDR10) \
311 CASE_##op((val), TRCIDR11) \
312 CASE_##op((val), TRCIDR12) \
313 CASE_##op((val), TRCIDR13) \
314 CASE_##op((val), TRCIMSPECn(0)) \
315 CASE_##op((val), TRCIMSPECn(1)) \
316 CASE_##op((val), TRCIMSPECn(2)) \
317 CASE_##op((val), TRCIMSPECn(3)) \
318 CASE_##op((val), TRCIMSPECn(4)) \
319 CASE_##op((val), TRCIMSPECn(5)) \
320 CASE_##op((val), TRCIMSPECn(6)) \
321 CASE_##op((val), TRCIMSPECn(7)) \
322 CASE_##op((val), TRCIDR0) \
323 CASE_##op((val), TRCIDR1) \
324 CASE_##op((val), TRCIDR2) \
325 CASE_##op((val), TRCIDR3) \
326 CASE_##op((val), TRCIDR4) \
327 CASE_##op((val), TRCIDR5) \
328 CASE_##op((val), TRCIDR6) \
329 CASE_##op((val), TRCIDR7) \
330 CASE_##op((val), TRCRSCTLRn(2)) \
331 CASE_##op((val), TRCRSCTLRn(3)) \
332 CASE_##op((val), TRCRSCTLRn(4)) \
333 CASE_##op((val), TRCRSCTLRn(5)) \
334 CASE_##op((val), TRCRSCTLRn(6)) \
335 CASE_##op((val), TRCRSCTLRn(7)) \
336 CASE_##op((val), TRCRSCTLRn(8)) \
337 CASE_##op((val), TRCRSCTLRn(9)) \
338 CASE_##op((val), TRCRSCTLRn(10)) \
339 CASE_##op((val), TRCRSCTLRn(11)) \
340 CASE_##op((val), TRCRSCTLRn(12)) \
341 CASE_##op((val), TRCRSCTLRn(13)) \
342 CASE_##op((val), TRCRSCTLRn(14)) \
343 CASE_##op((val), TRCRSCTLRn(15)) \
344 CASE_##op((val), TRCRSCTLRn(16)) \
345 CASE_##op((val), TRCRSCTLRn(17)) \
346 CASE_##op((val), TRCRSCTLRn(18)) \
347 CASE_##op((val), TRCRSCTLRn(19)) \
348 CASE_##op((val), TRCRSCTLRn(20)) \
349 CASE_##op((val), TRCRSCTLRn(21)) \
350 CASE_##op((val), TRCRSCTLRn(22)) \
351 CASE_##op((val), TRCRSCTLRn(23)) \
352 CASE_##op((val), TRCRSCTLRn(24)) \
353 CASE_##op((val), TRCRSCTLRn(25)) \
354 CASE_##op((val), TRCRSCTLRn(26)) \
355 CASE_##op((val), TRCRSCTLRn(27)) \
356 CASE_##op((val), TRCRSCTLRn(28)) \
357 CASE_##op((val), TRCRSCTLRn(29)) \
358 CASE_##op((val), TRCRSCTLRn(30)) \
359 CASE_##op((val), TRCRSCTLRn(31)) \
360 CASE_##op((val), TRCSSCCRn(0)) \
361 CASE_##op((val), TRCSSCCRn(1)) \
362 CASE_##op((val), TRCSSCCRn(2)) \
363 CASE_##op((val), TRCSSCCRn(3)) \
364 CASE_##op((val), TRCSSCCRn(4)) \
365 CASE_##op((val), TRCSSCCRn(5)) \
366 CASE_##op((val), TRCSSCCRn(6)) \
367 CASE_##op((val), TRCSSCCRn(7)) \
368 CASE_##op((val), TRCSSCSRn(0)) \
369 CASE_##op((val), TRCSSCSRn(1)) \
370 CASE_##op((val), TRCSSCSRn(2)) \
371 CASE_##op((val), TRCSSCSRn(3)) \
372 CASE_##op((val), TRCSSCSRn(4)) \
373 CASE_##op((val), TRCSSCSRn(5)) \
374 CASE_##op((val), TRCSSCSRn(6)) \
375 CASE_##op((val), TRCSSCSRn(7)) \
376 CASE_##op((val), TRCSSPCICRn(0)) \
377 CASE_##op((val), TRCSSPCICRn(1)) \
378 CASE_##op((val), TRCSSPCICRn(2)) \
379 CASE_##op((val), TRCSSPCICRn(3)) \
380 CASE_##op((val), TRCSSPCICRn(4)) \
381 CASE_##op((val), TRCSSPCICRn(5)) \
382 CASE_##op((val), TRCSSPCICRn(6)) \
383 CASE_##op((val), TRCSSPCICRn(7)) \
384 CASE_##op((val), TRCOSLSR) \
385 CASE_##op((val), TRCACVRn(0)) \
386 CASE_##op((val), TRCACVRn(1)) \
387 CASE_##op((val), TRCACVRn(2)) \
388 CASE_##op((val), TRCACVRn(3)) \
389 CASE_##op((val), TRCACVRn(4)) \
390 CASE_##op((val), TRCACVRn(5)) \
391 CASE_##op((val), TRCACVRn(6)) \
392 CASE_##op((val), TRCACVRn(7)) \
393 CASE_##op((val), TRCACVRn(8)) \
394 CASE_##op((val), TRCACVRn(9)) \
395 CASE_##op((val), TRCACVRn(10)) \
396 CASE_##op((val), TRCACVRn(11)) \
397 CASE_##op((val), TRCACVRn(12)) \
398 CASE_##op((val), TRCACVRn(13)) \
399 CASE_##op((val), TRCACVRn(14)) \
400 CASE_##op((val), TRCACVRn(15)) \
401 CASE_##op((val), TRCACATRn(0)) \
402 CASE_##op((val), TRCACATRn(1)) \
403 CASE_##op((val), TRCACATRn(2)) \
404 CASE_##op((val), TRCACATRn(3)) \
405 CASE_##op((val), TRCACATRn(4)) \
406 CASE_##op((val), TRCACATRn(5)) \
407 CASE_##op((val), TRCACATRn(6)) \
408 CASE_##op((val), TRCACATRn(7)) \
409 CASE_##op((val), TRCACATRn(8)) \
410 CASE_##op((val), TRCACATRn(9)) \
411 CASE_##op((val), TRCACATRn(10)) \
412 CASE_##op((val), TRCACATRn(11)) \
413 CASE_##op((val), TRCACATRn(12)) \
414 CASE_##op((val), TRCACATRn(13)) \
415 CASE_##op((val), TRCACATRn(14)) \
416 CASE_##op((val), TRCACATRn(15)) \
417 CASE_##op((val), TRCCIDCVRn(0)) \
418 CASE_##op((val), TRCCIDCVRn(1)) \
419 CASE_##op((val), TRCCIDCVRn(2)) \
420 CASE_##op((val), TRCCIDCVRn(3)) \
421 CASE_##op((val), TRCCIDCVRn(4)) \
422 CASE_##op((val), TRCCIDCVRn(5)) \
423 CASE_##op((val), TRCCIDCVRn(6)) \
424 CASE_##op((val), TRCCIDCVRn(7)) \
425 CASE_##op((val), TRCVMIDCVRn(0)) \
426 CASE_##op((val), TRCVMIDCVRn(1)) \
427 CASE_##op((val), TRCVMIDCVRn(2)) \
428 CASE_##op((val), TRCVMIDCVRn(3)) \
429 CASE_##op((val), TRCVMIDCVRn(4)) \
430 CASE_##op((val), TRCVMIDCVRn(5)) \
431 CASE_##op((val), TRCVMIDCVRn(6)) \
432 CASE_##op((val), TRCVMIDCVRn(7)) \
433 CASE_##op((val), TRCCIDCCTLR0) \
434 CASE_##op((val), TRCCIDCCTLR1) \
435 CASE_##op((val), TRCVMIDCCTLR0) \
436 CASE_##op((val), TRCVMIDCCTLR1) \
437 CASE_##op((val), TRCCLAIMSET) \
438 CASE_##op((val), TRCCLAIMCLR) \
439 CASE_##op((val), TRCAUTHSTATUS) \
440 CASE_##op((val), TRCDEVARCH) \
441 CASE_##op((val), TRCDEVID)
442
443/* List of registers only accessible via memory-mapped interface */
444#define ETM_MMAP_LIST(op, val) \
445 CASE_##op((val), TRCDEVTYPE) \
446 CASE_##op((val), TRCPDCR) \
447 CASE_##op((val), TRCPDSR) \
448 CASE_##op((val), TRCDEVAFF0) \
449 CASE_##op((val), TRCDEVAFF1) \
450 CASE_##op((val), TRCLAR) \
451 CASE_##op((val), TRCLSR) \
452 CASE_##op((val), TRCITCTRL) \
453 CASE_##op((val), TRCPIDR4) \
454 CASE_##op((val), TRCPIDR0) \
455 CASE_##op((val), TRCPIDR1) \
456 CASE_##op((val), TRCPIDR2) \
457 CASE_##op((val), TRCPIDR3)
458
459#define ETM4x_READ_SYSREG_CASES(res) \
460 ETM_COMMON_SYSREG_LIST(READ, (res)) \
461 ETM4x_ONLY_SYSREG_LIST(READ, (res))
462
463#define ETM4x_WRITE_SYSREG_CASES(val) \
464 ETM_COMMON_SYSREG_LIST(WRITE, (val)) \
465 ETM4x_ONLY_SYSREG_LIST(WRITE, (val))
466
467#define ETM_COMMON_SYSREG_LIST_CASES \
468 ETM_COMMON_SYSREG_LIST(NOP, __unused)
469
470#define ETM4x_ONLY_SYSREG_LIST_CASES \
471 ETM4x_ONLY_SYSREG_LIST(NOP, __unused)
472
473#define ETM4x_SYSREG_LIST_CASES \
474 ETM_COMMON_SYSREG_LIST_CASES \
475 ETM4x_ONLY_SYSREG_LIST(NOP, __unused)
476
477#define ETM4x_MMAP_LIST_CASES ETM_MMAP_LIST(NOP, __unused)
478
479/* ETE only supports system register access */
480#define ETE_READ_CASES(res) \
481 ETM_COMMON_SYSREG_LIST(READ, (res)) \
482 ETE_ONLY_SYSREG_LIST(READ, (res))
483
484#define ETE_WRITE_CASES(val) \
485 ETM_COMMON_SYSREG_LIST(WRITE, (val)) \
486 ETE_ONLY_SYSREG_LIST(WRITE, (val))
487
488#define ETE_ONLY_SYSREG_LIST_CASES \
489 ETE_ONLY_SYSREG_LIST(NOP, __unused)
490
491#define read_etm4x_sysreg_offset(offset, _64bit) \
492 ({ \
493 u64 __val; \
494 \
495 if (__is_constexpr((offset))) \
496 __val = read_etm4x_sysreg_const_offset((offset)); \
497 else \
498 __val = etm4x_sysreg_read((offset), true, (_64bit)); \
499 __val; \
500 })
501
502#define write_etm4x_sysreg_offset(val, offset, _64bit) \
503 do { \
504 if (__builtin_constant_p((offset))) \
505 write_etm4x_sysreg_const_offset((val), \
506 (offset)); \
507 else \
508 etm4x_sysreg_write((val), (offset), true, \
509 (_64bit)); \
510 } while (0)
511
512
513#define etm4x_relaxed_read32(csa, offset) \
514 ((u32)((csa)->io_mem ? \
515 readl_relaxed((csa)->base + (offset)) : \
516 read_etm4x_sysreg_offset((offset), false)))
517
518#define etm4x_relaxed_read64(csa, offset) \
519 ((u64)((csa)->io_mem ? \
520 readq_relaxed((csa)->base + (offset)) : \
521 read_etm4x_sysreg_offset((offset), true)))
522
523#define etm4x_read32(csa, offset) \
524 ({ \
525 u32 __val = etm4x_relaxed_read32((csa), (offset)); \
526 __io_ar(__val); \
527 __val; \
528 })
529
530#define etm4x_read64(csa, offset) \
531 ({ \
532 u64 __val = etm4x_relaxed_read64((csa), (offset)); \
533 __io_ar(__val); \
534 __val; \
535 })
536
537#define etm4x_relaxed_write32(csa, val, offset) \
538 do { \
539 if ((csa)->io_mem) \
540 writel_relaxed((val), (csa)->base + (offset)); \
541 else \
542 write_etm4x_sysreg_offset((val), (offset), \
543 false); \
544 } while (0)
545
546#define etm4x_relaxed_write64(csa, val, offset) \
547 do { \
548 if ((csa)->io_mem) \
549 writeq_relaxed((val), (csa)->base + (offset)); \
550 else \
551 write_etm4x_sysreg_offset((val), (offset), \
552 true); \
553 } while (0)
554
555#define etm4x_write32(csa, val, offset) \
556 do { \
557 __io_bw(); \
558 etm4x_relaxed_write32((csa), (val), (offset)); \
559 } while (0)
560
561#define etm4x_write64(csa, val, offset) \
562 do { \
563 __io_bw(); \
564 etm4x_relaxed_write64((csa), (val), (offset)); \
565 } while (0)
566
567
568/* ETMv4 resources */
569#define ETM_MAX_NR_PE 8
570#define ETMv4_MAX_CNTR 4
571#define ETM_MAX_SEQ_STATES 4
572#define ETM_MAX_EXT_INP_SEL 4
573#define ETM_MAX_EXT_INP 256
574#define ETM_MAX_EXT_OUT 4
575#define ETM_MAX_SINGLE_ADDR_CMP 16
576#define ETM_MAX_ADDR_RANGE_CMP (ETM_MAX_SINGLE_ADDR_CMP / 2)
577#define ETM_MAX_DATA_VAL_CMP 8
578#define ETMv4_MAX_CTXID_CMP 8
579#define ETM_MAX_VMID_CMP 8
580#define ETM_MAX_PE_CMP 8
581#define ETM_MAX_RES_SEL 32
582#define ETM_MAX_SS_CMP 8
583
584#define ETMv4_SYNC_MASK 0x1F
585#define ETM_CYC_THRESHOLD_MASK 0xFFF
586#define ETM_CYC_THRESHOLD_DEFAULT 0x100
587#define ETMv4_EVENT_MASK 0xFF
588#define ETM_CNTR_MAX_VAL 0xFFFF
589#define ETM_TRACEID_MASK 0x3f
590
591/* ETMv4 programming modes */
592#define ETM_MODE_EXCLUDE BIT(0)
593#define ETM_MODE_LOAD BIT(1)
594#define ETM_MODE_STORE BIT(2)
595#define ETM_MODE_LOAD_STORE BIT(3)
596#define ETM_MODE_BB BIT(4)
597#define ETMv4_MODE_CYCACC BIT(5)
598#define ETMv4_MODE_CTXID BIT(6)
599#define ETM_MODE_VMID BIT(7)
600#define ETM_MODE_COND(val) BMVAL(val, 8, 10)
601#define ETMv4_MODE_TIMESTAMP BIT(11)
602#define ETM_MODE_RETURNSTACK BIT(12)
603#define ETM_MODE_QELEM(val) BMVAL(val, 13, 14)
604#define ETM_MODE_DATA_TRACE_ADDR BIT(15)
605#define ETM_MODE_DATA_TRACE_VAL BIT(16)
606#define ETM_MODE_ISTALL BIT(17)
607#define ETM_MODE_DSTALL BIT(18)
608#define ETM_MODE_ATB_TRIGGER BIT(19)
609#define ETM_MODE_LPOVERRIDE BIT(20)
610#define ETM_MODE_ISTALL_EN BIT(21)
611#define ETM_MODE_DSTALL_EN BIT(22)
612#define ETM_MODE_INSTPRIO BIT(23)
613#define ETM_MODE_NOOVERFLOW BIT(24)
614#define ETM_MODE_TRACE_RESET BIT(25)
615#define ETM_MODE_TRACE_ERR BIT(26)
616#define ETM_MODE_VIEWINST_STARTSTOP BIT(27)
617#define ETMv4_MODE_ALL (GENMASK(27, 0) | \
618 ETM_MODE_EXCL_KERN | \
619 ETM_MODE_EXCL_USER)
620
621/*
622 * TRCOSLSR.OSLM advertises the OS Lock model.
623 * OSLM[2:0] = TRCOSLSR[4:3,0]
624 *
625 * 0b000 - Trace OS Lock is not implemented.
626 * 0b010 - Trace OS Lock is implemented.
627 * 0b100 - Trace OS Lock is not implemented, unit is controlled by PE OS Lock.
628 */
629#define ETM_OSLOCK_NI 0b000
630#define ETM_OSLOCK_PRESENT 0b010
631#define ETM_OSLOCK_PE 0b100
632
633#define ETM_OSLSR_OSLM(oslsr) ((((oslsr) & GENMASK(4, 3)) >> 2) | (oslsr & 0x1))
634
635/*
636 * TRCDEVARCH Bit field definitions
637 * Bits[31:21] - ARCHITECT = Always Arm Ltd.
638 * * Bits[31:28] = 0x4
639 * * Bits[27:21] = 0b0111011
640 * Bit[20] - PRESENT, Indicates the presence of this register.
641 *
642 * Bit[19:16] - REVISION, Revision of the architecture.
643 *
644 * Bit[15:0] - ARCHID, Identifies this component as an ETM
645 * * Bits[15:12] - architecture version of ETM
646 * * = 4 for ETMv4
647 * * Bits[11:0] = 0xA13, architecture part number for ETM.
648 */
649#define ETM_DEVARCH_ARCHITECT_MASK GENMASK(31, 21)
650#define ETM_DEVARCH_ARCHITECT_ARM ((0x4 << 28) | (0b0111011 << 21))
651#define ETM_DEVARCH_PRESENT BIT(20)
652#define ETM_DEVARCH_REVISION_SHIFT 16
653#define ETM_DEVARCH_REVISION_MASK GENMASK(19, 16)
654#define ETM_DEVARCH_REVISION(x) \
655 (((x) & ETM_DEVARCH_REVISION_MASK) >> ETM_DEVARCH_REVISION_SHIFT)
656#define ETM_DEVARCH_ARCHID_MASK GENMASK(15, 0)
657#define ETM_DEVARCH_ARCHID_ARCH_VER_SHIFT 12
658#define ETM_DEVARCH_ARCHID_ARCH_VER_MASK GENMASK(15, 12)
659#define ETM_DEVARCH_ARCHID_ARCH_VER(x) \
660 (((x) & ETM_DEVARCH_ARCHID_ARCH_VER_MASK) >> ETM_DEVARCH_ARCHID_ARCH_VER_SHIFT)
661
662#define ETM_DEVARCH_MAKE_ARCHID_ARCH_VER(ver) \
663 (((ver) << ETM_DEVARCH_ARCHID_ARCH_VER_SHIFT) & ETM_DEVARCH_ARCHID_ARCH_VER_MASK)
664
665#define ETM_DEVARCH_ARCHID_ARCH_PART(x) ((x) & 0xfffUL)
666
667#define ETM_DEVARCH_MAKE_ARCHID(major) \
668 ((ETM_DEVARCH_MAKE_ARCHID_ARCH_VER(major)) | ETM_DEVARCH_ARCHID_ARCH_PART(0xA13))
669
670#define ETM_DEVARCH_ARCHID_ETMv4x ETM_DEVARCH_MAKE_ARCHID(0x4)
671#define ETM_DEVARCH_ARCHID_ETE ETM_DEVARCH_MAKE_ARCHID(0x5)
672
673#define ETM_DEVARCH_ID_MASK \
674 (ETM_DEVARCH_ARCHITECT_MASK | ETM_DEVARCH_ARCHID_MASK | ETM_DEVARCH_PRESENT)
675#define ETM_DEVARCH_ETMv4x_ARCH \
676 (ETM_DEVARCH_ARCHITECT_ARM | ETM_DEVARCH_ARCHID_ETMv4x | ETM_DEVARCH_PRESENT)
677#define ETM_DEVARCH_ETE_ARCH \
678 (ETM_DEVARCH_ARCHITECT_ARM | ETM_DEVARCH_ARCHID_ETE | ETM_DEVARCH_PRESENT)
679
680#define CS_DEVTYPE_PE_TRACE 0x00000013
681
682#define TRCSTATR_IDLE_BIT 0
683#define TRCSTATR_PMSTABLE_BIT 1
684#define ETM_DEFAULT_ADDR_COMP 0
685
686#define TRCSSCSRn_PC BIT(3)
687
688/* PowerDown Control Register bits */
689#define TRCPDCR_PU BIT(3)
690
691#define TRCACATR_EXLEVEL_SHIFT 8
692
693/*
694 * Exception level mask for Secure and Non-Secure ELs.
695 * ETM defines the bits for EL control (e.g, TRVICTLR, TRCACTRn).
696 * The Secure and Non-Secure ELs are always to gether.
697 * Non-secure EL3 is never implemented.
698 * We use the following generic mask as they appear in different
699 * registers and this can be shifted for the appropriate
700 * fields.
701 */
702#define ETM_EXLEVEL_S_APP BIT(0) /* Secure EL0 */
703#define ETM_EXLEVEL_S_OS BIT(1) /* Secure EL1 */
704#define ETM_EXLEVEL_S_HYP BIT(2) /* Secure EL2 */
705#define ETM_EXLEVEL_S_MON BIT(3) /* Secure EL3/Monitor */
706#define ETM_EXLEVEL_NS_APP BIT(4) /* NonSecure EL0 */
707#define ETM_EXLEVEL_NS_OS BIT(5) /* NonSecure EL1 */
708#define ETM_EXLEVEL_NS_HYP BIT(6) /* NonSecure EL2 */
709
710/* access level controls in TRCACATRn */
711#define TRCACATR_EXLEVEL_SHIFT 8
712
713#define ETM_TRCIDR1_ARCH_MAJOR_SHIFT 8
714#define ETM_TRCIDR1_ARCH_MAJOR_MASK (0xfU << ETM_TRCIDR1_ARCH_MAJOR_SHIFT)
715#define ETM_TRCIDR1_ARCH_MAJOR(x) \
716 (((x) & ETM_TRCIDR1_ARCH_MAJOR_MASK) >> ETM_TRCIDR1_ARCH_MAJOR_SHIFT)
717#define ETM_TRCIDR1_ARCH_MINOR_SHIFT 4
718#define ETM_TRCIDR1_ARCH_MINOR_MASK (0xfU << ETM_TRCIDR1_ARCH_MINOR_SHIFT)
719#define ETM_TRCIDR1_ARCH_MINOR(x) \
720 (((x) & ETM_TRCIDR1_ARCH_MINOR_MASK) >> ETM_TRCIDR1_ARCH_MINOR_SHIFT)
721#define ETM_TRCIDR1_ARCH_SHIFT ETM_TRCIDR1_ARCH_MINOR_SHIFT
722#define ETM_TRCIDR1_ARCH_MASK \
723 (ETM_TRCIDR1_ARCH_MAJOR_MASK | ETM_TRCIDR1_ARCH_MINOR_MASK)
724
725#define ETM_TRCIDR1_ARCH_ETMv4 0x4
726
727/*
728 * Driver representation of the ETM architecture.
729 * The version of an ETM component can be detected from
730 *
731 * TRCDEVARCH - CoreSight architected register
732 * - Bits[15:12] - Major version
733 * - Bits[19:16] - Minor version
734 *
735 * We must rely only on TRCDEVARCH for the version information. Even though,
736 * TRCIDR1 also provides the architecture version, it is a "Trace" register
737 * and as such must be accessed only with Trace power domain ON. This may
738 * not be available at probe time.
739 *
740 * Now to make certain decisions easier based on the version
741 * we use an internal representation of the version in the
742 * driver, as follows :
743 *
744 * ETM_ARCH_VERSION[7:0], where :
745 * Bits[7:4] - Major version
746 * Bits[3:0] - Minro version
747 */
748#define ETM_ARCH_VERSION(major, minor) \
749 ((((major) & 0xfU) << 4) | (((minor) & 0xfU)))
750#define ETM_ARCH_MAJOR_VERSION(arch) (((arch) >> 4) & 0xfU)
751#define ETM_ARCH_MINOR_VERSION(arch) ((arch) & 0xfU)
752
753#define ETM_ARCH_V4 ETM_ARCH_VERSION(4, 0)
754#define ETM_ARCH_ETE ETM_ARCH_VERSION(5, 0)
755
756/* Interpretation of resource numbers change at ETM v4.3 architecture */
757#define ETM_ARCH_V4_3 ETM_ARCH_VERSION(4, 3)
758
759static inline u8 etm_devarch_to_arch(u32 devarch)
760{
761 return ETM_ARCH_VERSION(ETM_DEVARCH_ARCHID_ARCH_VER(devarch),
762 ETM_DEVARCH_REVISION(devarch));
763}
764
765enum etm_impdef_type {
766 ETM4_IMPDEF_HISI_CORE_COMMIT,
767 ETM4_IMPDEF_FEATURE_MAX,
768};
769
770/**
771 * struct etmv4_config - configuration information related to an ETMv4
772 * @mode: Controls various modes supported by this ETM.
773 * @pe_sel: Controls which PE to trace.
774 * @cfg: Controls the tracing options.
775 * @eventctrl0: Controls the tracing of arbitrary events.
776 * @eventctrl1: Controls the behavior of the events that @event_ctrl0 selects.
777 * @stallctl: If functionality that prevents trace unit buffer overflows
778 * is available.
779 * @ts_ctrl: Controls the insertion of global timestamps in the
780 * trace streams.
781 * @syncfreq: Controls how often trace synchronization requests occur.
782 * the TRCCCCTLR register.
783 * @ccctlr: Sets the threshold value for cycle counting.
784 * @vinst_ctrl: Controls instruction trace filtering.
785 * @viiectlr: Set or read, the address range comparators.
786 * @vissctlr: Set, or read, the single address comparators that control the
787 * ViewInst start-stop logic.
788 * @vipcssctlr: Set, or read, which PE comparator inputs can control the
789 * ViewInst start-stop logic.
790 * @seq_idx: Sequencor index selector.
791 * @seq_ctrl: Control for the sequencer state transition control register.
792 * @seq_rst: Moves the sequencer to state 0 when a programmed event occurs.
793 * @seq_state: Set, or read the sequencer state.
794 * @cntr_idx: Counter index seletor.
795 * @cntrldvr: Sets or returns the reload count value for a counter.
796 * @cntr_ctrl: Controls the operation of a counter.
797 * @cntr_val: Sets or returns the value for a counter.
798 * @res_idx: Resource index selector.
799 * @res_ctrl: Controls the selection of the resources in the trace unit.
800 * @ss_idx: Single-shot index selector.
801 * @ss_ctrl: Controls the corresponding single-shot comparator resource.
802 * @ss_status: The status of the corresponding single-shot comparator.
803 * @ss_pe_cmp: Selects the PE comparator inputs for Single-shot control.
804 * @addr_idx: Address comparator index selector.
805 * @addr_val: Value for address comparator.
806 * @addr_acc: Address comparator access type.
807 * @addr_type: Current status of the comparator register.
808 * @ctxid_idx: Context ID index selector.
809 * @ctxid_pid: Value of the context ID comparator.
810 * @ctxid_mask0:Context ID comparator mask for comparator 0-3.
811 * @ctxid_mask1:Context ID comparator mask for comparator 4-7.
812 * @vmid_idx: VM ID index selector.
813 * @vmid_val: Value of the VM ID comparator.
814 * @vmid_mask0: VM ID comparator mask for comparator 0-3.
815 * @vmid_mask1: VM ID comparator mask for comparator 4-7.
816 * @ext_inp: External input selection.
817 * @s_ex_level: Secure ELs where tracing is supported.
818 */
819struct etmv4_config {
820 u32 mode;
821 u32 pe_sel;
822 u32 cfg;
823 u32 eventctrl0;
824 u32 eventctrl1;
825 u32 stall_ctrl;
826 u32 ts_ctrl;
827 u32 syncfreq;
828 u32 ccctlr;
829 u32 bb_ctrl;
830 u32 vinst_ctrl;
831 u32 viiectlr;
832 u32 vissctlr;
833 u32 vipcssctlr;
834 u8 seq_idx;
835 u32 seq_ctrl[ETM_MAX_SEQ_STATES];
836 u32 seq_rst;
837 u32 seq_state;
838 u8 cntr_idx;
839 u32 cntrldvr[ETMv4_MAX_CNTR];
840 u32 cntr_ctrl[ETMv4_MAX_CNTR];
841 u32 cntr_val[ETMv4_MAX_CNTR];
842 u8 res_idx;
843 u32 res_ctrl[ETM_MAX_RES_SEL];
844 u8 ss_idx;
845 u32 ss_ctrl[ETM_MAX_SS_CMP];
846 u32 ss_status[ETM_MAX_SS_CMP];
847 u32 ss_pe_cmp[ETM_MAX_SS_CMP];
848 u8 addr_idx;
849 u64 addr_val[ETM_MAX_SINGLE_ADDR_CMP];
850 u64 addr_acc[ETM_MAX_SINGLE_ADDR_CMP];
851 u8 addr_type[ETM_MAX_SINGLE_ADDR_CMP];
852 u8 ctxid_idx;
853 u64 ctxid_pid[ETMv4_MAX_CTXID_CMP];
854 u32 ctxid_mask0;
855 u32 ctxid_mask1;
856 u8 vmid_idx;
857 u64 vmid_val[ETM_MAX_VMID_CMP];
858 u32 vmid_mask0;
859 u32 vmid_mask1;
860 u32 ext_inp;
861 u8 s_ex_level;
862};
863
864/**
865 * struct etm4_save_state - state to be preserved when ETM is without power
866 */
867struct etmv4_save_state {
868 u32 trcprgctlr;
869 u32 trcprocselr;
870 u32 trcconfigr;
871 u32 trcauxctlr;
872 u32 trceventctl0r;
873 u32 trceventctl1r;
874 u32 trcstallctlr;
875 u32 trctsctlr;
876 u32 trcsyncpr;
877 u32 trcccctlr;
878 u32 trcbbctlr;
879 u32 trctraceidr;
880 u32 trcqctlr;
881
882 u32 trcvictlr;
883 u32 trcviiectlr;
884 u32 trcvissctlr;
885 u32 trcvipcssctlr;
886
887 u32 trcseqevr[ETM_MAX_SEQ_STATES];
888 u32 trcseqrstevr;
889 u32 trcseqstr;
890 u32 trcextinselr;
891 u32 trccntrldvr[ETMv4_MAX_CNTR];
892 u32 trccntctlr[ETMv4_MAX_CNTR];
893 u32 trccntvr[ETMv4_MAX_CNTR];
894
895 u32 trcrsctlr[ETM_MAX_RES_SEL];
896
897 u32 trcssccr[ETM_MAX_SS_CMP];
898 u32 trcsscsr[ETM_MAX_SS_CMP];
899 u32 trcsspcicr[ETM_MAX_SS_CMP];
900
901 u64 trcacvr[ETM_MAX_SINGLE_ADDR_CMP];
902 u64 trcacatr[ETM_MAX_SINGLE_ADDR_CMP];
903 u64 trccidcvr[ETMv4_MAX_CTXID_CMP];
904 u64 trcvmidcvr[ETM_MAX_VMID_CMP];
905 u32 trccidcctlr0;
906 u32 trccidcctlr1;
907 u32 trcvmidcctlr0;
908 u32 trcvmidcctlr1;
909
910 u32 trcclaimset;
911
912 u32 cntr_val[ETMv4_MAX_CNTR];
913 u32 seq_state;
914 u32 vinst_ctrl;
915 u32 ss_status[ETM_MAX_SS_CMP];
916
917 u32 trcpdcr;
918};
919
920/**
921 * struct etm4_drvdata - specifics associated to an ETM component
922 * @pclk APB clock if present, otherwise NULL
923 * @base: Memory mapped base address for this component.
924 * @csdev: Component vitals needed by the framework.
925 * @spinlock: Only one at a time pls.
926 * @mode: This tracer's mode, i.e sysFS, Perf or disabled.
927 * @cpu: The cpu this component is affined to.
928 * @arch: ETM architecture version.
929 * @nr_pe: The number of processing entity available for tracing.
930 * @nr_pe_cmp: The number of processing entity comparator inputs that are
931 * available for tracing.
932 * @nr_addr_cmp:Number of pairs of address comparators available
933 * as found in ETMIDR4 0-3.
934 * @nr_cntr: Number of counters as found in ETMIDR5 bit 28-30.
935 * @nr_ext_inp: Number of external input.
936 * @numcidc: Number of contextID comparators.
937 * @numvmidc: Number of VMID comparators.
938 * @nrseqstate: The number of sequencer states that are implemented.
939 * @nr_event: Indicates how many events the trace unit support.
940 * @nr_resource:The number of resource selection pairs available for tracing.
941 * @nr_ss_cmp: Number of single-shot comparator controls that are available.
942 * @trcid: value of the current ID for this component.
943 * @trcid_size: Indicates the trace ID width.
944 * @ts_size: Global timestamp size field.
945 * @ctxid_size: Size of the context ID field to consider.
946 * @vmid_size: Size of the VM ID comparator to consider.
947 * @ccsize: Indicates the size of the cycle counter in bits.
948 * @ccitmin: minimum value that can be programmed in
949 * @s_ex_level: In secure state, indicates whether instruction tracing is
950 * supported for the corresponding Exception level.
951 * @ns_ex_level:In non-secure state, indicates whether instruction tracing is
952 * supported for the corresponding Exception level.
953 * @sticky_enable: true if ETM base configuration has been done.
954 * @boot_enable:True if we should start tracing at boot time.
955 * @os_unlock: True if access to management registers is allowed.
956 * @instrp0: Tracing of load and store instructions
957 * as P0 elements is supported.
958 * @q_filt: Q element filtering support, if Q elements are supported.
959 * @trcbb: Indicates if the trace unit supports branch broadcast tracing.
960 * @trccond: If the trace unit supports conditional
961 * instruction tracing.
962 * @retstack: Indicates if the implementation supports a return stack.
963 * @trccci: Indicates if the trace unit supports cycle counting
964 * for instruction.
965 * @q_support: Q element support characteristics.
966 * @trc_error: Whether a trace unit can trace a system
967 * error exception.
968 * @syncpr: Indicates if an implementation has a fixed
969 * synchronization period.
970 * @stall_ctrl: Enables trace unit functionality that prevents trace
971 * unit buffer overflows.
972 * @sysstall: Does the system support stall control of the PE?
973 * @nooverflow: Indicate if overflow prevention is supported.
974 * @atbtrig: If the implementation can support ATB triggers
975 * @lpoverride: If the implementation can support low-power state over.
976 * @trfcr: If the CPU supports FEAT_TRF, value of the TRFCR_ELx that
977 * allows tracing at all ELs. We don't want to compute this
978 * at runtime, due to the additional setting of TRFCR_CX when
979 * in EL2. Otherwise, 0.
980 * @config: structure holding configuration parameters.
981 * @save_trfcr: Saved TRFCR_EL1 register during a CPU PM event.
982 * @save_state: State to be preserved across power loss
983 * @state_needs_restore: True when there is context to restore after PM exit
984 * @skip_power_up: Indicates if an implementation can skip powering up
985 * the trace unit.
986 * @arch_features: Bitmap of arch features of etmv4 devices.
987 */
988struct etmv4_drvdata {
989 struct clk *pclk;
990 void __iomem *base;
991 struct coresight_device *csdev;
992 spinlock_t spinlock;
993 int cpu;
994 u8 arch;
995 u8 nr_pe;
996 u8 nr_pe_cmp;
997 u8 nr_addr_cmp;
998 u8 nr_cntr;
999 u8 nr_ext_inp;
1000 u8 numcidc;
1001 u8 numvmidc;
1002 u8 nrseqstate;
1003 u8 nr_event;
1004 u8 nr_resource;
1005 u8 nr_ss_cmp;
1006 u8 trcid;
1007 u8 trcid_size;
1008 u8 ts_size;
1009 u8 ctxid_size;
1010 u8 vmid_size;
1011 u8 ccsize;
1012 u16 ccitmin;
1013 u8 s_ex_level;
1014 u8 ns_ex_level;
1015 u8 q_support;
1016 u8 os_lock_model;
1017 bool sticky_enable;
1018 bool boot_enable;
1019 bool os_unlock;
1020 bool instrp0;
1021 bool q_filt;
1022 bool trcbb;
1023 bool trccond;
1024 bool retstack;
1025 bool trccci;
1026 bool trc_error;
1027 bool syncpr;
1028 bool stallctl;
1029 bool sysstall;
1030 bool nooverflow;
1031 bool atbtrig;
1032 bool lpoverride;
1033 u64 trfcr;
1034 struct etmv4_config config;
1035 u64 save_trfcr;
1036 struct etmv4_save_state *save_state;
1037 bool state_needs_restore;
1038 bool skip_power_up;
1039 DECLARE_BITMAP(arch_features, ETM4_IMPDEF_FEATURE_MAX);
1040};
1041
1042/* Address comparator access types */
1043enum etm_addr_acctype {
1044 TRCACATRn_TYPE_ADDR,
1045 TRCACATRn_TYPE_DATA_LOAD_ADDR,
1046 TRCACATRn_TYPE_DATA_STORE_ADDR,
1047 TRCACATRn_TYPE_DATA_LOAD_STORE_ADDR,
1048};
1049
1050/* Address comparator context types */
1051enum etm_addr_ctxtype {
1052 ETM_CTX_NONE,
1053 ETM_CTX_CTXID,
1054 ETM_CTX_VMID,
1055 ETM_CTX_CTXID_VMID,
1056};
1057
1058extern const struct attribute_group *coresight_etmv4_groups[];
1059void etm4_config_trace_mode(struct etmv4_config *config);
1060
1061u64 etm4x_sysreg_read(u32 offset, bool _relaxed, bool _64bit);
1062void etm4x_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit);
1063
1064static inline bool etm4x_is_ete(struct etmv4_drvdata *drvdata)
1065{
1066 return drvdata->arch >= ETM_ARCH_ETE;
1067}
1068
1069int etm4_read_alloc_trace_id(struct etmv4_drvdata *drvdata);
1070void etm4_release_trace_id(struct etmv4_drvdata *drvdata);
1071#endif